nuvoTon
M031AE_v1
2024.05.06
M031AE_v1 SVD file
8
32
ACMP01
ACMP Register Map
ACMP
0x0
0x0
0x18
registers
n
ACMP_CALCTL
ACMP_CALCTL
Analog Comparator Calibration Control Register
0x10
-1
read-write
n
0x0
0x0
CALRVS0
OPA0 Calibration Reference Voltage Selection \nNote: CALRVS0 and CALRVS1 must be the same setting in calibration
16
1
read-write
0
VREF is
#0
1
VREF from high vcm to low vcm
#1
CALRVS1
OPA1 Calibration Reference Voltage Selection \nNote: CALRVS0 and CALRVS1 must be the same setting in calibration
17
1
read-write
0
VREF is
#0
1
VREF from high vcm to low vcm
#1
CALTRG0
OP Amplifier 0 Calibration Trigger Bit\nNote 1: Before this bit is enabled,ACMPEN(ACMP_CTL0) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.\nNote 2: Hardware will auto clear this bit when next calibration is triggered by software\nNote 3: If user must trigger calibration twice or more times, the second trigger have to wait at least 300us after the previous calibration done
0
1
read-write
0
Calibration is stopped
#0
1
Calibration is triggered
#1
CALTRG1
OP Amplifier 1 Calibration Trigger Bit\nNote 1: Before this bit is enabled, ACMPEN(ACMP_CTL1) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.\nNote 2: Hardware will auto clear this bit when next calibration is triggered by software.\nNote 3: If user must trigger calibration twice or more times, the second trigger have to wait at least 300us after the previous calibration done
1
1
read-write
0
Calibration is stopped
#0
1
Calibration is triggered
#1
ACMP_CALSR
ACMP_CALSR
Analog Comparator Calibration Status Register
0x14
read-only
n
0x0
0x0
CALNS0
Comparator0 Calibration Result Status for NMOS
1
1
read-only
0
Pass
#0
1
Fail
#1
CALNS1
Comparator1 Calibration Result Status for NMOS
5
1
read-only
0
Pass
#0
1
Fail
#1
CALPS0
Comparator0 Calibration Result Status for PMOS
2
1
read-only
0
Pass
#0
1
Fail
#1
CALPS1
Comparator1 Calibration Result Status for PMOS
6
1
read-only
0
Pass
#0
1
Fail
#1
DONE0
Comparator0 Calibration Done Status
0
1
read-only
0
Calibrating
#0
1
Calibration Done
#1
DONE1
Comparator1 Calibration Done Status
4
1
read-only
0
Calibrating
#0
1
Calibration Done
#1
ACMP_CTL0
ACMP_CTL0
Analog Comparator 0 Control Register
0x0
read-write
n
0x0
0x0
ACMPEN
Comparator Enable Bit
0
1
read-write
0
Comparator 0 Disabled
#0
1
Comparator 0 Enabled
#1
ACMPIE
Comparator Interrupt Enable Bit
1
1
read-write
0
Comparator 0 interrupt Disabled
#0
1
Comparator 0 interrupt Enabled. If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well
#1
ACMPOINV
Comparator Output Inverse
3
1
read-write
0
Comparator 0 output inverse Disabled
#0
1
Comparator 0 output inverse Enabled
#1
FILTSEL
Comparator Output Filter Count Selection
13
3
read-write
0
Filter function is Disabled
#000
1
ACMP0 output is sampled 1 consecutive PCLK
#001
2
ACMP0 output is sampled 2 consecutive PCLKs
#010
3
ACMP0 output is sampled 4 consecutive PCLKs
#011
4
ACMP0 output is sampled 8 consecutive PCLKs
#100
5
ACMP0 output is sampled 16 consecutive PCLKs
#101
6
ACMP0 output is sampled 32 consecutive PCLKs
#110
7
ACMP0 output is sampled 64 consecutive PCLKs
#111
INTPOL
Interrupt Condition Polarity Selection\nACMPIF0 will be set to 1 when comparator output edge condition is detected.
8
2
read-write
0
Rising edge or falling edge
#00
1
Rising edge
#01
2
Falling edge
#10
3
Reserved.
#11
NEGSEL
Comparator Negative Input Selection
4
2
read-write
0
ACMP0_N pin
#00
1
Internal comparator reference voltage (CRV)
#01
2
Band-gap voltage
#10
3
Reserved.
#11
OUTSEL
Comparator Output Select
12
1
read-write
0
Comparator 0 output to ACMP0_O pin is unfiltered comparator output
#0
1
Comparator 0 output to ACMP0_O pin is from filter output
#1
POSSEL
Comparator Positive Input Selection
6
2
read-write
0
Input from ACMP0_P0
#00
1
Input from ACMP0_P1
#01
2
Input from ACMP0_P2
#10
3
Input from ACMP0_P3
#11
WCMPSEL
Window Compare Mode Selection
18
1
read-write
0
Window Compare Mode Disabled
#0
1
Window Compare Mode Selected
#1
WKEN
Power-down Wake-up Enable Bit
16
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
WLATEN
Window Latch Mode Enable Bit
17
1
read-write
0
Window Latch Mode Disabled
#0
1
Window Latch Mode Enabled
#1
ACMP_CTL1
ACMP_CTL1
Analog Comparator 1 Control Register
0x4
read-write
n
0x0
0x0
ACMPEN
Comparator Enable Bit
0
1
read-write
0
Comparator 1 Disabled
#0
1
Comparator 1 Enabled
#1
ACMPIE
Comparator Interrupt Enable Bit
1
1
read-write
0
Comparator 1 interrupt Disabled
#0
1
Comparator 1 interrupt Enabled. If WKEN (ACMP_CTL1[16]) is set to 1, the wake-up interrupt function will be enabled as well
#1
ACMPOINV
Comparator Output Inverse Control
3
1
read-write
0
Comparator 1 output inverse Disabled
#0
1
Comparator 1 output inverse Enabled
#1
FILTSEL
Comparator Output Filter Count Selection
13
3
read-write
0
Filter function is Disabled
#000
1
ACMP1 output is sampled 1 consecutive PCLK
#001
2
ACMP1 output is sampled 2 consecutive PCLKs
#010
3
ACMP1 output is sampled 4 consecutive PCLKs
#011
4
ACMP1 output is sampled 8 consecutive PCLKs
#100
5
ACMP1 output is sampled 16 consecutive PCLKs
#101
6
ACMP1 output is sampled 32 consecutive PCLKs
#110
7
ACMP1 output is sampled 64 consecutive PCLKs
#111
INTPOL
Interrupt Condition Polarity Selection\nACMPIF1 will be set to 1 when comparator output edge condition is detected.
8
2
read-write
0
Rising edge or falling edge
#00
1
Rising edge
#01
2
Falling edge
#10
3
Reserved.
#11
NEGSEL
Comparator Negative Input Selection
4
2
read-write
0
ACMP1_N pin
#00
1
Internal comparator reference voltage (CRV)
#01
2
Band-gap voltage
#10
3
Reserved.
#11
OUTSEL
Comparator Output Select
12
1
read-write
0
Comparator 1 output to ACMP1_O pin is unfiltered comparator output
#0
1
Comparator 1 output to ACMP1_O pin is from filter output
#1
POSSEL
Comparator Positive Input Selection
6
2
read-write
0
Input from ACMP1_P0
#00
1
Input from ACMP1_P1
#01
2
Input from ACMP1_P2
#10
3
Input from ACMP1_P3
#11
WCMPSEL
Window Compare Mode Selection
18
1
read-write
0
Window Compare Mode Disabled
#0
1
Window Compare Mode Selected
#1
WKEN
Power-down Wakeup Enable Bit
16
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
WLATEN
Window Latch Mode Enable Bit
17
1
read-write
0
Window Latch Mode Disabled
#0
1
Window Latch Mode Enabled
#1
ACMP_STATUS
ACMP_STATUS
Analog Comparator Status Register
0x8
read-write
n
0x0
0x0
ACMPIF0
Comparator 0 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.\nNote: Write 1 to clear this bit to 0.
0
1
read-write
ACMPIF1
Comparator 1 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output. This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.\nNote: Write 1 to clear this bit to 0.
1
1
read-write
ACMPO0
Comparator 0 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
4
1
read-write
ACMPO1
Comparator 1 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
5
1
read-write
ACMPS0
Comparator 0 Status \nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
12
1
read-write
ACMPS1
Comparator 1 Status\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
13
1
read-write
ACMPWO
Comparator Window Output\nThis bit shows the output status of window compare mode
16
1
read-write
0
The positive input voltage is outside the window
#0
1
The positive input voltage is in the window
#1
WKIF0
Comparator 0 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP0 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0.
8
1
read-write
0
No power-down wake-up occurred
#0
1
Power-down wake-up occurred
#1
WKIF1
Comparator 1 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP1 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0.
9
1
read-write
0
No power-down wake-up occurred
#0
1
Power-down wake-up occurred
#1
ACMP_VREF
ACMP_VREF
Analog Comparator Reference Voltage Control Register
0xC
read-write
n
0x0
0x0
CRVCTL
Comparator Reference Voltage Setting
0
4
read-write
CRVSSEL
CRV Source Voltage Selection
6
1
read-write
0
AVDD is selected as CRV source voltage
#0
1
VREF is selected as as CRV source voltage
#1
ADC
ADC Register Map
ADC
0x0
0x0
0x40
registers
n
0x100
0x4
registers
n
0x180
0x8
registers
n
0x74
0x4
registers
n
0x80
0x1C
registers
n
0xA0
0x8
registers
n
ADCALR
ADC_ADCALR
ADC Calibration Mode Register
0x180
-1
read-write
n
0x0
0x0
CALEN
Calibration Function Enable Bit\nNote: If chip is powered off, calibration function should be executed again.
0
1
read-write
0
Calibration function Disabled
#0
CALIE
Calibration Interrupt Enable Bit\nIf calibration function is enabled and the calibration finish, CALIF bit will be asserted, in the meanwhile, if CALIE bit is set to 1, a calibration interrupt request is generated.
1
1
read-write
0
Calibration function Interrupt Disabled
#0
1
Calibration function Interrupt Enabled
#1
ADCALSTSR
ADC_ADCALSTSR
ADC Calibration Status Register
0x184
read-write
n
0x0
0x0
CALIF
Calibration Finish Interrupt Flag\nIf calibration is finished, this flag will be set to 1. It is cleared by writing 1 to it.
0
1
read-write
ADCHER
ADC_ADCHER
ADC Channel Enable Register
0x84
read-write
n
0x0
0x0
CHEN
Analog Input Channel Enable Control\nSet ADCHER[15:0] bits to enable the corresponding analog input channel 15 ~ 0. If DIFFEN bit is set to 1, only the even number channel needs to be enabled.\nBesides, setting the ADCHER[29] bit will enable internal channel for band-gap voltage. Other bits are reserved.\nNote: If the internal channel for band-gap voltage (CHEN[29]) is active, the maximum sampling rate will be 300k SPS.
0
32
read-write
0
Channel Disabled
0
1
Channel Enabled
1
ADCMPR0
ADC_ADCMPR0
ADC Compare Register 0
0x88
read-write
n
0x0
0x0
CMPCH
Compare Channel Selection
3
5
read-write
0
Channel 0 conversion result is selected to be compared
#00000
1
Channel 1 conversion result is selected to be compared
#00001
2
Channel 2 conversion result is selected to be compared
#00010
3
Channel 3 conversion result is selected to be compared
#00011
4
Channel 4 conversion result is selected to be compared
#00100
5
Channel 5 conversion result is selected to be compared
#00101
6
Channel 6 conversion result is selected to be compared
#00110
7
Channel 7 conversion result is selected to be compared
#00111
8
Channel 8 conversion result is selected to be compared
#01000
9
Channel 9 conversion result is selected to be compared
#01001
10
Channel 10 conversion result is selected to be compared
#01010
11
Channel 11 conversion result is selected to be compared
#01011
12
Channel 12 conversion result is selected to be compared
#01100
13
Channel 13 conversion result is selected to be compared
#01101
14
Channel 14 conversion result is selected to be compared
#01110
15
Channel 15 conversion result is selected to be compared
#01111
28
Floating detect channel conversion result is selected to be compared
#11100
29
Band-gap voltage conversion result is selected to be compared
#11101
CMPCOND
Compare Condition\nNote: When the internal counter reaches to (CMPMATCNT +1), the CMPFx bit will be set.
2
1
read-write
0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD bits, the internal match counter will increase one
#0
1
Set the compare condition as that when a 12-bit A/D conversion result is greater than or equal to the 12-bit CMPD bits, the internal match counter will increase one
#1
CMPD
Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD bits should be filled in unsigned format (straight binary format).
16
12
read-write
CMPEN
Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register.
0
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
CMPIE
Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE bit is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Compare function interrupt Disabled
#0
1
Compare function interrupt Enabled
#1
CMPMATCNT
Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit, the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
8
4
read-write
CMPWEN
Compare Window Mode Enable Bit\nNote: This bit is only presented in ADCMPR0 register.
15
1
read-write
0
Compare Window Mode Disabled
#0
1
Compare Window Mode Enabled
#1
ADCMPR1
ADC_ADCMPR1
ADC Compare Register 1
0x8C
read-write
n
0x0
0x0
ADCR
ADC_ADCR
ADC Control Register
0x80
read-write
n
0x0
0x0
ADEN
A/D Converter Enable Bit\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
0
1
read-write
0
A/D converter Disabled
#0
1
A/D converter Enabled
#1
ADIE
A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.
1
1
read-write
0
A/D interrupt function Disabled
#0
1
A/D interrupt function Enabled
#1
ADMD
A/D Converter Operation Mode Control\nNote 1: When changing the operation mode, software should clear ADST bit first.\nNote 2: In Burst mode, the A/D result data is always at ADC Data Register 0.
2
2
read-write
0
Single conversion
#00
1
Burst conversion
#01
2
Single-cycle Scan
#10
3
Continuous Scan
#11
ADST
A/D Conversion Start or Calibration Start\nADST bit can be set to 1 from four sources: software, external pin STADC, PWM trigger and Timer trigger. ADST bit will be cleared to 0 by hardware automatically at the ends of Single mode, Single-cycle Scan mode and Calibration mode. In Continuous Scan mode and Burst mode, A/D conversion is continuously performed until software writes 0 to this bit or chip is reset.
11
1
read-write
0
Conversion stops and A/D converter enters idle state
#0
1
Conversion starts or Calibration Start
#1
DIFFEN
Differential Input Mode Control\nNote: In Differential Input mode, only the even number of the two corresponding channels needs to be enabled in ADCHER register. The conversion result will be placed to the corresponding data register of the enabled channel.
10
1
read-write
0
Single-end analog input mode
#0
1
Differential analog input mode
#1
DMOF
Differential Input Mode Output Format\nIf user enables differential input mode, the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format).
31
1
read-write
0
A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format (straight binary format)
#0
1
A/D Conversion result will be filled in RSLT at ADDRx registers with 2's complement format
#1
PTEN
PDMA Transfer Enable Bit\nWhen A/D conversion is completed, the converted data is loaded into ADDR0~15, ADDR29. Software can enable this bit to generate a PDMA data transfer request.
9
1
read-write
0
PDMA data transfer Disabled
#0
1
PDMA data transfer in ADDR0~15, ADDR29 Enabled
#1
RESET
ADC RESET (Write Protect)\nIf user writes this bit, the ADC analog macro will reset. Calibration data in macro will be deleted, but registers in ADC controller will keep.\nNote: This bit is cleared by hardware.
12
1
read-write
TRGCOND
External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger.
6
2
read-write
0
Low level
#00
1
High level
#01
2
Falling edge
#10
3
Rising edge
#11
TRGEN
External Trigger Enable Bit\nEnable or disable triggering of A/D conversion by external STADC pin, PWM trigger, BPWM trigger and Timer trigger. If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source.\nNote: The ADC external trigger function is only supported in Single-cycle Scan mode.
8
1
read-write
0
External trigger Disabled
#0
1
External trigger Enabled
#1
TRGS
Hardware Trigger Source\nNote: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits.
4
2
read-write
0
A/D conversion is started by external STADC pin
#00
1
Timer0 ~ Timer3 overflow pulse trigger
#01
2
A/D conversion is started by BPWM trigger
#10
3
A/D conversion is started by PWM trigger
#11
ADDR0
ADC_ADDR0
ADC Data Register 0
0x0
read-only
n
0x0
0x0
OVERRUN
Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register, OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read.
16
1
read-only
0
Data in RSLT bits is not overwritten
#0
1
Data in RSLT bits is overwritten
#1
RSLT
A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC.
0
16
read-only
VALID
Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read.
17
1
read-only
0
Data in RSLT bits is not valid
#0
1
Data in RSLT bits is valid
#1
ADDR1
ADC_ADDR1
ADC Data Register 1
0x4
read-write
n
0x0
0x0
ADDR10
ADC_ADDR10
ADC Data Register 10
0x28
read-write
n
0x0
0x0
ADDR11
ADC_ADDR11
ADC Data Register 11
0x2C
read-write
n
0x0
0x0
ADDR12
ADC_ADDR12
ADC Data Register 12
0x30
read-write
n
0x0
0x0
ADDR13
ADC_ADDR13
ADC Data Register 13
0x34
read-write
n
0x0
0x0
ADDR14
ADC_ADDR14
ADC Data Register 14
0x38
read-write
n
0x0
0x0
ADDR15
ADC_ADDR15
ADC Data Register 15
0x3C
read-write
n
0x0
0x0
ADDR2
ADC_ADDR2
ADC Data Register 2
0x8
read-write
n
0x0
0x0
ADDR29
ADC_ADDR29
ADC Data Register 29
0x74
read-write
n
0x0
0x0
ADDR3
ADC_ADDR3
ADC Data Register 3
0xC
read-write
n
0x0
0x0
ADDR4
ADC_ADDR4
ADC Data Register 4
0x10
read-write
n
0x0
0x0
ADDR5
ADC_ADDR5
ADC Data Register 5
0x14
read-write
n
0x0
0x0
ADDR6
ADC_ADDR6
ADC Data Register 6
0x18
read-write
n
0x0
0x0
ADDR7
ADC_ADDR7
ADC Data Register 7
0x1C
read-write
n
0x0
0x0
ADDR8
ADC_ADDR8
ADC Data Register 8
0x20
read-write
n
0x0
0x0
ADDR9
ADC_ADDR9
ADC Data Register 9
0x24
read-write
n
0x0
0x0
ADPDMA
ADC_ADPDMA
ADC PDMA Current Transfer Data Register
0x100
read-only
n
0x0
0x0
CURDAT
ADC PDMA Current Transfer Data Register (Read Only)\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.\nCurrent PDMA transfer data could be the content of ADDR0 ~ ADDR15, and ADDR29 registers.
0
18
read-only
ADSR0
ADC_ADSR0
ADC Status Register0
0x90
read-write
n
0x0
0x0
ADF
A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit.\nThe ADF bit is set to 1 at the following three conditions:\nWhen A/D conversion ends in Single mode.\nWhen A/D conversion ends on all specified channels in Single-cycle Scan mode and Continuous Scan mode.\nWhen more than or equal to 4 samples in FIFO in Burst mode.
0
1
read-write
BUSY
BUSY/IDLE (Read Only)\nThis bit is a mirror of ADST bit in ADCR register.
7
1
read-only
0
A/D converter is in idle state
#0
1
A/D converter is busy at conversion
#1
CHANNEL
Current Conversion Channel (Read Only)
27
5
read-only
CMPF0
Compare Flag 0\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1. This bit is cleared by writing 1 to it.
1
1
read-write
0
Conversion result in ADDR does not meet ADCMPR0 setting
#0
1
Conversion result in ADDR meets ADCMPR0 setting
#1
CMPF1
Compare Flag 1
When the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register, this bit is set to 1 it is cleared by writing 1 to it
2
1
read-write
0
Conversion result in ADDR does not meet ADCMPR1 setting
#0
1
Conversion result in ADDR meets ADCMPR1 setting
#1
OVERRUNF
Overrun Flag (Read Only)\nIf any one of OVERRUN (ADDRx[16]) is set, this flag will be set to 1.\nNote: When ADC is in burst mode and the FIFO is overrun, this flag will be set to 1.
16
1
read-only
VALIDF
Data Valid Flag (Read Only)\nIf any one of VALID (ADDRx[17]) is set, this flag will be set to 1.\nNote: When ADC is in burst mode and any conversion result is valid, this flag will be set to 1.
8
1
read-only
ADSR1
ADC_ADSR1
ADC Status Register1
0x94
read-only
n
0x0
0x0
VALID
Data Valid Flag (Read Only)\nVALID[29, 15:0] are the mirror of the VALID bits in ADDR29[17], ADDR15[17]~ ADDR0[17]. The other bits are reserved.\nNote: When ADC is in burst mode and any conversion result is valid, VALID[29, 15:0] will be set to 1.
0
32
read-only
ADSR2
ADC_ADSR2
ADC Status Register2
0x98
read-only
n
0x0
0x0
OVERRUN
Overrun Flag (Read Only)\nOVERRUN[29, 15:0] are the mirror of the OVERRUN bit in ADDR29[16], ADDR15[16] ~ ADDR0[16]. The other bits are reserved. \nNote: When ADC is in burst mode and the FIFO is overrun, OVERRUN[29, 15:0] will be set to 1.
0
32
read-only
CFDCTL
ADC_CFDCTL
ADC Channel Floating Detect Control Register
0xA4
read-write
n
0x0
0x0
DISCHEN
Discharge Enable\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enable.
1
1
read-write
0
Channel discharge Disabled
#0
1
Channel discharge Enabled
#1
FDETCHEN
Floating Detect Channel Enable Bit
Note: if FDETCHEN is enabled, internal channel is always turn on.
8
1
read-write
0
Floating Detect Channel Disabled
#0
1
Floating Detect Channel Enabled
#1
PRECHEN
Precharge Enable\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enable.
0
1
read-write
0
Channel precharge Disabled
#0
1
Channel precharge Enabled
#1
ESMPCTL
ADC_ESMPCTL
ADC Extend Sample Time Control Register
0xA0
read-write
n
0x0
0x0
EXTSMPT
ADC Sampling Time Extend \nWhen ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time.\nThe range of start delay time is from 0~255 ADC clock.
0
8
read-write
BPWM0
BPWM Register Map
BPWM
0x0
0x0
0x8
registers
n
0x10
0x8
registers
n
0x110
0x8
registers
n
0x120
0x4
registers
n
0x20
0x8
registers
n
0x200
0x3C
registers
n
0x250
0x8
registers
n
0x30
0x4
registers
n
0x304
0x4
registers
n
0x31C
0x18
registers
n
0x50
0x18
registers
n
0x90
0x4
registers
n
0xB0
0x10
registers
n
0xD4
0x8
registers
n
0xE0
0x4
registers
n
0xE8
0x4
registers
n
0xF8
0x8
registers
n
BPWM_ADCTS0
BPWM_ADCTS0
BPWM Trigger ADC Source Select Register 0
0xF8
read-write
n
0x0
0x0
TRGEN0
BPWM_CH0 Trigger ADC Enable Bit
7
1
read-write
TRGEN1
BPWM_CH1 Trigger ADC Enable Bit
15
1
read-write
TRGEN2
BPWM_CH2 Trigger ADC Enable Bit
23
1
read-write
TRGEN3
BPWM_CH3 Trigger ADC Enable Bit
31
1
read-write
TRGSEL0
BPWM_CH0 Trigger ADC Source Select\nOthers reserved
0
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count CMPDAT point
#0011
4
BPWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH1 up-count CMPDAT point
#1000
9
BPWM_CH1 down-count CMPDAT point
#1001
TRGSEL1
BPWM_CH1 Trigger ADC Source Select\nOthers reserved
8
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count CMPDAT point
#0011
4
BPWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH1 up-count CMPDAT point
#1000
9
BPWM_CH1 down-count CMPDAT point
#1001
TRGSEL2
BPWM_CH2 Trigger ADC Source Select\nOthers reserved
16
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count CMPDAT point
#0011
4
BPWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH3 up-count CMPDAT point
#1000
9
BPWM_CH3 down-count CMPDAT point
#1001
TRGSEL3
BPWM_CH3 Trigger ADC Source Select\nOthers reserved.
24
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count CMPDAT point
#0011
4
BPWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH3 up-count CMPDAT point
#1000
9
BPWM_CH3 down-count CMPDAT point
#1001
BPWM_ADCTS1
BPWM_ADCTS1
BPWM Trigger ADC Source Select Register 1
0xFC
read-write
n
0x0
0x0
TRGEN4
BPWM_CH4 Trigger ADC Enable Bit
7
1
read-write
TRGEN5
BPWM_CH5 Trigger ADC Enable Bit
15
1
read-write
TRGSEL4
BPWM_CH4 Trigger ADC Source Select\nOthers reserved
0
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count CMPDAT point
#0011
4
BPWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH5 up-count CMPDAT point
#1000
9
BPWM_CH5 down-count CMPDAT point
#1001
TRGSEL5
BPWM_CH5 Trigger ADC Source Select\nOthers reserved
8
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count CMPDAT point
#0011
4
BPWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH5 up-count CMPDAT point
#1000
9
BPWM_CH5 down-count CMPDAT point
#1001
BPWM_CAPCTL
BPWM_CAPCTL
BPWM Capture Control Register
0x204
read-write
n
0x0
0x0
CAPEN0
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN1
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN2
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN3
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN4
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN5
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPINV0
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
8
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
9
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV2
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
10
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
11
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV4
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
12
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV5
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
13
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
FCRLDEN0
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN1
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN2
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN3
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN4
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN5
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
RCRLDEN0
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN1
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN2
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN3
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN4
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN5
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
BPWM_CAPIEN
BPWM_CAPIEN
BPWM Capture Interrupt Enable Register
0x250
read-write
n
0x0
0x0
CAPFIENn
BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
8
6
read-write
0
Capture falling edge latch interrupt Disabled
0
1
Capture falling edge latch interrupt Enabled
1
CAPRIENn
BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
6
read-write
0
Capture rising edge latch interrupt Disabled
0
1
Capture rising edge latch interrupt Enabled
1
BPWM_CAPIF
BPWM_CAPIF
BPWM Capture Interrupt Flag Register
0x254
read-write
n
0x0
0x0
CAPFIF0
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
8
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF1
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
9
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF2
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
10
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF3
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
11
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF4
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
12
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF5
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
13
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPRIF0
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF1
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF2
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
2
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF3
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
3
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF4
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
4
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF5
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
5
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
BPWM_CAPINEN
BPWM_CAPINEN
BPWM Capture Input Enable Register
0x200
read-write
n
0x0
0x0
CAPINEN0
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN1
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN2
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN3
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN4
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN5
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
BPWM_CAPSTS
BPWM_CAPSTS
BPWM Capture Status Register
0x208
read-only
n
0x0
0x0
CFIFOV0
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPFIF.
8
1
read-only
CFIFOV1
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPFIF.
9
1
read-only
CFIFOV2
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPFIF.
10
1
read-only
CFIFOV3
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPFIF.
11
1
read-only
CFIFOV4
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPFIF.
12
1
read-only
CFIFOV5
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPFIF.
13
1
read-only
CRIFOV0
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPRIF.
0
1
read-only
CRIFOV1
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPRIF.
1
1
read-only
CRIFOV2
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPRIF.
2
1
read-only
CRIFOV3
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPRIF.
3
1
read-only
CRIFOV4
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPRIF.
4
1
read-only
CRIFOV5
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPRIF.
5
1
read-only
BPWM_CLKPSC
BPWM_CLKPSC
BPWM Clock Prescale Register
0x14
read-write
n
0x0
0x0
CLKPSC
BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1).
0
12
read-write
BPWM_CLKSRC
BPWM_CLKSRC
BPWM Clock Source Register
0x10
read-write
n
0x0
0x0
ECLKSRC0
BPWM_CH01 External Clock Source Select
0
3
read-write
0
BPWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
BPWM_CMPBUF0
BPWM_CMPBUF0
BPWM CMPDAT 0 Buffer
0x31C
read-only
n
0x0
0x0
CMPBUF
BPWM Comparator Buffer (Read Only)\nUsed as CMP active register.
0
16
read-only
BPWM_CMPBUF1
BPWM_CMPBUF1
BPWM CMPDAT 1 Buffer
0x320
read-write
n
0x0
0x0
BPWM_CMPBUF2
BPWM_CMPBUF2
BPWM CMPDAT 2 Buffer
0x324
read-write
n
0x0
0x0
BPWM_CMPBUF3
BPWM_CMPBUF3
BPWM CMPDAT 3 Buffer
0x328
read-write
n
0x0
0x0
BPWM_CMPBUF4
BPWM_CMPBUF4
BPWM CMPDAT 4 Buffer
0x32C
read-write
n
0x0
0x0
BPWM_CMPBUF5
BPWM_CMPBUF5
BPWM CMPDAT 5 Buffer
0x330
read-write
n
0x0
0x0
BPWM_CMPDAT0
BPWM_CMPDAT0
BPWM Comparator Register 0
0x50
read-write
n
0x0
0x0
CMPDAT
BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger ADC.\nIn independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.
0
16
read-write
BPWM_CMPDAT1
BPWM_CMPDAT1
BPWM Comparator Register 1
0x54
read-write
n
0x0
0x0
BPWM_CMPDAT2
BPWM_CMPDAT2
BPWM Comparator Register 2
0x58
read-write
n
0x0
0x0
BPWM_CMPDAT3
BPWM_CMPDAT3
BPWM Comparator Register 3
0x5C
read-write
n
0x0
0x0
BPWM_CMPDAT4
BPWM_CMPDAT4
BPWM Comparator Register 4
0x60
read-write
n
0x0
0x0
BPWM_CMPDAT5
BPWM_CMPDAT5
BPWM Comparator Register 5
0x64
read-write
n
0x0
0x0
BPWM_CNT
BPWM_CNT
BPWM Counter Register
0x90
read-only
n
0x0
0x0
CNT
BPWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter.
0
16
read-only
DIRF
BPWM Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is Down count
#0
1
Counter is UP count
#1
BPWM_CNTCLR
BPWM_CNTCLR
BPWM Clear Counter Register
0x24
read-write
n
0x0
0x0
CNTCLR0
Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit BPWM counter to 0000H
#1
BPWM_CNTEN
BPWM_CNTEN
BPWM Counter Enable Register
0x20
read-write
n
0x0
0x0
CNTEN0
BPWM Counter 0 Enable Bit
0
1
read-write
0
BPWM Counter and clock prescaler stop running
#0
1
BPWM Counter and clock prescaler start running
#1
BPWM_CTL0
BPWM_CTL0
BPWM Control Register 0
0x0
read-write
n
0x0
0x0
CTRLD0
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
0
1
read-write
CTRLD1
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
1
1
read-write
CTRLD2
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
2
1
read-write
CTRLD3
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
3
1
read-write
CTRLD4
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
4
1
read-write
CTRLD5
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
5
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt Disabled
#0
1
ICE debug mode counter halt Enabled
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects BPWM output
#0
1
ICE debug mode acknowledgement Disabled
#1
IMMLDEN0
Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
16
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN1
Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
17
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN2
Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
18
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN3
Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
19
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN4
Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
20
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN5
Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
21
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
BPWM_CTL1
BPWM_CTL1
BPWM Control Register 1
0x4
read-write
n
0x0
0x0
CNTTYPE0
BPWM Counter Behavior Type 0\nEach bit n controls corresponding BPWM channel n.
0
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
BPWM_FCAPDAT0
BPWM_FCAPDAT0
BPWM Falling Capture Data Register 0
0x210
read-only
n
0x0
0x0
FCAPDAT
BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_FCAPDAT1
BPWM_FCAPDAT1
BPWM Falling Capture Data Register 1
0x218
read-write
n
0x0
0x0
BPWM_FCAPDAT2
BPWM_FCAPDAT2
BPWM Falling Capture Data Register 2
0x220
read-write
n
0x0
0x0
BPWM_FCAPDAT3
BPWM_FCAPDAT3
BPWM Falling Capture Data Register 3
0x228
read-write
n
0x0
0x0
BPWM_FCAPDAT4
BPWM_FCAPDAT4
BPWM Falling Capture Data Register 4
0x230
read-write
n
0x0
0x0
BPWM_FCAPDAT5
BPWM_FCAPDAT5
BPWM Falling Capture Data Register 5
0x238
read-write
n
0x0
0x0
BPWM_INTEN
BPWM_INTEN
BPWM Interrupt Enable Register
0xE0
read-write
n
0x0
0x0
CMPDIEN0
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN1
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN2
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN3
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN4
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN5
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN0
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN1
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN2
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN3
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN4
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN5
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN0
BPWM Period Point Interrupt 0 Enable Bit\nNote: When up-down counter type period point means center point.
8
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN0
BPWM Zero Point Interrupt 0 Enable Bit
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
BPWM_INTSTS
BPWM_INTSTS
BPWM Interrupt Flag Register
0xE8
read-write
n
0x0
0x0
CMPDIF0
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
24
1
read-write
CMPDIF1
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
25
1
read-write
CMPDIF2
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
26
1
read-write
CMPDIF3
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
27
1
read-write
CMPDIF4
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
28
1
read-write
CMPDIF5
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
29
1
read-write
CMPUIF0
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
16
1
read-write
CMPUIF1
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
17
1
read-write
CMPUIF2
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
18
1
read-write
CMPUIF3
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
19
1
read-write
CMPUIF4
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
20
1
read-write
CMPUIF5
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
21
1
read-write
PIF0
BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to 0.
8
1
read-write
ZIF0
BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0, software can write 1 to clear this bit to 0.
0
1
read-write
BPWM_MSK
BPWM_MSK
BPWM Mask Data Register
0xBC
read-write
n
0x0
0x0
MSKDAT0
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT1
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT2
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT3
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT4
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT5
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
BPWM_MSKEN
BPWM_MSKEN
BPWM Mask Enable Register
0xB8
read-write
n
0x0
0x0
MSKEN0
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
0
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN1
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
1
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN2
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
2
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN3
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
3
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN4
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
4
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN5
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
5
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
BPWM_PBUF
BPWM_PBUF
BPWM PERIOD Buffer
0x304
read-only
n
0x0
0x0
PBUF
BPWM Period Buffer (Read Only)\nUsed as PERIOD active register.
0
16
read-only
BPWM_PERIOD
BPWM_PERIOD
BPWM Period Register
0x30
read-write
n
0x0
0x0
PERIOD
BPWM Period Register\nUp-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
0
16
read-write
BPWM_POEN
BPWM_POEN
BPWM Output Enable Register
0xD8
read-write
n
0x0
0x0
POEN0
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN1
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN2
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN3
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN4
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN5
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
BPWM_POLCTL
BPWM_POLCTL
BPWM Pin Polar Inverse Register
0xD4
read-write
n
0x0
0x0
PINV0
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
PINV1
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
PINV2
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
PINV3
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
PINV4
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
PINV5
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
BPWM_RCAPDAT0
BPWM_RCAPDAT0
BPWM Rising Capture Data Register 0
0x20C
read-only
n
0x0
0x0
RCAPDAT
BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_RCAPDAT1
BPWM_RCAPDAT1
BPWM Rising Capture Data Register 1
0x214
read-write
n
0x0
0x0
BPWM_RCAPDAT2
BPWM_RCAPDAT2
BPWM Rising Capture Data Register 2
0x21C
read-write
n
0x0
0x0
BPWM_RCAPDAT3
BPWM_RCAPDAT3
BPWM Rising Capture Data Register 3
0x224
read-write
n
0x0
0x0
BPWM_RCAPDAT4
BPWM_RCAPDAT4
BPWM Rising Capture Data Register 4
0x22C
read-write
n
0x0
0x0
BPWM_RCAPDAT5
BPWM_RCAPDAT5
BPWM Rising Capture Data Register 5
0x234
read-write
n
0x0
0x0
BPWM_SSCTL
BPWM_SSCTL
BPWM Synchronous Start Control Register
0x110
read-write
n
0x0
0x0
SSEN0
BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
0
1
read-write
0
BPWM synchronous start function Disabled
#0
1
BPWM synchronous start function Enabled
#1
SSRC
BPWM Synchronous Start Source Select
8
2
read-write
0
Synchronous start source come from PWM0
#00
1
Synchronous start source come from PWM1
#01
2
Synchronous start source come from BPWM0
#10
3
Synchronous start source come from BPWM1
#11
BPWM_SSTRG
BPWM_SSTRG
BPWM Synchronous Start Trigger Register
0x114
write-only
n
0x0
0x0
CNTSEN
BPWM Counter Synchronous Start Enable Bit(Write Only)\nBPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
0
1
write-only
BPWM_STATUS
BPWM_STATUS
BPWM Status Register
0x120
read-write
n
0x0
0x0
ADCTRG0
ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.
16
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
ADCTRG1
ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.
17
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
ADCTRG2
ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.
18
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
ADCTRG3
ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.
19
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
ADCTRG4
ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.
20
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
ADCTRG5
ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.
21
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
CNTMAX0
Time-base Counter 0 Equal to 0xFFFF Latched Status
0
1
read-write
0
The time-base counter never reached its maximum value 0xFFFF
#0
1
The time-base counter reached its maximum value. Software can write 1 to clear this bit
#1
BPWM_WGCTL0
BPWM_WGCTL0
BPWM Generation Register 0
0xB0
read-write
n
0x0
0x0
PRDPCTL0
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
16
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL1
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
18
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL2
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
20
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL3
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
22
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL4
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
24
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL5
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
26
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
ZPCTL0
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero.
0
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL1
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero.
2
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL2
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero.
4
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL3
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero.
6
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL4
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero.
8
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL5
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero.
10
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
BPWM_WGCTL1
BPWM_WGCTL1
BPWM Generation Register 1
0xB4
read-write
n
0x0
0x0
CMPDCTL0
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT.
16
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL1
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT.
18
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL2
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT.
20
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL3
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT.
22
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL4
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT.
24
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL5
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT.
26
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPUCTL0
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT.
0
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL1
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT.
2
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL2
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT.
4
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL3
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT.
6
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL4
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT.
8
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL5
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT.
10
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
BPWM1
BPWM Register Map
BPWM
0x0
0x0
0x8
registers
n
0x10
0x8
registers
n
0x110
0x8
registers
n
0x120
0x4
registers
n
0x20
0x8
registers
n
0x200
0x3C
registers
n
0x250
0x8
registers
n
0x30
0x4
registers
n
0x304
0x4
registers
n
0x31C
0x18
registers
n
0x50
0x18
registers
n
0x90
0x4
registers
n
0xB0
0x10
registers
n
0xD4
0x8
registers
n
0xE0
0x4
registers
n
0xE8
0x4
registers
n
0xF8
0x8
registers
n
BPWM_ADCTS0
BPWM_ADCTS0
BPWM Trigger ADC Source Select Register 0
0xF8
read-write
n
0x0
0x0
TRGEN0
BPWM_CH0 Trigger ADC Enable Bit
7
1
read-write
TRGEN1
BPWM_CH1 Trigger ADC Enable Bit
15
1
read-write
TRGEN2
BPWM_CH2 Trigger ADC Enable Bit
23
1
read-write
TRGEN3
BPWM_CH3 Trigger ADC Enable Bit
31
1
read-write
TRGSEL0
BPWM_CH0 Trigger ADC Source Select\nOthers reserved
0
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count CMPDAT point
#0011
4
BPWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH1 up-count CMPDAT point
#1000
9
BPWM_CH1 down-count CMPDAT point
#1001
TRGSEL1
BPWM_CH1 Trigger ADC Source Select\nOthers reserved
8
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count CMPDAT point
#0011
4
BPWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH1 up-count CMPDAT point
#1000
9
BPWM_CH1 down-count CMPDAT point
#1001
TRGSEL2
BPWM_CH2 Trigger ADC Source Select\nOthers reserved
16
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count CMPDAT point
#0011
4
BPWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH3 up-count CMPDAT point
#1000
9
BPWM_CH3 down-count CMPDAT point
#1001
TRGSEL3
BPWM_CH3 Trigger ADC Source Select\nOthers reserved.
24
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count CMPDAT point
#0011
4
BPWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH3 up-count CMPDAT point
#1000
9
BPWM_CH3 down-count CMPDAT point
#1001
BPWM_ADCTS1
BPWM_ADCTS1
BPWM Trigger ADC Source Select Register 1
0xFC
read-write
n
0x0
0x0
TRGEN4
BPWM_CH4 Trigger ADC Enable Bit
7
1
read-write
TRGEN5
BPWM_CH5 Trigger ADC Enable Bit
15
1
read-write
TRGSEL4
BPWM_CH4 Trigger ADC Source Select\nOthers reserved
0
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count CMPDAT point
#0011
4
BPWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH5 up-count CMPDAT point
#1000
9
BPWM_CH5 down-count CMPDAT point
#1001
TRGSEL5
BPWM_CH5 Trigger ADC Source Select\nOthers reserved
8
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count CMPDAT point
#0011
4
BPWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH5 up-count CMPDAT point
#1000
9
BPWM_CH5 down-count CMPDAT point
#1001
BPWM_CAPCTL
BPWM_CAPCTL
BPWM Capture Control Register
0x204
read-write
n
0x0
0x0
CAPEN0
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN1
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN2
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN3
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN4
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN5
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPINV0
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
8
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
9
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV2
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
10
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
11
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV4
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
12
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV5
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
13
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
FCRLDEN0
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN1
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN2
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN3
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN4
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN5
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
RCRLDEN0
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN1
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN2
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN3
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN4
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN5
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
BPWM_CAPIEN
BPWM_CAPIEN
BPWM Capture Interrupt Enable Register
0x250
read-write
n
0x0
0x0
CAPFIENn
BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
8
6
read-write
0
Capture falling edge latch interrupt Disabled
0
1
Capture falling edge latch interrupt Enabled
1
CAPRIENn
BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
6
read-write
0
Capture rising edge latch interrupt Disabled
0
1
Capture rising edge latch interrupt Enabled
1
BPWM_CAPIF
BPWM_CAPIF
BPWM Capture Interrupt Flag Register
0x254
read-write
n
0x0
0x0
CAPFIF0
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
8
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF1
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
9
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF2
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
10
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF3
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
11
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF4
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
12
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF5
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
13
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPRIF0
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF1
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF2
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
2
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF3
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
3
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF4
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
4
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF5
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
5
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
BPWM_CAPINEN
BPWM_CAPINEN
BPWM Capture Input Enable Register
0x200
read-write
n
0x0
0x0
CAPINEN0
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN1
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN2
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN3
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN4
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN5
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
BPWM_CAPSTS
BPWM_CAPSTS
BPWM Capture Status Register
0x208
read-only
n
0x0
0x0
CFIFOV0
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPFIF.
8
1
read-only
CFIFOV1
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPFIF.
9
1
read-only
CFIFOV2
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPFIF.
10
1
read-only
CFIFOV3
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPFIF.
11
1
read-only
CFIFOV4
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPFIF.
12
1
read-only
CFIFOV5
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPFIF.
13
1
read-only
CRIFOV0
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPRIF.
0
1
read-only
CRIFOV1
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPRIF.
1
1
read-only
CRIFOV2
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPRIF.
2
1
read-only
CRIFOV3
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPRIF.
3
1
read-only
CRIFOV4
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPRIF.
4
1
read-only
CRIFOV5
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CAPRIF.
5
1
read-only
BPWM_CLKPSC
BPWM_CLKPSC
BPWM Clock Prescale Register
0x14
read-write
n
0x0
0x0
CLKPSC
BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1).
0
12
read-write
BPWM_CLKSRC
BPWM_CLKSRC
BPWM Clock Source Register
0x10
read-write
n
0x0
0x0
ECLKSRC0
BPWM_CH01 External Clock Source Select
0
3
read-write
0
BPWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
BPWM_CMPBUF0
BPWM_CMPBUF0
BPWM CMPDAT 0 Buffer
0x31C
read-only
n
0x0
0x0
CMPBUF
BPWM Comparator Buffer (Read Only)\nUsed as CMP active register.
0
16
read-only
BPWM_CMPBUF1
BPWM_CMPBUF1
BPWM CMPDAT 1 Buffer
0x320
read-write
n
0x0
0x0
BPWM_CMPBUF2
BPWM_CMPBUF2
BPWM CMPDAT 2 Buffer
0x324
read-write
n
0x0
0x0
BPWM_CMPBUF3
BPWM_CMPBUF3
BPWM CMPDAT 3 Buffer
0x328
read-write
n
0x0
0x0
BPWM_CMPBUF4
BPWM_CMPBUF4
BPWM CMPDAT 4 Buffer
0x32C
read-write
n
0x0
0x0
BPWM_CMPBUF5
BPWM_CMPBUF5
BPWM CMPDAT 5 Buffer
0x330
read-write
n
0x0
0x0
BPWM_CMPDAT0
BPWM_CMPDAT0
BPWM Comparator Register 0
0x50
read-write
n
0x0
0x0
CMPDAT
BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger ADC.\nIn independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.
0
16
read-write
BPWM_CMPDAT1
BPWM_CMPDAT1
BPWM Comparator Register 1
0x54
read-write
n
0x0
0x0
BPWM_CMPDAT2
BPWM_CMPDAT2
BPWM Comparator Register 2
0x58
read-write
n
0x0
0x0
BPWM_CMPDAT3
BPWM_CMPDAT3
BPWM Comparator Register 3
0x5C
read-write
n
0x0
0x0
BPWM_CMPDAT4
BPWM_CMPDAT4
BPWM Comparator Register 4
0x60
read-write
n
0x0
0x0
BPWM_CMPDAT5
BPWM_CMPDAT5
BPWM Comparator Register 5
0x64
read-write
n
0x0
0x0
BPWM_CNT
BPWM_CNT
BPWM Counter Register
0x90
read-only
n
0x0
0x0
CNT
BPWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter.
0
16
read-only
DIRF
BPWM Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is Down count
#0
1
Counter is UP count
#1
BPWM_CNTCLR
BPWM_CNTCLR
BPWM Clear Counter Register
0x24
read-write
n
0x0
0x0
CNTCLR0
Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit BPWM counter to 0000H
#1
BPWM_CNTEN
BPWM_CNTEN
BPWM Counter Enable Register
0x20
read-write
n
0x0
0x0
CNTEN0
BPWM Counter 0 Enable Bit
0
1
read-write
0
BPWM Counter and clock prescaler stop running
#0
1
BPWM Counter and clock prescaler start running
#1
BPWM_CTL0
BPWM_CTL0
BPWM Control Register 0
0x0
read-write
n
0x0
0x0
CTRLD0
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
0
1
read-write
CTRLD1
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
1
1
read-write
CTRLD2
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
2
1
read-write
CTRLD3
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
3
1
read-write
CTRLD4
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
4
1
read-write
CTRLD5
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
5
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt Disabled
#0
1
ICE debug mode counter halt Enabled
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects BPWM output
#0
1
ICE debug mode acknowledgement Disabled
#1
IMMLDEN0
Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
16
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN1
Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
17
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN2
Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
18
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN3
Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
19
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN4
Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
20
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN5
Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
21
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
BPWM_CTL1
BPWM_CTL1
BPWM Control Register 1
0x4
read-write
n
0x0
0x0
CNTTYPE0
BPWM Counter Behavior Type 0\nEach bit n controls corresponding BPWM channel n.
0
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
BPWM_FCAPDAT0
BPWM_FCAPDAT0
BPWM Falling Capture Data Register 0
0x210
read-only
n
0x0
0x0
FCAPDAT
BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_FCAPDAT1
BPWM_FCAPDAT1
BPWM Falling Capture Data Register 1
0x218
read-write
n
0x0
0x0
BPWM_FCAPDAT2
BPWM_FCAPDAT2
BPWM Falling Capture Data Register 2
0x220
read-write
n
0x0
0x0
BPWM_FCAPDAT3
BPWM_FCAPDAT3
BPWM Falling Capture Data Register 3
0x228
read-write
n
0x0
0x0
BPWM_FCAPDAT4
BPWM_FCAPDAT4
BPWM Falling Capture Data Register 4
0x230
read-write
n
0x0
0x0
BPWM_FCAPDAT5
BPWM_FCAPDAT5
BPWM Falling Capture Data Register 5
0x238
read-write
n
0x0
0x0
BPWM_INTEN
BPWM_INTEN
BPWM Interrupt Enable Register
0xE0
read-write
n
0x0
0x0
CMPDIEN0
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN1
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN2
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN3
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN4
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN5
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN0
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN1
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN2
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN3
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN4
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN5
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN0
BPWM Period Point Interrupt 0 Enable Bit\nNote: When up-down counter type period point means center point.
8
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN0
BPWM Zero Point Interrupt 0 Enable Bit
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
BPWM_INTSTS
BPWM_INTSTS
BPWM Interrupt Flag Register
0xE8
read-write
n
0x0
0x0
CMPDIF0
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
24
1
read-write
CMPDIF1
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
25
1
read-write
CMPDIF2
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
26
1
read-write
CMPDIF3
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
27
1
read-write
CMPDIF4
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
28
1
read-write
CMPDIF5
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
29
1
read-write
CMPUIF0
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
16
1
read-write
CMPUIF1
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
17
1
read-write
CMPUIF2
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
18
1
read-write
CMPUIF3
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
19
1
read-write
CMPUIF4
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
20
1
read-write
CMPUIF5
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
21
1
read-write
PIF0
BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to 0.
8
1
read-write
ZIF0
BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0, software can write 1 to clear this bit to 0.
0
1
read-write
BPWM_MSK
BPWM_MSK
BPWM Mask Data Register
0xBC
read-write
n
0x0
0x0
MSKDAT0
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT1
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT2
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT3
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT4
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT5
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
BPWM_MSKEN
BPWM_MSKEN
BPWM Mask Enable Register
0xB8
read-write
n
0x0
0x0
MSKEN0
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
0
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN1
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
1
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN2
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
2
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN3
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
3
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN4
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
4
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN5
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
5
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
BPWM_PBUF
BPWM_PBUF
BPWM PERIOD Buffer
0x304
read-only
n
0x0
0x0
PBUF
BPWM Period Buffer (Read Only)\nUsed as PERIOD active register.
0
16
read-only
BPWM_PERIOD
BPWM_PERIOD
BPWM Period Register
0x30
read-write
n
0x0
0x0
PERIOD
BPWM Period Register\nUp-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
0
16
read-write
BPWM_POEN
BPWM_POEN
BPWM Output Enable Register
0xD8
read-write
n
0x0
0x0
POEN0
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN1
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN2
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN3
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN4
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN5
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
BPWM_POLCTL
BPWM_POLCTL
BPWM Pin Polar Inverse Register
0xD4
read-write
n
0x0
0x0
PINV0
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
PINV1
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
PINV2
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
PINV3
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
PINV4
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
PINV5
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
BPWM_RCAPDAT0
BPWM_RCAPDAT0
BPWM Rising Capture Data Register 0
0x20C
read-only
n
0x0
0x0
RCAPDAT
BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_RCAPDAT1
BPWM_RCAPDAT1
BPWM Rising Capture Data Register 1
0x214
read-write
n
0x0
0x0
BPWM_RCAPDAT2
BPWM_RCAPDAT2
BPWM Rising Capture Data Register 2
0x21C
read-write
n
0x0
0x0
BPWM_RCAPDAT3
BPWM_RCAPDAT3
BPWM Rising Capture Data Register 3
0x224
read-write
n
0x0
0x0
BPWM_RCAPDAT4
BPWM_RCAPDAT4
BPWM Rising Capture Data Register 4
0x22C
read-write
n
0x0
0x0
BPWM_RCAPDAT5
BPWM_RCAPDAT5
BPWM Rising Capture Data Register 5
0x234
read-write
n
0x0
0x0
BPWM_SSCTL
BPWM_SSCTL
BPWM Synchronous Start Control Register
0x110
read-write
n
0x0
0x0
SSEN0
BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
0
1
read-write
0
BPWM synchronous start function Disabled
#0
1
BPWM synchronous start function Enabled
#1
SSRC
BPWM Synchronous Start Source Select
8
2
read-write
0
Synchronous start source come from PWM0
#00
1
Synchronous start source come from PWM1
#01
2
Synchronous start source come from BPWM0
#10
3
Synchronous start source come from BPWM1
#11
BPWM_SSTRG
BPWM_SSTRG
BPWM Synchronous Start Trigger Register
0x114
write-only
n
0x0
0x0
CNTSEN
BPWM Counter Synchronous Start Enable Bit(Write Only)\nBPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
0
1
write-only
BPWM_STATUS
BPWM_STATUS
BPWM Status Register
0x120
read-write
n
0x0
0x0
ADCTRG0
ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.
16
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
ADCTRG1
ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.
17
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
ADCTRG2
ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.
18
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
ADCTRG3
ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.
19
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
ADCTRG4
ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.
20
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
ADCTRG5
ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.
21
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
CNTMAX0
Time-base Counter 0 Equal to 0xFFFF Latched Status
0
1
read-write
0
The time-base counter never reached its maximum value 0xFFFF
#0
1
The time-base counter reached its maximum value. Software can write 1 to clear this bit
#1
BPWM_WGCTL0
BPWM_WGCTL0
BPWM Generation Register 0
0xB0
read-write
n
0x0
0x0
PRDPCTL0
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
16
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL1
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
18
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL2
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
20
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL3
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
22
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL4
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
24
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL5
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
26
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
ZPCTL0
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero.
0
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL1
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero.
2
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL2
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero.
4
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL3
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero.
6
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL4
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero.
8
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL5
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero.
10
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
BPWM_WGCTL1
BPWM_WGCTL1
BPWM Generation Register 1
0xB4
read-write
n
0x0
0x0
CMPDCTL0
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT.
16
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL1
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT.
18
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL2
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT.
20
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL3
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT.
22
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL4
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT.
24
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL5
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT.
26
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPUCTL0
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT.
0
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL1
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT.
2
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL2
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT.
4
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL3
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT.
6
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL4
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT.
8
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL5
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT.
10
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CLK
CLK Register Map
CLK
0x0
0x0
0x24
registers
n
0x30
0x8
registers
n
0x40
0x4
registers
n
0x50
0x4
registers
n
0x60
0x4
registers
n
0x70
0x14
registers
n
0xB4
0x4
registers
n
AHBCLK
CLK_AHBCLK
AHB Devices Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
CRCCKEN
CRC Generator Controller Clock Enable Bit
7
1
read-write
0
CRC peripheral clock Disabled
#0
1
CRC peripheral clock Enabled
#1
EBICKEN
EBI Controller Clock Enable Bit
3
1
read-write
0
EBI peripheral clock Disabled
#0
1
EBI peripheral clock Enabled
#1
HDIV_EN
Divider Controller Clock Enable Control
4
1
read-write
0
Divider controller peripheral clock Disabled
#0
1
Divider controller peripheral clock Enabled
#1
ISPCKEN
Flash ISP Controller Clock Enable Bit
2
1
read-write
0
Flash ISP peripheral clock Disabled
#0
1
Flash ISP peripheral clock Enabled
#1
PDMACKEN
PDMA Controller Clock Enable Bit
1
1
read-write
0
PDMA peripheral clock Disabled
#0
1
PDMA peripheral clock Enabled
#1
APBCLK0
CLK_APBCLK0
APB Devices Clock Enable Control Register 0
0x8
-1
read-write
n
0x0
0x0
ACMP01CKEN
Analog Comparator 0/1 Clock Enable Bit
7
1
read-write
0
Analog comparator 0/1 clock Disabled
#0
1
Analog comparator 0/1 clock Enabled
#1
ADCCKEN
Analog-digital-converter (ADC) Clock Enable Bit
28
1
read-write
0
ADC clock Disabled
#0
1
ADC clock Enabled
#1
CLKOCKEN
CLKO Clock Enable Bit
6
1
read-write
0
CLKO clock Disabled
#0
1
CLKO clock Enabled
#1
I2C0CKEN
I2C0 Clock Enable Bit
8
1
read-write
0
I2C0 clock Disabled
#0
1
I2C0 clock Enabled
#1
I2C1CKEN
I2C1 Clock Enable Bit
9
1
read-write
0
I2C1 clock Disabled
#0
1
I2C1 clock Enabled
#1
QSPI0CKEN
QSPI0 Clock Enable Bit
12
1
read-write
0
QSPI0 clock Disabled
#0
1
QSPI0 clock Enabled
#1
RTCCKEN
RTC Clock Enable Bit
1
1
read-write
0
RTC clock Disabled
#0
1
RTC clock Enabled
#1
SPI0CKEN
SPI0 Clock Enable Bit
13
1
read-write
0
SPI0 clock Disabled
#0
1
SPI0 clock Enabled
#1
TMR0CKEN
Timer0 Clock Enable Bit
2
1
read-write
0
Timer0 clock Disabled
#0
1
Timer0 clock Enabled
#1
TMR1CKEN
Timer1 Clock Enable Bit
3
1
read-write
0
Timer1 clock Disabled
#0
1
Timer1 clock Enabled
#1
TMR2CKEN
Timer2 Clock Enable Bit
4
1
read-write
0
Timer2 clock Disabled
#0
1
Timer2 clock Enabled
#1
TMR3CKEN
Timer3 Clock Enable Bit
5
1
read-write
0
Timer3 clock Disabled
#0
1
Timer3 clock Enabled
#1
UART0CKEN
UART0 Clock Enable Bit
16
1
read-write
0
UART0 clock Disabled
#0
1
UART0 clock Enabled
#1
UART1CKEN
UART1 Clock Enable Bit
17
1
read-write
0
UART1 clock Disabled
#0
1
UART1 clock Enabled
#1
UART2CKEN
UART2 Clock Enable Bit
18
1
read-write
0
UART2 clock Disabled
#0
1
UART2 clock Enabled
#1
UART3CKEN
UART3 Clock Enable Bit
19
1
read-write
0
UART3 clock Disabled
#0
1
UART3 clock Enabled
#1
UART4CKEN
UART4 Clock Enable Bit
20
1
read-write
0
UART4 clock Disabled
#0
1
UART4 clock Enabled
#1
UART5CKEN
UART5 Clock Enable Bit
21
1
read-write
0
UART5 clock Disabled
#0
1
UART5 clock Enabled
#1
UART6CKEN
UART6 Clock Enable Bit
22
1
read-write
0
UART6 clock Disabled
#0
1
UART6 clock Enabled
#1
UART7CKEN
UART7 Clock Enable Bit
23
1
read-write
0
UART7 clock Disabled
#0
1
UART7 clock Enabled
#1
USBDCKEN
USB Device Clock Enable Bit
27
1
read-write
0
USB Device clock Disabled
#0
1
USB Device clock Enabled
#1
WDTCKEN
Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote: This bit is reset by power on reset, Watchdog reset or software chip reset.
0
1
read-write
0
Watchdog timer clock Disabled
#0
1
Watchdog timer clock Enabled
#1
APBCLK1
CLK_APBCLK1
APB Devices Clock Enable Control Register 1
0xC
read-write
n
0x0
0x0
BPWM0CKEN
BPWM0 Clock Enable Bit
18
1
read-write
0
BPWM0 clock Disabled
#0
1
BPWM0 clock Enabled
#1
BPWM1CKEN
BPWM1 Clock Enable Bit
19
1
read-write
0
BPWM1 clock Disabled
#0
1
BPWM1 clock Enabled
#1
PWM0CKEN
PWM0 Clock Enable Bit
16
1
read-write
0
PWM0 clock Disabled
#0
1
PWM0 clock Enabled
#1
PWM1CKEN
PWM1 Clock Enable Bit
17
1
read-write
0
PWM1 clock Disabled
#0
1
PWM1 clock Enabled
#1
USCI0CKEN
USCI0 Clock Enable Bit
8
1
read-write
0
USCI0 clock Disabled
#0
1
USCI0 clock Enabled
#1
USCI1CKEN
USCI1 Clock Enable Bit
9
1
read-write
0
USCI1 clock Disabled
#0
1
USCI1 clock Enabled
#1
CDLOWB
CLK_CDLOWB
Clock Frequency Range Detector Lower Boundary Register
0x7C
read-write
n
0x0
0x0
LOWERBD
HXT Clock Frequency Range Detector Lower Boundary Value\nThe bits define the minimum value of frequency range detector window.\nWhen HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
0
10
read-write
CDUPB
CLK_CDUPB
Clock Frequency Range Detector Upper Boundary Register
0x78
read-write
n
0x0
0x0
UPERBD
HXT Clock Frequency Range Detector Upper Boundary Value\nThe bits define the maximum value of frequency range detector window.\nWhen HXT frequency is higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will be set to 1.
0
10
read-write
CLKDCTL
CLK_CLKDCTL
Clock Fail Detector Control Register
0x70
read-write
n
0x0
0x0
HXTFDEN
HXT Clock Fail Detector Enable Bit
4
1
read-write
0
External high speed crystal oscillator (HXT) clock fail detector Disabled
#0
1
External high speed crystal oscillator (HXT) clock fail detector Enabled
#1
HXTFIEN
HXT Clock Fail Interrupt Enable Bit
5
1
read-write
0
External high speed crystal oscillator (HXT) clock fail interrupt Disabled
#0
1
External high speed crystal oscillator (HXT) clock fail interrupt Enabled
#1
HXTFQDEN
HXT Clock Frequency Range Detector Enable Bit
16
1
read-write
0
External high speed crystal oscillator (HXT) clock frequency range detector Disabled
#0
1
External high speed crystal oscillator (HXT) clock frequency range detector Enabled
#1
HXTFQIEN
HXT Clock Frequency Range Detector Interrupt Enable Bit
17
1
read-write
0
External high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled
#0
1
External high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled
#1
LXTFDEN
LXT Clock Fail Detector Enable Bit
12
1
read-write
0
External low speed crystal oscillator (LXT) clock fail detector Disabled
#0
1
External low speed crystal oscillator (LXT) clock fail detector Enabled
#1
LXTFIEN
LXT Clock Fail Interrupt Enable Bit
13
1
read-write
0
External low speed crystal oscillator (LXT) clock fail interrupt Disabled
#0
1
External low speed crystal oscillator (LXT) clock fail interrupt Enabled
#1
CLKDIV0
CLK_CLKDIV0
Clock Divider Number Register 0
0x20
read-write
n
0x0
0x0
ADCDIV
ADC Clock Divide Number From ADC Clock Source
16
8
read-write
HCLKDIV
HCLK Clock Divide Number From HCLK Clock Source
0
4
read-write
UART0DIV
UART0 Clock Divide Number From UART0 Clock Source
8
4
read-write
UART1DIV
UART1 Clock Divide Number From UART1 Clock Source
12
4
read-write
USBDIV
USB Clock Divide Number From PLL Clock
4
4
read-write
CLKDIV4
CLK_CLKDIV4
Clock Divider Number Register 4
0x30
read-write
n
0x0
0x0
UART2DIV
UART2 Clock Divide Number From UART2 Clock Source
0
4
read-write
UART3DIV
UART3 Clock Divide Number From UART3 Clock Source
4
4
read-write
UART4DIV
UART4 Clock Divide Number From UART4 Clock Source
8
4
read-write
UART5DIV
UART5 Clock Divide Number From UART5 Clock Source
12
4
read-write
UART6DIV
UART6 Clock Divide Number From UART6 Clock Source
16
4
read-write
UART7DIV
UART7 Clock Divide Number From UART7 Clock Source
20
4
read-write
CLKDSTS
CLK_CLKDSTS
Clock Fail Detector Status Register
0x74
read-write
n
0x0
0x0
HXTFIF
HXT Clock Fail Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0.
0
1
read-write
0
External high speed crystal oscillator (HXT) clock is normal
#0
1
External high speed crystal oscillator (HXT) clock stops
#1
HXTFQIF
HXT Clock Frequency Range Detector Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0.
8
1
read-write
0
External high speed crystal oscillator (HXT) clock frequency is normal
#0
1
External high speed crystal oscillator (HXT) clock frequency is abnormal
#1
LXTFIF
LXT Clock Fail Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0.
1
1
read-write
0
External low speed crystal oscillator (LXT) clock is normal
#0
1
External low speed crystal oscillator (LXT) stops
#1
CLKOCTL
CLK_CLKOCTL
Clock Output Control Register
0x60
read-write
n
0x0
0x0
CLK1HZEN
Clock Output 1Hz Enable Bit
6
1
read-write
0
1 Hz clock output for 32.768 kHz frequency compensation Disabled
#0
1
1 Hz clock output for 32.768 kHz frequency compensation Enabled
#1
CLKOEN
Clock Output Enable Bit
4
1
read-write
0
Clock Output function Disabled
#0
1
Clock Output function Enabled
#1
DIV1EN
Clock Output Divide One Enable Bit
5
1
read-write
0
Clock Output will output clock with source frequency divided by FREQSEL
#0
1
Clock Output will output clock with source frequency
#1
FREQSEL
Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0].
0
4
read-write
CLKSEL0
CLK_CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLKSEL
HCLK Clock Source Selection (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turned on.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote : reset by power on reset\nNote: If PLL is not supported, clock source of selection '010' will be changed to HIRC. \nNote: If LXT or HXT is not supported, clock source of selection '000'or '001' will be kept previous clock selection.\nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
0
3
read-write
0
Clock source from HXT
#000
1
Clock source from LXT
#001
2
Clock source from PLL
#010
3
Clock source from LIRC
#011
7
Clock source from HIRC
#111
STCLKSEL
Cortex-M0 SysTick Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote: If LXT or HXT is not supported, clock source of selection '000', '001', or '010' will be stopped. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
3
3
read-write
0
Clock source from HXT
#000
1
Clock source from LXT
#001
2
Clock source from HXT/2
#010
3
Clock source from HCLK/2
#011
7
Clock source from HIRC/2
#111
USBDSEL
USB Device Clock Source Selection (Write Protect)\nThese bits are protected bit. It means programming this bit needs to write '59h', '16h', '88h' to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\nNote: If PLL is not supported, clock source of selection '1' will be changed to HIRC. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
8
1
read-write
0
Clock source from HIRC
#0
1
Clock source from PLL divided
#1
CLKSEL1
CLK_CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
CLKOSEL
Clock Divider Clock Source Selection\nNote: If PLL is not supported, clock source of selection '110' will be changed to HIRC.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '001' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
4
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from external low speed crystal oscillator (LXT)
#001
2
Clock source from HCLK
#010
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from internal low speed RC oscillator (LIRC)
#100
5
Clock source from internal high speed RC oscillator (HIRC)
#101
6
Clock source from PLL
#110
TMR0SEL
TIMER0 Clock Source Selection\nNote: If LXT or HXT is not supported, clock source of selection '000' or '001' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
8
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK0
#010
3
Clock source from external clock TM0 pin
#011
5
Clock source from internal low speed RC oscillator (LIRC)
#101
7
Clock source from internal high speed RC oscillator (HIRC)
#111
TMR1SEL
TIMER1 Clock Source Selection\nNote: If LXT or HXT is not supported, clock source of selection '000' or '001' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
12
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK0
#010
3
Clock source from external clock TM1 pin
#011
5
Clock source from internal low speed RC oscillator (LIRC)
#101
7
Clock source from internal high speed RC oscillator (HIRC)
#111
TMR2SEL
TIMER2 Clock Source Selection\nNote: If LXT or HXT is not supported, clock source of selection '000' or '001' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
16
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK1
#010
3
Clock source from external clock TM2 pin
#011
5
Clock source from internal low speed RC oscillator (LIRC)
#101
7
Clock source from internal high speed RC oscillator (HIRC)
#111
TMR3SEL
TIMER3 Clock Source Selection\nNote: If LXT or HXT is not supported, clock source of selection '000' or '001' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
20
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK1
#010
3
Clock source from external clock TM3 pin
#011
5
Clock source from internal low speed RC oscillator (LIRC)
#101
7
Clock source from internal high speed RC oscillator (HIRC)
#111
UART0SEL
UART0 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '001' will be changed to PCLK0.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
24
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from external low speed crystal oscillator (LXT)
#010
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK0
#100
5
Clock source from internal low speed RC oscillator (LIRC)
#101
UART1SEL
UART1 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '001' will be changed to PCLK1.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
28
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from external low speed crystal oscillator (LXT)
#010
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK1
#100
5
Clock source from internal low speed RC oscillator (LIRC)
#101
WDTSEL
Watchdog Timer Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2. Will be forced to 11 when CONFIG0[31], CONFIG0[4], CONFIG0[3] are all ones.\nNote: If LXT is not supported, clock source of selection '01' will be stopped. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
0
2
read-write
0
Reserved.
#00
1
Clock source from external low speed crystal oscillator (LXT)
#01
2
Clock source from HCLK/2048
#10
3
Clock source from internal low speed RC oscillator (LIRC)
#11
WWDTSEL
Window Watchdog Timer Clock Source Selection (Write Protect)
2
2
read-write
2
Clock source from HCLK/2048
#10
3
Clock source from internal low speed RC oscillator (LIRC)
#11
CLKSEL2
CLK_CLKSEL2
Clock Source Select Control Register 2
0x18
-1
read-write
n
0x0
0x0
ADCSEL
ADC Clock Source Selection\nNote: If PLL is not supported, clock source of selection '01' will be changed to PCLK1.\nNote: If HXT is not supported, clock source of selection '00' will be stopped. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
20
2
read-write
0
Clock source from external high speed crystal oscillator (HXT) clock
#00
1
Clock source from PLL
#01
2
Clock source from PCLK1
#10
3
Clock source from internal high speed RC oscillator (HIRC) clock
#11
BPWM0SEL
BPWM0 Clock Source Selection\nThe peripheral clock source of BPWM0 is defined by BPWM0SEL. \nNote: If PLL is not supported, clock source of selection '0' will be changed to PCLK0.\nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
8
1
read-write
0
Clock source from PLL
#0
1
Clock source from PCLK0
#1
BPWM1SEL
BPWM1 Clock Source Selection\nThe peripheral clock source of BPWM1 is defined by BPWM1SEL. \nNote: If PLL is not supported, clock source of selection '0' will be changed to PCLK1.\nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
9
1
read-write
0
Clock source from PLL
#0
1
Clock source from PCLK1
#1
PWM0SEL
PWM0 Clock Source Selection\nThe peripheral clock source of PWM0 is defined by PWM0SEL. \nNote: If PLL is not supported, clock source of selection '0' will be changed to PCLK0.\nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
0
1
read-write
0
Clock source from PLL
#0
1
Clock source from PCLK0
#1
PWM1SEL
PWM1 Clock Source Selection\nThe peripheral clock source of PWM1 is defined by PWM1SEL. \nNote: If PLL is not supported, clock source of selection '0' will be changed to PCLK1.\nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
1
1
read-write
0
Clock source from PLL
#0
1
Clock source from PCLK1
#1
QSPI0SEL
QSPI0 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '01' will be changed to PCLK0.\nNote: If HXT is not supported, clock source of selection '00' will be stopped.\nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
2
2
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#00
1
Clock source from PLL
#01
2
Clock source from PCLK0
#10
3
Clock source from internal high speed RC oscillator (HIRC)
#11
SPI0SEL
SPI0 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '01' will be changed to PCLK1.\nNote: If HXT is not supported, clock source of selection '00' will be stopped.\nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
4
2
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#00
1
Clock source from PLL
#01
2
Clock source from PCLK1
#10
3
Clock source from internal high speed RC oscillator (HIRC)
#11
CLKSEL3
CLK_CLKSEL3
Clock Source Select Control Register 3
0x1C
-1
read-write
n
0x0
0x0
UART2SEL
UART2 Clock Source Selection
Note: If PLL is not supported, clock source of selection '001' will be changed to PCLK0.
Note: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
24
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from external low speed crystal oscillator (LXT)
#010
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK0
#100
5
Clock source from internal low speed RC oscillator (LIRC)
#101
UART3SEL
UART3 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '001' will be changed to PCLK1.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
28
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from external low speed crystal oscillator (LXT)
#010
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK1
#100
5
Clock source from internal low speed RC oscillator (LIRC)
#101
UART4SEL
UART4 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '001' will be changed to PCLK0.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
16
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from external low speed crystal oscillator (LXT)
#010
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK0
#100
5
Clock source from internal low speed RC oscillator (LIRC)
#101
UART5SEL
UART5 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '001' will be changed to PCLK1.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
20
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from external low speed crystal oscillator (LXT)
#010
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK1
#100
5
Clock source from internal low speed RC oscillator (LIRC)
#101
UART6SEL
UART6 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '001' will be changed to PCLK0.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
8
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from external low speed crystal oscillator (LXT)
#010
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK0
#100
5
Clock source from internal low speed RC oscillator (LIRC)
#101
UART7SEL
UART7 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '001' will be changed to PCLK1.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
12
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from external low speed crystal oscillator (LXT)
#010
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK1
#100
5
Clock source from internal low speed RC oscillator (LIRC)
#101
HXTFSEL
CLK_HXTFSEL
HXT Filter Select Control Register
0xB4
read-write
n
0x0
0x0
HXTFSEL
HXT Filter Select \nNote: This bit should not be changed during HXT running.
0
1
read-write
0
HXT frequency is greater than12 MHz
#0
1
HXT frequency is less than or equal to 12 MHz
#1
LDOCTL
CLK_LDOCTL
LDO Control Register
0x80
read-write
n
0x0
0x0
PCLKDIV
CLK_PCLKDIV
APB Clock Divider Register
0x34
read-write
n
0x0
0x0
APB0DIV
APB0 Clock DIvider\nAPB0 clock can be divided from HCLK\nOthers: Reserved.
0
3
read-write
APB1DIV
APB1 Clock DIvider\nAPB1 clock can be divided from HCLK\nOthers: Reserved.
4
3
read-write
PLLCTL
CLK_PLLCTL
PLL Control Register
0x40
-1
read-write
n
0x0
0x0
BP
PLL Bypass Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
17
1
read-write
0
PLL is in normal mode (default)
#0
1
PLL clock output is same as PLL input clock FIN
#1
FBDIV
PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
9
read-write
INDIV
PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
9
5
read-write
OE
PLL OE (FOUT Enable) Pin Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
18
1
read-write
0
PLL FOUT Enabled
#0
1
PLL FOUT is fixed low
#1
OUTDIV
PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
14
2
read-write
PD
Power-down Mode (Write Protect)\nIf set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
16
1
read-write
0
PLL is in normal mode
#0
1
PLL is in Power-down mode (default)
#1
PLLSRC
PLL Source Clock Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
19
1
read-write
0
PLL source clock from external high-speed crystal oscillator (HXT)
#0
1
PLL source clock from 48 MHz internal high-speed oscillator (HIRC/4)
#1
STBSEL
PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
23
1
read-write
0
PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz )
#0
1
PLL stable time is 16128 PLL source clock (suitable for source clock is larger than 12 MHz)
#1
PWRCTL
CLK_PWRCTL
System Power-down Control Register
0x0
-1
read-write
n
0x0
0x0
HIRCEN
HIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
Internal high speed RC oscillator (HIRC) Disabled
#0
1
Internal high speed RC oscillator (HIRC) Enabled
#1
HXTEN
HXT Enable Bit (Write Protect)\nNote1 : reset by power on reset\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
Eexternal high speed crystal (HXT) Disabled
#0
1
External high speed crystal (HXT) Enabled
#1
HXTGAIN
HXT Gain Control Bit (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nGain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. \nOthers: Reserved \nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
20
3
read-write
0
HXT frequency is lower than from 4 MHz
#000
1
HXT frequency is from 4 MHz to 8 MHz
#001
2
HXT frequency is from 8 MHz to 12 MHz
#010
3
HXT frequency is from 12 MHz to 16 MHz
#011
4
HXT frequency is from 16 MHz to 24 MHz
#100
7
HXT frequency is from 24 MHz to 32 MHz
#111
LIRCEN
LIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
3
1
read-write
0
Internal low speed RC oscillator (LIRC) Disabled
#0
1
Internal low speed RC oscillator (LIRC) Enabled
#1
LXTEN
LXT Enable Bit (Write Protect)\nNote1 : \nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
External low speed crystal (LXT) Disabled
#0
1
External low speed crystal (LXT) Enabled
#1
LXTGAIN
LXT Gain Control Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
25
2
read-write
0
LXT Crystal ESR = 35K, CL=12.5pF
#00
2
LXT Crystal ESR = 70K, CL=12.5pF
#10
LXTSELXT
LXT Mode Selection\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register.
24
1
read-write
0
LXT work as crystal mode. PF.4 and PF.5 are configured as external low speed crystal (LXT) pins
#0
1
LXT work as external clock mode. PF.5 is configured as external clock input pin
#1
PDEN
System Power-down Enable (Write Protect)
When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.
In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. If user disable LIRC before entering power-down mode, this bit should be set after LIRC disabled 50us.
In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
Chip operating normally or chip in idle mode because of WFI command
#0
1
Chip enters Power-down mode instant or wait CPU sleep command WFI
#1
PDWKDLY
Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at external high speed crystal oscillator (HXT), and 512 clock cycles when chip works at internal high speed RC oscillator (HIRC).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
Clock cycles delay Disabled
#0
1
Clock cycles delay Enabled
#1
PDWKIEN
Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote 1: The interrupt will occur when both PDWKIF and PDWKIEN are high.\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
Power-down mode wake-up interrupt Disabled
#0
1
Power-down mode wake-up interrupt Enabled
#1
PDWKIF
Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event', it indicates that resume from Power-down mode' \nThe flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.\nNote 1: Write 1 to clear the bit to 0.\nNote 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
6
1
read-write
STATUS
CLK_STATUS
Clock Status Monitor Register
0x50
read-only
n
0x0
0x0
CLKSFAIL
Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote: Write 1 to clear the bit to 0.
7
1
read-only
0
Clock switching success
#0
1
Clock switching failure
#1
HIRCSTB
HIRC Clock Source Stable Flag (Read Only)
4
1
read-only
0
Internal high speed RC oscillator (HIRC) clock is not stable or disabled
#0
1
Internal high speed RC oscillator (HIRC) clock is stable and enabled
#1
HXTSTB
HXT Clock Source Stable Flag (Read Only)\nNote: If HXT is not supported, this bit field will be invalid. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
0
1
read-only
0
External high speed crystal oscillator (HXT) clock is not stable or disabled
#0
1
External high speed crystal oscillator (HXT) clock is stable and enabled
#1
LIRCSTB
LIRC Clock Source Stable Flag (Read Only)
3
1
read-only
0
Internal low speed RC oscillator (LIRC) clock is not stable or disabled
#0
1
Internal low speed RC oscillator (LIRC) clock is stable and enabled
#1
LXTSTB
LXT Clock Source Stable Flag (Read Only)\nNote: If LXT is not supported, this bit field will be invalid. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
1
1
read-only
0
External low speed crystal oscillator (LXT) clock is not stable or disabled
#0
1
External low speed crystal oscillator (LXT) clock is stabled and enabled
#1
PLLSTB
Internal PLL Clock Source Stable Flag (Read Only)\nNote: If PLL is not supported, this bit field will be invalid. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
2
1
read-only
0
Internal PLL clock is not stable or disabled
#0
1
Internal PLL clock is stable and enabled
#1
CRC
CRC Register Map
CRC
0x0
0x0
0x10
registers
n
CHECKSUM
CRC_CHECKSUM
CRC Checksum Register
0xC
-1
read-only
n
0x0
0x0
CHECKSUM
CRC Checksum Results\nThis field indicates the CRC checksum result.
0
32
read-only
CTL
CRC_CTL
CRC Control Register
0x0
-1
read-write
n
0x0
0x0
CHKSFMT
Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
27
1
read-write
0
1's complement for CRC checksum Disabled
#0
1
1's complement for CRC checksum Enabled
#1
CHKSINIT
Checksum Initialization\nNote: This bit will be cleared automatically.
1
1
read-write
0
No effect
#0
1
Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value
#1
CHKSREV
Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
25
1
read-write
0
Bit order reverse for CRC checksum Disabled
#0
1
Bit order reverse for CRC checksum Enabled
#1
CRCEN
CRC Channel Enable Bit
0
1
read-write
0
No effect
#0
1
CRC operation Enabled
#1
CRCMODE
CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode.
30
2
read-write
0
CRC-CCITT Polynomial mode
#00
1
CRC-8 Polynomial mode
#01
2
CRC-16 Polynomial mode
#10
3
CRC-32 Polynomial mode
#11
DATFMT
Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DAT register.
26
1
read-write
0
1's complement for CRC writes data in Disabled
#0
1
1's complement for CRC writes data in Enabled
#1
DATLEN
CPU Write Data Length
This field indicates the write data length.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
28
2
read-write
0
Data length is 8-bit mode
#00
1
Data length is 16-bit mode.\nData length is 32-bit mode
#01
DATREV
Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
24
1
read-write
0
Bit order reversed for CRC write data in Disabled
#0
1
Bit order reversed for CRC write data in Enabled (per byte)
#1
DAT
CRC_DAT
CRC Write Data Register
0x4
read-write
n
0x0
0x0
DATA
CRC Write Data Bits
User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
0
32
read-write
SEED
CRC_SEED
CRC Seed Register
0x8
-1
read-write
n
0x0
0x0
SEED
CRC Seed Value\nThis field indicates the CRC seed value.\nNote: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
0
32
read-write
EBI
EBI Register Map
EBI
0x0
0x0
0x8
registers
n
0x10
0x8
registers
n
CTL0
EBI_CTL0
External Bus Interface Bank0 Control Register
0x0
read-write
n
0x0
0x0
ADSEPEN
EBI Address/Data Bus Separating Mode Enable Bit
3
1
read-write
0
Address/Data Bus Separating Mode Disabled
#0
1
Address/Data Bus Separating Mode Enabled
#1
CACCESS
Continuous Data Access Mode\nWhen Continuous access mode is enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
4
1
read-write
0
Continuous data access mode Disabled
#0
1
Continuous data access mode Enabled
#1
CSPOLINV
Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS).
2
1
read-write
0
Chip select pin (EBI_nCS) is active low
#0
1
Chip select pin (EBI_nCS) is active high
#1
DW16
EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit.
1
1
read-write
0
EBI data width is 8-bit
#0
1
EBI data width is 16-bit
#1
EN
EBI Enable Bit\nThis bit is the functional enable bit for EBI.
0
1
read-write
0
EBI function Disabled
#0
1
EBI function Enabled
#1
MCLKDIV
External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
8
3
read-write
0
HCLK/1
#000
1
HCLK/2
#001
2
HCLK/4
#010
3
HCLK/8
#011
4
HCLK/16
#100
5
HCLK/32
#101
6
HCLK/64
#110
7
HCLK/128
#111
TALE
Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field is only available in EBI_CTL0 register.
16
3
read-write
WBUFEN
EBI Write Buffer Enable Bit\nNote: This bit is only available in EBI_CTL0 register.
24
1
read-write
0
EBI write buffer Disabled
#0
1
EBI write buffer Enabled
#1
CTL1
EBI_CTL1
External Bus Interface Bank1 Control Register
0x10
read-write
n
0x0
0x0
TCTL0
EBI_TCTL0
External Bus Interface Bank0 Timing Control Register
0x4
read-write
n
0x0
0x0
R2R
Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nNote: When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
24
4
read-write
RAHDOFF
Access Hold Time Disable Control When Read
22
1
read-write
0
Data Access Hold Time (tAHD) during EBI reading Enabled
#0
1
Data Access Hold Time (tAHD) during EBI reading Disabled
#1
TACC
EBI Data Access Time\nTACC defines data access time (tACC).
3
5
read-write
TAHD
EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD).
8
3
read-write
W2X
Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nNote: When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state.
12
4
read-write
WAHDOFF
Access Hold Time Disable Control When Write
23
1
read-write
0
Data Access Hold Time (tAHD) during EBI writing Enabled
#0
1
Data Access Hold Time (tAHD) during EBI writing Disabled
#1
TCTL1
EBI_TCTL1
External Bus Interface Bank1 Timing Control Register
0x14
read-write
n
0x0
0x0
FMC
FMC Register Map
FMC
0x0
0x0
0x1C
registers
n
0x40
0x4
registers
n
0x80
0x10
registers
n
0xC0
0x8
registers
n
DFBA
FMC_DFBA
Data Flash Base Address
0x14
read-only
n
0x0
0x0
DFBA
Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
0
32
read-only
FTCTL
FMC_FTCTL
Flash Access Time Control Register
0x18
read-write
n
0x0
0x0
BBOFF
Flash Branch Buffer Disable Control (Write Protect)\nNote 1: This bit is write-protected. Refer to the SYS_REGLCTL register.\nNote 2: Only suppoted in 16/32/64/128 Kbytes Flash.
7
1
read-write
0
Flash Branch Buffer function Enabled (default)
#0
1
Flash Branch Buffer function Disabled
#1
CACHEINV
Flash Cache Invalidation (Write Protect)\nNote 1: Write 1 to start cache invalidation. The value will be changed to 0 once the process is finished.\nNote 2: This bit is write-protected. Refer to the SYS_REGLCTL register.\nNote 3: Only supported in 256/512 Kbytes Flash.
9
1
read-write
0
Flash Cache Invalidation finished (default)
#0
1
Flash Cache Invalidation
#1
FOM
Frequency Optimization Mode (Write Protect)\nThe M031/M032 series support adjustable Flash access timing to optimize the Flash access cycles in different system working frequency.\nFor 16/32/64/128 Kbytes Flash:\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
4
3
read-write
0
Frequency is less than or equal to 48 MHz
#000
1
Frequency is less than or equal to 24 MHz.\nFrequency is less than or equal to 12 MHz
#001
2
Frequency is less than or equal to 36 MHz
#010
3
Frequency is less than or equal to 60 MHz
#011
ISPADDR
FMC_ISPADDR
ISP Address Register
0x4
read-write
n
0x0
0x0
ISPADDR
ISP Address\nThe M031/M032 series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. For CRC32 Checksum Calculation command, this field is the Flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation.\n16/32/64/128 Kbytes Flash:\nISPADR[8:0] must be kept all 0 for Vector Page Re-map Command.\n256/512 Kbytes Flash:\nISPADR[11:0] must be kept all 0 for Vector Page Re-map Command.
0
32
read-write
ISPCMD
FMC_ISPCMD
ISP Command Register
0xC
read-write
n
0x0
0x0
CMD
ISP CMD\nISP command table is shown below:\nThe other commands are invalid.
0
7
read-write
0
Flash Read
0x00
4
Read Unique ID
0x04
8
Read All One
0x08
11
Read Company ID
0x0b
12
Read Device ID
0x0c
13
Read CRC32 Checksum
0x0d
33
Flash 32-bit Program
0x21
34
Flash Page Erase
0x22
35
Flash APROM Bank Erase
0x23
39
Flash Multi-Word Program
0x27
40
Run All One
0x28
44
APROM Address Operation Model Selection
0x2c
45
Run CRC32 Checksum Calculation
0x2d
46
Vector Remap
0x2e
97
Flash 64-bit Program
0x61
ISPCTL
FMC_ISPCTL
ISP Control Register
0x0
read-write
n
0x0
0x0
APUEN
APROM Update Enable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
3
1
read-write
0
APROM cannot be updated when the chip runs in APROM
#0
1
APROM can be updated when the chip runs in APROM
#1
BS
Boot Selection (Write Protect)
Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
Booting from APROM
#0
1
Booting from LDROM
#1
CFGUEN
CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
CONFIG cannot be updated
#0
1
CONFIG can be updated
#1
INTEN
ISP Interrupt Enabled Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.Before use INT,user needs to clear the INTFLAG(FMC_ISPSTS[8]) make sure INT happen at correct time.
24
1
read-write
0
ISP INT Disabled
#0
1
ISP INT Enabled
#1
ISPEN
ISP Enable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
0
1
read-write
1
ISP function Enabled
#1
ISPFF
ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\nAPROM writes to itself if APUEN is set to 0.\nLDROM writes to itself if LDUEN is set to 0.\nCONFIG is erased/programmed if CFGUEN is set to 0.\nSPROM is erased/programmed if SPUEN is set to 0\nSPROM is programmed at SPROM secured mode.\nPage Erase command at LOCK mode with ICE connection\nErase or Program command at brown-out detected\nDestination address is illegal, such as over an available range.\nInvalid ISP commands\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
6
1
read-write
LDUEN
LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated
#1
SPUEN
SPROM Update Enable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
SPROM cannot be updated
#0
1
SPROM can be updated
#1
ISPDAT
FMC_ISPDAT
ISP Data Register
0x8
read-write
n
0x0
0x0
ISPDAT
ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
0
32
read-write
ISPSTS
FMC_ISPSTS
ISP Status Register
0x40
read-write
n
0x0
0x0
ALLONE
Flash All-one Verification Flag
This bit is set by hardware if all of Flash bits are 1, and cleared if Flash bits are not all 1 after 'Run Flash All-One Verification' complete this bit can also be cleared by writing 1.
7
1
read-write
0
Flash bits are not all 1 after'Run Flash All-One Verification' complete
#0
1
All of Flash bits are 1 after'Run Flash All-One Verification' complete
#1
CBS
Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
1
2
read-only
0
LDROM with IAP mode
#00
1
LDROM without IAP mode
#01
2
APROM with IAP mode
#10
3
APROM without IAP mode
#11
FBS
Flash Bank Select Indicator\nThis bit indicates which APROM address model is selected to boot.\nNote: Only supported in 256/512 Kbytes Flash.
30
1
read-write
0
Address model OP0 is selected to boot
#0
1
Address model OP1 is selected to boot
#1
INTFLAG
ISP Command Finish Interrupt Flag\nNote: Only supported in 256/512 Kbytes Flash.
8
1
read-write
0
ISP Not Finished
#0
1
ISP done or ISPFF set
#1
ISPBUSY
ISP BUSY (Read Only)
0
1
read-only
0
ISP operation is finished
#0
1
ISP operation is busy
#1
ISPFF
ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\nAPROM writes to itself if APUEN is set to 0.\nLDROM writes to itself if LDUEN is set to 0.\nCONFIG is erased/programmed if CFGUEN is set to 0.\nSPROM is erased/programmed if SPUEN is set to 0\nSPROM is programmed at SPROM secured mode.\nPage Erase command at LOCK mode with ICE connection\nErase or Program command at brown-out detected\nDestination address is illegal, such as over an available range.\nInvalid ISP commands
6
1
read-write
PGFF
Flash Program with Fast Verification Flag (Read Only)\nThis bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP Flash erase or ISP read CID operation
5
1
read-only
0
Flash Program is successful
#0
1
Flash Program is failed. Program data is different with data in the Flash memory
#1
SCODE
Security Code Active Flag
This bit is set to 1 by hardware when detecting SPROM secured code is active at Flash initialization, or software writes 1 to this bit to make secured code active this bit is only cleared by SPROM page erase operation.
31
1
read-write
0
SPROM secured code is inactive
#0
1
SPROM secured code is active
#1
VECMAP
Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}, except SPROM.\nVECMAP [18:12] should be 0.
9
21
read-only
ISPTRG
FMC_ISPTRG
ISP Trigger Control Register
0x10
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
0
1
read-write
0
ISP operation is finished
#0
1
ISP is progressed.Note: This bit is write-protected. Refer to the SYS_REGLCTL register
#1
MPADDR
FMC_MPADDR
ISP Multi-program Address Register
0xC4
read-only
n
0x0
0x0
MPADDR
ISP Multi-word Program Address\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete.
0
32
read-only
MPDAT0
FMC_MPDAT0
ISP Data0 Register
0x80
read-write
n
0x0
0x0
ISPDAT0
ISP Data 0\nThis register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data.
0
32
read-write
MPDAT1
FMC_MPDAT1
ISP Data1 Register
0x84
read-write
n
0x0
0x0
ISPDAT1
ISP Data 1\nThis register is the second 32-bit data for 64-bit/multi-word programming.
0
32
read-write
MPDAT2
FMC_MPDAT2
ISP Data2 Register
0x88
read-write
n
0x0
0x0
ISPDAT2
ISP Data 2\nThis register is the third 32-bit data for multi-word programming.
0
32
read-write
MPDAT3
FMC_MPDAT3
ISP Data3 Register
0x8C
read-write
n
0x0
0x0
ISPDAT3
ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming.
0
32
read-write
MPSTS
FMC_MPSTS
ISP Multi-program Status Register
0xC0
read-only
n
0x0
0x0
D0
ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto cleared to 0 when the FMC_MPDAT0 data is programmed to Flash complete.
4
1
read-only
0
FMC_MPDAT0 register is empty, or program to Flash complete
#0
1
FMC_MPDAT0 register has been written, and not program to Flash complete
#1
D1
ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto cleared to 0 when the FMC_MPDAT1 data is programmed to Flash complete.
5
1
read-only
0
FMC_MPDAT1 register is empty, or program to Flash complete
#0
1
FMC_MPDAT1 register has been written, and not program to Flash complete
#1
D2
ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto cleared to 0 when the FMC_MPDAT2 data is programmed to Flash complete.
6
1
read-only
0
FMC_MPDAT2 register is empty, or program to Flash complete
#0
1
FMC_MPDAT2 register has been written, and not program to Flash complete
#1
D3
ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto cleared to 0 when the FMC_MPDAT3 data is programmed to Flash complete.
7
1
read-only
0
FMC_MPDAT3 register is empty, or program to Flash complete
#0
1
FMC_MPDAT3 register has been written, and not program to Flash complete
#1
ISPFF
ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\nAPROM writes to itself if APUEN is set to 0.\nLDROM writes to itself if LDUEN is set to 0.\nCONFIG is erased/programmed if CFGUEN is set to 0.\nPage Erase command at LOCK mode with ICE connection\nErase or Program command at brown-out detected\nDestination address is illegal, such as over an available range.\nInvalid ISP commands
2
1
read-only
MPBUSY
ISP Multi-word Program Busy Flag (Read Only)\nWrite 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]).
0
1
read-only
0
ISP Multi-Word program operation is finished
#0
1
ISP Multi-Word program operation is progressed
#1
PPGO
ISP Multi-program Status (Read Only)
1
1
read-only
0
ISP multi-word program operation is not active
#0
1
ISP multi-word program operation is in progress
#1
GPIO
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
0x100
0x24
registers
n
0x140
0x24
registers
n
0x180
0x24
registers
n
0x1C0
0x24
registers
n
0x40
0x24
registers
n
0x440
0x4
registers
n
0x80
0x24
registers
n
0x800
0xBC
registers
n
0x8C0
0x84
registers
n
0x980
0x4
registers
n
0x9D0
0x20
registers
n
0xC0
0x24
registers
n
DBCTL
GPIO_DBCTL
Interrupt De-bounce Control Register
0x440
-1
read-write
n
0x0
0x0
DBCLKSEL
De-bounce Sampling Cycle Selection
0
4
read-write
0
Sample interrupt input once per 1 clocks
#0000
1
Sample interrupt input once per 2 clocks
#0001
2
Sample interrupt input once per 4 clocks
#0010
3
Sample interrupt input once per 8 clocks
#0011
4
Sample interrupt input once per 16 clocks
#0100
5
Sample interrupt input once per 32 clocks
#0101
6
Sample interrupt input once per 64 clocks
#0110
7
Sample interrupt input once per 128 clocks
#0111
8
Sample interrupt input once per 256 clocks
#1000
9
Sample interrupt input once per 2*256 clocks
#1001
10
Sample interrupt input once per 4*256 clocks
#1010
11
Sample interrupt input once per 8*256 clocks
#1011
12
Sample interrupt input once per 16*256 clocks
#1100
13
Sample interrupt input once per 32*256 clocks
#1101
14
Sample interrupt input once per 64*256 clocks
#1110
15
Sample interrupt input once per 128*256 clocks
#1111
DBCLKSRC
De-bounce Counter Clock Source Selection
4
1
read-write
0
De-bounce counter clock source is the HCLK
#0
1
De-bounce counter clock source is the 38.4 kHz internal low speed RC oscillator (LIRC)
#1
ICLKON
Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern.
5
1
read-write
0
Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1
#0
1
All I/O pins edge detection circuit is always active after reset
#1
PA0_PDIO
PA0_PDIO
GPIO PA.n Pin Data Input/Output Register
0x800
read-write
n
0x0
0x0
PDIO
GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example, writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]), reading PA0_PDIO will return the value of PIN (PA_PIN[0]).\nNote 1: The writing operation will not be affected by register DATMSK (Px_DATMSK[n]).\nNote 2: The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
0
1
read-write
0
Corresponding GPIO pin set to low
#0
1
Corresponding GPIO pin set to high
#1
PA10_PDIO
PA10_PDIO
GPIO PA.n Pin Data Input/Output Register
0x828
read-write
n
0x0
0x0
PA11_PDIO
PA11_PDIO
GPIO PA.n Pin Data Input/Output Register
0x82C
read-write
n
0x0
0x0
PA12_PDIO
PA12_PDIO
GPIO PA.n Pin Data Input/Output Register
0x830
read-write
n
0x0
0x0
PA13_PDIO
PA13_PDIO
GPIO PA.n Pin Data Input/Output Register
0x834
read-write
n
0x0
0x0
PA14_PDIO
PA14_PDIO
GPIO PA.n Pin Data Input/Output Register
0x838
read-write
n
0x0
0x0
PA15_PDIO
PA15_PDIO
GPIO PA.n Pin Data Input/Output Register
0x83C
read-write
n
0x0
0x0
PA1_PDIO
PA1_PDIO
GPIO PA.n Pin Data Input/Output Register
0x804
read-write
n
0x0
0x0
PA2_PDIO
PA2_PDIO
GPIO PA.n Pin Data Input/Output Register
0x808
read-write
n
0x0
0x0
PA3_PDIO
PA3_PDIO
GPIO PA.n Pin Data Input/Output Register
0x80C
read-write
n
0x0
0x0
PA4_PDIO
PA4_PDIO
GPIO PA.n Pin Data Input/Output Register
0x810
read-write
n
0x0
0x0
PA5_PDIO
PA5_PDIO
GPIO PA.n Pin Data Input/Output Register
0x814
read-write
n
0x0
0x0
PA6_PDIO
PA6_PDIO
GPIO PA.n Pin Data Input/Output Register
0x818
read-write
n
0x0
0x0
PA7_PDIO
PA7_PDIO
GPIO PA.n Pin Data Input/Output Register
0x81C
read-write
n
0x0
0x0
PA8_PDIO
PA8_PDIO
GPIO PA.n Pin Data Input/Output Register
0x820
read-write
n
0x0
0x0
PA9_PDIO
PA9_PDIO
GPIO PA.n Pin Data Input/Output Register
0x824
read-write
n
0x0
0x0
PA_DATMSK
PA_DATMSK
PA Data Output Write Mask
0xC
read-write
n
0x0
0x0
DATMSK0
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
0
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK1
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
1
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK10
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
10
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK11
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
11
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK12
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
12
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK13
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
13
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK14
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
14
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK15
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
15
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK2
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
2
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK3
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
3
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK4
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
4
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK5
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
5
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK6
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
6
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK7
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
7
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK8
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
8
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK9
Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
9
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
PA_DBEN
PA_DBEN
PA De-bounce Enable Control Register
0x14
read-write
n
0x0
0x0
DBEN0
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
0
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN1
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
1
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN10
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
10
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN11
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
11
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN12
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
12
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN13
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
13
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN14
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
14
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN15
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
15
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN2
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
2
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN3
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
3
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN4
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
4
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN5
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
5
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN6
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
6
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN7
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
7
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN8
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
8
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN9
Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
9
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
PA_DINOFF
PA_DINOFF
PA Digital Input Path Disable Control
0x4
read-write
n
0x0
0x0
DINOFF0
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
16
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF1
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
17
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF10
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
26
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF11
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
27
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF12
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
28
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF13
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
29
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF14
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
30
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF15
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
31
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF2
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
18
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF3
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
19
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF4
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
20
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF5
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
21
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF6
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
22
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF7
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
23
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF8
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
24
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF9
Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
25
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
PA_DOUT
PA_DOUT
PA Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
0
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
1
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT10
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
10
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT11
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
11
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT12
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
12
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT13
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
13
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT14
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
14
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT15
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
15
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
2
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
3
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
4
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
5
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
6
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
7
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT8
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
8
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT9
Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
9
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
PA_INTEN
PA_INTEN
PA Interrupt Enable Control Register
0x1C
read-write
n
0x0
0x0
FLIEN0
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
0
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN1
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
1
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN10
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
10
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN11
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
11
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN12
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
12
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN13
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
13
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN14
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
14
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN15
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
15
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN2
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
2
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN3
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
3
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN4
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
4
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN5
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
5
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN6
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
6
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN7
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
7
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN8
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
8
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN9
Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
9
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
RHIEN0
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
16
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN1
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
17
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN10
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
26
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN11
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
27
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN12
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
28
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN13
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
29
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN14
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
30
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN15
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
31
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN2
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
18
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN3
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
19
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN4
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
20
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN5
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
21
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN6
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
22
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN7
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
23
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN8
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
24
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN9
Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
25
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
PA_INTSRC
PA_INTSRC
PA Interrupt Source Flag
0x20
read-write
n
0x0
0x0
INTSRC0
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
0
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC1
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
1
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC10
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
10
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC11
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
11
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC12
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
12
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC13
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
13
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC14
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
14
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC15
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
15
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC2
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
2
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC3
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
3
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC4
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
4
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC5
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
5
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC6
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
6
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC7
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
7
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC8
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
8
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC9
Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
9
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
PA_INTTYPE
PA_INTTYPE
PA Interrupt Trigger Type Control
0x18
read-write
n
0x0
0x0
TYPE0
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
0
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE1
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
1
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE10
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
10
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE11
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
11
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE12
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
12
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE13
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
13
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE14
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
14
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE15
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
15
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE2
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
2
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE3
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
3
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE4
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
4
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE5
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
5
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE6
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
6
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE7
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
7
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE8
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
8
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE9
Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
9
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
PA_MODE
PA_MODE
PA I/O Mode Control
0x0
read-write
n
0x0
0x0
MODE0
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
0
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE1
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
2
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE10
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
20
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE11
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
22
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE12
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
24
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE13
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
26
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE14
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
28
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE15
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
30
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE2
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
4
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE3
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
6
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE4
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
8
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE5
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
10
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE6
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
12
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE7
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
14
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE8
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
16
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE9
Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote 2: \nThe PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
18
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
PA_PIN
PA_PIN
PA Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
0
1
read-only
PIN1
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
1
1
read-only
PIN10
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
10
1
read-only
PIN11
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
11
1
read-only
PIN12
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
12
1
read-only
PIN13
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
13
1
read-only
PIN14
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
14
1
read-only
PIN15
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
15
1
read-only
PIN2
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
2
1
read-only
PIN3
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
3
1
read-only
PIN4
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
4
1
read-only
PIN5
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
5
1
read-only
PIN6
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
6
1
read-only
PIN7
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
7
1
read-only
PIN8
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
8
1
read-only
PIN9
Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
The PC.15/PF.12~13/PG.0~1,5~8/PH.0~3,12~15 pin is ignored.
9
1
read-only
PB0_PDIO
PB0_PDIO
GPIO PB.n Pin Data Input/Output Register
0x840
read-write
n
0x0
0x0
PB10_PDIO
PB10_PDIO
GPIO PB.n Pin Data Input/Output Register
0x868
read-write
n
0x0
0x0
PB11_PDIO
PB11_PDIO
GPIO PB.n Pin Data Input/Output Register
0x86C
read-write
n
0x0
0x0
PB12_PDIO
PB12_PDIO
GPIO PB.n Pin Data Input/Output Register
0x870
read-write
n
0x0
0x0
PB13_PDIO
PB13_PDIO
GPIO PB.n Pin Data Input/Output Register
0x874
read-write
n
0x0
0x0
PB14_PDIO
PB14_PDIO
GPIO PB.n Pin Data Input/Output Register
0x878
read-write
n
0x0
0x0
PB15_PDIO
PB15_PDIO
GPIO PB.n Pin Data Input/Output Register
0x87C
read-write
n
0x0
0x0
PB1_PDIO
PB1_PDIO
GPIO PB.n Pin Data Input/Output Register
0x844
read-write
n
0x0
0x0
PB2_PDIO
PB2_PDIO
GPIO PB.n Pin Data Input/Output Register
0x848
read-write
n
0x0
0x0
PB3_PDIO
PB3_PDIO
GPIO PB.n Pin Data Input/Output Register
0x84C
read-write
n
0x0
0x0
PB4_PDIO
PB4_PDIO
GPIO PB.n Pin Data Input/Output Register
0x850
read-write
n
0x0
0x0
PB5_PDIO
PB5_PDIO
GPIO PB.n Pin Data Input/Output Register
0x854
read-write
n
0x0
0x0
PB6_PDIO
PB6_PDIO
GPIO PB.n Pin Data Input/Output Register
0x858
read-write
n
0x0
0x0
PB7_PDIO
PB7_PDIO
GPIO PB.n Pin Data Input/Output Register
0x85C
read-write
n
0x0
0x0
PB8_PDIO
PB8_PDIO
GPIO PB.n Pin Data Input/Output Register
0x860
read-write
n
0x0
0x0
PB9_PDIO
PB9_PDIO
GPIO PB.n Pin Data Input/Output Register
0x864
read-write
n
0x0
0x0
PB_DATMSK
PB_DATMSK
PB Data Output Write Mask
0x4C
read-write
n
0x0
0x0
PB_DBEN
PB_DBEN
PB De-bounce Enable Control Register
0x54
read-write
n
0x0
0x0
PB_DINOFF
PB_DINOFF
PB Digital Input Path Disable Control
0x44
read-write
n
0x0
0x0
PB_DOUT
PB_DOUT
PB Data Output Value
0x48
read-write
n
0x0
0x0
PB_INTEN
PB_INTEN
PB Interrupt Enable Control Register
0x5C
read-write
n
0x0
0x0
PB_INTSRC
PB_INTSRC
PB Interrupt Source Flag
0x60
read-write
n
0x0
0x0
PB_INTTYPE
PB_INTTYPE
PB Interrupt Trigger Type Control
0x58
read-write
n
0x0
0x0
PB_MODE
PB_MODE
PB I/O Mode Control
0x40
read-write
n
0x0
0x0
PB_PIN
PB_PIN
PB Pin Value
0x50
read-write
n
0x0
0x0
PC0_PDIO
PC0_PDIO
GPIO PC.n Pin Data Input/Output Register
0x880
read-write
n
0x0
0x0
PC10_PDIO
PC10_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8A8
read-write
n
0x0
0x0
PC11_PDIO
PC11_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8AC
read-write
n
0x0
0x0
PC12_PDIO
PC12_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8B0
read-write
n
0x0
0x0
PC13_PDIO
PC13_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8B4
read-write
n
0x0
0x0
PC14_PDIO
PC14_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8B8
read-write
n
0x0
0x0
PC1_PDIO
PC1_PDIO
GPIO PC.n Pin Data Input/Output Register
0x884
read-write
n
0x0
0x0
PC2_PDIO
PC2_PDIO
GPIO PC.n Pin Data Input/Output Register
0x888
read-write
n
0x0
0x0
PC3_PDIO
PC3_PDIO
GPIO PC.n Pin Data Input/Output Register
0x88C
read-write
n
0x0
0x0
PC4_PDIO
PC4_PDIO
GPIO PC.n Pin Data Input/Output Register
0x890
read-write
n
0x0
0x0
PC5_PDIO
PC5_PDIO
GPIO PC.n Pin Data Input/Output Register
0x894
read-write
n
0x0
0x0
PC6_PDIO
PC6_PDIO
GPIO PC.n Pin Data Input/Output Register
0x898
read-write
n
0x0
0x0
PC7_PDIO
PC7_PDIO
GPIO PC.n Pin Data Input/Output Register
0x89C
read-write
n
0x0
0x0
PC8_PDIO
PC8_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8A0
read-write
n
0x0
0x0
PC9_PDIO
PC9_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8A4
read-write
n
0x0
0x0
PC_DATMSK
PC_DATMSK
PC Data Output Write Mask
0x8C
read-write
n
0x0
0x0
PC_DBEN
PC_DBEN
PC De-bounce Enable Control Register
0x94
read-write
n
0x0
0x0
PC_DINOFF
PC_DINOFF
PC Digital Input Path Disable Control
0x84
read-write
n
0x0
0x0
PC_DOUT
PC_DOUT
PC Data Output Value
0x88
read-write
n
0x0
0x0
PC_INTEN
PC_INTEN
PC Interrupt Enable Control Register
0x9C
read-write
n
0x0
0x0
PC_INTSRC
PC_INTSRC
PC Interrupt Source Flag
0xA0
read-write
n
0x0
0x0
PC_INTTYPE
PC_INTTYPE
PC Interrupt Trigger Type Control
0x98
read-write
n
0x0
0x0
PC_MODE
PC_MODE
PC I/O Mode Control
0x80
read-write
n
0x0
0x0
PC_PIN
PC_PIN
PC Pin Value
0x90
read-write
n
0x0
0x0
PD0_PDIO
PD0_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8C0
read-write
n
0x0
0x0
PD10_PDIO
PD10_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8E8
read-write
n
0x0
0x0
PD11_PDIO
PD11_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8EC
read-write
n
0x0
0x0
PD12_PDIO
PD12_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8F0
read-write
n
0x0
0x0
PD13_PDIO
PD13_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8F4
read-write
n
0x0
0x0
PD14_PDIO
PD14_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8F8
read-write
n
0x0
0x0
PD15_PDIO
PD15_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8FC
read-write
n
0x0
0x0
PD1_PDIO
PD1_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8C4
read-write
n
0x0
0x0
PD2_PDIO
PD2_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8C8
read-write
n
0x0
0x0
PD3_PDIO
PD3_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8CC
read-write
n
0x0
0x0
PD4_PDIO
PD4_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8D0
read-write
n
0x0
0x0
PD5_PDIO
PD5_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8D4
read-write
n
0x0
0x0
PD6_PDIO
PD6_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8D8
read-write
n
0x0
0x0
PD7_PDIO
PD7_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8DC
read-write
n
0x0
0x0
PD8_PDIO
PD8_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8E0
read-write
n
0x0
0x0
PD9_PDIO
PD9_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8E4
read-write
n
0x0
0x0
PD_DATMSK
PD_DATMSK
PD Data Output Write Mask
0xCC
read-write
n
0x0
0x0
PD_DBEN
PD_DBEN
PD De-bounce Enable Control Register
0xD4
read-write
n
0x0
0x0
PD_DINOFF
PD_DINOFF
PD Digital Input Path Disable Control
0xC4
read-write
n
0x0
0x0
PD_DOUT
PD_DOUT
PD Data Output Value
0xC8
read-write
n
0x0
0x0
PD_INTEN
PD_INTEN
PD Interrupt Enable Control Register
0xDC
read-write
n
0x0
0x0
PD_INTSRC
PD_INTSRC
PD Interrupt Source Flag
0xE0
read-write
n
0x0
0x0
PD_INTTYPE
PD_INTTYPE
PD Interrupt Trigger Type Control
0xD8
read-write
n
0x0
0x0
PD_MODE
PD_MODE
PD I/O Mode Control
0xC0
read-write
n
0x0
0x0
PD_PIN
PD_PIN
PD Pin Value
0xD0
read-write
n
0x0
0x0
PE0_PDIO
PE0_PDIO
GPIO PE.n Pin Data Input/Output Register
0x900
read-write
n
0x0
0x0
PE10_PDIO
PE10_PDIO
GPIO PE.n Pin Data Input/Output Register
0x928
read-write
n
0x0
0x0
PE11_PDIO
PE11_PDIO
GPIO PE.n Pin Data Input/Output Register
0x92C
read-write
n
0x0
0x0
PE12_PDIO
PE12_PDIO
GPIO PE.n Pin Data Input/Output Register
0x930
read-write
n
0x0
0x0
PE13_PDIO
PE13_PDIO
GPIO PE.n Pin Data Input/Output Register
0x934
read-write
n
0x0
0x0
PE14_PDIO
PE14_PDIO
GPIO PE.n Pin Data Input/Output Register
0x938
read-write
n
0x0
0x0
PE15_PDIO
PE15_PDIO
GPIO PE.n Pin Data Input/Output Register
0x93C
read-write
n
0x0
0x0
PE1_PDIO
PE1_PDIO
GPIO PE.n Pin Data Input/Output Register
0x904
read-write
n
0x0
0x0
PE2_PDIO
PE2_PDIO
GPIO PE.n Pin Data Input/Output Register
0x908
read-write
n
0x0
0x0
PE3_PDIO
PE3_PDIO
GPIO PE.n Pin Data Input/Output Register
0x90C
read-write
n
0x0
0x0
PE4_PDIO
PE4_PDIO
GPIO PE.n Pin Data Input/Output Register
0x910
read-write
n
0x0
0x0
PE5_PDIO
PE5_PDIO
GPIO PE.n Pin Data Input/Output Register
0x914
read-write
n
0x0
0x0
PE6_PDIO
PE6_PDIO
GPIO PE.n Pin Data Input/Output Register
0x918
read-write
n
0x0
0x0
PE7_PDIO
PE7_PDIO
GPIO PE.n Pin Data Input/Output Register
0x91C
read-write
n
0x0
0x0
PE8_PDIO
PE8_PDIO
GPIO PE.n Pin Data Input/Output Register
0x920
read-write
n
0x0
0x0
PE9_PDIO
PE9_PDIO
GPIO PE.n Pin Data Input/Output Register
0x924
read-write
n
0x0
0x0
PE_DATMSK
PE_DATMSK
PE Data Output Write Mask
0x10C
read-write
n
0x0
0x0
PE_DBEN
PE_DBEN
PE De-bounce Enable Control Register
0x114
read-write
n
0x0
0x0
PE_DINOFF
PE_DINOFF
PE Digital Input Path Disable Control
0x104
read-write
n
0x0
0x0
PE_DOUT
PE_DOUT
PE Data Output Value
0x108
read-write
n
0x0
0x0
PE_INTEN
PE_INTEN
PE Interrupt Enable Control Register
0x11C
read-write
n
0x0
0x0
PE_INTSRC
PE_INTSRC
PE Interrupt Source Flag
0x120
read-write
n
0x0
0x0
PE_INTTYPE
PE_INTTYPE
PE Interrupt Trigger Type Control
0x118
read-write
n
0x0
0x0
PE_MODE
PE_MODE
PE I/O Mode Control
0x100
read-write
n
0x0
0x0
PE_PIN
PE_PIN
PE Pin Value
0x110
read-write
n
0x0
0x0
PFn_PDIO
PFn_PDIO
GPIO PF.n Pin Data Input/Output Register
0x940
read-write
n
0x0
0x0
PF_DATMSK
PF_DATMSK
PF Data Output Write Mask
0x14C
read-write
n
0x0
0x0
PF_DBEN
PF_DBEN
PF De-bounce Enable Control Register
0x154
read-write
n
0x0
0x0
PF_DINOFF
PF_DINOFF
PF Digital Input Path Disable Control
0x144
read-write
n
0x0
0x0
PF_DOUT
PF_DOUT
PF Data Output Value
0x148
read-write
n
0x0
0x0
PF_INTEN
PF_INTEN
PF Interrupt Enable Control Register
0x15C
read-write
n
0x0
0x0
PF_INTSRC
PF_INTSRC
PF Interrupt Source Flag
0x160
read-write
n
0x0
0x0
PF_INTTYPE
PF_INTTYPE
PF Interrupt Trigger Type Control
0x158
read-write
n
0x0
0x0
PF_MODE
PF_MODE
PF I/O Mode Control
0x140
read-write
n
0x0
0x0
PF_PIN
PF_PIN
PF Pin Value
0x150
read-write
n
0x0
0x0
PGn_PDIO
PGn_PDIO
GPIO PG.n Pin Data Input/Output Register
0x980
read-write
n
0x0
0x0
PG_DATMSK
PG_DATMSK
PG Data Output Write Mask
0x18C
read-write
n
0x0
0x0
PG_DBEN
PG_DBEN
PG De-bounce Enable Control Register
0x194
read-write
n
0x0
0x0
PG_DINOFF
PG_DINOFF
PG Digital Input Path Disable Control
0x184
read-write
n
0x0
0x0
PG_DOUT
PG_DOUT
PG Data Output Value
0x188
read-write
n
0x0
0x0
PG_INTEN
PG_INTEN
PG Interrupt Enable Control Register
0x19C
read-write
n
0x0
0x0
PG_INTSRC
PG_INTSRC
PG Interrupt Source Flag
0x1A0
read-write
n
0x0
0x0
PG_INTTYPE
PG_INTTYPE
PG Interrupt Trigger Type Control
0x198
read-write
n
0x0
0x0
PG_MODE
PG_MODE
PG I/O Mode Control
0x180
read-write
n
0x0
0x0
PG_PIN
PG_PIN
PG Pin Value
0x190
read-write
n
0x0
0x0
PH10_PDIO
PH10_PDIO
GPIO PH.n Pin Data Input/Output Register
0x9E8
read-write
n
0x0
0x0
PH11_PDIO
PH11_PDIO
GPIO PH.n Pin Data Input/Output Register
0x9EC
read-write
n
0x0
0x0
PH4_PDIO
PH4_PDIO
GPIO PH.n Pin Data Input/Output Register
0x9D0
read-write
n
0x0
0x0
PH5_PDIO
PH5_PDIO
GPIO PH.n Pin Data Input/Output Register
0x9D4
read-write
n
0x0
0x0
PH6_PDIO
PH6_PDIO
GPIO PH.n Pin Data Input/Output Register
0x9D8
read-write
n
0x0
0x0
PH7_PDIO
PH7_PDIO
GPIO PH.n Pin Data Input/Output Register
0x9DC
read-write
n
0x0
0x0
PH8_PDIO
PH8_PDIO
GPIO PH.n Pin Data Input/Output Register
0x9E0
read-write
n
0x0
0x0
PH9_PDIO
PH9_PDIO
GPIO PH.n Pin Data Input/Output Register
0x9E4
read-write
n
0x0
0x0
PH_DATMSK
PH_DATMSK
PH Data Output Write Mask
0x1CC
read-write
n
0x0
0x0
PH_DBEN
PH_DBEN
PH De-bounce Enable Control Register
0x1D4
read-write
n
0x0
0x0
PH_DINOFF
PH_DINOFF
PH Digital Input Path Disable Control
0x1C4
read-write
n
0x0
0x0
PH_DOUT
PH_DOUT
PH Data Output Value
0x1C8
read-write
n
0x0
0x0
PH_INTEN
PH_INTEN
PH Interrupt Enable Control Register
0x1DC
read-write
n
0x0
0x0
PH_INTSRC
PH_INTSRC
PH Interrupt Source Flag
0x1E0
read-write
n
0x0
0x0
PH_INTTYPE
PH_INTTYPE
PH Interrupt Trigger Type Control
0x1D8
read-write
n
0x0
0x0
PH_MODE
PH_MODE
PH I/O Mode Control
0x1C0
read-write
n
0x0
0x0
PH_PIN
PH_PIN
PH Pin Value
0x1D0
read-write
n
0x0
0x0
HDIV
HDIV Register Map
HDIV
0x0
0x0
0x14
registers
n
DIVIDEND
DIVIDEND
Dividend Source Register
0x0
read-write
n
0x0
0x0
DIVIDEND
Dividend Source\nThis register is given the dividend of divider before calculation starts.
0
32
read-write
DIVISOR
DIVISOR
Divisor Source Resister
0x4
-1
read-write
n
0x0
0x0
DIVISOR
Divisor Source\nThis register is provided with the divisor of divider before calculation starts.\nNote: When this register is written, hardware divider will start calculation.
0
16
read-write
DIVQUO
DIVQUO
Quotient Result Resister
0x8
read-write
n
0x0
0x0
QUOTIENT
Quotient Result\nThis register holds the quotient result of divider after calculation is complete.
0
32
read-write
DIVREM
DIVREM
Remainder Result Register
0xC
read-write
n
0x0
0x0
REMAINDER15_0
Remainder Result\nThis register holds the remainder result of divider after calculation is complete.
0
16
read-write
REMAINDER31_16
Sign Extension of REMAINDER[15:0]\nThe remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]) with sign extension (REMAINDER[31:16]) to 32-bit integer.
16
16
read-write
DIVSTS
DIVSTS
Divider Status Register
0x10
-1
read-only
n
0x0
0x0
DIV0
Divisor Zero Warning (Read Only)\nNote: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written.
1
1
read-only
0
The divisor is not 0
#0
1
The divisor is 0
#1
I2C0
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x30
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
ADDR
I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.\nNote: When software set 7'h00, the address can not be used.
1
7
read-write
GC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
ADDR
I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.\nNote: When software set 7'h00, the address can not be used.
1
7
read-write
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2C_BUSCTL
I2C_BUSCTL
I2C Bus Management Control Register
0x50
read-write
n
0x0
0x0
ACKM9SI
Acknowledge Manual Enable Extra SI Interrupt
11
1
read-write
0
There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1
#0
1
There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1
#1
ACKMEN
Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
0
1
read-write
0
Slave byte control Disabled
#0
1
Slave byte control Enabled. The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse
#1
ALERTEN
Bus Management Alert Enable Bit
4
1
read-write
0
Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin not supported
#0
1
Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin supported
#1
BCDIEN
Packet Error Checking Byte Count Done Interrupt Enable Bit
12
1
read-write
0
Byte count done interrupt Disabled
#0
1
Byte count done interrupt Enabled
#1
BMDEN
Bus Management Device Default Address Enable Bit
2
1
read-write
0
Device default address Disable. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed
#0
1
Device default address Enabled. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed
#1
BMHEN
Bus Management Host Enable Bit
3
1
read-write
0
Host function Disabled
#0
1
Host function Enabled
#1
BUSEN
BUS Enable Bit\nNote: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
7
1
read-write
0
The system management function Disabled
#0
1
The system management function Enabled
#1
PECCLR
PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
10
1
read-write
0
PEC calculation is cleared by 'Repeat Start' function Disabled
#0
1
PEC calculation is cleared by 'Repeat Start' function Enabled
#1
PECDIEN
Packet Error Checking Byte Transfer Done Interrupt Enable Bit
13
1
read-write
0
PEC transfer done interrupt Disabled
#0
1
PEC transfer done interrupt Enabled
#1
PECEN
Packet Error Checking Calculation Enable Bit\nNote: When I2C enter powerdown mode, the bit should be enabled after wake-up if needed PEC calculation.
1
1
read-write
0
Packet Error Checking Calculation Disabled
#0
1
Packet Error Checking Calculation Enabled
#1
PECTXEN
Packet Error Checking Byte Transmission/Reception
8
1
read-write
0
No PEC transfer
#0
1
PEC transmission is requested
#1
SCTLOEN
Suspend or Control Pin Output Enable Bit
6
1
read-write
0
The SUSCON pin in input
#0
1
The output enable is active on the SUSCON pin
#1
SCTLOSTS
Suspend/Control Data Output Status
5
1
read-write
0
The output of SUSCON pin is low
#0
1
The output of SUSCON pin is high
#1
TIDLE
Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
9
1
read-write
0
BUSTOUT is used to calculate the clock low period in bus active
#0
1
BUSTOUT is used to calculate the IDLE period in bus Idle
#1
I2C_BUSSTS
I2C_BUSSTS
I2C Bus Management Status Register
0x58
read-write
n
0x0
0x0
ALERT
SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit.
3
1
read-write
0
SMBALERT pin state is low.\nNo SMBALERT event
#0
1
SMBALERT pin state is high.\nThere is SMBALERT event (falling edge) is detected in SMBALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1
#1
BCDONE
Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit.
1
1
read-write
0
Byte count transmission/ receive is not finished when the PECEN is set
#0
1
Byte count transmission/ receive is finished when the PECEN is set
#1
BUSTO
Bus Time-out Status
In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
Note: Software can write 1 to clear this bit.
5
1
read-write
0
There is no any time-out or external clock time-out
#0
1
A time-out or external clock time-out occurred
#1
BUSY
Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
0
1
read-only
0
Bus is IDLE (both SCLK and SDA High)
#0
1
Bus is busy
#1
CLKTO
Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit.
6
1
read-write
0
Cumulative clock low is no any time-out
#0
1
Cumulative clock low time-out occurred
#1
PECDONE
PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit.
7
1
read-write
0
PEC transmission/ receive is not finished when the PECEN is set
#0
1
PEC transmission/ receive is finished when the PECEN is set
#1
PECERR
PEC Error in Reception \nNote: Software can write 1 to clear this bit.
2
1
read-write
0
PEC value equal the received PEC data packet
#0
1
PEC value doesn't match the receive PEC data packet
#1
SCTLDIN
Bus Suspend or Control Signal Input Status (Read Only)
4
1
read-only
0
The input status of SUSCON pin is 0
#0
1
The input status of SUSCON pin is 1
#1
I2C_BUSTCTL
I2C_BUSTCTL
I2C Bus Management Timer Control Register
0x54
read-write
n
0x0
0x0
BUSTOEN
Bus Time Out Enable Bit
0
1
read-write
0
Bus clock low time-out detection Disabled
#0
1
Bus clock low time-out detection Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1)
#1
BUSTOIEN
Time-out Interrupt Enable Bit
2
1
read-write
0
SCLK low time-out interrupt Disabled.\nBus IDLE time-out interrupt Disabled
#0
1
SCLK low time-out interrupt Enabled.\nBus IDLE time-out interrupt Enabled
#1
CLKTOEN
Cumulative Clock Low Time Out Enable Bit\nFor Master, it calculates the period from START to ACK\nFor Slave, it calculates the period from START to STOP
1
1
read-write
0
Cumulative clock low time-out detection Disabled
#0
1
Cumulative clock low time-out detection Enabled
#1
CLKTOIEN
Extended Clock Time Out Interrupt Enable Bit
3
1
read-write
0
Clock time out interrupt Disabled
#0
1
Clock time out interrupt Enabled
#1
TORSTEN
Time Out Reset Enable Bit
4
1
read-write
0
I2C state machine reset Disabled
#0
1
I2C state machine reset Enabled. (The clock and data bus will be released to high)
#1
I2C_BUSTOUT
I2C_BUSTOUT
I2C Bus Management Timer Register
0x64
-1
read-write
n
0x0
0x0
BUSTO
Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
0
8
read-write
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4.
0
10
read-write
I2C_CLKTOUT
I2C_CLKTOUT
I2C Bus Management Clock Low Timer Register
0x68
-1
read-write
n
0x0
0x0
CLKTO
Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.
0
8
read-write
I2C_CTL0
I2C_CTL0
I2C Control Register 0
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
2
1
read-write
I2CEN
I2C Controller Enable Bit
6
1
read-write
0
I2C controller Disabled
#0
1
I2C controller Enabled
#1
INTEN
Enable Interrupt
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.\nFor ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
3
1
read-write
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
4
1
read-write
I2C_CTL1
I2C_CTL1
I2C Control Register 1
0x44
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the I2C request to PDMA
#1
PDMASTR
PDMA Stretch Bit
8
1
read-write
0
I2C send STOP automatically after PDMA transfer done. (only master TX)
#0
1
I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX)
#1
RXPDMAEN
PDMA Receive Channel Available
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
I2C_DAT
I2C_DAT
I2C Data Register
0x8
read-write
n
0x0
0x0
DAT
I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
0
8
read-write
I2C_PKTCRC
I2C_PKTCRC
I2C Packet Error Checking Byte Value Register
0x60
read-only
n
0x0
0x0
PECCRC
Packet Error Checking Byte Value
0
8
read-only
I2C_PKTSIZE
I2C_PKTSIZE
I2C Packet Error Checking Byte Number Register
0x5C
read-write
n
0x0
0x0
PLDSIZE
Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address, command code, and data frame.
0
9
read-write
I2C_STATUS0
I2C_STATUS0
I2C Status Register 0
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status
0
8
read-only
I2C_STATUS1
I2C_STATUS1
I2C Status Register 1
0x48
read-write
n
0x0
0x0
ONBUSY
On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.
8
1
read-only
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
I2C_TMCTL
I2C_TMCTL
I2C Timing Configure Control Register
0x4C
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
16
9
read-write
STCTL
Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs.
0
9
read-write
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
read-write
n
0x0
0x0
TOCDIV4
Time-out Counter Input Clock Divided by 4\nWhen enabled, the time-out period is extended 4 times.
1
1
read-write
0
Time-out period is extend 4 times Disabled
#0
1
Time-out period is extend 4 times Enabled
#1
TOCEN
Time-out Counter Enable Bit\nWhen enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOIF
Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
read-write
n
0x0
0x0
NHDBUSEN
I2C No Hold BUS Enable Bit
Note: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
7
1
read-write
0
I2C hold bus after wake-up
#0
1
I2C don't hold bus after wake-up
#1
WKEN
I2C Wake-up Enable Bit
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
read-write
n
0x0
0x0
WKAKDONE
Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit.
1
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WKIF
I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WRSTSWK
Read/Write Status Bit in Address Wakeup Frame (Read Only)\nNote: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit.
2
1
read-only
0
Write command be record on the address match wakeup frame
#0
1
Read command be record on the address match wakeup frame
#1
I2C1
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x30
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
ADDR
I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.\nNote: When software set 7'h00, the address can not be used.
1
7
read-write
GC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
ADDR
I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.\nNote: When software set 7'h00, the address can not be used.
1
7
read-write
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2C_BUSCTL
I2C_BUSCTL
I2C Bus Management Control Register
0x50
read-write
n
0x0
0x0
ACKM9SI
Acknowledge Manual Enable Extra SI Interrupt
11
1
read-write
0
There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1
#0
1
There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1
#1
ACKMEN
Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
0
1
read-write
0
Slave byte control Disabled
#0
1
Slave byte control Enabled. The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse
#1
ALERTEN
Bus Management Alert Enable Bit
4
1
read-write
0
Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin not supported
#0
1
Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin supported
#1
BCDIEN
Packet Error Checking Byte Count Done Interrupt Enable Bit
12
1
read-write
0
Byte count done interrupt Disabled
#0
1
Byte count done interrupt Enabled
#1
BMDEN
Bus Management Device Default Address Enable Bit
2
1
read-write
0
Device default address Disable. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed
#0
1
Device default address Enabled. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed
#1
BMHEN
Bus Management Host Enable Bit
3
1
read-write
0
Host function Disabled
#0
1
Host function Enabled
#1
BUSEN
BUS Enable Bit\nNote: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
7
1
read-write
0
The system management function Disabled
#0
1
The system management function Enabled
#1
PECCLR
PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
10
1
read-write
0
PEC calculation is cleared by 'Repeat Start' function Disabled
#0
1
PEC calculation is cleared by 'Repeat Start' function Enabled
#1
PECDIEN
Packet Error Checking Byte Transfer Done Interrupt Enable Bit
13
1
read-write
0
PEC transfer done interrupt Disabled
#0
1
PEC transfer done interrupt Enabled
#1
PECEN
Packet Error Checking Calculation Enable Bit\nNote: When I2C enter powerdown mode, the bit should be enabled after wake-up if needed PEC calculation.
1
1
read-write
0
Packet Error Checking Calculation Disabled
#0
1
Packet Error Checking Calculation Enabled
#1
PECTXEN
Packet Error Checking Byte Transmission/Reception
8
1
read-write
0
No PEC transfer
#0
1
PEC transmission is requested
#1
SCTLOEN
Suspend or Control Pin Output Enable Bit
6
1
read-write
0
The SUSCON pin in input
#0
1
The output enable is active on the SUSCON pin
#1
SCTLOSTS
Suspend/Control Data Output Status
5
1
read-write
0
The output of SUSCON pin is low
#0
1
The output of SUSCON pin is high
#1
TIDLE
Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
9
1
read-write
0
BUSTOUT is used to calculate the clock low period in bus active
#0
1
BUSTOUT is used to calculate the IDLE period in bus Idle
#1
I2C_BUSSTS
I2C_BUSSTS
I2C Bus Management Status Register
0x58
read-write
n
0x0
0x0
ALERT
SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit.
3
1
read-write
0
SMBALERT pin state is low.\nNo SMBALERT event
#0
1
SMBALERT pin state is high.\nThere is SMBALERT event (falling edge) is detected in SMBALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1
#1
BCDONE
Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit.
1
1
read-write
0
Byte count transmission/ receive is not finished when the PECEN is set
#0
1
Byte count transmission/ receive is finished when the PECEN is set
#1
BUSTO
Bus Time-out Status
In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
Note: Software can write 1 to clear this bit.
5
1
read-write
0
There is no any time-out or external clock time-out
#0
1
A time-out or external clock time-out occurred
#1
BUSY
Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
0
1
read-only
0
Bus is IDLE (both SCLK and SDA High)
#0
1
Bus is busy
#1
CLKTO
Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit.
6
1
read-write
0
Cumulative clock low is no any time-out
#0
1
Cumulative clock low time-out occurred
#1
PECDONE
PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit.
7
1
read-write
0
PEC transmission/ receive is not finished when the PECEN is set
#0
1
PEC transmission/ receive is finished when the PECEN is set
#1
PECERR
PEC Error in Reception \nNote: Software can write 1 to clear this bit.
2
1
read-write
0
PEC value equal the received PEC data packet
#0
1
PEC value doesn't match the receive PEC data packet
#1
SCTLDIN
Bus Suspend or Control Signal Input Status (Read Only)
4
1
read-only
0
The input status of SUSCON pin is 0
#0
1
The input status of SUSCON pin is 1
#1
I2C_BUSTCTL
I2C_BUSTCTL
I2C Bus Management Timer Control Register
0x54
read-write
n
0x0
0x0
BUSTOEN
Bus Time Out Enable Bit
0
1
read-write
0
Bus clock low time-out detection Disabled
#0
1
Bus clock low time-out detection Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1)
#1
BUSTOIEN
Time-out Interrupt Enable Bit
2
1
read-write
0
SCLK low time-out interrupt Disabled.\nBus IDLE time-out interrupt Disabled
#0
1
SCLK low time-out interrupt Enabled.\nBus IDLE time-out interrupt Enabled
#1
CLKTOEN
Cumulative Clock Low Time Out Enable Bit\nFor Master, it calculates the period from START to ACK\nFor Slave, it calculates the period from START to STOP
1
1
read-write
0
Cumulative clock low time-out detection Disabled
#0
1
Cumulative clock low time-out detection Enabled
#1
CLKTOIEN
Extended Clock Time Out Interrupt Enable Bit
3
1
read-write
0
Clock time out interrupt Disabled
#0
1
Clock time out interrupt Enabled
#1
TORSTEN
Time Out Reset Enable Bit
4
1
read-write
0
I2C state machine reset Disabled
#0
1
I2C state machine reset Enabled. (The clock and data bus will be released to high)
#1
I2C_BUSTOUT
I2C_BUSTOUT
I2C Bus Management Timer Register
0x64
-1
read-write
n
0x0
0x0
BUSTO
Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
0
8
read-write
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4.
0
10
read-write
I2C_CLKTOUT
I2C_CLKTOUT
I2C Bus Management Clock Low Timer Register
0x68
-1
read-write
n
0x0
0x0
CLKTO
Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.
0
8
read-write
I2C_CTL0
I2C_CTL0
I2C Control Register 0
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
2
1
read-write
I2CEN
I2C Controller Enable Bit
6
1
read-write
0
I2C controller Disabled
#0
1
I2C controller Enabled
#1
INTEN
Enable Interrupt
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.\nFor ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
3
1
read-write
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
4
1
read-write
I2C_CTL1
I2C_CTL1
I2C Control Register 1
0x44
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the I2C request to PDMA
#1
PDMASTR
PDMA Stretch Bit
8
1
read-write
0
I2C send STOP automatically after PDMA transfer done. (only master TX)
#0
1
I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX)
#1
RXPDMAEN
PDMA Receive Channel Available
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
I2C_DAT
I2C_DAT
I2C Data Register
0x8
read-write
n
0x0
0x0
DAT
I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
0
8
read-write
I2C_PKTCRC
I2C_PKTCRC
I2C Packet Error Checking Byte Value Register
0x60
read-only
n
0x0
0x0
PECCRC
Packet Error Checking Byte Value
0
8
read-only
I2C_PKTSIZE
I2C_PKTSIZE
I2C Packet Error Checking Byte Number Register
0x5C
read-write
n
0x0
0x0
PLDSIZE
Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address, command code, and data frame.
0
9
read-write
I2C_STATUS0
I2C_STATUS0
I2C Status Register 0
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status
0
8
read-only
I2C_STATUS1
I2C_STATUS1
I2C Status Register 1
0x48
read-write
n
0x0
0x0
ONBUSY
On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.
8
1
read-only
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
I2C_TMCTL
I2C_TMCTL
I2C Timing Configure Control Register
0x4C
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
16
9
read-write
STCTL
Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs.
0
9
read-write
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
read-write
n
0x0
0x0
TOCDIV4
Time-out Counter Input Clock Divided by 4\nWhen enabled, the time-out period is extended 4 times.
1
1
read-write
0
Time-out period is extend 4 times Disabled
#0
1
Time-out period is extend 4 times Enabled
#1
TOCEN
Time-out Counter Enable Bit\nWhen enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOIF
Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
read-write
n
0x0
0x0
NHDBUSEN
I2C No Hold BUS Enable Bit
Note: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
7
1
read-write
0
I2C hold bus after wake-up
#0
1
I2C don't hold bus after wake-up
#1
WKEN
I2C Wake-up Enable Bit
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
read-write
n
0x0
0x0
WKAKDONE
Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit.
1
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WKIF
I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WRSTSWK
Read/Write Status Bit in Address Wakeup Frame (Read Only)\nNote: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit.
2
1
read-only
0
Write command be record on the address match wakeup frame
#0
1
Read command be record on the address match wakeup frame
#1
NMI
NMI Register Map
NMI
0x0
0x0
0x8
registers
n
NMIEN
NMIEN
NMI Source Interrupt Enable Register
0x0
read-write
n
0x0
0x0
BODOUT
BOD NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
BOD NMI source Disabled
#0
1
BOD NMI source Enabled
#1
CLKFAIL
Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
Clock fail detected and IRC Auto Trim interrupt NMI source Disabled
#0
1
Clock fail detected and IRC Auto Trim interrupt NMI source Enabled
#1
EINT0
External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
8
1
read-write
0
External interrupt from PA.6 or PB.5 pin NMI source Disabled
#0
1
External interrupt from PA.6 or PB.5 pin NMI source Enabled
#1
EINT1
External Interrupt From PA.7, PB.4 or PD.15 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
9
1
read-write
0
External interrupt from PA.7, PB.4 or PD.15 pin NMI source Disabled
#0
1
External interrupt from PA.7, PB.4 or PD.15 pin NMI source Enabled
#1
EINT2
External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
10
1
read-write
0
External interrupt from PB.3 or PC.6 pin NMI source Disabled
#0
1
External interrupt from PB.3 or PC.6 pin NMI source Enabled
#1
EINT3
External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
11
1
read-write
0
External interrupt from PB.2 or PC.7 pin NMI source Disabled
#0
1
External interrupt from PB.2 or PC.7 pin NMI source Enabled
#1
EINT4
External Interrupt From PA.8, PB.6 or PF.15 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
12
1
read-write
0
External interrupt from PA.8, PB.6 or PF.15 pin NMI source Disabled
#0
1
External interrupt from PA.8, PB.6 or PF.15 pin NMI source Enabled
#1
EINT5
External Interrupt From PB.7, PD.12 or PF.14 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
13
1
read-write
0
External interrupt from PB.7, PD.12 or PF.14 pin NMI source Disabled
#0
1
External interrupt from PB.7, PD.12 or PF.14 pin NMI source Enabled
#1
IRC_INT
IRC TRIM NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
IRC TRIM NMI source Disabled
#0
1
IRC TRIM NMI source Enabled
#1
PWRWU_INT
Power-down Mode Wake-up NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
Power-down mode wake-up NMI source Disabled
#0
1
Power-down mode wake-up NMI source Enabled
#1
RTC_INT
RTC NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
RTC NMI source Disabled
#0
1
RTC NMI source Enabled
#1
SRAM_PERR
SRAM ParityCheck Error NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
3
1
read-write
0
SRAM parity check error NMI source Disabled
#0
1
SRAM parity check error NMI source Enabled
#1
UART0_INT
UART0 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
14
1
read-write
0
UART0 NMI source Disabled
#0
1
UART0 NMI source Enabled
#1
UART1_INT
UART1 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
15
1
read-write
0
UART1 NMI source Disabled
#0
1
UART1 NMI source Enabled
#1
NMISTS
NMISTS
NMI Source Interrupt Status Register
0x4
read-only
n
0x0
0x0
BODOUT
BOD Interrupt Flag (Read Only)
0
1
read-only
0
BOD interrupt is deasserted
#0
1
BOD interrupt is asserted
#1
CLKFAIL
Clock Fail Detected or IRC Auto Trim Interrupt Flag (Read Only)
4
1
read-only
0
Clock fail detected or IRC Auto Trim interrupt is deasserted
#0
1
Clock fail detected or IRC Auto Trim interrupt is asserted
#1
EINT0
External Interrupt From PA.6 or PB.5 Pin Interrupt Flag (Read Only)
8
1
read-only
0
External Interrupt from PA.6 or PB.5 interrupt is deasserted
#0
1
External Interrupt from PA.6 or PB.5 interrupt is asserted
#1
EINT1
External Interrupt From PA.7, PB.4 or PD.15 Pin Interrupt Flag (Read Only)
9
1
read-only
0
External Interrupt from PA.7, PB.4 or PD.15 interrupt is deasserted
#0
1
External Interrupt from PA.7, PB.4 or PD.15 interrupt is asserted
#1
EINT2
External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only)
10
1
read-only
0
External Interrupt from PB.3 or PC.6 interrupt is deasserted
#0
1
External Interrupt from PB.3 or PC.6 interrupt is asserted
#1
EINT3
External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only)
11
1
read-only
0
External Interrupt from PB.2 or PC.7 interrupt is deasserted
#0
1
External Interrupt from PB.2 or PC.7 interrupt is asserted
#1
EINT4
External Interrupt From PA.8, PB.6 or PF.15 Pin Interrupt Flag (Read Only)
12
1
read-only
0
External Interrupt from PA.8, PB.6 or PF.15 interrupt is deasserted
#0
1
External Interrupt from PA.8, PB.6 or PF.15 interrupt is asserted
#1
EINT5
External Interrupt From PB.7 or PF.14 Pin Interrupt Flag (Read Only)
13
1
read-only
0
External Interrupt from PB.7 or PF.14 interrupt is deasserted
#0
1
External Interrupt from PB.7 or PF.14 interrupt is asserted
#1
IRC_INT
IRC TRIM Interrupt Flag (Read Only)
1
1
read-only
0
HIRC TRIM interrupt is deasserted
#0
1
HIRC TRIM interrupt is asserted
#1
PWRWU_INT
Power-down Mode Wake-up Interrupt Flag (Read Only)
2
1
read-only
0
Power-down mode wake-up interrupt is deasserted
#0
1
Power-down mode wake-up interrupt is asserted
#1
RTC_INT
RTC Interrupt Flag (Read Only)
6
1
read-only
0
RTC interrupt is deasserted
#0
1
RTC interrupt is asserted
#1
SRAM_PERR
SRAM ParityCheck Error Interrupt Flag (Read Only)
3
1
read-only
0
SRAM parity check error interrupt is deasserted
#0
1
SRAM parity check error interrupt is asserted
#1
UART0_INT
UART0 Interrupt Flag (Read Only)
14
1
read-only
0
UART1 interrupt is deasserted
#0
1
UART1 interrupt is asserted
#1
UART1_INT
UART1 Interrupt Flag (Read Only)
15
1
read-only
0
UART1 interrupt is deasserted
#0
1
UART1 interrupt is asserted
#1
NVIC
NVIC Register Map
NVIC
0x0
0x0
0x4
registers
n
0x100
0x4
registers
n
0x180
0x4
registers
n
0x200
0x4
registers
n
0x80
0x4
registers
n
IABR0
NVIC_IABR0
IRQ0 ~ IRQ31 Active Bit Register
0x200
read-write
n
0x0
0x0
ACTIVE
Interrupt Active Flags\nThe NVIC_IABR0 registers indicate which interrupts are active.
0
32
read-write
0
interrupt not active
0
1
interrupt active
1
ICER0
NVIC_ICER0
IRQ0 ~ IRQ31 Clear-enable Control Register
0x80
read-write
n
0x0
0x0
CALENA
Interrupt Clear Enable Bit\nThe NVIC_ICER0 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation:
0
32
read-write
0
No effect.\nInterrupt Disabled
0
1
Interrupt Disabled.\nInterrupt Enabled
1
ICPR0
NVIC_ICPR0
IRQ0 ~ IRQ31 Clear-pending Control Register
0x180
read-write
n
0x0
0x0
CALPEND
Interrupt Clear-pending\nThe NVIC_ICPR0 registers remove the pending state from interrupts, and show which interrupts are pending\nWrite Operation:
0
32
read-write
0
No effect.\nInterrupt is not pending
0
1
Removes pending state an interrupt.\nInterrupt is pending
1
ISER0
NVIC_ISER0
IRQ0 ~ IRQ31 Set-enable Control Register
0x0
read-write
n
0x0
0x0
SETENA
Interrupt Set Enable Bit\nThe NVIC_ISER0 registers enable interrupts, and show which interrupts are enabled\nWrite Operation:
0
32
read-write
0
No effect.\nInterrupt Disabled
0
1
Interrupt Enabled
1
ISPR0
NVIC_ISPR0
IRQ0 ~ IRQ31 Set-pending Control Register
0x100
read-write
n
0x0
0x0
SETPEND
Interrupt Set-pending \nThe NVIC_ISPR0 registers force interrupts into the pending state, and show which interrupts are pending\nWrite Operation:
0
32
read-write
0
No effect.\nInterrupt is not pending
0
1
Changes interrupt state to pending.\nInterrupt is pending
1
PDMA
PDMA Register Map
PDMA
0x0
0x0
0x80
registers
n
0x100
0x24
registers
n
0x400
0x44
registers
n
0x460
0x4
registers
n
0x480
0xC
registers
n
ABTSTS
PDMA_ABTSTS
PDMA Channel Read/Write Target Abort Flag Register
0x420
read-write
n
0x0
0x0
ABTIF0
PDMA Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
0
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF1
PDMA Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
1
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF2
PDMA Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
2
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF3
PDMA Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
3
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF4
PDMA Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
4
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF5
PDMA Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
5
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF6
PDMA Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
6
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF7
PDMA Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
7
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF8
PDMA Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
8
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ALIGN
PDMA_ALIGN
PDMA Transfer Alignment Status Register
0x428
read-write
n
0x0
0x0
ALIGN0
Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting, user can write 1 to clear these bits.
0
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN1
Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting, user can write 1 to clear these bits.
1
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN2
Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting, user can write 1 to clear these bits.
2
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN3
Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting, user can write 1 to clear these bits.
3
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN4
Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting, user can write 1 to clear these bits.
4
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN5
Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting, user can write 1 to clear these bits.
5
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN6
Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting, user can write 1 to clear these bits.
6
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN7
Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting, user can write 1 to clear these bits.
7
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN8
Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting, user can write 1 to clear these bits.
8
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
CHCTL
PDMA_CHCTL
PDMA Channel Control Register
0x400
read-write
n
0x0
0x0
CHEN0
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
0
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN1
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
1
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN2
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
2
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN3
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
3
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN4
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
4
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN5
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
5
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN6
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
6
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN7
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
7
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN8
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
8
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHRST
PDMA_CHRST
PDMA Channel Reset Register
0x460
read-write
n
0x0
0x0
CHnRST
Channel n Reset
0
9
read-write
0
corresponding channel n is not reset
0
1
corresponding channel n is reset
1
CURSCAT0
PDMA_CURSCAT0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x100
read-only
n
0x0
0x0
CURADDR
PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external description address.
0
32
read-only
CURSCAT1
PDMA_CURSCAT1
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x104
read-write
n
0x0
0x0
CURSCAT2
PDMA_CURSCAT2
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x108
read-write
n
0x0
0x0
CURSCAT3
PDMA_CURSCAT3
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x10C
read-write
n
0x0
0x0
CURSCAT4
PDMA_CURSCAT4
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x110
read-write
n
0x0
0x0
CURSCAT5
PDMA_CURSCAT5
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x114
read-write
n
0x0
0x0
CURSCAT6
PDMA_CURSCAT6
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x118
read-write
n
0x0
0x0
CURSCAT7
PDMA_CURSCAT7
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x11C
read-write
n
0x0
0x0
CURSCAT8
PDMA_CURSCAT8
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x120
read-write
n
0x0
0x0
DSCT0_CTL
PDMA_DSCT0_CTL
Descriptor Table Control Register of PDMA Channel n
0x0
read-write
n
0x0
0x0
BURSIZE
Burst Size\nNote: This field is only useful in burst transfer type.
4
3
read-write
0
128 Transfers
#000
1
64 Transfers
#001
2
32 Transfers
#010
3
16 Transfers
#011
4
8 Transfers
#100
5
4 Transfers
#101
6
2 Transfers
#110
7
1 Transfers
#111
DAINC
Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type.
10
2
read-write
3
No increment (fixed address)
#11
OPMODE
PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table, user must check the PDMA_INTSTS[1] to make sure the curren task is complete.
0
2
read-write
0
Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically
#00
1
Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[1] will be asserted
#01
2
Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register PDMA controller will ignore this task, then load the next task to execute
#10
3
Reserved.
#11
SAINC
Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type.
8
2
read-write
3
No increment (fixed address)
#11
TBINTDIS
Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[8:0]) when PDMA controller finishes transfer task.\nNote: This function only for scatter-gather mode.
7
1
read-write
0
Table interrupt Enabled
#0
1
Table interrupt Disabled
#1
TXCNT
Transfer Count
The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 16384, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
Note: When PDMA finish each transfer data, this field will be decrease immediately.
16
16
read-write
TXTYPE
Transfer Type
2
1
read-write
0
Burst transfer type
#0
1
Single transfer type
#1
TXWIDTH
Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
12
2
read-write
0
One byte (8 bit) is transferred for every operation
#00
1
One half-word (16 bit) is transferred for every operation
#01
2
One word (32-bit) is transferred for every operation
#10
3
Reserved.
#11
DSCT0_DA
PDMA_DSCT0_DA
Destination Address Register of PDMA Channel n
0x8
read-write
n
0x0
0x0
DA
PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller.
0
32
read-write
DSCT0_NEXT
PDMA_DSCT0_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0xC
read-write
n
0x0
0x0
EXENEXT
PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: write operation is useless in this field.
16
16
read-write
NEXT
PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.\nRead Operation:\nWhen operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory.\nNote 1: The descriptor table address must be word boundary.\nNote 2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
0
16
read-write
DSCT0_SA
PDMA_DSCT0_SA
Source Address Register of PDMA Channel n
0x4
read-write
n
0x0
0x0
SA
PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller.
0
32
read-write
DSCT1_CTL
PDMA_DSCT1_CTL
Descriptor Table Control Register of PDMA Channel n
0x10
read-write
n
0x0
0x0
DSCT1_DA
PDMA_DSCT1_DA
Destination Address Register of PDMA Channel n
0x18
read-write
n
0x0
0x0
DSCT1_NEXT
PDMA_DSCT1_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x1C
read-write
n
0x0
0x0
DSCT1_SA
PDMA_DSCT1_SA
Source Address Register of PDMA Channel n
0x14
read-write
n
0x0
0x0
DSCT2_CTL
PDMA_DSCT2_CTL
Descriptor Table Control Register of PDMA Channel n
0x20
read-write
n
0x0
0x0
DSCT2_DA
PDMA_DSCT2_DA
Destination Address Register of PDMA Channel n
0x28
read-write
n
0x0
0x0
DSCT2_NEXT
PDMA_DSCT2_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x2C
read-write
n
0x0
0x0
DSCT2_SA
PDMA_DSCT2_SA
Source Address Register of PDMA Channel n
0x24
read-write
n
0x0
0x0
DSCT3_CTL
PDMA_DSCT3_CTL
Descriptor Table Control Register of PDMA Channel n
0x30
read-write
n
0x0
0x0
DSCT3_DA
PDMA_DSCT3_DA
Destination Address Register of PDMA Channel n
0x38
read-write
n
0x0
0x0
DSCT3_NEXT
PDMA_DSCT3_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x3C
read-write
n
0x0
0x0
DSCT3_SA
PDMA_DSCT3_SA
Source Address Register of PDMA Channel n
0x34
read-write
n
0x0
0x0
DSCT4_CTL
PDMA_DSCT4_CTL
Descriptor Table Control Register of PDMA Channel n
0x40
read-write
n
0x0
0x0
DSCT4_DA
PDMA_DSCT4_DA
Destination Address Register of PDMA Channel n
0x48
read-write
n
0x0
0x0
DSCT4_NEXT
PDMA_DSCT4_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x4C
read-write
n
0x0
0x0
DSCT4_SA
PDMA_DSCT4_SA
Source Address Register of PDMA Channel n
0x44
read-write
n
0x0
0x0
DSCT5_CTL
PDMA_DSCT5_CTL
Descriptor Table Control Register of PDMA Channel n
0x50
read-write
n
0x0
0x0
DSCT5_DA
PDMA_DSCT5_DA
Destination Address Register of PDMA Channel n
0x58
read-write
n
0x0
0x0
DSCT5_NEXT
PDMA_DSCT5_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x5C
read-write
n
0x0
0x0
DSCT5_SA
PDMA_DSCT5_SA
Source Address Register of PDMA Channel n
0x54
read-write
n
0x0
0x0
DSCT6_CTL
PDMA_DSCT6_CTL
Descriptor Table Control Register of PDMA Channel n
0x60
read-write
n
0x0
0x0
DSCT6_DA
PDMA_DSCT6_DA
Destination Address Register of PDMA Channel n
0x68
read-write
n
0x0
0x0
DSCT6_NEXT
PDMA_DSCT6_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x6C
read-write
n
0x0
0x0
DSCT6_SA
PDMA_DSCT6_SA
Source Address Register of PDMA Channel n
0x64
read-write
n
0x0
0x0
DSCT7_CTL
PDMA_DSCT7_CTL
Descriptor Table Control Register of PDMA Channel n
0x70
read-write
n
0x0
0x0
DSCT7_DA
PDMA_DSCT7_DA
Destination Address Register of PDMA Channel n
0x78
read-write
n
0x0
0x0
DSCT7_NEXT
PDMA_DSCT7_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x7C
read-write
n
0x0
0x0
DSCT7_SA
PDMA_DSCT7_SA
Source Address Register of PDMA Channel n
0x74
read-write
n
0x0
0x0
DSCT8_CTL
PDMA_DSCT8_CTL
Descriptor Table Control Register of PDMA Channel n
0x80
read-write
n
0x0
0x0
DSCT8_DA
PDMA_DSCT8_DA
Destination Address Register of PDMA Channel n
0x88
read-write
n
0x0
0x0
DSCT8_NEXT
PDMA_DSCT8_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x8C
read-write
n
0x0
0x0
DSCT8_SA
PDMA_DSCT8_SA
Source Address Register of PDMA Channel n
0x84
read-write
n
0x0
0x0
INTEN
PDMA_INTEN
PDMA Interrupt Enable Register
0x418
read-write
n
0x0
0x0
INTEN0
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
0
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN1
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
1
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN2
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
2
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN3
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
3
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN4
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
4
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN5
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
5
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN6
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
6
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN7
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
7
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN8
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
8
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTSTS
PDMA_INTSTS
PDMA Interrupt Status Register
0x41C
read-write
n
0x0
0x0
ABTIF
PDMA Read/Write Target Abort Interrupt Flag (Read Only)
This bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error.
0
1
read-only
0
No AHB bus ERROR response received
#0
1
AHB bus ERROR response received
#1
ALIGNF
Transfer Alignment Interrupt Flag (Read Only)
2
1
read-only
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
REQTOF0
Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits.\nNote: Please disable time-out function before clear this bit.
8
1
read-write
0
No request time-out
#0
1
Peripheral request time-out
#1
REQTOF1
Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits.\nNote: Please disable time-out function before clear this bit.
9
1
read-write
0
No request time-out
#0
1
Peripheral request time-out
#1
TDIF
Transfer Done Interrupt Flag (Read Only)
This bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer.
1
1
read-only
0
Not finished yet
#0
1
PDMA channel has finished transmission
#1
PAUSE
PDMA_PAUSE
PDMA Transfer Pause Control Register
0x404
write-only
n
0x0
0x0
PAUSE0
PDMA Channel n Transfer Pause Control (Write Only)
0
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE1
PDMA Channel n Transfer Pause Control (Write Only)
1
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE2
PDMA Channel n Transfer Pause Control (Write Only)
2
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE3
PDMA Channel n Transfer Pause Control (Write Only)
3
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE4
PDMA Channel n Transfer Pause Control (Write Only)
4
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE5
PDMA Channel n Transfer Pause Control (Write Only)
5
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE6
PDMA Channel n Transfer Pause Control (Write Only)
6
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE7
PDMA Channel n Transfer Pause Control (Write Only)
7
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE8
PDMA Channel n Transfer Pause Control (Write Only)
8
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PRICLR
PDMA_PRICLR
PDMA Fixed Priority Clear Register
0x414
write-only
n
0x0
0x0
FPRICLR0
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
0
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR1
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
1
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR2
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
2
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR3
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
3
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR4
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
4
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR5
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
5
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR6
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
6
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR7
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
7
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR8
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
8
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
PRISET
PDMA_PRISET
PDMA Fixed Priority Setting Register
0x410
read-write
n
0x0
0x0
FPRISET0
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
0
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
FPRISET1
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
1
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
FPRISET2
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
2
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
FPRISET3
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
3
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
FPRISET4
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
4
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
FPRISET5
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
5
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
FPRISET6
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
6
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
FPRISET7
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
7
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
FPRISET8
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
8
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
REQSEL0_3
PDMA_REQSEL0_3
PDMA Request Source Select Register 0
0x480
read-write
n
0x0
0x0
REQSRC0
Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\n\nNote 1: A peripheral cannot be assigned to two channels at the same time.\nNote 2: This field is useless when transfer between memory and memory.
0
6
read-write
0
Disable PDMA peripheral request
0
1
Reserved.
1
10
Channel connects to USCI0_TX
10
11
Channel connects to USCI0_RX
11
12
Channel connects to USCI1_TX
12
13
Channel connects to USCI1_RX
13
14
Reserved.
14
15
Reserved.
15
16
Channel connects to QSPI0_TX
16
17
Channel connects to QSPI0_RX
17
18
Channel connects to SPI0_TX
18
19
Channel connects to SPI0_RX
19
20
Channel connects to ADC_RX
20
21
Channel connects to PWM0_P1_RX
21
22
Channel connects to PWM0_P2_RX
22
23
Channel connects to PWM0_P3_RX
23
24
Channel connects to PWM1_P1_RX
24
25
Channel connects to PWM1_P2_RX
25
26
Channel connects to PWM1_P3_RX
26
27
Reserved.
27
28
Channel connects to I2C0_TX
28
29
Channel connects to I2C0_RX
29
30
Channel connects to I2C1_TX
30
31
Channel connects to I2C1_RX
31
32
Channel connects to TMR0
32
33
Channel connects to TMR1
33
34
Channel connects to TMR2
34
35
Channel connects to TMR3
35
36
Channel connects to UART3_TX
36
37
Channel connects to UART3_RX
37
38
Channel connects to UART4_TX
38
39
Channel connects to UART4_RX
39
4
Channel connects to UART0_TX
4
40
Channel connects to UART5_TX
40
41
Channel connects to UART5_RX
41
42
Channel connects to UART6_TX
42
43
Channel connects to UART6_RX
43
44
Channel connects to UART7_TX
44
45
Channel connects to UART7_RX
45
5
Channel connects to UART0_RX
5
6
Channel connects to UART1_TX
6
7
Channel connects to UART1_RX
7
8
Channel connects to UART2_TX
8
9
Channel connects to UART2_RX
9
REQSRC1
Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
6
read-write
REQSRC2
Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
6
read-write
REQSRC3
Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
6
read-write
REQSEL4_7
PDMA_REQSEL4_7
PDMA Request Source Select Register 1
0x484
read-write
n
0x0
0x0
REQSRC4
Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
0
6
read-write
REQSRC5
Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
6
read-write
REQSRC6
Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
6
read-write
REQSRC7
Channel 7 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
6
read-write
REQSEL8
PDMA_REQSEL8
PDMA Request Source Select Register 2
0x488
read-write
n
0x0
0x0
REQSRC8
Channel 8 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 8. User can configure the peripheral setting by REQSRC8. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
0
6
read-write
SCATBA
PDMA_SCATBA
PDMA Scatter-gather Descriptor Table Base Address Register
0x43C
-1
read-write
n
0x0
0x0
SCATBA
PDMA Scatter-gather Descriptor Table Address\nIn Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-Gather mode.
16
16
read-write
SWREQ
PDMA_SWREQ
PDMA Software Request Register
0x408
write-only
n
0x0
0x0
SWREQ0
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
0
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ1
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
1
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ2
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
2
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ3
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
3
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ4
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
4
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ5
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
5
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ6
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
6
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ7
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
7
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ8
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
8
1
write-only
0
No effect
#0
1
Generate a software request
#1
TACTSTS
PDMA_TACTSTS
PDMA Transfer Active Flag Register
0x42C
read-only
n
0x0
0x0
TXACTF0
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
0
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TXACTF1
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
1
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TXACTF2
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
2
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TXACTF3
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
3
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TXACTF4
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
4
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TXACTF5
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
5
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TXACTF6
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
6
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TXACTF7
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
7
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TXACTF8
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
8
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TDSTS
PDMA_TDSTS
PDMA Channel Transfer Done Flag Register
0x424
read-write
n
0x0
0x0
TDIF0
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
0
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF1
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
1
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF2
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
2
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF3
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
3
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF4
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
4
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF5
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
5
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF6
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
6
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF7
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
7
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF8
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
8
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TOC0_1
PDMA_TOC0_1
PDMA Time-out Counter Ch1 and Ch0 Register
0x440
-1
read-write
n
0x0
0x0
TOC0
Time-out Counter for Channel 0
0
16
read-write
TOC1
Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[6:4]) clock. The example of time-out period can refer TOC0 bit description.
16
16
read-write
TOUTEN
PDMA_TOUTEN
PDMA Time-out Enable Register
0x434
read-write
n
0x0
0x0
TOUTEN0
PDMA Time-out Enable Bits
0
1
read-write
0
PDMA Channel n time-out function Disabled
#0
1
PDMA Channel n time-out function Enabled
#1
TOUTEN1
PDMA Time-out Enable Bits
1
1
read-write
0
PDMA Channel n time-out function Disabled
#0
1
PDMA Channel n time-out function Enabled
#1
TOUTIEN
PDMA_TOUTIEN
PDMA Time-out Interrupt Enable Register
0x438
read-write
n
0x0
0x0
TOUTIEN0
PDMA Time-out Interrupt Enable Bits
0
1
read-write
0
PDMA Channel n time-out interrupt Disabled
#0
1
PDMA Channel n time-out interrupt Enabled
#1
TOUTIEN1
PDMA Time-out Interrupt Enable Bits
1
1
read-write
0
PDMA Channel n time-out interrupt Disabled
#0
1
PDMA Channel n time-out interrupt Enabled
#1
TOUTPSC
PDMA_TOUTPSC
PDMA Time-out Prescaler Register
0x430
read-write
n
0x0
0x0
TOUTPSC0
PDMA Channel 0 Time-out Clock Source Prescaler Bits
0
3
read-write
0
PDMA channel 0 time-out clock source is HCLK/28
#000
1
PDMA channel 0 time-out clock source is HCLK/29
#001
2
PDMA channel 0 time-out clock source is HCLK/210
#010
3
PDMA channel 0 time-out clock source is HCLK/211
#011
4
PDMA channel 0 time-out clock source is HCLK/212
#100
5
PDMA channel 0 time-out clock source is HCLK/213
#101
6
PDMA channel 0 time-out clock source is HCLK/214
#110
7
PDMA channel 0 time-out clock source is HCLK/215
#111
TOUTPSC1
PDMA Channel 1 Time-out Clock Source Prescaler Bits
4
3
read-write
0
PDMA channel 1 time-out clock source is HCLK/28
#000
1
PDMA channel 1 time-out clock source is HCLK/29
#001
2
PDMA channel 1 time-out clock source is HCLK/210
#010
3
PDMA channel 1 time-out clock source is HCLK/211
#011
4
PDMA channel 1 time-out clock source is HCLK/212
#100
5
PDMA channel 1 time-out clock source is HCLK/213
#101
6
PDMA channel 1 time-out clock source is HCLK/214
#110
7
PDMA channel 1 time-out clock source is HCLK/215
#111
TRGSTS
PDMA_TRGSTS
PDMA Channel Request Status Register
0x40C
read-only
n
0x0
0x0
REQSTS0
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
0
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS1
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
1
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS2
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
2
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS3
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
3
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS4
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
4
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS5
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
5
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS6
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
6
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS7
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
7
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS8
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
8
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
PWM0
PWM Register Map
PWM
0x0
0x0
0x8
registers
n
0x10
0x18
registers
n
0x110
0x8
registers
n
0x120
0x4
registers
n
0x200
0x4C
registers
n
0x250
0x8
registers
n
0x30
0x4
registers
n
0x304
0x4
registers
n
0x30C
0x4
registers
n
0x314
0x4
registers
n
0x31C
0x18
registers
n
0x38
0x4
registers
n
0x40
0x4
registers
n
0x50
0x18
registers
n
0x70
0xC
registers
n
0x90
0x4
registers
n
0x98
0x4
registers
n
0xA0
0x4
registers
n
0xB0
0x40
registers
n
0xF8
0x8
registers
n
PWM_ADCTS0
PWM_ADCTS0
PWM Trigger ADC Source Select Register 0
0xF8
read-write
n
0x0
0x0
TRGEN0
PWM_CH0 Trigger ADC Enable Bit
7
1
read-write
0
PWM_CH0 Trigger ADC function Disabled
#0
1
PWM_CH0 Trigger ADC function Enabled
#1
TRGEN1
PWM_CH1 Trigger ADC Enable Bit
15
1
read-write
0
PWM_CH1 Trigger ADC function Disabled
#0
1
PWM_CH1 Trigger ADC function Enabled
#1
TRGEN2
PWM_CH2 Trigger ADC Enable Bit
23
1
read-write
0
PWM_CH2 Trigger ADC function Disabled
#0
1
PWM_CH2 Trigger ADC function Enabled
#1
TRGEN3
PWM_CH3 Trigger ADC Enable Bit
31
1
read-write
0
PWM_CH3 Trigger ADC function Disabled
#0
1
PWM_CH3 Trigger ADC function Enabled
#1
TRGSEL0
PWM_CH0 Trigger ADC Source Select
0
4
read-write
0
PWM_CH0 zero point
#0000
1
PWM_CH0 period point
#0001
2
PWM_CH0 zero or period point
#0010
3
PWM_CH0 up-count CMPDAT point
#0011
4
PWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH1 up-count CMPDAT point
#1000
9
PWM_CH1 down-count CMPDAT point
#1001
TRGSEL1
PWM_CH1 Trigger ADC Source Select
8
4
read-write
0
PWM_CH0 zero point
#0000
1
PWM_CH0 period point
#0001
2
PWM_CH0 zero or period point
#0010
3
PWM_CH0 up-count CMPDAT point
#0011
4
PWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH1 up-count CMPDAT point
#1000
9
PWM_CH1 down-count CMPDAT point
#1001
TRGSEL2
PWM_CH2 Trigger ADC Source Select
16
4
read-write
0
PWM_CH2 zero point
#0000
1
PWM_CH2 period point
#0001
2
PWM_CH2 zero or period point
#0010
3
PWM_CH2 up-count CMPDAT point
#0011
4
PWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH3 up-count CMPDAT point
#1000
9
PWM_CH3 down-count CMPDAT point
#1001
TRGSEL3
PWM_CH3 Trigger ADC Source Select
24
4
read-write
0
PWM_CH2 zero point
#0000
1
PWM_CH2 period point
#0001
2
PWM_CH2 zero or period point
#0010
3
PWM_CH2 up-count CMPDAT point
#0011
4
PWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH3 up-count CMPDAT point
#1000
9
PWM_CH3 down-count CMPDAT point
#1001
PWM_ADCTS1
PWM_ADCTS1
PWM Trigger ADC Source Select Register 1
0xFC
read-write
n
0x0
0x0
TRGEN4
PWM_CH4 Trigger ADC Enable Bit
7
1
read-write
0
PWM_CH4 Trigger ADC function Disabled
#0
1
PWM_CH4 Trigger ADC function Enabled
#1
TRGEN5
PWM_CH5 Trigger ADC Enable Bit
15
1
read-write
0
PWM_CH5 Trigger ADC function Disabled
#0
1
PWM_CH5 Trigger ADC function Enabled
#1
TRGSEL4
PWM_CH4 Trigger ADC Source Select
0
4
read-write
0
PWM_CH4 zero point
#0000
1
PWM_CH4 period point
#0001
2
PWM_CH4 zero or period point
#0010
3
PWM_CH4 up-count CMPDAT point
#0011
4
PWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH5 up-count CMPDAT point
#1000
9
PWM_CH5 down-count CMPDAT point
#1001
TRGSEL5
PWM_CH5 Trigger ADC Source Select
8
4
read-write
0
PWM_CH4 zero point
#0000
1
PWM_CH4 period point
#0001
2
PWM_CH4 zero or period point
#0010
3
PWM_CH4 up-count CMPDAT point
#0011
4
PWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH5 up-count CMPDAT point
#1000
9
PWM_CH5 down-count CMPDAT point
#1001
PWM_BNF
PWM_BNF
PWM Brake Noise Filter Register
0xC0
read-write
n
0x0
0x0
BK0SRC
Brake 0 Pin Source Select\nFor PWM0 setting:
16
1
read-write
0
Brake 0 pin source come from PWM0_BRAKE0.\nBrake 0 pin source come from PWM1_BRAKE0
#0
1
Brake 0 pin source come from PWM1_BRAKE0.\nBrake 0 pin source come from PWM0_BRAKE0
#1
BK1SRC
Brake 1 Pin Source Select\nFor PWM0 setting:
24
1
read-write
0
Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1
#0
1
Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1
#1
BRK0FCNT
Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
4
3
read-write
BRK0NFEN
PWM Brake 0 Noise Filter Enable Bit
0
1
read-write
0
Noise filter of PWM Brake 0 Disabled
#0
1
Noise filter of PWM Brake 0 Enabled
#1
BRK0NFSEL
Brake 0 Edge Detector Filter Clock Selection
1
3
read-write
0
Filter clock = HCLK
#000
1
Filter clock = HCLK/2
#001
2
Filter clock = HCLK/4
#010
3
Filter clock = HCLK/8
#011
4
Filter clock = HCLK/16
#100
5
Filter clock = HCLK/32
#101
6
Filter clock = HCLK/64
#110
7
Filter clock = HCLK/128
#111
BRK0PINV
Brake 0 Pin Inverse
7
1
read-write
0
The state of pin PWMx_BRAKE0 is passed to the negative edge detector
#0
1
The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector
#1
BRK1FCNT
Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
12
3
read-write
BRK1NFEN
PWM Brake 1 Noise Filter Enable Bit
8
1
read-write
0
Noise filter of PWM Brake 1 Disabled
#0
1
Noise filter of PWM Brake 1 Enabled
#1
BRK1NFSEL
Brake 1 Edge Detector Filter Clock Selection
9
3
read-write
0
Filter clock = HCLK
#000
1
Filter clock = HCLK/2
#001
2
Filter clock = HCLK/4
#010
3
Filter clock = HCLK/8
#011
4
Filter clock = HCLK/16
#100
5
Filter clock = HCLK/32
#101
6
Filter clock = HCLK/64
#110
7
Filter clock = HCLK/128
#111
BRK1PINV
Brake 1 Pin Inverse
15
1
read-write
0
The state of pin PWMx_BRAKE1 is passed to the negative edge detector
#0
1
The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector
#1
PWM_BRKCTL0_1
PWM_BRKCTL0_1
PWM Brake Edge Detect Control Register 0/1
0xC8
read-write
n
0x0
0x0
BRKAEVEN
PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register.
16
2
read-write
0
PWM even channel level-detect brake function not affect channel output
#00
1
PWM even channel output tri-state when level-detect brake happened
#01
2
PWM even channel output low level when level-detect brake happened
#10
3
PWM even channel output high level when level-detect brake happened
#11
BRKAODD
PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register.
18
2
read-write
0
PWM odd channel level-detect brake function not affect channel output
#00
1
PWM odd channel output tri-state when level-detect brake happened
#01
2
PWM odd channel output low level when level-detect brake happened
#10
3
PWM odd channel output high level when level-detect brake happened
#11
BRKP0EEN
Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
4
1
read-write
0
BKP0 pin as edge-detect brake source Disabled
#0
1
BKP0 pin as edge-detect brake source Enabled
#1
BRKP0LEN
Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
12
1
read-write
0
PWMx_BRAKE0 pin as level-detect brake source Disabled
#0
1
PWMx_BRAKE0 pin as level-detect brake source Enabled
#1
BRKP1EEN
Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
5
1
read-write
0
BKP1 pin as edge-detect brake source Disabled
#0
1
BKP1 pin as edge-detect brake source Enabled
#1
BRKP1LEN
Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
13
1
read-write
0
PWMx_BRAKE1 pin as level-detect brake source Disabled
#0
1
PWMx_BRAKE1 pin as level-detect brake source Enabled
#1
CPO0EBEN
Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
0
1
read-write
0
ACMP0_O as edge-detect brake source Disabled
#0
1
ACMP0_O as edge-detect brake source Enabled
#1
CPO0LBEN
Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
8
1
read-write
0
ACMP0_O as level-detect brake source Disabled
#0
1
ACMP0_O as level-detect brake source Enabled
#1
CPO1EBEN
Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
1
1
read-write
0
ACMP1_O as edge-detect brake source Disabled
#0
1
ACMP1_O as edge-detect brake source Enabled
#1
CPO1LBEN
Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
9
1
read-write
0
ACMP1_O as level-detect brake source Disabled
#0
1
ACMP1_O as level-detect brake source Enabled
#1
SYSEBEN
Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
7
1
read-write
0
System Fail condition as edge-detect brake source Disabled
#0
1
System Fail condition as edge-detect brake source Enabled
#1
SYSLBEN
Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
15
1
read-write
0
System Fail condition as level-detect brake source Disabled
#0
1
System Fail condition as level-detect brake source Enabled
#1
PWM_BRKCTL2_3
PWM_BRKCTL2_3
PWM Brake Edge Detect Control Register 2/3
0xCC
read-write
n
0x0
0x0
PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM Brake Edge Detect Control Register 4/5
0xD0
read-write
n
0x0
0x0
PWM_CAPCTL
PWM_CAPCTL
PWM Capture Control Register
0x204
read-write
n
0x0
0x0
CAPEN0
Capture Function Enable Bits
0
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN1
Capture Function Enable Bits
1
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN2
Capture Function Enable Bits
2
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN3
Capture Function Enable Bits
3
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN4
Capture Function Enable Bits
4
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN5
Capture Function Enable Bits
5
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPINV0
Capture Inverter Enable Bits
8
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
Capture Inverter Enable Bits
9
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV2
Capture Inverter Enable Bits
10
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
Capture Inverter Enable Bits
11
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV4
Capture Inverter Enable Bits
12
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV5
Capture Inverter Enable Bits
13
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
FCRLDEN0
Falling Capture Reload Enable Bits
24
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN1
Falling Capture Reload Enable Bits
25
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN2
Falling Capture Reload Enable Bits
26
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN3
Falling Capture Reload Enable Bits
27
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN4
Falling Capture Reload Enable Bits
28
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN5
Falling Capture Reload Enable Bits
29
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
RCRLDEN0
Rising Capture Reload Enable Bits
16
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN1
Rising Capture Reload Enable Bits
17
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN2
Rising Capture Reload Enable Bits
18
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN3
Rising Capture Reload Enable Bits
19
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN4
Rising Capture Reload Enable Bits
20
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN5
Rising Capture Reload Enable Bits
21
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
PWM_CAPIEN
PWM_CAPIEN
PWM Capture Interrupt Enable Register
0x250
read-write
n
0x0
0x0
CAPFIEN0
PWM Capture Falling Latch Interrupt Enable Bits
8
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN1
PWM Capture Falling Latch Interrupt Enable Bits
9
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN2
PWM Capture Falling Latch Interrupt Enable Bits
10
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN3
PWM Capture Falling Latch Interrupt Enable Bits
11
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN4
PWM Capture Falling Latch Interrupt Enable Bits
12
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN5
PWM Capture Falling Latch Interrupt Enable Bits
13
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPRIEN0
PWM Capture Rising Latch Interrupt Enable Bits
0
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN1
PWM Capture Rising Latch Interrupt Enable Bits
1
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN2
PWM Capture Rising Latch Interrupt Enable Bits
2
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN3
PWM Capture Rising Latch Interrupt Enable Bits
3
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN4
PWM Capture Rising Latch Interrupt Enable Bits
4
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN5
PWM Capture Rising Latch Interrupt Enable Bits
5
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
PWM_CAPIF
PWM_CAPIF
PWM Capture Interrupt Flag Register
0x254
read-write
n
0x0
0x0
CFLIF0
PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
8
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF1
PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
9
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF2
PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
10
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF3
PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
11
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF4
PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
12
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF5
PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
13
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CRLIF0
PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
0
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF1
PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
1
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF2
PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
2
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF3
PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
3
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF4
PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
4
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF5
PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
5
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
PWM_CAPINEN
PWM_CAPINEN
PWM Capture Input Enable Register
0x200
read-write
n
0x0
0x0
CAPINEN0
Capture Input Enable Bits
0
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN1
Capture Input Enable Bits
1
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN2
Capture Input Enable Bits
2
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN3
Capture Input Enable Bits
3
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN4
Capture Input Enable Bits
4
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN5
Capture Input Enable Bits
5
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
PWM_CAPSTS
PWM_CAPSTS
PWM Capture Status Register
0x208
read-only
n
0x0
0x0
CFLIFOV0
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
8
1
read-only
CFLIFOV1
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
9
1
read-only
CFLIFOV2
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
10
1
read-only
CFLIFOV3
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
11
1
read-only
CFLIFOV4
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
12
1
read-only
CFLIFOV5
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
13
1
read-only
CRLIFOV0
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
0
1
read-only
CRLIFOV1
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
1
1
read-only
CRLIFOV2
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
2
1
read-only
CRLIFOV3
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
3
1
read-only
CRLIFOV4
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
4
1
read-only
CRLIFOV5
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
5
1
read-only
PWM_CLKPSC0_1
PWM_CLKPSC0_1
PWM Clock Prescale Register 0/1
0x14
read-write
n
0x0
0x0
CLKPSC
PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1).
0
12
read-write
PWM_CLKPSC2_3
PWM_CLKPSC2_3
PWM Clock Prescale Register 2/3
0x18
read-write
n
0x0
0x0
PWM_CLKPSC4_5
PWM_CLKPSC4_5
PWM Clock Prescale Register 4/5
0x1C
read-write
n
0x0
0x0
PWM_CLKSRC
PWM_CLKSRC
PWM Clock Source Register
0x10
read-write
n
0x0
0x0
ECLKSRC0
PWM_CH01 External Clock Source Select
0
3
read-write
0
PWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
ECLKSRC2
PWM_CH23 External Clock Source Select
8
3
read-write
0
PWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
ECLKSRC4
PWM_CH45 External Clock Source Select
16
3
read-write
0
PWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
PWM_CMPBUF0
PWM_CMPBUF0
PWM CMPDAT0 Buffer
0x31C
read-only
n
0x0
0x0
CMPBUF
PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register.
0
16
read-only
PWM_CMPBUF1
PWM_CMPBUF1
PWM CMPDAT1 Buffer
0x320
read-write
n
0x0
0x0
PWM_CMPBUF2
PWM_CMPBUF2
PWM CMPDAT2 Buffer
0x324
read-write
n
0x0
0x0
PWM_CMPBUF3
PWM_CMPBUF3
PWM CMPDAT3 Buffer
0x328
read-write
n
0x0
0x0
PWM_CMPBUF4
PWM_CMPBUF4
PWM CMPDAT4 Buffer
0x32C
read-write
n
0x0
0x0
PWM_CMPBUF5
PWM_CMPBUF5
PWM CMPDAT5 Buffer
0x330
read-write
n
0x0
0x0
PWM_CMPDAT0
PWM_CMPDAT0
PWM Comparator Register 0
0x50
read-write
n
0x0
0x0
CMP
PWM Comparator Register\nCMP is used to compare with CNTR to generate PWM waveform, interrupt and trigger ADC.\nIn independent mode, PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode, PWM_CMPDAT0, 2, 4 denote as first compared point, and PWM_CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
0
16
read-write
PWM_CMPDAT1
PWM_CMPDAT1
PWM Comparator Register 1
0x54
read-write
n
0x0
0x0
PWM_CMPDAT2
PWM_CMPDAT2
PWM Comparator Register 2
0x58
read-write
n
0x0
0x0
PWM_CMPDAT3
PWM_CMPDAT3
PWM Comparator Register 3
0x5C
read-write
n
0x0
0x0
PWM_CMPDAT4
PWM_CMPDAT4
PWM Comparator Register 4
0x60
read-write
n
0x0
0x0
PWM_CMPDAT5
PWM_CMPDAT5
PWM Comparator Register 5
0x64
read-write
n
0x0
0x0
PWM_CNT0
PWM_CNT0
PWM Counter Register 0
0x90
read-only
n
0x0
0x0
CNT
PWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter.
0
16
read-only
DIRF
PWM Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is counting down
#0
1
Counter is counting up
#1
PWM_CNT2
PWM_CNT2
PWM Counter Register 2
0x98
read-write
n
0x0
0x0
PWM_CNT4
PWM_CNT4
PWM Counter Register 4
0xA0
read-write
n
0x0
0x0
PWM_CNTCLR
PWM_CNTCLR
PWM Clear Counter Register
0x24
read-write
n
0x0
0x0
CNTCLR0
Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
CNTCLR2
Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware.
2
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
CNTCLR4
Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware.
4
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
PWM_CNTEN
PWM_CNTEN
PWM Counter Enable Register
0x20
read-write
n
0x0
0x0
CNTEN0
PWM Counter Enable Bit 0
0
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
CNTEN2
PWM Counter Enable Bit 2
2
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
CNTEN4
PWM Counter Enable Bit 4
4
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
PWM_CTL0
PWM_CTL0
PWM Control Register 0
0x0
read-write
n
0x0
0x0
CTRLDn
Center Load Enable Bits\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
0
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt Disable
#0
1
ICE debug mode counter halt Enable
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects PWM output
#0
1
ICE debug mode acknowledgement disabled
#1
IMMLDENn
Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
16
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
PWM_CTL1
PWM_CTL1
PWM Control Register 1
0x4
read-write
n
0x0
0x0
CNTTYPE0
PWM Counter Behavior Type 0\nThe two bits control channel1 and channel0
0
2
read-write
0
Up counter type (supported in capture mode)
#00
1
Down count type (supported in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
CNTTYPE2
PWM Counter Behavior Type 2\nThe two bits control channel3 and channel2
4
2
read-write
0
Up counter type (supported in capture mode)
#00
1
Down count type (supported in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
CNTTYPE4
PWM Counter Behavior Type 4\nThe two bits control channel5 and channel4
8
2
read-write
0
Up counter type (supported in capture mode)
#00
1
Down count type (supported in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
OUTMODEn
PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode.
24
3
read-write
0
PWM independent mode
0
1
PWM complementary mode
1
PWM_DTCTL0_1
PWM_DTCTL0_1
PWM Dead-time Control Register 0/1
0x70
read-write
n
0x0
0x0
DTCKSEL
Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to REGWRPROT register.
24
1
read-write
0
Dead-time clock source from PWM_CLK
#0
1
Dead-time clock source from prescaler output
#1
DTCNT
Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
12
read-write
DTEN
Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
16
1
read-write
0
Dead-time insertion Disabled on the pin pair
#0
1
Dead-time insertion Enabled on the pin pair
#1
PWM_DTCTL2_3
PWM_DTCTL2_3
PWM Dead-time Control Register 2/3
0x74
read-write
n
0x0
0x0
PWM_DTCTL4_5
PWM_DTCTL4_5
PWM Dead-time Control Register 4/5
0x78
read-write
n
0x0
0x0
PWM_FAILBRK
PWM_FAILBRK
PWM System Fail Brake Control Register
0xC4
read-write
n
0x0
0x0
BODBRKEN
Brown-out Detection Trigger PWM Brake Function 0 Enable Bit
1
1
read-write
0
Brake Function triggered by BOD Disabled
#0
1
Brake Function triggered by BOD Enabled
#1
CORBRKEN
Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit
3
1
read-write
0
Brake Function triggered by Core lockup detection Disabled
#0
1
Brake Function triggered by Core lockup detection Enabled
#1
CSSBRKEN
Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit
0
1
read-write
0
Brake Function triggered by CSS detection Disabled
#0
1
Brake Function triggered by CSS detection Enabled
#1
RAMBRKEN
SRAM Parity Error Detection Trigger PWM Brake Function 0 Enable Bit
2
1
read-write
0
Brake Function triggered by SRAM parity error detection Disabled
#0
1
Brake Function triggered by SRAM parity error detection Enabled
#1
PWM_FCAPDAT0
PWM_FCAPDAT0
PWM Falling Capture Data Register 0
0x210
read-only
n
0x0
0x0
FCAPDAT
PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the PWM counter value will be saved in this register.
0
16
read-only
PWM_FCAPDAT1
PWM_FCAPDAT1
PWM Falling Capture Data Register 1
0x218
read-write
n
0x0
0x0
PWM_FCAPDAT2
PWM_FCAPDAT2
PWM Falling Capture Data Register 2
0x220
read-write
n
0x0
0x0
PWM_FCAPDAT3
PWM_FCAPDAT3
PWM Falling Capture Data Register 3
0x228
read-write
n
0x0
0x0
PWM_FCAPDAT4
PWM_FCAPDAT4
PWM Falling Capture Data Register 4
0x230
read-write
n
0x0
0x0
PWM_FCAPDAT5
PWM_FCAPDAT5
PWM Falling Capture Data Register 5
0x238
read-write
n
0x0
0x0
PWM_INTEN0
PWM_INTEN0
PWM Interrupt Enable Register 0
0xE0
read-write
n
0x0
0x0
CMPDIEN0
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
24
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN1
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
25
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN2
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
26
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN3
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
27
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN4
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
28
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN5
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
29
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN0
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
16
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN1
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
17
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN2
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
18
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN3
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
19
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN4
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
20
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN5
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
21
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN0
PWM Period Point Interrupt Enable Bit 0\nNote: When up-down counter type, period point means center point.
8
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
PIEN2
PWM Period Point Interrupt Enable Bit 2\nNote: When up-down counter type, period point means center point.
10
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
PIEN4
PWM Period Point Interrupt Enable Bit 4\nNote: When up-down counter type, period point means center point.
12
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN0
PWM Zero Point Interrupt Enable Bit 0\nNote: Odd channels will read always 0 at complementary mode.
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
ZIEN2
PWM Zero Point Interrupt Enable Bit 2\nNote: Odd channels will read always 0 at complementary mode.
2
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
ZIEN4
PWM Zero Point Interrupt Enable Bit 4\nNote: Odd channels will read always 0 at complementary mode.
4
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
PWM_INTEN1
PWM_INTEN1
PWM Interrupt Enable Register 1
0xE4
read-write
n
0x0
0x0
BRKEIEN0_1
PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
1
read-write
0
Edge-detect Brake interrupt for channel0/1 Disabled
#0
1
Edge-detect Brake interrupt for channel0/1 Enabled
#1
BRKEIEN2_3
PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
1
1
read-write
0
Edge-detect Brake interrupt for channel2/3 Disabled
#0
1
Edge-detect Brake interrupt for channel2/3 Enabled
#1
BRKEIEN4_5
PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bitr is write protected. Refer to SYS_REGLCTL register.
2
1
read-write
0
Edge-detect Brake interrupt for channel4/5 Disabled
#0
1
Edge-detect Brake interrupt for channel4/5 Enabled
#1
BRKLIEN0_1
PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
8
1
read-write
0
Level-detect Brake interrupt for channel0/1 Disabled
#0
1
Level-detect Brake interrupt for channel0/1 Enabled
#1
BRKLIEN2_3
PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
9
1
read-write
0
Level-detect Brake interrupt for channel2/3 Disabled
#0
1
Level-detect Brake interrupt for channel2/3 Enabled
#1
BRKLIEN4_5
PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
10
1
read-write
0
Level-detect Brake interrupt for channel4/5 Disabled
#0
1
Level-detect Brake interrupt for channel4/5 Enabled
#1
PWM_INTSTS0
PWM_INTSTS0
PWM Interrupt Flag Register 0
0xE8
read-write
n
0x0
0x0
CMPDIF0
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
24
1
read-write
CMPDIF1
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
25
1
read-write
CMPDIF2
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
26
1
read-write
CMPDIF3
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
27
1
read-write
CMPDIF4
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
28
1
read-write
CMPDIF5
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
29
1
read-write
CMPUIFn
PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
16
6
read-write
PIF0
PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0.\nNote: This bit can be cleared to 0 by software writing 1.
8
1
read-write
PIF2
PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2.\nNote: This bit can be cleared to 0 by software writing 1.
10
1
read-write
PIF4
PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4.\nNote: This bit can be cleared to 0 by software writing 1.
12
1
read-write
ZIF0
PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1.
0
1
read-write
ZIF2
PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1.
2
1
read-write
ZIF4
PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1.
4
1
read-write
PWM_INTSTS1
PWM_INTSTS1
PWM Interrupt Flag Register 1
0xEC
read-write
n
0x0
0x0
BRKEIF0
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF1
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
1
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF2
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
2
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF3
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
3
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF4
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
4
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF5
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
5
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKESTS0
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
16
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS1
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
17
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS2
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
18
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS3
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
19
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS4
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
20
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS5
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
21
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKLIF0
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
8
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF1
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
9
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF2
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
10
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF3
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
11
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF4
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
12
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF5
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
13
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLSTS0
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
24
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS1
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
25
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS2
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
26
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS3
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
27
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS4
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
28
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS5
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
29
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
PWM_MSK
PWM_MSK
PWM Mask Data Register
0xBC
read-write
n
0x0
0x0
MSKDAT0
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
0
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT1
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
1
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT2
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
2
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT3
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
3
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT4
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
4
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT5
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
5
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
PWM_MSKEN
PWM_MSKEN
PWM Mask Enable Register
0xB8
read-write
n
0x0
0x0
MSKEN0
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
0
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN1
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
1
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN2
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
2
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN3
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
3
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN4
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
4
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN5
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
5
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
PWM_PBUF0
PWM_PBUF0
PWM PERIOD0 Buffer
0x304
read-only
n
0x0
0x0
PBUF
PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register.
0
16
read-only
PWM_PBUF2
PWM_PBUF2
PWM PERIOD2 Buffer
0x30C
read-write
n
0x0
0x0
PWM_PBUF4
PWM_PBUF4
PWM PERIOD4 Buffer
0x314
read-write
n
0x0
0x0
PWM_PDMACAP0_1
PWM_PDMACAP0_1
PWM Capture Channel 01 PDMA Register
0x240
read-only
n
0x0
0x0
CAPBUF
PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
0
16
read-only
PWM_PDMACAP2_3
PWM_PDMACAP2_3
PWM Capture Channel 23 PDMA Register
0x244
read-write
n
0x0
0x0
PWM_PDMACAP4_5
PWM_PDMACAP4_5
PWM Capture Channel 45 PDMA Register
0x248
read-write
n
0x0
0x0
PWM_PDMACTL
PWM_PDMACTL
PWM PDMA Control Register
0x23C
read-write
n
0x0
0x0
CAPMOD0_1
Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
1
2
read-write
0
Reserved.
#00
1
PWM_RCAPDAT0/1
#01
2
PWM_FCAPDAT0/1
#10
3
Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1
#11
CAPMOD2_3
Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
9
2
read-write
0
Reserved.
#00
1
PWM_RCAPDAT2/3
#01
2
PWM_FCAPDAT2/3
#10
3
Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3
#11
CAPMOD4_5
Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
17
2
read-write
0
Reserved.
#00
1
PWM_RCAPDAT4/5
#01
2
PWM_FCAPDAT4/5
#10
3
Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5
#11
CAPORD0_1
Capture Channel 0/1 Rising/Falling Order \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
3
1
read-write
0
PWM_FCAPDAT0/1 is the first captured data to memory
#0
1
PWM_RCAPDAT0/1 is the first captured data to memory
#1
CAPORD2_3
Capture Channel 2/3 Rising/Falling Order \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
11
1
read-write
0
PWM_FCAPDAT2/3 is the first captured data to memory
#0
1
PWM_RCAPDAT2/3 is the first captured data to memory
#1
CAPORD4_5
Capture Channel 4/5 Rising/Falling Order \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
19
1
read-write
0
PWM_FCAPDAT4/5 is the first captured data to memory
#0
1
PWM_RCAPDAT4/5 is the first captured data to memory
#1
CHEN0_1
Channel 0/1 PDMA Enable Bit\nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
0
1
read-write
0
Channel 0/1 PDMA function Disabled
#0
1
Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory
#1
CHEN2_3
Channel 2/3 PDMA Enable Bit\nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
8
1
read-write
0
Channel 2/3 PDMA function Disabled
#0
1
Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory
#1
CHEN4_5
Channel 4/5 PDMA Enable Bit\nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
16
1
read-write
0
Channel 4/5 PDMA function Disabled
#0
1
Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory
#1
CHSEL0_1
Select Channel 0/1 to Do PDMA Transfer \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
4
1
read-write
0
Channel0
#0
1
Channel1
#1
CHSEL2_3
Select Channel 2/3 to Do PDMA Transfer \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
12
1
read-write
0
Channel2
#0
1
Channel3
#1
CHSEL4_5
Select Channel 4/5 to Do PDMA Transfer \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
20
1
read-write
0
Channel4
#0
1
Channel5
#1
PWM_PERIOD0
PWM_PERIOD0
PWM Period Register 0
0x30
read-write
n
0x0
0x0
PERIOD
PWM Period Register\nUp-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.
0
16
read-write
PWM_PERIOD2
PWM_PERIOD2
PWM Period Register 2
0x38
read-write
n
0x0
0x0
PWM_PERIOD4
PWM_PERIOD4
PWM Period Register 4
0x40
read-write
n
0x0
0x0
PWM_POEN
PWM_POEN
PWM Output Enable Register
0xD8
read-write
n
0x0
0x0
POEN0
PWM Pin Output Enable Bits
0
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN1
PWM Pin Output Enable Bits
1
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN2
PWM Pin Output Enable Bits
2
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN3
PWM Pin Output Enable Bits
3
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN4
PWM Pin Output Enable Bits
4
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN5
PWM Pin Output Enable Bits
5
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
PWM_POLCTL
PWM_POLCTL
PWM Pin Polar Inverse Register
0xD4
read-write
n
0x0
0x0
PINV0
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
0
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV1
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
1
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV2
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
2
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV3
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
3
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV4
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
4
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV5
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
5
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PWM_RCAPDAT0
PWM_RCAPDAT0
PWM Rising Capture Data Register 0
0x20C
read-only
n
0x0
0x0
RCAPDAT
PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the PWM counter value will be saved in this register.
0
16
read-only
PWM_RCAPDAT1
PWM_RCAPDAT1
PWM Rising Capture Data Register 1
0x214
read-write
n
0x0
0x0
PWM_RCAPDAT2
PWM_RCAPDAT2
PWM Rising Capture Data Register 2
0x21C
read-write
n
0x0
0x0
PWM_RCAPDAT3
PWM_RCAPDAT3
PWM Rising Capture Data Register 3
0x224
read-write
n
0x0
0x0
PWM_RCAPDAT4
PWM_RCAPDAT4
PWM Rising Capture Data Register 4
0x22C
read-write
n
0x0
0x0
PWM_RCAPDAT5
PWM_RCAPDAT5
PWM Rising Capture Data Register 5
0x234
read-write
n
0x0
0x0
PWM_SSCTL
PWM_SSCTL
PWM Synchronous Start Control Register
0x110
read-write
n
0x0
0x0
SSEN0
PWM Synchronous Start Function Enable Bit 0\nWhen synchronous start function is enabled, the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
0
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSEN2
PWM Synchronous Start Function Enable Bit 2\nWhen synchronous start function is enabled, the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
2
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSEN4
PWM Synchronous Start Function Enable Bit 4\nWhen synchronous start function is enabled, the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
4
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSRC
PWM Synchronous Start Source Select Bits
8
2
read-write
0
Synchronous start source come from PWM0
#00
1
Synchronous start source come from PWM1
#01
2
Reserved.
#10
3
Reserved.
#11
PWM_SSTRG
PWM_SSTRG
PWM Synchronous Start Trigger Register
0x114
write-only
n
0x0
0x0
CNTSEN
PWM Counter Synchronous Start Enable (Write Only)\nPWM counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.
0
1
write-only
PWM_STATUS
PWM_STATUS
PWM Status Register
0x120
read-write
n
0x0
0x0
ADCTRG0
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
16
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG1
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
17
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG2
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
18
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG3
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
19
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG4
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
20
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG5
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
21
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
CNTMAX0
Time-base Counter 0 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
0
1
read-write
0
indicates the time-base counter never reached its maximum value 0xFFFF
#0
1
indicates the time-base counter reached its maximum value
#1
CNTMAX2
Time-base Counter 2 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
2
1
read-write
0
indicates the time-base counter never reached its maximum value 0xFFFF
#0
1
indicates the time-base counter reached its maximum value
#1
CNTMAX4
Time-base Counter 4 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
4
1
read-write
0
The time-base counter never reached its maximum value 0xFFFF
#0
1
The time-base counter reached its maximum value
#1
PWM_SWBRK
PWM_SWBRK
PWM Software Brake Control Register
0xDC
write-only
n
0x0
0x0
BRKETRG0
PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
1
write-only
BRKETRG2
PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
1
1
write-only
BRKETRG4
PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
2
1
write-only
BRKLTRG0
PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
8
1
write-only
BRKLTRG2
PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
9
1
write-only
BRKLTRG4
PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
10
1
write-only
PWM_WGCTL0
PWM_WGCTL0
PWM Generation Register 0
0xB0
read-write
n
0x0
0x0
PRDPCTL0
PWM Period (Center) Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type.
16
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL1
PWM Period (Center) Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type.
18
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL2
PWM Period (Center) Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type.
20
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL3
PWM Period (Center) Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type.
22
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL4
PWM Period (Center) Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type.
24
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL5
PWM Period (Center) Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type.
26
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
ZPCTL0
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
0
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL1
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
2
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL2
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
4
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL3
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
6
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL4
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
8
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL5
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
10
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
PWM_WGCTL1
PWM_WGCTL1
PWM Generation Register 1
0xB4
read-write
n
0x0
0x0
CMPDCTL0
PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
16
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL1
PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
18
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL2
PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
20
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL3
PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
22
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL4
PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
24
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL5
PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
26
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPUCTL0
PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
0
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL1
PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
2
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL2
PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
4
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL3
PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
6
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL4
PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
8
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL5
PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
10
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
PWM1
PWM Register Map
PWM
0x0
0x0
0x8
registers
n
0x10
0x18
registers
n
0x110
0x8
registers
n
0x120
0x4
registers
n
0x200
0x4C
registers
n
0x250
0x8
registers
n
0x30
0x4
registers
n
0x304
0x4
registers
n
0x30C
0x4
registers
n
0x314
0x4
registers
n
0x31C
0x18
registers
n
0x38
0x4
registers
n
0x40
0x4
registers
n
0x50
0x18
registers
n
0x70
0xC
registers
n
0x90
0x4
registers
n
0x98
0x4
registers
n
0xA0
0x4
registers
n
0xB0
0x40
registers
n
0xF8
0x8
registers
n
PWM_ADCTS0
PWM_ADCTS0
PWM Trigger ADC Source Select Register 0
0xF8
read-write
n
0x0
0x0
TRGEN0
PWM_CH0 Trigger ADC Enable Bit
7
1
read-write
0
PWM_CH0 Trigger ADC function Disabled
#0
1
PWM_CH0 Trigger ADC function Enabled
#1
TRGEN1
PWM_CH1 Trigger ADC Enable Bit
15
1
read-write
0
PWM_CH1 Trigger ADC function Disabled
#0
1
PWM_CH1 Trigger ADC function Enabled
#1
TRGEN2
PWM_CH2 Trigger ADC Enable Bit
23
1
read-write
0
PWM_CH2 Trigger ADC function Disabled
#0
1
PWM_CH2 Trigger ADC function Enabled
#1
TRGEN3
PWM_CH3 Trigger ADC Enable Bit
31
1
read-write
0
PWM_CH3 Trigger ADC function Disabled
#0
1
PWM_CH3 Trigger ADC function Enabled
#1
TRGSEL0
PWM_CH0 Trigger ADC Source Select
0
4
read-write
0
PWM_CH0 zero point
#0000
1
PWM_CH0 period point
#0001
2
PWM_CH0 zero or period point
#0010
3
PWM_CH0 up-count CMPDAT point
#0011
4
PWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH1 up-count CMPDAT point
#1000
9
PWM_CH1 down-count CMPDAT point
#1001
TRGSEL1
PWM_CH1 Trigger ADC Source Select
8
4
read-write
0
PWM_CH0 zero point
#0000
1
PWM_CH0 period point
#0001
2
PWM_CH0 zero or period point
#0010
3
PWM_CH0 up-count CMPDAT point
#0011
4
PWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH1 up-count CMPDAT point
#1000
9
PWM_CH1 down-count CMPDAT point
#1001
TRGSEL2
PWM_CH2 Trigger ADC Source Select
16
4
read-write
0
PWM_CH2 zero point
#0000
1
PWM_CH2 period point
#0001
2
PWM_CH2 zero or period point
#0010
3
PWM_CH2 up-count CMPDAT point
#0011
4
PWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH3 up-count CMPDAT point
#1000
9
PWM_CH3 down-count CMPDAT point
#1001
TRGSEL3
PWM_CH3 Trigger ADC Source Select
24
4
read-write
0
PWM_CH2 zero point
#0000
1
PWM_CH2 period point
#0001
2
PWM_CH2 zero or period point
#0010
3
PWM_CH2 up-count CMPDAT point
#0011
4
PWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH3 up-count CMPDAT point
#1000
9
PWM_CH3 down-count CMPDAT point
#1001
PWM_ADCTS1
PWM_ADCTS1
PWM Trigger ADC Source Select Register 1
0xFC
read-write
n
0x0
0x0
TRGEN4
PWM_CH4 Trigger ADC Enable Bit
7
1
read-write
0
PWM_CH4 Trigger ADC function Disabled
#0
1
PWM_CH4 Trigger ADC function Enabled
#1
TRGEN5
PWM_CH5 Trigger ADC Enable Bit
15
1
read-write
0
PWM_CH5 Trigger ADC function Disabled
#0
1
PWM_CH5 Trigger ADC function Enabled
#1
TRGSEL4
PWM_CH4 Trigger ADC Source Select
0
4
read-write
0
PWM_CH4 zero point
#0000
1
PWM_CH4 period point
#0001
2
PWM_CH4 zero or period point
#0010
3
PWM_CH4 up-count CMPDAT point
#0011
4
PWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH5 up-count CMPDAT point
#1000
9
PWM_CH5 down-count CMPDAT point
#1001
TRGSEL5
PWM_CH5 Trigger ADC Source Select
8
4
read-write
0
PWM_CH4 zero point
#0000
1
PWM_CH4 period point
#0001
2
PWM_CH4 zero or period point
#0010
3
PWM_CH4 up-count CMPDAT point
#0011
4
PWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH5 up-count CMPDAT point
#1000
9
PWM_CH5 down-count CMPDAT point
#1001
PWM_BNF
PWM_BNF
PWM Brake Noise Filter Register
0xC0
read-write
n
0x0
0x0
BK0SRC
Brake 0 Pin Source Select\nFor PWM0 setting:
16
1
read-write
0
Brake 0 pin source come from PWM0_BRAKE0.\nBrake 0 pin source come from PWM1_BRAKE0
#0
1
Brake 0 pin source come from PWM1_BRAKE0.\nBrake 0 pin source come from PWM0_BRAKE0
#1
BK1SRC
Brake 1 Pin Source Select\nFor PWM0 setting:
24
1
read-write
0
Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1
#0
1
Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1
#1
BRK0FCNT
Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
4
3
read-write
BRK0NFEN
PWM Brake 0 Noise Filter Enable Bit
0
1
read-write
0
Noise filter of PWM Brake 0 Disabled
#0
1
Noise filter of PWM Brake 0 Enabled
#1
BRK0NFSEL
Brake 0 Edge Detector Filter Clock Selection
1
3
read-write
0
Filter clock = HCLK
#000
1
Filter clock = HCLK/2
#001
2
Filter clock = HCLK/4
#010
3
Filter clock = HCLK/8
#011
4
Filter clock = HCLK/16
#100
5
Filter clock = HCLK/32
#101
6
Filter clock = HCLK/64
#110
7
Filter clock = HCLK/128
#111
BRK0PINV
Brake 0 Pin Inverse
7
1
read-write
0
The state of pin PWMx_BRAKE0 is passed to the negative edge detector
#0
1
The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector
#1
BRK1FCNT
Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
12
3
read-write
BRK1NFEN
PWM Brake 1 Noise Filter Enable Bit
8
1
read-write
0
Noise filter of PWM Brake 1 Disabled
#0
1
Noise filter of PWM Brake 1 Enabled
#1
BRK1NFSEL
Brake 1 Edge Detector Filter Clock Selection
9
3
read-write
0
Filter clock = HCLK
#000
1
Filter clock = HCLK/2
#001
2
Filter clock = HCLK/4
#010
3
Filter clock = HCLK/8
#011
4
Filter clock = HCLK/16
#100
5
Filter clock = HCLK/32
#101
6
Filter clock = HCLK/64
#110
7
Filter clock = HCLK/128
#111
BRK1PINV
Brake 1 Pin Inverse
15
1
read-write
0
The state of pin PWMx_BRAKE1 is passed to the negative edge detector
#0
1
The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector
#1
PWM_BRKCTL0_1
PWM_BRKCTL0_1
PWM Brake Edge Detect Control Register 0/1
0xC8
read-write
n
0x0
0x0
BRKAEVEN
PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register.
16
2
read-write
0
PWM even channel level-detect brake function not affect channel output
#00
1
PWM even channel output tri-state when level-detect brake happened
#01
2
PWM even channel output low level when level-detect brake happened
#10
3
PWM even channel output high level when level-detect brake happened
#11
BRKAODD
PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register.
18
2
read-write
0
PWM odd channel level-detect brake function not affect channel output
#00
1
PWM odd channel output tri-state when level-detect brake happened
#01
2
PWM odd channel output low level when level-detect brake happened
#10
3
PWM odd channel output high level when level-detect brake happened
#11
BRKP0EEN
Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
4
1
read-write
0
BKP0 pin as edge-detect brake source Disabled
#0
1
BKP0 pin as edge-detect brake source Enabled
#1
BRKP0LEN
Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
12
1
read-write
0
PWMx_BRAKE0 pin as level-detect brake source Disabled
#0
1
PWMx_BRAKE0 pin as level-detect brake source Enabled
#1
BRKP1EEN
Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
5
1
read-write
0
BKP1 pin as edge-detect brake source Disabled
#0
1
BKP1 pin as edge-detect brake source Enabled
#1
BRKP1LEN
Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
13
1
read-write
0
PWMx_BRAKE1 pin as level-detect brake source Disabled
#0
1
PWMx_BRAKE1 pin as level-detect brake source Enabled
#1
CPO0EBEN
Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
0
1
read-write
0
ACMP0_O as edge-detect brake source Disabled
#0
1
ACMP0_O as edge-detect brake source Enabled
#1
CPO0LBEN
Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
8
1
read-write
0
ACMP0_O as level-detect brake source Disabled
#0
1
ACMP0_O as level-detect brake source Enabled
#1
CPO1EBEN
Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
1
1
read-write
0
ACMP1_O as edge-detect brake source Disabled
#0
1
ACMP1_O as edge-detect brake source Enabled
#1
CPO1LBEN
Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
9
1
read-write
0
ACMP1_O as level-detect brake source Disabled
#0
1
ACMP1_O as level-detect brake source Enabled
#1
SYSEBEN
Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
7
1
read-write
0
System Fail condition as edge-detect brake source Disabled
#0
1
System Fail condition as edge-detect brake source Enabled
#1
SYSLBEN
Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
15
1
read-write
0
System Fail condition as level-detect brake source Disabled
#0
1
System Fail condition as level-detect brake source Enabled
#1
PWM_BRKCTL2_3
PWM_BRKCTL2_3
PWM Brake Edge Detect Control Register 2/3
0xCC
read-write
n
0x0
0x0
PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM Brake Edge Detect Control Register 4/5
0xD0
read-write
n
0x0
0x0
PWM_CAPCTL
PWM_CAPCTL
PWM Capture Control Register
0x204
read-write
n
0x0
0x0
CAPEN0
Capture Function Enable Bits
0
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN1
Capture Function Enable Bits
1
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN2
Capture Function Enable Bits
2
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN3
Capture Function Enable Bits
3
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN4
Capture Function Enable Bits
4
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN5
Capture Function Enable Bits
5
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPINV0
Capture Inverter Enable Bits
8
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
Capture Inverter Enable Bits
9
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV2
Capture Inverter Enable Bits
10
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
Capture Inverter Enable Bits
11
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV4
Capture Inverter Enable Bits
12
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV5
Capture Inverter Enable Bits
13
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
FCRLDEN0
Falling Capture Reload Enable Bits
24
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN1
Falling Capture Reload Enable Bits
25
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN2
Falling Capture Reload Enable Bits
26
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN3
Falling Capture Reload Enable Bits
27
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN4
Falling Capture Reload Enable Bits
28
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN5
Falling Capture Reload Enable Bits
29
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
RCRLDEN0
Rising Capture Reload Enable Bits
16
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN1
Rising Capture Reload Enable Bits
17
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN2
Rising Capture Reload Enable Bits
18
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN3
Rising Capture Reload Enable Bits
19
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN4
Rising Capture Reload Enable Bits
20
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN5
Rising Capture Reload Enable Bits
21
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
PWM_CAPIEN
PWM_CAPIEN
PWM Capture Interrupt Enable Register
0x250
read-write
n
0x0
0x0
CAPFIEN0
PWM Capture Falling Latch Interrupt Enable Bits
8
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN1
PWM Capture Falling Latch Interrupt Enable Bits
9
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN2
PWM Capture Falling Latch Interrupt Enable Bits
10
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN3
PWM Capture Falling Latch Interrupt Enable Bits
11
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN4
PWM Capture Falling Latch Interrupt Enable Bits
12
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN5
PWM Capture Falling Latch Interrupt Enable Bits
13
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPRIEN0
PWM Capture Rising Latch Interrupt Enable Bits
0
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN1
PWM Capture Rising Latch Interrupt Enable Bits
1
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN2
PWM Capture Rising Latch Interrupt Enable Bits
2
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN3
PWM Capture Rising Latch Interrupt Enable Bits
3
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN4
PWM Capture Rising Latch Interrupt Enable Bits
4
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN5
PWM Capture Rising Latch Interrupt Enable Bits
5
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
PWM_CAPIF
PWM_CAPIF
PWM Capture Interrupt Flag Register
0x254
read-write
n
0x0
0x0
CFLIF0
PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
8
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF1
PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
9
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF2
PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
10
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF3
PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
11
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF4
PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
12
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF5
PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
13
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CRLIF0
PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
0
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF1
PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
1
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF2
PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
2
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF3
PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
3
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF4
PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
4
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF5
PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it.
5
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
PWM_CAPINEN
PWM_CAPINEN
PWM Capture Input Enable Register
0x200
read-write
n
0x0
0x0
CAPINEN0
Capture Input Enable Bits
0
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN1
Capture Input Enable Bits
1
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN2
Capture Input Enable Bits
2
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN3
Capture Input Enable Bits
3
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN4
Capture Input Enable Bits
4
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN5
Capture Input Enable Bits
5
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
PWM_CAPSTS
PWM_CAPSTS
PWM Capture Status Register
0x208
read-only
n
0x0
0x0
CFLIFOV0
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
8
1
read-only
CFLIFOV1
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
9
1
read-only
CFLIFOV2
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
10
1
read-only
CFLIFOV3
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
11
1
read-only
CFLIFOV4
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
12
1
read-only
CFLIFOV5
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
13
1
read-only
CRLIFOV0
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
0
1
read-only
CRLIFOV1
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
1
1
read-only
CRLIFOV2
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
2
1
read-only
CRLIFOV3
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
3
1
read-only
CRLIFOV4
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
4
1
read-only
CRLIFOV5
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
5
1
read-only
PWM_CLKPSC0_1
PWM_CLKPSC0_1
PWM Clock Prescale Register 0/1
0x14
read-write
n
0x0
0x0
CLKPSC
PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1).
0
12
read-write
PWM_CLKPSC2_3
PWM_CLKPSC2_3
PWM Clock Prescale Register 2/3
0x18
read-write
n
0x0
0x0
PWM_CLKPSC4_5
PWM_CLKPSC4_5
PWM Clock Prescale Register 4/5
0x1C
read-write
n
0x0
0x0
PWM_CLKSRC
PWM_CLKSRC
PWM Clock Source Register
0x10
read-write
n
0x0
0x0
ECLKSRC0
PWM_CH01 External Clock Source Select
0
3
read-write
0
PWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
ECLKSRC2
PWM_CH23 External Clock Source Select
8
3
read-write
0
PWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
ECLKSRC4
PWM_CH45 External Clock Source Select
16
3
read-write
0
PWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
PWM_CMPBUF0
PWM_CMPBUF0
PWM CMPDAT0 Buffer
0x31C
read-only
n
0x0
0x0
CMPBUF
PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register.
0
16
read-only
PWM_CMPBUF1
PWM_CMPBUF1
PWM CMPDAT1 Buffer
0x320
read-write
n
0x0
0x0
PWM_CMPBUF2
PWM_CMPBUF2
PWM CMPDAT2 Buffer
0x324
read-write
n
0x0
0x0
PWM_CMPBUF3
PWM_CMPBUF3
PWM CMPDAT3 Buffer
0x328
read-write
n
0x0
0x0
PWM_CMPBUF4
PWM_CMPBUF4
PWM CMPDAT4 Buffer
0x32C
read-write
n
0x0
0x0
PWM_CMPBUF5
PWM_CMPBUF5
PWM CMPDAT5 Buffer
0x330
read-write
n
0x0
0x0
PWM_CMPDAT0
PWM_CMPDAT0
PWM Comparator Register 0
0x50
read-write
n
0x0
0x0
CMP
PWM Comparator Register\nCMP is used to compare with CNTR to generate PWM waveform, interrupt and trigger ADC.\nIn independent mode, PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode, PWM_CMPDAT0, 2, 4 denote as first compared point, and PWM_CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
0
16
read-write
PWM_CMPDAT1
PWM_CMPDAT1
PWM Comparator Register 1
0x54
read-write
n
0x0
0x0
PWM_CMPDAT2
PWM_CMPDAT2
PWM Comparator Register 2
0x58
read-write
n
0x0
0x0
PWM_CMPDAT3
PWM_CMPDAT3
PWM Comparator Register 3
0x5C
read-write
n
0x0
0x0
PWM_CMPDAT4
PWM_CMPDAT4
PWM Comparator Register 4
0x60
read-write
n
0x0
0x0
PWM_CMPDAT5
PWM_CMPDAT5
PWM Comparator Register 5
0x64
read-write
n
0x0
0x0
PWM_CNT0
PWM_CNT0
PWM Counter Register 0
0x90
read-only
n
0x0
0x0
CNT
PWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter.
0
16
read-only
DIRF
PWM Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is counting down
#0
1
Counter is counting up
#1
PWM_CNT2
PWM_CNT2
PWM Counter Register 2
0x98
read-write
n
0x0
0x0
PWM_CNT4
PWM_CNT4
PWM Counter Register 4
0xA0
read-write
n
0x0
0x0
PWM_CNTCLR
PWM_CNTCLR
PWM Clear Counter Register
0x24
read-write
n
0x0
0x0
CNTCLR0
Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
CNTCLR2
Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware.
2
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
CNTCLR4
Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware.
4
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
PWM_CNTEN
PWM_CNTEN
PWM Counter Enable Register
0x20
read-write
n
0x0
0x0
CNTEN0
PWM Counter Enable Bit 0
0
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
CNTEN2
PWM Counter Enable Bit 2
2
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
CNTEN4
PWM Counter Enable Bit 4
4
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
PWM_CTL0
PWM_CTL0
PWM Control Register 0
0x0
read-write
n
0x0
0x0
CTRLDn
Center Load Enable Bits\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
0
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt Disable
#0
1
ICE debug mode counter halt Enable
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects PWM output
#0
1
ICE debug mode acknowledgement disabled
#1
IMMLDENn
Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
16
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
PWM_CTL1
PWM_CTL1
PWM Control Register 1
0x4
read-write
n
0x0
0x0
CNTTYPE0
PWM Counter Behavior Type 0\nThe two bits control channel1 and channel0
0
2
read-write
0
Up counter type (supported in capture mode)
#00
1
Down count type (supported in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
CNTTYPE2
PWM Counter Behavior Type 2\nThe two bits control channel3 and channel2
4
2
read-write
0
Up counter type (supported in capture mode)
#00
1
Down count type (supported in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
CNTTYPE4
PWM Counter Behavior Type 4\nThe two bits control channel5 and channel4
8
2
read-write
0
Up counter type (supported in capture mode)
#00
1
Down count type (supported in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
OUTMODEn
PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode.
24
3
read-write
0
PWM independent mode
0
1
PWM complementary mode
1
PWM_DTCTL0_1
PWM_DTCTL0_1
PWM Dead-time Control Register 0/1
0x70
read-write
n
0x0
0x0
DTCKSEL
Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to REGWRPROT register.
24
1
read-write
0
Dead-time clock source from PWM_CLK
#0
1
Dead-time clock source from prescaler output
#1
DTCNT
Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
12
read-write
DTEN
Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
16
1
read-write
0
Dead-time insertion Disabled on the pin pair
#0
1
Dead-time insertion Enabled on the pin pair
#1
PWM_DTCTL2_3
PWM_DTCTL2_3
PWM Dead-time Control Register 2/3
0x74
read-write
n
0x0
0x0
PWM_DTCTL4_5
PWM_DTCTL4_5
PWM Dead-time Control Register 4/5
0x78
read-write
n
0x0
0x0
PWM_FAILBRK
PWM_FAILBRK
PWM System Fail Brake Control Register
0xC4
read-write
n
0x0
0x0
BODBRKEN
Brown-out Detection Trigger PWM Brake Function 0 Enable Bit
1
1
read-write
0
Brake Function triggered by BOD Disabled
#0
1
Brake Function triggered by BOD Enabled
#1
CORBRKEN
Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit
3
1
read-write
0
Brake Function triggered by Core lockup detection Disabled
#0
1
Brake Function triggered by Core lockup detection Enabled
#1
CSSBRKEN
Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit
0
1
read-write
0
Brake Function triggered by CSS detection Disabled
#0
1
Brake Function triggered by CSS detection Enabled
#1
RAMBRKEN
SRAM Parity Error Detection Trigger PWM Brake Function 0 Enable Bit
2
1
read-write
0
Brake Function triggered by SRAM parity error detection Disabled
#0
1
Brake Function triggered by SRAM parity error detection Enabled
#1
PWM_FCAPDAT0
PWM_FCAPDAT0
PWM Falling Capture Data Register 0
0x210
read-only
n
0x0
0x0
FCAPDAT
PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the PWM counter value will be saved in this register.
0
16
read-only
PWM_FCAPDAT1
PWM_FCAPDAT1
PWM Falling Capture Data Register 1
0x218
read-write
n
0x0
0x0
PWM_FCAPDAT2
PWM_FCAPDAT2
PWM Falling Capture Data Register 2
0x220
read-write
n
0x0
0x0
PWM_FCAPDAT3
PWM_FCAPDAT3
PWM Falling Capture Data Register 3
0x228
read-write
n
0x0
0x0
PWM_FCAPDAT4
PWM_FCAPDAT4
PWM Falling Capture Data Register 4
0x230
read-write
n
0x0
0x0
PWM_FCAPDAT5
PWM_FCAPDAT5
PWM Falling Capture Data Register 5
0x238
read-write
n
0x0
0x0
PWM_INTEN0
PWM_INTEN0
PWM Interrupt Enable Register 0
0xE0
read-write
n
0x0
0x0
CMPDIEN0
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
24
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN1
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
25
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN2
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
26
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN3
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
27
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN4
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
28
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN5
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
29
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN0
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
16
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN1
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
17
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN2
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
18
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN3
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
19
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN4
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
20
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN5
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
21
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN0
PWM Period Point Interrupt Enable Bit 0\nNote: When up-down counter type, period point means center point.
8
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
PIEN2
PWM Period Point Interrupt Enable Bit 2\nNote: When up-down counter type, period point means center point.
10
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
PIEN4
PWM Period Point Interrupt Enable Bit 4\nNote: When up-down counter type, period point means center point.
12
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN0
PWM Zero Point Interrupt Enable Bit 0\nNote: Odd channels will read always 0 at complementary mode.
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
ZIEN2
PWM Zero Point Interrupt Enable Bit 2\nNote: Odd channels will read always 0 at complementary mode.
2
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
ZIEN4
PWM Zero Point Interrupt Enable Bit 4\nNote: Odd channels will read always 0 at complementary mode.
4
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
PWM_INTEN1
PWM_INTEN1
PWM Interrupt Enable Register 1
0xE4
read-write
n
0x0
0x0
BRKEIEN0_1
PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
1
read-write
0
Edge-detect Brake interrupt for channel0/1 Disabled
#0
1
Edge-detect Brake interrupt for channel0/1 Enabled
#1
BRKEIEN2_3
PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
1
1
read-write
0
Edge-detect Brake interrupt for channel2/3 Disabled
#0
1
Edge-detect Brake interrupt for channel2/3 Enabled
#1
BRKEIEN4_5
PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bitr is write protected. Refer to SYS_REGLCTL register.
2
1
read-write
0
Edge-detect Brake interrupt for channel4/5 Disabled
#0
1
Edge-detect Brake interrupt for channel4/5 Enabled
#1
BRKLIEN0_1
PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
8
1
read-write
0
Level-detect Brake interrupt for channel0/1 Disabled
#0
1
Level-detect Brake interrupt for channel0/1 Enabled
#1
BRKLIEN2_3
PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
9
1
read-write
0
Level-detect Brake interrupt for channel2/3 Disabled
#0
1
Level-detect Brake interrupt for channel2/3 Enabled
#1
BRKLIEN4_5
PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
10
1
read-write
0
Level-detect Brake interrupt for channel4/5 Disabled
#0
1
Level-detect Brake interrupt for channel4/5 Enabled
#1
PWM_INTSTS0
PWM_INTSTS0
PWM Interrupt Flag Register 0
0xE8
read-write
n
0x0
0x0
CMPDIF0
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
24
1
read-write
CMPDIF1
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
25
1
read-write
CMPDIF2
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
26
1
read-write
CMPDIF3
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
27
1
read-write
CMPDIF4
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
28
1
read-write
CMPDIF5
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
29
1
read-write
CMPUIFn
PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
16
6
read-write
PIF0
PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0.\nNote: This bit can be cleared to 0 by software writing 1.
8
1
read-write
PIF2
PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2.\nNote: This bit can be cleared to 0 by software writing 1.
10
1
read-write
PIF4
PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4.\nNote: This bit can be cleared to 0 by software writing 1.
12
1
read-write
ZIF0
PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1.
0
1
read-write
ZIF2
PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1.
2
1
read-write
ZIF4
PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1.
4
1
read-write
PWM_INTSTS1
PWM_INTSTS1
PWM Interrupt Flag Register 1
0xEC
read-write
n
0x0
0x0
BRKEIF0
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF1
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
1
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF2
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
2
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF3
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
3
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF4
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
4
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF5
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
5
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKESTS0
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
16
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS1
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
17
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS2
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
18
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS3
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
19
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS4
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
20
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS5
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
21
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKLIF0
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
8
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF1
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
9
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF2
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
10
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF3
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
11
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF4
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
12
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF5
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
13
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLSTS0
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
24
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS1
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
25
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS2
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
26
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS3
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
27
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS4
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
28
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS5
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
29
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
#1
PWM_MSK
PWM_MSK
PWM Mask Data Register
0xBC
read-write
n
0x0
0x0
MSKDAT0
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
0
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT1
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
1
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT2
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
2
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT3
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
3
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT4
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
4
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT5
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
5
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
PWM_MSKEN
PWM_MSKEN
PWM Mask Enable Register
0xB8
read-write
n
0x0
0x0
MSKEN0
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
0
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN1
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
1
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN2
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
2
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN3
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
3
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN4
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
4
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN5
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
5
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
PWM_PBUF0
PWM_PBUF0
PWM PERIOD0 Buffer
0x304
read-only
n
0x0
0x0
PBUF
PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register.
0
16
read-only
PWM_PBUF2
PWM_PBUF2
PWM PERIOD2 Buffer
0x30C
read-write
n
0x0
0x0
PWM_PBUF4
PWM_PBUF4
PWM PERIOD4 Buffer
0x314
read-write
n
0x0
0x0
PWM_PDMACAP0_1
PWM_PDMACAP0_1
PWM Capture Channel 01 PDMA Register
0x240
read-only
n
0x0
0x0
CAPBUF
PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
0
16
read-only
PWM_PDMACAP2_3
PWM_PDMACAP2_3
PWM Capture Channel 23 PDMA Register
0x244
read-write
n
0x0
0x0
PWM_PDMACAP4_5
PWM_PDMACAP4_5
PWM Capture Channel 45 PDMA Register
0x248
read-write
n
0x0
0x0
PWM_PDMACTL
PWM_PDMACTL
PWM PDMA Control Register
0x23C
read-write
n
0x0
0x0
CAPMOD0_1
Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
1
2
read-write
0
Reserved.
#00
1
PWM_RCAPDAT0/1
#01
2
PWM_FCAPDAT0/1
#10
3
Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1
#11
CAPMOD2_3
Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
9
2
read-write
0
Reserved.
#00
1
PWM_RCAPDAT2/3
#01
2
PWM_FCAPDAT2/3
#10
3
Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3
#11
CAPMOD4_5
Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
17
2
read-write
0
Reserved.
#00
1
PWM_RCAPDAT4/5
#01
2
PWM_FCAPDAT4/5
#10
3
Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5
#11
CAPORD0_1
Capture Channel 0/1 Rising/Falling Order \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
3
1
read-write
0
PWM_FCAPDAT0/1 is the first captured data to memory
#0
1
PWM_RCAPDAT0/1 is the first captured data to memory
#1
CAPORD2_3
Capture Channel 2/3 Rising/Falling Order \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
11
1
read-write
0
PWM_FCAPDAT2/3 is the first captured data to memory
#0
1
PWM_RCAPDAT2/3 is the first captured data to memory
#1
CAPORD4_5
Capture Channel 4/5 Rising/Falling Order \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
19
1
read-write
0
PWM_FCAPDAT4/5 is the first captured data to memory
#0
1
PWM_RCAPDAT4/5 is the first captured data to memory
#1
CHEN0_1
Channel 0/1 PDMA Enable Bit\nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
0
1
read-write
0
Channel 0/1 PDMA function Disabled
#0
1
Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory
#1
CHEN2_3
Channel 2/3 PDMA Enable Bit\nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
8
1
read-write
0
Channel 2/3 PDMA function Disabled
#0
1
Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory
#1
CHEN4_5
Channel 4/5 PDMA Enable Bit\nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
16
1
read-write
0
Channel 4/5 PDMA function Disabled
#0
1
Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory
#1
CHSEL0_1
Select Channel 0/1 to Do PDMA Transfer \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
4
1
read-write
0
Channel0
#0
1
Channel1
#1
CHSEL2_3
Select Channel 2/3 to Do PDMA Transfer \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
12
1
read-write
0
Channel2
#0
1
Channel3
#1
CHSEL4_5
Select Channel 4/5 to Do PDMA Transfer \nNote: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
20
1
read-write
0
Channel4
#0
1
Channel5
#1
PWM_PERIOD0
PWM_PERIOD0
PWM Period Register 0
0x30
read-write
n
0x0
0x0
PERIOD
PWM Period Register\nUp-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.
0
16
read-write
PWM_PERIOD2
PWM_PERIOD2
PWM Period Register 2
0x38
read-write
n
0x0
0x0
PWM_PERIOD4
PWM_PERIOD4
PWM Period Register 4
0x40
read-write
n
0x0
0x0
PWM_POEN
PWM_POEN
PWM Output Enable Register
0xD8
read-write
n
0x0
0x0
POEN0
PWM Pin Output Enable Bits
0
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN1
PWM Pin Output Enable Bits
1
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN2
PWM Pin Output Enable Bits
2
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN3
PWM Pin Output Enable Bits
3
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN4
PWM Pin Output Enable Bits
4
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN5
PWM Pin Output Enable Bits
5
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
PWM_POLCTL
PWM_POLCTL
PWM Pin Polar Inverse Register
0xD4
read-write
n
0x0
0x0
PINV0
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
0
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV1
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
1
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV2
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
2
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV3
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
3
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV4
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
4
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV5
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
5
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PWM_RCAPDAT0
PWM_RCAPDAT0
PWM Rising Capture Data Register 0
0x20C
read-only
n
0x0
0x0
RCAPDAT
PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the PWM counter value will be saved in this register.
0
16
read-only
PWM_RCAPDAT1
PWM_RCAPDAT1
PWM Rising Capture Data Register 1
0x214
read-write
n
0x0
0x0
PWM_RCAPDAT2
PWM_RCAPDAT2
PWM Rising Capture Data Register 2
0x21C
read-write
n
0x0
0x0
PWM_RCAPDAT3
PWM_RCAPDAT3
PWM Rising Capture Data Register 3
0x224
read-write
n
0x0
0x0
PWM_RCAPDAT4
PWM_RCAPDAT4
PWM Rising Capture Data Register 4
0x22C
read-write
n
0x0
0x0
PWM_RCAPDAT5
PWM_RCAPDAT5
PWM Rising Capture Data Register 5
0x234
read-write
n
0x0
0x0
PWM_SSCTL
PWM_SSCTL
PWM Synchronous Start Control Register
0x110
read-write
n
0x0
0x0
SSEN0
PWM Synchronous Start Function Enable Bit 0\nWhen synchronous start function is enabled, the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
0
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSEN2
PWM Synchronous Start Function Enable Bit 2\nWhen synchronous start function is enabled, the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
2
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSEN4
PWM Synchronous Start Function Enable Bit 4\nWhen synchronous start function is enabled, the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
4
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSRC
PWM Synchronous Start Source Select Bits
8
2
read-write
0
Synchronous start source come from PWM0
#00
1
Synchronous start source come from PWM1
#01
2
Reserved.
#10
3
Reserved.
#11
PWM_SSTRG
PWM_SSTRG
PWM Synchronous Start Trigger Register
0x114
write-only
n
0x0
0x0
CNTSEN
PWM Counter Synchronous Start Enable (Write Only)\nPWM counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.
0
1
write-only
PWM_STATUS
PWM_STATUS
PWM Status Register
0x120
read-write
n
0x0
0x0
ADCTRG0
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
16
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG1
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
17
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG2
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
18
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG3
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
19
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG4
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
20
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG5
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
21
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
CNTMAX0
Time-base Counter 0 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
0
1
read-write
0
indicates the time-base counter never reached its maximum value 0xFFFF
#0
1
indicates the time-base counter reached its maximum value
#1
CNTMAX2
Time-base Counter 2 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
2
1
read-write
0
indicates the time-base counter never reached its maximum value 0xFFFF
#0
1
indicates the time-base counter reached its maximum value
#1
CNTMAX4
Time-base Counter 4 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
4
1
read-write
0
The time-base counter never reached its maximum value 0xFFFF
#0
1
The time-base counter reached its maximum value
#1
PWM_SWBRK
PWM_SWBRK
PWM Software Brake Control Register
0xDC
write-only
n
0x0
0x0
BRKETRG0
PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
1
write-only
BRKETRG2
PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
1
1
write-only
BRKETRG4
PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
2
1
write-only
BRKLTRG0
PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
8
1
write-only
BRKLTRG2
PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
9
1
write-only
BRKLTRG4
PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
10
1
write-only
PWM_WGCTL0
PWM_WGCTL0
PWM Generation Register 0
0xB0
read-write
n
0x0
0x0
PRDPCTL0
PWM Period (Center) Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type.
16
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL1
PWM Period (Center) Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type.
18
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL2
PWM Period (Center) Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type.
20
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL3
PWM Period (Center) Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type.
22
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL4
PWM Period (Center) Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type.
24
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL5
PWM Period (Center) Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type.
26
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
ZPCTL0
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
0
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL1
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
2
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL2
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
4
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL3
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
6
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL4
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
8
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL5
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
10
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
PWM_WGCTL1
PWM_WGCTL1
PWM Generation Register 1
0xB4
read-write
n
0x0
0x0
CMPDCTL0
PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
16
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL1
PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
18
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL2
PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
20
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL3
PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
22
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL4
PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
24
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL5
PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
26
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPUCTL0
PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
0
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL1
PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
2
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL2
PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
4
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL3
PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
6
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL4
PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
8
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL5
PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
10
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
QSPIx
QSPI Register Map
QSPI
0x0
0x0
0x18
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
CLKDIV
QSPIx_CLKDIV
QSPI Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.\nNote: The time interval must be larger than or equal 8 peripheral clock cycles between releasing QSPI IP software reset and setting this clock divider register.
0
9
read-write
CTL
QSPIx_CTL
QSPI Control Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity
3
1
read-write
0
QSPI bus clock is idle low
#0
1
QSPI bus clock is idle high
#1
DATDIR
Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
20
1
read-write
0
QSPI data is input direction
#0
1
QSPI data is output direction
#1
DUALIOEN
Dual I/O Mode Enable Bit
21
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
DWIDTH
Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.
8
5
read-write
HALFDPX
QSPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for QSPI transfer. The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
14
1
read-write
0
QSPI operates in full-duplex transfer
#0
1
QSPI operates in half-duplex transfer
#1
LSB
Send LSB First
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the QSPIx TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPIx_RX)
#1
QUADIOEN
Quad I/O Mode Enable Bit
22
1
read-write
0
Quad I/O mode Disabled
#0
1
Quad I/O mode Enabled
#1
REORDER
Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXNEG
Receive on Negative Edge
1
1
read-write
0
Received data input signal is latched on the rising edge of QSPI bus clock
#0
1
Received data input signal is latched on the falling edge of QSPI bus clock
#1
RXONLY
Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode. In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status.
15
1
read-write
0
Receive-only mode Disabled
#0
1
Receive-only mode Enabled
#1
SLAVE
Slave Mode Control
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
QSPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the SPIEN (QSPIx_CTL[0]) and confirm the SPIENSTS (QSPIx_STATUS[15]) is 0.
0
1
read-write
0
Transfer control Disabled
#0
1
Transfer control Enabled
#1
SUSPITV
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV + 0.5) * period of QSPICLK clock cycle\nExample:
4
4
read-write
TWOBIT
2-bit Transfer Mode Enable Bit\nNote: When 2-bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
16
1
read-write
0
2-bit Transfer mode Disabled
#0
1
2-bit Transfer mode Enabled
#1
TXNEG
Transmit on Negative Edge
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of QSPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of QSPI bus clock
#1
UNITIEN
Unit Transfer Interrupt Enable Bit
17
1
read-write
0
QSPI unit transfer interrupt Disabled
#0
1
QSPI unit transfer interrupt Enabled
#1
FIFOCTL
QSPIx_FIFOCTL
QSPI FIFO Control Register
0x10
-1
read-write
n
0x0
0x0
RXFBCLR
Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared.
8
1
read-write
0
No effect
#0
1
Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
RXOVIEN
Receive FIFO Overrun Interrupt Enable Bit
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Receive Reset
0
1
read-write
0
No effect
#0
1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not
#1
RXTH
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
24
3
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Bit
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Receive Time-out Interrupt Enable Bit
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXFBCLR
Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared.
9
1
read-write
0
No effect
#0
1
Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
TXRST
Transmit Reset\nNote: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state.
1
1
read-write
0
No effect
#0
1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not
#1
TXTH
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
28
3
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt.
7
1
read-write
0
Slave TX underflow interrupt Disabled
#0
1
Slave TX underflow interrupt Enabled
#1
TXUFPOL
TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame.
6
1
read-write
0
The QSPI data out is keep 0 if there is TX underflow event in Slave mode
#0
1
The QSPI data out is keep 1 if there is TX underflow event in Slave mode
#1
PDMACTL
QSPIx_PDMACTL
QSPI PDMA Control Register
0xC
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0
#1
RXPDMAEN
Receive PDMA Enable Bit
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
Transmit PDMA Enable Bit\nNote: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
RX
QSPIx_RX
QSPI Data Receive Register
0x30
read-only
n
0x0
0x0
RX
Data Receive Register (Read Only)\nThere are 8-level FIFO buffers in this controller. The data receive register holds the data received from QSPI data input pin. If the RXEMPTY (QSPIx_STATUS[8) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
0
32
read-only
SSCTL
QSPIx_SSCTL
QSPI Slave Select Control Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit (Master Only)
3
1
read-write
0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0])
#0
1
Automatic slave selection function Enabled
#1
SLV3WIRE
Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPIx_CLK, QSPIx_MISO and QSPIx_MOSI pins.
4
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit
8
1
read-write
0
Slave mode bit count error interrupt Disabled
#0
1
Slave mode bit count error interrupt Enabled
#1
SLVTOCNT
Slave Mode Time-out Period\nIn Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled.
16
16
read-write
SLVTOIEN
Slave Mode Time-out Interrupt Enable Bit
5
1
read-write
0
Slave mode time-out interrupt Disabled
#0
1
Slave mode time-out interrupt Enabled
#1
SLVTORST
Slave Mode Time-out Reset Control
6
1
read-write
0
When Slave mode time-out event occurs, the TX and RX control circuit will not be reset
#0
1
When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware
#1
SLVURIEN
Slave Mode TX Under Run Interrupt Enable Bit
9
1
read-write
0
Slave mode TX under run interrupt Disabled
#0
1
Slave mode TX under run interrupt Enabled
#1
SS
Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0,
0
1
read-write
0
set the QSPIx_SS line to inactive state.\nKeep the QSPIx_SS line at inactive state
#0
1
set the QSPIx_SS line to active state.\nQSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit
12
1
read-write
0
Slave select active interrupt Disabled
#0
1
Slave select active interrupt Enabled
#1
SSACTPOL
Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (QSPIx_SS).
2
1
read-write
0
The slave selection signal QSPIx_SS is active low
#0
1
The slave selection signal QSPIx_SS is active high
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit
13
1
read-write
0
Slave select inactive interrupt Disabled
#0
1
Slave select inactive interrupt Enabled
#1
STATUS
QSPIx_STATUS
QSPI Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
0
1
read-only
0
QSPI controller is in idle state
#0
1
QSPI controller is in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
11
1
read-write
0
No FIFO is overrun
#0
1
Receive FIFO is overrun
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
6
1
read-write
0
No Slave mode bit count error event
#0
1
Slave mode bit count error event occurred
#1
SLVTOIF
Slave Time-out Interrupt Flag \nWhen the slave select is active and the value of SLVTOCNT is not 0, if the bus clock is detected, the slave time-out counter in QSPI controller logic will be started. When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPIx_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.\nNote: This bit will be cleared by writing 1 to it.
5
1
read-write
0
Slave time-out is not active
#0
1
Slave time-out is active
#1
SLVURIF
Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
7
1
read-write
0
No Slave TX under run event
#0
1
Slave TX under run event occurred
#1
SPIENSTS
QSPI Enable Status (Read Only)\nNote: The QSPI peripheral clock is asynchronous with the system clock. In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller.
15
1
read-only
0
QSPI controller Disabled
#0
1
QSPI controller Enabled
#1
SSACTIF
Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
2
1
read-write
0
Slave select active interrupt was cleared or not occurred
#0
1
Slave select active interrupt event occurred
#1
SSINAIF
Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
3
1
read-write
0
Slave select inactive interrupt was cleared or not occurred
#0
1
Slave select inactive interrupt event occurred
#1
SSLINE
Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status.
4
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
QSPI controller has finished one unit transfer
#1
TX
QSPIx_TX
QSPI Data Transmit Register
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]).\nIf DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the QSPI controller will perform a 32-bit transfer.\nNote: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
0
32
write-only
RTC
RTC Register Map
RTC
0x0
0x0
0x4
registers
n
0x100
0x4
registers
n
0x8
0x34
registers
n
CAL
RTC_CAL
RTC Calendar Loading Register
0x10
-1
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit (0~9)
0
4
read-write
MON
1-Month Calendar Digit (0~9)
8
4
read-write
TENDAY
10-Day Calendar Digit (0~3)
4
2
read-write
TENMON
10-Month Calendar Digit (0~1)
12
1
read-write
TENYEAR
10-Year Calendar Digit (0~9)
20
4
read-write
YEAR
1-Year Calendar Digit (0~9)
16
4
read-write
CALM
RTC_CALM
RTC Calendar Alarm Register
0x20
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit of Alarm Setting (0~9)
0
4
read-write
MON
1-Month Calendar Digit of Alarm Setting (0~9)
8
4
read-write
TENDAY
10-Day Calendar Digit of Alarm Setting (0~3)
4
2
read-write
TENMON
10-Month Calendar Digit of Alarm Setting (0~1)
12
1
read-write
TENYEAR
10-Year Calendar Digit of Alarm Setting (0~9)
20
4
read-write
YEAR
1-Year Calendar Digit of Alarm Setting (0~9)
16
4
read-write
CAMSK
RTC_CAMSK
RTC Calendar Alarm Mask Register
0x38
read-write
n
0x0
0x0
MDAY
Mask 1-Day Calendar Digit of Alarm Setting (0~9)
0
1
read-write
MMON
Mask 1-Month Calendar Digit of Alarm Setting (0~9)
2
1
read-write
MTENDAY
Mask 10-Day Calendar Digit of Alarm Setting (0~3)
1
1
read-write
MTENMON
Mask 10-Month Calendar Digit of Alarm Setting (0~1)
3
1
read-write
MTENYEAR
Mask 10-Year Calendar Digit of Alarm Setting (0~9)
5
1
read-write
MYEAR
Mask 1-Year Calendar Digit of Alarm Setting (0~9)
4
1
read-write
CLKFMT
RTC_CLKFMT
RTC Time Scale Selection Register
0x14
-1
read-write
n
0x0
0x0
_24HEN
24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
0
1
read-write
0
12-hour time scale with AM and PM indication selected
#0
1
24-hour time scale selected
#1
FREQADJ
RTC_FREQADJ
RTC Frequency Compensation Register
0x8
-1
read-write
n
0x0
0x0
FRACTION
Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number.
0
6
read-write
INTEGER
Integer Part
8
5
read-write
0
Integer part of detected value is 32752
#00000
1
Integer part of detected value is 32753
#00001
2
Integer part of detected value is 32754
#00010
3
Integer part of detected value is 32755
#00011
4
Integer part of detected value is 32756
#00100
5
Integer part of detected value is 32757
#00101
6
Integer part of detected value is 32758
#00110
7
Integer part of detected value is 32759
#00111
8
Integer part of detected value is 32760
#01000
9
Integer part of detected value is 32761
#01001
10
Integer part of detected value is 32762
#01010
11
Integer part of detected value is 32763
#01011
12
Integer part of detected value is 32764
#01100
13
Integer part of detected value is 32765
#01101
14
Integer part of detected value is 32766
#01110
15
Integer part of detected value is 32767
#01111
16
Integer part of detected value is 32768
#10000
17
Integer part of detected value is 32769
#10001
18
Integer part of detected value is 32770
#10010
19
Integer part of detected value is 32771
#10011
20
Integer part of detected value is 32772
#10100
21
Integer part of detected value is 32773
#10101
22
Integer part of detected value is 32774
#10110
23
Integer part of detected value is 32775
#10111
24
Integer part of detected value is 32776
#11000
25
Integer part of detected value is 32777
#11001
26
Integer part of detected value is 32778
#11010
27
Integer part of detected value is 32779
#11011
28
Integer part of detected value is 32780
#11100
29
Integer part of detected value is 32781
#11101
30
Integer part of detected value is 32782
#11110
31
Integer part of detected value is 32783
#11111
INIT
RTC_INIT
RTC Initiation Register
0x0
read-write
n
0x0
0x0
INIT
RTC Initiation (Write Only)\nWhen RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leave reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.\nThe INIT is a write-only field and read value will be always 0.
1
31
write-only
INIT_ACTIVE
RTC Active Status (Read Only)
0
1
read-only
0
RTC is at reset state
#0
1
RTC is at normal active state
#1
INTEN
RTC_INTEN
RTC Interrupt Enable Register
0x28
read-write
n
0x0
0x0
ALMIEN
Alarm Interrupt Enable Bit\nSet ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
0
1
read-write
0
RTC Alarm interrupt Disabled
#0
1
RTC Alarm interrupt Enabled
#1
TICKIEN
Time Tick Interrupt Enable Bit\nSet TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
1
1
read-write
0
RTC Time Tick interrupt Disabled
#0
1
RTC Time Tick interrupt Enabled
#1
INTSTS
RTC_INTSTS
RTC Interrupt Status Register
0x2C
read-write
n
0x0
0x0
ALMIF
RTC Alarm Interrupt Flag\nNote: Write 1 to clear this bit.
0
1
read-write
0
Alarm condition is not matched
#0
1
Alarm condition is matched
#1
TICKIF
RTC Time Tick Interrupt Flag\nNote: Write 1 to clear this bit.
1
1
read-write
0
Tick condition did not occur
#0
1
Tick condition occurred
#1
LEAPYEAR
RTC_LEAPYEAR
RTC Leap Year Indicator Register
0x24
read-only
n
0x0
0x0
LEAPYEAR
Leap Year Indication (Read Only)
0
1
read-only
0
This year is not a leap year
#0
1
This year is leap year
#1
LXTCTL
RTC_LXTCTL
RTC 32K.768 KHz LXT Control Register
0x100
read-write
n
0x0
0x0
OSC32_S
Clock 32K Source Selection
7
1
read-write
0
Clock source from LXT32K
#0
1
Clock source from LIRC38K
#1
TALM
RTC_TALM
RTC Time Alarm Register
0x1C
read-write
n
0x0
0x0
HR
1-Hour Time Digit of Alarm Setting (0~9)
16
4
read-write
MIN
1-Min Time Digit of Alarm Setting (0~9)
8
4
read-write
SEC
1-Sec Time Digit of Alarm Setting (0~9)
0
4
read-write
TENHR
10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
20
2
read-write
TENMIN
10-Min Time Digit of Alarm Setting (0~5)
12
3
read-write
TENSEC
10-Sec Time Digit of Alarm Setting (0~5)
4
3
read-write
TAMSK
RTC_TAMSK
RTC Time Alarm Mask Register
0x34
read-write
n
0x0
0x0
MHR
Mask 1-Hour Time Digit of Alarm Setting (0~9)
4
1
read-write
MMIN
Mask 1-Min Time Digit of Alarm Setting (0~9)
2
1
read-write
MSEC
Mask 1-Sec Time Digit of Alarm Setting (0~9)
0
1
read-write
MTENHR
Mask 10-Hour Time Digit of Alarm Setting (0~2)
5
1
read-write
MTENMIN
Mask 10-Min Time Digit of Alarm Setting (0~5)
3
1
read-write
MTENSEC
Mask 10-Sec Time Digit of Alarm Setting (0~5)
1
1
read-write
TICK
RTC_TICK
RTC Time Tick Register
0x30
read-write
n
0x0
0x0
TICK
Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
0
3
read-write
0
Time tick is 1 second
#000
1
Time tick is 1/2 second
#001
2
Time tick is 1/4 second
#010
3
Time tick is 1/8 second
#011
4
Time tick is 1/16 second
#100
5
Time tick is 1/32 second
#101
6
Time tick is 1/64 second
#110
7
Time tick is 1/128 second
#111
TIME
RTC_TIME
RTC Time Loading Register
0xC
read-write
n
0x0
0x0
HR
1-Hour Time Digit (0~9)
16
4
read-write
MIN
1-Min Time Digit (0~9)
8
4
read-write
SEC
1-Sec Time Digit (0~9)
0
4
read-write
TENHR
10-Hour Time Digit (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
20
2
read-write
TENMIN
10-Min Time Digit (0~5)
12
3
read-write
TENSEC
10-Sec Time Digit (0~5)
4
3
read-write
WEEKDAY
RTC_WEEKDAY
RTC Day of the Week Register
0x18
-1
read-write
n
0x0
0x0
WEEKDAY
Day of the Week Register
0
3
read-write
0
Sunday
#000
1
Monday
#001
2
Tuesday
#010
3
Wednesday
#011
4
Thursday
#100
5
Friday
#101
6
Saturday
#110
7
Reserved.
#111
SCS
SYST_SCR Register Map
SYST_SCR
0x0
0x10
0xC
registers
n
0xD04
0x10
registers
n
0xD18
0xC
registers
n
AIRCR
AIRCR
Application Interrupt and Reset Control Register
0xD0C
-1
read-write
n
0x0
0x0
ENDIANNESS
Data Endianness
15
1
read-write
0
Little-endian
#0
1
Big-endian
#1
PRIGROUP
Interrupt Priority Grouping\nThis field determines the Split Of Group priority from subpriority,
8
3
read-write
SYSRESETREQ
System Reset Request\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence.
2
1
read-write
VECTCLRACTIVE
Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack.
1
1
read-write
VECTORKEY
Register Access Key\nWhen writing this register, this field should be 0x05FA, otherwise the write action will be unpredictable.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.
16
16
read-write
VECTRESET
Reserved.
0
1
read-write
ICSR
ICSR
Interrupt Control and State Register
0xD04
read-write
n
0x0
0x0
ISRPENDING
Interrupt Pending Flag, Excluding NMI and Faults (Read Only)
22
1
read-only
0
Interrupt not pending
#0
1
Interrupt pending
#1
ISRPREEMPT
Interrupt Preempt Bit (Read Only)\nIf set, a pending exception will be serviced on exit from the debug halt state.
23
1
read-only
NMIPENDSET
NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
31
1
read-write
0
No effect.\nNMI exception is not pending
#0
1
Changes NMI exception state to pending.\nNMI exception is pending
#1
PENDSTCLR
SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDST bit, you must 'write 0 to PENDSTSET and write 1 to PENDSTRTC_CAL' at the same time.
25
1
read-write
0
No effect
#0
1
Removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick Exception Set-pending Bit\nWrite Operation:
26
1
read-write
0
No effect.\nSysTick exception is not pending
#0
1
Changes SysTick exception state to pending.\nSysTick exception is pending
#1
PENDSVCLR
PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDSV bit, you must 'write 0 to PENDSVSET and write 1 to PENDSVRTC_CAL' at the same time.
27
1
read-write
0
No effect
#0
1
Removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
No effect.\nPendSV exception is not pending
#0
1
Changes PendSV exception state to pending.\nPendSV exception is pending
#1
RETTOBASE
Preempted Active Exceptions Indicator\nIndicate whether There are Preempted Active Exceptions
11
1
read-write
0
there are preempted active exceptions to execute
#0
1
there are no active exceptions, or the currently-executing exception is the only active exception
#1
VECTACTIVE
Number of the Current Active Exception
0
6
read-write
0
Thread mode
0
VECTPENDING
Number of the Highest Pended Exception\nIndicate the Exception Number of the Highest Priority Pending Enabled Exception\nThe value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register.
12
6
read-write
0
no pending exceptions
0
SCR
SCR
System Control Register
0xD10
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded
#0
1
Enabled events and all interrupts, including disabled interrupts, can wake up the processor
#1
SLEEPDEEP
Processor Deep Sleep and Sleep Mode Selection\nControl Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode.
2
1
read-write
0
Sleep
#0
1
Deep sleep
#1
SLEEPONEXIT
Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
0
Do not sleep when returning to Thread mode
#0
1
Enters sleep, or deep sleep, on return from an ISR to Thread mode
#1
SHPR1
SHPR1
System Handler Priority Register 1
0xD18
read-write
n
0x0
0x0
PRI_4
Priority of system handler 4, MemManage
0
8
read-write
PRI_5
Priority of system handler 5, BusFault
8
8
read-write
PRI_6
Priority of system handler 6, UsageFault
16
8
read-write
SHPR2
SHPR2
System Handler Priority Register 2
0xD1C
read-write
n
0x0
0x0
PRI_11
Priority of System Handler 11 - SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority.
30
2
read-write
SHPR3
SHPR3
System Handler Priority Register 3
0xD20
read-write
n
0x0
0x0
PRI_14
Priority of System Handler 14 - PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority.
22
2
read-write
PRI_15
Priority of System Handler 15 - SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority.
30
2
read-write
SYST_CTRL
SYST_CTRL
SysTick Control and Status Register
0x10
read-write
n
0x0
0x0
CLKSRC
System Tick Clock Source Selection
2
1
read-write
0
Clock source is the (optional) external reference clock
#0
1
Core clock used for SysTick
#1
COUNTFLAG
System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-write
ENABLE
System Tick Counter Enabled
0
1
read-write
0
Counter Disabled
#0
1
Counter will operate in a multi-shot manner
#1
TICKINT
System Tick Interrupt Enabled
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended
#1
SYST_LOAD
SYST_LOAD
SysTick Reload Value Register
0x14
read-write
n
0x0
0x0
RELOAD
System Tick Reload Value\nThe value to load into the Current Value register when the counter reaches 0.
0
24
read-write
SYST_VAL
SYST_VAL
SysTick Current Value Register
0x18
read-write
n
0x0
0x0
CURRENT
System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
0
24
read-write
VTOR
VTOR
Vector Table Offset Register
0xD08
read-write
n
0x0
0x0
TBLOFF
Table Offset Bits\nThe vector table address for the selected Security state.
7
25
read-write
SPIx
SPI Register Map
SPI
0x0
0x0
0x18
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
0x60
0xC
registers
n
CLKDIV
SPIx_CLKDIV
SPI Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.\nNote 1: Not supported in I2S mode.\nNote 2: The time interval must be larger than or equal 8 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register.
0
9
read-write
CTL
SPIx_CTL
SPI Control Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity
3
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
DATDIR
Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
20
1
read-write
0
SPI data is input direction
#0
1
SPI data is output direction
#1
DWIDTH
Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can be up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically.
8
5
read-write
HALFDPX
SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
14
1
read-write
0
SPI operates in full-duplex transfer
#0
1
SPI operates in half-duplex transfer
#1
LSB
Send LSB First
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
#1
REORDER
Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXNEG
Receive on Negative Edge
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
RXONLY
Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
15
1
read-write
0
Receive-only mode Disabled
#0
1
Receive-only mode Enabled
#1
SLAVE
Slave Mode Control
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
0
1
read-write
0
Transfer control Disabled
#0
1
Transfer control Enabled
#1
SUSPITV
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle\nExample:
4
4
read-write
TXNEG
Transmit on Negative Edge
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SPI bus clock
#1
UNITIEN
Unit Transfer Interrupt Enable Bit
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
FIFOCTL
SPIx_FIFOCTL
SPI FIFO Control Register
0x10
-1
read-write
n
0x0
0x0
RXFBCLR
Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared.
8
1
read-write
0
No effect
#0
1
Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
RXOVIEN
Receive FIFO Overrun Interrupt Enable Bit
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Receive Reset
0
1
read-write
0
No effect
#0
1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not
#1
RXTH
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
24
3
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Bit
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-out Interrupt Enable Bit
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXFBCLR
Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared.
9
1
read-write
0
No effect
#0
1
Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
TXRST
Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
1
1
read-write
0
No effect
#0
1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not
#1
TXTH
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
28
3
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt.
7
1
read-write
0
Slave TX underflow interrupt Disabled
#0
1
Slave TX underflow interrupt Enabled
#1
TXUFPOL
TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: This bit should be set as 0 in I2S mode.\nNote 3: When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
6
1
read-write
0
The SPI data out is keep 0 if there is TX underflow event in Slave mode
#0
1
The SPI data out is keep 1 if there is TX underflow event in Slave mode
#1
I2SCLK
SPIx_I2SCLK
I2S Clock Divider Control Register
0x64
read-write
n
0x0
0x0
BCLKDIV
Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock , fBCLK, is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.\nIn I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . \nThe peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.\nNote: The time interval must be larger than or equal to 8 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register.
8
10
read-write
MCLKDIV
Master Clock Divider\nIf MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate.
0
7
read-write
I2SCTL
SPIx_I2SCTL
I2S Control Register
0x60
read-write
n
0x0
0x0
FORMAT
Data Format Selection
28
2
read-write
0
I2S data format
#00
1
MSB justified data format
#01
2
PCM mode A
#10
3
PCM mode B
#11
I2SEN
I2S Controller Enable Bit\nNote 1: If enabling this bit, I2Sx_BCLK will start to output in Master mode.\nNote 2: Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.
0
1
read-write
0
I2S mode Disabled
#0
1
I2S mode Enabled
#1
LZCEN
Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation.
17
1
read-write
0
Left channel zero cross detection Disabled
#0
1
Left channel zero cross detection Enabled
#1
LZCIEN
Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs.
25
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
MCLKEN
Master Clock Enable Bit\nIf MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
15
1
read-write
0
Master clock Disabled
#0
1
Master clock Enabled
#1
MONO
Monaural Data
6
1
read-write
0
Data is stereo format
#0
1
Data is monaural format
#1
MUTE
Transmit Mute Enable Bit
3
1
read-write
0
Transmit data is shifted from buffer
#0
1
Transmit channel zero
#1
ORDER
Stereo Data Order in FIFO
7
1
read-write
0
Left channel data at high byte
#0
1
Left channel data at low byte
#1
RXEN
Receive Enable Bit
2
1
read-write
0
Data receive Disabled
#0
1
Data receive Enabled
#1
RXLCH
Receive Left Channel Enable Bit
23
1
read-write
0
Receive right channel data in Mono mode
#0
1
Receive left channel data in Mono mode
#1
RZCEN
Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation.
16
1
read-write
0
Right channel zero cross detection Disabled
#0
1
Right channel zero cross detection Enabled
#1
RZCIEN
Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs.
24
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
SLAVE
Slave Mode\nI2S can operate as master or slave. For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.
8
1
read-write
0
Master mode
#0
1
Slave mode
#1
SLVERRIEN
Bit Clock Loss Interrupt Enable Bit for Slave Mode\nInterrupt occurs if this bit is set to 1 and bit clock loss event occurs.
31
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXEN
Transmit Enable Bit
1
1
read-write
0
Data transmit Disabled
#0
1
Data transmit Enabled
#1
WDWIDTH
Word Width
4
2
read-write
0
data size is 8-bit
#00
1
data size is 16-bit
#01
2
data size is 24-bit
#10
3
data size is 32-bit
#11
I2SSTS
SPIx_I2SSTS
I2S Status Register
0x68
-1
read-write
n
0x0
0x0
I2SENSTS
I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.
15
1
read-only
0
SPI/I2S control logic Disabled
#0
1
SPI/I2S control logic Enabled
#1
LZCIF
Left Channel Zero Cross Interrupt Flag
21
1
read-write
0
No zero cross event occurred on left channel
#0
1
Zero cross event occurred on left channel
#1
RIGHT
Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel.
4
1
read-only
0
Left channel
#0
1
Right channel
#1
RXCNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
24
3
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
11
1
read-write
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
RZCIF
Right Channel Zero Cross Interrupt Flag
20
1
read-write
0
No zero cross event occurred on right channel
#0
1
Zero cross event occurred on right channel
#1
SLVERRIF
Bit Clock Loss Interrupt Flag for Slave Mode\nNote: This bit will be cleared by writing 1 to it.
22
1
read-write
0
No bit clock loss event occurred
#0
1
Bit clock loss event occurred
#1
TXCNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
3
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
19
1
read-write
PDMACTL
SPIx_PDMACTL
SPI PDMA Control Register
0xC
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0
#1
RXPDMAEN
Receive PDMA Enable Bit
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
RX
SPIx_RX
SPI Data Receive Register
0x30
read-only
n
0x0
0x0
RX
Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
0
32
read-only
SSCTL
SPIx_SSCTL
SPI Slave Select Control Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit (Master Only)
3
1
read-write
0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0])
#0
1
Automatic slave selection function Enabled
#1
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit
8
1
read-write
0
Slave mode bit count error interrupt Disabled
#0
1
Slave mode bit count error interrupt Enabled
#1
SLVURIEN
Slave Mode TX Under Run Interrupt Enable Bit
9
1
read-write
0
Slave mode TX under run interrupt Disabled
#0
1
Slave mode TX under run interrupt Enabled
#1
SS
Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0,
0
1
read-write
0
set the SPIx_SS line to inactive state.\nKeep the SPIx_SS line at inactive state
#0
1
set the SPIx_SS line to active state.\nSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit
12
1
read-write
0
Slave select active interrupt Disabled
#0
1
Slave select active interrupt Enabled
#1
SSACTPOL
Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS).
2
1
read-write
0
The slave selection signal SPIx_SS is active low
#0
1
The slave selection signal SPIx_SS is active high
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit
13
1
read-write
0
Slave select inactive interrupt Disabled
#0
1
Slave select inactive interrupt Enabled
#1
STATUS
SPIx_STATUS
SPI Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
0
1
read-only
0
SPI controller is in idle state
#0
1
SPI controller is in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
11
1
read-write
0
No FIFO is overrun
#0
1
Receive FIFO is overrun
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
6
1
read-write
0
No Slave mode bit count error event
#0
1
Slave mode bit count error event occurred
#1
SLVURIF
Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
7
1
read-write
0
No Slave TX under run event
#0
1
Slave TX under run event occurred
#1
SPIENSTS
SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
15
1
read-only
0
SPI controller Disabled
#0
1
SPI controller Enabled
#1
SSACTIF
Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
2
1
read-write
0
Slave select active interrupt was cleared or not occurred
#0
1
Slave select active interrupt event occurred
#1
SSINAIF
Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
3
1
read-write
0
Slave select inactive interrupt was cleared or not occurred
#0
1
Slave select inactive interrupt event occurred
#1
SSLINE
Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
TX
SPIx_TX
SPI Data Transmit Register
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.\nIn SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.\nIn I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section\nNote: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
0
32
write-only
SYS
SYS Register Map
SYS
0x0
0x0
0x14
registers
n
0x100
0x4
registers
n
0x18
0x4
registers
n
0x1EC
0x4
registers
n
0x24
0x4
registers
n
0x30
0x40
registers
n
0xC0
0x4
registers
n
0xD0
0x8
registers
n
0xDC
0xC
registers
n
0xF0
0xC
registers
n
BODCTL
SYS_BODCTL
Brown-out Detector Control Register
0x18
-1
read-write
n
0x0
0x0
BODDGSEL
Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
8
3
read-write
0
BOD output is sampled by LIRC/4 clock
#000
1
64 system clock (HCLK)
#001
2
128 system clock (HCLK)
#010
3
256 system clock (HCLK)
#011
4
512 system clock (HCLK)
#100
5
1024 system clock (HCLK)
#101
6
2048 system clock (HCLK)
#110
7
4096 system clock (HCLK)
#111
BODEN
Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]).\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: Reset by powr on reset
0
1
read-write
0
Brown-out Detector function Disabled
#0
1
Brown-out Detector function Enabled
#1
BODIF
Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0.
4
1
read-write
0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting
#0
1
When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled
#1
BODLPM
Brown-out Detector Low Power Mode (Write Protect)\nNote 1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
BOD operate in normal mode (default)
#0
1
BOD Low Power mode Enabled
#1
BODOUT
Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled , this bit always responds 0000.
6
1
read-write
0
Brown-out Detector output status is 0
#0
1
Brown-out Detector output status is 1
#1
BODRSTEN
Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit .\nNote 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).\nWhile the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 3: Reset by powr on reset
3
1
read-write
0
Brown-out 'INTERRUPT' function Enabled
#0
1
Brown-out 'RESET' function Enabled
#1
BODVL
Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by Flash controller user configuration register CBOV (CONFIG0 [21]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote : reset by powr on reset
16
1
read-write
0
Brown-Out Detector threshold voltage is 2.0V
#0
1
Brown-Out Detector threshold voltage is 2.5V
#1
LVRDGSEL
LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
12
3
read-write
0
Without de-glitch function
#000
1
64 system clock (HCLK)
#001
2
128 system clock (HCLK)
#010
3
256 system clock (HCLK)
#011
4
512 system clock (HCLK)
#100
5
1024 system clock (HCLK)
#101
6
2048 system clock (HCLK)
#110
7
4096 system clock (HCLK)
#111
LVREN
Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote 1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default).\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
Low Voltage Reset function Disabled
#0
1
Low Voltage Reset function Enabled
#1
LVRVL
LVR Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by Flash controller user configuration register LVRLVSEL (CONFIG0 [29]).\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: This bit is only for special case.\nNote 3: reset by powr on reset
20
1
read-write
0
LVR-Out Detector threshold voltage is 1.6V
#0
1
LVR-Out Detector threshold voltage is 1.7V
#1
GPA_MFPH
SYS_GPA_MFPH
GPIOA High Byte Multiple Function Control Register
0x34
read-write
n
0x0
0x0
PA10MFP
PA.10 Multi-function Pin Selection
8
4
read-write
PA11MFP
PA.11 Multi-function Pin Selection
12
4
read-write
PA12MFP
PA.12 Multi-function Pin Selection
16
4
read-write
PA13MFP
PA.13 Multi-function Pin Selection
20
4
read-write
PA14MFP
PA.14 Multi-function Pin Selection
24
4
read-write
PA15MFP
PA.15 Multi-function Pin Selection
28
4
read-write
PA8MFP
PA.8 Multi-function Pin Selection
0
4
read-write
PA9MFP
PA.9 Multi-function Pin Selection
4
4
read-write
GPA_MFPL
SYS_GPA_MFPL
GPIOA Low Byte Multiple Function Control Register
0x30
read-write
n
0x0
0x0
PA0MFP
PA.0 Multi-function Pin Selection
0
4
read-write
PA1MFP
PA.1 Multi-function Pin Selection
4
4
read-write
PA2MFP
PA.2 Multi-function Pin Selection
8
4
read-write
PA3MFP
PA.3 Multi-function Pin Selection
12
4
read-write
PA4MFP
PA.4 Multi-function Pin Selection
16
4
read-write
PA5MFP
PA.5 Multi-function Pin Selection
20
4
read-write
PA6MFP
PA.6 Multi-function Pin Selection
24
4
read-write
PA7MFP
PA.7 Multi-function Pin Selection
28
4
read-write
GPB_MFPH
SYS_GPB_MFPH
GPIOB High Byte Multiple Function Control Register
0x3C
read-write
n
0x0
0x0
PB10MFP
PB.10 Multi-function Pin Selection
8
4
read-write
PB11MFP
PB.11 Multi-function Pin Selection
12
4
read-write
PB12MFP
PB.12 Multi-function Pin Selection
16
4
read-write
PB13MFP
PB.13 Multi-function Pin Selection
20
4
read-write
PB14MFP
PB.14 Multi-function Pin Selection
24
4
read-write
PB15MFP
PB.15 Multi-function Pin Selection
28
4
read-write
PB8MFP
PB.8 Multi-function Pin Selection
0
4
read-write
PB9MFP
PB.9 Multi-function Pin Selection
4
4
read-write
GPB_MFPL
SYS_GPB_MFPL
GPIOB Low Byte Multiple Function Control Register
0x38
read-write
n
0x0
0x0
PB0MFP
PB.0 Multi-function Pin Selection
0
4
read-write
PB1MFP
PB.1 Multi-function Pin Selection
4
4
read-write
PB2MFP
PB.2 Multi-function Pin Selection
8
4
read-write
PB3MFP
PB.3 Multi-function Pin Selection
12
4
read-write
PB4MFP
PB.4 Multi-function Pin Selection
16
4
read-write
PB5MFP
PB.5 Multi-function Pin Selection
20
4
read-write
PB6MFP
PB.6 Multi-function Pin Selection
24
4
read-write
PB7MFP
PB.7 Multi-function Pin Selection
28
4
read-write
GPC_MFPH
SYS_GPC_MFPH
GPIOC High Byte Multiple Function Control Register
0x44
read-write
n
0x0
0x0
PC10MFP
PC.10 Multi-function Pin Selection
8
4
read-write
PC11MFP
PC.11 Multi-function Pin Selection
12
4
read-write
PC12MFP
PC.12 Multi-function Pin Selection
16
4
read-write
PC13MFP
PC.13 Multi-function Pin Selection
20
4
read-write
PC14MFP
PC.14 Multi-function Pin Selection
24
4
read-write
PC15MFP
PC.15 Multi-function Pin Selection
28
4
read-write
PC8MFP
PC.8 Multi-function Pin Selection
0
4
read-write
PC9MFP
PC.9 Multi-function Pin Selection
4
4
read-write
GPC_MFPL
SYS_GPC_MFPL
GPIOC Low Byte Multiple Function Control Register
0x40
read-write
n
0x0
0x0
PC0MFP
PC.0 Multi-function Pin Selection
0
4
read-write
PC1MFP
PC.1 Multi-function Pin Selection
4
4
read-write
PC2MFP
PC.2 Multi-function Pin Selection
8
4
read-write
PC3MFP
PC.3 Multi-function Pin Selection
12
4
read-write
PC4MFP
PC.4 Multi-function Pin Selection
16
4
read-write
PC5MFP
PC.5 Multi-function Pin Selection
20
4
read-write
PC6MFP
PC.6 Multi-function Pin Selection
24
4
read-write
PC7MFP
PC.7 Multi-function Pin Selection
28
4
read-write
GPD_MFPH
SYS_GPD_MFPH
GPIOD High Byte Multiple Function Control Register
0x4C
read-write
n
0x0
0x0
PD10MFP
PD.10 Multi-function Pin Selection
8
4
read-write
PD11MFP
PD.11 Multi-function Pin Selection
12
4
read-write
PD12MFP
PD.12 Multi-function Pin Selection
16
4
read-write
PD13MFP
PD.13 Multi-function Pin Selection
20
4
read-write
PD14MFP
PD.14 Multi-function Pin Selection
24
4
read-write
PD15MFP
PD.15 Multi-function Pin Selection
28
4
read-write
PD8MFP
PD.8 Multi-function Pin Selection
0
4
read-write
PD9MFP
PD.9 Multi-function Pin Selection
4
4
read-write
GPD_MFPL
SYS_GPD_MFPL
GPIOD Low Byte Multiple Function Control Register
0x48
read-write
n
0x0
0x0
PD0MFP
PD.0 Multi-function Pin Selection
0
4
read-write
PD1MFP
PD.1 Multi-function Pin Selection
4
4
read-write
PD2MFP
PD.2 Multi-function Pin Selection
8
4
read-write
PD3MFP
PD.3 Multi-function Pin Selection
12
4
read-write
PD4MFP
PD.4 Multi-function Pin Selection
16
4
read-write
PD5MFP
PD.5 Multi-function Pin Selection
20
4
read-write
PD6MFP
PD.6 Multi-function Pin Selection
24
4
read-write
PD7MFP
PD.7 Multi-function Pin Selection
28
4
read-write
GPE_MFPH
SYS_GPE_MFPH
GPIOE High Byte Multiple Function Control Register
0x54
read-write
n
0x0
0x0
PE10MFP
PE.10 Multi-function Pin Selection
8
4
read-write
PE11MFP
PE.11 Multi-function Pin Selection
12
4
read-write
PE12MFP
PE.12 Multi-function Pin Selection
16
4
read-write
PE13MFP
PE.13 Multi-function Pin Selection
20
4
read-write
PE14MFP
PE.14 Multi-function Pin Selection
24
4
read-write
PE15MFP
PE.15 Multi-function Pin Selection
28
4
read-write
PE8MFP
PE.8 Multi-function Pin Selection
0
4
read-write
PE9MFP
PE.9 Multi-function Pin Selection
4
4
read-write
GPE_MFPL
SYS_GPE_MFPL
GPIOE Low Byte Multiple Function Control Register
0x50
read-write
n
0x0
0x0
PE0MFP
PE.0 Multi-function Pin Selection
0
4
read-write
PE1MFP
PE.1 Multi-function Pin Selection
4
4
read-write
PE2MFP
PE.2 Multi-function Pin Selection
8
4
read-write
PE3MFP
PE.3 Multi-function Pin Selection
12
4
read-write
PE4MFP
PE.4 Multi-function Pin Selection
16
4
read-write
PE5MFP
PE.5 Multi-function Pin Selection
20
4
read-write
PE6MFP
PE.6 Multi-function Pin Selection
24
4
read-write
PE7MFP
PE.7 Multi-function Pin Selection
28
4
read-write
GPF_MFPH
SYS_GPF_MFPH
GPIOF High Byte Multiple Function Control Register
0x5C
read-write
n
0x0
0x0
PF10MFP
PF.10 Multi-function Pin Selection
8
4
read-write
PF11MFP
PF.11 Multi-function Pin Selection
12
4
read-write
PF12MFP
PF.12 Multi-function Pin Selection
16
4
read-write
PF13MFP
PF.13 Multi-function Pin Selection
20
4
read-write
PF14MFP
PF.14 Multi-function Pin Selection
24
4
read-write
PF15MFP
PF.15 Multi-function Pin Selection
28
4
read-write
PF8MFP
PF.8 Multi-function Pin Selection
0
4
read-write
PF9MFP
PF.9 Multi-function Pin Selection
4
4
read-write
GPF_MFPL
SYS_GPF_MFPL
GPIOF Low Byte Multiple Function Control Register
0x58
-1
read-write
n
0x0
0x0
PF0MFP
PF.0 Multi-function Pin Selection
0
4
read-write
PF1MFP
PF.1 Multi-function Pin Selection
4
4
read-write
PF2MFP
PF.2 Multi-function Pin Selection
8
4
read-write
PF3MFP
PF.3 Multi-function Pin Selection
12
4
read-write
PF4MFP
PF.4 Multi-function Pin Selection
16
4
read-write
PF5MFP
PF.5 Multi-function Pin Selection
20
4
read-write
PF6MFP
PF.6 Multi-function Pin Selection
24
4
read-write
PF7MFP
PF.7 Multi-function Pin Selection
28
4
read-write
GPG_MFPH
SYS_GPG_MFPH
GPIOG High Byte Multiple Function Control Register
0x64
read-write
n
0x0
0x0
PG10MFP
PG.10 Multi-function Pin Selection
8
4
read-write
PG11MFP
PG.11 Multi-function Pin Selection
12
4
read-write
PG12MFP
PG.12 Multi-function Pin Selection
16
4
read-write
PG13MFP
PG.13 Multi-function Pin Selection
20
4
read-write
PG14MFP
PG.14 Multi-function Pin Selection
24
4
read-write
PG15MFP
PG.15 Multi-function Pin Selection
28
4
read-write
PG8MFP
PG.8 Multi-function Pin Selection
0
4
read-write
PG9MFP
PG.9 Multi-function Pin Selection
4
4
read-write
GPG_MFPL
SYS_GPG_MFPL
GPIOG Low Byte Multiple Function Control Register
0x60
read-write
n
0x0
0x0
PG0MFP
PG.0 Multi-function Pin Selection
0
4
read-write
PG1MFP
PG.1 Multi-function Pin Selection
4
4
read-write
PG2MFP
PG.2 Multi-function Pin Selection
8
4
read-write
PG3MFP
PG.3 Multi-function Pin Selection
12
4
read-write
PG4MFP
PG.4 Multi-function Pin Selection
16
4
read-write
PG5MFP
PG.5 Multi-function Pin Selection
20
4
read-write
PG6MFP
PG.6 Multi-function Pin Selection
24
4
read-write
PG7MFP
PG.7 Multi-function Pin Selection
28
4
read-write
GPH_MFPH
SYS_GPH_MFPH
GPIOH High Byte Multiple Function Control Register
0x6C
read-write
n
0x0
0x0
PH10MFP
PH.10 Multi-function Pin Selection
8
4
read-write
PH11MFP
PH.11 Multi-function Pin Selection
12
4
read-write
PH12MFP
PH.12 Multi-function Pin Selection
16
4
read-write
PH13MFP
PH.13 Multi-function Pin Selection
20
4
read-write
PH14MFP
PH.14 Multi-function Pin Selection
24
4
read-write
PH15MFP
PH.15 Multi-function Pin Selection
28
4
read-write
PH8MFP
PH.8 Multi-function Pin Selection
0
4
read-write
PH9MFP
PH.9 Multi-function Pin Selection
4
4
read-write
GPH_MFPL
SYS_GPH_MFPL
GPIOH Low Byte Multiple Function Control Register
0x68
read-write
n
0x0
0x0
PH0MFP
PH.0 Multi-function Pin Selection
0
4
read-write
PH1MFP
PH.1 Multi-function Pin Selection
4
4
read-write
PH2MFP
PH.2 Multi-function Pin Selection
8
4
read-write
PH3MFP
PH.3 Multi-function Pin Selection
12
4
read-write
PH4MFP
PH.4 Multi-function Pin Selection
16
4
read-write
PH5MFP
PH.5 Multi-function Pin Selection
20
4
read-write
PH6MFP
PH.6 Multi-function Pin Selection
24
4
read-write
PH7MFP
PH.7 Multi-function Pin Selection
28
4
read-write
HIRCTRIMCTL
SYS_HIRCTRIMCTL
HIRC Trim Control Register
0xF0
-1
read-write
n
0x0
0x0
BOUNDARY
Boundary Selection\nFill the boundary range from 0x1 to 0x1F, 0x0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enable.
16
5
read-write
BOUNDEN
Boundary Enable Bit
9
1
read-write
0
Boundary function Disabled
#0
1
Boundary function Enabled
#1
CESTOPEN
Clock Error Stop Enable Bit
8
1
read-write
0
The trim operation is keep going if clock is inaccuracy
#0
1
The trim operation is stopped if clock is inaccuracy
#1
FREQSEL
Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
0
2
read-write
0
Disable HIRC auto trim function
#00
1
Enable HIRC auto trim function and trim HIRC to 48 MHz
#01
2
Reserved.
#10
3
Reserved.
#11
LOOPSEL
Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
4
2
read-write
0
Trim value calculation is based on average difference in 4 clocks of reference clock
#00
1
Trim value calculation is based on average difference in 8 clocks of reference clock
#01
2
Trim value calculation is based on average difference in 16 clocks of reference clock
#10
3
Trim value calculation is based on average difference in 32 clocks of reference clock
#11
REFCKSEL
Reference Clock Selection\nNote 1: HIRC trim reference clock supports LXT or internal USB synchronous mode depending on the chip spec. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.\nNote 2: If there is no reference clock (LXT or internal USB synchronous mode) when the rc_trim is enabled, CLKERIF (SYS_HIRCTRIMCTL[2]) will be set to 1.
10
1
read-write
0
HIRC trim reference clock is from LXT (32.768 kHz)
#0
1
HIRC trim reference clock is from internal USB synchronous mode
#1
RETRYCNT
Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
6
2
read-write
0
Trim retry count limitation is 64 loops
#00
1
Trim retry count limitation is 128 loops
#01
2
Trim retry count limitation is 256 loops
#10
3
Trim retry count limitation is 512 loops
#11
HIRCTRIMIEN
SYS_HIRCTRIMIEN
HIRC Trim Interrupt Enable Register
0xF4
read-write
n
0x0
0x0
CLKEIEN
Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_HIRCTRIMSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
2
1
read-write
0
Disable CLKERRIF(SYS_HIRCTRIMSTS[2]) status to trigger an interrupt to CPU
#0
1
Enable CLKERRIF(SYS_HIRCTRIMSTS[2]) status to trigger an interrupt to CPU
#1
TFALIEN
Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTRIMCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_HIRCTRIMSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
1
1
read-write
0
Disable TFAILIF(SYS_HIRCTRIMSTS[1]) status to trigger an interrupt to CPU
#0
1
Enable TFAILIF(SYS_HIRCTRIMSTS[1]) status to trigger an interrupt to CPU
#1
HIRCTRIMSTS
SYS_HIRCTRIMSTS
HIRC Trim Interrupt Status Register
0xF8
read-write
n
0x0
0x0
CLKERIF
Clock Error Interrupt Status\nWhen the frequency relation between reference clock (LXT or USB sync signals) and 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_HIRCTRIMCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_HIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.\nNote : Reset by powr on reset
2
1
read-write
0
Clock frequency is accuracy
#0
1
Clock frequency is inaccuracy
#1
FREQLOCK
HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled. \nNote : Reset by powr on reset.
0
1
read-write
0
The internal high-speed oscillator frequency doesn't lock at 48 MHz yet
#0
1
The internal high-speed oscillator frequency locked at 48 MHz
#1
OVBDIF
Over Boundary Status\nWhen the over boundary function is set, if there occurs the over boundary condition, this flag will be set.\nNote: Write 1 to clear this flag.
3
1
read-write
0
Over boundary coundition did not occur
#0
1
Over boundary coundition occurred
#1
TFAILIF
Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_HIRCIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.\nNote : Reset by powr on reset
1
1
read-write
0
Trim value update limitation count does not reach
#0
1
Trim value update limitation count reached and HIRC frequency still not locked
#1
IPRST0
SYS_IPRST0
Peripheral Reset Control Register 0
0x8
read-write
n
0x0
0x0
CHIPRST
Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload.\nAbout the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote : reset by powr on reset
0
1
read-write
0
Chip normal operation
#0
1
Chip one-shot reset
#1
CPURST
Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
Processor core normal operation
#0
1
Processor core one-shot reset
#1
CRCRST
CRC Calculation Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
CRC calculation controller normal operation
#0
1
CRC calculation controller reset
#1
EBIRST
EBI Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
3
1
read-write
0
EBI controller normal operation
#0
1
EBI controller reset
#1
HDIV_RST
HDIV Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the hardware divider. User need to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
Hardware divider controller normal operation
#0
1
Hardware divider controller reset
#1
PDMARST
PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
PDMA controller normal operation
#0
1
PDMA controller reset
#1
IPRST1
SYS_IPRST1
Peripheral Reset Control Register 1
0xC
read-write
n
0x0
0x0
ACMP01RST
Analog Comparator 0/1 Controller Reset
7
1
read-write
0
Analog Comparator 0/1 controller normal operation
#0
1
Analog Comparator 0/1 controller reset
#1
ADCRST
ADC Controller Reset
28
1
read-write
0
ADC controller normal operation
#0
1
ADC controller reset
#1
GPIORST
GPIO Controller Reset
1
1
read-write
0
GPIO controller normal operation
#0
1
GPIO controller reset
#1
I2C0RST
I2C0 Controller Reset
8
1
read-write
0
I2C0 controller normal operation
#0
1
I2C0 controller reset
#1
I2C1RST
I2C1 Controller Reset
9
1
read-write
0
I2C1 controller normal operation
#0
1
I2C1 controller reset
#1
QSPI0RST
QSPI0 Controller Reset
12
1
read-write
0
QSPI0 controller normal operation
#0
1
QSPI0 controller reset
#1
SPI0RST
SPI0 Controller Reset
13
1
read-write
0
SPI0 controller normal operation
#0
1
SPI0 controller reset
#1
TMR0RST
Timer0 Controller Reset
2
1
read-write
0
Timer0 controller normal operation
#0
1
Timer0 controller reset
#1
TMR1RST
Timer1 Controller Reset
3
1
read-write
0
Timer1 controller normal operation
#0
1
Timer1 controller reset
#1
TMR2RST
Timer2 Controller Reset
4
1
read-write
0
Timer2 controller normal operation
#0
1
Timer2 controller reset
#1
TMR3RST
Timer3 Controller Reset
5
1
read-write
0
Timer3 controller normal operation
#0
1
Timer3 controller reset
#1
UART0RST
UART0 Controller Reset
16
1
read-write
0
UART0 controller normal operation
#0
1
UART0 controller reset
#1
UART1RST
UART1 Controller Reset
17
1
read-write
0
UART1 controller normal operation
#0
1
UART1 controller reset
#1
UART2RST
UART2 Controller Reset
18
1
read-write
0
UART2 controller normal operation
#0
1
UART2 controller reset
#1
UART3RST
UART3 Controller Reset
19
1
read-write
0
UART3 controller normal operation
#0
1
UART3 controller reset
#1
UART4RST
UART4 Controller Reset
20
1
read-write
0
UART4 controller normal operation
#0
1
UART4 controller reset
#1
UART5RST
UART5 Controller Reset
21
1
read-write
0
UART5 controller normal operation
#0
1
UART5 controller reset
#1
UART6RST
UART6 Controller Reset
22
1
read-write
0
UART6 controller normal operation
#0
1
UART6 controller reset
#1
UART7RST
UART7 Controller Reset
23
1
read-write
0
UART7 controller normal operation
#0
1
UART7 controller reset
#1
USBDRST
USBD Controller Reset
27
1
read-write
0
USBD controller normal operation
#0
1
USBD controller reset
#1
IPRST2
SYS_IPRST2
Peripheral Reset Control Register 2
0x10
read-write
n
0x0
0x0
BPWM0RST
BPWM0 Controller Reset
18
1
read-write
0
BPWM0 controller normal operation
#0
1
BPWM0 controller reset
#1
BPWM1RST
BPWM1 Controller Reset
19
1
read-write
0
BPWM1 controller normal operation
#0
1
BPWM1 controller reset
#1
PWM0RST
PWM0 Controller Reset
16
1
read-write
0
PWM0 controller normal operation
#0
1
PWM0 controller reset
#1
PWM1RST
PWM1 Controller Reset
17
1
read-write
0
PWM1 controller normal operation
#0
1
PWM1 controller reset
#1
USCI0RST
USCI0 Controller Reset
8
1
read-write
0
USCI0 controller normal operation
#0
1
USCI0 controller reset
#1
USCI1RST
USCI1 Controller Reset
9
1
read-write
0
USCI1 controller normal operation
#0
1
USCI1 controller reset
#1
MODCTL
SYS_MODCTL
Modulation Control Register
0xC0
read-write
n
0x0
0x0
MODEN
Modulation Function Enable Bit\nThis bit enables modulation funcion by modulating with PWM0 channel output and USCI0(USCI0_DAT0) or UART0(UART0_TXD) output.
0
1
read-write
0
Modulation Function Disabled
#0
1
Modulation Function Enabled
#1
MODH
Modulation at Data High\nSelect modulation pulse(PWM0) at high or low of UART0_TXD or USCI0_DAT0\n0: Modulation pulse at UART0_TXD low or USCI0_DAT0 low.\n1: Modulation pulse at UART0_TXD high or USCI0_DAT0 high.
1
1
read-write
MODPWMSEL
PWM0 Channel Select for Modulation\nSelect the PWM0 channel to modulate with the UART0_TXD or USCI0_DAT0.\n0000: PWM0 Channel 0 modulate with UART0_TXD.\n0001: PWM0 Channel 1 modulate with UART0_TXD.\n0010: PWM0 Channel 2 modulate with UART0_TXD.\n0011: PWM0 Channel 3 modulete with UART0_TXD.\n0100: PWM0 Channel 4 modulete with UART0_TXD.\n0101: PWM0 Channel 5 modulete with UART0_TXD.\n0110: Reserved.\n0111: Reserved.\n1000: PWM0 Channel 0 modulate with USCI0_DAT0.\n1001: PWM0 Channel 1 modulate with USCI0_DAT0.\n1010: PWM0 Channel 2 modulate with USCI0_DAT0.\n1011: PWM0 Channel 3 modulete with USCI0_DAT0.\n1100: PWM0 Channel 4 modulete with USCI0_DAT0.\n1101: PWM0 Channel 5 modulete with USCI0_DAT0.\n1110: Reserved.\n1111: Reserved.\nNote: This bis is valid while MODEN (SYS_MODCTL[0]) is set to 1.
4
4
read-write
PDID
SYS_PDID
Part Device Identification Number Register
0x0
read-only
n
0x0
0x0
PDID
Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used.
0
32
read-only
PORCTL
SYS_PORCTL
Power-On-reset Controller Register
0x24
read-write
n
0x0
0x0
POROFF
Power-on Reset Enable Bit (Write Protect)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will be active again when this field is set to another value or chip is reset by other reset source, including:\nnRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
16
read-write
PORDISAN
SYS_PORDISAN
Analog POR Disable Control Register
0x1EC
read-write
n
0x0
0x0
POROFFAN
Power-on Reset Enable Bit (Write Protect)\nAfter powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field.\nThe analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including:\nnRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
16
read-write
REGLCTL
SYS_REGLCTL
Register Lock Control Register
0x100
read-write
n
0x0
0x0
REGLCTL
Register Lock Control Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.\nREGLCTL[0]\nRegister Lock Control Disable Index (Read Only)
0
8
read-write
0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
0
1
Write-protection Disabled for writing protected registers
1
RSTSTS
SYS_RSTSTS
System Reset Status Register
0x4
-1
read-write
n
0x0
0x0
BODRF
BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
4
1
read-write
0
No reset from BOD
#0
1
The BOD had issued the reset signal to reset the system
#1
CPULKRF
CPU Lockup Reset Flag\nNote: Write 1 to clear this bit to 0.\nNote 2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset.
8
1
read-write
0
No reset from CPU lockup happened
#0
1
The Cortex-M0 lockup happened and chip is reset
#1
CPURF
CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex- M0 Core and Flash Memory Controller (FMC).\nNote: Write to clear this bit to 0.
7
1
read-write
0
No reset from CPU
#0
1
The Cortex-M0 Core and FMC are reset by software setting CPURST to 1
#1
LVRF
LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
3
1
read-write
0
No reset from LVR
#0
1
LVR controller had issued the reset signal to reset the system
#1
PINRF
NRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
1
1
read-write
0
No reset from nRESET pin
#0
1
Pin nRESET had issued the reset signal to reset the system
#1
PORF
POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
0
1
read-write
0
No reset from POR or CHIPRST
#0
1
Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system
#1
SYSRF
System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
5
1
read-write
0
No reset from Cortex-M0
#0
1
The Cortex- M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core
#1
WDTRF
WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote 1: Write 1 to clear this bit to 0.\nNote 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
2
1
read-write
0
No reset from watchdog timer or window watchdog timer
#0
1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
#1
SRAM_BISTCTL
SYS_SRAM_BISTCTL
System SRAM BIST Test Control Register
0xD0
read-write
n
0x0
0x0
FMCBIST
FMC CACHE BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CACHE RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
System CACHE BIST Disabled
#0
1
System CACHE BIST Enabled
#1
PDMABIST
PDMA BIST Enable Bit (Write Protect)\nThis bit enables BIST test for PDMA RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
system PDMA BIST Disabled
#0
1
system PDMA BIST Enabled
#1
SRBIST
SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for SRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
system SRAM BIST Disabled
#0
1
system SRAM BIST Enabled
#1
SRS0
SRAM Bank0 Section 0 BIST Select (Write Protect)\nThis bit define if the bank0 section0 (0x2000_0000~0x2000_7FFF) of SRAM is selected or not when doing bist test.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote: At least one section of SRAM should be selected when doing SRAM bist test.
16
1
read-write
0
SRAM bank0 section0 is deselected when doing bist test
#0
1
SRAM bank0 section0 is selected when doing bist test
#1
SRS1
SRAM Bank0 Section 1 BIST Select (Write Protect)\nThis bit define if the bank0 section1 (0x2000_8000~0x2000_FFFF) of SRAM is selected or not when doing bist test.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote: At least one section of SRAM should be selected when doing SRAM bist test.
17
1
read-write
0
SRAM bank0 section1 is deselected when doing bist test
#0
1
SRAM bank0 section1 is selected when doing bist test
#1
SRS2
SRAM Bank0 Section 2 BIST Select (Write Protect)\nThis bit define if the bank0 section2 (0x2001_0000~0x2001_7FFF) of SRAM is selected or not when doing bist test.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote: At least one section of SRAM should be selected when doing SRAM bist test.
18
1
read-write
0
SRAM back0 section2 is deselected when doing bist test
#0
1
SRAM back0 section2 is selected when doing bist test
#1
USBBIST
USB BIST Enable Bit (Write Protect) \nThis bit enables BIST test for USB RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
system USB BIST Disabled
#0
1
system USB BIST Enabled
#1
SRAM_BISTSTS
SYS_SRAM_BISTSTS
System SRAM BIST Test Status Register
0xD4
read-only
n
0x0
0x0
CR0BISTEF
CACHE SRAM BIST Fail Flag
1
1
read-only
0
System CACHE RAM BIST test pass
#0
1
System CACHE RAM BIST test failed
#1
CRBEND
CACHE SRAM BIST Test Finish
17
1
read-only
0
System CACHE RAM BIST is active
#0
1
System CACHE RAM BIST test finished
#1
PDMABISTF
PDMA SRAM BIST Failed Flag
7
1
read-only
0
PDMA SRAM BIST pass
#0
1
PDMA SRAM BIST failed
#1
PDMAEND
PDMA SRAM BIST Test Finish
23
1
read-only
0
PDMA SRAM BIST is active
#0
1
PDMA SRAM BIST test finish
#1
SRBEND
System SRAM BIST Test Finish
16
1
read-only
0
System SRAM BIST active
#0
1
System SRAM BIST finish
#1
SRBISTEF
System SRAM BIST Fail Flag
0
1
read-only
0
System SRAM BIST test pass
#0
1
System SRAM BIST test fail
#1
USBBEF
USB SRAM BIST Fail Flag
4
1
read-only
0
USB SRAM BIST test pass
#0
1
USB SRAM BIST test fail
#1
USBBEND
USB SRAM BIST Test Finish
20
1
read-only
0
USB SRAM BIST is active
#0
1
USB SRAM BIST test finish
#1
SRAM_ERRADDR
SYS_SRAM_ERRADDR
System SRAM Parity Check Error Address Register
0xE4
read-only
n
0x0
0x0
ERRADDR
System SRAM Parity Error Address\nThis register shows system SRAM parity error byte address.
0
32
read-only
SRAM_INTCTL
SYS_SRAM_INTCTL
System SRAM Interrupt Enable Control Register
0xDC
read-write
n
0x0
0x0
PERRIEN
SRAM Parity Check Error Interrupt Enable Bit
0
1
read-write
0
SRAM parity check error interrupt Disabled
#0
1
SRAM parity check error interrupt Enabled
#1
SRAM_STATUS
SYS_SRAM_STATUS
System SRAM Parity Error Status Register
0xE0
read-write
n
0x0
0x0
PERRIF
SRAM Parity Check Error Flag\nThis bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0.
0
1
read-write
0
No System SRAM parity error
#0
1
System SRAM parity error occur
#1
TMR01
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TIMER0_CAP
TIMER0_CAP
Timer0 Capture Data Register
0x10
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
0
24
read-only
TIMER0_CMP
TIMER0_CMP
Timer0 Comparator Register
0x4
read-write
n
0x0
0x0
CMPDAT
Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
0
24
read-write
TIMER0_CNT
TIMER0_CNT
Timer0 Data Register
0xC
read-only
n
0x0
0x0
CNT
Timer Data Register\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.
0
24
read-only
TIMER0_CTL
TIMER0_CTL
Timer0 Control Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1.
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CAPSRC
Capture Pin Source Selection
16
1
read-write
0
Capture Function source is from TMx_EXT (x= 0~3) pin
#0
1
Capture Function source is from internal ACMP output signal or LIRC. User can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which internal ACMP output signal or LIRC as timer capture source
#1
CNTEN
Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote 2: When TMR0/TMR2 INTRGEN is set to 1, this bit is forced to 1. When INTRGEN is 1 and TMR1/TMR3 CAPIF (TIMERx_EINTSTS[0]) is 1, this bit is forced to 0.
24
1
read-write
0
Event counter mode Disabled
#0
1
Event counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer time-out interrupt Disabled
#0
1
Timer time-out interrupt Enabled
#1
INTRGEN
Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.\nNote: For Timer1/3, this bit is ignored and the read back value is always 0.
10
1
read-write
0
Inter-Timer Trigger mode Disabled
#0
1
Inter-Timer Trigger mode Enabled
#1
OPMODE
Timer Counting Mode Select
27
2
read-write
0
The timer controller is operated in One-shot mode
#00
1
The timer controller is operated in Periodic mode
#01
2
The timer controller is operated in Toggle-output mode
#10
3
The timer controller is operated in Continuous Counting mode
#11
PSC
Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
0
8
read-write
RSTCNT
Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared.
26
1
read-write
0
No effect
#0
1
Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit
#1
TGLPINSEL
Toggle-output Pin Select
22
1
read-write
0
Toggle mode output to Tx (Timer Event Counter Pin)
#0
1
Toggle mode output to Tx_EXT (Timer External Capture Pin)
#1
TRGADC
Trigger ADC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.
21
1
read-write
0
Timer interrupt trigger ADC Disabled
#0
1
Timer interrupt trigger ADC Enabled
#1
TRGBPWM
Trigger BPWM Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM.
9
1
read-write
0
Timer interrupt trigger BPWM Disabled
#0
1
Timer interrupt trigger BPWM Enabled
#1
TRGPDMA
Trigger PDMA Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.
8
1
read-write
0
Timer interrupt trigger PDMA Disabled
#0
1
Timer interrupt trigger PDMA Enabled
#1
TRGPWM
Trigger PWM Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM.
19
1
read-write
0
Timer interrupt trigger PWM Disabled
#0
1
Timer interrupt trigger PWM Enabled
#1
TRGSSEL
Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.
18
1
read-write
0
Timer time-out interrupt signal is used to trigger PWM, BPWM, ADC and PDMA
#0
1
Capture interrupt signal is used to trigger PWM, BPWM, ADC and PDMA
#1
WKEN
Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
23
1
read-write
0
Wake-up function Disabled if timer interrupt signal generated
#0
1
Wake-up function Enabled if timer interrupt signal generated
#1
TIMER0_EINTSTS
TIMER0_EINTSTS
Timer0 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
CAPIF
Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
0
1
read-write
0
TMx_EXT (x= 0~3) pin interrupt did not occur
#0
1
TMx_EXT (x= 0~3) pin interrupt occurred
#1
TIMER0_EXTCTL
TIMER0_EXTCTL
Timer0 External Control Register
0x14
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled
#0
1
TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled
#1
CAPEDGE
Timer External Capture Pin Edge Detect
1
2
read-write
0
A Falling edge on Tx_EXT (x= 0~3) pin, LIRC or ACMPx (x=0~1) will be detected
#00
1
A Rising edge on Tx_EXT (x= 0~3) pin, LIRC or ACMPx (x=0~1) will be detected
#01
2
Either Rising or Falling edge on Tx_EXT (x= 0~3) pin, LIRC or ACMPx (x=0~1) will be detected
#10
3
Reserved.
#11
CAPEN
Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1/TMR3 CAPEN will be forced to 1 when TMR0/TMR2 INTRGEN is enabled.
3
1
read-write
0
Capture source Disabled
#0
1
Capture source Enabled
#1
CAPFUNCS
Capture Function Selection
4
1
read-write
0
External Capture Mode Enabled
#0
1
External Reset Mode Enabled
#1
CAPIEN
Timer External Capture Interrupt Enable Bit
5
1
read-write
0
TMx_EXT (x= 0~3) pin, LIRC, or ACMP detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~3) pin, LIRC, or ACMP detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~3) pin de-bounce Disabled
#0
1
TMx (x= 0~3) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
ECNTSSEL
Event Counter Source Selection to Trigger Event Counter Function
16
1
read-write
0
Event Counter input source is from TMx (x= 0~3) pin
#0
1
Event Counter input source is from USB internal SOF output signal
#1
INTERCAPSEL
Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1.
8
3
read-write
0
Capture Function source is from internal ACMP0 output signal
#000
1
Capture Function source is from internal ACMP1 output signal
#001
5
Capture Function source is from LIRC
#101
TIMER0_INTSTS
TIMER0_INTSTS
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
#1
TIMER1_CAP
TIMER1_CAP
Timer1 Capture Data Register
0x30
read-write
n
0x0
0x0
TIMER1_CMP
TIMER1_CMP
Timer1 Comparator Register
0x24
read-write
n
0x0
0x0
TIMER1_CNT
TIMER1_CNT
Timer1 Data Register
0x2C
read-write
n
0x0
0x0
TIMER1_CTL
TIMER1_CTL
Timer1 Control Register
0x20
read-write
n
0x0
0x0
TIMER1_EINTSTS
TIMER1_EINTSTS
Timer1 External Interrupt Status Register
0x38
read-write
n
0x0
0x0
TIMER1_EXTCTL
TIMER1_EXTCTL
Timer1 External Control Register
0x34
read-write
n
0x0
0x0
TIMER1_INTSTS
TIMER1_INTSTS
Timer1 Interrupt Status Register
0x28
read-write
n
0x0
0x0
TMR23
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TIMER2_CAP
TIMER2_CAP
Timer2 Capture Data Register
0x10
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
0
24
read-only
TIMER2_CMP
TIMER2_CMP
Timer2 Comparator Register
0x4
read-write
n
0x0
0x0
CMPDAT
Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
0
24
read-write
TIMER2_CNT
TIMER2_CNT
Timer2 Data Register
0xC
read-only
n
0x0
0x0
CNT
Timer Data Register\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.
0
24
read-only
TIMER2_CTL
TIMER2_CTL
Timer2 Control Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1.
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CAPSRC
Capture Pin Source Selection
16
1
read-write
0
Capture Function source is from TMx_EXT (x= 0~3) pin
#0
1
Capture Function source is from internal ACMP output signal or LIRC. User can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which internal ACMP output signal or LIRC as timer capture source
#1
CNTEN
Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote 2: When TMR0/TMR2 INTRGEN is set to 1, this bit is forced to 1. When INTRGEN is 1 and TMR1/TMR3 CAPIF (TIMERx_EINTSTS[0]) is 1, this bit is forced to 0.
24
1
read-write
0
Event counter mode Disabled
#0
1
Event counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer time-out interrupt Disabled
#0
1
Timer time-out interrupt Enabled
#1
INTRGEN
Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.\nNote: For Timer1/3, this bit is ignored and the read back value is always 0.
10
1
read-write
0
Inter-Timer Trigger mode Disabled
#0
1
Inter-Timer Trigger mode Enabled
#1
OPMODE
Timer Counting Mode Select
27
2
read-write
0
The timer controller is operated in One-shot mode
#00
1
The timer controller is operated in Periodic mode
#01
2
The timer controller is operated in Toggle-output mode
#10
3
The timer controller is operated in Continuous Counting mode
#11
PSC
Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
0
8
read-write
RSTCNT
Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared.
26
1
read-write
0
No effect
#0
1
Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit
#1
TGLPINSEL
Toggle-output Pin Select
22
1
read-write
0
Toggle mode output to Tx (Timer Event Counter Pin)
#0
1
Toggle mode output to Tx_EXT (Timer External Capture Pin)
#1
TRGADC
Trigger ADC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.
21
1
read-write
0
Timer interrupt trigger ADC Disabled
#0
1
Timer interrupt trigger ADC Enabled
#1
TRGBPWM
Trigger BPWM Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM.
9
1
read-write
0
Timer interrupt trigger BPWM Disabled
#0
1
Timer interrupt trigger BPWM Enabled
#1
TRGPDMA
Trigger PDMA Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.
8
1
read-write
0
Timer interrupt trigger PDMA Disabled
#0
1
Timer interrupt trigger PDMA Enabled
#1
TRGPWM
Trigger PWM Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM.
19
1
read-write
0
Timer interrupt trigger PWM Disabled
#0
1
Timer interrupt trigger PWM Enabled
#1
TRGSSEL
Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.
18
1
read-write
0
Timer time-out interrupt signal is used to trigger PWM, BPWM, ADC and PDMA
#0
1
Capture interrupt signal is used to trigger PWM, BPWM, ADC and PDMA
#1
WKEN
Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
23
1
read-write
0
Wake-up function Disabled if timer interrupt signal generated
#0
1
Wake-up function Enabled if timer interrupt signal generated
#1
TIMER2_EINTSTS
TIMER2_EINTSTS
Timer2 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
CAPIF
Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
0
1
read-write
0
TMx_EXT (x= 0~3) pin interrupt did not occur
#0
1
TMx_EXT (x= 0~3) pin interrupt occurred
#1
TIMER2_EXTCTL
TIMER2_EXTCTL
Timer2 External Control Register
0x14
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled
#0
1
TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled
#1
CAPEDGE
Timer External Capture Pin Edge Detect
1
2
read-write
0
A Falling edge on Tx_EXT (x= 0~3) pin, LIRC or ACMPx (x=0~1) will be detected
#00
1
A Rising edge on Tx_EXT (x= 0~3) pin, LIRC or ACMPx (x=0~1) will be detected
#01
2
Either Rising or Falling edge on Tx_EXT (x= 0~3) pin, LIRC or ACMPx (x=0~1) will be detected
#10
3
Reserved.
#11
CAPEN
Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1/TMR3 CAPEN will be forced to 1 when TMR0/TMR2 INTRGEN is enabled.
3
1
read-write
0
Capture source Disabled
#0
1
Capture source Enabled
#1
CAPFUNCS
Capture Function Selection
4
1
read-write
0
External Capture Mode Enabled
#0
1
External Reset Mode Enabled
#1
CAPIEN
Timer External Capture Interrupt Enable Bit
5
1
read-write
0
TMx_EXT (x= 0~3) pin, LIRC, or ACMP detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~3) pin, LIRC, or ACMP detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~3) pin de-bounce Disabled
#0
1
TMx (x= 0~3) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
ECNTSSEL
Event Counter Source Selection to Trigger Event Counter Function
16
1
read-write
0
Event Counter input source is from TMx (x= 0~3) pin
#0
1
Event Counter input source is from USB internal SOF output signal
#1
INTERCAPSEL
Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1.
8
3
read-write
0
Capture Function source is from internal ACMP0 output signal
#000
1
Capture Function source is from internal ACMP1 output signal
#001
5
Capture Function source is from LIRC
#101
TIMER2_INTSTS
TIMER2_INTSTS
Timer2 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
#1
TIMER3_CAP
TIMER3_CAP
Timer3 Capture Data Register
0x30
read-write
n
0x0
0x0
TIMER3_CMP
TIMER3_CMP
Timer3 Comparator Register
0x24
read-write
n
0x0
0x0
TIMER3_CNT
TIMER3_CNT
Timer3 Data Register
0x2C
read-write
n
0x0
0x0
TIMER3_CTL
TIMER3_CTL
Timer3 Control Register
0x20
read-write
n
0x0
0x0
TIMER3_EINTSTS
TIMER3_EINTSTS
Timer3 External Interrupt Status Register
0x38
read-write
n
0x0
0x0
TIMER3_EXTCTL
TIMER3_EXTCTL
Timer3 External Control Register
0x34
read-write
n
0x0
0x0
TIMER3_INTSTS
TIMER3_INTSTS
Timer3 Interrupt Status Register
0x28
read-write
n
0x0
0x0
UART0
UART Register Map
UART
0x0
0x0
0x30
registers
n
0x3C
0x10
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
BRKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1.
0
4
read-write
LINRXEN
LIN RX Enable Bit
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.134.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.134.\nNote: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.134.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.134.
24
4
read-write
UART_BRCOMP
UART_BRCOMP
UART Baud Rate Compensation Register
0x3C
read-write
n
0x0
0x0
BRCOMP
Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit.
0
9
read-write
BRCOMPDEC
Baud Rate Compensation Decrease
31
1
read-write
0
Positive (increase one module clock) compensation for each compensated bit
#0
1
Negative (decrease one module clock) compensation for each compensated bit
#1
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
read-write
n
0x0
0x0
STCOMP
Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Inerrupt Disabled
#0
1
Single-wire Bit Error Detect Inerrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated.
#1
RDAIF
Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.\nNote 2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
Parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
PSS
Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
Parity bit generated and checked by software
#1
RXDINV
RX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection\nThis field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.\nNote 3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.1313 and Figure 6.1314 for UART function mode.\nNote 2: Refer to Figure 6.1317 and Figure 6.1318 for RS-485 function mode.\nNote 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote 1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UART1
UART Register Map
UART
0x0
0x0
0x30
registers
n
0x3C
0x10
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
BRKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1.
0
4
read-write
LINRXEN
LIN RX Enable Bit
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.134.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.134.\nNote: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.134.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.134.
24
4
read-write
UART_BRCOMP
UART_BRCOMP
UART Baud Rate Compensation Register
0x3C
read-write
n
0x0
0x0
BRCOMP
Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit.
0
9
read-write
BRCOMPDEC
Baud Rate Compensation Decrease
31
1
read-write
0
Positive (increase one module clock) compensation for each compensated bit
#0
1
Negative (decrease one module clock) compensation for each compensated bit
#1
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
read-write
n
0x0
0x0
STCOMP
Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Inerrupt Disabled
#0
1
Single-wire Bit Error Detect Inerrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.\nNote 2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
Parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
PSS
Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
Parity bit generated and checked by software
#1
RXDINV
RX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection\nThis field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.\nNote 3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.1313 and Figure 6.1314 for UART function mode.\nNote 2: Refer to Figure 6.1317 and Figure 6.1318 for RS-485 function mode.\nNote 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote 1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UART2
UART Register Map
UART
0x0
0x0
0x30
registers
n
0x40
0xC
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
BRKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1.
0
4
read-write
LINRXEN
LIN RX Enable Bit
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.134.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.134.\nNote: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.134.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.134.
24
4
read-write
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
read-write
n
0x0
0x0
STCOMP
Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Inerrupt Disabled
#0
1
Single-wire Bit Error Detect Inerrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.\nNote 2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
Parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
PSS
Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
Parity bit generated and checked by software
#1
RXDINV
RX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection\nThis field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.\nNote 3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.1313 and Figure 6.1314 for UART function mode.\nNote 2: Refer to Figure 6.1317 and Figure 6.1318 for RS-485 function mode.\nNote 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote 1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UART3
UART Register Map
UART
0x0
0x0
0x30
registers
n
0x40
0xC
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
BRKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1.
0
4
read-write
LINRXEN
LIN RX Enable Bit
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.134.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.134.\nNote: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.134.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.134.
24
4
read-write
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
read-write
n
0x0
0x0
STCOMP
Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Inerrupt Disabled
#0
1
Single-wire Bit Error Detect Inerrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.\nNote 2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
Parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
PSS
Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
Parity bit generated and checked by software
#1
RXDINV
RX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection\nThis field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.\nNote 3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.1313 and Figure 6.1314 for UART function mode.\nNote 2: Refer to Figure 6.1317 and Figure 6.1318 for RS-485 function mode.\nNote 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote 1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UART4
UART Register Map
UART
0x0
0x0
0x30
registers
n
0x3C
0x10
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
BRKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1.
0
4
read-write
LINRXEN
LIN RX Enable Bit
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.134.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.134.\nNote: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.134.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.134.
24
4
read-write
UART_BRCOMP
UART_BRCOMP
UART Baud Rate Compensation Register
0x3C
read-write
n
0x0
0x0
BRCOMP
Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit.
0
9
read-write
BRCOMPDEC
Baud Rate Compensation Decrease
31
1
read-write
0
Positive (increase one module clock) compensation for each compensated bit
#0
1
Negative (decrease one module clock) compensation for each compensated bit
#1
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
read-write
n
0x0
0x0
STCOMP
Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Inerrupt Disabled
#0
1
Single-wire Bit Error Detect Inerrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.\nNote 2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
Parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
PSS
Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
Parity bit generated and checked by software
#1
RXDINV
RX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection\nThis field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.\nNote 3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.1313 and Figure 6.1314 for UART function mode.\nNote 2: Refer to Figure 6.1317 and Figure 6.1318 for RS-485 function mode.\nNote 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote 1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UART5
UART Register Map
UART
0x0
0x0
0x30
registers
n
0x3C
0x10
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
BRKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1.
0
4
read-write
LINRXEN
LIN RX Enable Bit
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.134.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.134.\nNote: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.134.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.134.
24
4
read-write
UART_BRCOMP
UART_BRCOMP
UART Baud Rate Compensation Register
0x3C
read-write
n
0x0
0x0
BRCOMP
Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit.
0
9
read-write
BRCOMPDEC
Baud Rate Compensation Decrease
31
1
read-write
0
Positive (increase one module clock) compensation for each compensated bit
#0
1
Negative (decrease one module clock) compensation for each compensated bit
#1
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
read-write
n
0x0
0x0
STCOMP
Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Inerrupt Disabled
#0
1
Single-wire Bit Error Detect Inerrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.\nNote 2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
Parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
PSS
Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
Parity bit generated and checked by software
#1
RXDINV
RX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection\nThis field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.\nNote 3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.1313 and Figure 6.1314 for UART function mode.\nNote 2: Refer to Figure 6.1317 and Figure 6.1318 for RS-485 function mode.\nNote 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote 1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UART6
UART Register Map
UART
0x0
0x0
0x30
registers
n
0x40
0xC
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
BRKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1.
0
4
read-write
LINRXEN
LIN RX Enable Bit
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.134.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.134.\nNote: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.134.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.134.
24
4
read-write
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
read-write
n
0x0
0x0
STCOMP
Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Inerrupt Disabled
#0
1
Single-wire Bit Error Detect Inerrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.\nNote 2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
Parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
PSS
Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
Parity bit generated and checked by software
#1
RXDINV
RX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection\nThis field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.\nNote 3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.1313 and Figure 6.1314 for UART function mode.\nNote 2: Refer to Figure 6.1317 and Figure 6.1318 for RS-485 function mode.\nNote 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote 1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UART7
UART Register Map
UART
0x0
0x0
0x30
registers
n
0x40
0xC
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
BRKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1.
0
4
read-write
LINRXEN
LIN RX Enable Bit
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.134.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.134.\nNote: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.134.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.134.
24
4
read-write
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
read-write
n
0x0
0x0
STCOMP
Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Inerrupt Disabled
#0
1
Single-wire Bit Error Detect Inerrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.\nNote 2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
Parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
PSS
Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
Parity bit generated and checked by software
#1
RXDINV
RX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted\nNote 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection\nThis field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.\nNote 3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.1313 and Figure 6.1314 for UART function mode.\nNote 2: Refer to Figure 6.1317 and Figure 6.1318 for RS-485 function mode.\nNote 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote 1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it.\nNote 3: This bit is valid in UART0, UART1, UART4 and UART5.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UI2C0
UI2CI2C Register Map
UI2CI2C
0x0
0x0
0x4
registers
n
0x2C
0xC
registers
n
0x44
0x24
registers
n
0x8
0x4
registers
n
0x88
0x8
registers
n
UI2C_ADDRMSK0
UI2C_ADDRMSK0
USCI Device Address Mask Register 0
0x4C
read-write
n
0x0
0x0
ADDRMSK
USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
0
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
UI2C_ADDRMSK1
UI2C_ADDRMSK1
USCI Device Address Mask Register 1
0x50
read-write
n
0x0
0x0
UI2C_ADMAT
UI2C_ADMAT
I2C Slave Match Address Register
0x88
read-write
n
0x0
0x0
ADMAT0
USCI Address 0 Match Status Register\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
USCI Address 1 Match Status Register\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
UI2C_BRGEN
UI2C_BRGEN
USCI Baud Rate Generator Register
0x8
-1
read-write
n
0x0
0x0
CLKDIV
Clock Divider
16
10
read-write
DSCNT
Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fSAMP_CLK = fDIV_CLK
#00
1
fSAMP_CLK = fPROT_CLK
#01
2
fSAMP_CLK = fSCLK
#10
3
fSAMP_CLK = fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Time measurement counter is Disabled
#0
1
Time measurement counter is Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
UI2C_CTL
UI2C_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
UI2C_DEVADDR0
UI2C_DEVADDR0
USCI Device Address Register 0
0x44
read-write
n
0x0
0x0
DEVADDR
Device Address\nIn I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].\nNote 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.\nNote 2: When software set 10'h000, the address can not be used.
0
10
read-write
UI2C_DEVADDR1
UI2C_DEVADDR1
USCI Device Address Register 1
0x48
read-write
n
0x0
0x0
UI2C_LINECTL
UI2C_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
UI2C_PROTCTL
UI2C_PROTCTL
USCI Protocol Control Register
0x5C
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
1
1
read-write
ADDR10EN
Address 10-bit Function Enable Bit
4
1
read-write
0
Address match 10 bit function Disabled
#0
1
Address match 10 bit function Enabled
#1
GCFUNC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
MONEN
Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
9
1
read-write
0
The monitor mode Disabled
#0
1
The monitor mode Enabled
#1
PROTEN
I2C Protocol Enable Bit
31
1
read-write
0
I2C Protocol Disabled
#0
1
I2C Protocol Enabled
#1
PTRG
I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTIEN is disabled.
5
1
write-only
0
I2C's stretch disabled and the I2C protocol function will go ahead
#0
1
I2C's stretch active
#1
SCLOUTEN
SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
8
1
read-write
0
SCL output will be forced high due to open drain mechanism
#0
1
I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt
#1
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
3
1
read-write
STO
I2C STOP Control
2
1
read-write
TOCNT
Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode.
16
10
read-write
UI2C_PROTIEN
UI2C_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
ACKIEN
Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
6
1
read-write
0
The acknowledge interrupt Disabled
#0
1
The acknowledge interrupt Enabled
#1
ARBLOIEN
Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
4
1
read-write
0
The arbitration lost interrupt Disabled
#0
1
The arbitration lost interrupt Enabled
#1
ERRIEN
Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERRIF (UI2C_PROTSTS [12])).
5
1
read-write
0
The error interrupt Disabled
#0
1
The error interrupt Enabled
#1
NACKIEN
Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master.
3
1
read-write
0
The non - acknowledge interrupt Disabled
#0
1
The non - acknowledge interrupt Enabled
#1
STARIEN
START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected.
1
1
read-write
0
The start condition interrupt Disabled
#0
1
The start condition interrupt Enabled
#1
STORIEN
STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected.
2
1
read-write
0
The stop condition interrupt Disabled
#0
1
The stop condition interrupt Enabled
#1
TOIEN
Time-out Interrupt Enable Bit\nIn I2C protocol, this bit enables the interrupt generation in case of a time-out event.
0
1
read-write
0
The time-out interrupt Disabled
#0
1
The time-out interrupt Enabled
#1
UI2C_PROTSTS
UI2C_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
ACKIF
Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit
13
1
read-write
0
An acknowledge has not been received
#0
1
An acknowledge has been received
#1
ARBLOIF
Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit
11
1
read-write
0
An arbitration has not been lost
#0
1
An arbitration has been lost
#1
BUSHANG
Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
18
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is hang-up status for transmission
#1
ERRARBLO
Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
19
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is error arbitration lost status for transmission
#1
ERRIF
Error Interrupt Flag\nNote 1: It is cleared by software writing 1 into this bit\nNote 2: This bit is set for slave mode, and user must write 1 into STO register to the defined 'not addressed' slave mode.
12
1
read-write
0
An I2C error has not been detected
#0
1
An I2C error has been detected
#1
NACKIF
Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit
10
1
read-write
0
A non - acknowledge has not been received
#0
1
A non - acknowledge has been received
#1
ONBUSY
On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
6
1
read-write
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
SLAREAD
Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
15
1
read-write
0
A slave R/W bit is 1 has not been detected
#0
1
A slave R/W bit is 1 has been detected
#1
SLASEL
Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
14
1
read-write
0
The device is not selected as slave
#0
1
The device is selected as slave
#1
STARIF
Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.\nNote: It is cleared by software writing 1 into this bit
8
1
read-write
0
A start condition has not yet been detected
#0
1
A start condition has been detected
#1
STORIF
Stop Condition Received Interrupt Flag\nNote 1: It is cleared by software writing 1 into this bit
9
1
read-write
0
A stop condition has not yet been detected
#0
1
A stop condition has been detected
#1
TOIF
Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit
5
1
read-write
0
A time-out interrupt status has not occurred
#0
1
A time-out interrupt status has occurred
#1
WKAKDONE
Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set.
16
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WRSTSWK
Read/Write Status Bit in Address Wake-up Frame
17
1
read-write
0
Write command be record on the address match wake-up frame
#0
1
Read command be record on the address match wake-up frame
#1
UI2C_RXDAT
UI2C_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.
0
16
read-only
UI2C_TMCTL
UI2C_TMCTL
I2C Timing Configure Control Register
0x8C
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode.\nNote: Hold time adjust function can only work in master mode, when slave mode, this field should set as 0
16
9
read-write
STCTL
Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode..
0
9
read-write
UI2C_TXDAT
UI2C_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
UI2C_WKCTL
UI2C_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
WKADDREN
Wake-up Address Match Enable Bit
1
1
read-write
0
The chip is woken up according receive 'START' symbol
#0
1
The chip is woken up according address match
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
UI2C_WKSTS
UI2C_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
UI2C1
UI2CI2C Register Map
UI2CI2C
0x0
0x0
0x4
registers
n
0x2C
0xC
registers
n
0x44
0x24
registers
n
0x8
0x4
registers
n
0x88
0x8
registers
n
UI2C_ADDRMSK0
UI2C_ADDRMSK0
USCI Device Address Mask Register 0
0x4C
read-write
n
0x0
0x0
ADDRMSK
USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
0
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
UI2C_ADDRMSK1
UI2C_ADDRMSK1
USCI Device Address Mask Register 1
0x50
read-write
n
0x0
0x0
UI2C_ADMAT
UI2C_ADMAT
I2C Slave Match Address Register
0x88
read-write
n
0x0
0x0
ADMAT0
USCI Address 0 Match Status Register\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
USCI Address 1 Match Status Register\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
UI2C_BRGEN
UI2C_BRGEN
USCI Baud Rate Generator Register
0x8
-1
read-write
n
0x0
0x0
CLKDIV
Clock Divider
16
10
read-write
DSCNT
Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fSAMP_CLK = fDIV_CLK
#00
1
fSAMP_CLK = fPROT_CLK
#01
2
fSAMP_CLK = fSCLK
#10
3
fSAMP_CLK = fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Time measurement counter is Disabled
#0
1
Time measurement counter is Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
UI2C_CTL
UI2C_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
UI2C_DEVADDR0
UI2C_DEVADDR0
USCI Device Address Register 0
0x44
read-write
n
0x0
0x0
DEVADDR
Device Address\nIn I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].\nNote 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.\nNote 2: When software set 10'h000, the address can not be used.
0
10
read-write
UI2C_DEVADDR1
UI2C_DEVADDR1
USCI Device Address Register 1
0x48
read-write
n
0x0
0x0
UI2C_LINECTL
UI2C_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
UI2C_PROTCTL
UI2C_PROTCTL
USCI Protocol Control Register
0x5C
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
1
1
read-write
ADDR10EN
Address 10-bit Function Enable Bit
4
1
read-write
0
Address match 10 bit function Disabled
#0
1
Address match 10 bit function Enabled
#1
GCFUNC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
MONEN
Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
9
1
read-write
0
The monitor mode Disabled
#0
1
The monitor mode Enabled
#1
PROTEN
I2C Protocol Enable Bit
31
1
read-write
0
I2C Protocol Disabled
#0
1
I2C Protocol Enabled
#1
PTRG
I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTIEN is disabled.
5
1
write-only
0
I2C's stretch disabled and the I2C protocol function will go ahead
#0
1
I2C's stretch active
#1
SCLOUTEN
SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
8
1
read-write
0
SCL output will be forced high due to open drain mechanism
#0
1
I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt
#1
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
3
1
read-write
STO
I2C STOP Control
2
1
read-write
TOCNT
Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode.
16
10
read-write
UI2C_PROTIEN
UI2C_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
ACKIEN
Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
6
1
read-write
0
The acknowledge interrupt Disabled
#0
1
The acknowledge interrupt Enabled
#1
ARBLOIEN
Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
4
1
read-write
0
The arbitration lost interrupt Disabled
#0
1
The arbitration lost interrupt Enabled
#1
ERRIEN
Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERRIF (UI2C_PROTSTS [12])).
5
1
read-write
0
The error interrupt Disabled
#0
1
The error interrupt Enabled
#1
NACKIEN
Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master.
3
1
read-write
0
The non - acknowledge interrupt Disabled
#0
1
The non - acknowledge interrupt Enabled
#1
STARIEN
START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected.
1
1
read-write
0
The start condition interrupt Disabled
#0
1
The start condition interrupt Enabled
#1
STORIEN
STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected.
2
1
read-write
0
The stop condition interrupt Disabled
#0
1
The stop condition interrupt Enabled
#1
TOIEN
Time-out Interrupt Enable Bit\nIn I2C protocol, this bit enables the interrupt generation in case of a time-out event.
0
1
read-write
0
The time-out interrupt Disabled
#0
1
The time-out interrupt Enabled
#1
UI2C_PROTSTS
UI2C_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
ACKIF
Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit
13
1
read-write
0
An acknowledge has not been received
#0
1
An acknowledge has been received
#1
ARBLOIF
Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit
11
1
read-write
0
An arbitration has not been lost
#0
1
An arbitration has been lost
#1
BUSHANG
Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
18
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is hang-up status for transmission
#1
ERRARBLO
Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
19
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is error arbitration lost status for transmission
#1
ERRIF
Error Interrupt Flag\nNote 1: It is cleared by software writing 1 into this bit\nNote 2: This bit is set for slave mode, and user must write 1 into STO register to the defined 'not addressed' slave mode.
12
1
read-write
0
An I2C error has not been detected
#0
1
An I2C error has been detected
#1
NACKIF
Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit
10
1
read-write
0
A non - acknowledge has not been received
#0
1
A non - acknowledge has been received
#1
ONBUSY
On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
6
1
read-write
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
SLAREAD
Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
15
1
read-write
0
A slave R/W bit is 1 has not been detected
#0
1
A slave R/W bit is 1 has been detected
#1
SLASEL
Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
14
1
read-write
0
The device is not selected as slave
#0
1
The device is selected as slave
#1
STARIF
Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.\nNote: It is cleared by software writing 1 into this bit
8
1
read-write
0
A start condition has not yet been detected
#0
1
A start condition has been detected
#1
STORIF
Stop Condition Received Interrupt Flag\nNote 1: It is cleared by software writing 1 into this bit
9
1
read-write
0
A stop condition has not yet been detected
#0
1
A stop condition has been detected
#1
TOIF
Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit
5
1
read-write
0
A time-out interrupt status has not occurred
#0
1
A time-out interrupt status has occurred
#1
WKAKDONE
Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set.
16
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WRSTSWK
Read/Write Status Bit in Address Wake-up Frame
17
1
read-write
0
Write command be record on the address match wake-up frame
#0
1
Read command be record on the address match wake-up frame
#1
UI2C_RXDAT
UI2C_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.
0
16
read-only
UI2C_TMCTL
UI2C_TMCTL
I2C Timing Configure Control Register
0x8C
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode.\nNote: Hold time adjust function can only work in master mode, when slave mode, this field should set as 0
16
9
read-write
STCTL
Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode..
0
9
read-write
UI2C_TXDAT
UI2C_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
UI2C_WKCTL
UI2C_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
WKADDREN
Wake-up Address Match Enable Bit
1
1
read-write
0
The chip is woken up according receive 'START' symbol
#0
1
The chip is woken up according address match
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
UI2C_WKSTS
UI2C_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
USBD
USBD Register Map
USBD
0x0
0x0
0x1C
registers
n
0x20
0x4
registers
n
0x500
0x80
registers
n
0x88
0xC
registers
n
ATTR
USBD_ATTR
USB Device Bus Status and Attribution Register
0x10
-1
read-write
n
0x0
0x0
BYTEM
CPU Access USB SRAM Size Mode Selection
10
1
read-write
0
Word mode: The size of the transfer from CPU to USB SRAM can be Word only
#0
1
Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only
#1
DPPUEN
Pull-up Resistor on USB_DP Enable Bit
8
1
read-write
0
Pull-up resistor in USB_D+ bus Disabled
#0
1
Pull-up resistor in USB_D+ bus Active
#1
L1RESUME
LPM L1 Resume (Read Only)
13
1
read-only
0
Bus no LPM L1 state resume
#0
1
LPM L1 state Resume from LPM L1 state suspend
#1
L1SUSPEND
LPM L1 Suspend (Read Only)
12
1
read-only
0
Bus no L1 state suspend
#0
1
This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged
#1
LPMACK
LPM Token Acknowledge Enable Bit
11
1
read-write
0
the valid LPM Token will be NYET
#0
1
the valid LPM Token will be ACK
#1
PHYEN
PHY Transceiver Function Enable Bit
4
1
read-write
0
PHY transceiver function Disabled
#0
1
PHY transceiver function Enabled
#1
PWRDN
Power-down PHY Transceiver, Low Active
9
1
read-write
0
Power-down related circuit of PHY transceiver
#0
1
Turn-on related circuit of PHY transceiver
#1
RESUME
Resume Status (Read Only)
2
1
read-only
0
No bus resume
#0
1
Resume from suspend
#1
RWAKEUP
Remote Wake-up
5
1
read-write
0
Release the USB bus from K state
#0
1
Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up
#1
SUSPEND
Suspend Status (Read Only)
1
1
read-only
0
Bus no suspend
#0
1
Bus idle more than 3ms, either cable is plugged off or host is sleeping
#1
TOUT
Time-out Status (Read Only)\nWhen USB Device controller after received setup token or out token, USB controller stay J state to wait data package. If the waiting time exceeds 18-bit length timing, TOUT flag will be generated.
3
1
read-only
0
No time-out
#0
1
No Bus response more than 18 bits time
#1
USBEN
USB Controller Enable Bit
7
1
read-write
0
USB Controller Disabled
#0
1
USB Controller Enabled
#1
USBRST
USB Reset Status (Read Only)
0
1
read-only
0
Bus no reset
#0
1
Bus reset when SE0 (single-ended 0) more than 2.5us
#1
BUFSEG0
USBD_BUFSEG0
Endpoint 0 Buffer Segmentation Register
0x500
read-write
n
0x0
0x0
BUFSEG
Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + { BUFSEG, 3'b000}\nRefer to the section 6.22.5.7 for the endpoint SRAM structure and its description.
3
6
read-write
BUFSEG1
USBD_BUFSEG1
Endpoint 1 Buffer Segmentation Register
0x510
read-write
n
0x0
0x0
BUFSEG2
USBD_BUFSEG2
Endpoint 2 Buffer Segmentation Register
0x520
read-write
n
0x0
0x0
BUFSEG3
USBD_BUFSEG3
Endpoint 3 Buffer Segmentation Register
0x530
read-write
n
0x0
0x0
BUFSEG4
USBD_BUFSEG4
Endpoint 4 Buffer Segmentation Register
0x540
read-write
n
0x0
0x0
BUFSEG5
USBD_BUFSEG5
Endpoint 5 Buffer Segmentation Register
0x550
read-write
n
0x0
0x0
BUFSEG6
USBD_BUFSEG6
Endpoint 6 Buffer Segmentation Register
0x560
read-write
n
0x0
0x0
BUFSEG7
USBD_BUFSEG7
Endpoint 7 Buffer Segmentation Register
0x570
read-write
n
0x0
0x0
CFG0
USBD_CFG0
Endpoint 0 Configuration Register
0x508
read-write
n
0x0
0x0
CSTALL
Clear STALL Response
9
1
read-write
0
Disable the device to clear the STALL handshake in setup stage
#0
1
Clear the device to response STALL handshake in setup stage
#1
DSQSYNC
Data Sequence Synchronization\nIN Token Transaction:\nThis bit is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on it.\nOUT Token Transaction:\nThis bit is used to specify the DATA0 or DATA1 PID in the following OUT token transaction. Hardware will toggle automatically OUT token base on this bit.
7
1
read-write
0
DATA0 PID
#0
1
DATA1 PID
#1
EPNUM
Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint
0
4
read-write
ISOCH
Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake.
4
1
read-write
0
No Isochronous endpoint
#0
1
Isochronous endpoint
#1
STATE
Endpoint STATE
5
2
read-write
0
Endpoint is Disabled
#00
1
Out endpoint
#01
2
IN endpoint
#10
3
Undefined
#11
CFG1
USBD_CFG1
Endpoint 1 Configuration Register
0x518
read-write
n
0x0
0x0
CFG2
USBD_CFG2
Endpoint 2 Configuration Register
0x528
read-write
n
0x0
0x0
CFG3
USBD_CFG3
Endpoint 3 Configuration Register
0x538
read-write
n
0x0
0x0
CFG4
USBD_CFG4
Endpoint 4 Configuration Register
0x548
read-write
n
0x0
0x0
CFG5
USBD_CFG5
Endpoint 5 Configuration Register
0x558
read-write
n
0x0
0x0
CFG6
USBD_CFG6
Endpoint 6 Configuration Register
0x568
read-write
n
0x0
0x0
CFG7
USBD_CFG7
Endpoint 7 Configuration Register
0x578
read-write
n
0x0
0x0
CFGP0
USBD_CFGP0
Endpoint 0 Set Stall and Clear In/Out Ready Control Register
0x50C
read-write
n
0x0
0x0
CLRRDY
Clear Ready\nWhen the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.\nFor IN token, write '1' to clear the IN token had ready to transmit the data to USB.\nFor OUT token, write '1' to clear the OUT token had ready to receive the data from USB.\nThis bit is write 1 only and is always 0 when it is read back.
0
1
read-write
SSTALL
Set STALL
1
1
read-write
0
Disable the device to response STALL
#0
1
Set the device to respond STALL automatically
#1
CFGP1
USBD_CFGP1
Endpoint 1 Set Stall and Clear In/Out Ready Control Register
0x51C
read-write
n
0x0
0x0
CFGP2
USBD_CFGP2
Endpoint 2 Set Stall and Clear In/Out Ready Control Register
0x52C
read-write
n
0x0
0x0
CFGP3
USBD_CFGP3
Endpoint 3 Set Stall and Clear In/Out Ready Control Register
0x53C
read-write
n
0x0
0x0
CFGP4
USBD_CFGP4
Endpoint 4 Set Stall and Clear In/Out Ready Control Register
0x54C
read-write
n
0x0
0x0
CFGP5
USBD_CFGP5
Endpoint 5 Set Stall and Clear In/Out Ready Control Register
0x55C
read-write
n
0x0
0x0
CFGP6
USBD_CFGP6
Endpoint 6 Set Stall and Clear In/Out Ready Control Register
0x56C
read-write
n
0x0
0x0
CFGP7
USBD_CFGP7
Endpoint 7 Set Stall and Clear In/Out Ready Control Register
0x57C
read-write
n
0x0
0x0
EPSTS
USBD_EPSTS
USB Device Endpoint Status Register
0xC
read-only
n
0x0
0x0
OV
Overrun\nIt indicates that the received data is over the maximum payload number or not.\nif received data is over the maximum payload number, the extra data will be ignored.
7
1
read-only
0
No overrun
#0
1
Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes
#1
EPSTS0
USBD_EPSTS0
USB Device Endpoint Status Register 0
0x20
read-only
n
0x0
0x0
EPSTS5
Endpoint 5 Status\nThese bits are used to indicate the current status of this endpoint
20
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS6
Endpoint 6 Status\nThese bits are used to indicate the current status of this endpoint
24
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS7
Endpoint 7 Status\nThese bits are used to indicate the current status of this endpoint
28
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
FADDR
USBD_FADDR
USB Device Function Address Register
0x8
read-write
n
0x0
0x0
FADDR
USB Device Function Address
0
7
read-write
FN
USBD_FN
USB Frame Number Register
0x8C
read-only
n
0x0
0x0
FN
Frame Number\nThese bits contain the 11-bits frame number in the last received SOF packet.
0
11
read-only
INTEN
USBD_INTEN
USB Device Interrupt Enable Register
0x0
read-write
n
0x0
0x0
BUSIEN
Bus Event Interrupt Enable Bit
0
1
read-write
0
BUS event interrupt Disabled
#0
1
BUS event interrupt Enabled
#1
INNAKEN
Active NAK Function and Its Status in IN Token
15
1
read-write
0
When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 register, so that the USB interrupt event will not be asserted
#0
1
IN NAK status will be updated to USBD_EPSTS0 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token
#1
NEVWKIEN
USB No-event-wake-up Interrupt Enable Bit
3
1
read-write
0
No-event-wake-up Interrupt Disabled
#0
1
No-event-wake-up Interrupt Enabled
#1
SOFIEN
Start of Frame Interrupt Enable Bit
4
1
read-write
0
SOF Interrupt Disabled
#0
1
SOF Interrupt Enabled
#1
USBIEN
USB Event Interrupt Enable Bit
1
1
read-write
0
USB event interrupt Disabled
#0
1
USB event interrupt Enabled
#1
VBDETIEN
VBUS Detection Interrupt Enable Bit
2
1
read-write
0
VBUS detection Interrupt Disabled
#0
1
VBUS detection Interrupt Enabled
#1
WKEN
Wake-up Function Enable Bit
8
1
read-write
0
USB wake-up function Disabled
#0
1
USB wake-up function Enabled
#1
INTSTS
USBD_INTSTS
USB Device Interrupt Event Status Register
0x4
read-write
n
0x0
0x0
BUSIF
BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus.
0
1
read-write
0
No BUS event occurred
#0
1
Bus event occurred check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0]
#1
EPEVT0
Endpoint 0's USB Event Status
16
1
read-write
0
No event occurred in endpoint 0
#0
1
USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1]
#1
EPEVT1
Endpoint 1's USB Event Status
17
1
read-write
0
No event occurred in endpoint 1
#0
1
USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1]
#1
EPEVT2
Endpoint 2's USB Event Status
18
1
read-write
0
No event occurred in endpoint 2
#0
1
USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1]
#1
EPEVT3
Endpoint 3's USB Event Status
19
1
read-write
0
No event occurred in endpoint 3
#0
1
USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1]
#1
EPEVT4
Endpoint 4's USB Event Status
20
1
read-write
0
No event occurred in endpoint 4
#0
1
USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1]
#1
EPEVT5
Endpoint 5's USB Event Status
21
1
read-write
0
No event occurred in endpoint 5
#0
1
USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1]
#1
EPEVT6
Endpoint 6's USB Event Status
22
1
read-write
0
No event occurred in endpoint 6
#0
1
USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1]
#1
EPEVT7
Endpoint 7's USB Event Status
23
1
read-write
0
No event occurred in endpoint 7
#0
1
USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1]
#1
NEVWKIF
No-event-wake-up Interrupt Status
3
1
read-write
0
NEVWK event does not occur
#0
1
No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3]
#1
SETUP
Setup Event Status
31
1
read-write
0
No Setup event
#0
1
Setup event occurred, cleared by write 1 to USBD_INTSTS[31]
#1
SOFIF
Start of Frame Interrupt Status
4
1
read-write
0
SOF event does not occur
#0
1
SOF event occurred, cleared by write 1 to USBD_INTSTS[4]
#1
USBIF
USB Event Interrupt Status\nThe USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
1
1
read-write
0
No USB event occurred
#0
1
USB event occurred, check EPSTS0~7[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~7 and SETUP (USBD_INTSTS[31])
#1
VBDETIF
VBUS Detection Interrupt Status
2
1
read-write
0
There is not attached/detached event in the USB
#0
1
There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2]
#1
LPMATTR
USBD_LPMATTR
USB LPM Attribution Register
0x88
read-only
n
0x0
0x0
LPMBESL
LPM Best Effort Service Latency\nThese bits contain the BESL value received with last ACK LPM Token
4
4
read-only
LPMLINKSTS
LPM Link State\nThese bits contain the bLinkState received with last ACK LPM Token
0
4
read-only
LPMRWAKUP
LPM Remote Wakeup\nThis bit contains the bRemoteWake value received with last ACK LPM Token
8
1
read-only
MXPLD0
USBD_MXPLD0
Endpoint 0 Maximal Payload Register
0x504
read-write
n
0x0
0x0
MXPLD
Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.\n(1) When the register is written by CPU, \nFor IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.\nFor OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.\n(2) When the register is read by CPU,\nFor IN token, the value of MXPLD is indicated by the data length be transmitted to host\nFor OUT token, the value of MXPLD is indicated the actual data length receiving from host.\nNote: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
0
9
read-write
MXPLD1
USBD_MXPLD1
Endpoint 1 Maximal Payload Register
0x514
read-write
n
0x0
0x0
MXPLD2
USBD_MXPLD2
Endpoint 2 Maximal Payload Register
0x524
read-write
n
0x0
0x0
MXPLD3
USBD_MXPLD3
Endpoint 3 Maximal Payload Register
0x534
read-write
n
0x0
0x0
MXPLD4
USBD_MXPLD4
Endpoint 4 Maximal Payload Register
0x544
read-write
n
0x0
0x0
MXPLD5
USBD_MXPLD5
Endpoint 5 Maximal Payload Register
0x554
read-write
n
0x0
0x0
MXPLD6
USBD_MXPLD6
Endpoint 6 Maximal Payload Register
0x564
read-write
n
0x0
0x0
MXPLD7
USBD_MXPLD7
Endpoint 7 Maximal Payload Register
0x574
read-write
n
0x0
0x0
SE0
USBD_SE0
USB Device Drive SE0 Control Register
0x90
-1
read-write
n
0x0
0x0
SE0
Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
0
1
read-write
0
Normal operation
#0
1
Force USB PHY transceiver to drive SE0
#1
STBUFSEG
USBD_STBUFSEG
SETUP Token Buffer Segmentation Register
0x18
read-write
n
0x0
0x0
STBUFSEG
SETUP Token Buffer Segmentation\nIt is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is\nUSBD_SRAM address + {STBUFSEG, 3'b000} \nNote: It is used for SETUP token only.
3
6
read-write
VBUSDET
USBD_VBUSDET
USB Device VBUS Detection Register
0x14
read-only
n
0x0
0x0
VBUSDET
Device VBUS Detection
0
1
read-only
0
Controller is not attached to the USB host
#0
1
Controller is attached to the USB host
#1
USPI0
USCISPI Register Map
USCISPI
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x28
0x1C
registers
n
0x54
0x14
registers
n
USPI_BRGEN
USPI_BRGEN
USCI Baud Rate Generator Register
0x8
-1
read-write
n
0x0
0x0
CLKDIV
Clock Divider
16
10
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fDIV_CLK
#00
1
fPROT_CLK
#01
2
fSCLK
#10
3
fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Time measurement counter Disabled
#0
1
Time measurement counter Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
USPI_BUFCTL
USPI_BUFCTL
USCI Transmit/Receive Buffer Control Register
0x38
read-write
n
0x0
0x0
RXCLR
Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle.
15
1
read-write
0
No effect
#0
1
The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic
#1
RXOVIEN
Receive Buffer Overrun Interrupt Enable Bit
14
1
read-write
0
Receive overrun interrupt Disabled
#0
1
Receive overrun interrupt Enabled
#1
RXRST
Receive Reset\nNote: It is cleared automatically after one PCLK cycle.
17
1
read-write
0
No effect
#0
1
Reset the receive-related counters, state machine, and the content of receive shift register and data buffer
#1
TXCLR
Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle.
7
1
read-write
0
No effect
#0
1
The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic
#1
TXRST
Transmit Reset
16
1
read-write
0
No effect
#0
1
Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer
#1
TXUDRIEN
Slave Transmit Under Run Interrupt Enable Bit
6
1
read-write
0
Transmit under-run interrupt Disabled
#0
1
Transmit under-run interrupt Enabled
#1
USPI_BUFSTS
USPI_BUFSTS
USCI Transmit/Receive Buffer Status Register
0x3C
-1
read-only
n
0x0
0x0
RXEMPTY
Receive Buffer Empty Indicator
0
1
read-only
0
Receive buffer is not empty
#0
1
Receive buffer is empty
#1
RXFULL
Receive Buffer Full Indicator
1
1
read-only
0
Receive buffer is not full
#0
1
Receive buffer is full
#1
RXOVIF
Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit.
3
1
read-only
0
A receive buffer overrun event has not been detected
#0
1
A receive buffer overrun event has been detected
#1
TXEMPTY
Transmit Buffer Empty Indicator
8
1
read-only
0
Transmit buffer is not empty
#0
1
Transmit buffer is empty and available for the next transmission datum
#1
TXFULL
Transmit Buffer Full Indicator
9
1
read-only
0
Transmit buffer is not full
#0
1
Transmit buffer is full
#1
TXUDRIF
Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit
11
1
read-only
0
A transmit buffer under-run event has not been detected
#0
1
A transmit buffer under-run event has been detected
#1
USPI_CLKIN
USPI_CLKIN
USCI Input Clock Signal Configuration Register
0x28
read-write
n
0x0
0x0
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_CTL
USPI_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
USPI_CTLIN0
USPI_CTLIN0
USCI Input Control Signal Configuration Register 0
0x20
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_DATIN0
USPI_DATIN0
USCI Input Data Signal Configuration Register 0
0x10
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_INTEN
USPI_INTEN
USCI Interrupt Enable Register
0x4
read-write
n
0x0
0x0
RXENDIEN
Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\nNote: The receive finish event happens when hardware receives the last bit of RX data into shift data unit.
4
1
read-write
0
The receive end interrupt Disabled
#0
1
The receive end interrupt Enabled
#1
RXSTIEN
Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\nNote: For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
3
1
read-write
0
The receive start interrupt Disabled
#0
1
The receive start interrupt Enabled
#1
TXENDIEN
Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\nNote: The transmit finish event happens when hardware sends the last bit of TX data from shift data unit.
2
1
read-write
0
The transmit finish interrupt Disabled
#0
1
The transmit finish interrupt Enabled
#1
TXSTIEN
Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\nNote: The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
1
1
read-write
0
The transmit start interrupt Disabled
#0
1
The transmit start interrupt Enabled
#1
USPI_LINECTL
USPI_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
CTLOINV
Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal.
7
1
read-write
0
No effect
#0
1
The control signal will be inverted before its output
#1
DATOINV
Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pins.
5
1
read-write
0
Data output values of USCIx_DAT0/1 pins are not inverted
#0
1
Data output values of USCIx_DAT0/1 pins are inverted
#1
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
USPI_PDMACTL
USPI_PDMACTL
USCI PDMA Control Register
0x40
read-write
n
0x0
0x0
PDMAEN
PDMA Mode Enable Bit
3
1
read-write
0
PDMA function Disabled
#0
1
PDMA function Enabled
#1
PDMARST
PDMA Reset
0
1
read-write
0
No effect
#0
1
Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically
#1
RXPDMAEN
PDMA Receive Channel Available
2
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
1
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
USPI_PROTCTL
USPI_PROTCTL
USCI Protocol Control Register
0x5C
-1
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)
3
1
read-write
0
Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit
#0
1
Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
PROTEN
SPI Protocol Enable Bit
31
1
read-write
0
SPI Protocol Disabled
#0
1
SPI Protocol Enabled
#1
SCLKMODE
Serial Bus Clock Mode\nThis bit field defines the SCLK idle status, data transmit, and data receive edge.
6
2
read-write
SLAVE
Slave Mode Selection
0
1
read-write
0
Master mode
#0
1
Slave mode
#1
SLV3WIRE
Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
1
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLVTOCNT
Slave Mode Time-out Period (Slave Only)\nIn Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function.\nExample: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
16
10
read-write
SS
Slave Select Control (Master Only)\nIf AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select back to inactive state.\nNote: In SPI protocol, the internal slave select signal is active high.
2
1
read-write
SUSPITV
Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\nExample:
8
4
read-write
TSMSEL
Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
12
3
read-write
TXUDRPOL
Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data value of USCIx_DAT1 when no data is available for transferring.
28
1
read-write
0
The output data value is 0 if TX under run event occurs
#0
1
The output data value is 1 if TX under run event occurs
#1
USPI_PROTIEN
USPI_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]). Bit count error event occurs.
3
1
read-write
0
The Slave mode bit count error interrupt Disabled
#0
1
The Slave mode bit count error interrupt Enabled
#1
SLVTOIEN
Slave Time-out Interrupt Enable Bit\nIn SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
2
1
read-write
0
The Slave time-out interrupt Disabled
#0
1
The Slave time-out interrupt Enabled
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
1
1
read-write
0
Slave select active interrupt generation Disabled
#0
1
Slave select active interrupt generation Enabled
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
0
1
read-write
0
Slave select inactive interrupt generation Disabled
#0
1
Slave select inactive interrupt generation Enabled
#1
USPI_PROTSTS
USPI_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
17
1
read-only
0
SPI is in idle state
#0
1
SPI is in busy state
#1
RXENDIF
Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The receive end event happens when hardware receives the last bit of RX data into shift data unit.
4
1
read-write
0
Receive end event did not occur
#0
1
Receive end event occurred
#1
RXSTIF
Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
3
1
read-write
0
Receive start event did not occur
#0
1
Receive start event occurred
#1
SLVBEIF
Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit. If the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]), bit count error event occurs.
6
1
read-write
0
Slave bit count error event did not occur
#0
1
Slave bit count error event occurred
#1
SLVTOIF
Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit
5
1
read-write
0
Slave time-out event did not occur
#0
1
Slave time-out event occurred
#1
SLVUDR
Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
18
1
read-only
0
Slave transmit under run event does not occur
#0
1
Slave transmit under run event occurs
#1
SSACTIF
Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high.
9
1
read-write
0
The slave select signal has not changed to active
#0
1
The slave select signal has changed to active
#1
SSINAIF
Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high.
8
1
read-write
0
The slave select signal has not changed to inactive
#0
1
The slave select signal has changed to inactive
#1
SSLINE
Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus.
16
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXENDIF
Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit end event happens when hardware sends the last bit of TX data from shift data unit.
2
1
read-write
0
Transmit end event did not occur
#0
1
Transmit end event occurred
#1
TXSTIF
Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
1
1
read-write
0
Transmit start event did not occur
#0
1
Transmit start event occurred
#1
USPI_RXDAT
USPI_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.
0
16
read-only
USPI_TXDAT
USPI_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
PORTDIR
Port Direction Control
16
1
write-only
0
The data pin is configured as output mode
#0
1
The data pin is configured as input mode
#1
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
0
16
write-only
USPI_WKCTL
USPI_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
PDBOPT
Power Down Blocking Option
2
1
read-write
0
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately
#0
1
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
USPI_WKSTS
USPI_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
USPI1
USCISPI Register Map
USCISPI
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x28
0x1C
registers
n
0x54
0x14
registers
n
USPI_BRGEN
USPI_BRGEN
USCI Baud Rate Generator Register
0x8
-1
read-write
n
0x0
0x0
CLKDIV
Clock Divider
16
10
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fDIV_CLK
#00
1
fPROT_CLK
#01
2
fSCLK
#10
3
fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Time measurement counter Disabled
#0
1
Time measurement counter Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
USPI_BUFCTL
USPI_BUFCTL
USCI Transmit/Receive Buffer Control Register
0x38
read-write
n
0x0
0x0
RXCLR
Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle.
15
1
read-write
0
No effect
#0
1
The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic
#1
RXOVIEN
Receive Buffer Overrun Interrupt Enable Bit
14
1
read-write
0
Receive overrun interrupt Disabled
#0
1
Receive overrun interrupt Enabled
#1
RXRST
Receive Reset\nNote: It is cleared automatically after one PCLK cycle.
17
1
read-write
0
No effect
#0
1
Reset the receive-related counters, state machine, and the content of receive shift register and data buffer
#1
TXCLR
Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle.
7
1
read-write
0
No effect
#0
1
The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic
#1
TXRST
Transmit Reset
16
1
read-write
0
No effect
#0
1
Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer
#1
TXUDRIEN
Slave Transmit Under Run Interrupt Enable Bit
6
1
read-write
0
Transmit under-run interrupt Disabled
#0
1
Transmit under-run interrupt Enabled
#1
USPI_BUFSTS
USPI_BUFSTS
USCI Transmit/Receive Buffer Status Register
0x3C
-1
read-only
n
0x0
0x0
RXEMPTY
Receive Buffer Empty Indicator
0
1
read-only
0
Receive buffer is not empty
#0
1
Receive buffer is empty
#1
RXFULL
Receive Buffer Full Indicator
1
1
read-only
0
Receive buffer is not full
#0
1
Receive buffer is full
#1
RXOVIF
Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit.
3
1
read-only
0
A receive buffer overrun event has not been detected
#0
1
A receive buffer overrun event has been detected
#1
TXEMPTY
Transmit Buffer Empty Indicator
8
1
read-only
0
Transmit buffer is not empty
#0
1
Transmit buffer is empty and available for the next transmission datum
#1
TXFULL
Transmit Buffer Full Indicator
9
1
read-only
0
Transmit buffer is not full
#0
1
Transmit buffer is full
#1
TXUDRIF
Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit
11
1
read-only
0
A transmit buffer under-run event has not been detected
#0
1
A transmit buffer under-run event has been detected
#1
USPI_CLKIN
USPI_CLKIN
USCI Input Clock Signal Configuration Register
0x28
read-write
n
0x0
0x0
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_CTL
USPI_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
USPI_CTLIN0
USPI_CTLIN0
USCI Input Control Signal Configuration Register 0
0x20
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_DATIN0
USPI_DATIN0
USCI Input Data Signal Configuration Register 0
0x10
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_INTEN
USPI_INTEN
USCI Interrupt Enable Register
0x4
read-write
n
0x0
0x0
RXENDIEN
Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\nNote: The receive finish event happens when hardware receives the last bit of RX data into shift data unit.
4
1
read-write
0
The receive end interrupt Disabled
#0
1
The receive end interrupt Enabled
#1
RXSTIEN
Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\nNote: For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
3
1
read-write
0
The receive start interrupt Disabled
#0
1
The receive start interrupt Enabled
#1
TXENDIEN
Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\nNote: The transmit finish event happens when hardware sends the last bit of TX data from shift data unit.
2
1
read-write
0
The transmit finish interrupt Disabled
#0
1
The transmit finish interrupt Enabled
#1
TXSTIEN
Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\nNote: The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
1
1
read-write
0
The transmit start interrupt Disabled
#0
1
The transmit start interrupt Enabled
#1
USPI_LINECTL
USPI_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
CTLOINV
Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal.
7
1
read-write
0
No effect
#0
1
The control signal will be inverted before its output
#1
DATOINV
Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pins.
5
1
read-write
0
Data output values of USCIx_DAT0/1 pins are not inverted
#0
1
Data output values of USCIx_DAT0/1 pins are inverted
#1
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
USPI_PDMACTL
USPI_PDMACTL
USCI PDMA Control Register
0x40
read-write
n
0x0
0x0
PDMAEN
PDMA Mode Enable Bit
3
1
read-write
0
PDMA function Disabled
#0
1
PDMA function Enabled
#1
PDMARST
PDMA Reset
0
1
read-write
0
No effect
#0
1
Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically
#1
RXPDMAEN
PDMA Receive Channel Available
2
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
1
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
USPI_PROTCTL
USPI_PROTCTL
USCI Protocol Control Register
0x5C
-1
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)
3
1
read-write
0
Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit
#0
1
Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
PROTEN
SPI Protocol Enable Bit
31
1
read-write
0
SPI Protocol Disabled
#0
1
SPI Protocol Enabled
#1
SCLKMODE
Serial Bus Clock Mode\nThis bit field defines the SCLK idle status, data transmit, and data receive edge.
6
2
read-write
SLAVE
Slave Mode Selection
0
1
read-write
0
Master mode
#0
1
Slave mode
#1
SLV3WIRE
Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
1
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLVTOCNT
Slave Mode Time-out Period (Slave Only)\nIn Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function.\nExample: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
16
10
read-write
SS
Slave Select Control (Master Only)\nIf AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select back to inactive state.\nNote: In SPI protocol, the internal slave select signal is active high.
2
1
read-write
SUSPITV
Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\nExample:
8
4
read-write
TSMSEL
Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
12
3
read-write
TXUDRPOL
Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data value of USCIx_DAT1 when no data is available for transferring.
28
1
read-write
0
The output data value is 0 if TX under run event occurs
#0
1
The output data value is 1 if TX under run event occurs
#1
USPI_PROTIEN
USPI_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]). Bit count error event occurs.
3
1
read-write
0
The Slave mode bit count error interrupt Disabled
#0
1
The Slave mode bit count error interrupt Enabled
#1
SLVTOIEN
Slave Time-out Interrupt Enable Bit\nIn SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
2
1
read-write
0
The Slave time-out interrupt Disabled
#0
1
The Slave time-out interrupt Enabled
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
1
1
read-write
0
Slave select active interrupt generation Disabled
#0
1
Slave select active interrupt generation Enabled
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
0
1
read-write
0
Slave select inactive interrupt generation Disabled
#0
1
Slave select inactive interrupt generation Enabled
#1
USPI_PROTSTS
USPI_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
17
1
read-only
0
SPI is in idle state
#0
1
SPI is in busy state
#1
RXENDIF
Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The receive end event happens when hardware receives the last bit of RX data into shift data unit.
4
1
read-write
0
Receive end event did not occur
#0
1
Receive end event occurred
#1
RXSTIF
Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
3
1
read-write
0
Receive start event did not occur
#0
1
Receive start event occurred
#1
SLVBEIF
Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit. If the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]), bit count error event occurs.
6
1
read-write
0
Slave bit count error event did not occur
#0
1
Slave bit count error event occurred
#1
SLVTOIF
Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit
5
1
read-write
0
Slave time-out event did not occur
#0
1
Slave time-out event occurred
#1
SLVUDR
Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
18
1
read-only
0
Slave transmit under run event does not occur
#0
1
Slave transmit under run event occurs
#1
SSACTIF
Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high.
9
1
read-write
0
The slave select signal has not changed to active
#0
1
The slave select signal has changed to active
#1
SSINAIF
Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high.
8
1
read-write
0
The slave select signal has not changed to inactive
#0
1
The slave select signal has changed to inactive
#1
SSLINE
Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus.
16
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXENDIF
Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit end event happens when hardware sends the last bit of TX data from shift data unit.
2
1
read-write
0
Transmit end event did not occur
#0
1
Transmit end event occurred
#1
TXSTIF
Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
1
1
read-write
0
Transmit start event did not occur
#0
1
Transmit start event occurred
#1
USPI_RXDAT
USPI_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.
0
16
read-only
USPI_TXDAT
USPI_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
PORTDIR
Port Direction Control
16
1
write-only
0
The data pin is configured as output mode
#0
1
The data pin is configured as input mode
#1
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
0
16
write-only
USPI_WKCTL
USPI_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
PDBOPT
Power Down Blocking Option
2
1
read-write
0
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately
#0
1
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
USPI_WKSTS
USPI_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
UUART0
USCIUART Register Map
USCIUART
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x28
0x1C
registers
n
0x54
0x14
registers
n
UUART_BRGEN
UUART_BRGEN
USCI Baud Rate Generator Register
0x8
-1
read-write
n
0x0
0x0
CLKDIV
Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate.
16
10
read-write
DSCNT
Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fSAMP_CLK = fDIV_CLK
#00
1
fSAMP_CLK = fPROT_CLK
#01
2
fSAMP_CLK = fSCLK
#10
3
fSAMP_CLK = fREF_CLK
#11
TMCNTEN
Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Timing measurement counter is Disabled
#0
1
Timing measurement counter is Enabled
#1
TMCNTSRC
Timing Measurement Counter Clock Source Selection
5
1
read-write
0
Timing measurement counter with fPROT_CLK
#0
1
Timing measurement counter with fDIV_CLK
#1
UUART_BUFCTL
UUART_BUFCTL
USCI Transmit/Receive Buffer Control Register
0x38
read-write
n
0x0
0x0
RXCLR
Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle.
15
1
read-write
0
No effect
#0
1
The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic
#1
RXOVIEN
Receive Buffer Overrun Error Interrupt Enable Bit
14
1
read-write
0
Receive overrun interrupt Disabled
#0
1
Receive overrun interrupt Enabled
#1
RXRST
Receive Reset\nNote 1: It is cleared automatically after one PCLK cycle.\nNote 2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1.
17
1
read-write
0
No effect
#0
1
Reset the receive-related counters, state machine, and the content of receive shift register and data buffer
#1
TXCLR
Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle.
7
1
read-write
0
No effect
#0
1
The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic
#1
TXRST
Transmit Reset\nNote: It is cleared automatically after one PCLK cycle.
16
1
read-write
0
No effect
#0
1
Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer
#1
UUART_BUFSTS
UUART_BUFSTS
USCI Transmit/Receive Buffer Status Register
0x3C
-1
read-only
n
0x0
0x0
RXEMPTY
Receive Buffer Empty Indicator
0
1
read-only
0
Receive buffer is not empty
#0
1
Receive buffer is empty
#1
RXFULL
Receive Buffer Full Indicator
1
1
read-only
0
Receive buffer is not full
#0
1
Receive buffer is full
#1
RXOVIF
Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit.
3
1
read-only
0
A receive buffer overrun error event has not been detected
#0
1
A receive buffer overrun error event has been detected
#1
TXEMPTY
Transmit Buffer Empty Indicator
8
1
read-only
0
Transmit buffer is not empty
#0
1
Transmit buffer is empty
#1
TXFULL
Transmit Buffer Full Indicator
9
1
read-only
0
Transmit buffer is not full
#0
1
Transmit buffer is full
#1
UUART_CLKIN
UUART_CLKIN
USCI Input Clock Signal Configuration Register
0x28
read-write
n
0x0
0x0
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_CTL
UUART_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
UUART_CTLIN0
UUART_CTLIN0
USCI Input Control Signal Configuration Register 0
0x20
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_DATIN0
UUART_DATIN0
USCI Input Data Signal Configuration Register 0
0x10
read-write
n
0x0
0x0
EDGEDET
Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode, it is suggested to set this bit field as 10.
3
2
read-write
0
The trigger event activation is disabled
#00
1
A rising edge activates the trigger event of input data signal
#01
2
A falling edge activates the trigger event of input data signal
#10
3
Both edges activate the trigger event of input data signal
#11
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_INTEN
UUART_INTEN
USCI Interrupt Enable Register
0x4
read-write
n
0x0
0x0
RXENDIEN
Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.
4
1
read-write
0
The receive end interrupt Disabled
#0
1
The receive end interrupt Enabled
#1
RXSTIEN
Receive Start Interrupt Enable BIt\nThis bit enables the interrupt generation in case of a receive start event.
3
1
read-write
0
The receive start interrupt Disabled
#0
1
The receive start interrupt Enabled
#1
TXENDIEN
Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.
2
1
read-write
0
The transmit finish interrupt Disabled
#0
1
The transmit finish interrupt Enabled
#1
TXSTIEN
Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.
1
1
read-write
0
The transmit start interrupt Disabled
#0
1
The transmit start interrupt Enabled
#1
UUART_LINECTL
UUART_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
CTLOINV
Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol, the control signal means nRTS signal.
7
1
read-write
0
No effect
#0
1
The control signal will be inverted before its output
#1
DATOINV
Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
5
1
read-write
0
The value of USCIx_DAT1 is equal to the data shift register
#0
1
The value of USCIx_DAT1 is the inversion of data shift register
#1
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In UART protocol, the length can be configured as 6~13 bits.
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
UUART_PDMACTL
UUART_PDMACTL
USCI PDMA Control Register
0x40
read-write
n
0x0
0x0
PDMAEN
PDMA Mode Enable Bit
3
1
read-write
0
PDMA function Disabled
#0
1
PDMA function Enabled
#1
PDMARST
PDMA Reset
0
1
read-write
0
No effect
#0
1
Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically
#1
RXPDMAEN
PDMA Receive Channel Available
2
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
1
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
UUART_PROTCTL
UUART_PROTCTL
USCI Protocol Control Register
0x5C
read-write
n
0x0
0x0
ABREN
Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).
6
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
BCEN
Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
29
1
read-write
0
Transmit Break Control Disabled
#0
1
Transmit Break Control Enabled
#1
BRDETITV
Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTSTS[9]) is set.\nNote: This bit can be cleared to 0 by software writing '0' to the BRDETITV.
16
9
read-write
CTSAUTOEN
nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).
4
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
CTSWKEN
nCTS Wake-up Mode Enable Bit
10
1
read-write
0
nCTS wake-up mode Disabled
#0
1
nCTS wake-up mode Enabled
#1
DATWKEN
Data Wake-up Mode Enable Bit
9
1
read-write
0
Data wake-up mode Disabled
#0
1
Data wake-up mode Enabled
#1
EVENPARITY
Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set.
2
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
PARITYEN
Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame.
1
1
read-write
0
The parity bit Disabled
#0
1
The parity bit Enabled
#1
PROTEN
UART Protocol Enable Bit
31
1
read-write
0
UART Protocol Disabled
#0
1
UART Protocol Enabled
#1
RTSAUDIREN
nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2: This bit has effect only when the RTSAUTOEN is not set.
5
1
read-write
0
nRTS auto direction control Disabled
#0
1
nRTS auto direction control Enabled
#1
RTSAUTOEN
nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set.
3
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
STICKEN
Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information.
26
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
STOPB
Stop Bits\nThis bit defines the number of stop bits in an UART frame.
0
1
read-write
0
The number of stop bits is 1
#0
1
The number of stop bits is 2
#1
WAKECNT
Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode.
11
4
read-write
UUART_PROTIEN
UUART_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
1
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
2
1
read-write
0
Receive line status interrupt Disabled
#0
1
Receive line status interrupt Enabled
#1
UUART_PROTSTS
UUART_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
ABERRSTS
Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.\nNote 1: This bit is set at the same time of ABRDETIF.\nNote 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS.
11
1
read-write
0
Auto-baud rate detect counter is not overrun
#0
1
Auto-baud rate detect counter is overrun
#1
ABRDETIF
Auto-baud Rate Interrupt Flag
This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.
Note: This bit can be cleared by writing '1' to it.
9
1
read-write
0
Auto-baud rate detect function is not done
#0
1
One Bit auto-baud rate detect function is done
#1
BREAK
Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
7
1
read-write
0
No Break is generated
#0
1
Break is generated in the receiver bus
#1
CTSLV
nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input.
17
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
CTSSYNCLV
nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal.
16
1
read-only
0
The internal synchronized nCTS is low
#0
1
The internal synchronized nCTS is high
#1
FRMERR
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
6
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PARITYERR
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
5
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXBUSY
RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver.
10
1
read-only
0
The receiver is Idle
#0
1
The receiver is BUSY
#1
RXENDIF
Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
4
1
read-write
0
A receive finish interrupt status has not occurred
#0
1
A receive finish interrupt status has occurred
#1
RXSTIF
Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
3
1
read-write
0
A receive start interrupt status has not occurred
#0
1
A receive start interrupt status has occurred
#1
TXENDIF
Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
2
1
read-write
0
A transmit end interrupt status has not occurred
#0
1
A transmit end interrupt status has occurred
#1
TXSTIF
Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer.
1
1
read-write
0
A transmit start interrupt status has not occurred
#0
1
A transmit start interrupt status has occurred
#1
UUART_RXDAT
UUART_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]).
0
16
read-only
UUART_TXDAT
UUART_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
UUART_WKCTL
UUART_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
PDBOPT
Power Down Blocking Option
2
1
read-write
0
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately
#0
1
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
UUART_WKSTS
UUART_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
UUART1
USCIUART Register Map
USCIUART
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x28
0x1C
registers
n
0x54
0x14
registers
n
UUART_BRGEN
UUART_BRGEN
USCI Baud Rate Generator Register
0x8
-1
read-write
n
0x0
0x0
CLKDIV
Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate.
16
10
read-write
DSCNT
Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fSAMP_CLK = fDIV_CLK
#00
1
fSAMP_CLK = fPROT_CLK
#01
2
fSAMP_CLK = fSCLK
#10
3
fSAMP_CLK = fREF_CLK
#11
TMCNTEN
Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Timing measurement counter is Disabled
#0
1
Timing measurement counter is Enabled
#1
TMCNTSRC
Timing Measurement Counter Clock Source Selection
5
1
read-write
0
Timing measurement counter with fPROT_CLK
#0
1
Timing measurement counter with fDIV_CLK
#1
UUART_BUFCTL
UUART_BUFCTL
USCI Transmit/Receive Buffer Control Register
0x38
read-write
n
0x0
0x0
RXCLR
Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle.
15
1
read-write
0
No effect
#0
1
The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic
#1
RXOVIEN
Receive Buffer Overrun Error Interrupt Enable Bit
14
1
read-write
0
Receive overrun interrupt Disabled
#0
1
Receive overrun interrupt Enabled
#1
RXRST
Receive Reset\nNote 1: It is cleared automatically after one PCLK cycle.\nNote 2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1.
17
1
read-write
0
No effect
#0
1
Reset the receive-related counters, state machine, and the content of receive shift register and data buffer
#1
TXCLR
Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle.
7
1
read-write
0
No effect
#0
1
The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic
#1
TXRST
Transmit Reset\nNote: It is cleared automatically after one PCLK cycle.
16
1
read-write
0
No effect
#0
1
Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer
#1
UUART_BUFSTS
UUART_BUFSTS
USCI Transmit/Receive Buffer Status Register
0x3C
-1
read-only
n
0x0
0x0
RXEMPTY
Receive Buffer Empty Indicator
0
1
read-only
0
Receive buffer is not empty
#0
1
Receive buffer is empty
#1
RXFULL
Receive Buffer Full Indicator
1
1
read-only
0
Receive buffer is not full
#0
1
Receive buffer is full
#1
RXOVIF
Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit.
3
1
read-only
0
A receive buffer overrun error event has not been detected
#0
1
A receive buffer overrun error event has been detected
#1
TXEMPTY
Transmit Buffer Empty Indicator
8
1
read-only
0
Transmit buffer is not empty
#0
1
Transmit buffer is empty
#1
TXFULL
Transmit Buffer Full Indicator
9
1
read-only
0
Transmit buffer is not full
#0
1
Transmit buffer is full
#1
UUART_CLKIN
UUART_CLKIN
USCI Input Clock Signal Configuration Register
0x28
read-write
n
0x0
0x0
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_CTL
UUART_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
UUART_CTLIN0
UUART_CTLIN0
USCI Input Control Signal Configuration Register 0
0x20
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_DATIN0
UUART_DATIN0
USCI Input Data Signal Configuration Register 0
0x10
read-write
n
0x0
0x0
EDGEDET
Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode, it is suggested to set this bit field as 10.
3
2
read-write
0
The trigger event activation is disabled
#00
1
A rising edge activates the trigger event of input data signal
#01
2
A falling edge activates the trigger event of input data signal
#10
3
Both edges activate the trigger event of input data signal
#11
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_INTEN
UUART_INTEN
USCI Interrupt Enable Register
0x4
read-write
n
0x0
0x0
RXENDIEN
Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.
4
1
read-write
0
The receive end interrupt Disabled
#0
1
The receive end interrupt Enabled
#1
RXSTIEN
Receive Start Interrupt Enable BIt\nThis bit enables the interrupt generation in case of a receive start event.
3
1
read-write
0
The receive start interrupt Disabled
#0
1
The receive start interrupt Enabled
#1
TXENDIEN
Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.
2
1
read-write
0
The transmit finish interrupt Disabled
#0
1
The transmit finish interrupt Enabled
#1
TXSTIEN
Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.
1
1
read-write
0
The transmit start interrupt Disabled
#0
1
The transmit start interrupt Enabled
#1
UUART_LINECTL
UUART_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
CTLOINV
Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol, the control signal means nRTS signal.
7
1
read-write
0
No effect
#0
1
The control signal will be inverted before its output
#1
DATOINV
Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
5
1
read-write
0
The value of USCIx_DAT1 is equal to the data shift register
#0
1
The value of USCIx_DAT1 is the inversion of data shift register
#1
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In UART protocol, the length can be configured as 6~13 bits.
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
UUART_PDMACTL
UUART_PDMACTL
USCI PDMA Control Register
0x40
read-write
n
0x0
0x0
PDMAEN
PDMA Mode Enable Bit
3
1
read-write
0
PDMA function Disabled
#0
1
PDMA function Enabled
#1
PDMARST
PDMA Reset
0
1
read-write
0
No effect
#0
1
Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically
#1
RXPDMAEN
PDMA Receive Channel Available
2
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
1
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
UUART_PROTCTL
UUART_PROTCTL
USCI Protocol Control Register
0x5C
read-write
n
0x0
0x0
ABREN
Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).
6
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
BCEN
Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
29
1
read-write
0
Transmit Break Control Disabled
#0
1
Transmit Break Control Enabled
#1
BRDETITV
Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTSTS[9]) is set.\nNote: This bit can be cleared to 0 by software writing '0' to the BRDETITV.
16
9
read-write
CTSAUTOEN
nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).
4
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
CTSWKEN
nCTS Wake-up Mode Enable Bit
10
1
read-write
0
nCTS wake-up mode Disabled
#0
1
nCTS wake-up mode Enabled
#1
DATWKEN
Data Wake-up Mode Enable Bit
9
1
read-write
0
Data wake-up mode Disabled
#0
1
Data wake-up mode Enabled
#1
EVENPARITY
Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set.
2
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
PARITYEN
Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame.
1
1
read-write
0
The parity bit Disabled
#0
1
The parity bit Enabled
#1
PROTEN
UART Protocol Enable Bit
31
1
read-write
0
UART Protocol Disabled
#0
1
UART Protocol Enabled
#1
RTSAUDIREN
nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2: This bit has effect only when the RTSAUTOEN is not set.
5
1
read-write
0
nRTS auto direction control Disabled
#0
1
nRTS auto direction control Enabled
#1
RTSAUTOEN
nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set.
3
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
STICKEN
Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information.
26
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
STOPB
Stop Bits\nThis bit defines the number of stop bits in an UART frame.
0
1
read-write
0
The number of stop bits is 1
#0
1
The number of stop bits is 2
#1
WAKECNT
Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode.
11
4
read-write
UUART_PROTIEN
UUART_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
1
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
2
1
read-write
0
Receive line status interrupt Disabled
#0
1
Receive line status interrupt Enabled
#1
UUART_PROTSTS
UUART_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
ABERRSTS
Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.\nNote 1: This bit is set at the same time of ABRDETIF.\nNote 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS.
11
1
read-write
0
Auto-baud rate detect counter is not overrun
#0
1
Auto-baud rate detect counter is overrun
#1
ABRDETIF
Auto-baud Rate Interrupt Flag
This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.
Note: This bit can be cleared by writing '1' to it.
9
1
read-write
0
Auto-baud rate detect function is not done
#0
1
One Bit auto-baud rate detect function is done
#1
BREAK
Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
7
1
read-write
0
No Break is generated
#0
1
Break is generated in the receiver bus
#1
CTSLV
nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input.
17
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
CTSSYNCLV
nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal.
16
1
read-only
0
The internal synchronized nCTS is low
#0
1
The internal synchronized nCTS is high
#1
FRMERR
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
6
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PARITYERR
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
5
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXBUSY
RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver.
10
1
read-only
0
The receiver is Idle
#0
1
The receiver is BUSY
#1
RXENDIF
Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
4
1
read-write
0
A receive finish interrupt status has not occurred
#0
1
A receive finish interrupt status has occurred
#1
RXSTIF
Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
3
1
read-write
0
A receive start interrupt status has not occurred
#0
1
A receive start interrupt status has occurred
#1
TXENDIF
Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
2
1
read-write
0
A transmit end interrupt status has not occurred
#0
1
A transmit end interrupt status has occurred
#1
TXSTIF
Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer.
1
1
read-write
0
A transmit start interrupt status has not occurred
#0
1
A transmit start interrupt status has occurred
#1
UUART_RXDAT
UUART_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]).
0
16
read-only
UUART_TXDAT
UUART_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
UUART_WKCTL
UUART_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
PDBOPT
Power Down Blocking Option
2
1
read-write
0
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately
#0
1
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
UUART_WKSTS
UUART_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WDT
WDT Register Map
WDT
0x0
0x0
0xC
registers
n
ALTCTL
WDT_ALTCTL
WDT Alternative Control Register
0x4
read-write
n
0x0
0x0
RSTDSEL
WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT (WDT_RSTCNT[31:0]) to prevent WDT time-out reset happened.\nUser can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: This register will be reset to 0 if WDT time-out reset happened.
0
2
read-write
0
WDT Reset Delay Period is 1026 * WDT_CLK
#00
1
WDT Reset Delay Period is 130 * WDT_CLK
#01
2
WDT Reset Delay Period is 18 * WDT_CLK
#10
3
WDT Reset Delay Period is 3 * WDT_CLK
#11
CTL
WDT_CTL
WDT Control Register
0x0
-1
read-write
n
0x0
0x0
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement affects WDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
IF
WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it.
3
1
read-write
0
WDT time-out interrupt did not occur
#0
1
WDT time-out interrupt occurred
#1
INTEN
WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. \nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
WDT time-out interrupt Disabled
#0
1
WDT time-out interrupt Enabled
#1
RSTEN
WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
WDT time-out reset function Disabled
#0
1
WDT time-out reset function Enabled
#1
RSTF
WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
2
1
read-write
0
WDT time-out reset did not occur
#0
1
WDT time-out reset occurred
#1
SYNC
WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user executes enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Performing enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
30
1
read-only
0
Set WDTEN bit is completed
#0
1
Set WDTEN bit is synchronizing and not become active yet
#1
TOUTSEL
WDT Time-out Interval Selection (Write Protect)\nThese four bits select the time-out interval period for the WDT.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
8
4
read-write
0
24 * WDT_CLK
#0000
1
26 * WDT_CLK
#0001
2
28 * WDT_CLK
#0010
3
210 * WDT_CLK
#0011
4
212 * WDT_CLK
#0100
5
214 * WDT_CLK
#0101
6
216 * WDT_CLK
#0110
7
218 * WDT_CLK
#0111
8
220 * WDT_CLK
#1000
WDTEN
WDT Enable Bit (Write Protect)\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111, this bit is forced as 1 and user cannot change this bit to 0.
7
1
read-write
0
WDT Disabled (This action will reset the internal up counter value)
#0
1
WDT Enabled
#1
WKEN
WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: Chip can be woken up by WDT time-out interrupt signal generated only if WDT clock source is selected to 38.4 kHz internal low speed RC oscillator (LIRC) or LXT.
4
1
read-write
0
Wake-up trigger event Disabled if WDT time-out interrupt signal generated
#0
1
Wake-up trigger event Enabled if WDT time-out interrupt signal generated
#1
WKF
WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the interrupt wake-up flag status of WDT\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: This bit is cleared by writing 1 to it.
5
1
read-write
0
WDT does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated
#1
RSTCNT
WDT_RSTCNT
WDT Reset Counter Register
0x8
write-only
n
0x0
0x0
RSTCNT
WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0.\nNote 1: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
0
32
write-only
WWDT
WWDT Register Map
WWDT
0x0
0x0
0x10
registers
n
CNT
WWDT_CNT
WWDT Counter Value Register
0xC
-1
read-only
n
0x0
0x0
CNTDAT
WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
0
6
read-only
CTL
WWDT_CTL
WWDT Control Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
16
6
read-write
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit\nNote: WWDT down counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects WWDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
WWDT Interrupt Enable Bit\nIf this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
1
1
read-write
0
WWDT counter compare match interrupt Disabled
#0
1
WWDT counter compare match interrupt Enabled
#1
PSCSEL
WWDT Counter Prescale Period Selection
8
4
read-write
0
Pre-scale is 1 Max time-out period is 1 * 64 * WWDT_CLK
#0000
1
Pre-scale is 2 Max time-out period is 2 * 64 * WWDT_CLK
#0001
2
Pre-scale is 4 Max time-out period is 4 * 64 * WWDT_CLK
#0010
3
Pre-scale is 8 Max time-out period is 8 * 64 * WWDT_CLK
#0011
4
Pre-scale is 16 Max time-out period is 16 * 64 * WWDT_CLK
#0100
5
Pre-scale is 32 Max time-out period is 32 * 64 * WWDT_CLK
#0101
6
Pre-scale is 64 Max time-out period is 64 * 64 * WWDT_CLK
#0110
7
Pre-scale is 128 Max time-out period is 128 * 64 * WWDT_CLK
#0111
8
Pre-scale is 192 Max time-out period is 192 * 64 * WWDT_CLK
#1000
9
Pre-scale is 256 Max time-out period is 256 * 64 * WWDT_CLK
#1001
10
Pre-scale is 384 Max time-out period is 384 * 64 * WWDT_CLK
#1010
11
Pre-scale is 512 Max time-out period is 512 * 64 * WWDT_CLK
#1011
12
Pre-scale is 768 Max time-out period is 768 * 64 * WWDT_CLK
#1100
13
Pre-scale is 1024 Max time-out period is 1024 * 64 * WWDT_CLK
#1101
14
Pre-scale is 1536 Max time-out period is 1536 * 64 * WWDT_CLK
#1110
15
Pre-scale is 2048 Max time-out period is 2048 * 64 * WWDT_CLK
#1111
WWDTEN
WWDT Enable Bit
0
1
read-write
0
WWDT counter is stopped
#0
1
WWDT counter starts counting
#1
RLDCNT
WWDT_RLDCNT
WWDT Reload Counter Register
0x0
write-only
n
0x0
0x0
RLDCNT
WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]). If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated immediately.
0
32
write-only
STATUS
WWDT_STATUS
WWDT Status Register
0x8
read-write
n
0x0
0x0
WWDTIF
WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
WWDT counter value matches CMPDAT
#1
WWDTRF
WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
WWDT time-out reset did not occur
#0
1
WWDT time-out reset occurred
#1