nuvoTon M0519AE_v1 2024.05.02 M0519AE_v1 SVD file 8 32 ACMP ACMP Register Map ACMP 0x0 0x0 0x10 registers n ACMP0CR ACMP0CR Analog Comparator 0 Control Register 0x0 read-write n 0x0 0x0 ACMP0INV Analog Comparator 0 Output Inverse Select \n 6 1 read-write 0 The comparator output inverse function Disabled #0 1 The comparator output inverse function Enabled #1 ACMP0_EN Analog Comparator 0 Enable Bit\n 0 1 read-write 0 Analog comparator Disabled #0 1 Analog comparator Enabled #1 ACMP0_HYS_EN CMP Hysteresis Enable Bit\n 2 1 read-write 0 Hysteresis function Disabled #0 1 Hysteresis function Enabled #1 ACMPIE0 Analog Comparator 0 Interrupt Enable Bit\n 1 1 read-write 0 Interrupt function Disabled #0 1 Interrupt function Enabled #1 CN0 Analog Comparator 0 Negative Input Select \n 4 1 read-write 0 The comparator reference pin P8.3/ACMP0_N is selected as the negative comparator input #0 1 The internal band-gap voltage (VBG) is selected as the negative comparator input #1 CP0 Analog Comparator 0 Positive Input Select \n 3 1 read-write 0 The comparator reference pin P8.4/ACMP0_P is selected as the positive comparator input #0 1 The internal OP amplifier 0 output is selected as the positive comparator input #1 ACMP1CR ACMP1CR Analog Comparator 1 Control Register 0x4 read-write n 0x0 0x0 ACMP1INV Analog Comparator 1 Output Inverse Select \n 6 1 read-write 0 The comparator output inverse function Disabled #0 1 The comparator output inverse function Enabled #1 ACMP1_EN Analog Comparator 1 Enable Bit\n 0 1 read-write 0 Analog comparator Disabled #0 1 Analog comparator Enabled #1 ACMP1_HYS_EN CMP Hysteresis Enable Bit\n 2 1 read-write 0 Hysteresis function Disabled #0 1 Hysteresis function Enabled #1 ACMPIE1 Analog Comparator 1 Interrupt Enable Bit\n 1 1 read-write 0 Interrupt function Disabled #0 1 Interrupt function Enabled #1 CN1 Analog Comparator 1 Negative Input Select \n 4 1 read-write 0 The comparator reference pin P6.4/ACMP1_N is selected as the negative comparator input #0 1 The internal band-gap voltage (VBG) is selected as the negative comparator input #1 CP1 Analog Comparator 1 Positive Input Select \n 3 1 read-write 0 The comparator reference pin P6.5/ACMP1_P is selected as the positive comparator input #0 1 The internal OP amplifier 1 output is selected as the positive comparator input #1 ACMP2CR ACMP2CR Analog Comparator 2 Control Register 0x8 read-write n 0x0 0x0 ACMP2INV Analog Comparator 2 Output Inverse Select \n 6 1 read-write 0 The comparator output inverse function Disabled #0 1 The comparator output inverse function Enabled #1 ACMP2_EN Analog Comparator 2 Enable Bit\n 0 1 read-write 0 Analog comparator Disabled #0 1 Analog comparator Enabled #1 ACMP2_HYS_EN CMP Hysteresis Enable Bit\n 2 1 read-write 0 Hysteresis function Disabled #0 1 Hysteresis function Enabled #1 ACMPIE2 Analog Comparator 2 Interrupt Enable Bit\n 1 1 read-write 0 Interrupt function Disabled #0 1 Interrupt function Enabled #1 CN2 Analog Comparator 2 Negative Input Select \n 4 1 read-write 0 The comparator reference pin P7.4/ACMP2_N is selected as the negative comparator input #0 1 The internal band-gap voltage (VBG) is selected as the negative comparator input #1 ACMPSR ACMPSR Analog Comparator Status Register 0xC read-write n 0x0 0x0 ACMPF0 Compare 0 Flag\nThis bit is set by hardware whenever the comparator 0 output changes state. This will cause an interrupt if ACMP0CR[1] is set to 1.\nWrite 1 to clear this bit to 0. 0 1 read-write ACMPF1 Compare 1 Flag\nThis bit is set by hardware whenever the comparator 1 output changes state. This will cause an interrupt if ACMP1CR[1] is set to 1.\nWrite 1 to clear this bit to 0. 1 1 read-write ACMPF2 Compare 2 Flag\nThis bit is set by hardware whenever the comparator 2 output changes state. This will cause an interrupt if ACMP2CR[1] is set to 1.\nWrite 1 to clear this bit to 0. 2 1 read-write CO0 Compare 0 Output\n 8 1 read-write CO1 Compare 1 Output\n 9 1 read-write CO2 Compare 2 Output\n 10 1 read-write OPDF0 OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag\nOPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state. \nNote: This bit is remapping from OPASR[4] and writing 1 to ACMPSR[4] or OPASR[4] can clear this bit. 4 1 read-write OPDF1 OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag\nOPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state. \nNote: This bit is remapping from OPASR[5] and writing 1 to ACMPSR[5] or OPASR[5] can clear this bit. 5 1 read-write BPWM0 BPWM0 Register Map BPWM0 0x0 0x0 0x24 registers n 0x40 0x8 registers n 0x50 0x4 registers n 0x58 0x10 registers n 0x78 0x8 registers n CAPENR CAPENR BPWM0 Capture Input Enable Register 0x78 read-write n 0x0 0x0 CINEN0 Channel 0 Capture Input Enable Bit\n 0 1 read-write 0 BPWM0_CH0 capture input path Disabled. The input of BPWM0_CH0 capture function is always regarded as 0 #0 1 BPWM0_CH0 capture input path Enabled. The input of BPWM0_CH0 capture function comes from correlative multifunction pin if GPIO multi-function is set as BPWM0_CH0 #1 CINEN1 Channel 1 Capture Input Enable Bit\n 1 1 read-write 0 BPWM0_CH1 capture input path Disabled. The input of BPWM0_CH1 capture function is always regarded as 0 #0 1 BPWM0_CH1 capture input path Enabled. The input of BPWM0_CH1 capture function comes from correlative multifunction pin if GPIO multi-function is set as BPWM0_CH1 #1 CCR CCR BPWM0 Capture Control Register 0x50 read-write n 0x0 0x0 CAPCH0EN Channel 0 Capture Function Enable Bit\nWhen enabled, capture latched the BPWM0-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen disabled, capture does not update CRLR and CFLR, and disable BPWM0 channel 0 Interrupt. 3 1 read-write 0 Capture function on BPWM0_CH0 Disabled #0 1 Capture function on BPWM0_CH0 Enabled #1 CAPCH1EN Channel 1 Capture Function Enable Bit\nWhen Enabled, Capture latched the BPWM0-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen disabled, capture does not update CRLR and CFLR, and disable BPWM0_CH1 interrupt. 19 1 read-write 0 Capture function on BPWM0_CH1 Disabled #0 1 Capture function on BPWM0_CH1 Enabled #1 CAPIF0 Channel 0 Capture Interrupt Indication Flag\nNote: This bit can be cleared by writing '1' to it. 4 1 read-write CAPIF1 Channel 1 Capture Interrupt Indication Flag\nNote: This bit can be cleared by writing '1' to it. 20 1 read-write CFLRI0 CFLR0 Latched Indicator Bit\nWhen BPWM0 input channel 0 has a falling transition, CFLR0 was latched with the value of BPWM0 down-counter and this bit is set by hardware.\nNote: This bit can be cleared by writing '1' to it. 7 1 read-write CFLRI1 CFLR1 Latched Indicator Bit\nWhen BPWM0 input channel 1 has a falling transition, CFLR1 was latched with the value of BPWM0 down-counter and this bit is set by hardware.\nNote: This bit can be cleared by writing '1' to it. 23 1 read-write CFL_IE0 Channel 0 Falling Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects BPWM0 channel 0 has falling transition, Capture will issue an Interrupt. 2 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CFL_IE1 Channel 1 Falling Latch Interrupt Enable Bit\nWhen enabled, if capture detects BPWM0_CH1 has falling transition, capture will issue an interrupt. 18 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CRLRI0 CRLR0 Latched Indicator Bit\nWhen BPWM0 input channel 0 has a rising transition, CRLR0 was latched with the value of BPWM0 down-counter and this bit is set by hardware.\nNote: This bit can be cleared by writing '1' to it. 6 1 read-write CRLRI1 CRLR1 Latched Indicator Bit\nWhen BPWM0 input channel 1 has a rising transition, CRLR1 was latched with the value of BPWM0 down-counter and this bit is set by hardware.\nNote: This bit can be cleared by writing '1' to it. 22 1 read-write CRL_IE0 Channel 0 Rising Latch Interrupt Enable Bit\nWhen Enabled, if capture detects BPWM0 channel 0 has rising transition, capture will issue an interrupt. 1 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 CRL_IE1 Channel 1 Rising Latch Interrupt Enable Bit\nWhen enabled, if capture detects BPWM0_CH1 has rising transition, capture will issue an interrupt. 17 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 INV0 Channel 0 Inverter Enable Bit\n 0 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled. Reverse the input signal from GPIO before fed to capture timer #1 INV1 Channel 1 Inverter Enable Bit\n 16 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled. Reverse the input signal from GPIO before fed to capture timer #1 CFLR0 CFLR0 BPWM0 Capture Falling Latch Register (Channel 0) 0x5C read-only n 0x0 0x0 CFLR Capture Falling Latch Register\nLatch the BPWM0 counter when Channel 0/1 has Falling transition. 0 16 read-only CFLR1 CFLR1 BPWM0 Capture Falling Latch Register (Channel 1) 0x64 read-write n 0x0 0x0 CMR0 CMR0 BPWM0 Comparator Register 0 0x10 read-write n 0x0 0x0 CMR BPWM Comparator Register\nCMR determines the BPWM duty.\nNote: Any write to CMR will take effect in next BPWM cycle. 0 16 read-write CMR1 CMR1 BPWM0 Comparator Register 1 0x1C read-write n 0x0 0x0 CNR0 CNR0 BPWM0 Counter Register 0 0xC read-write n 0x0 0x0 CNR BPWM Timer Loaded Value\nCNR determines the BPWM period.\nNote: Any write to CNR will take effect in next BPWM cycle.\nNote: When BPWM operating at Center-aligned type, CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF, the BPWM will work unpredictable.\nNote: When CNR value is set to 0, BPWM output is always high. 0 16 read-write CNR1 CNR1 BPWM0 Counter Register 1 0x18 read-write n 0x0 0x0 CRLR0 CRLR0 BPWM0 Capture Rising Latch Register (Channel 0) 0x58 read-only n 0x0 0x0 CRLR Capture Rising Latch Register\nLatch the BPWM0 counter when Channel 0/1 has rising transition. 0 16 read-only CRLR1 CRLR1 BPWM0 Capture Rising Latch Register (Channel 1) 0x60 read-write n 0x0 0x0 CSR CSR BPWM0 Clock Source Divider Select Register 0x4 read-write n 0x0 0x0 CSR0 BPWM Timer 0 Clock Source Divider Selection\nSelect clock source divider for BPWM timer 0, please refer to CSR1 0 3 read-write CSR1 BPWM Timer 1 Clock Source Divider Selection\nSelect clock source divider for BPWM timer 1.\n 4 3 read-write 0 Input clock divided by 2 #000 1 Input clock divided by 4 #001 2 Input clock divided by 8 #010 3 Input clock divided by 16 #011 4 Input clock divided by 1 #100 PCR PCR BPWM0 Control Register 0x8 read-write n 0x0 0x0 CH0EN BPWM-timer 0 Enable Bit\n 0 1 read-write 0 The corresponding BPWM-Timer stops running #0 1 The corresponding BPWM-Timer starts running #1 CH0INV BPWM-timer 0 Output Inverter Enable Bit\n 2 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 CH0MOD BPWM-timer 0 Auto-reload/One-shot Mode\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared. 3 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CH0PINV BPWM-timer 0 Output Polar Inverse Enable Bit\n 1 1 read-write 0 BPWM0_CH0 output polar inverse Disabled #0 1 BPWM0_CH0 output polar inverse Enabled #1 CH1EN BPWM-timer 1 Enable Bit\n 8 1 read-write 0 Corresponding BPWM-Timer Stopped #0 1 Corresponding BPWM-Timer Start Running #1 CH1INV BPWM-timer 1 Output Inverter Enable Bit\n 10 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 CH1MOD BPWM-timer 1 Auto-reload/One-shot Mode\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared. 11 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CH1PINV BPWM-timer 1 Output Polar Inverse Enable Bit\n 9 1 read-write 0 BPWM0_CH1 output polar inverse Disabled #0 1 BPWM0_CH1 output polar inverse Enabled #1 DZEN01 Dead-zone 0 Generator Enable Bit\nNote: When Dead-zone generator is enabled, the pair of BPWM0_CH0 and BPWM0_CH1 becomes a complementary pair. 4 1 read-write 0 Dead-zone 0 generator Disabled #0 1 Dead-zone 0 generator Enabled #1 PWM01TYPE BPWM0_CH0/1 Aligned Type Selection Bit \n 30 1 read-write 0 Edge-aligned type #0 1 Center-aligned type #1 PDR0 PDR0 BPWM0 Data Register 0 0x14 read-only n 0x0 0x0 PDR BPWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter. 0 16 read-only PDR1 PDR1 BPWM0 Data Register 1 0x20 read-write n 0x0 0x0 PIER PIER BPWM0 Interrupt Enable Register 0x40 read-write n 0x0 0x0 BPWMDIE0 BPWM Channel 0 Duty Interrupt Enable Bit\n 8 1 read-write 0 BPWM0_CH0 duty interrupt Disabled #0 1 BPWM0_CH0 duty interrupt Enabled #1 BPWMDIE1 BPWM Channel 1 Duty Interrupt Enable Bit\n 9 1 read-write 0 BPWM0_CH1 duty interrupt Disabled #0 1 BPWM0_CH1 duty interrupt Enabled #1 BPWMPIE0 BPWM Channel 0 Period Interrupt Enable Bit\n 0 1 read-write 0 BPWM0_CH0 period interrupt Disabled #0 1 BPWM0_CH0 period interrupt Enabled #1 BPWMPIE1 BPWM Channel 1 Period Interrupt Enable Bit\n 1 1 read-write 0 BPWM0_CH1 period interrupt Disabled #0 1 BPWM0_CH1 period interrupt Enabled #1 INTTYPE BPWM Interrupt Period Type Selection Bit\nNote: This bit is effective when BPWM in Center-aligned type only. 16 1 read-write 0 BPWMIFn will be set if BPWM counter underflow #0 1 BPWMIFn will be set if BPWM counter matches CNRn register #1 PIIR PIIR BPWM0 Interrupt Indication Register 0x44 read-write n 0x0 0x0 BPWMDIF0 BPWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when BPWM0_CH0 counter down count and reaches CMR0, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection 8 1 read-write BPWMDIF1 BPWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when BPWM0_CH1 counter down count and reaches CMR1, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection 9 1 read-write BPWMIF0 BPWM Channel 0 Period Interrupt Flag\nThis bit is set by hardware when BPWM0_CH0 counter reaches the requirement of interrupt (depend on INTTYPE bit of PIER register). \nNote: This bit can be cleared by writing '1' to it. 0 1 read-write BPWMIF1 BPWM Channel 1 Period Interrupt Flag\nThis bit is set by hardware when BPWM0_CH1 counter reaches the requirement of interrupt (depend on INTTYPE bit of PIER register).\nNote: This bit can be cleared by writing '1' to it. 1 1 read-write POE POE BPWM0 Output Enable 0x7C read-write n 0x0 0x0 POE0 Channel 0 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to BPWM0 function 0 1 read-write 0 BPWM0_CH0 output to pin Disabled #0 1 BPWM0_CH0 output to pin Enabled #1 POE1 Channel 1 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to BPWM0 function 1 1 read-write 0 BPWM0_CH1 output to pin Disabled #0 1 BPWM0_CH1 output to pin Enabled #1 PPR PPR BPWM0 Prescaler Register 0x0 read-write n 0x0 0x0 CP01 Clock Prescaler\nClock input is divided by (CP01 + 1) before it is fed to the corresponding BPWM-timer\n 0 8 read-write DZI01 Dead-zone Interval for Pair of Channel 0 and Channel 1\nThese 8-bit determine the Dead-zone length.\n 16 8 read-write CLK CLK Register Map CLK 0x0 0x0 0x28 registers n AHBCLK AHBCLK AHB Devices Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 HDIV_EN Hardware Divider Controller Clock Enable Bit\n 4 1 read-write 0 Hardware Divider engine clock Disabled #0 1 Hardware Divider engine clock Enabled #1 APBCLK APBCLK APB Devices Clock Enable Control Register 0x8 -1 read-write n 0x0 0x0 ACMP_EN Analog Comparator Clock Enable Bit\n 22 1 read-write 0 Analog comparator clock Disabled #0 1 Analog comparator clock Enabled #1 BPWM0_EN Basic PWM0 Clock Enable Bit\n 19 1 read-write 0 Basic PWM0 clock Disabled #0 1 Basic PWM0 clock Enabled #1 EADC_EN EADC Clock Enable Bit\n 28 1 read-write 0 EADC clock Disabled #0 1 EADC clock Enabled #1 ECAP0_EN Enhanced Input Capture 0 Clock Enable Bit\n 26 1 read-write 0 Enhanced input capture 0 clock Disabled #0 1 Enhanced input capture 0 clock Enabled #1 ECAP1_EN Enhanced Input Capture 1 Clock Enable Bit\n 27 1 read-write 0 Enhanced input capture 1 clock Disabled #0 1 Enhanced input capture 1 clock Enabled #1 EPWM0_EN Enhanced PWM0 Clock Enable Bit\n 20 1 read-write 0 Enhanced PWM0 clock Disabled #0 1 Enhanced PWM0 clock Enabled #1 EPWM1_EN Enhanced PWM1 Clock Enable Bit\n 21 1 read-write 0 Enhanced PWM1 clock Disabled #0 1 Enhanced PWM1 clock Enabled #1 FDIV_EN Frequency Divider Output Clock Enable Bit\n 6 1 read-write 0 Frequency divider output clock Disabled #0 1 Frequency divider output clock Enabled #1 I2C0_EN I2C0 Clock Enable Bit\n 8 1 read-write 0 I2C0 clock Disabled #0 1 I2C0 clock Enabled #1 OPA_EN OPA0 and OPA1 Clock Enable Bit\n 29 1 read-write 0 OPA0 and OPA1 clock Disabled #0 1 OPA0 and OPA1 clock Enabled #1 SPI0_EN SPI0 Clock Enable Bit\n 12 1 read-write 0 SPI0 clock Disabled #0 1 SPI0 clock Enabled #1 SPI1_EN SPI1 Clock Enable Bit\n 13 1 read-write 0 SPI1 clock Disabled #0 1 SPI1 clock Enabled #1 SPI2_EN SPI2 Clock Enable Bit\n 14 1 read-write 0 SPI2 clock Disabled #0 1 SPI2 clock Enabled #1 TMR0_EN Timer0 Clock Enable Bit\n 2 1 read-write 0 Timer0 clock Disabled #0 1 Timer0 clock Enabled #1 TMR1_EN Timer1 Clock Enable Bit\n 3 1 read-write 0 Timer1 clock Disabled #0 1 Timer1 clock Enabled #1 TMR2_EN Timer2 Clock Enable Bit\n 4 1 read-write 0 Timer2 clock Disabled #0 1 Timer2 clock Enabled #1 TMR3_EN Timer3 Clock Enable Bit\n 5 1 read-write 0 Timer3 clock Disabled #0 1 Timer3 clock Enabled #1 UART0_EN UART0 Clock Enable Bit\n 16 1 read-write 0 UART0 clock Disabled #0 1 UART0 clock Enabled #1 UART1_EN UART1 Clock Enable Bit\n 17 1 read-write 0 UART1 clock Disabled #0 1 UART1 clock Enabled #1 WDT_EN Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected bit. Refer to the REGWRPROT register. 0 1 read-write 0 Watchdog Timer clock Disabled #0 1 Watchdog Timer clock Enabled #1 CLKDIV CLKDIV Clock Divider Number Register 0x18 read-write n 0x0 0x0 EADC_N EADC Clock Divider\n 16 8 read-write HCLK_N HCLK Clock Divider\n 0 4 read-write UART_N UART Clock Divider\n 8 4 read-write CLKSEL0 CLKSEL0 Clock Source Select Control Register 0 0x10 -1 read-write n 0x0 0x0 HCLK_S HCLK Clock Source Selection (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turn on.\nThe 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nNote: These bits are write protected bits. Refer to the REGWRPROT register. 0 3 read-write 0 Clock source from external 4~24 MHz crystal clock #000 1 Reserved #001 2 Clock source from PLL clock #010 3 Clock source from internal 10 kHz oscillator clock #011 7 Clock source from internal 22.1184 MHz oscillator clock #111 STCLK_S Cortex-M0 SysTick Clock Source Selection (Write Protect)\n 3 3 read-write 0 Clock source from external 4~24 MHz crystal clock #000 1 Reserved #001 2 Clock source from external 4~24 MHz crystal clock/2 #010 3 Clock source from HCLK/2 #011 7 Clock source from internal 22.1184 MHz oscillator clock/2 #111 CLKSEL1 CLKSEL1 Clock Source Select Control Register 1 0x14 -1 read-write n 0x0 0x0 SPI0_S SPI0 Clock Source Selection\n 4 1 read-write 0 Clock source from PLL clock #0 1 Clock source from HCLK #1 SPI1_S SPI1 Clock Source Selection\n 5 1 read-write 0 Clock source from PLL clock #0 1 Clock source from HCLK #1 SPI2_S SPI2 Clock Source Selection\n 6 1 read-write 0 Clock source from PLL clock #0 1 Clock source from HCLK #1 UART_S UART Clock Source Selection\n 24 2 read-write 0 Clock source from external 4~24 MHz crystal clock #00 1 Clock source from PLL clock #01 2 Reserved #10 3 Clock source from internal 22.1184 MHz oscillator clock #11 WDT_S Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected bits. Refer to the REGWRPROT register. 0 2 read-write 0 Clock source from HCLK/128 clock #00 1 Clock source from HCLK/512 clock #01 2 Clock source from HCLK/2048 clock #10 3 Clock source from internal 10 kHz oscillator clock #11 CLKSEL2 CLKSEL2 Clock Source Select Control Register 2 0x1C -1 read-write n 0x0 0x0 FRQDIV_S Clock Divider Clock Source Selection\n 2 2 read-write 0 Clock source from external 4~24 MHz crystal clock #00 1 Reserved #01 2 Clock source from HCLK #10 3 Clock source from internal 22.1184 MHz oscillator clock #11 WWDT_S Window Watchdog Timer Clock Source Selection\n 16 2 read-write 0 Reserved #00 1 Reserved #01 2 Clock source from HCLK/2048 clock #10 3 Clock source from internal 10 kHz low speed oscillator clock #11 CLKSTATUS CLKSTATUS Clock Status Monitor Register 0xC read-only n 0x0 0x0 CLK_SW_FAIL Clock Switching Fail Flag (Read Only)\nThis bit is an index that if current system clock source is match as user defined at HCLK_S (CLKSEL0[2:0]). When user switch system clock, the system clock source will keep old clock until the new clock is stable. During the period that waiting new clock stable, this bit will be an index shows system clock source is not match as user wanted. 7 1 read-only 0 Clock switching success #0 1 Clock switching failure #1 OSC10K_STB Internal 10k Hz Clock Source Stable Flag (Read Only)\n 3 1 read-only 0 Internal 10k Hz oscillator clock is not stable or disabled #0 1 Internal 10k Hz oscillator clock is stable and enabled #1 OSC22M_STB Internal 22.1184M Hz Oscillator Clock Source Stable Flag (Read Only)\n 4 1 read-only 0 Internal 22.1184M Hz oscillator clock is not stable or disabled #0 1 Internal 22.1184M Hz oscillator clock is stable and enabled #1 PLL_STB PLL Clock Source Stable Flag (Read Only)\n 2 1 read-only 0 PLL clock is not stable or disabled #0 1 PLL clock is stable in normal mode #1 XTL12M_STB External 4~24 MHz Crystal Clock Source Stable Flag (Read Only)\n 0 1 read-only 0 External 4~24 MHz crystal clock is not stable or disabled #0 1 External 4~24 MHz crystal clock is stable and enabled #1 FRQDIV FRQDIV Frequency Divider Control Register 0x24 read-write n 0x0 0x0 DIV1 Frequency Divider Divide 1 Enable Bit\n 5 1 read-write 0 Frequency divider will output clock with source frequency divide by FSEL #0 1 Frequency divider will output clock with source frequency #1 DIVIDER_EN Frequency Divider Enable Bit\n 4 1 read-write 0 Frequency divider Disabled #0 1 Frequency divider Enabled #1 FSEL Frequency Divider Output Selection Bits\nThe output formula is:\nwhere FFRQDIV_CLK is the input clock frequency, FCLKO is the clock divider output frequency and N is the 4-bit value in FSEL[3:0]. 0 4 read-write PLLCON PLLCON PLL Control Register 0x20 -1 read-write n 0x0 0x0 BP PLL Bypass Control\n 17 1 read-write 0 PLL is in normal mode (default) #0 1 PLL clock output is same as clock input #1 FB_DV PLL Feedback Divider Control Bits\nRefer to the formulas below the table. 0 9 read-write FCO_SEL PLL FCO Selection\n 20 1 read-write 0 When the FCO frequency range between 100MHz and 200MHz, this bit should be set as 0 #0 1 When the FCO frequency range between 200MHz to 500MHz, this bit should be set as 1 #1 IN_DV PLL Input Divider Control Bits\nRefer to the formulas below the table. 9 5 read-write OE PLL OE (FOUT Enable) Bit\n 18 1 read-write 0 PLL FOUT enable #0 1 PLL FOUT is fixed low #1 OUT_DV PLL Output Divider Control Bits\nRefer to the formulas below the table. 14 2 read-write PD Power-down Mode\n 16 1 read-write 0 PLL is in normal mode #0 1 PLL is in power-down mode (default) #1 PLL_SRC PLL Source Clock Selection\n 19 1 read-write 0 PLL source clock from external 4~24 MHz crystal #0 1 PLL source clock from internal 22.1184 MHz oscillator #1 PWRCON PWRCON System Power-down Control Register 0x0 read-write n 0x0 0x0 OSC10K_EN Internal 10 kHz Oscillator Enable Bit (Write Protect)\nNote: This bit is write protected bit. Refer to the REGWRPROT register. 3 1 read-write 0 10 kHz Oscillation Disabled #0 1 10 kHz Oscillation Enabled #1 OSC22M_EN Internal 22.1184 MHz Oscillator Enable Bit (Write Protect)\nNote: This bit is write protected bit. Refer to the REGWRPROT register. 2 1 read-write 0 22.1184 MHz Oscillation Disabled #0 1 22.1184 MHz Oscillation Enabled #1 PD_WU_INT_EN Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.\nNote2: This bit is write protected bit. Refer to the REGWRPROT register. 5 1 read-write 0 Power-down mode wake-up interrupt Disabled #0 1 Power-down mode wake-up interrupt Enabled #1 PD_WU_STS Power-down Mode Wake-up Interrupt Status Set by power down wake up event , it indicates that resume from Power-down mode. Write 1 to clear the bit to zero. Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1. 6 1 read-write XTL12M_EN External 4~24 MHz Crystal Enable Bit (Write Protect)\nThe bit default value is set by flash controller user configuration register CFOSC (Config0[26:24]). When the default clock source is from external 4~24 MHz crystal, this bit is set to 1 automatically.\nNote: This bit is write protected bit. Refer to the REGWRPROT register. 0 1 read-write 0 External 4~24 MHz crystal Disabled #0 1 External 4~24 MHz crystal Enabled #1 EADC EADC Register Map EADC 0x0 0x0 0x98 registers n 0x100 0x10 registers n 0x120 0x44 registers n 0xA4 0x18 registers n ADCHISELR ADCHISELR A/D Channel Input Sources Select Register 0x44 read-write n 0x0 0x0 AINA0SEL A/D Channel AINA[0] Analog Input Selection \n 0 1 read-write 0 AINA[0] pin P6.0/EADC0_CH0is selected as the ADC AINA[0] input signal #0 1 OP Amplifier 0 output is selected as the ADC AINA[0] input signal #1 AINB0SEL A/D Channel AINB[0] Analog Input Selection\n 1 1 read-write 0 AINB[0] pin P7.0E/EADC1_CH0 is selected as the A/D AINB[0] input signal #0 1 OP Amplifier 1 output is selected as the A/D AINB[0] input signal #1 PRESEL A/D Channel AINA[7] Analog Input Selection\n 2 2 read-write 0 Analog Input Channel AINA7 #00 1 Band-gap (VBG) Analog Input #01 2 VTEMP Internal Temperature Sensor Analog Input #10 3 Analog ground #11 ADCMPR0 ADCMPR0 A/D Result Compare Register 0 0xA8 read-write n 0x0 0x0 ADCMPIE A/D Result Compare Interrupt Enable Bit\n 1 1 read-write 0 Compare function interrupt Disabled #0 1 Compare function interrupt Enabled #1 ADCMP_EN A/D Result Compare Enable Bit\n 0 1 read-write 0 Compare Disabled #0 1 Compare Enabled #1 CMPCOND Compare Condition\n 2 1 read-write 0 Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD(ADCMPRn[27:16], n=0, 1), the internal match counter will increase one #0 1 Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD(ADCMPRn[27:16] , n=0, 1), the internal match counter will increase one #1 CMPD Comparison Data\nThe 12 bits data is used to compare with the conversion result of specified SAMPLE. Software can use it to monitor the external analog input pin voltage transition without imposing a load on software. 16 12 read-write CMPMATCNT Compare Match Count\n 8 4 read-write CMPSMPL Compare SAMPLE Selection\n 3 3 read-write 0 SAMPLEA0 conversion result ADDRA0 is selected to be compared #000 1 SAMPLEA1 conversion result ADDRA1 is selected to be compared #001 2 SAMPLEA2 conversion result ADDRA2 is selected to be compared #010 3 SAMPLEA3 conversion result ADDRA3 is selected to be compared #011 4 SAMPLEB0 conversion result ADDRB0 is selected to be compared #100 5 SAMPLEB1 conversion result ADDRB1 is selected to be compared #101 6 SAMPLEB2 conversion result ADDRB2 is selected to be compared #110 7 SAMPLEB3 conversion result ADDRB3 is selected to be compared #111 ADCMPR1 ADCMPR1 A/D Result Compare Register 1 0xAC read-write n 0x0 0x0 ADCR ADCR A/D Control Register 0x40 read-write n 0x0 0x0 ADIE0 Specific SAMPLE A/D ADINT0 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADF0 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE0 bit is set then conversion end interrupt request ADINT0 is generated. 2 1 read-write 0 Specific SAMPLE A/D ADINT0 interrupt function Disabled #0 1 Specific SAMPLE A/D ADINT0 interrupt function Enabled #1 ADIE1 Specific SAMPLE A/D ADINT1 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADF1 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE1 bit is set then conversion end interrupt request ADINT1 is generated. 3 1 read-write 0 Specific SAMPLE A/D ADINT1 interrupt function Disabled #0 1 Specific SAMPLE A/D ADINT1 interrupt function Enabled #1 ADIE2 Specific SAMPLE A/D ADINT2 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADF2 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE2 bit is set then conversion end interrupt request ADINT2 is generated. 4 1 read-write 0 Specific SAMPLE A/D ADINT2 interrupt function Disabled #0 1 Specific SAMPLE A/D ADINT2 interrupt function Enabled #1 ADIE3 Specific SAMPLE A/D ADINT3 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADF3 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE3 bit is set then conversion end interrupt request ADINT3 is generated. 5 1 read-write 0 Specific SAMPLE A/D ADINT3 interrupt function Disabled #0 1 Specific SAMPLE A/D ADINT3 interrupt function Enabled #1 ADRESET ADCA, ADCB A/D Converter Control Circuits Reset\nNote: This bit remains 1 during ADC reset, when ADC reset end, the ADRESET bit is automatically cleared to 0. 1 1 read-write 0 Writing 0 has no effect #0 1 Writing 1 will cause ADC control circuits reset to initial state, but not change the ADC registers value #1 AD_EN A/D Converter Enable Bit\nNote: Before starting the A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption. 0 1 read-write 0 A/D converter Disabled #0 1 A/D converter Enabled #1 ADDBM ADDBM A/D Double Buffer Mode Select 0x130 read-write n 0x0 0x0 DBMA0 Double Buffer Mode for SAMPLE A0 \n 0 1 read-write 0 SampleA0 has one sample result register. (default) #0 1 SampleA0 has two sample result registers #1 DBMA1 Double Buffer Mode for SAMPLE A1 \n 1 1 read-write 0 SampleA1 has one sample result register. (default) #0 1 SampleA1 has two sample result registers #1 DBMA2 Double Buffer Mode for SAMPLE A2 \n 2 1 read-write 0 SampleA2 has one sample result register. (default) #0 1 SampleA2 has two sample result registers #1 DBMA3 Double Buffer Mode for SAMPLE A3 \n 3 1 read-write 0 SampleA3 has one sample result register. (default) #0 1 SampleA3 has two sample result registers #1 DBMB0 Double Buffer Mode for SAMPLE B0 \n 8 1 read-write 0 SampleB0 has one sample result register. (default) #0 1 SampleB0 has two sample result registers #1 DBMB1 Double Buffer Mode for SAMPLE B1 \n 9 1 read-write 0 SampleB1 has one sample result register. (default) #0 1 SampleB1 has two sample result registers #1 DBMB2 Double Buffer Mode for SAMPLE B2 \n 10 1 read-write 0 SampleB2 has one sample result register. (default) #0 1 SampleB2 has two sample result registers #1 DBMB3 Double Buffer Mode for SAMPLE B3 \n 11 1 read-write 0 SampleB3 has one sample result register. (default) #0 1 SampleB3 has two sample result registers #1 ADDRA0 ADDRA0 A/D Data Register 0 for SAMPLEA0 0x0 read-only n 0x0 0x0 OVERRUN over Run Flag\n 16 1 read-only 0 Data in RSLT[11:0] is the recent conversion result #0 1 Data in RSLT[11:0] is overwritten. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after ADDR register is read #1 RSLT A/D Conversion Result\nThis field contains 12-bit conversion result. 0 12 read-only VALID Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is read. 17 1 read-only 0 Data in RSLT[11:0] bits is not valid #0 1 Data in RSLT[11:0] bits is valid #1 ADDRA1 ADDRA1 A/D Data Register 1 for SAMPLEA1 0x4 read-write n 0x0 0x0 ADDRA2 ADDRA2 A/D Data Register 2 for SAMPLEA2 0x8 read-write n 0x0 0x0 ADDRA3 ADDRA3 A/D Data Register 3 for SAMPLEA3 0xC read-write n 0x0 0x0 ADDRA4 ADDRA4 A/D Data Register 4 for SAMPLEA4 0x10 read-write n 0x0 0x0 ADDRA5 ADDRA5 A/D Data Register 5 for SAMPLEA5 0x14 read-write n 0x0 0x0 ADDRA6 ADDRA6 A/D Data Register 6 for SAMPLEA6 0x18 read-write n 0x0 0x0 ADDRA7 ADDRA7 A/D Data Register 7 for SAMPLEA7 0x1C read-write n 0x0 0x0 ADDRB0 ADDRB0 A/D Data Register 8 for SAMPLEB0 0x20 read-write n 0x0 0x0 ADDRB1 ADDRB1 A/D Data Register 9 for SAMPLEB1 0x24 read-write n 0x0 0x0 ADDRB2 ADDRB2 A/D Data Register 10 for SAMPLEB2 0x28 read-write n 0x0 0x0 ADDRB3 ADDRB3 A/D Data Register 11 for SAMPLEB3 0x2C read-write n 0x0 0x0 ADDRB4 ADDRB4 A/D Data Register 12 for SAMPLEB4 0x30 read-write n 0x0 0x0 ADDRB5 ADDRB5 A/D Data Register 13 for SAMPLEB5 0x34 read-write n 0x0 0x0 ADDRB6 ADDRB6 A/D Data Register 14 for SAMPLEB6 0x38 read-write n 0x0 0x0 ADDRB7 ADDRB7 A/D Data Register 15 for SAMPLEB7 0x3C read-write n 0x0 0x0 ADDRDBA0 ADDRDBA0 A/D Data Register Double Buffer for SAMPLEA0 0x100 read-only n 0x0 0x0 RSLTDB A/D Conversion Result\n 0 12 read-only VALID Valid Flag\n 16 1 read-only 0 Double data in RSLTDB[11:0] bits is not valid #0 1 Double data in RSLTDB[11:0] bits is valid #1 ADDRDBA1 ADDRDBA1 A/D Data Register Double Buffer for SAMPLEA1 0x104 read-write n 0x0 0x0 ADDRDBA2 ADDRDBA2 A/D Data Register Double Buffer for SAMPLEA2 0x108 read-write n 0x0 0x0 ADDRDBA3 ADDRDBA3 A/D Data Register Double Buffer for SAMPLEA3 0x10C read-write n 0x0 0x0 ADDRDBB0 ADDRDBB0 A/D Data Register Double Buffer for SAMPLEB0 0x120 read-write n 0x0 0x0 ADDRDBB1 ADDRDBB1 A/D Data Register Double Buffer for SAMPLEB1 0x124 read-write n 0x0 0x0 ADDRDBB2 ADDRDBB2 A/D Data Register Double Buffer for SAMPLEB2 0x128 read-write n 0x0 0x0 ADDRDBB3 ADDRDBB3 A/D Data Register Double Buffer for SAMPLEB3 0x12C read-write n 0x0 0x0 ADIFOVR ADIFOVR A/D ADINT3~0 Interrupt Flag over Run Register 0x50 read-write n 0x0 0x0 ADFOV0 A/D ADINT0 Interrupt Flag over Run Bit Note: This bit is cleared by writing 1 to 1. 0 1 read-write 0 ADINT0 interrupt flag is not over run #0 1 ADINT0 interrupt flag is overwrite to 1 #1 ADFOV1 A/D ADINT1 Interrupt Flag over Run Bit Note: This bit is cleared by writing 1 to 1. 1 1 read-write 0 ADINT1 interrupt flag is not over run #0 1 ADINT1 interrupt flag is overwrite to 1 #1 ADFOV2 A/D ADINT2 Interrupt Flag over Run Bit Note: This bit is cleared by writing 1 to 1. 2 1 read-write 0 ADINT2 interrupt flag is not over run #0 1 ADINT2 interrupt flag is overwrite to 1 #1 ADFOV3 A/D ADINT3 Interrupt Flag over Run Bit Note: This bit is cleared by writing 1 to 1. 3 1 read-write 0 ADINT3 interrupt flag is not over run #0 1 ADINT3 interrupt pulse received when ADF3 is 1 #1 ADINT0SRCTL ADINT0SRCTL A/D Interrupt 0 Source Enable Control Register. 0x134 read-write n 0x0 0x0 IESPLA0 SAMPLE A0 Interrupt Mask Enable Bit\n 0 1 read-write 0 SAMPLE A0 interrupt mask Disabled #0 1 SAMPLE A0 interrupt mask Enabled #1 IESPLA1 SAMPLE A1 Interrupt Mask Enable Bit\n 1 1 read-write 0 SAMPLE A1 interrupt mask Disabled #0 1 SAMPLE A1 interrupt mask Enabled #1 IESPLA2 SAMPLE A2 Interrupt Mask Enable Bit\n 2 1 read-write 0 SAMPLE A2 interrupt mask Disabled #0 1 SAMPLE A2 interrupt mask Enabled #1 IESPLA3 SAMPLE A3 Interrupt Mask Enable Bit\n 3 1 read-write 0 SAMPLE A3 interrupt mask Disabled #0 1 SAMPLE A3 interrupt mask Enabled #1 IESPLA4 SAMPLE A4 Interrupt Mask Enable Bit\n 4 1 read-write 0 SAMPLE A4 interrupt mask Disabled #0 1 SAMPLE A4 interrupt mask Enabled #1 IESPLA5 SAMPLE A5 Interrupt Mask Enable Bit\n 5 1 read-write 0 SAMPLE A5 interrupt mask Disabled #0 1 SAMPLE A5 interrupt mask Enabled #1 IESPLA6 SAMPLE A6 Interrupt Mask Enable Bit\n 6 1 read-write 0 SAMPLE A6 interrupt mask Disabled #0 1 SAMPLE A6 interrupt mask Enabled #1 IESPLA7 SAMPLE A7 Interrupt Mask Enable Bit\n 7 1 read-write 0 SAMPLE A7 interrupt mask Disabled #0 1 SAMPLE A7 interrupt mask Enabled #1 IESPLB0 SAMPLE B0 Interrupt Mask Enable Bit\n 8 1 read-write 0 SAMPLE B0 interrupt mask Disabled #0 1 SAMPLE B0 interrupt mask Enabled #1 IESPLB1 SAMPLE B1 Interrupt Mask Enable Bit\n 9 1 read-write 0 SAMPLE B1 interrupt mask Disabled #0 1 SAMPLE B1 interrupt mask Enabled #1 IESPLB2 SAMPLE B2 Interrupt Mask Enable Bit\n 10 1 read-write 0 SAMPLE B2 interrupt mask Disabled #0 1 SAMPLE B2 interrupt mask Enabled #1 IESPLB3 SAMPLE B3 Interrupt Mask Enable Bit\n 11 1 read-write 0 SAMPLE B3 interrupt mask Disabled #0 1 SAMPLE B3 interrupt mask Enabled #1 IESPLB4 SAMPLE B4 Interrupt Mask Enable Bit\n 12 1 read-write 0 SAMPLE B4 interrupt mask Disabled #0 1 SAMPLE B4 interrupt mask Enabled #1 IESPLB5 SAMPLE B5 Interrupt Mask Enable Bit\n 13 1 read-write 0 SAMPLE B5 interrupt mask Disabled #0 1 SAMPLE B5 interrupt mask Enabled #1 IESPLB6 SAMPLE B6 Interrupt Mask Enable Bit\n 14 1 read-write 0 SAMPLE B6 interrupt mask Disabled #0 1 SAMPLE B6 interrupt mask Enabled #1 IESPLB7 SAMPLE B7 Interrupt Mask Enable Bit\n 15 1 read-write 0 SAMPLE B7 interrupt mask Disabled #0 1 SAMPLE B7 interrupt mask Enabled #1 ADINT1SRCTL ADINT1SRCTL A/D Interrupt 1 Source Enable Control Register. 0x138 read-write n 0x0 0x0 ADINT2SRCTL ADINT2SRCTL A/D Interrupt 2 Source Enable Control Register. 0x13C read-write n 0x0 0x0 ADINT3SRCTL ADINT3SRCTL A/D Interrupt 3 Source Enable Control Register. 0x140 read-write n 0x0 0x0 ADSMSELR ADSMSELR A/D SAMPLE Simultaneous Mode Select Register 0xA4 read-write n 0x0 0x0 SIMUSEL0 A/D SAMPLEA0, SAMPLEB0 Simultaneous Sampling Mode Selection \n 0 1 read-write 0 SAMPLEA0, SAMPLEB0 are in single sampling mode, both SAMPLEA0 and SAMPLEB0's 3 bits of CHSEL define the ADC channels to be converted #0 1 SAMPLEA0, SAMPLEB0 are in simultaneous sampling mode, Only SAMPLEA0 can trigger both the ADC conversions of SAMPLEA0 and SAMPLEB0, SAMPLEB0 trigger select TRGSEL is ignored. If SAMPLEA0's CHSEL = 1, and SAMPLEB0's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time #1 SIMUSEL1 A/D SAMPLEA1, SAMPLEB1 Simultaneous Sampling Mode Selection \n 1 1 read-write 0 SAMPLEA1, SAMPLEB1 are in single sampling mode, both SAMPLEA1 and SAMPLEB1's 3 bits of CHSEL define the ADC channels to be converted #0 1 SAMPLEA1, SAMPLEB1 are in simultaneous sampling mode, Only SAMPLEA1 can trigger both the ADC conversions of SAMPLEA1 and SAMPLEB1, SAMPLEB1 trigger select TRGSEL is ignored. If SAMPLEA1's CHSEL = 1, and SAMPLEB1's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time #1 SIMUSEL2 A/D SAMPLEA2, SAMPLEB2 Simultaneous Sampling Mode Selection \n 2 1 read-write 0 SAMPLEA2, SAMPLEB2 are in single sampling mode, both SAMPLEA2 and SAMPLEB2's 3 bits of CHSEL define the ADC channels to be converted #0 1 SAMPLEA2, SAMPLEB2 are in simultaneous sampling mode, Only SAMPLEA2 can trigger both the ADC conversions of SAMPLEA2 and SAMPLEB2, SAMPLEB2 trigger select TRGSEL is ignored. If SAMPLEA2's CHSEL = 1, and SAMPLEB2's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time #1 SIMUSEL3 A/D SAMPLEA3, SAMPLEB3 Simultaneous Sampling Mode Select Ion\n 3 1 read-write 0 SAMPLEA3, SAMPLEB3 are in single sampling mode, both SAMPLEA3 and SAMPLEB3's 3 bits of CHSEL define the ADC channels to be converted #0 1 SAMPLEA3, SAMPLEB3 are in simultaneous sampling mode, Only SAMPLEA3 can trigger both the ADC conversions of SAMPLEA3 and SAMPLEB3, SAMPLEB3 trigger select TRGSEL is ignored. If SAMPLEA3's CHSEL = 1, and SAMPLEB3's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time #1 SIMUSEL4 A/D SAMPLEA4, SAMPLEB4 Simultaneous Sampling Mode Select Ion\n 4 1 read-write 0 SAMPLEA4, SAMPLEB4 are in single sampling mode, both SAMPLEA4 and SAMPLEB4's 3 bits of CHSEL define the ADC channels to be converted #0 1 SAMPLEA4, SAMPLEB4 are in simultaneous sampling mode, Only SAMPLEA4 can trigger both the ADC conversions of SAMPLEA4 and SAMPLEB4, SAMPLEB4 trigger select TRGSEL is ignored. If SAMPLEA4's CHSEL = 1, and SAMPLEB4's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time #1 SIMUSEL5 A/D SAMPLEA5, SAMPLEB5 Simultaneous Sampling Mode Selection \n 5 1 read-write 0 SAMPLEA5, SAMPLEB5 are in single sampling mode, both SAMPLEA5 and SAMPLEB5's 3 bits of CHSEL define the ADC channels to be converted #0 1 SAMPLEA5, SAMPLEB5 are in simultaneous sampling mode, Only SAMPLEA5 can trigger both the ADC conversions of SAMPLEA5 and SAMPLEB5, SAMPLEB5 trigger select TRGSEL is ignored. If SAMPLEA5's CHSEL = 1, and SAMPLEB5's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time #1 SIMUSEL6 A/D SAMPLEA6, SAMPLEB6 Simultaneous Sampling Mode Selection \n 6 1 read-write 0 SAMPLEA6, SAMPLEB6 are in single sampling mode, both SAMPLEA6 and SAMPLEB6's 3 bits of CHSEL define the ADC channels to be converted #0 1 SAMPLEA6, SAMPLEB6 are in simultaneous sampling mode, Only SAMPLEA6 can trigger both the ADC conversions of SAMPLEA6 and SAMPLEB6, SAMPLEB6 trigger select TRGSEL is ignored. If SAMPLEA6's CHSEL = 1, and SAMPLEB6's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time #1 SIMUSEL7 A/D SAMPLEA7, SAMPLEB7 Simultaneous Sampling Mode Selection\n 7 1 read-write 0 SAMPLEA7, SAMPLEB7 are in single sampling mode, both SAMPLEA7 and SAMPLEB7's 3 bits of CHSEL define the ADC channels to be converted #0 1 SAMPLEA7, SAMPLEB7 are in simultaneous sampling mode, Only SAMPLEA7 can trigger both the ADC conversions of SAMPLEA7 and SAMPLEB7, SAMPLEB7 trigger select TRGSEL is ignored. If SAMPLEA7's CHSEL = 1, SAMPLEB7's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time #1 ADSPCRA0 ADSPCRA0 A/D SAMPLEA0 Control Register 0x58 read-write n 0x0 0x0 CHSEL A/D SAMPLEA,B Channel Selection\n 0 3 read-write 0 AINx[0] #000 1 AINx[1] #001 2 AINx[2] #010 3 AINx[3] #011 4 AINx[4] #100 5 AINx[5] #101 6 AINx[6] #110 7 AINx[7] #111 EXTFEN A/D External Trigger Falling Edge Enable Bit\n 21 1 read-write 0 Falling edge Disabled when A/D selects STADC as trigger source #0 1 Falling edge Enabled when A/D selects STADC as trigger source #1 EXTREN A/D External Trigger Rising Edge Enable Bit\n 20 1 read-write 0 Rising edge Disabled when A/D selects STADC as trigger source #0 1 Rising edge Enabled when A/D selects STADC as trigger source #1 TRGDLYCNT A/D SAMPLE Start Conversion Trigger Delay Time\n 8 8 read-write TRGDLYDIV A/D SAMPLE Start Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n 16 2 read-write 0 ADC_CLK/1 #00 1 ADC_CLK/2 #01 2 ADC_CLK/4 #10 3 ADC_CLK/16 #11 TRGSEL A/D SAMPLE Start Conversion Trigger Source Selection\n 4 4 read-write 0 Disable hardware trigger #0000 1 External trigger from STADC pin input #0001 2 ADC ADINT0 interrupt EOC pulse trigger #0010 3 ADC ADINT1 interrupt EOC pulse trigger #0011 4 Timer0 overflow pulse trigger #0100 5 Timer1 overflow pulse trigger #0101 6 Timer2 overflow pulse trigger #0110 7 Timer3 overflow pulse trigger #0111 8 PWM00 trigger #1000 9 PWM02 trigger #1001 10 PWM04 trigger #1010 11 PWM10 trigger #1011 12 PWM12 trigger #1100 13 PWM14 trigger #1101 14 PWM20 trigger #1110 15 PWM21 trigger #1111 ADSPCRA1 ADSPCRA1 A/D SAMPLEA1 Control Register 0x5C read-write n 0x0 0x0 ADSPCRA2 ADSPCRA2 A/D SAMPLEA2 Control Register 0x60 read-write n 0x0 0x0 ADSPCRA3 ADSPCRA3 A/D SAMPLEA3 Control Register 0x64 read-write n 0x0 0x0 ADSPCRA4 ADSPCRA4 A/D SAMPLEA4 Control Register 0x68 read-write n 0x0 0x0 CHSEL A/D SAMPLEA,B Channel Selection\n 0 3 read-write 0 AINx[0] #000 1 AINx[1] #001 2 AINx[2] #010 3 AINx[3] #011 4 AINx[4] #100 5 AINx[5] #101 6 AINx[6] #110 7 AINx[7] #111 EXTFEN A/D External Trigger Falling Edge Enable Bit\n 21 1 read-write 0 Falling edge Disabled when A/D selects STADC as trigger source #0 1 Falling edge Enabled when A/D selects STADC as trigger source #1 EXTREN A/D External Trigger Rising Edge Enable Bit\n 20 1 read-write 0 Rising edge Disabled when A/D selects STADC as trigger source #0 1 Rising edge Enabled when A/D selects STADC as trigger source #1 TRGSEL A/D SAMPLE Start Conversion Trigger Source Selection\n 4 3 read-write 0 Disable hardware trigger #000 1 External trigger from STADC pin input #001 2 ADC ADINT0 interrupt EOC pulse trigger #010 3 ADC ADINT1 interrupt EOC pulse trigger #011 4 Timer0 overflow pulse trigger #100 5 Timer1 overflow pulse trigger #101 6 Timer2 overflow pulse trigger #110 7 Timer3 overflow pulse trigger #111 ADSPCRA5 ADSPCRA5 A/D SAMPLEA5 Control Register 0x6C read-write n 0x0 0x0 ADSPCRA6 ADSPCRA6 A/D SAMPLEA6 Control Register 0x70 read-write n 0x0 0x0 ADSPCRA7 ADSPCRA7 A/D SAMPLEA7 Control Register 0x74 read-write n 0x0 0x0 ADSPCRB0 ADSPCRB0 A/D SAMPLEB0 Control Register 0x78 read-write n 0x0 0x0 ADSPCRB1 ADSPCRB1 A/D SAMPLEB1 Control Register 0x7C read-write n 0x0 0x0 ADSPCRB2 ADSPCRB2 A/D SAMPLEB2 Control Register 0x80 read-write n 0x0 0x0 ADSPCRB3 ADSPCRB3 A/D SAMPLEB3 Control Register 0x84 read-write n 0x0 0x0 ADSPCRB4 ADSPCRB4 A/D SAMPLEB4 Control Register 0x88 read-write n 0x0 0x0 ADSPCRB5 ADSPCRB5 A/D SAMPLEB5 Control Register 0x8C read-write n 0x0 0x0 ADSPCRB6 ADSPCRB6 A/D SAMPLEB6 Control Register 0x90 read-write n 0x0 0x0 ADSPCRB7 ADSPCRB7 A/D SAMPLEB7 Control Register 0x94 read-write n 0x0 0x0 ADSPOVFR ADSPOVFR A/D SAMPLE Start of Conversion over Run Flag Register 0x54 read-write n 0x0 0x0 SPOVF15_8 A/D SAMPLEB7~SAMPLEB0 Start Conversion Overrun Flag\n 8 8 read-write 0 No SAMPLE event overrun 0 1 Indicates new SAMPLEBn event is generated while an old one event is pending 1 SPOVF7_0 A/D SAMPLEA7~SAMPLEA0 Start Conversion Overrun Flag\n 0 8 read-write 0 No SAMPLE event overrun 0 1 Indicates new SAMPLEAn event is generated while an old one event is pending 1 ADSR0 ADSR0 A/D Status Register 0 0xB0 read-only n 0x0 0x0 OVERRUN26_16 ADDRA7~0 over Run Flag\n 16 8 read-only OVERRUN31_24 ADDRB7~0 over Run Flag\n 24 8 read-only VALID15_8 ADDRB7~0 Data Valid Flag\n 8 8 read-only VALID7_0 ADDRA7~0 Data Valid Flag\n 0 8 read-only ADSR1 ADSR1 A/D Status Register 1 0xB4 read-write n 0x0 0x0 AADFOV All A/D Interrupt Flag over Run Bits Check \n 24 1 read-write 0 None of ADINT interrupt flag ADFOVn is overwritten to 1 #0 1 Any one of ADINT interrupt flag ADFOVn is overwritten to 1 #1 ADCMPF0 ADC Compare 0 Flag\nWhen the specific SAMPLE A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by write 1.\n 6 1 read-write 0 Conversion result in ADDR does not meet ADCMPR0 register setting #0 1 Conversion result in ADDR meets ADCMPR0 register setting #1 ADCMPF1 ADC Compare 1 Flag\nWhen the specific SAMPLE A/D conversion result meets setting condition in ADCMPR1 register then this bit is set to 1. And it is cleared by write 1.\n 7 1 read-write 0 Conversion result in ADDR does not meet ADCMPR1 register setting #0 1 Conversion result in ADDR meets ADCMPR1 register setting #1 ADCMPO0 ADC Compare 0 Output Status Bit The 12 bits compare0 data CMPD(ADCMPR0[27:16]) is used to compare with conversion result of specified SAMPLE. Software can use it to monitor the external analog input pin voltage status. 4 1 read-write 0 Conversion result in ADDR is less than CMPD(ADCMPR0[27:16]) setting #0 1 Conversion result in ADDR is great than or equal CMPD(ADCMPR0[27:16]) setting #1 ADCMPO1 ADC Compare 1 Output Status Bit The 12 bits compare1 data CMPD(ADCMPR1[27:16]) is used to compare with conversion result of specified SAMPLE. Software can use it to monitor the external analog input pin voltage status. 5 1 read-write 0 Conversion result in ADDR less than CMPD(ADCMPR1[27:16]) setting #0 1 Conversion result in ADDR great than or equal CMPD(ADCMPR1[27:16]) setting #1 ADF0 A/D ADINT0 Interrupt Flag\nNote1: It is cleared by writing 1.\nNote2: This bit indicates whether an A/D conversion of specific SAMPLE has been completed. 0 1 read-write 0 No ADINT0 interrupt pulse received #0 1 ADINT0 interrupt pulse received #1 ADF1 A/D ADINT1 Interrupt Flag\nNote1: It is cleared by writing 1.\nNote2: This bit indicates whether an A/D conversion of specific SAMPLE has been completed. 1 1 read-write 0 no ADINT1 interrupt pulse received #0 1 ADINT1 interrupt pulse has been received #1 ADF2 A/D ADINT2 Interrupt Flag\nNote1: It is cleared by writing 1. \nNote2: This bit indicates whether an A/D conversion of specific SAMPLE has been completed. 2 1 read-write 0 No ADINT2 interrupt pulse received #0 1 ADINT2 interrupt pulse received #1 ADF3 A/D ADINT3 Interrupt Flag\nNote1: It is cleared by writing 1.\nNote2: This bit indicates whether an A/D conversion of specific SAMPLE has been completed 3 1 read-write 0 No ADINT3 interrupt pulse received #0 1 ADINT3 interrupt pulse received #1 AOVERRUN All SAMPLE A/D Result Data Register over Run Flags Check \n 27 1 read-write 0 None of SAMPLE data register over run flag OVERRUNn is set to 1 #0 1 Any one of SAMPLE data register over run flag OVERRUNn is set to 1 #1 ASPOVF All A/D SAMPLE Start Conversion over Run Flags Check\n 25 1 read-write 0 None of SAMPLE event over run flag SPOVFn is set to 1 #0 1 Any one of SAMPLE event over run flag SPOVFn is set to 1 #1 AVALID All SAMPLE A/D Result Data Register ADDR Data Valid Flag Check\n 26 1 read-write 0 None of SAMPLE data register valid flag VALIDn is set to 1 #0 1 Any one of SAMPLE data register valid flag VALIDn is set to 1 #1 BUSYA BUSY/IDLE (Read Only)\n 8 1 read-only 0 A/D converter A (ADCA) is in idle state #0 1 A/D converter A (ADCA) is busy at conversion #1 BUSYB BUSY/IDLE (Read Only)\n 16 1 read-only 0 A/D converter B (ADCB) is in idle state #0 1 A/D converter B (ADCB) is busy at conversion #1 CHANNELA Current Conversion Channel (Read Only)\n 12 3 read-only 0 AINA[0] #000 1 AINA[1] #001 2 AINA[2] #010 3 AINA[3] #011 4 AINA[4] #100 5 AINA[5] #101 6 AINA[6] #110 7 AINA[7] #111 CHANNELB Current Conversion Channel (Read Only)\n 20 3 read-only 0 AINB[0] #000 1 AINB[1] #001 2 AINB[2] #010 3 AINB[3] #011 4 AINB[4] #100 5 AINB[5] #101 6 AINB[6] #110 7 AINB[7] #111 ADSSTR ADSSTR A/D SAMPLE Software Start Register 0x48 write-only n 0x0 0x0 ADST15_8 A/D SAMPLEB7~0 Software Force to Start ADC Conversion Register \n 8 8 write-only 0 No effect 0 1 Cause an ADC conversion when the priority is given to SAMPLEB 1 ADST7_0 A/D SAMPLEA7~0 Software Force to Start ADC Conversion Register \n 0 8 write-only 0 No effect 0 1 Cause an ADC conversion when the priority is given to SAMPLEA 1 ADSTPFR ADSTPFR A/D SAMPLE Start of Conversion Pending Flag Register 0x4C read-only n 0x0 0x0 STPF15_8 A/D SAMPLEB7~0 Start Conversion Pending Flag \n 8 8 read-only 0 No pending conversion for SAMPLEB 0 1 SAMPLEBn ADC start of conversion is pending 1 STPF7_0 A/D SAMPLEA7~0 Start Conversion Pending Flag \n 0 8 read-only 0 There is no pending conversion for SAMPLEA 0 1 SAMPLEAn ADC start of conversion is pending 1 ADTCR ADTCR A/D Timing Control Register 0xB8 read-write n 0x0 0x0 ADAEST ADCA Extend Sampling Time \nWhen A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, User can extend A/D sampling time after trigger source is coming to get enough sampling time.\nThe range of start delay time is from 0~255 ADC clock. 0 8 read-write ADBEST ADCB Extend Sampling Time \nWhen A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, User can extend A/D sampling time after trigger source is coming to get enough sampling time.\nThe range of start delay time is from 0~255 ADC clock. 16 8 read-write SMPTRGA0 SMPTRGA0 A/D Trigger Condition for SAMPLEA0 0x144 read-write n 0x0 0x0 PWM00CEN PWM0_CH0 Center Trigger Enable Bit\n 3 1 read-write 0 PWM0_CH0 center trigger Disabled #0 1 PWM0_CH0 center trigger Enabled #1 PWM00FEN PWM0_CH0 Falling Edge Trigger Enable Bit\n 1 1 read-write 0 PWM0_CH0 falling edge trigger Disabled #0 1 PWM0_CH0 falling edge trigger Enabled #1 PWM00PEN PWM0_CH0 Period Trigger Enable Bit\n 2 1 read-write 0 PWM0_CH0 period trigger Disabled #0 1 PWM0_CH0 period trigger Enabled #1 PWM00REN PWM0_CH0 Rising Edge Trigger Enable Bit\n 0 1 read-write 0 PWM0_CH0 rising edge trigger Disabled #0 1 PWM0_CH0 rising edge trigger Enabled #1 PWM02CEN PWM0_CH2 Center Trigger Enable Bit\n 7 1 read-write 0 PWM0_CH2 center trigger Disabled #0 1 PWM0_CH2 center trigger Enabled #1 PWM02FEN PWM0_CH2 Falling Edge Trigger Enable Bit\n 5 1 read-write 0 PWM0_CH2 falling edge trigger Disabled #0 1 PWM0_CH2 falling edge trigger Enabled #1 PWM02PEN PWM0_CH2 Period Trigger Enable Bit\n 6 1 read-write 0 PWM0_CH2 period trigger Disabled #0 1 PWM0_CH2 period trigger Enabled #1 PWM02REN PWM0_CH2 Rising Edge Trigger Enable Bit\n 4 1 read-write 0 PWM0_CH2 rising edge trigger Disabled #0 1 PWM0_CH2 rising edge trigger Enabled #1 PWM04CEN PWM0_CH4 Center Trigger Enable Bit\n 11 1 read-write 0 PWM0_CH4 center trigger Disabled #0 1 PWM0_CH4 center trigger Enabled #1 PWM04FEN PWM0_CH4 Falling Rdge Trigger Enable Bit\n 9 1 read-write 0 PWM0_CH4 falling edge trigger Disabled #0 1 PWM0_CH4 falling edge trigger Enabled #1 PWM04PEN PWM0_CH4 Period Trigger Enable Bit\n 10 1 read-write 0 PWM0_CH4 period trigger Disabled #0 1 PWM0_CH4 period trigger Enabled #1 PWM04REN PWM0_CH4 Rising Edge Trigger Enable Bit\n 8 1 read-write 0 PWM0_CH4 rising edge trigger Disabled #0 1 PWM0_CH4 rising edge trigger Enabled #1 PWM10CEN PWM1_CH0 Center Trigger Enable Bit\n 15 1 read-write 0 PWM1_CH0 center trigger Disabled #0 1 PWM1_CH0 center trigger Enabled #1 PWM10FEN PWM1_CH0 Falling Edge Trigger Enable Bit\n 13 1 read-write 0 PWM1_CH0 falling edge trigger Disabled #0 1 PWM1_CH0 falling edge trigger Enabled #1 PWM10PEN PWM1_CH0 Period Trigger Enable Bit\n 14 1 read-write 0 PWM1_CH0 period trigger Disabled #0 1 PWM1_CH0 period trigger Enabled #1 PWM10REN PWM1_CH0 Rising Edge Trigger Enable Bit\n 12 1 read-write 0 PWM1_CH0 rising edge trigger Disabled #0 1 PWM1_CH0 rising edge trigger Enabled #1 PWM12CEN PWM1_CH2 Center Trigger Enable Bit\n 19 1 read-write 0 PWM1_CH2 center trigger Disabled #0 1 PWM1_CH2 center trigger Enabled #1 PWM12FEN PWM1_CH2 Falling Edge Trigger Enable Bit\n 17 1 read-write 0 PWM1_CH2 falling edge trigger Disabled #0 1 PWM1_CH2 falling edge trigger Enabled #1 PWM12PEN PWM1_CH2 Period Trigger Enable Bit\n 18 1 read-write 0 PWM1_CH2 period trigger Disabled #0 1 PWM1_CH2 period trigger Enabled #1 PWM12REN PWM1_CH2 Rising Edge Trigger Enable Bit\n 16 1 read-write 0 PWM1_CH2 rising edge trigger Disabled #0 1 PWM1_CH2 rising edge trigger Enabled #1 PWM14CEN PWM1_CH4 Center Trigger Enable Bit\n 23 1 read-write 0 PWM1_CH4 center trigger Disabled #0 1 PWM1_CH4 center trigger Enabled #1 PWM14FEN PWM1_CH4 Falling Edge Trigger Enable Bit\n 21 1 read-write 0 PWM1_CH4 falling edge trigger Disabled #0 1 PWM1_CH4 falling edge trigger Enabled #1 PWM14PEN PWM1_CH4 Period Trigger Enable Bit\n 22 1 read-write 0 PWM1_CH4 period trigger Disabled #0 1 PWM1_CH4 period trigger Enabled #1 PWM14REN PWM1_CH4 Rising Edge Trigger Enable Bit\n 20 1 read-write 0 PWM1_CH4 rising edge trigger Disabled #0 1 PWM1_CH4 rising edge trigger Enabled #1 PWM20CEN BPWM0_CH0 Center Trigger Enable Bit\n 27 1 read-write 0 BPWM0_CH0 center trigger Disabled #0 1 BPWM0_CH0 center trigger Enabled #1 PWM20FEN BPWM0_CH0 Falling Edge Trigger Enable Bit\n 25 1 read-write 0 BPWM0_CH0 falling edge trigger Disabled #0 1 BPWM0_CH0 falling edge trigger Enabled #1 PWM20PEN BPWM0_CH0 Period Trigger Enable Bit\n 26 1 read-write 0 BPWM0_CH0 period trigger Disabled #0 1 BPWM0_CH0 period trigger Enabled #1 PWM20REN BPWM0_CH0 Rising Edge Trigger Enable Bit\n 24 1 read-write 0 BPWM0_CH0 rising edge trigger Disabled #0 1 BPWM0_CH0 rising edge trigger Enabled #1 PWM21CEN BPWM0_CH1 Center Trigger Enable Bit\n 31 1 read-write 0 BPWM0_CH1 center trigger Disabled #0 1 BPWM0_CH1 center trigger Enabled #1 PWM21FEN BPWM0_CH1 Falling Edge Trigger Enable Bit\n 29 1 read-write 0 BPWM0_CH1 falling edge trigger Disabled #0 1 BPWM0_CH1 falling edge trigger Enabled #1 PWM21PEN BPWM0_CH1 Period Trigger Enable Bit\n 30 1 read-write 0 BPWM0_CH1 period trigger Disabled #0 1 BPWM0_CH1 period trigger Enabled #1 PWM21REN BPWM0_CH1 Rising Edge Trigger Enable Bit\n 28 1 read-write 0 BPWM0_CH1 rising edge trigger Disabled #0 1 BPWM0_CH1 rising edge trigger Enabled #1 SMPTRGA1 SMPTRGA1 A/D Trigger Condition for SAMPLEA1 0x148 read-write n 0x0 0x0 SMPTRGA2 SMPTRGA2 A/D Trigger Condition for SAMPLEA2 0x14C read-write n 0x0 0x0 SMPTRGA3 SMPTRGA3 A/D Trigger Condition for SAMPLEA3 0x150 read-write n 0x0 0x0 SMPTRGB0 SMPTRGB0 A/D Trigger Condition for SAMPLEB0 0x154 read-write n 0x0 0x0 SMPTRGB1 SMPTRGB1 A/D Trigger Condition for SAMPLEB1 0x158 read-write n 0x0 0x0 SMPTRGB2 SMPTRGB2 A/D Trigger Condition for SAMPLEB2 0x15C read-write n 0x0 0x0 SMPTRGB3 SMPTRGB3 A/D Trigger Condition for SAMPLEB3 0x160 read-write n 0x0 0x0 ECAP0 ECAP Register Map ECAP 0x0 0x0 0x20 registers n ECAP_CNT ECAP_CNT Input Capture Counter (24-bit Up Counter) 0x0 read-write n 0x0 0x0 VAL Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider output which the CAP_CLK is software optionally divided by 1,4,16 or 32. 0 24 read-write ECAP_CNTCMP ECAP_CNTCMP Input Capture Counter Compare Register 0x10 read-write n 0x0 0x0 VAL Input Capture Counter Compare Register\n 0 24 read-write ECAP_CTL0 ECAP_CTL0 Input Capture Control Register 0 0x14 read-write n 0x0 0x0 CAPEN Input Capture Timer/Counter Enable Bit\n 29 1 read-write 0 Input Capture function Disabled #0 1 Input Capture function Enabled #1 CAPEN0 Pin ECAPx_IC0 Input to Input Capture Unit Enable Bit\n 4 1 read-write 0 ECAPx_IC0 input to Input Capture Unit Disabled #0 1 ECAPx_IC0 input to Input Capture Unit Enabled #1 CAPEN1 Pin ECAPx_IC1 Input to Input Capture Unit Enable Bit\n 5 1 read-write 0 ECAPx_IC1 input to Input Capture Unit Disabled #0 1 ECAPx_IC1 input to Input Capture Unit Enabled #1 CAPEN2 Pin ECAPx_IC2 Input to Input Capture Unit Enable Bit\n 6 1 read-write 0 ECAPx_IC2 input to Input Capture Unit Disabled #0 1 ECAPx_IC2 input to Input Capture Unit Enabled #1 CAPIEN0 Input Capture Channel 0 Interrupt Enable Bit\n 16 1 read-write 0 The flag CAPF0 can trigger Input Capture interrupt Disabled #0 1 The flag CAPF0 can trigger Input Capture interrupt Enabled #1 CAPIEN1 Input Capture Channel 1 Interrupt Enable Bit\n 17 1 read-write 0 The flag CAPF1 can trigger Input Capture interrupt Disabled #0 1 The flag CAPF1 can trigger Input Capture interrupt Enabled #1 CAPIEN2 Input Capture Channel 2 Interrupt Enable Bit\n 18 1 read-write 0 The flag CAPF2 can trigger Input Capture interrupt Disabled #0 1 The flag CAPF2 can trigger Input Capture interrupt Enabled #1 CAPNF_DIS Input Capture Noise Filter Disable Bit\n 3 1 read-write 0 Noise filter of Input Capture Enabled #0 1 Noise filter of Input Capture Disabled #1 CAPSEL0 CAP0 Input Source Selection\n 8 2 read-write 0 CAP0 input is from pin ECAPx_IC0 #00 1 CAP0 input is from CO0 (ACMPSR[8]) #01 2 Reserved #10 3 CAP0 input is from OPDO0 (OPASR[0]) #11 CAPSEL1 CAP1 Input Source Selection\n 10 2 read-write 0 CAP1 input is from pin ECAPx_IC1 #00 1 CAP1 input is from CO1 (ACMPSR[9]) #01 2 Reserved #10 3 CAP1 input is from OPDO1 (OPASR[1]) #11 CAPSEL2 CAP2 Input Source Selection\n 12 2 read-write 0 CAP2 input is from pin RCAPx_IC2 #00 1 CAP2 input is from CO2 (ACMPSR[10]) #01 2 Reserved #10 3 CAP2 input is from signal ADCMPOx (ADC compare output x) #11 CMPCLR Input Capture Counter Cleared by Compare-match Control\n 25 1 read-write 0 Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Disabled #0 1 Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Enabled #1 CMPEN Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CMPF will be set. \n 28 1 read-write 0 The compare function Disabled #0 1 The compare function Enabled #1 CMPIEN CMPF Trigger Input Capture Interrupt Enable Bit\n 21 1 read-write 0 The flag CMPF can trigger Input Capture interrupt Disabled #0 1 The flag CMPF can trigger Input Capture interrupt Enabled #1 CNTEN Input Capture Counter Start\nSetting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK). \n 24 1 read-write 0 ECAP_CNT stop counting #0 1 ECAP_CNT starts up-counting #1 CPTCLR Input Capture Counter Cleared by Capture Events Control\nIf this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to zero when any one of capture events (CAPF0~3) occurs. \n 26 1 read-write 0 Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Disabled #0 1 Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Enabled #1 NFDIS Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock \n 0 2 read-write 0 CAP_CLK #00 1 CAP_CLK/2 #01 2 CAP_CLK/4 #10 3 CAP_CLK/16 #11 OVIEN OVF Trigger Input Capture Interrupt Enable Bit\n 20 1 read-write 0 The flag OVUNF can trigger Input Capture interrupt Disabled #0 1 The flag OVUNF can trigger Input Capture interrupt Enabled #1 RLDEN Reload Function Enable Bit \nSetting this bit to enable the reload function. If the reload control is enabled, an overflow event (OVF) or capture events (CAPFx) will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT.\n 27 1 read-write 0 The reload function Disabled #0 1 The reload function Enabled #1 ECAP_CTL1 ECAP_CTL1 Input Capture Control Register 1 0x18 read-write n 0x0 0x0 CLKSEL Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[1:0].\n 12 3 read-write 0 CAP_CLK/1 #000 1 CAP_CLK/4 #001 2 CAP_CLK/16 #010 3 CAP_CLK/32 #011 4 CAP_CLK/64 #100 5 CAP_CLK/96 #101 6 CAP_CLK/112 #110 7 CAP_CLK/128 #111 EDGESEL0 Channel 0 Captured Edge Selection\nInput capture can detect falling edge change only, rising edge change only or one of both edge change \n 0 2 read-write 0 Detect rising edge #00 1 Detect falling edge.\nDetect either rising or falling edge #01 EDGESEL1 Channel 1 Captured Edge Selection\nInput capture can detect falling edge change only, rising edge change only or one of both edge change \n 2 2 read-write 0 Detect rising edge #00 1 Detect falling edge.\nDetect either rising or falling edge #01 EDGESEL2 Channel 2 Captured Edge Selection\nInput capture can detect falling edge change or rising edge change only, or one of both edge changes. \n 4 2 read-write 0 Detect rising edge #00 1 Detect falling edge.\nDetect either rising or falling edge #01 RLDSEL ECAP_CNT Reload Trigger Source Selection\n 8 3 read-write 0 CAPF0 #000 1 CAPF1 #001 2 CAPF2 #010 4 OVF #100 SRCSEL Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source.\n 16 2 read-write 0 CAP_CLK (default) #00 1 CAP0 #01 2 CAP1 #10 3 CAP2 #11 ECAP_HOLD0 ECAP_HOLD0 Input Capture Counter Hold Register 0 0x4 read-write n 0x0 0x0 VAL Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register. Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from ECAPx_IC0 to ECAPx_IC2, respectively. 0 24 read-write ECAP_HOLD1 ECAP_HOLD1 Input Capture Counter Hold Register 1 0x8 read-write n 0x0 0x0 ECAP_HOLD2 ECAP_HOLD2 Input Capture Counter Hold Register 2 0xC read-write n 0x0 0x0 ECAP_STATUS ECAP_STATUS Input Capture Status Register 0x1C read-write n 0x0 0x0 CAPF0 Input Capture Channel 0 Captured Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPF0 to high. \nNote: This bit is only cleared by writing 1 to it. 0 1 read-write 0 No valid edge change is detected at CAP0 input #0 1 A valid edge change is detected at CAP0 input #1 CAPF1 Input Capture Channel 1 Captured Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPF1 to high. \nNote: This bit is only cleared by writing 1 to it. 1 1 read-write 0 No valid edge change is detected at CAP1 input #0 1 A valid edge change is detected at CAP1 input #1 CAPF2 Input Capture Channel 2 Captured Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPF2 to high. \nNote: This bit is only cleared by writing 1 to it. 2 1 read-write 0 No valid edge change is detected at CAP2 input #0 1 A valid edge change is detected at CAP2 input #1 CMPF Input Capture Compare-match Flag\nIf the input capture compare function is enabled, the flag is set by hardware while capture counter (ECAP_CNT) up counts and reach to the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it. 4 1 read-write 0 ECAP_CNT does not match with ECAP_CNTCMP value #0 1 ECAP_CNT counts to the same as ECAP_CNTCMP value #1 OVF Input Capture Counter Overflow Flag\nFlag is set by hardware when input capture up counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\nNote: This bit is only cleared by writing 1 to it. 5 1 read-write 0 No overflow occurs in ECAP_CNT #0 1 ECAP_CNT overflows #1 ECAP1 ECAP Register Map ECAP 0x0 0x0 0x20 registers n ECAP_CNT ECAP_CNT Input Capture Counter (24-bit Up Counter) 0x0 read-write n 0x0 0x0 VAL Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider output which the CAP_CLK is software optionally divided by 1,4,16 or 32. 0 24 read-write ECAP_CNTCMP ECAP_CNTCMP Input Capture Counter Compare Register 0x10 read-write n 0x0 0x0 VAL Input Capture Counter Compare Register\n 0 24 read-write ECAP_CTL0 ECAP_CTL0 Input Capture Control Register 0 0x14 read-write n 0x0 0x0 CAPEN Input Capture Timer/Counter Enable Bit\n 29 1 read-write 0 Input Capture function Disabled #0 1 Input Capture function Enabled #1 CAPEN0 Pin ECAPx_IC0 Input to Input Capture Unit Enable Bit\n 4 1 read-write 0 ECAPx_IC0 input to Input Capture Unit Disabled #0 1 ECAPx_IC0 input to Input Capture Unit Enabled #1 CAPEN1 Pin ECAPx_IC1 Input to Input Capture Unit Enable Bit\n 5 1 read-write 0 ECAPx_IC1 input to Input Capture Unit Disabled #0 1 ECAPx_IC1 input to Input Capture Unit Enabled #1 CAPEN2 Pin ECAPx_IC2 Input to Input Capture Unit Enable Bit\n 6 1 read-write 0 ECAPx_IC2 input to Input Capture Unit Disabled #0 1 ECAPx_IC2 input to Input Capture Unit Enabled #1 CAPIEN0 Input Capture Channel 0 Interrupt Enable Bit\n 16 1 read-write 0 The flag CAPF0 can trigger Input Capture interrupt Disabled #0 1 The flag CAPF0 can trigger Input Capture interrupt Enabled #1 CAPIEN1 Input Capture Channel 1 Interrupt Enable Bit\n 17 1 read-write 0 The flag CAPF1 can trigger Input Capture interrupt Disabled #0 1 The flag CAPF1 can trigger Input Capture interrupt Enabled #1 CAPIEN2 Input Capture Channel 2 Interrupt Enable Bit\n 18 1 read-write 0 The flag CAPF2 can trigger Input Capture interrupt Disabled #0 1 The flag CAPF2 can trigger Input Capture interrupt Enabled #1 CAPNF_DIS Input Capture Noise Filter Disable Bit\n 3 1 read-write 0 Noise filter of Input Capture Enabled #0 1 Noise filter of Input Capture Disabled #1 CAPSEL0 CAP0 Input Source Selection\n 8 2 read-write 0 CAP0 input is from pin ECAPx_IC0 #00 1 CAP0 input is from CO0 (ACMPSR[8]) #01 2 Reserved #10 3 CAP0 input is from OPDO0 (OPASR[0]) #11 CAPSEL1 CAP1 Input Source Selection\n 10 2 read-write 0 CAP1 input is from pin ECAPx_IC1 #00 1 CAP1 input is from CO1 (ACMPSR[9]) #01 2 Reserved #10 3 CAP1 input is from OPDO1 (OPASR[1]) #11 CAPSEL2 CAP2 Input Source Selection\n 12 2 read-write 0 CAP2 input is from pin RCAPx_IC2 #00 1 CAP2 input is from CO2 (ACMPSR[10]) #01 2 Reserved #10 3 CAP2 input is from signal ADCMPOx (ADC compare output x) #11 CMPCLR Input Capture Counter Cleared by Compare-match Control\n 25 1 read-write 0 Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Disabled #0 1 Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Enabled #1 CMPEN Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CMPF will be set. \n 28 1 read-write 0 The compare function Disabled #0 1 The compare function Enabled #1 CMPIEN CMPF Trigger Input Capture Interrupt Enable Bit\n 21 1 read-write 0 The flag CMPF can trigger Input Capture interrupt Disabled #0 1 The flag CMPF can trigger Input Capture interrupt Enabled #1 CNTEN Input Capture Counter Start\nSetting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK). \n 24 1 read-write 0 ECAP_CNT stop counting #0 1 ECAP_CNT starts up-counting #1 CPTCLR Input Capture Counter Cleared by Capture Events Control\nIf this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to zero when any one of capture events (CAPF0~3) occurs. \n 26 1 read-write 0 Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Disabled #0 1 Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Enabled #1 NFDIS Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock \n 0 2 read-write 0 CAP_CLK #00 1 CAP_CLK/2 #01 2 CAP_CLK/4 #10 3 CAP_CLK/16 #11 OVIEN OVF Trigger Input Capture Interrupt Enable Bit\n 20 1 read-write 0 The flag OVUNF can trigger Input Capture interrupt Disabled #0 1 The flag OVUNF can trigger Input Capture interrupt Enabled #1 RLDEN Reload Function Enable Bit \nSetting this bit to enable the reload function. If the reload control is enabled, an overflow event (OVF) or capture events (CAPFx) will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT.\n 27 1 read-write 0 The reload function Disabled #0 1 The reload function Enabled #1 ECAP_CTL1 ECAP_CTL1 Input Capture Control Register 1 0x18 read-write n 0x0 0x0 CLKSEL Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[1:0].\n 12 3 read-write 0 CAP_CLK/1 #000 1 CAP_CLK/4 #001 2 CAP_CLK/16 #010 3 CAP_CLK/32 #011 4 CAP_CLK/64 #100 5 CAP_CLK/96 #101 6 CAP_CLK/112 #110 7 CAP_CLK/128 #111 EDGESEL0 Channel 0 Captured Edge Selection\nInput capture can detect falling edge change only, rising edge change only or one of both edge change \n 0 2 read-write 0 Detect rising edge #00 1 Detect falling edge.\nDetect either rising or falling edge #01 EDGESEL1 Channel 1 Captured Edge Selection\nInput capture can detect falling edge change only, rising edge change only or one of both edge change \n 2 2 read-write 0 Detect rising edge #00 1 Detect falling edge.\nDetect either rising or falling edge #01 EDGESEL2 Channel 2 Captured Edge Selection\nInput capture can detect falling edge change or rising edge change only, or one of both edge changes. \n 4 2 read-write 0 Detect rising edge #00 1 Detect falling edge.\nDetect either rising or falling edge #01 RLDSEL ECAP_CNT Reload Trigger Source Selection\n 8 3 read-write 0 CAPF0 #000 1 CAPF1 #001 2 CAPF2 #010 4 OVF #100 SRCSEL Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source.\n 16 2 read-write 0 CAP_CLK (default) #00 1 CAP0 #01 2 CAP1 #10 3 CAP2 #11 ECAP_HOLD0 ECAP_HOLD0 Input Capture Counter Hold Register 0 0x4 read-write n 0x0 0x0 VAL Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register. Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from ECAPx_IC0 to ECAPx_IC2, respectively. 0 24 read-write ECAP_HOLD1 ECAP_HOLD1 Input Capture Counter Hold Register 1 0x8 read-write n 0x0 0x0 ECAP_HOLD2 ECAP_HOLD2 Input Capture Counter Hold Register 2 0xC read-write n 0x0 0x0 ECAP_STATUS ECAP_STATUS Input Capture Status Register 0x1C read-write n 0x0 0x0 CAPF0 Input Capture Channel 0 Captured Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPF0 to high. \nNote: This bit is only cleared by writing 1 to it. 0 1 read-write 0 No valid edge change is detected at CAP0 input #0 1 A valid edge change is detected at CAP0 input #1 CAPF1 Input Capture Channel 1 Captured Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPF1 to high. \nNote: This bit is only cleared by writing 1 to it. 1 1 read-write 0 No valid edge change is detected at CAP1 input #0 1 A valid edge change is detected at CAP1 input #1 CAPF2 Input Capture Channel 2 Captured Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPF2 to high. \nNote: This bit is only cleared by writing 1 to it. 2 1 read-write 0 No valid edge change is detected at CAP2 input #0 1 A valid edge change is detected at CAP2 input #1 CMPF Input Capture Compare-match Flag\nIf the input capture compare function is enabled, the flag is set by hardware while capture counter (ECAP_CNT) up counts and reach to the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it. 4 1 read-write 0 ECAP_CNT does not match with ECAP_CNTCMP value #0 1 ECAP_CNT counts to the same as ECAP_CNTCMP value #1 OVF Input Capture Counter Overflow Flag\nFlag is set by hardware when input capture up counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\nNote: This bit is only cleared by writing 1 to it. 5 1 read-write 0 No overflow occurs in ECAP_CNT #0 1 ECAP_CNT overflows #1 EPWM0 EPWM Register Map EPWM 0x0 0x0 0x20 registers n 0x2C 0xC registers n 0x3C 0x8 registers n PDTC PDTC EPWM Dead-time Control Register 0x2C read-write n 0x0 0x0 DTCNT Dead-time Counter\nThe dead-time can be calculated according to the following formula: \n 0 11 read-write DTEN0 Enable Dead-time Insertion for PWMx Pair (PWM_CH0, PWM_CH1)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n 16 1 read-write 0 Dead-time insertion Disabled on the pin pair (PWM_CH0, PWM_CH1) #0 1 Dead-time insertion Enabled on the pin pair (PWM_CH0, PWM_CH1) #1 DTEN2 Enable Dead-time Insertion for PWMx Pair (PWM_CH2, PWM_CH3)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n 17 1 read-write 0 Dead-time insertion Disabled on the pin pair (PWM_CH2, PWM_CH3) #0 1 Dead-time insertion Enabled on the pin pair (PWM_CH2, PWM_CH3) #1 DTEN4 Enable Dead-time Insertion for PWMx Pair (PWM_CH4, PWM_CH5)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n 18 1 read-write 0 Dead-time insertion Disabled on the pin pair (PWM_CH4, PWM_CH5) #0 1 Dead-time insertion Enabled on the pin pair (PWM_CH4, PWM_CH5) #1 PMSKD PMSKD EPWM Mask Mode Data Register 0x1C read-write n 0x0 0x0 PMSKD PWM Mask Data Bit\n 0 6 read-write 0 Output logic low to PWM_CHn 0 1 Output logic high to PWM_CHn 1 PMSKE PMSKE EPWM Mask Mode Enable Register 0x18 read-write n 0x0 0x0 PMSKE PWM Mask Enable Bits\nThe PWM generator signal will be masked when this bit is enabled. The corresponding PWM channel n will be output with PMSKD[n] data. \n 0 6 read-write 0 PWM generator signal is output to next stage 0 1 PWM generator signal is masked and PMSKD[n] is output to next stage, n = 0~5 1 PNPC PNPC EPWM Negative Polarity Control Register 0x34 read-write n 0x0 0x0 PNP PWM Negative Polarity Control\n 0 6 read-write 0 PWM_CHn output is active high 0 1 PWM_CHn output is active low 1 PWM0 PWM0 EPWM PWM0 Duty Register 0xC read-write n 0x0 0x0 PWM_Duty PWM Duty Register\nEdge-aligned:\n 0 16 read-write PWM2 PWM2 EPWM PWM2 Duty Register 0x10 read-write n 0x0 0x0 PWM4 PWM4 EPWM PWM4 Duty Register 0x14 read-write n 0x0 0x0 PWMB PWMB EPWM Brake Output Register 0x30 read-write n 0x0 0x0 PWMB PWM Brake Output\n 0 6 read-write 0 PWM_CHn output before polarity control is low when Brake is asserted 0 1 PWM_CHn output before polarity control is high when Brake is asserted 1 PWMCON PWMCON EPWM Control Register 0x0 read-write n 0x0 0x0 BK0FILT Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection\n 20 2 read-write 0 filter clock is HCLK #00 1 filter clock is HCLK/2 #01 2 filter clock is HCLK/4 #10 3 filter clock is HCLK/16 #11 BK0NF_DIS PWM Brake 0 Noise Filter Disable Bit\n 28 1 read-write 0 Noise filter of PWM Brake 0 Enabled #0 1 Noise filter of PWM Brake 0 Disabled #1 BK1FILT Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection\n 22 2 read-write 0 filter clock is HCLK #00 1 filter clock is HCLK/2 #01 2 filter clock is HCLK/4 #10 3 filter clock is HCLK/16 #11 BK1NF_DIS PWM Brake 1 Noise Filter Disable Bit\n 29 1 read-write 0 Noise filter of PWM Brake 1 Enabled #0 1 Noise filter of PWM Brake 1 Disabled #1 BK1SEL Brake Function 1 Source Selection\n 18 2 read-write 0 brake signal is from external pin EPWMx_BRAKE1 (x=0~1 for unit0~1) #00 1 brake signal is from analog comparator 0 output CO0 (ACMPSR[8]) #01 2 brake signal is from analog comparator 1 output CO1 (ACMPSR[9]) #10 3 brake signal is from analog comparator 2 output CO2 (ACMPSR[10]) #11 BKEN0 BRAKE0 Pin Trigger Brake Function 0 Enable Bit\n 16 1 read-write 0 PWMx brake function 0 Disabled #0 1 PWMx brake function 0 Enabled #1 BKEN1 BRAKE1 Pin Trigger Brake Function 1 Enable Bit\n 17 1 read-write 0 PWMx brake function 1 Disabled #0 1 PWMx brake function 1 Enabled #1 BRKI_EN Brake0 and Brak1 Interrupt Enable Bit\n 5 1 read-write 0 Flags BKF0 (PWMSTS[0]) and BKF1 (PWMSTS[1]) Disabled to trigger PWM interrupt #0 1 Flags BKF0 (PWMSTS[0]) and BKF1 (PWMSTS[1]) Enabled to trigger PWM interrupt #1 CLDMD Center Reload Mode Enable Bit\nThis bit only works when EPWM operating in Center-aligned mode. 31 1 read-write 0 EPWM reload duty register at the period point of PWM counter #0 1 EPWM reload duty register at the center point of PWM counter #1 CLRPWM Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware. 11 1 read-write 0 Ignored #0 1 Clear 16-bit PWM counter to 0000H #1 CPO0BK_EN ACMP0 Digital Output As Brake0 Source Enable Bit\n 24 1 read-write 0 CO0 (ACMPSR[8]) as one brake source in Brake 0 Disabled #0 1 CO0 (ACMPSR[8]) as one brake source in Brake 0 Enabled #1 CPO1BK_EN ACMP1 Digital Output As Brake 0 Source Enable Bit\n 25 1 read-write 0 CO1 (ACMPSR[9]) as one brake source in Brake 0 Disabled #0 1 CO1 (ACMPSR[9]) as one brake source in Brake 0 Enabled #1 CPO2BK_EN ACMP2 Digital Output As Brake 0 Source Enable Bit\n 26 1 read-write 0 CO2 (ACMPSR[10]) as one brake source in Brake 0 Disabled #0 1 CO2 (ACMPSR[10]) as one brake source in Brake 0 Enabled #1 GRP Group Bit\n 13 1 read-write 0 The signals timing of PWM_CH0, PWM_CH2 and PWM_CH4 are independent #0 1 Unify the signals timing of PWM_CH0, PWM_CH2 and PWM_CH4 in the same phase which is controlled by PWM_CH0 #1 INT_TYPE PWM Interrupt Type Selection Bit\nNote: This bit is effective when PWM is in Center-aligned mode only. 8 1 read-write 0 PWMF will be set if PWM counter underflow #0 1 PWMF will be set if PWM counter matches PWMP register #1 INVBKP0 Inverse Brake 0 Pin State\n 14 1 read-write 0 The state of pin EPWMx_BRAKE0 is passed to the negative edge detector #0 1 The inversed state of pin EPWMx_BRAKE0 is passed to the negative edge detector #1 INVBKP1 Inverse Brake 1 Pin State\n 15 1 read-write 0 The state of pin EPWMx_BRAKE1 is passed to the negative edge detector #0 1 The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector #1 LOAD Reload PWM Period Registers (PWMP) and PWM Duty Registers (PWM0~4) Control Bit\nNote: This bit is written by software, cleared by hardware, and always read as 0. 6 1 read-write 0 No action if written with 0. The value of PWM period register (PWMP) and PWM duty registers (PWM0~PWM4) are not loaded to PWM counter and Comparator registers #0 1 Hardware will update the value of PWM period register (PWMP) and PWM duty registers (PWM0~PWM4) to PWM Counter and Comparator register at the time of PWM Counter matches PWMP in Edge- and Center-aligned modes or at the time of PWM Counter down counts with underflow in Center-aligned mode #1 LVDBK_EN Low-level Detection Trigger PWM Brake Function 1 Enable Bit\n 27 1 read-write 0 Brake Function 1 triggered by Low-level detection Disabled #0 1 Brake Function 1 triggered by Low-level detection Enabled #1 PWMDIV PWM Clock Pre-divider Selection\n 2 2 read-write 0 PWM clock is EPWMx_CLK #00 1 PWM clock is EPWMx_CLK/2 #01 2 PWM clock is EPWMx_CLK/4 #10 3 PWM clock is EPWMx_CLK/16 #11 PWMINV Inverse PWM Comparator Output\nWhen PWMINV is set to high the PWM comparator output signals will be inversed, therefore the PWM Duty (in percentage) is changed to (1-Duty) before PWMINV is set to high.\n 9 1 read-write 0 Not inverse PWM comparator output #0 1 Inverse PWM comparator output #1 PWMI_EN PWM Interrupt Enable Bit\n 4 1 read-write 0 Flag PWMF (PWMSTS[2]) Disabled to trigger PWM interrupt #0 1 Flag PWMF (PWMSTS[2]) Enabled to trigger PWM interrupt #1 PWMMOD PWM Mode Selection\n 0 2 read-write 0 PWM mode is independent mode #00 1 PWM mode is pair/complementary mode #01 2 PWM mode is synchronized mode #10 3 Reserved #11 PWMRUN Start PWMRUN Control Bit\n 7 1 read-write 0 The PWM stops running #0 1 The PWM counter starts running #1 PWMTYPE PWM Aligned Type Selection Bit\n 12 1 read-write 0 Edge-aligned type #0 1 Center-aligned type #1 PWMEIC PWMEIC EPWM Edge Interrupt Control Register 0x40 read-write n 0x0 0x0 EINT0_TYPE PWM Channel 0 Edge Interrupt Type\n 8 1 read-write 0 PWM0EF will be set if falling edge is detected at PWM_CH0 #0 1 PWM0EF will be set if rising edge is detected at PWM_CH0 #1 EINT2_TYPE PWM Channel 2 Edge Interrupt Type\n 9 1 read-write 0 PWM2EF will be set if falling edge is detected at PWM_CH2 #0 1 PWM2EF will be set if rising edge is detected at PWM_CH2 #1 EINT4_TYPE PWM Channel 4 Edge Interrupt Type\n 10 1 read-write 0 PWM4EF will be set if falling edge is detected at PWM_CH4 #0 1 PWM4EF will be set if rising edge is detected at PWM_CH4 #1 PWM0EI_EN Enable PWM Channel 0 Edge Interrupt\n 0 1 read-write 0 Flag PWM0EF Disabled to trigger PWM interrupt #0 1 Flag PWM0EF Enabled to trigger PWM interrupt #1 PWM2EI_EN Enable PWM Channel 2 Edge Interrupt\n 1 1 read-write 0 Flag PWM2EF Disabled to trigger PWM interrupt #0 1 Flag PWM2EF Enabled to trigger PWM interrupt #1 PWM4EI_EN Enable PWM Channel 4 Edge Interrupt\n 2 1 read-write 0 Flag PWM4EF Disabled to trigger PWM interrupt #0 1 Flag PWM4EF Enabled to trigger PWM interrupt #1 PWMFCNT PWMFCNT EPWMF Compared Counter Register 0x3C read-write n 0x0 0x0 PWMFCNT PWMF Compared Counter\nThe register sets the count number which defines how many times of PWM period occurs to set bit PWMF (PWMSTS[2]) to request the PWM period interrupt. \nPWMF (PWMSTS[2]) will be set in every (PWMFCNT[3:0] + 1) times of PWM period or center point defined by INT_TYPE at PWMCON[8] occurs 0 4 read-write PWMP PWMP EPWM Period Register 0x8 read-write n 0x0 0x0 PWMP PWM Period Register\nEdge-aligned:\n 0 16 read-write PWMSTS PWMSTS EPWM Status Register 0x4 read-write n 0x0 0x0 BK0STS Brake 0 Status (Read Only)\n 24 1 read-only 0 PWM had been out of Brake 0 state #0 1 PWM is in Brake 0 state #1 BK1STS Brake 1 Status (Read Only)\n 25 1 read-only 0 PWM had been out of Brake 1 state #0 1 PWM is in Brake 1 state #1 BKF0 PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to itself through software. 0 1 read-write 0 PWM Brake 0 is able to poll falling signal at EPWMx_BRAKE0, x=0, 1 and has not recognized any one #0 1 When PWM Brake 0 detects a falling signal at EPWMx_BRAKE0, x=0, 1, this flag will be set to high #1 BKF1 PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to itself through software. 1 1 read-write 0 PWM Brake 1 is able to poll falling signal at EPWMx_BRAKE1, x=0, 1 and has not recognized any one #0 1 When PWM Brake 1 detects a falling signal at pin EPWMx_BRAKE1, x=0, 1, this flag will be set to high #1 BKLK0 PWM Brake 0 Locked \nNote: This bit must be cleared by writing 1 to itself through software. 8 1 read-write 0 Brake 0 state is released #0 1 When PWM Brake detects a falling signal at EPWMx_BRAKE0, x=0, 1. This flag will be set to high to indicate the Brake 0 state is locked #1 PWM0EF PWM Channel 0 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software. 4 1 read-write 0 PWM_CH0 not toggled #0 1 Hardware will set this flag to high at the time of PWM_CH0 rising or falling. If EINT0_TYPE (PWMEIC[8]) = 0, this bit is set when PWM_CH0 falling is detected. If EINT0_TYPE (PWMEIC[8]) = 1, this bit is set when PWM_CH0 rising is detected #1 PWM2EF PWM Channel 2 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software. 5 1 read-write 0 PWM_CH2 not toggled #0 1 Hardware will set this flag to high at the time of PWM_CH2 rising or falling. If EINT2_TYPE (PWMEIC[9]) = 0, this bit is set when PWM_CH2 falling is detected. If EINT2_TYPE (PWMEIC[9]) = 1, this bit is set when PWM_CH2 rising is detected #1 PWM4EF PWM Channel 4 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software. 6 1 read-write 0 PWM_CH4 not toggled #0 1 Hardware will set this flag to high at the time of PWM_CH4 rising or falling. If EINT4_TYPE (PWMEIC[10]) = 0, this bit is set when PWM_CH4 falling is detected. If EINT4_TYPE (PWMEIC[10]) = 1, this bit is set when PWM_CH4 rising is detected #1 PWMF PWM Period Flag\nNote: This bit must be cleared by writing 1 to itself through software. 2 1 read-write 0 The PWM Counter has not up counted to the value of PWMP or down counted with underflow #0 1 Hardware will set this flag to high at the time of PWM Counter matches PWMP in Edge- and Center-aligned modes or at the time of PWM Counter down counts with underflow in Center-aligned mode #1 EPWM1 EPWM Register Map EPWM 0x0 0x0 0x20 registers n 0x2C 0xC registers n 0x3C 0x8 registers n PDTC PDTC EPWM Dead-time Control Register 0x2C read-write n 0x0 0x0 DTCNT Dead-time Counter\nThe dead-time can be calculated according to the following formula: \n 0 11 read-write DTEN0 Enable Dead-time Insertion for PWMx Pair (PWM_CH0, PWM_CH1)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n 16 1 read-write 0 Dead-time insertion Disabled on the pin pair (PWM_CH0, PWM_CH1) #0 1 Dead-time insertion Enabled on the pin pair (PWM_CH0, PWM_CH1) #1 DTEN2 Enable Dead-time Insertion for PWMx Pair (PWM_CH2, PWM_CH3)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n 17 1 read-write 0 Dead-time insertion Disabled on the pin pair (PWM_CH2, PWM_CH3) #0 1 Dead-time insertion Enabled on the pin pair (PWM_CH2, PWM_CH3) #1 DTEN4 Enable Dead-time Insertion for PWMx Pair (PWM_CH4, PWM_CH5)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n 18 1 read-write 0 Dead-time insertion Disabled on the pin pair (PWM_CH4, PWM_CH5) #0 1 Dead-time insertion Enabled on the pin pair (PWM_CH4, PWM_CH5) #1 PMSKD PMSKD EPWM Mask Mode Data Register 0x1C read-write n 0x0 0x0 PMSKD PWM Mask Data Bit\n 0 6 read-write 0 Output logic low to PWM_CHn 0 1 Output logic high to PWM_CHn 1 PMSKE PMSKE EPWM Mask Mode Enable Register 0x18 read-write n 0x0 0x0 PMSKE PWM Mask Enable Bits\nThe PWM generator signal will be masked when this bit is enabled. The corresponding PWM channel n will be output with PMSKD[n] data. \n 0 6 read-write 0 PWM generator signal is output to next stage 0 1 PWM generator signal is masked and PMSKD[n] is output to next stage, n = 0~5 1 PNPC PNPC EPWM Negative Polarity Control Register 0x34 read-write n 0x0 0x0 PNP PWM Negative Polarity Control\n 0 6 read-write 0 PWM_CHn output is active high 0 1 PWM_CHn output is active low 1 PWM0 PWM0 EPWM PWM0 Duty Register 0xC read-write n 0x0 0x0 PWM_Duty PWM Duty Register\nEdge-aligned:\n 0 16 read-write PWM2 PWM2 EPWM PWM2 Duty Register 0x10 read-write n 0x0 0x0 PWM4 PWM4 EPWM PWM4 Duty Register 0x14 read-write n 0x0 0x0 PWMB PWMB EPWM Brake Output Register 0x30 read-write n 0x0 0x0 PWMB PWM Brake Output\n 0 6 read-write 0 PWM_CHn output before polarity control is low when Brake is asserted 0 1 PWM_CHn output before polarity control is high when Brake is asserted 1 PWMCON PWMCON EPWM Control Register 0x0 read-write n 0x0 0x0 BK0FILT Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection\n 20 2 read-write 0 filter clock is HCLK #00 1 filter clock is HCLK/2 #01 2 filter clock is HCLK/4 #10 3 filter clock is HCLK/16 #11 BK0NF_DIS PWM Brake 0 Noise Filter Disable Bit\n 28 1 read-write 0 Noise filter of PWM Brake 0 Enabled #0 1 Noise filter of PWM Brake 0 Disabled #1 BK1FILT Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection\n 22 2 read-write 0 filter clock is HCLK #00 1 filter clock is HCLK/2 #01 2 filter clock is HCLK/4 #10 3 filter clock is HCLK/16 #11 BK1NF_DIS PWM Brake 1 Noise Filter Disable Bit\n 29 1 read-write 0 Noise filter of PWM Brake 1 Enabled #0 1 Noise filter of PWM Brake 1 Disabled #1 BK1SEL Brake Function 1 Source Selection\n 18 2 read-write 0 brake signal is from external pin EPWMx_BRAKE1 (x=0~1 for unit0~1) #00 1 brake signal is from analog comparator 0 output CO0 (ACMPSR[8]) #01 2 brake signal is from analog comparator 1 output CO1 (ACMPSR[9]) #10 3 brake signal is from analog comparator 2 output CO2 (ACMPSR[10]) #11 BKEN0 BRAKE0 Pin Trigger Brake Function 0 Enable Bit\n 16 1 read-write 0 PWMx brake function 0 Disabled #0 1 PWMx brake function 0 Enabled #1 BKEN1 BRAKE1 Pin Trigger Brake Function 1 Enable Bit\n 17 1 read-write 0 PWMx brake function 1 Disabled #0 1 PWMx brake function 1 Enabled #1 BRKI_EN Brake0 and Brak1 Interrupt Enable Bit\n 5 1 read-write 0 Flags BKF0 (PWMSTS[0]) and BKF1 (PWMSTS[1]) Disabled to trigger PWM interrupt #0 1 Flags BKF0 (PWMSTS[0]) and BKF1 (PWMSTS[1]) Enabled to trigger PWM interrupt #1 CLDMD Center Reload Mode Enable Bit\nThis bit only works when EPWM operating in Center-aligned mode. 31 1 read-write 0 EPWM reload duty register at the period point of PWM counter #0 1 EPWM reload duty register at the center point of PWM counter #1 CLRPWM Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware. 11 1 read-write 0 Ignored #0 1 Clear 16-bit PWM counter to 0000H #1 CPO0BK_EN ACMP0 Digital Output As Brake0 Source Enable Bit\n 24 1 read-write 0 CO0 (ACMPSR[8]) as one brake source in Brake 0 Disabled #0 1 CO0 (ACMPSR[8]) as one brake source in Brake 0 Enabled #1 CPO1BK_EN ACMP1 Digital Output As Brake 0 Source Enable Bit\n 25 1 read-write 0 CO1 (ACMPSR[9]) as one brake source in Brake 0 Disabled #0 1 CO1 (ACMPSR[9]) as one brake source in Brake 0 Enabled #1 CPO2BK_EN ACMP2 Digital Output As Brake 0 Source Enable Bit\n 26 1 read-write 0 CO2 (ACMPSR[10]) as one brake source in Brake 0 Disabled #0 1 CO2 (ACMPSR[10]) as one brake source in Brake 0 Enabled #1 GRP Group Bit\n 13 1 read-write 0 The signals timing of PWM_CH0, PWM_CH2 and PWM_CH4 are independent #0 1 Unify the signals timing of PWM_CH0, PWM_CH2 and PWM_CH4 in the same phase which is controlled by PWM_CH0 #1 INT_TYPE PWM Interrupt Type Selection Bit\nNote: This bit is effective when PWM is in Center-aligned mode only. 8 1 read-write 0 PWMF will be set if PWM counter underflow #0 1 PWMF will be set if PWM counter matches PWMP register #1 INVBKP0 Inverse Brake 0 Pin State\n 14 1 read-write 0 The state of pin EPWMx_BRAKE0 is passed to the negative edge detector #0 1 The inversed state of pin EPWMx_BRAKE0 is passed to the negative edge detector #1 INVBKP1 Inverse Brake 1 Pin State\n 15 1 read-write 0 The state of pin EPWMx_BRAKE1 is passed to the negative edge detector #0 1 The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector #1 LOAD Reload PWM Period Registers (PWMP) and PWM Duty Registers (PWM0~4) Control Bit\nNote: This bit is written by software, cleared by hardware, and always read as 0. 6 1 read-write 0 No action if written with 0. The value of PWM period register (PWMP) and PWM duty registers (PWM0~PWM4) are not loaded to PWM counter and Comparator registers #0 1 Hardware will update the value of PWM period register (PWMP) and PWM duty registers (PWM0~PWM4) to PWM Counter and Comparator register at the time of PWM Counter matches PWMP in Edge- and Center-aligned modes or at the time of PWM Counter down counts with underflow in Center-aligned mode #1 LVDBK_EN Low-level Detection Trigger PWM Brake Function 1 Enable Bit\n 27 1 read-write 0 Brake Function 1 triggered by Low-level detection Disabled #0 1 Brake Function 1 triggered by Low-level detection Enabled #1 PWMDIV PWM Clock Pre-divider Selection\n 2 2 read-write 0 PWM clock is EPWMx_CLK #00 1 PWM clock is EPWMx_CLK/2 #01 2 PWM clock is EPWMx_CLK/4 #10 3 PWM clock is EPWMx_CLK/16 #11 PWMINV Inverse PWM Comparator Output\nWhen PWMINV is set to high the PWM comparator output signals will be inversed, therefore the PWM Duty (in percentage) is changed to (1-Duty) before PWMINV is set to high.\n 9 1 read-write 0 Not inverse PWM comparator output #0 1 Inverse PWM comparator output #1 PWMI_EN PWM Interrupt Enable Bit\n 4 1 read-write 0 Flag PWMF (PWMSTS[2]) Disabled to trigger PWM interrupt #0 1 Flag PWMF (PWMSTS[2]) Enabled to trigger PWM interrupt #1 PWMMOD PWM Mode Selection\n 0 2 read-write 0 PWM mode is independent mode #00 1 PWM mode is pair/complementary mode #01 2 PWM mode is synchronized mode #10 3 Reserved #11 PWMRUN Start PWMRUN Control Bit\n 7 1 read-write 0 The PWM stops running #0 1 The PWM counter starts running #1 PWMTYPE PWM Aligned Type Selection Bit\n 12 1 read-write 0 Edge-aligned type #0 1 Center-aligned type #1 PWMEIC PWMEIC EPWM Edge Interrupt Control Register 0x40 read-write n 0x0 0x0 EINT0_TYPE PWM Channel 0 Edge Interrupt Type\n 8 1 read-write 0 PWM0EF will be set if falling edge is detected at PWM_CH0 #0 1 PWM0EF will be set if rising edge is detected at PWM_CH0 #1 EINT2_TYPE PWM Channel 2 Edge Interrupt Type\n 9 1 read-write 0 PWM2EF will be set if falling edge is detected at PWM_CH2 #0 1 PWM2EF will be set if rising edge is detected at PWM_CH2 #1 EINT4_TYPE PWM Channel 4 Edge Interrupt Type\n 10 1 read-write 0 PWM4EF will be set if falling edge is detected at PWM_CH4 #0 1 PWM4EF will be set if rising edge is detected at PWM_CH4 #1 PWM0EI_EN Enable PWM Channel 0 Edge Interrupt\n 0 1 read-write 0 Flag PWM0EF Disabled to trigger PWM interrupt #0 1 Flag PWM0EF Enabled to trigger PWM interrupt #1 PWM2EI_EN Enable PWM Channel 2 Edge Interrupt\n 1 1 read-write 0 Flag PWM2EF Disabled to trigger PWM interrupt #0 1 Flag PWM2EF Enabled to trigger PWM interrupt #1 PWM4EI_EN Enable PWM Channel 4 Edge Interrupt\n 2 1 read-write 0 Flag PWM4EF Disabled to trigger PWM interrupt #0 1 Flag PWM4EF Enabled to trigger PWM interrupt #1 PWMFCNT PWMFCNT EPWMF Compared Counter Register 0x3C read-write n 0x0 0x0 PWMFCNT PWMF Compared Counter\nThe register sets the count number which defines how many times of PWM period occurs to set bit PWMF (PWMSTS[2]) to request the PWM period interrupt. \nPWMF (PWMSTS[2]) will be set in every (PWMFCNT[3:0] + 1) times of PWM period or center point defined by INT_TYPE at PWMCON[8] occurs 0 4 read-write PWMP PWMP EPWM Period Register 0x8 read-write n 0x0 0x0 PWMP PWM Period Register\nEdge-aligned:\n 0 16 read-write PWMSTS PWMSTS EPWM Status Register 0x4 read-write n 0x0 0x0 BK0STS Brake 0 Status (Read Only)\n 24 1 read-only 0 PWM had been out of Brake 0 state #0 1 PWM is in Brake 0 state #1 BK1STS Brake 1 Status (Read Only)\n 25 1 read-only 0 PWM had been out of Brake 1 state #0 1 PWM is in Brake 1 state #1 BKF0 PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to itself through software. 0 1 read-write 0 PWM Brake 0 is able to poll falling signal at EPWMx_BRAKE0, x=0, 1 and has not recognized any one #0 1 When PWM Brake 0 detects a falling signal at EPWMx_BRAKE0, x=0, 1, this flag will be set to high #1 BKF1 PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to itself through software. 1 1 read-write 0 PWM Brake 1 is able to poll falling signal at EPWMx_BRAKE1, x=0, 1 and has not recognized any one #0 1 When PWM Brake 1 detects a falling signal at pin EPWMx_BRAKE1, x=0, 1, this flag will be set to high #1 BKLK0 PWM Brake 0 Locked \nNote: This bit must be cleared by writing 1 to itself through software. 8 1 read-write 0 Brake 0 state is released #0 1 When PWM Brake detects a falling signal at EPWMx_BRAKE0, x=0, 1. This flag will be set to high to indicate the Brake 0 state is locked #1 PWM0EF PWM Channel 0 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software. 4 1 read-write 0 PWM_CH0 not toggled #0 1 Hardware will set this flag to high at the time of PWM_CH0 rising or falling. If EINT0_TYPE (PWMEIC[8]) = 0, this bit is set when PWM_CH0 falling is detected. If EINT0_TYPE (PWMEIC[8]) = 1, this bit is set when PWM_CH0 rising is detected #1 PWM2EF PWM Channel 2 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software. 5 1 read-write 0 PWM_CH2 not toggled #0 1 Hardware will set this flag to high at the time of PWM_CH2 rising or falling. If EINT2_TYPE (PWMEIC[9]) = 0, this bit is set when PWM_CH2 falling is detected. If EINT2_TYPE (PWMEIC[9]) = 1, this bit is set when PWM_CH2 rising is detected #1 PWM4EF PWM Channel 4 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software. 6 1 read-write 0 PWM_CH4 not toggled #0 1 Hardware will set this flag to high at the time of PWM_CH4 rising or falling. If EINT4_TYPE (PWMEIC[10]) = 0, this bit is set when PWM_CH4 falling is detected. If EINT4_TYPE (PWMEIC[10]) = 1, this bit is set when PWM_CH4 rising is detected #1 PWMF PWM Period Flag\nNote: This bit must be cleared by writing 1 to itself through software. 2 1 read-write 0 The PWM Counter has not up counted to the value of PWMP or down counted with underflow #0 1 Hardware will set this flag to high at the time of PWM Counter matches PWMP in Edge- and Center-aligned modes or at the time of PWM Counter down counts with underflow in Center-aligned mode #1 FMC FMC Register Map FMC 0x0 0x0 0x1C registers n 0x40 0x4 registers n DFBADR DFBADR Data Flash Base Address 0x14 read-only n 0x0 0x0 DFBADR Data Flash Base Address\nThis register indicates data flash start address. It is read only.\nFor 128 KB flash memory device, the data flash size is defined by user configuration, register content is loaded from Config1 when chip is powered on but for 64 KB device, it is fixed at 0x0001_F000. 0 32 read-only FATCON FATCON Flash Access Time Control Register 0x18 read-write n 0x0 0x0 FOM_SEL0 Chip Frequency Optimization Mode Select (Write Protect)\n 4 1 read-write FOM_SEL1 Chip Frequency Optimization Mode Select (Write Protect)\n 6 1 read-write ISPADR ISPADR ISP Address Register 0x4 read-write n 0x0 0x0 ISPADR ISP Address The NuMicro M0519 Series has a maximum 32Kx32 (128 KB) of embedded Flash, which supports word program only. ISPADR[1:0] must be kept 00b for ISP operation. 0 32 read-write ISPCMD ISPCMD ISP Command Register 0xC read-write n 0x0 0x0 CMD ISP Command\nISP command table is shown below:\nThe other commands are invalid. 0 6 read-write 0 FLASH Read 0x00 4 Read Unique ID 0x04 11 Read Company ID 0x0b 33 FLASH Program 0x21 34 FLASH Page Erase 0x22 46 Vector Remap 0x2e ISPCON ISPCON ISP Control Register 0x0 read-write n 0x0 0x0 APUEN APROM Update Enable Bit (Write Protect)\n 3 1 read-write 0 APROM cannot be updated when chip runs in APROM #0 1 APROM can be updated when chip runs in APROM #1 BS Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened\n 1 1 read-write 0 Boot from APROM #0 1 Boot from LDROM #1 CFGUEN Config-bits Update Enable Bit (Write Protect)\n 4 1 read-write 0 User Configuration cannot be updated #0 1 User Configuration can be updated #1 ISPEN ISP Enable Bit (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\n 0 1 read-write 0 ISP function Disabled #0 1 ISP function Enabled #1 ISPFF ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\nWrite 1 to clear this bit. 6 1 read-write LDUEN LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\n 5 1 read-write 0 LDROM cannot be updated #0 1 LDROM can be updated when chip runs in APROM #1 ISPDAT ISPDAT ISP Data Register 0x8 read-write n 0x0 0x0 ISPDAT ISP Data\nWrite data to this register before ISP program operation\nRead data from this register after ISP read operation 0 32 read-write ISPSTA ISPSTA ISP Status Register 0x40 read-write n 0x0 0x0 CBS Chip Boot Selection of CONFIG (Read Only)\n 1 2 read-only 0 Boot from LDROM with IAP mode #00 1 Boot from LDROM without IAP mode #01 2 Boot from APROM with IAP mode #10 3 Boot from APROM without IAP mode #11 ISPFF ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (ISPCON[6]), it needs to be cleared by writing 1 to ISPCON[6] or FMC_ISPSTA[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\nWrite 1 to clear this bit. 6 1 read-write ISPGO ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same with ISPTRG bit0 0 1 read-only 0 ISP operation finished #0 1 ISP operation progressed #1 VECMAP Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}\nNote: vector map function only workable when IAP mode enabled 9 12 read-only ISPTRG ISPTRG ISP Trigger Control Register 0x10 read-write n 0x0 0x0 ISPGO ISP Start Trigger (Write Protect) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100 Note: To make sure ISP function has been finished before CPU goes ahead, ISB (Instruction Synchronization Barrier) instruction is used right after ISPGO (ISPTRG[0]) setting. 0 1 read-write 0 ISP operation finished #0 1 ISP progressed #1 GCR GCR Register Map GCR 0x0 0x0 0x10 registers n 0x100 0x4 registers n 0x18 0x8 registers n 0x24 0x4 registers n 0x30 0x2C registers n BODCR BODCR Brown-out Detector Control Register 0x18 -1 read-write n 0x0 0x0 BOD_EN Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (Config0[23]) bit.\nNote: This bit is write protected. Refer to the REGWRPROT register. 0 1 read-write 0 Brown-out Detector function Disabled #0 1 Brown-out Detector function Enabled #1 BOD_INTF Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0. 4 1 read-write 0 Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting #0 1 When Brown-out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled #1 BOD_LPM Brown-out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100 uA in Normal mode, and the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is write protected. Refer to the REGWRPROT register. 5 1 read-write 0 BOD operated in Normal mode (default) #0 1 BOD Low Power mode Enabled #1 BOD_OUT Brown-out Detector Output Status\n 6 1 read-write 0 Brown-out Detector output status is 0. It means the detected voltage is higher than BOD_VL setting or BOD_EN is 0 #0 1 Brown-out Detector output status is 1. It means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled, this bit always responds to 0 #1 BOD_RSTEN Brown-out Reset Enable Bit (Write Protect)\nNote1: While the Brown-out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BOD_OUT high).\nNote2: The default value is set by flash controller user configuration register CBRST (Config0[20]).\nNote3: This bit is write protected. Refer to the REGWRPROT register. 3 1 read-write 0 Brown-out INTERRUPT function Enabled #0 1 Brown-out RESET function Enabled #1 BOD_VL Brown-out Detector Threshold Voltage Select (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (Config0[22:21]) bits.\nNote: This bit is write protected. Refer to the REGWRPROT register. 1 2 read-write 0 Brown-out voltage is 2.2V #00 1 Brown-out voltage is 2.7V #01 2 Brown-out voltage is 3.7V #10 3 Brown-out voltage is 4.4V #11 LVR_EN Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote: This bit is write protected. Refer to the REGWRPROT register. 7 1 read-write 0 Low Voltage Reset function Disabled #0 1 Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default) #1 IPRSTC1 IPRSTC1 Peripheral Reset Control Register1 0x8 read-write n 0x0 0x0 CHIP_RST Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is the same as the POR reset. All the chip controllers are reset and the chip setting from flash are also reload.\nNote: This bit is write protected. Refer to the REGWRPROT register. 0 1 read-write 0 Chip normal operation #0 1 Chip one-shot reset #1 CPU_RST Cortex-M0 Core One-shot Reset (Write Protect)\nSetting this bit will only reset the CPU kernel and Flash Memory Controller (FMC), and this bit will automatically return 0 after the two clock cycles.\nNote: This bit is write protected. Refer to the REGWRPROT register. 1 1 read-write 0 CPU normal operation #0 1 CPU one-shot reset #1 HDIV_RST HDIV Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the hardware divider. User need to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the REGWRPROT register. 4 1 read-write 0 Hardware divider controller normal operation #0 1 Hardware divider controller reset #1 IPRSTC2 IPRSTC2 Peripheral Reset Control Register2 0xC read-write n 0x0 0x0 ACMP_RST Analog Comparator Controller Reset\n 22 1 read-write 0 Analog Comparator controller normal operation #0 1 Analog Comparator controller reset #1 BPWM0_RST Basic PWM0 Controller Reset\n 19 1 read-write 0 Basic PWM0 controller normal operation #0 1 Basic PWM0 controller reset #1 EADC_RST EADC Controller Reset\n 28 1 read-write 0 EADC controller normal operation #0 1 EADC controller reset #1 ECAP0_RST Enhanced Input Capture 0 Controller Reset\n 26 1 read-write 0 Enhanced input capture 0 controller normal operation #0 1 Enhanced input capture 0 controller reset #1 ECAP1_RST Enhanced Input Capture 1 Controller Reset\n 27 1 read-write 0 Enhanced input capture 1 controller normal operation #0 1 Enhanced input capture 1 controller reset #1 EPWM0_RST Enhanced PWM0 Controller Reset\n 20 1 read-write 0 EPWM0 controller normal operation #0 1 EPWM0 controller reset #1 EPWM1_RST Enhanced PWM1 Controller Reset\n 21 1 read-write 0 EPWM1 controller normal operation #0 1 EPWM1 controller reset #1 GPIO_RST GPIO Controller Reset\n 1 1 read-write 0 GPIO controller normal operation #0 1 GPIO controller reset #1 I2C0_RST I2C0 Controller Reset\n 8 1 read-write 0 I2C0 controller normal operation #0 1 I2C0 controller reset #1 OPA_RST OPA0 and OPA1 Controller Reset\n 29 1 read-write 0 OPA0 and OPA1 controller normal operation #0 1 OPA0 and OPA1 controller reset #1 SPI0_RST SPI0 Controller Reset\n 12 1 read-write 0 SPI0 controller normal operation #0 1 SPI0 controller reset #1 SPI1_RST SPI1 Controller Reset\n 13 1 read-write 0 SPI1 controller normal operation #0 1 SPI1 controller reset #1 SPI2_RST SPI2 Controller Reset\n 14 1 read-write 0 SPI2 controller normal operation #0 1 SPI2 controller reset #1 TMR0_RST Timer0 Controller Reset\n 2 1 read-write 0 Timer0 controller normal operation #0 1 Timer0 controller reset #1 TMR1_RST Timer1 Controller Reset\n 3 1 read-write 0 Timer1 controller normal operation #0 1 Timer1 controller reset #1 TMR2_RST Timer2 Controller Reset\n 4 1 read-write 0 Timer2 controller normal operation #0 1 Timer2 controller reset #1 TMR3_RST Timer3 Controller Reset\n 5 1 read-write 0 Timer3 controller normal operation #0 1 Timer3 controller reset #1 UART0_RST UART0 Controller Reset\n 16 1 read-write 0 UART0 controller normal operation #0 1 UART0 controller reset #1 UART1_RST UART1 Controller Reset\n 17 1 read-write 0 UART1 controller normal operation #0 1 UART1 controller reset #1 P0_MFP P0_MFP P0 Multiple Function and Input Type Control Register 0x30 read-write n 0x0 0x0 P0_ALT0 P0.0 Alternative Function\nSee P0_MFP[0]. 8 1 read-write P0_ALT1 P0.1 Alternative Function\nSee P0_MFP[1]. 9 1 read-write P0_ALT2 P0.2 Alternative Function\nSee P0_MFP[2]. 10 1 read-write P0_ALT3 P0.3 Alternative Function\nSee P0_MFP[3]. 11 1 read-write P0_MFP0 P0.0 Multi-function Selection\nBits P0_ALT[0] and P0_MFP[0] determine the P0.0 function.\n(P0_ALT[0], P0_MFP[0]) value and function mapping is as following list.\n 0 1 read-write P0_MFP1 P0.1 Multi-function Selection\nBits P0_ALT[1] and P0_MFP[1] determine the P0.1 function.\n(P0_ALT[2], P0_MFP[2]) value and function mapping is as following list.\n 1 1 read-write P0_MFP2 P0.2 Multi-function Selection\nBits P0_ALT[2] and P0_MFP[2] determine the P0.2 function.\n(P0_ALT[2], P0_MFP[2]) value and function mapping is as following list.\n 2 1 read-write P0_MFP3 P0.3 Multi-function Selection\nBits P0_ALT[3] and P0_MFP[3] determine the P0.3 function.\n(P0_ALT[3], P0_MFP[3]) value and function mapping is as following list.\n 3 1 read-write P0_MFP4 P0.4 Multi-function Selection\n 4 1 read-write 0 The GPIO P0.4 is selected #0 1 The EPWM0_CH4 function is selected #1 P0_MFP5 P0.5 Multi-function Selection\n 5 1 read-write 0 The GPIO P0.5 is selected #0 1 The EPWM0_CH5 function is selected #1 P0_MFP6 P0.6 Multi-function Selection\n 6 1 read-write 0 The GPIO P0.6 is selected #0 1 The EPWM0_BRAKE1 function is selected #1 P0_MFP7 P0.7 Multi-function Selection\n 7 1 read-write 0 The GPIO P0.7 is selected #0 1 The STADC function is selected #1 P0_TYPE0 Port 0 Schmitt Trigger Input Enable Bits\n 16 1 read-write 0 Port 0 bit m Schmitt trigger input function Disabled #0 1 Port 0 bit m Schmitt trigger input function Enabled #1 P0_TYPE1 Port 0 Schmitt Trigger Input Enable Bits\n 17 1 read-write 0 Port 0 bit m Schmitt trigger input function Disabled #0 1 Port 0 bit m Schmitt trigger input function Enabled #1 P0_TYPE2 Port 0 Schmitt Trigger Input Enable Bits\n 18 1 read-write 0 Port 0 bit m Schmitt trigger input function Disabled #0 1 Port 0 bit m Schmitt trigger input function Enabled #1 P0_TYPE3 Port 0 Schmitt Trigger Input Enable Bits\n 19 1 read-write 0 Port 0 bit m Schmitt trigger input function Disabled #0 1 Port 0 bit m Schmitt trigger input function Enabled #1 P0_TYPE4 Port 0 Schmitt Trigger Input Enable Bits\n 20 1 read-write 0 Port 0 bit m Schmitt trigger input function Disabled #0 1 Port 0 bit m Schmitt trigger input function Enabled #1 P0_TYPE5 Port 0 Schmitt Trigger Input Enable Bits\n 21 1 read-write 0 Port 0 bit m Schmitt trigger input function Disabled #0 1 Port 0 bit m Schmitt trigger input function Enabled #1 P0_TYPE6 Port 0 Schmitt Trigger Input Enable Bits\n 22 1 read-write 0 Port 0 bit m Schmitt trigger input function Disabled #0 1 Port 0 bit m Schmitt trigger input function Enabled #1 P0_TYPE7 Port 0 Schmitt Trigger Input Enable Bits\n 23 1 read-write 0 Port 0 bit m Schmitt trigger input function Disabled #0 1 Port 0 bit m Schmitt trigger input function Enabled #1 P1_MFP P1_MFP P1 Multiple Function and Input Type Control Register 0x34 read-write n 0x0 0x0 P1_MFP0 P1.0 Multi-function Selection\n 0 1 read-write 0 The GPIO P1.0 is selected #0 1 The EPWM1_CH0 function is selected #1 P1_MFP1 P1.1 Multi-function Selection\n 1 1 read-write 0 The GPIO P1.1 is selected #0 1 The EPWM1_CH1 function is selected #1 P1_MFP2 P1.2 Multi-function Selection\n 2 1 read-write 0 The GPIO P1.2 is selected #0 1 The EPWM1_CH2 function is selected #1 P1_MFP3 P1.3 Multi-function Selection\n 3 1 read-write 0 The GPIO P1.3 is selected #0 1 The EPWM1_CH3 function is selected #1 P1_MFP4 P1.4 Multi-function Selection\n 4 1 read-write 0 The GPIO P1.4 is selected #0 1 The EPWM1_CH4 function is selected #1 P1_MFP5 P1.5 Multi-function Selection\n 5 1 read-write 0 The GPIO P1.5 is selected #0 1 The EPWM1_CH5 function is selected #1 P1_MFP6 P1.6 Multi-function Selection\n 6 1 read-write 0 The GPIO P1.6 is selected #0 1 The EPWM0_BRAKE0 function is selected #1 P1_MFP7 P1.7 Multi-function Selection\n 7 1 read-write 0 The GPIO P1.7 is selected #0 1 The EPWM1_BRAKE0 function is selected #1 P1_TYPE0 Port 1 Schmitt Trigger Input Enable Bits\n 16 1 read-write 0 Port 1 bit m Schmitt trigger input function Disabled #0 1 Port 1 bit m Schmitt trigger input function Enabled #1 P1_TYPE1 Port 1 Schmitt Trigger Input Enable Bits\n 17 1 read-write 0 Port 1 bit m Schmitt trigger input function Disabled #0 1 Port 1 bit m Schmitt trigger input function Enabled #1 P1_TYPE2 Port 1 Schmitt Trigger Input Enable Bits\n 18 1 read-write 0 Port 1 bit m Schmitt trigger input function Disabled #0 1 Port 1 bit m Schmitt trigger input function Enabled #1 P1_TYPE3 Port 1 Schmitt Trigger Input Enable Bits\n 19 1 read-write 0 Port 1 bit m Schmitt trigger input function Disabled #0 1 Port 1 bit m Schmitt trigger input function Enabled #1 P1_TYPE4 Port 1 Schmitt Trigger Input Enable Bits\n 20 1 read-write 0 Port 1 bit m Schmitt trigger input function Disabled #0 1 Port 1 bit m Schmitt trigger input function Enabled #1 P1_TYPE5 Port 1 Schmitt Trigger Input Enable Bits\n 21 1 read-write 0 Port 1 bit m Schmitt trigger input function Disabled #0 1 Port 1 bit m Schmitt trigger input function Enabled #1 P1_TYPE6 Port 1 Schmitt Trigger Input Enable Bits\n 22 1 read-write 0 Port 1 bit m Schmitt trigger input function Disabled #0 1 Port 1 bit m Schmitt trigger input function Enabled #1 P1_TYPE7 Port 1 Schmitt Trigger Input Enable Bits\n 23 1 read-write 0 Port 1 bit m Schmitt trigger input function Disabled #0 1 Port 1 bit m Schmitt trigger input function Enabled #1 P2_MFP P2_MFP P2 Multiple Function and Input Type Control Register 0x38 read-write n 0x0 0x0 P2_ALT0 P2.0 Alternative Function\nSee P2_MFP[0]. 8 1 read-write P2_ALT4 P2.4 Alternative Function\nSee P2_MFP[4]. 12 1 read-write P2_ALT5 P2.5 Alternative Function\nSee P2_MFP[5]. 13 1 read-write P2_ALT6 P2.6 Alternative Function\nSee P2_MFP[6]. 14 1 read-write P2_ALT7 P2.7 Alternative Function\nSee P2_MFP[7]. 15 1 read-write P2_MFP0 P2.0 Multi-function Selection\nBits P2_ALT[0] and P2_MFP[0] determine the P2.0 function.\n(P2_ALT[0], P2_MFP[0]) value and function mapping is as following list.\n 0 1 read-write P2_MFP1 P2.1 Multi-function Selection\n 1 1 read-write 0 The GPIO P2.1 is selected #0 1 The ECAP0_IC2 function is selected #1 P2_MFP2 P2.2 Multi-function Selection\n 2 1 read-write 0 The GPIO P2.2 is selected #0 1 The ECAP0_IC1 function is selected #1 P2_MFP3 P2.3 Multi-function Selection\n 3 1 read-write 0 The GPIO P2.3 is selected #0 1 The ECAP0_IC0 function is selected #1 P2_MFP4 P2.4 Multi-function Selection\nBits P2_ALT[4] and P2_MFP[4] determine the P2.4 function.\n(P2_ALT[4], P2_MFP[4]) value and function mapping is as following list.\n 4 1 read-write P2_MFP5 P2.5 Multi-function Selection\nBits P2_ALT[5] and P2_MFP[5] determine the P2.5 function.\n(P2_ALT[5], P2_MFP[5]) value and function mapping is as following list.\n 5 1 read-write P2_MFP6 P2.6 Multi-function Selection\nBits P2_ALT[6] and P2_MFP[6] determine the P2.6 function.\n(P2_ALT[6], P2_MFP[6]) value and function mapping is as following list.\n 6 1 read-write P2_MFP7 P2.7 Multi-function Selection\nBits P2_ALT[7] and P2_MFP[7] determine the P2.7 function.\n(P2_ALT[7], P2_MFP[7]) value and function mapping is as following list.\n 7 1 read-write P2_TYPE Port 2 Schmitt Trigger Input Enable Bits\n 16 8 read-write 0 Port 2 bit m Schmitt trigger input function Disabled 0 1 Port 2 bit m Schmitt trigger input function Enabled 1 P3_MFP P3_MFP P3 Multiple Function and Input Type Control Register 0x3C read-write n 0x0 0x0 P3_ALT0 P3.0 Alternative Function\nSee P3_MFP[0]. 8 1 read-write P3_ALT1 P3.1 Alternative Function\nSee P3_MFP[1]. 9 1 read-write P3_ALT4 P3.4 Alternative Function\nSee P3_MFP[4]. 12 1 read-write P3_ALT5 P3.5 Alternative Function\nSee P3_MFP[5]. 13 1 read-write P3_MFP0 P3.0 Multi-function Selection\nBits P3_ALT[0] and P3_MFP[0] determine the P3.0 function.\n(P3_ALT[0], P3_MFP[0]) value and function mapping is as following list.\n 0 1 read-write P3_MFP1 P3.1 Multi-function Selection\nBits P3_ALT[1] and P3_MFP[1] determine the P3.1 function.\n(P3_ALT[1], P3_MFP[1]) value and function mapping is as following list.\n 1 1 read-write P3_MFP2 P3.2 Multi-function Selection\n 2 1 read-write 0 The GPIO P3.2 is selected #0 1 The INT0 function is selected #1 P3_MFP3 P3.3 Multi-function Selection\n 3 1 read-write 0 The GPIO P3.3 is selected #0 1 The INT1 function is selected #1 P3_MFP4 P3.4 Multi-function Selection\nBits P3_ALT[4] and P3_MFP[4] determine the P3.4 function.\n(P3_ALT[4], P3_MFP[4]) value and function mapping is as following list.\n 4 1 read-write P3_MFP5 P3.5 Multi-function Selection\nBits P3_ALT[5] and P3_MFP[5] determine the P3.5 function.\n(P3_ALT[5], P3_MFP[5]) value and function mapping is as following list.\n 5 1 read-write P3_MFP6 P3.6 Multi-function Selection\nShould be 0 for GPIO P3.6. 6 1 read-write P3_MFP7 P3.7 Multi-function Selection\nShould be 0 for GPIO P3.7. 7 1 read-write P3_TYPE Port 3 Schmitt Trigger Input Enable Bit\n 16 8 read-write 0 Port 3 bit m Schmitt trigger input function Disabled 0 1 Port 3 bit m Schmitt trigger input function Enabled 1 P4_MFP P4_MFP P4 Multiple Function and Input Type Control Register 0x40 read-write n 0x0 0x0 P4_ALT P4.6 Alternative Function\nSee P4_MFP[6]. 14 1 read-write P4_MFP0 P4.0 Multi-function Selection\n 0 1 read-write 0 The GPIO P4.0 is selected #0 1 The ECAP1_IC0 function is selected #1 P4_MFP1 P4.1 Multi-function Selection\n 1 1 read-write 0 The GPIO P4.1 is selected #0 1 The ECAP1_IC1 function is selected #1 P4_MFP2 P4.2 Multi-function Selection\n 2 1 read-write 0 The GPIO P4.2 is selected #0 1 The ECAP1_IC2 function is selected #1 P4_MFP4 P4.4 Multi-function Selection\n 4 1 read-write 0 The GPIO P4.4 is selected #0 1 Reserved #1 P4_MFP5 P4.5 Multi-function Selection\n 5 1 read-write 0 The GPIO P4.5 is selected #0 1 Reserved #1 P4_MFP6 P4.6 Multi-function Selection\nBits P4_ALT[6] and P4_MFP[6] determine the P4.6 function.\n(P4_ALT[6], P4_MFP[6]) value and function mapping is as following list.\n 6 1 read-write P4_MFP7 P4.7 Multi-function Selection\n 7 1 read-write 0 The GPIO P4.7 is selected #0 1 The TM3 function is selected #1 P4_TYPE Port 4 Schmitt Trigger Input Enable Bit\n 16 8 read-write 0 Port 4 bit m Schmitt trigger input function Disabled 0 1 Port 4 bit m Schmitt trigger input function Enabled 1 P5_MFP P5_MFP P5 Multiple Function and Input Type Control Register 0x44 read-write n 0x0 0x0 P5_ALT0 P5.0 Alternative Function\nSee P5_MFP[0]. 8 1 read-write P5_ALT1 P5.1 Alternative Function\nSee P5_MFP[1]. 9 1 read-write P5_ALT2 P5.2 Alternative Function\nSee P5_MFP[2]. 10 1 read-write P5_MFP0 P5.0 Multi-function Selection\nThis bit combined with P5_ALT[0] selects P5.0 multi-function.\nBits P5_ALT[0] and P5_MFP[0] determine the P5.0 function.\n(P5_ALT[0], P5_MFP[0]) value and function mapping is as following list.\n 0 1 read-write P5_MFP1 P5.1 Multi-function Selection\nBits P5_ALT[1] and P5_MFP[1] determine the P5.1 function.\n(P5_ALT[1], P5_MFP[1]) value and function mapping is as following list.\n 1 1 read-write P5_MFP2 P5.2 Multi-function Selection\nBits P5_ALT[2] and P5_MFP[2] determine the P5.2 function.\n(P5_ALT[2], P5_MFP[2]) value and function mapping is as following list.\n 2 1 read-write P5_MFP3 P5.3 Multi-function Selection\n 3 1 read-write 0 The GPIO P5.3 is selected #0 1 The SPI2_CLK function is selected #1 P5_MFP4 P5.4 Multi-function Selection\n 4 1 read-write 0 The GPIO P5.4 is selected #0 1 The SPI2_SS function is selected #1 P5_MFP5 P5.5 Multi-function Selection\n 5 1 read-write 0 The GPIO P5.5 is selected #0 1 The CLKO function is selected #1 P5_MFP6 P5.6 Multi-function Selection\n 6 1 read-write 0 The GPIO P5.6 is selected #0 1 The BPWM0_CH0 function is selected #1 P5_MFP7 P5.7 Multi-function Selection\n 7 1 read-write 0 The GPIO P5.7 is selected #0 1 The BPWM0_CH1 function is selected #1 P5_TYPE Port 5 Schmitt Trigger Input Enable Bit\n 16 8 read-write 0 Port 5 bit m Schmitt trigger input function Disabled 0 1 Port 5 bit m Schmitt trigger input function Enabled 1 P6_MFP P6_MFP P6 Multiple Function and Input Type Control Register 0x48 read-write n 0x0 0x0 P6_MFP0 P6.0 Multi-function Selection\n 0 1 read-write 0 The GPIO P6.0 is selected #0 1 The EADC0_CH0 function is selected #1 P6_MFP1 P6.1 Multi-function Selection\n 1 1 read-write 0 The GPIO P6.1 is selected #0 1 The EADC0_CH1 function is selected #1 P6_MFP2 P6.2 Multi-function Selection\n 2 1 read-write 0 The GPIO P6.2 is selected #0 1 The EADC0_CH2 function is selected #1 P6_MFP3 P6.3 Multi-function Selection\n 3 1 read-write 0 The GPIO P6.3 is selected #0 1 The EADC0_CH3 function is selected #1 P6_MFP4 P6.4 Multi-function Selection\n 4 1 read-write 0 The GPIO P6.4 is selected #0 1 The EADC0_CH4 or ACMP1_N function is selected #1 P6_MFP5 P6.5 Multi-function Selection\n 5 1 read-write 0 The GPIO P6.5 is selected #0 1 The EADC0_CH5 or ACMP1_P function is selected #1 P6_MFP6 P6.6 Multi-function Selection\n 6 1 read-write 0 The GPIO P6.6 is selected #0 1 The EADC0_CH6 function is selected #1 P6_MFP7 P6.7 Multi-function Selection\n 7 1 read-write 0 The GPIO P6.7 is selected #0 1 The EADC0_CH7 function is selected #1 P6_TYPE Port 6 Schmitt Trigger Input Enable Bit\n 16 8 read-write 0 Port 6 bit m Schmitt trigger input function Disabled 0 1 Port 6 bit m Schmitt trigger input function Enabled 1 P7_MFP P7_MFP P7 Multiple Function and Input Type Control Register 0x4C read-write n 0x0 0x0 P7_MFP0 P7.0 Multi-function Selection\n 0 1 read-write 0 The GPIO P7.0 is selected #0 1 The EADC1_CH0 function is selected #1 P7_MFP1 P7.1 Multi-function Selection\n 1 1 read-write 0 The GPIO P7.1 is selected #0 1 The EADC1_CH1 function is selected #1 P7_MFP2 P7.2 Multi-function Selection\n 2 1 read-write 0 The GPIO P7.2 is selected #0 1 The EADC1_CH2 function is selected #1 P7_MFP3 P7.3 Multi-function Selection\n 3 1 read-write 0 The GPIO P7.3 is selected #0 1 The EADC1_CH3 function is selected #1 P7_MFP4 P7.4 Multi-function Selection\n 4 1 read-write 0 The GPIO P7.4 is selected #0 1 The EADC1_CH4 or ACMP2_N function is selected #1 P7_MFP5 P7.5 Multi-function Selection\n 5 1 read-write 0 The GPIO P7.5 is selected #0 1 The EADC1_CH5 or ACMP2_P function is selected #1 P7_MFP6 P7.6 Multi-function Selection\n 6 1 read-write 0 The GPIO P7.6 is selected #0 1 The EADC1_CH6 function is selected #1 P7_MFP7 P7.7 Multi-function Selection\n 7 1 read-write 0 The GPIO P7.7 is selected #0 1 The EADC1_CH7 function is selected #1 P7_TYPE Port 7 Schmitt Trigger Input Enable Bit\n 16 8 read-write 0 Port 7 bit m Schmitt trigger input function Disabled 0 1 Port 7 bit m Schmitt trigger input function Enabled 1 P8_MFP P8_MFP P8 Multiple Function and Input Type Control Register 0x50 read-write n 0x0 0x0 P8_MFP0 P8.0 Multi-function Selection\n 0 1 read-write 0 The GPIO P8.0 is selected #0 1 The OP0_P function is selected #1 P8_MFP1 P8.1 Multi-function Selection\n 1 1 read-write 0 The GPIO P8.1 is selected #0 1 The OP0_N function is selected #1 P8_MFP2 P8.2 Multi-function Selection\n 2 1 read-write 0 The GPIO P8.2 is selected #0 1 The OP0_O function is selected #1 P8_MFP3 P8.3 Multi-function Selection\n 3 1 read-write 0 The GPIO P8.3 is selected #0 1 The ACMP0_N function is selected #1 P8_MFP4 P8.4 Multi-function Selection\n 4 1 read-write 0 The GPIO P8.4 is selected #0 1 The ACMP0_P function is selected #1 P8_MFP7 P8.7 Multi-function Selection\n 7 1 read-write 0 The GPIO P8.7 is selected #0 1 The ACMP0_O function is selected #1 P8_TYPE Port 8 Schmitt Trigger Input Enable Bits\n 16 8 read-write 0 Port 8 bit m Schmitt trigger input function Disabled 0 1 Port 8 bit m Schmitt trigger input function Enabled 1 P9_MFP P9_MFP P9 Multiple Function and Input Type Control Register 0x54 read-write n 0x0 0x0 P9_MFP0 P9.0 Multi-function Selection\n 0 1 read-write 0 The GPIO P9.0 is selected #0 1 The OP1_O function is selected #1 P9_MFP1 P9.1 Multi-function Selection\n 1 1 read-write 0 The GPIO P9.1 is selected #0 1 The OP1_N function is selected #1 P9_MFP2 P9.2 Multi-function Selection\n 2 1 read-write 0 The GPIO P9.2 is selected #0 1 The OP1_P function is selected #1 P9_MFP3 P9.3 Multi-function Selection\n 3 1 read-write 0 The GPIO P9.3 is selected #0 1 The EPWM1_BRAKE1 function is selected #1 P9_MFP4 P9.4 Multi-function Selection\n 4 1 read-write 0 The GPIO P9.4 is selected #0 1 The SPI1_CLK function is selected #1 P9_MFP5 P9.5 Multi-function Selection\n 5 1 read-write 0 The GPIO P9.5 is selected #0 1 The SPI1_MISO function is selected #1 P9_MFP6 P9.6 Multi-function Selection\n 6 1 read-write 0 The GPIO P9.6 is selected #0 1 The SPI1_MOSI function is selected #1 P9_MFP7 P9.7 Multi-function Selection\n 7 1 read-write 0 The GPIO P9.7 is selected #0 1 The SPI1_SS function is selected #1 P9_TYPE Port 9 Schmitt Trigger Input Enable Bits\n 16 8 read-write 0 Port 9 bit m Schmitt trigger input function Disabled 0 1 Port 9 bit m Schmitt trigger input function Enabled 1 PA_MFP PA_MFP PA Multiple Function and Input Type Control Register 0x58 read-write n 0x0 0x0 PA_ALT0 PA.0 Alternative Function\nSee PA_MFP[0]. 8 1 read-write PA_ALT1 PA.1 Alternative Function\nSee PA_MFP[1]. 9 1 read-write PA_MFP0 PA.0 Multi-function Selection\nBits PA_ALT[0] and PA_MFP[0] determine the PA.0 function.\n(PA_ALT[0], PA_MFP[0]) value and function mapping is as following list.\n 0 1 read-write PA_MFP1 PA.1 Multi-function Selection\nBits PA_ALT[1] and PA_MFP[1] determine the PA.1 function.\n(PA_ALT[1], PA_MFP[1]) value and function mapping is as following list.\n 1 1 read-write PA_TYPE Port a Schmitt Trigger Input Enable Bits\n 16 8 read-write 0 Port A bit m Schmitt trigger input function Disabled 0 1 Port A bit m Schmitt trigger input function Enabled 1 PDID PDID Part Device Identification Number Register 0x0 -1 read-only n 0x0 0x0 PDID Part Device Identification Number\nThis register reflects device part number code. Software can read this register to identify which device is used. 0 32 read-only PORCR PORCR Power-on Reset Controller Register 0x24 read-write n 0x0 0x0 POR_DIS_CODE Power-on Reset Enable Bits (Write Protect)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will be active again when this field is set to another value or chip is reset by other reset source, including:\nnRESET, Watchdog Timer reset, Window Watchdog Timer reset, LVR reset, BOD reset, ICE reset command and the software-chip reset function.\nNote: This bit is write protected. Refer to the REGWRPROT register. 0 16 read-write REGWRPROT REGWRPROT Register Write-protection Control Register 0x100 read-write n 0x0 0x0 REGPROTDIS Register Write-protection Disable Index (Read Only)\nNote: This bit is write protected bit. Refer to the REGWRPROT register.\nPlease refer to Table 6-3 The protected register table. 0 1 read-only 0 Write-protection Enabled for writing protected registers. Any write to the protected register is ignored #0 1 Write-protection Disabled for writing protected registers #1 REGWRPROT Register Write-protection Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write. 1 7 write-only RSTSRC RSTSRC System Reset Source Register 0x4 read-write n 0x0 0x0 RSTS_BOD Brown-out Detector Reset Flag The RSTS_BOD flag is set by the Reset Signal from the Brown-out Detector to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 4 1 read-write 0 No reset from BOD #0 1 The BOD had issued the reset signal to reset the system #1 RSTS_CPU CPU Reset Flag\nThe RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC).\nNote: Write 1 to clear this bit to 0. 7 1 read-write 0 No reset from CPU #0 1 Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST(IPRSTC1[1]) to 1 #1 RSTS_LVR Low Voltage Reset Flag The RSTS_LVR flag is set by the Reset Signal from the Low-Voltage-Reset controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 3 1 read-write 0 No reset from LVR #0 1 The LVR controller had issued the reset signal to reset the system #1 RSTS_POR Power-on Reset Flag The RSTS_POR flag is set by the Reset Signal from the Power-on Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 0 1 read-write 0 No reset from POR or CHIP_RST (IPRSTC1[0]) #0 1 Power-on Reset (POR) or CHIP_RST (IPRSTC1[0]) had issued the reset signal to reset the system #1 RSTS_RESET Reset Pin Reset Flag The RSTS_RESET flag is set by the Reset Signal from the nRESET pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 1 1 read-write 0 No reset from the nRESET pin #0 1 The nRESET pin had issued the reset signal to reset the system #1 RSTS_SYS SYS Reset Flag The RSTS_SYS flag is set by the Reset Signal from the Cortex-M0 kernel to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 5 1 read-write 0 No reset from Cortex-M0 #0 1 The Cortex-M0 had issued the reset signal to reset the system by writing 1 to bit SYSRESETREQ (AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core #1 RSTS_WDT Watchdog Timer Reset Flag The RSTS_WDT flag is set by the Reset Signal from the watchdog timer or window watchdog timer to indicate the previous reset source. Note1: Write 1 to clear this bit to 0. Note2: Watchdog Timer register WTRF(WTCR[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDTSR) bit is set if the system has been reset by WWDT time-out reset. 2 1 read-write 0 No reset from watchdog timer or window watchdog timer #0 1 The watchdog timer or window watchdog timer had issued the reset signal to reset the system #1 TEMPCR TEMPCR Temperature Sensor Control Register 0x1C read-write n 0x0 0x0 VTEMP_EN Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1, the value of temperature sensor output can be obtained from the ADC conversion result. Please refer to the EADC chapter for detailed ADC conversion functional description. 0 1 read-write 0 Temperature sensor function Disabled (default) #0 1 Temperature sensor function Enabled #1 GPIO GPIO Register Map GPIO 0x0 0x0 0x24 registers n 0x100 0x24 registers n 0x140 0x24 registers n 0x180 0x20 registers n 0x1C0 0x24 registers n 0x200 0x24 registers n 0x240 0x24 registers n 0x280 0x24 registers n 0x2E0 0x8 registers n 0x300 0x148 registers n 0x40 0x24 registers n 0x80 0x24 registers n 0xC0 0x24 registers n DBNCECON DBNCECON External Interrupt De-bounce Control 0x2E0 read-write n 0x0 0x0 DBCLKSEL De-bounce Sampling Cycle Selection\n 0 4 read-write 0 Sample interrupt input once per 1 clocks #0000 1 Sample interrupt input once per 2 clocks #0001 2 Sample interrupt input once per 4 clocks #0010 3 Sample interrupt input once per 8 clocks #0011 4 Sample interrupt input once per 16 clocks #0100 5 Sample interrupt input once per 32 clocks #0101 6 Sample interrupt input once per 64 clocks #0110 7 Sample interrupt input once per 128 clocks #0111 8 Sample interrupt input once per 256 clocks #1000 9 Sample interrupt input once per 2*256 clocks #1001 10 Sample interrupt input once per 4*256 clocks #1010 11 Sample interrupt input once per 8*256 clocks #1011 12 Sample interrupt input once per 16*256 clocks #1100 13 Sample interrupt input once per 32*256 clocks #1101 14 Sample interrupt input once per 64*256 clocks #1110 15 Sample interrupt input once per 128*256 clocks #1111 DBCLKSRC De-bounce Counter Clock Source Selection\n 4 1 read-write 0 De-bounce counter clock source is the HCLK #0 1 De-bounce counter clock source is the internal 10 kHz low speed oscillator #1 ICLK_ON Interrupt Clock on Mode\nIt is recommended to turn off this bit to save system power if no special application concern. 5 1 read-write 0 Edge detection circuit is active only if I/O pin corresponding Px_IEN bit is set to 1 #0 1 All I/O pins edge detection circuit is always active after reset #1 P0_0 P0_0 GPIO P0.n Pin Data Input/Output 0x300 read-write n 0x0 0x0 Pxn GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing P0_0 will reflect the written value to bit P0_DOUT[0], read P0_0 will return the value of P0_PIN[0].\nNote: The write operation will not be affected by register Px_DMASK. 0 1 read-write 0 Corresponding GPIO pin set to low #0 1 Corresponding GPIO pin set to high #1 P0_1 P0_1 GPIO P0.n Pin Data Input/Output 0x304 read-write n 0x0 0x0 P0_2 P0_2 GPIO P0.n Pin Data Input/Output 0x308 read-write n 0x0 0x0 P0_3 P0_3 GPIO P0.n Pin Data Input/Output 0x30C read-write n 0x0 0x0 P0_4 P0_4 GPIO P0.n Pin Data Input/Output 0x310 read-write n 0x0 0x0 P0_5 P0_5 GPIO P0.n Pin Data Input/Output 0x314 read-write n 0x0 0x0 P0_6 P0_6 GPIO P0.n Pin Data Input/Output 0x318 read-write n 0x0 0x0 P0_7 P0_7 GPIO P0.n Pin Data Input/Output 0x31C read-write n 0x0 0x0 P0_DBEN P0_DBEN GPIO Port 0 De-bounce Enable 0x14 read-write n 0x0 0x0 DBEN Port 0-a Input Signal De-bounce Enable Bits\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (DBNCECON[4]), one de-bounce sample cycle period is controlled by DBCLKSEL (DBNCECON[3:0]).\n 0 8 read-write 0 Bit[n] de-bounce function Disabled 0 1 Bit[n] de-bounce function Enabled 1 P0_DMASK P0_DMASK GPIO Port 0 Data Output Write Mask 0xC read-write n 0x0 0x0 DMASK Port 0-a Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] is set to 1, the corresponding Px_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 0 8 read-write 0 Corresponding Px_DOUT[n] bit can be updated 0 1 Corresponding Px_DOUT[n] bit protected 1 P0_DOUT P0_DOUT GPIO Port 0 Data Output Value 0x8 -1 read-write n 0x0 0x0 DOUT Port 0-a Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n 0 8 read-write 0 GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode 0 1 GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode 1 P0_IEN P0_IEN GPIO Port 0 Interrupt Enable 0x1C read-write n 0x0 0x0 IF_EN Port 0-a Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input Px_PIN[n]. Set bit to 1 also enable the pin wake-up function. When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 0 8 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled 0 1 PIN[n] state low-level or high-to-low change interrupt Enabled 1 IR_EN Port 0-a Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px_PIN[n]. Set bit to 1 also enable the pin wake-up function. When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 16 8 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled 0 1 PIN[n] level-high or low-to-high interrupt Enabled 1 P0_IMD P0_IMD GPIO Port 0 Interrupt Mode Control 0x18 read-write n 0x0 0x0 IMD Port 0-a Edge or Level Detection Interrupt Control\nIMD[n] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 0 8 read-write 0 Edge triggered interrupt 0 1 Level triggered interrupt 1 P0_ISF P0_ISF GPIO Port 0 Interrupt Source Flag 0x20 read-write n 0x0 0x0 IF_ISF Port 0-a Interrupt Source Flag\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :\n 0 8 read-write 0 No interrupt at Px[n].\nNo action 0 1 Px[n] generates an interrupt.\nClear the corresponding pending interrupt 1 P0_OFFD P0_OFFD GPIO Port 0 Pin Digital Input Path Disable Control 0x4 read-write n 0x0 0x0 OFFD Port 0-a Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid input current leakage.\n 16 8 read-write 0 I/O digital input path Enabled 0 1 I/O digital input path Disabled (digital input tied to low) 1 P0_PIN P0_PIN GPIO Port 0 Pin Value 0x10 read-only n 0x0 0x0 PIN Port 0-a Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\n 0 8 read-only P0_PMD P0_PMD GPIO Port 0 Pin I/O Mode Control 0x0 read-write n 0x0 0x0 PMD0 Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n 0 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD1 Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n 2 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD2 Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n 4 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD3 Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n 6 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD4 Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n 8 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD5 Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n 10 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD6 Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n 12 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD7 Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n 14 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 P1_0 P1_0 GPIO P1.n Pin Data Input/Output 0x320 read-write n 0x0 0x0 P1_1 P1_1 GPIO P1.n Pin Data Input/Output 0x324 read-write n 0x0 0x0 P1_2 P1_2 GPIO P1.n Pin Data Input/Output 0x328 read-write n 0x0 0x0 P1_3 P1_3 GPIO P1.n Pin Data Input/Output 0x32C read-write n 0x0 0x0 P1_4 P1_4 GPIO P1.n Pin Data Input/Output 0x330 read-write n 0x0 0x0 P1_5 P1_5 GPIO P1.n Pin Data Input/Output 0x334 read-write n 0x0 0x0 P1_6 P1_6 GPIO P1.n Pin Data Input/Output 0x338 read-write n 0x0 0x0 P1_7 P1_7 GPIO P1.n Pin Data Input/Output 0x33C read-write n 0x0 0x0 P1_DBEN P1_DBEN GPIO Port 1 De-bounce Enable 0x54 read-write n 0x0 0x0 P1_DMASK P1_DMASK GPIO Port 1 Data Output Write Mask 0x4C read-write n 0x0 0x0 P1_DOUT P1_DOUT GPIO Port 1 Data Output Value 0x48 read-write n 0x0 0x0 P1_IEN P1_IEN GPIO Port 1 Interrupt Enable 0x5C read-write n 0x0 0x0 P1_IMD P1_IMD GPIO Port 1 Interrupt Mode Control 0x58 read-write n 0x0 0x0 P1_ISF P1_ISF GPIO Port 1 Interrupt Source Flag 0x60 read-write n 0x0 0x0 P1_OFFD P1_OFFD GPIO Port 1 Pin Digital Input Path Disable Control 0x44 read-write n 0x0 0x0 P1_PIN P1_PIN GPIO Port 1 Pin Value 0x50 read-write n 0x0 0x0 P1_PMD P1_PMD GPIO Port 1 Pin I/O Mode Control 0x40 read-write n 0x0 0x0 P2_0 P2_0 GPIO P2.n Pin Data Input/Output 0x340 read-write n 0x0 0x0 P2_1 P2_1 GPIO P2.n Pin Data Input/Output 0x344 read-write n 0x0 0x0 P2_2 P2_2 GPIO P2.n Pin Data Input/Output 0x348 read-write n 0x0 0x0 P2_3 P2_3 GPIO P2.n Pin Data Input/Output 0x34C read-write n 0x0 0x0 P2_4 P2_4 GPIO P2.n Pin Data Input/Output 0x350 read-write n 0x0 0x0 P2_5 P2_5 GPIO P2.n Pin Data Input/Output 0x354 read-write n 0x0 0x0 P2_6 P2_6 GPIO P2.n Pin Data Input/Output 0x358 read-write n 0x0 0x0 P2_7 P2_7 GPIO P2.n Pin Data Input/Output 0x35C read-write n 0x0 0x0 P2_DBEN P2_DBEN GPIO Port 2 De-bounce Enable 0x94 read-write n 0x0 0x0 P2_DMASK P2_DMASK GPIO Port 2 Data Output Write Mask 0x8C read-write n 0x0 0x0 P2_DOUT P2_DOUT GPIO Port 2 Data Output Value 0x88 read-write n 0x0 0x0 P2_IEN P2_IEN GPIO Port 2 Interrupt Enable 0x9C read-write n 0x0 0x0 P2_IMD P2_IMD GPIO Port 2 Interrupt Mode Control 0x98 read-write n 0x0 0x0 P2_ISF P2_ISF GPIO Port 2 Interrupt Source Flag 0xA0 read-write n 0x0 0x0 P2_OFFD P2_OFFD GPIO Port 2 Pin Digital Input Path Disable Control 0x84 read-write n 0x0 0x0 P2_PIN P2_PIN GPIO Port 2 Pin Value 0x90 read-write n 0x0 0x0 P2_PMD P2_PMD GPIO Port 2 Pin I/O Mode Control 0x80 read-write n 0x0 0x0 P3_0 P3_0 GPIO P3.n Pin Data Input/Output 0x360 read-write n 0x0 0x0 P3_1 P3_1 GPIO P3.n Pin Data Input/Output 0x364 read-write n 0x0 0x0 P3_2 P3_2 GPIO P3.n Pin Data Input/Output 0x368 read-write n 0x0 0x0 P3_3 P3_3 GPIO P3.n Pin Data Input/Output 0x36C read-write n 0x0 0x0 P3_4 P3_4 GPIO P3.n Pin Data Input/Output 0x370 read-write n 0x0 0x0 P3_5 P3_5 GPIO P3.n Pin Data Input/Output 0x374 read-write n 0x0 0x0 P3_6 P3_6 GPIO P3.n Pin Data Input/Output 0x378 read-write n 0x0 0x0 P3_7 P3_7 GPIO P3.n Pin Data Input/Output 0x37C read-write n 0x0 0x0 P3_DBEN P3_DBEN GPIO Port 3 De-bounce Enable 0xD4 read-write n 0x0 0x0 P3_DMASK P3_DMASK GPIO Port 3 Data Output Write Mask 0xCC read-write n 0x0 0x0 P3_DOUT P3_DOUT GPIO Port 3 Data Output Value 0xC8 read-write n 0x0 0x0 P3_IEN P3_IEN GPIO Port 3 Interrupt Enable 0xDC read-write n 0x0 0x0 P3_IMD P3_IMD GPIO Port 3 Interrupt Mode Control 0xD8 read-write n 0x0 0x0 P3_ISF P3_ISF GPIO Port 3 Interrupt Source Flag 0xE0 read-write n 0x0 0x0 P3_OFFD P3_OFFD GPIO Port 3 Pin Digital Input Path Disable Control 0xC4 read-write n 0x0 0x0 P3_PIN P3_PIN GPIO Port 3 Pin Value 0xD0 read-write n 0x0 0x0 P3_PMD P3_PMD GPIO Port 3 Pin I/O Mode Control 0xC0 read-write n 0x0 0x0 P4_0 P4_0 GPIO P4.n Pin Data Input/Output 0x380 read-write n 0x0 0x0 P4_1 P4_1 GPIO P4.n Pin Data Input/Output 0x384 read-write n 0x0 0x0 P4_2 P4_2 GPIO P4.n Pin Data Input/Output 0x388 read-write n 0x0 0x0 P4_3 P4_3 GPIO P4.n Pin Data Input/Output 0x38C read-write n 0x0 0x0 P4_4 P4_4 GPIO P4.n Pin Data Input/Output 0x390 read-write n 0x0 0x0 P4_5 P4_5 GPIO P4.n Pin Data Input/Output 0x394 read-write n 0x0 0x0 P4_6 P4_6 GPIO P4.n Pin Data Input/Output 0x398 read-write n 0x0 0x0 P4_7 P4_7 GPIO P4.n Pin Data Input/Output 0x39C read-write n 0x0 0x0 P4_DBEN P4_DBEN GPIO Port 4 De-bounce Enable 0x114 read-write n 0x0 0x0 P4_DMASK P4_DMASK GPIO Port 4 Data Output Write Mask 0x10C read-write n 0x0 0x0 P4_DOUT P4_DOUT GPIO Port 4 Data Output Value 0x108 read-write n 0x0 0x0 P4_IEN P4_IEN GPIO Port 4 Interrupt Enable 0x11C read-write n 0x0 0x0 P4_IMD P4_IMD GPIO Port 4 Interrupt Mode Control 0x118 read-write n 0x0 0x0 P4_ISF P4_ISF GPIO Port 4 Interrupt Source Flag 0x120 read-write n 0x0 0x0 P4_OFFD P4_OFFD GPIO Port 4 Pin Digital Input Path Disable Control 0x104 read-write n 0x0 0x0 P4_PIN P4_PIN GPIO Port 4 Pin Value 0x110 read-write n 0x0 0x0 P4_PMD P4_PMD GPIO Port 4 Pin I/O Mode Control 0x100 read-write n 0x0 0x0 P5_0 P5_0 GPIO P5.n Pin Data Input/Output 0x3A0 read-write n 0x0 0x0 P5_1 P5_1 GPIO P5.n Pin Data Input/Output 0x3A4 read-write n 0x0 0x0 P5_2 P5_2 GPIO P5.n Pin Data Input/Output 0x3A8 read-write n 0x0 0x0 P5_3 P5_3 GPIO P5.n Pin Data Input/Output 0x3AC read-write n 0x0 0x0 P5_4 P5_4 GPIO P5.n Pin Data Input/Output 0x3B0 read-write n 0x0 0x0 P5_5 P5_5 GPIO P5.n Pin Data Input/Output 0x3B4 read-write n 0x0 0x0 P5_6 P5_6 GPIO P5.n Pin Data Input/Output 0x3B8 read-write n 0x0 0x0 P5_7 P5_7 GPIO P5.n Pin Data Input/Output 0x3BC read-write n 0x0 0x0 P5_DBEN P5_DBEN GPIO Port 5 De-bounce Enable 0x154 read-write n 0x0 0x0 P5_DMASK P5_DMASK GPIO Port 5 Data Output Write Mask 0x14C read-write n 0x0 0x0 P5_DOUT P5_DOUT GPIO Port 5 Data Output Value 0x148 read-write n 0x0 0x0 P5_IEN P5_IEN GPIO Port 5 Interrupt Enable 0x15C read-write n 0x0 0x0 P5_IMD P5_IMD GPIO Port 5 Interrupt Mode Control 0x158 read-write n 0x0 0x0 P5_ISF P5_ISF GPIO Port 5 Interrupt Source Flag 0x160 read-write n 0x0 0x0 P5_OFFD P5_OFFD GPIO Port 5 Pin Digital Input Path Disable Control 0x144 read-write n 0x0 0x0 P5_PIN P5_PIN GPIO Port 5 Pin Value 0x150 read-write n 0x0 0x0 P5_PMD P5_PMD GPIO Port 5 Pin I/O Mode Control 0x140 read-write n 0x0 0x0 P6_0 P6_0 GPIO P6.n Pin Data Input/Output 0x3C0 read-write n 0x0 0x0 P6_1 P6_1 GPIO P6.n Pin Data Input/Output 0x3C4 read-write n 0x0 0x0 P6_2 P6_2 GPIO P6.n Pin Data Input/Output 0x3C8 read-write n 0x0 0x0 P6_3 P6_3 GPIO P6.n Pin Data Input/Output 0x3CC read-write n 0x0 0x0 P6_4 P6_4 GPIO P6.n Pin Data Input/Output 0x3D0 read-write n 0x0 0x0 P6_5 P6_5 GPIO P6.n Pin Data Input/Output 0x3D4 read-write n 0x0 0x0 P6_6 P6_6 GPIO P6.n Pin Data Input/Output 0x3D8 read-write n 0x0 0x0 P6_7 P6_7 GPIO P6.n Pin Data Input/Output 0x3DC read-write n 0x0 0x0 P6_DBEN P6_DBEN GPIO Port 6 De-bounce Enable 0x194 read-write n 0x0 0x0 P6_DMASK P6_DMASK GPIO Port 6 Data Output Write Mask 0x18C read-write n 0x0 0x0 P6_DOUT P6_DOUT GPIO Port 6 Data Output Value 0x188 read-write n 0x0 0x0 P6_IEN P6_IEN GPIO Port 6 Interrupt Enable 0x19C read-write n 0x0 0x0 P6_IMD P6_IMD GPIO Port 6 Interrupt Mode Control 0x198 read-write n 0x0 0x0 P6_ISF P6_ISF GPIO Port 6 Interrupt Source Flag 0x200 read-write n 0x0 0x0 P6_OFFD P6_OFFD GPIO Port 6 Pin Digital Input Path Disable Control 0x184 read-write n 0x0 0x0 P6_PIN P6_PIN GPIO Port 6 Pin Value 0x190 read-write n 0x0 0x0 P6_PMD P6_PMD GPIO Port 6 Pin I/O Mode Control 0x180 read-write n 0x0 0x0 P7_0 P7_0 GPIO P7.n Pin Data Input/Output 0x3E0 read-write n 0x0 0x0 P7_1 P7_1 GPIO P7.n Pin Data Input/Output 0x3E4 read-write n 0x0 0x0 P7_2 P7_2 GPIO P7.n Pin Data Input/Output 0x3E8 read-write n 0x0 0x0 P7_3 P7_3 GPIO P7.n Pin Data Input/Output 0x3EC read-write n 0x0 0x0 P7_4 P7_4 GPIO P7.n Pin Data Input/Output 0x3F0 read-write n 0x0 0x0 P7_5 P7_5 GPIO P7.n Pin Data Input/Output 0x3F4 read-write n 0x0 0x0 P7_6 P7_6 GPIO P7.n Pin Data Input/Output 0x3F8 read-write n 0x0 0x0 P7_7 P7_7 GPIO P7.n Pin Data Input/Output 0x3FC read-write n 0x0 0x0 P7_DBEN P7_DBEN GPIO Port 7 De-bounce Enable 0x1D4 read-write n 0x0 0x0 P7_DMASK P7_DMASK GPIO Port 7 Data Output Write Mask 0x1CC read-write n 0x0 0x0 P7_DOUT P7_DOUT GPIO Port 7 Data Output Value 0x1C8 read-write n 0x0 0x0 P7_IEN P7_IEN GPIO Port 7 Interrupt Enable 0x1DC read-write n 0x0 0x0 P7_IMD P7_IMD GPIO Port 7 Interrupt Mode Control 0x1D8 read-write n 0x0 0x0 P7_ISF P7_ISF GPIO Port 7 Interrupt Source Flag 0x1E0 read-write n 0x0 0x0 P7_OFFD P7_OFFD GPIO Port 7 Pin Digital Input Path Disable Control 0x1C4 read-write n 0x0 0x0 P7_PIN P7_PIN GPIO Port 7 Pin Value 0x1D0 read-write n 0x0 0x0 P7_PMD P7_PMD GPIO Port 7 Pin I/O Mode Control 0x1C0 read-write n 0x0 0x0 P8_0 P8_0 GPIO P8.n Pin Data Input/Output 0x400 read-write n 0x0 0x0 P8_1 P8_1 GPIO P8.n Pin Data Input/Output 0x404 read-write n 0x0 0x0 P8_2 P8_2 GPIO P8.n Pin Data Input/Output 0x408 read-write n 0x0 0x0 P8_3 P8_3 GPIO P8.n Pin Data Input/Output 0x40C read-write n 0x0 0x0 P8_4 P8_4 GPIO P8.n Pin Data Input/Output 0x410 read-write n 0x0 0x0 P8_5 P8_5 GPIO P8.n Pin Data Input/Output 0x414 read-write n 0x0 0x0 P8_6 P8_6 GPIO P8.n Pin Data Input/Output 0x418 read-write n 0x0 0x0 P8_7 P8_7 GPIO P8.n Pin Data Input/Output 0x41C read-write n 0x0 0x0 P8_DBEN P8_DBEN GPIO Port 8 De-bounce Enable 0x214 read-write n 0x0 0x0 P8_DMASK P8_DMASK GPIO Port 8 Data Output Write Mask 0x20C read-write n 0x0 0x0 P8_DOUT P8_DOUT GPIO Port 8 Data Output Value 0x208 read-write n 0x0 0x0 P8_IEN P8_IEN GPIO Port 8 Interrupt Enable 0x21C read-write n 0x0 0x0 P8_IMD P8_IMD GPIO Port 8 Interrupt Mode Control 0x218 read-write n 0x0 0x0 P8_ISF P8_ISF GPIO Port 8 Interrupt Source Flag 0x220 read-write n 0x0 0x0 P8_OFFD P8_OFFD GPIO Port 8 Pin Digital Input Path Disable Control 0x204 read-write n 0x0 0x0 P8_PIN P8_PIN GPIO Port 8 Pin Value 0x210 read-write n 0x0 0x0 P8_PMD P8_PMD GPIO Port 8 Pin I/O Mode Control P6_ISF 0x200 read-write n 0x0 0x0 P9_0 P9_0 GPIO P9.n Pin Data Input/Output 0x420 read-write n 0x0 0x0 P9_1 P9_1 GPIO P9.n Pin Data Input/Output 0x424 read-write n 0x0 0x0 P9_2 P9_2 GPIO P9.n Pin Data Input/Output 0x428 read-write n 0x0 0x0 P9_3 P9_3 GPIO P9.n Pin Data Input/Output 0x42C read-write n 0x0 0x0 P9_4 P9_4 GPIO P9.n Pin Data Input/Output 0x430 read-write n 0x0 0x0 P9_5 P9_5 GPIO P9.n Pin Data Input/Output 0x434 read-write n 0x0 0x0 P9_6 P9_6 GPIO P9.n Pin Data Input/Output 0x438 read-write n 0x0 0x0 P9_7 P9_7 GPIO P9.n Pin Data Input/Output 0x43C read-write n 0x0 0x0 P9_DBEN P9_DBEN GPIO Port 9 De-bounce Enable 0x254 read-write n 0x0 0x0 P9_DMASK P9_DMASK GPIO Port 9 Data Output Write Mask 0x24C read-write n 0x0 0x0 P9_DOUT P9_DOUT GPIO Port 9 Data Output Value 0x248 read-write n 0x0 0x0 P9_IEN P9_IEN GPIO Port 9 Interrupt Enable 0x25C read-write n 0x0 0x0 P9_IMD P9_IMD GPIO Port 9 Interrupt Mode Control 0x258 read-write n 0x0 0x0 P9_ISF P9_ISF GPIO Port 9 Interrupt Source Flag 0x260 read-write n 0x0 0x0 P9_OFFD P9_OFFD GPIO Port 9 Pin Digital Input Path Disable Control 0x244 read-write n 0x0 0x0 P9_PIN P9_PIN GPIO Port 9 Pin Value 0x250 read-write n 0x0 0x0 P9_PMD P9_PMD GPIO Port 9 Pin I/O Mode Control 0x240 read-write n 0x0 0x0 PA_0 PA_0 GPIO PA.n Pin Data Input/Output 0x440 read-write n 0x0 0x0 PA_1 PA_1 GPIO PA.n Pin Data Input/Output 0x444 read-write n 0x0 0x0 PA_DBEN PA_DBEN GPIO Port A De-bounce Enable 0x294 read-write n 0x0 0x0 PA_DMASK PA_DMASK GPIO Port A Data Output Write Mask 0x28C read-write n 0x0 0x0 PA_DOUT PA_DOUT GPIO Port A Data Output Value 0x288 read-write n 0x0 0x0 PA_IEN PA_IEN GPIO Port A Interrupt Enable 0x29C read-write n 0x0 0x0 PA_IMD PA_IMD GPIO Port A Interrupt Mode Control 0x298 read-write n 0x0 0x0 PA_ISF PA_ISF GPIO Port A Interrupt Source Flag 0x2A0 read-write n 0x0 0x0 PA_OFFD PA_OFFD GPIO Port A Pin Digital Input Path Disable Control 0x284 read-write n 0x0 0x0 PA_PIN PA_PIN GPIO Port A Pin Value 0x290 read-write n 0x0 0x0 PA_PMD PA_PMD GPIO Port A Pin I/O Mode Control 0x280 read-write n 0x0 0x0 PWMPOEN PWMPOEN PWM Port Output Enable 0x2E4 read-write n 0x0 0x0 HZ_BPWM Basic PWM0 Ports Output Control\nNote: The initial value is loaded from CHZ_BPWM (Config0[12]) after any reset. 4 1 read-write 0 The driving mode of Basic PWM ports are controlled by GPIO mode register #0 1 The driving mode of Basic PWM ports are forced in tri-state (Hi-Z) all the time #1 HZ_Even0 Enhanced PWM Unit0 Even Ports Output Control\nNote: The initial value is loaded from CHZ_Even0 (Config0[8]) after any reset. 0 1 read-write 0 The driving mode of Enhanced PWM unit0 even ports are controlled by GPIO mode register (Px_PMD) or multi-function register (Px_MFP) #0 1 The driving mode of Enhanced PWM unit0 even ports are forced in tri-state (Hi-Z) all the time #1 HZ_Even1 Enhanced PWM Unit1 Even Ports Output Control\nNote: The initial value is loaded from CHZ_Even1 (Config0[10]) after any reset. 2 1 read-write 0 The driving mode of Enhanced PWM unit1 even ports are controlled by GPIO mode register (Px_PMD) or multi-function register (Px_MFP) #0 1 The driving mode of Enhanced PWM unit1 even ports are forced in tri-state (Hi-Z) all the time #1 HZ_Odd0 Enhanced PWM Unit0 Odd Ports Output Control\nNote: The initial value is loaded from CHZ_Odd0 (Config0[9]) after any reset. 1 1 read-write 0 The driving mode of Enhanced PWM unit0 odd ports are controlled by GPIO mode register (Px_PMD) or multi-function register (Px_MFP) #0 1 The driving mode of Enhanced PWM unit0 odd ports are forced in tri-state (Hi-Z) all the time #1 HZ_Odd1 Enhanced PWM Unit1 Odd Ports Output Control\nNote: The initial value is loaded from CHZ_Odd1 (Config0[11]) after any reset. 3 1 read-write 0 The driving mode of Enhanced PWM unit1 odd ports are controlled by GPIO mode register (Px_PMD) or multi-function register (Px_MFP) #0 1 The driving mode of Enhanced PWM unit1 odd ports are forced in tri-state (Hi-Z) all the time #1 HDIV HDIV Register Map HDIV 0x0 0x4 0x14 registers n DIVIDEND DIVIDEND Dividend Source Register (Signed 32-bit) 0x4 read-write n 0x0 0x0 Dividend Dividend Source\nThis register is given the dividend (signed 32-bit) of divider before calculation starts. 0 32 read-write DIVISOR DIVISOR Divisor Source Resister (Signed 16-bit) 0x8 -1 read-write n 0x0 0x0 Divisor Divisor Source\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written, hardware divider will start calculation. 0 16 read-write DIVQUO DIVQUO Quotient Result Resister (Signed 32-bit) 0xC read-only n 0x0 0x0 Quotient Quotient Result\nThis register holds the quotient (signed 32-bit) result of divider after calculation completed. 0 32 read-only DIVREM DIVREM Reminder Result Register (Signed 16-bit) 0x10 read-only n 0x0 0x0 Reminder Reminder Result\nThis register holds the reminder (signed 16-bit) result of divider after calculation completed. 0 16 read-only DIVSTS DIVSTS Divider Status Register 0x14 -1 read-write n 0x0 0x0 DIV0 Divisor Zero Warning\nThis register is read only. 1 1 read-write 0 The divisor is not 0 #0 1 The divisor is 0 #1 DIVFF Divider Operation Finish Flag\nWhen divider calculation has finished, this bit is set to 1. This bit is cleared to 0 by writing 1 to it through software 2 1 read-write DIV_FINISH Divider Operation Finished\nThis register is read only. 0 1 read-write 0 The divider calculation not finished yet #0 1 The divider calculation finished #1 I2C0 I2C Register Map I2C 0x0 0x0 0x30 registers n 0x3C 0x8 registers n I2CADDR0 I2CADDR0 I2C Slave Address Register0 0x4 read-write n 0x0 0x0 GC General Call Function\n 0 1 read-write 0 General Call function Disabled #0 1 General Call function Enabled #1 I2CADDR I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched. 1 7 read-write I2CADDR1 I2CADDR1 I2C Slave Address Register1 0x18 read-write n 0x0 0x0 I2CADDR2 I2CADDR2 I2C Slave Address Register2 0x1C read-write n 0x0 0x0 I2CADDR3 I2CADDR3 I2C Slave Address Register3 0x20 read-write n 0x0 0x0 I2CADM0 I2CADM0 I2C Slave Address Mask Register0 0x24 read-write n 0x0 0x0 I2CADM I2C Address Mask Register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to 0, that means the received corresponding register bit should be exact the same as address register.\n 1 7 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 I2CADM1 I2CADM1 I2C Slave Address Mask Register1 0x28 read-write n 0x0 0x0 I2CADM2 I2CADM2 I2C Slave Address Mask Register2 0x2C read-write n 0x0 0x0 I2CADM3 I2CADM3 I2C Slave Address Mask Register3 0x30 read-write n 0x0 0x0 I2CDAT I2CDAT I2C Data Register 0x8 read-write n 0x0 0x0 I2CDAT I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port. 0 8 read-write I2CLK I2CLK I2C Clock Divided Register 0x10 read-write n 0x0 0x0 I2CLK I2C Clock Divided Register\nNote: The minimum value of I2CLK is 4. 0 8 read-write I2CON I2CON I2C Control Register 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control Bit\n 2 1 read-write EI Interrupt Enable Bit\n 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 ENS1 I2C Controller Enable Bit\n 6 1 read-write 0 I2C controller Disabled #0 1 I2C controller Enabled #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit. 3 1 read-write STA I2C START Control Bit\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control Bit In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. 4 1 read-write I2CSTATUS I2CSTATUS I2C Status Register 0xC -1 read-only n 0x0 0x0 I2CSTATUS I2C Status Register\nThe three least significant bits are always 0. The five most significant bits contain the status code. There are 26 possible status codes.\nIn addition, states 00H stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame. Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. 0 8 read-only I2CTOC I2CTOC I2C Time Out Counter Register 0x14 read-write n 0x0 0x0 DIV4 Time-out Counter Input Clock Is Divided by 4\nWhen Enabled, the time out period is extend 4 times.\n 1 1 read-write 0 The time out counter input clock divided by 4 Disabled #0 1 The time out counter input clock divided by 4 Enabled #1 ENTI Time-out Counter Enable Bit\nWhen Enabled, the 14-bit time out counter will start counting when SI is clear. Write 1 to SI flag will reset counter and re-start up counting after SI is cleared.\n 2 1 read-write 0 Time out counter Disabled #0 1 Time out counter Enabled #1 TIF Time-out Flag\nThis bit is set by H/W when I2C time out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write I2CWKUPCON I2CWKUPCON I2C Wake Up Control Register 0x3C read-write n 0x0 0x0 WKUPEN I2C Wake-up Function Enable Bit\n 0 1 read-write 0 I2C wake up function Disabled #0 1 I2C wake up function Enabled #1 I2CWKUPSTS I2CWKUPSTS I2C Wake Up Status Register 0x40 read-write n 0x0 0x0 WKUPIF I2C Wake-up Interrupt Flag\nWhen chip is woken-up from Power-down mode by I2C, this bit is set to 1. \nNote: This bit can be cleared by writing '1' to it. 0 1 read-write INT INT Register Map INT 0x0 0x0 0x44 registers n 0x48 0x8 registers n 0x54 0x14 registers n 0x70 0x1C registers n IRQ0_SRC IRQ0_SRC IRQ0 (BOD) Interrupt Source Identity 0x0 read-only n 0x0 0x0 BOD_INT IRQ0 Source Identity\n 0 1 read-only 0 IRQ0 source is not from BOD interrupt (BOD_INT) #0 1 IRQ0 source is from BOD interrupt (BOD_INT) #1 IRQ10_SRC IRQ10_SRC IRQ10 (TMR2) Interrupt Source Identity 0x28 read-only n 0x0 0x0 TMR2_INT IRQ10 Source Identity \n 0 1 read-only 0 IRQ10 source is not from Timer2 interrupt (TMR2_INT) #0 1 IRQ10 source is from Timer2 interrupt (TMR2_INT) #1 IRQ11_SRC IRQ11_SRC IRQ11 (TMR3) Interrupt Source Identity 0x2C read-only n 0x0 0x0 TMR3_INT IRQ11 Source Identity \n 0 1 read-only 0 IRQ11 source is not from Timer3 interrupt (TMR3_INT) #0 1 IRQ11 source is from Timer3 interrupt (TMR3_INT) #1 IRQ12_SRC IRQ12_SRC IRQ12 (UART0) Interrupt Source Identity 0x30 read-only n 0x0 0x0 UART0_INT IRQ12 Source Identity\n 0 1 read-only 0 IRQ12 source is not from UART0 interrupt (UART0_INT) #0 1 IRQ12 source is from UART0 interrupt (UART0_INT) #1 IRQ13_SRC IRQ13_SRC IRQ13 (UART1) Interrupt Source Identity 0x34 read-only n 0x0 0x0 UART1_INT IRQ13 Source Identity\n 0 1 read-only 0 IRQ13 source is not from UART1 interrupt (UART1_INT) #0 1 IRQ13 source is from UART1 interrupt (UART1_INT) #1 IRQ14_SRC IRQ14_SRC IRQ14 (SPI0) Interrupt Source Identity 0x38 read-only n 0x0 0x0 SPI0_INT IRQ14 Source Identity\n 0 1 read-only 0 IRQ14 source is not from SPI0 interrupt (SPI0_INT) #0 1 IRQ14 source is from SPI0 interrupt (SPI0_INT) #1 IRQ15_SRC IRQ15_SRC IRQ15 (SPI1) Interrupt Source Identity 0x3C read-only n 0x0 0x0 SPI1_INT IRQ15 Source Identity\n 0 1 read-only 0 IRQ15 source is not from SPI1 interrupt (SPI1_INT) #0 1 IRQ15 source is from SPI1 interrupt (SPI1_INT) #1 IRQ16_SRC IRQ16_SRC IRQ16 (SPI2) Interrupt Source Identity 0x40 read-only n 0x0 0x0 SPI2_INT IRQ16 Source Identity\n 0 1 read-only 0 IRQ16 source is not from SPI2 interrupt (SPI2_INT) #0 1 IRQ16 source is from SPI2 interrupt (SPI2_INT) #1 IRQ18_SRC IRQ18_SRC IRQ18 (I2C0) Interrupt Source Identity 0x48 read-only n 0x0 0x0 I2C0_INT IRQ18 Source Identity\n 0 1 read-only 0 IRQ18 source is not from I2C0 interrupt (I2C0_INT) #0 1 IRQ18 source is from I2C0 interrupt (I2C0_INT) #1 IRQ19_SRC IRQ19_SRC IRQ19 (CKD) Interrupt Source Identity 0x4C read-only n 0x0 0x0 CKD_INT IRQ19 Source Identity\n 0 1 read-only 0 IRQ19 source is not from CKD interrupt (CKD_INT) #0 1 IRQ19 source is from CKD interrupt (CKD_INT) #1 IRQ1_SRC IRQ1_SRC IRQ1 (WDT) Interrupt Source Identity 0x4 read-only n 0x0 0x0 WDT_INT IRQ1 Source Identity\n 0 1 read-only 0 IRQ1 source is not from watchdog interrupt (WDT _INT) #0 1 IRQ1 source is from watchdog interrupt (WDT_INT) #1 WWDT_INT IRQ1 Source Identity\n 1 1 read-only 0 IRQ1 source is not from window-watchdog interrupt (WWDT _INT) #0 1 IRQ1 source is from window-watchdog interrupt (WWDT_INT) #1 IRQ21_SRC IRQ21_SRC IRQ21 (EPWM0) Interrupt Source Identity 0x54 read-only n 0x0 0x0 EPWM0_INT IRQ21 Source Identity\n 0 1 read-only 0 IRQ21 source is not from EPWM0 interrupt (EPWM0_INT) #0 1 IRQ21 source is from EPWM0 interrupt (EPWM0_INT) #1 IRQ22_SRC IRQ22_SRC IRQ22 (EPWM1) Interrupt Source Identity 0x58 read-only n 0x0 0x0 EPWM1_INT IRQ22 Source Identity\n 0 1 read-only 0 IRQ22 source is not from EPWM1 interrupt (EPWM1_INT) #0 1 IRQ22 source is from EPWM1 interrupt (EPWM1_INT) #1 IRQ23_SRC IRQ23_SRC IRQ23 (ECAP0) Interrupt Source Identity 0x5C read-only n 0x0 0x0 ECAP0_INT IRQ23 Source Identity\n 0 1 read-only 0 IRQ23 source is not from ECAP0 interrupt (ECAP0_INT) #0 1 IRQ23 source is from ECAP0 interrupt (ECAP0_INT) #1 IRQ24_SRC IRQ24_SRC IRQ24 (ECAP1) Interrupt Source Identity 0x60 read-only n 0x0 0x0 ECAP1_INT IRQ24 Source Identity\n 0 1 read-only 0 IRQ24 source is not from ECAP1 interrupt (ECAP1_INT) #0 1 IRQ24 source is from ECAP1 interrupt (ECAP1_INT) #1 IRQ25_SRC IRQ25_SRC IRQ25 (ACMP) Interrupt Source Identity 0x64 read-only n 0x0 0x0 ACMP_INT IRQ25 Source Identity\n 0 1 read-only 0 IRQ25 source is not from ACMP interrupt (ACMP_INT) #0 1 IRQ25 source is from ACMP interrupt (ACMP_INT) #1 IRQ28_SRC IRQ28_SRC IRQ28 (PWRWU) Interrupt Source Identity 0x70 read-only n 0x0 0x0 PWRWU_INT IRQ28 Source Identity\n 0 1 read-only 0 IRQ28 source is not from PWRWU interrupt (PWRWU_INT) #0 1 IRQ28 source is from PWREU interrupt (PWRWU_INT) #1 IRQ29_SRC IRQ29_SRC IRQ29 (EADC1) Interrupt Source Identity 0x74 read-only n 0x0 0x0 EADC1_INT IRQ29 Source Identity \n 0 1 read-only 0 IRQ29 source is not from EADC1 interrupt (EADC1_INT) #0 1 IRQ29 source is from EADC1 interrupt (EADC1_INT) #1 IRQ2_SRC IRQ2_SRC IRQ2 (EINT0) Interrupt Source Identity 0x8 read-only n 0x0 0x0 EINT0 IRQ2 Source Identity\n 0 1 read-only 0 IRQ2 source is not from external signal interrupt 0 from P3.2 (EINT0) #0 1 IRQ2 source is from external signal interrupt 0 from P3.2 (EINT0) #1 IRQ30_SRC IRQ30_SRC IRQ30 (EADC2) Interrupt Source Identity 0x78 read-only n 0x0 0x0 EADC2_INT IRQ30 Source Identity \n 0 1 read-only 0 IRQ30 source is not from EADC2 interrupt (EADC2_INT) #0 1 IRQ30 source is from EADC2 interrupt (EADC2_INT) #1 IRQ31_SRC IRQ31_SRC IRQ31 (EADC3) Interrupt Source Identity 0x7C read-only n 0x0 0x0 EADC3_INT IRQ31 Source Identity \n 0 1 read-only 0 IRQ31 source is not from EADC3 interrupt (EADC3_INT) #0 1 IRQ31 source is from EADC3 interrupt (EADC3_INT) #1 IRQ3_SRC IRQ3_SRC IRQ3 (EINT1) Interrupt Source Identity 0xC read-only n 0x0 0x0 EINT1 IRQ3 Source Identity\n 0 1 read-only 0 IRQ3 source is not from external signal interrupt 1 from P3.3 (EINT1) #0 1 IRQ3 source is from external signal interrupt 1 from P3.3 (EINT1) #1 IRQ4_SRC IRQ4_SRC IRQ4 (P0-P4) Interrupt Source Identity 0x10 read-only n 0x0 0x0 P0_INT IRQ4 Source Identity\n 0 1 read-only 0 IRQ4 source is not from P0 interrupt (P0_INT) #0 1 IRQ4 source is from P0 interrupt (P0_INT) #1 P1_INT IRQ4 Source Identity\n 1 1 read-only 0 IRQ4 source is not from P1 interrupt (P1_INT) #0 1 IRQ4 source is from P1 interrupt (P1_INT) #1 P2_INT IRQ4 Source Identity\n 2 1 read-only 0 IRQ4 source is not from P2 interrupt (P2_INT) #0 1 IRQ4 source is from P2 interrupt (P2_INT) #1 P3_INT IRQ4 Source Identity\n 3 1 read-only 0 IRQ4 source is not from P3 interrupt (P3_INT) #0 1 IRQ4 source is from P3 interrupt (P3_INT) #1 P4_INT IRQ4 Source Identity\n 4 1 read-only 0 IRQ4 source is not from P4 interrupt (P4_INT) #0 1 IRQ4 source is from P4 interrupt (P4_INT) #1 IRQ5_SRC IRQ5_SRC IRQ5 (P5-PA) Interrupt Source Identity 0x14 read-only n 0x0 0x0 P5_INT IRQ5 Source Identity\n 0 1 read-only 0 IRQ5 source is not from P5 interrupt (P5_INT) #0 1 IRQ5 source is from P5 interrupt (P5_INT) #1 P6_INT IRQ5 Source Identity\n 1 1 read-only 0 IRQ5 source is not from P6 interrupt (P6_INT) #0 1 IRQ5 source is from P6 interrupt (P6_INT) #1 P7_INT IRQ5 Source Identity\n 2 1 read-only 0 IRQ5 source is not from P7 interrupt (P7_INT) #0 1 IRQ5 source is from P7 interrupt (P7_INT) #1 P8_INT IRQ5 Source Identity\n 3 1 read-only 0 IRQ5 source is not from P8 interrupt (P8_INT) #0 1 IRQ5 source is from P8 interrupt (P8_INT) #1 P9_INT IRQ5 Source Identity\n 4 1 read-only 0 IRQ5 source is not from P9 interrupt (P9_INT) #0 1 IRQ5 source is from P9 interrupt (P9_INT) #1 PA_INT IRQ5 Source Identity\n 5 1 read-only 0 IRQ5 source is not from PA interrupt (PA_INT) #0 1 IRQ5 source is from PA interrupt (PA_INT) #1 IRQ6_SRC IRQ6_SRC IRQ6 (BPWM0) Interrupt Source Identity 0x18 read-only n 0x0 0x0 BPCH0_INT IRQ6 Source Identity\n 0 1 read-only 0 IRQ6 source is not from BPWM0 channel 0 interrupt (BPCH0_INT) #0 1 IRQ6 source is from BPWM0 channel 0 interrupt (BPCH0_INT) #1 BPCH1_INT IRQ6 Source Identity\n 1 1 read-only 0 IRQ6 source is not from BPWM0 channel 1 interrupt (BPCH1_INT) #0 1 IRQ6 source is from BPWM0 channel 1 interrupt (BPCH1_INT) #1 IRQ7_SRC IRQ7_SRC IRQ7 (EADC0) Interrupt Source Identity 0x1C read-only n 0x0 0x0 EADC0_INT IRQ7 Source Identity \n 0 1 read-only 0 IRQ7 source is not from EADC0 interrupt (EADC0_INT) #0 1 IRQ7 source is from EADC0 interrupt (EADC0_INT) #1 IRQ8_SRC IRQ8_SRC IRQ8 (TMR0) Interrupt Source Identity 0x20 read-only n 0x0 0x0 TMR0_INT IRQ8 Source Identity \n 0 1 read-only 0 IRQ8 source is not from Timer0 interrupt (TMR0_INT) #0 1 IRQ8 source is from Timer0 interrupt (TMR0_INT) #1 IRQ9_SRC IRQ9_SRC IRQ9 (TMR1) Interrupt Source Identity 0x24 read-only n 0x0 0x0 TMR1_INT IRQ9 Source Identity \n 0 1 read-only 0 IRQ9 source is not from Timer1 interrupt (TMR1_INT) #0 1 IRQ9 source is from Timer1 interrupt (TMR1_INT) #1 MCU_IRQ MCU_IRQ MCU Interrupt Request Source Register 0x84 read-write n 0x0 0x0 MCU_IRQ MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and then interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0, it means no interrupt is assert.\nWrite 1 to generate an interrupt to Cortex-M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1, it means an interrupt is assert.\nWrite 1 to clear the interrupt and MCU_IRQ[n]. 0 32 read-write MCU_IRQCR MCU_IRQCR MCU Interrupt Request Control Register 0x88 read-write n 0x0 0x0 FAST_IRQ Fast IRQ Latency Enable Bit\n 0 1 read-write 0 MCU IRQ latency is fixed at 13 HCLK, MCU will enter IRQ handler after this fixed latency when interrupt happened #0 1 MCU IRQ latency will not fixed, MCU will enter IRQ handler as soon as possible when interrupt happened #1 NMI_SEL NMI_SEL NMI Interrupt Source Select Control Register 0x80 read-write n 0x0 0x0 NMI_EN NMI Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected bit. Refer to the REGWRPROT register. 8 1 read-write 0 IRQ0~31 assigned to NMI Disabled. (NMI still can be software triggered by setting its pending flag.) #0 1 IRQ0~31 assigned to NMI Enabled #1 NMI_SEL NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of IRQ0~IRQ31 by setting NMI_SEL with IRQ number. The default NMI interrupt is assigned as IRQ0 interrupt if NMI is enabled by setting NMI_SEL[8]. 0 5 read-write NVIC NVIC Register Map NVIC 0x0 0x0 0x4 registers n 0x100 0x4 registers n 0x180 0x4 registers n 0x300 0x20 registers n 0x80 0x4 registers n ICER NVIC_ICER IRQ0 ~ IRQ31 Clear-enable Control Register 0x80 read-write n 0x0 0x0 CLRENA Interrupt Clear Enable Bits\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nNote: Read value indicates the current enable status. 0 32 read-write 0 No effect.\nAssociated interrupt status Disabled 0 1 Write 1 to disable associated interrupt.\nAssociated interrupt status Enabled 1 ICPR NVIC_ICPR IRQ0 ~ IRQ31 Clear-pending Control Register 0x180 read-write n 0x0 0x0 CLRPEND Interrupt Clear-pending\nThe ICPR removes the pending state from interrupts, and shows the interrupts that are pending. Each bit represents an IRQ number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nRead value indicates the current pending status. 0 32 read-write 0 No effect.\nAssociated interrupt in not in pending status 0 1 Write 1 to clear pending state.\nAssociated interrupt is in pending status 1 IPR0 NVIC_IPR0 IRQ0 ~ IRQ3 Interrupt Priority Control Register 0x300 read-write n 0x0 0x0 PRI_0 Priority of IRQ0 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_1 Priority of IRQ1 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write PRI_2 Priority of IRQ2 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_3 Priority of IRQ3 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write IPR1 NVIC_IPR1 IRQ4 ~ IRQ7 Interrupt Priority Control Register 0x304 read-write n 0x0 0x0 PRI_4 Priority of IRQ4 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_5 Priority of IRQ5 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write PRI_6 Priority of IRQ6 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_7 Priority of IRQ7 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write IPR2 NVIC_IPR2 IRQ8 ~ IRQ11 Interrupt Priority Control Register 0x308 read-write n 0x0 0x0 PRI_10 Priority of IRQ10 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_11 Priority of IRQ11 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write PRI_8 Priority of IRQ8 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_9 Priority of IRQ9 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write IPR3 NVIC_IPR3 IRQ12 ~ IRQ15 Interrupt Priority Control Register 0x30C read-write n 0x0 0x0 PRI_12 Priority of IRQ12 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_13 Priority of IRQ13 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write PRI_14 Priority of IRQ14 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_15 Priority of IRQ15 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write IPR4 NVIC_IPR4 IRQ16 ~ IRQ19 Interrupt Priority Control Register 0x310 read-write n 0x0 0x0 PRI_16 Priority of IRQ16 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_17 Priority of IRQ17 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write PRI_18 Priority of IRQ18 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_19 Priority of IRQ19 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write IPR5 NVIC_IPR5 IRQ20 ~ IRQ23 Interrupt Priority Control Register 0x314 read-write n 0x0 0x0 PRI_20 Priority of IRQ20 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_21 Priority of IRQ21 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write PRI_22 Priority of IRQ22 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_23 Priority of IRQ23 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write IPR6 NVIC_IPR6 IRQ24 ~ IRQ27 Interrupt Priority Control Register 0x318 read-write n 0x0 0x0 PRI_24 Priority of IRQ24 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_25 Priority of IRQ25 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write PRI_26 Priority of IRQ26 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_27 Priority of IRQ27 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write IPR7 NVIC_IPR7 IRQ28 ~ IRQ31 Interrupt Priority Control Register 0x31C read-write n 0x0 0x0 PRI_28 Priority of IRQ28 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_29 Priority of IRQ29 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write PRI_30 Priority of IRQ30 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_31 Priority of IRQ31 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write ISER NVIC_ISER IRQ0 ~ IRQ31 Set-enable Control Register 0x0 read-write n 0x0 0x0 SETENA Interrupt Enable Register\nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nNote: Read value indicates the current enable status. 0 32 read-write 0 No effect.\nAssociated interrupt status Disabled 0 1 Write 1 to enable associated interrupt.\nAssociated interrupt status Enabled 1 ISPR NVIC_ISPR IRQ0 ~ IRQ31 Set-pending Control Register 0x100 read-write n 0x0 0x0 SETPEND Interrupt Set-pending\nThe ISPR forces interrupts into the pending state, and shows the interrupts that are pending. Each bit represents an IRQ number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nRead value indicates the current pending status. 0 32 read-write 0 No effect.\nAssociated interrupt in not in pending status 0 1 Write 1 to set pending state.\nAssociated interrupt is in pending status 1 OPA OPA Register Map OPA 0x0 0x0 0x8 registers n OPACR OPACR OP Amplifier Control Register 0x0 read-write n 0x0 0x0 OP0_EN OP Amplifier 0 Enable Bit\n 0 1 read-write 0 OP Amplifier 0 Disabled #0 1 OP Amplifier 0 Enabled #1 OP1_EN OP Amplifier 1 Enable Bit\n 1 1 read-write 0 OP Amplifier 1 Disabled #0 1 OP Amplifier 1 Enabled #1 OPDIE0 OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit\nThe OPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDIE0 is set to 1, a comparator interrupt request is generated. 8 1 read-write 0 OP Amplifier 0 digital output interrupt function Disabled #0 1 OP Amplifier 0 digital output interrupt function Enabled #1 OPDIE1 OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Bit\nThe OPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDIE1 is set to 1, a comparator interrupt request is generated. 9 1 read-write 0 OP Amplifier 1 digital output interrupt function Disabled #0 1 OP Amplifier 1 digital output interrupt function Enabled #1 OPSCH0_EN OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit\n 4 1 read-write 0 OP Amplifier 0 Schmitt trigger Disabled #0 1 OP Amplifier 0 Schmitt trigger Enabled #1 OPSCH1_EN OP Amplifier 1 Schmitt Trigger Non-inverting Buffer Enable Bit\n 5 1 read-write 0 OP Amplifier 1 Schmitt trigger Disabled #0 1 OP Amplifier 1 Schmitt trigger Enabled #1 OPASR OPASR OP Amplifier Status Register 0x4 read-write n 0x0 0x0 OPDF0 OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag\nOPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state. \nNote: This bit is cleared by writing 1 to it. 4 1 read-write OPDF1 OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag\nOPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state. \nNote: This bit is cleared by writing 1 to it. 5 1 read-write OPDO0 OP Amplifier 0 Digital Output\n 0 1 read-write OPDO1 OP Amplifier 1 Digital Output\n 1 1 read-write SCB SCB Register Map SCB 0x0 0x0 0x8 registers n 0x1C 0x8 registers n 0xC 0x8 registers n AIRCR AIRCR Application Interrupt and Reset Control Register 0xC -1 read-write n 0x0 0x0 SYSRESETREQ System Reset Request (Write Only)\n 2 1 write-only 0 no effect #0 1 requests a system level reset #1 VECTKEY Register Key (Write Only)\nWhen writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status. 16 16 write-only CPUID CPUID CPUID Register 0x0 -1 read-only n 0x0 0x0 IMPLEMENTER Implementer Code Assigned by ARM \n 24 8 read-only PART Architecture of the Processor\nRead as 0xC corresponding to ARMv6-M architecture. 16 4 read-only PARTNO Part Number of the Processor\nReads as 0xC20 corresponding to Cortex-M0 4 12 read-only REVISION Revision Number\nReads as 0x0. 0 4 read-only ICSR ICSR Interrupt Control State Register 0x4 read-write n 0x0 0x0 ISRPENDING Interrupt Pending Flag (Read Only)\nIndicates if an external configurable (NVIC generated) interrupt is pending.\n 22 1 read-only 0 interrupt not pending #0 1 interrupt pending #1 NMIPENDSET NMI Set-pending Bit\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.\nWrite Operation:\n 31 1 read-write 0 no effect.\nNMI exception is not pending #0 1 changes NMI exception state to pending.\nNMI exception is pending #1 PENDSTCLR SysTick Exception Clear-pending Bit (Write Only)\n 25 1 write-only 0 no effect #0 1 removes the pending state from the SysTick exception #1 PENDSTSET SysTick Exception Set-pending Bit\nWrite Operation:\n 26 1 read-write 0 no effect.\nSysTick exception is not pending #0 1 changes SysTick exception state to pending.\nSysTick exception is pending #1 PENDSVCLR PendSV Clear-pending Bit (Write Only)\n 27 1 write-only 0 no effect #0 1 removes the pending state from the PendSV exception #1 PENDSVSET PendSV Set-pending Bit\nWrite Operation:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending. 28 1 read-write 0 no effect.\nPendSV exception is not pending #0 1 changes PendSV exception state to pending.\nPendSV exception is pending #1 VECTACTIVE Vector Active Indicator (Read Only)\nThis field contains the active exception number:\n 0 6 read-only 0 Thread mode 0 VECTPENDING Vector Pending Indicator (Read Only)\nThis field indicates the exception number of the highest priority pending enabled exception:\n 12 6 read-only 0 no pending exceptions 0 SCR SCR System Control Register 0x10 read-write n 0x0 0x0 SEVONPEND Send Event on Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event. 4 1 read-write 0 Oonly enabled interrupts or events can wake up the processor, disabled interrupts are excluded #0 1 Enabled events and all interrupts, including disabled interrupts, can wake-up the processor #1 SLEEPDEEP Deep Sleep Mode Enable Bit\nThis bit controls whether the processor uses sleep or deep sleep as its low power mode:\n 2 1 read-write 0 Sleep mode #0 1 Deep sleep mode #1 SLEEPONEXIT Sleep-on-exit Enable Bit\nThis bit controls sleep-on-exit when returning from Handler mode to Thread mode:\nNote: Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 1 1 read-write 0 Do not sleep when returning to Thread mode #0 1 Enter Sleep, or Deep Sleep, on return from an ISR to Thread mode #1 SHPR2 SHPR2 System Handler Priority Register 2 0x1C read-write n 0x0 0x0 PRI_11 Priority of System Handler 11, SVCall 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write SHPR3 SHPR3 System Handler Priority Register 3 0x20 read-write n 0x0 0x0 PRI_14 Priority of System Handler 14, PendSV 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_15 Priority of System Handler 15, SysTick 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write SPI0 SPI Register Map SPI 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x3C 0xC registers n SPI_CNTRL SPI_CNTRL Control and Status Register 0x0 -1 read-write n 0x0 0x0 CLKP Clock Polarity\n 11 1 read-write 0 SPI bus clock is idle low #0 1 SPI bus clock is idle high #1 FIFO FIFO Mode Enable Bit Note: Before enabling FIFO mode, the other related settings should be set in advance. In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0. 21 1 read-write 0 FIFO mode Disabled #0 1 FIFO mode Enabled #1 GO_BUSY SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit. 0 1 read-write 0 Data transfer stopped #0 1 In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master #1 IE Unit Transfer Interrupt Enable Bit\n 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 IF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 16 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 LSB Send LSB First\n 10 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX) #1 REORDER Byte Reorder Function Enable Bit\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval. 19 1 read-write 0 Byte reorder function Disabled #0 1 Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE #1 RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_STATUS[24].\n 24 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RX_FULL Receive FIFO Buffer Full Indicator (Read Only)\nA mutual mirror bit of SPI_STATUS[25].\n 25 1 read-only 0 Receive FIOF buffer is not full #0 1 Receive FIFO buffer is full #1 RX_NEG Receive on Negative Edge\n 1 1 read-write 0 Received data input signal is latched on the rising-edge of SPI bus clock #0 1 Received data input signal is latched on the falling-edge of SPI bus clock #1 SLAVE Slave Mode Enable Bit\n 18 1 read-write 0 Master mode #0 1 Slave mode #1 SP_CYCLE Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPI clock cycle\nExample:\n 12 4 read-write TX_BIT_LEN Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n 3 5 read-write TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_STAUTS[26].\n 26 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nA mutual mirror bit of SPI_STATUS[27].\n 27 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TX_NEG Transmit on Negative Edge\n 2 1 read-write 0 Transmitted data output signal is changed on the rising-edge of SPI bus clock #0 1 Transmitted data output signal is changed on the falling-edge of SPI bus clock #1 SPI_CNTRL2 SPI_CNTRL2 Control and Status Register 2 0x3C -1 read-write n 0x0 0x0 NOSLVSEL Slave 3-wire Mode Enable Bit\n In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG (SPI_SSR[4]) will be set as 1 automatically. 8 1 read-write 0 4-wire bi-direction interface in Slave mode #0 1 3-wire bi-direction interface in Slave mode. The controller will be ready to transmit/receive data after the GO_BUSY bit is set to 1 #1 SLV_ABORT Slave 3-wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over one transaction time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a transfer done interrupt event.\nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.. 9 1 read-write 0 No effect #0 1 Force the current transaction done #1 SLV_START_INTSTS Slave 3-wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n 11 1 read-write 0 Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 #0 1 A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit #1 SSTA_INTEN Slave 3-wire Mode Start Interrupt Enable Bit\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n 10 1 read-write 0 Transaction start interrupt Disabled #0 1 Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared #1 SS_INT_OPT Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n 16 1 read-write 0 As the slave select signal goes to inactive level, the IF bit will NOT be set to 1 #0 1 As the slave select signal goes to inactive level, the IF bit will be set to 1 #1 SPI_DIVIDER SPI_DIVIDER Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation. \n\nwhere \n is the SPI peripheral clock source, which is defined in the CLKSEL1 register. 0 8 read-write SPI_FIFO_CTL SPI_FIFO_CTL SPI FIFO Control Register 0x40 -1 read-write n 0x0 0x0 RXOV_INTEN Receive FIFO Overrun Interrupt Enable Bit\n 6 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RX_CLR Clear Receive FIFO Buffer\n 0 1 read-write 0 No effect #0 1 Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software #1 RX_INTEN Receive Threshold Interrupt Enable Bit\n 2 1 read-write 0 RX threshold interrupt Disabled #0 1 RX threshold interrupt Enabled #1 RX_THRESHOLD Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. 24 3 read-write TIMEOUT_INTEN Receive FIFO Time-out Interrupt Enable Bit\n 21 1 read-write 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 TX_CLR Clear Transmit FIFO Buffer\n 1 1 read-write 0 No effect #0 1 Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software #1 TX_INTEN Transmit Threshold Interrupt Enable Bit\n 3 1 read-write 0 TX threshold interrupt Disabled #0 1 TX threshold interrupt Enabled #1 TX_THRESHOLD Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. 28 3 read-write SPI_RX SPI_RX Data Receive Register 0x10 read-only n 0x0 0x0 RX Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If the FIFO mode is disabled, the software can access the last received data by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, then the receive FIFO buffers can be accessed through software by reading this register. This is a read-only register. 0 32 read-only SPI_SSR SPI_SSR Slave Select Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable Bit (Master Only)\n 3 1 read-write 0 If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[0] #0 1 If this bit is set, SPI_SS signals will be generated automatically by hardware. It means that device/slave select signal, which is set in SPI_SSR[0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 LTRIG_FLAG Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \n 5 1 read-write 0 Transferred bit length of one transaction does not meet the specified requirement #0 1 Transferred bit length meets the specified requirement which defined in TX_BIT_LEN. Note: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning #1 SSR Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared\n 0 1 read-write 0 Set the SPIx_SS pin to inactive state.\nKeep the SPIx_SS pin to inactive state #0 1 Set the SPIx_SS pin to active state.\nSelect the SPIx_SS pin to be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SS_LVL #1 SS_LTRIG Slave Select Level Trigger Enable Bit (Slave Only)\n 4 1 read-write 0 Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge #0 1 Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high #1 SS_LVL Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS).\n 2 1 read-write 0 The slave select signal SPI_SS is active on low-level/falling-edge #0 1 The slave select signal SPI_SS is active on high-level/rising-edge #1 SPI_STATUS SPI_STATUS SPI Status Register 0x44 -1 read-write n 0x0 0x0 IF SPI Unit Transfer Interrupt Flag\nA mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself. 16 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[24].\n 24 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RX_FIFO_COUNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 12 4 read-only RX_FULL Receive FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[25].\n 25 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RX_INTSTS Receive FIFO Threshold Interrupt Status (Read Only)\n 0 1 read-only 0 The valid data count within the receive FIFO buffer is less than or equal to the setting value of RX_THRESHOLD #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD #1 RX_OVERRUN Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. 2 1 read-write 0 Receive FIFO does not overrun #0 1 Receive FIFO overruns #1 SLV_START_INTSTS Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n 11 1 read-write 0 Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1. The transfer is not started #0 1 A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit #1 TIMEOUT Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 20 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[26].\n 26 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TX_FIFO_COUNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[27].\n 27 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TX_INTSTS Transmit FIFO Threshold Interrupt Status (Read Only)\n 4 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD #1 SPI_TX SPI_TX Data Transmit Register 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe Data Transmit Register holds the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field TX_BIT_LEN in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bit field TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1 0 32 write-only SPI1 SPI Register Map SPI 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x3C 0xC registers n SPI_CNTRL SPI_CNTRL Control and Status Register 0x0 -1 read-write n 0x0 0x0 CLKP Clock Polarity\n 11 1 read-write 0 SPI bus clock is idle low #0 1 SPI bus clock is idle high #1 FIFO FIFO Mode Enable Bit Note: Before enabling FIFO mode, the other related settings should be set in advance. In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0. 21 1 read-write 0 FIFO mode Disabled #0 1 FIFO mode Enabled #1 GO_BUSY SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit. 0 1 read-write 0 Data transfer stopped #0 1 In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master #1 IE Unit Transfer Interrupt Enable Bit\n 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 IF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 16 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 LSB Send LSB First\n 10 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX) #1 REORDER Byte Reorder Function Enable Bit\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval. 19 1 read-write 0 Byte reorder function Disabled #0 1 Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE #1 RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_STATUS[24].\n 24 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RX_FULL Receive FIFO Buffer Full Indicator (Read Only)\nA mutual mirror bit of SPI_STATUS[25].\n 25 1 read-only 0 Receive FIOF buffer is not full #0 1 Receive FIFO buffer is full #1 RX_NEG Receive on Negative Edge\n 1 1 read-write 0 Received data input signal is latched on the rising-edge of SPI bus clock #0 1 Received data input signal is latched on the falling-edge of SPI bus clock #1 SLAVE Slave Mode Enable Bit\n 18 1 read-write 0 Master mode #0 1 Slave mode #1 SP_CYCLE Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPI clock cycle\nExample:\n 12 4 read-write TX_BIT_LEN Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n 3 5 read-write TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_STAUTS[26].\n 26 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nA mutual mirror bit of SPI_STATUS[27].\n 27 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TX_NEG Transmit on Negative Edge\n 2 1 read-write 0 Transmitted data output signal is changed on the rising-edge of SPI bus clock #0 1 Transmitted data output signal is changed on the falling-edge of SPI bus clock #1 SPI_CNTRL2 SPI_CNTRL2 Control and Status Register 2 0x3C -1 read-write n 0x0 0x0 NOSLVSEL Slave 3-wire Mode Enable Bit\n In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG (SPI_SSR[4]) will be set as 1 automatically. 8 1 read-write 0 4-wire bi-direction interface in Slave mode #0 1 3-wire bi-direction interface in Slave mode. The controller will be ready to transmit/receive data after the GO_BUSY bit is set to 1 #1 SLV_ABORT Slave 3-wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over one transaction time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a transfer done interrupt event.\nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.. 9 1 read-write 0 No effect #0 1 Force the current transaction done #1 SLV_START_INTSTS Slave 3-wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n 11 1 read-write 0 Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 #0 1 A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit #1 SSTA_INTEN Slave 3-wire Mode Start Interrupt Enable Bit\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n 10 1 read-write 0 Transaction start interrupt Disabled #0 1 Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared #1 SS_INT_OPT Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n 16 1 read-write 0 As the slave select signal goes to inactive level, the IF bit will NOT be set to 1 #0 1 As the slave select signal goes to inactive level, the IF bit will be set to 1 #1 SPI_DIVIDER SPI_DIVIDER Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation. \n\nwhere \n is the SPI peripheral clock source, which is defined in the CLKSEL1 register. 0 8 read-write SPI_FIFO_CTL SPI_FIFO_CTL SPI FIFO Control Register 0x40 -1 read-write n 0x0 0x0 RXOV_INTEN Receive FIFO Overrun Interrupt Enable Bit\n 6 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RX_CLR Clear Receive FIFO Buffer\n 0 1 read-write 0 No effect #0 1 Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software #1 RX_INTEN Receive Threshold Interrupt Enable Bit\n 2 1 read-write 0 RX threshold interrupt Disabled #0 1 RX threshold interrupt Enabled #1 RX_THRESHOLD Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. 24 3 read-write TIMEOUT_INTEN Receive FIFO Time-out Interrupt Enable Bit\n 21 1 read-write 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 TX_CLR Clear Transmit FIFO Buffer\n 1 1 read-write 0 No effect #0 1 Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software #1 TX_INTEN Transmit Threshold Interrupt Enable Bit\n 3 1 read-write 0 TX threshold interrupt Disabled #0 1 TX threshold interrupt Enabled #1 TX_THRESHOLD Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. 28 3 read-write SPI_RX SPI_RX Data Receive Register 0x10 read-only n 0x0 0x0 RX Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If the FIFO mode is disabled, the software can access the last received data by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, then the receive FIFO buffers can be accessed through software by reading this register. This is a read-only register. 0 32 read-only SPI_SSR SPI_SSR Slave Select Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable Bit (Master Only)\n 3 1 read-write 0 If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[0] #0 1 If this bit is set, SPI_SS signals will be generated automatically by hardware. It means that device/slave select signal, which is set in SPI_SSR[0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 LTRIG_FLAG Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \n 5 1 read-write 0 Transferred bit length of one transaction does not meet the specified requirement #0 1 Transferred bit length meets the specified requirement which defined in TX_BIT_LEN. Note: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning #1 SSR Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared\n 0 1 read-write 0 Set the SPIx_SS pin to inactive state.\nKeep the SPIx_SS pin to inactive state #0 1 Set the SPIx_SS pin to active state.\nSelect the SPIx_SS pin to be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SS_LVL #1 SS_LTRIG Slave Select Level Trigger Enable Bit (Slave Only)\n 4 1 read-write 0 Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge #0 1 Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high #1 SS_LVL Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS).\n 2 1 read-write 0 The slave select signal SPI_SS is active on low-level/falling-edge #0 1 The slave select signal SPI_SS is active on high-level/rising-edge #1 SPI_STATUS SPI_STATUS SPI Status Register 0x44 -1 read-write n 0x0 0x0 IF SPI Unit Transfer Interrupt Flag\nA mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself. 16 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[24].\n 24 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RX_FIFO_COUNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 12 4 read-only RX_FULL Receive FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[25].\n 25 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RX_INTSTS Receive FIFO Threshold Interrupt Status (Read Only)\n 0 1 read-only 0 The valid data count within the receive FIFO buffer is less than or equal to the setting value of RX_THRESHOLD #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD #1 RX_OVERRUN Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. 2 1 read-write 0 Receive FIFO does not overrun #0 1 Receive FIFO overruns #1 SLV_START_INTSTS Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n 11 1 read-write 0 Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1. The transfer is not started #0 1 A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit #1 TIMEOUT Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 20 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[26].\n 26 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TX_FIFO_COUNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[27].\n 27 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TX_INTSTS Transmit FIFO Threshold Interrupt Status (Read Only)\n 4 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD #1 SPI_TX SPI_TX Data Transmit Register 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe Data Transmit Register holds the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field TX_BIT_LEN in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bit field TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1 0 32 write-only SPI2 SPI Register Map SPI 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x3C 0xC registers n SPI_CNTRL SPI_CNTRL Control and Status Register 0x0 -1 read-write n 0x0 0x0 CLKP Clock Polarity\n 11 1 read-write 0 SPI bus clock is idle low #0 1 SPI bus clock is idle high #1 FIFO FIFO Mode Enable Bit Note: Before enabling FIFO mode, the other related settings should be set in advance. In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0. 21 1 read-write 0 FIFO mode Disabled #0 1 FIFO mode Enabled #1 GO_BUSY SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit. 0 1 read-write 0 Data transfer stopped #0 1 In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master #1 IE Unit Transfer Interrupt Enable Bit\n 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 IF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 16 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 LSB Send LSB First\n 10 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX) #1 REORDER Byte Reorder Function Enable Bit\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval. 19 1 read-write 0 Byte reorder function Disabled #0 1 Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE #1 RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_STATUS[24].\n 24 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RX_FULL Receive FIFO Buffer Full Indicator (Read Only)\nA mutual mirror bit of SPI_STATUS[25].\n 25 1 read-only 0 Receive FIOF buffer is not full #0 1 Receive FIFO buffer is full #1 RX_NEG Receive on Negative Edge\n 1 1 read-write 0 Received data input signal is latched on the rising-edge of SPI bus clock #0 1 Received data input signal is latched on the falling-edge of SPI bus clock #1 SLAVE Slave Mode Enable Bit\n 18 1 read-write 0 Master mode #0 1 Slave mode #1 SP_CYCLE Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPI clock cycle\nExample:\n 12 4 read-write TX_BIT_LEN Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n 3 5 read-write TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_STAUTS[26].\n 26 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nA mutual mirror bit of SPI_STATUS[27].\n 27 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TX_NEG Transmit on Negative Edge\n 2 1 read-write 0 Transmitted data output signal is changed on the rising-edge of SPI bus clock #0 1 Transmitted data output signal is changed on the falling-edge of SPI bus clock #1 SPI_CNTRL2 SPI_CNTRL2 Control and Status Register 2 0x3C -1 read-write n 0x0 0x0 NOSLVSEL Slave 3-wire Mode Enable Bit\n In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG (SPI_SSR[4]) will be set as 1 automatically. 8 1 read-write 0 4-wire bi-direction interface in Slave mode #0 1 3-wire bi-direction interface in Slave mode. The controller will be ready to transmit/receive data after the GO_BUSY bit is set to 1 #1 SLV_ABORT Slave 3-wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over one transaction time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a transfer done interrupt event.\nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.. 9 1 read-write 0 No effect #0 1 Force the current transaction done #1 SLV_START_INTSTS Slave 3-wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n 11 1 read-write 0 Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 #0 1 A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit #1 SSTA_INTEN Slave 3-wire Mode Start Interrupt Enable Bit\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n 10 1 read-write 0 Transaction start interrupt Disabled #0 1 Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared #1 SS_INT_OPT Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n 16 1 read-write 0 As the slave select signal goes to inactive level, the IF bit will NOT be set to 1 #0 1 As the slave select signal goes to inactive level, the IF bit will be set to 1 #1 SPI_DIVIDER SPI_DIVIDER Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation. \n\nwhere \n is the SPI peripheral clock source, which is defined in the CLKSEL1 register. 0 8 read-write SPI_FIFO_CTL SPI_FIFO_CTL SPI FIFO Control Register 0x40 -1 read-write n 0x0 0x0 RXOV_INTEN Receive FIFO Overrun Interrupt Enable Bit\n 6 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RX_CLR Clear Receive FIFO Buffer\n 0 1 read-write 0 No effect #0 1 Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software #1 RX_INTEN Receive Threshold Interrupt Enable Bit\n 2 1 read-write 0 RX threshold interrupt Disabled #0 1 RX threshold interrupt Enabled #1 RX_THRESHOLD Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. 24 3 read-write TIMEOUT_INTEN Receive FIFO Time-out Interrupt Enable Bit\n 21 1 read-write 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 TX_CLR Clear Transmit FIFO Buffer\n 1 1 read-write 0 No effect #0 1 Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software #1 TX_INTEN Transmit Threshold Interrupt Enable Bit\n 3 1 read-write 0 TX threshold interrupt Disabled #0 1 TX threshold interrupt Enabled #1 TX_THRESHOLD Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. 28 3 read-write SPI_RX SPI_RX Data Receive Register 0x10 read-only n 0x0 0x0 RX Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If the FIFO mode is disabled, the software can access the last received data by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, then the receive FIFO buffers can be accessed through software by reading this register. This is a read-only register. 0 32 read-only SPI_SSR SPI_SSR Slave Select Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable Bit (Master Only)\n 3 1 read-write 0 If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[0] #0 1 If this bit is set, SPI_SS signals will be generated automatically by hardware. It means that device/slave select signal, which is set in SPI_SSR[0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 LTRIG_FLAG Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \n 5 1 read-write 0 Transferred bit length of one transaction does not meet the specified requirement #0 1 Transferred bit length meets the specified requirement which defined in TX_BIT_LEN. Note: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning #1 SSR Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared\n 0 1 read-write 0 Set the SPIx_SS pin to inactive state.\nKeep the SPIx_SS pin to inactive state #0 1 Set the SPIx_SS pin to active state.\nSelect the SPIx_SS pin to be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SS_LVL #1 SS_LTRIG Slave Select Level Trigger Enable Bit (Slave Only)\n 4 1 read-write 0 Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge #0 1 Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high #1 SS_LVL Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS).\n 2 1 read-write 0 The slave select signal SPI_SS is active on low-level/falling-edge #0 1 The slave select signal SPI_SS is active on high-level/rising-edge #1 SPI_STATUS SPI_STATUS SPI Status Register 0x44 -1 read-write n 0x0 0x0 IF SPI Unit Transfer Interrupt Flag\nA mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself. 16 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[24].\n 24 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RX_FIFO_COUNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 12 4 read-only RX_FULL Receive FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[25].\n 25 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RX_INTSTS Receive FIFO Threshold Interrupt Status (Read Only)\n 0 1 read-only 0 The valid data count within the receive FIFO buffer is less than or equal to the setting value of RX_THRESHOLD #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD #1 RX_OVERRUN Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. 2 1 read-write 0 Receive FIFO does not overrun #0 1 Receive FIFO overruns #1 SLV_START_INTSTS Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n 11 1 read-write 0 Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1. The transfer is not started #0 1 A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit #1 TIMEOUT Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 20 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[26].\n 26 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TX_FIFO_COUNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[27].\n 27 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TX_INTSTS Transmit FIFO Threshold Interrupt Status (Read Only)\n 4 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD #1 SPI_TX SPI_TX Data Transmit Register 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe Data Transmit Register holds the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field TX_BIT_LEN in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bit field TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1 0 32 write-only SYST SYST Register Map SYST 0x0 0x0 0xC registers n CSR SYST_CSR SysTick Control and Status Register 0x0 read-write n 0x0 0x0 CLKSRC System Tick Clock Source Selection\n 2 1 read-write 0 Clock source is optional, refer to STCLK_S (CLKSEL0[5:3]) #0 1 Core clock used for SysTick timer #1 COUNTFLAG System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register (SYST_CVR). 16 1 read-write ENABLE System Tick Counter Enable Bit\n 0 1 read-write 0 SysTick counter Disabled #0 1 SysTick counter Enabled #1 TICKINT System Tick Interrupt Enabled\n 1 1 read-write 0 Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to 0 has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a write in software will not cause SysTick to be pended #1 CVR SYST_CVR SysTick Current Value Register 0x8 read-write n 0x0 0x0 CURRENT System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. 0 24 read-write RVR SYST_RVR SysTick Reload Value Register 0x4 read-write n 0x0 0x0 RELOAD System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0. 0 24 read-write TMR01 TMR Register Map TMR 0x0 0x0 0x1C registers n 0x20 0x1C registers n TCAP0 TCAP0 Timer0 Capture Data Register 0x10 read-only n 0x0 0x0 TCAP Timer Capture Data Register\n 0 24 read-only TCAP1 TCAP1 Timer1 Capture Data Register 0x30 read-write n 0x0 0x0 TCMPR0 TCMPR0 Timer0 Compare Register 0x4 read-write n 0x0 0x0 TCMP Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF (TISR[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest TCMP value to be the timer compared value while user writes a new value into TCMP field. 0 24 read-write TCMPR1 TCMPR1 Timer1 Compare Register 0x24 read-write n 0x0 0x0 TCSR0 TCSR0 Timer0 Control and Status Register 0x0 -1 read-write n 0x0 0x0 CACT Timer Active Status Bit (Read Only)\nThis bit indicates the up-timer status.\n 25 1 read-only 0 Timer is not active #0 1 Timer is active #1 CEN Timer Enable Bit\n 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 CRST Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value TDR and also force CEN (TCSR[30]) to 0 if CACT (TCSR[25]) is 1.\n 26 1 read-write 0 No effect #0 1 Reset internal 8-bit prescale counter, 24-bit up counter value and CEN bit #1 CTB Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \n 24 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 DBGACK_TMR ICE Debug Mode Acknowledge Disable (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the REGWRPROT register. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 IE Interrupt Enable Bit\nNote: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 MODE Timer Counting Mode Select\n 27 2 read-write 0 The Timer controller is operated in One-shot mode #00 1 The Timer controller is operated in Periodic mode #01 2 The Timer controller is operated in Toggle-output mode #10 3 The Timer controller is operated in Continuous Counting mode #11 PRESCALE Prescale Counter\n 0 8 read-write TDR_EN Data Load Enable Bit\nWhen this bit is set, timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n 16 1 read-write 0 Timer Data Register update Disabled #0 1 Timer Data Register update Enabled while timer counter is active #1 TCSR1 TCSR1 Timer1 Control and Status Register 0x20 read-write n 0x0 0x0 TDR0 TDR0 Timer0 Data Register 0xC read-only n 0x0 0x0 TDR Timer Data Register\nIf CTB (TCSR[24] ) is 0, user can read TDR value for getting current 24- bit counter value .\nIf CTB (TCSR[24] ) is 1, user can read TDR value for getting current 24- bit event input counter value. 0 24 read-only TDR1 TDR1 Timer1 Data Register 0x2C read-write n 0x0 0x0 TEXCON0 TEXCON0 Timer0 External Control Register 0x14 read-write n 0x0 0x0 RSTCAPSEL Capture Function Selection\n 4 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 TCDB Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. 7 1 read-write 0 TMx (x= 0~3) pin de-bounce Disabled #0 1 TMx (x= 0~3) pin de-bounce Enabled #1 TEXDB Timer External Capture Pin De-bounce Enable Bit \nNote: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. 6 1 read-write 0 TMx (x= 0~3) pin de-bounce Disabled #0 1 TMx (x= 0~3) pin de-bounce Enabled #1 TEXEN Timer External Capture Pin Enable Bit\nThis bit enables the TMx pin. \n 3 1 read-write 0 TMx (x= 0~3) pin Disabled #0 1 TMx (x= 0~3) pin Enabled #1 TEXIEN Timer External Capture Interrupt Enable Bit\n 5 1 read-write 0 TMx (x= 0~3) pin detection Interrupt Disabled #0 1 TMx (x= 0~3) pin detection Interrupt Enabled #1 TEX_EDGE Timer External Capture Pin Edge Detect\n 1 2 read-write 0 A Falling edge on TMx (x= 0~3) pin will be detected #00 1 A Rising edge on TMx (x= 0~3) pin will be detected #01 2 Either Rising or Falling edge on TMx (x= 0~3) pin will be detected #10 3 Reserved #11 TX_PHASE Timer External Count Phase \n 0 1 read-write 0 A Falling edge of external counting pin will be counted #0 1 A Rising edge of external counting pin will be counted #1 TEXCON1 TEXCON1 Timer1 External Control Register 0x34 read-write n 0x0 0x0 TEXISR0 TEXISR0 Timer0 External Interrupt Status Register 0x18 read-write n 0x0 0x0 TEXIF Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the TEXIF status. If the above condition occurred, the Timer will keep register TCAP unchanged and drop the new capture value. 0 1 read-write 0 TMx (x= 0~3) pin interrupt did not occur #0 1 TMx (x= 0~3) pin interrupt occurred #1 TEXISR1 TEXISR1 Timer1 External Interrupt Status Register 0x38 read-write n 0x0 0x0 TISR0 TISR0 Timer0 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter TDR value reaches to TCMP (TCMPR[23:0]) value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 TDR value matches the TCMP value #1 TISR1 TISR1 Timer1 Interrupt Status Register 0x28 read-write n 0x0 0x0 TMR23 TMR Register Map TMR 0x0 0x0 0x1C registers n 0x20 0x1C registers n TCAP2 TCAP2 Timer2 Capture Data Register 0x10 read-only n 0x0 0x0 TCAP Timer Capture Data Register\n 0 24 read-only TCAP3 TCAP3 Timer3 Capture Data Register 0x30 read-write n 0x0 0x0 TCMPR2 TCMPR2 Timer2 Compare Register 0x4 read-write n 0x0 0x0 TCMP Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF (TISR[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest TCMP value to be the timer compared value while user writes a new value into TCMP field. 0 24 read-write TCMPR3 TCMPR3 Timer3 Compare Register 0x24 read-write n 0x0 0x0 TCSR2 TCSR2 Timer2 Control and Status Register 0x0 -1 read-write n 0x0 0x0 CACT Timer Active Status Bit (Read Only)\nThis bit indicates the up-timer status.\n 25 1 read-only 0 Timer is not active #0 1 Timer is active #1 CEN Timer Enable Bit\n 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 CRST Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value TDR and also force CEN (TCSR[30]) to 0 if CACT (TCSR[25]) is 1.\n 26 1 read-write 0 No effect #0 1 Reset internal 8-bit prescale counter, 24-bit up counter value and CEN bit #1 CTB Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \n 24 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 DBGACK_TMR ICE Debug Mode Acknowledge Disable (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the REGWRPROT register. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 IE Interrupt Enable Bit\nNote: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 MODE Timer Counting Mode Select\n 27 2 read-write 0 The Timer controller is operated in One-shot mode #00 1 The Timer controller is operated in Periodic mode #01 2 The Timer controller is operated in Toggle-output mode #10 3 The Timer controller is operated in Continuous Counting mode #11 PRESCALE Prescale Counter\n 0 8 read-write TDR_EN Data Load Enable Bit\nWhen this bit is set, timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n 16 1 read-write 0 Timer Data Register update Disabled #0 1 Timer Data Register update Enabled while timer counter is active #1 TCSR3 TCSR3 Timer3 Control and Status Register 0x20 read-write n 0x0 0x0 TDR2 TDR2 Timer2 Data Register 0xC read-only n 0x0 0x0 TDR Timer Data Register\nIf CTB (TCSR[24] ) is 0, user can read TDR value for getting current 24- bit counter value .\nIf CTB (TCSR[24] ) is 1, user can read TDR value for getting current 24- bit event input counter value. 0 24 read-only TDR3 TDR3 Timer3 Data Register 0x2C read-write n 0x0 0x0 TEXCON2 TEXCON2 Timer2 External Control Register 0x14 read-write n 0x0 0x0 RSTCAPSEL Capture Function Selection\n 4 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 TCDB Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. 7 1 read-write 0 TMx (x= 0~3) pin de-bounce Disabled #0 1 TMx (x= 0~3) pin de-bounce Enabled #1 TEXDB Timer External Capture Pin De-bounce Enable Bit \nNote: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. 6 1 read-write 0 TMx (x= 0~3) pin de-bounce Disabled #0 1 TMx (x= 0~3) pin de-bounce Enabled #1 TEXEN Timer External Capture Pin Enable Bit\nThis bit enables the TMx pin. \n 3 1 read-write 0 TMx (x= 0~3) pin Disabled #0 1 TMx (x= 0~3) pin Enabled #1 TEXIEN Timer External Capture Interrupt Enable Bit\n 5 1 read-write 0 TMx (x= 0~3) pin detection Interrupt Disabled #0 1 TMx (x= 0~3) pin detection Interrupt Enabled #1 TEX_EDGE Timer External Capture Pin Edge Detect\n 1 2 read-write 0 A Falling edge on TMx (x= 0~3) pin will be detected #00 1 A Rising edge on TMx (x= 0~3) pin will be detected #01 2 Either Rising or Falling edge on TMx (x= 0~3) pin will be detected #10 3 Reserved #11 TX_PHASE Timer External Count Phase \n 0 1 read-write 0 A Falling edge of external counting pin will be counted #0 1 A Rising edge of external counting pin will be counted #1 TEXCON3 TEXCON3 Timer3 External Control Register 0x34 read-write n 0x0 0x0 TEXISR2 TEXISR2 Timer2 External Interrupt Status Register 0x18 read-write n 0x0 0x0 TEXIF Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the TEXIF status. If the above condition occurred, the Timer will keep register TCAP unchanged and drop the new capture value. 0 1 read-write 0 TMx (x= 0~3) pin interrupt did not occur #0 1 TMx (x= 0~3) pin interrupt occurred #1 TEXISR3 TEXISR3 Timer3 External Interrupt Status Register 0x38 read-write n 0x0 0x0 TISR2 TISR2 Timer2 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter TDR value reaches to TCMP (TCMPR[23:0]) value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 TDR value matches the TCMP value #1 TISR3 TISR3 Timer3 Interrupt Status Register 0x28 read-write n 0x0 0x0 UART0 UART Register Map UART 0x0 0x0 0x3C registers n UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ADDR_MATCH Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write LIN_BKFL UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1.\n 0 4 read-write LIN_RX_EN LIN RX Enable Bit\n 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LIN_TX_EN LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485_AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485_ADD_EN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This field is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 RS485_AUD RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation mode (AUO) Disabled #0 1 RS-485 Auto Direction Operation mode (AUO) Enabled #1 RS485_NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 -1 read-write n 0x0 0x0 BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation.\nNote: The detail description is shown in UART Controller Baud Rate Generator section. 0 16 read-write DIVIDER_X Divider X\nNote 1: This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2.\nNote 2: The detail description is shown in UART Controller Baud Rate Generator section. 24 4 read-write DIV_X_EN Divider X Enable Bit\nNote1: The detail description is shown in UART Controller Baud Rate Generator section.\nNote2: In IrDA mode, this bit must disable. 29 1 read-write 0 Divider X Disabled (the equation of M = 16) #0 1 Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 DIV_X_ONE Divider X Equal to 1\nNote: The detail description is shown in UART Controller Baud Rate Generator section. 28 1 read-write 0 Divider M = X+1 (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 #1 UA_FCR UA_FCR UART FIFO Control Register 0x8 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDA_IF will be set (if RDA_IEN(UA_IER [0]) enabled, and an interrupt will be generated).\n 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RFR RX Field Software Reset\nWhen RFR is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 RTS_TRI_LEV nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RX_DIS Receiver Disable Register\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485_NMM (UA_ALT_CSR [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 TFR TX Field Software Reset\nWhen TFR is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UA_FSR UA_FSR UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 BIF Break Error Interrupt Flag This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). Note: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break error is generated #0 1 Break error is generated #1 FEF Frame Error Flag This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0). Note: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No frame error is generated #0 1 Frame error is generated #1 PEF Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RS485_ADD_DETF RS-485 Address Byte Detection Flag \nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 RX_EMPTY Receiver FIFO Empty (Read Only)\nThis bit indicates RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RX_FULL Receiver FIFO Full (Read Only)\nThis bit indicates RX FIFO is full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RX_OVER_IF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, this bit will be set.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RX_POINTER RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15. When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 15. 8 6 read-only TE_FLAG Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has not been transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TX_EMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UA_THR (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TX_FULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TX_OVER_IF TX Overflow Error Interrupt Flag\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TX_POINTER TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15. When the using level of TX FIFO Buffer equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 15. 16 6 read-only UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUN_SEL Function Select Enable Bit\n 0 2 read-write 0 UART function Enabled #00 1 LIN function Enabled #01 2 IrDA function Enabled #10 3 RS-485 function Enabled #11 UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 AUTO_CTS_EN nCTS Auto Flow Control Enable Bit\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 AUTO_RTS_EN nRTS Auto Flow Control Enable Bit\nWhen nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUF_ERR_IEN Buffer Error Interrupt Enable Bit\n 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LIN_IEN LIN Bus Interrupt Enable Bit\nNote: This field is used for LIN function mode. 8 1 read-write 0 Lin bus interrupt Disabled #0 1 Lin bus interrupt Enabled #1 MODEM_IEN Modem Status Interrupt Enable Bit\n 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDA_IEN Receive Data Available Interrupt Enable Bit\n 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLS_IEN Receive Line Status Interrupt Enable Bit\n 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 THRE_IEN Transmit Holding Register Empty Interrupt Enable Bit\n 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TIME_OUT_EN Receive Buffer Time Out Counter Enable Bit\n 11 1 read-write 0 Receive Buffer time out counter Disabled #0 1 Receive Buffer time out counter Enabled #1 TOUT_IEN RX Time Out Interrupt Enable Bit\n 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 WAKE_EN UART Wake-up Function Enable Bit\n 6 1 read-write 0 UART wake-up function Disabled #0 1 UART wake-up function Enabled, when the chip is in Power-down mode, an external nCTS change will wake-up chip from Power-down mode #1 UA_IRCR UA_IRCR UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 INV_RX IrDA Inverse Receive Input Signal\n 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 INV_TX IrDA Inverse Transmitting Output Signal\n 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 TX_SELECT IrDA Receiver/Transmitter Selection Enable Bit\n 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 UA_ISR UA_ISR UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 BUF_ERR_IF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set. When BUF_ERR_IF (UA_ISR[5]) is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RX_OVER_IF (UA_FSR[0]) and TX_OVER_IF (UA_FSR[24]) are cleared to 0 by writing 1 to RX_OVER_IF (UA_FSR[0]) and TX_OVER_IF (UA_FSR[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUF_ERR_INT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN (UA_IER[5]) and BUF_ERR_IF (UA_ISR[5]) are both set to 1.\n 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 LIN_IF LIN Bus Flag (Read Only)\nNote: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]), LIN_BKDET_F (UA_LIN_SR[8]), BIT_ERR_F (UA_LIN_SR[9]), LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all are cleared. 7 1 read-only 0 None of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #0 1 At least one of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #1 LIN_INT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF (UA_ISR[7]) are both set to 1.\n 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEM_IF MODEM Interrupt Flag (Read Only)\nNote: This bit is reset to 0 when bit DCTSF (UA_MSR[0]) is cleared by a write 1 on DCTSF (UA_MSR[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEM_INT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEM_IEN (UA_IER[3]) and MODEM_IF (UA_ISR[3]) are both set to 1.\n 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDA_IF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL (UA_FCR[7:4]) then the RDA_IF (UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL (UA_FCR[7:4])). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDA_INT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLS_IF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UA_FSR[6]), FEF (UA_FSR[5]) and PEF (UA_FSR[4]), is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated. Note2: This bit is read only and reset to 0 when all bits of BIF (UA_FSR[6]), FEF (UA_FSR[5]) and PEF (UA_FSR[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLS_INT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2] and RLS_IF (UA_ISR[2]) are both set to 1.\n 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 THRE_IF Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER [1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THRE_INT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1]) and THRE_IF (UA_ISR[1]) are both set to 1.\n 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TOUT_IF Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC (UA_TOR[7:0]). If TOUT_IEN (UA_IER [4]) is enabled, the time-out interrupt will be generated. \nNote: User can read UA_RBR (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 TOUT_INT Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN (UA_IER[4]) and TOUT_IF (UA_ISR[4]) are both set to 1.\n 12 1 read-only 0 No time-out interrupt is generated #0 1 Time-out interrupt is generated #1 UA_LCR UA_LCR UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote: This bit has effect only when PBE (UA_LCR[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of STOP Bit 2 1 read-write 0 One STOP bit is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-,7- and 8-bit word length, 2 STOP bit is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 No parity bit #0 1 Parity bit generated Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 WLS Word Length Selection\n 0 2 read-write 0 character length is 5-bit #00 1 character length is 6-bit #01 2 character length is 7-bit #10 3 character length is 8-bit #11 UA_LIN_CTL UA_LIN_CTL UART LIN Control Register 0x34 -1 read-write n 0x0 0x0 BIT_ERR_EN Bit Error Detect Enable Bit\n 12 1 read-write 0 Bit error detection function Disabled #0 1 Bit error detection Enabled #1 LINS_ARS_EN LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (DIV_X_EN (UA_BAUD [29]) and DIV_X_ONE (UA_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.12.5.9.4 (Slave mode with automatic resynchronization). 2 1 read-write 0 LIN automatic resynchronization Disabled #0 1 LIN automatic resynchronization Enabled #1 LINS_DUM_EN LIN Slave Divider Update Method Enable Bit\nNote2: This bit is used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.12.5.9.4 (Slave mode with automatic resynchronization). 3 1 read-write 0 UA_BAUD updated is writing by software (if no automatic resynchronization update occurs at the same time) #0 1 UA_BAUD is updated at the next received character. User must set the bit before checksum reception #1 LINS_EN LIN Slave Mode Enable Bit\n 0 1 read-write 0 LIN slave mode Disabled #0 1 LIN slave mode Enabled #1 LINS_HDET_EN LIN Slave Header Detection Enable Bit\n 1 1 read-write 0 LIN slave header detection Disabled #0 1 LIN slave header detection Enabled #1 LIN_BKDET_EN LIN Break Detection Enable Bit\n 10 1 read-write 0 LIN break detection Disabled #0 1 LIN break detection Enabled #1 LIN_BKFL LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL (UA_ALT_CSR[19:16]), User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16]).\nNote2: This break field length is LIN_BKFL + 1.\n 16 4 read-write LIN_BS_LEN LIN Break/Sync Delimiter Length\n\nNote: This bit is used for LIN master to sending header field. 20 2 read-write 0 The LIN break/sync delimiter length is 1 bit time #00 2 The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time #10 3 The LIN break/sync delimiter length is 4 bit time #11 LIN_HEAD_SEL LIN Header Select\n 22 2 read-write 0 The LIN header includes break field #00 1 The LIN header includes break field and sync field #01 2 The LIN header includes break field , sync field and frame ID field #10 3 Reserved #11 LIN_IDPEN LIN ID Parity Enable Bit\n 9 1 read-write 0 LIN frame ID parity Disabled #0 1 LIN frame ID parity Enabled #1 LIN_MUTE_EN LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in LIN slave mode. 4 1 read-write 0 LIN mute mode Disabled #0 1 LIN mute mode Enabled #1 LIN_PID LIN PID Register\nThis field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on LIN_IDPEN (UA_LIN_CTL[9]). \n\nNote1: User can filled any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode. 24 8 read-write LIN_RX_DIS LIN Receiver Disable Bit\n 11 1 read-write 0 LIN receiver Enabled #0 1 LIN receiver Disabled #1 LIN_SHD LIN TX Send Header Enable Bit The LIN TX header can be break field or break and sync field or break, sync and frame ID field , it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]). Note1: These registers are shadow registers of LIN_TX_EN (UA_ALT_CSR[7]) user can read/write it by setting LIN_TX_EN (UA_ALT_CSR[7]) or LIN_SHD (UA_LIN_CTL[8]). Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by LIN_HEAD_SEL (UA_LIN_CTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 8 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 UA_LIN_SR UA_LIN_SR UART LIN Status Register 0x38 read-write n 0x0 0x0 BIT_ERR_F Bit Error Detect Status Flag\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F (UA_LIN_SR[9]) will be set.\n 9 1 read-write LINS_HDET_F LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n 0 1 read-write 0 LIN header not detected #0 1 LIN header detected (break + sync + frame ID) #1 LINS_HERR_F LIN Slave Header Error Flag This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include break delimiter is too short , frame error in sync field or Identifier field , sync field data is not 0x55 without automatic resynchronization mode , sync field deviation error with automatic resynchronization mode , sync field measure time-out with automatic resynchronization mode and LIN header reception time-out . 1 1 read-write 0 LIN header error not detected #0 1 LIN header error detected #1 LINS_IDPERR_F LIN Slave ID Parity Error Flag\nThis bit is set by hardware when receipted frame ID parity is not correct.\n 2 1 read-write 0 no active #0 1 Receipted frame ID parity is not correct #1 LINS_SYNC_F LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in automatic resynchronization mode. When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is cleared by writing 1 to it.\nNote3: When user writing 1 to it, hardware will reload the initial baud-rate and re-search new frame header. 3 1 read-write 0 The current character is not at LIN sync state #0 1 The current character is at LIN sync state #1 LIN_BKDET_F LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it.\n 8 1 read-write 0 LIN break not detected #0 1 LIN break detected #1 UA_MCR UA_MCR UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 LEV_RTS nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 678 and Figure 679 for UART function mode.\nNote2: Refer to Figure 682 and Figure 683 for RS-485 function mode. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTS nRTS (Request-to-send) Signal\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with LEV_RTS bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTS_ST nRTS Pin State (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.\n 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UA_MSR UA_MSR UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTS_ST nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is low level voltage logic state #1 DCTSF Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER[3]) is set to 1.\nWrite 1 to clear this bit to 0 0 1 read-write LEV_CTS nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\n 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from UART_RXD pin (LSB first). 0 8 read-only UA_THR UA_THR UART Transmit Holding Register UA_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD pin. (LSB first) 0 8 write-only UA_TOR UA_TOR UART Time Out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time Out Interrupt Comparator\n 0 8 read-write UART1 UART Register Map UART 0x0 0x0 0x3C registers n UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ADDR_MATCH Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write LIN_BKFL UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1.\n 0 4 read-write LIN_RX_EN LIN RX Enable Bit\n 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LIN_TX_EN LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485_AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485_ADD_EN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This field is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 RS485_AUD RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation mode (AUO) Disabled #0 1 RS-485 Auto Direction Operation mode (AUO) Enabled #1 RS485_NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 -1 read-write n 0x0 0x0 BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation.\nNote: The detail description is shown in UART Controller Baud Rate Generator section. 0 16 read-write DIVIDER_X Divider X\nNote 1: This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2.\nNote 2: The detail description is shown in UART Controller Baud Rate Generator section. 24 4 read-write DIV_X_EN Divider X Enable Bit\nNote1: The detail description is shown in UART Controller Baud Rate Generator section.\nNote2: In IrDA mode, this bit must disable. 29 1 read-write 0 Divider X Disabled (the equation of M = 16) #0 1 Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 DIV_X_ONE Divider X Equal to 1\nNote: The detail description is shown in UART Controller Baud Rate Generator section. 28 1 read-write 0 Divider M = X+1 (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 #1 UA_FCR UA_FCR UART FIFO Control Register 0x8 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDA_IF will be set (if RDA_IEN(UA_IER [0]) enabled, and an interrupt will be generated).\n 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RFR RX Field Software Reset\nWhen RFR is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 RTS_TRI_LEV nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RX_DIS Receiver Disable Register\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485_NMM (UA_ALT_CSR [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 TFR TX Field Software Reset\nWhen TFR is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UA_FSR UA_FSR UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 BIF Break Error Interrupt Flag This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). Note: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break error is generated #0 1 Break error is generated #1 FEF Frame Error Flag This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0). Note: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No frame error is generated #0 1 Frame error is generated #1 PEF Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RS485_ADD_DETF RS-485 Address Byte Detection Flag \nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 RX_EMPTY Receiver FIFO Empty (Read Only)\nThis bit indicates RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RX_FULL Receiver FIFO Full (Read Only)\nThis bit indicates RX FIFO is full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RX_OVER_IF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, this bit will be set.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RX_POINTER RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15. When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 15. 8 6 read-only TE_FLAG Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has not been transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TX_EMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UA_THR (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TX_FULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TX_OVER_IF TX Overflow Error Interrupt Flag\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TX_POINTER TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15. When the using level of TX FIFO Buffer equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 15. 16 6 read-only UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUN_SEL Function Select Enable Bit\n 0 2 read-write 0 UART function Enabled #00 1 LIN function Enabled #01 2 IrDA function Enabled #10 3 RS-485 function Enabled #11 UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 AUTO_CTS_EN nCTS Auto Flow Control Enable Bit\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 AUTO_RTS_EN nRTS Auto Flow Control Enable Bit\nWhen nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUF_ERR_IEN Buffer Error Interrupt Enable Bit\n 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LIN_IEN LIN Bus Interrupt Enable Bit\nNote: This field is used for LIN function mode. 8 1 read-write 0 Lin bus interrupt Disabled #0 1 Lin bus interrupt Enabled #1 MODEM_IEN Modem Status Interrupt Enable Bit\n 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDA_IEN Receive Data Available Interrupt Enable Bit\n 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLS_IEN Receive Line Status Interrupt Enable Bit\n 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 THRE_IEN Transmit Holding Register Empty Interrupt Enable Bit\n 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TIME_OUT_EN Receive Buffer Time Out Counter Enable Bit\n 11 1 read-write 0 Receive Buffer time out counter Disabled #0 1 Receive Buffer time out counter Enabled #1 TOUT_IEN RX Time Out Interrupt Enable Bit\n 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 WAKE_EN UART Wake-up Function Enable Bit\n 6 1 read-write 0 UART wake-up function Disabled #0 1 UART wake-up function Enabled, when the chip is in Power-down mode, an external nCTS change will wake-up chip from Power-down mode #1 UA_IRCR UA_IRCR UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 INV_RX IrDA Inverse Receive Input Signal\n 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 INV_TX IrDA Inverse Transmitting Output Signal\n 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 TX_SELECT IrDA Receiver/Transmitter Selection Enable Bit\n 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 UA_ISR UA_ISR UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 BUF_ERR_IF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set. When BUF_ERR_IF (UA_ISR[5]) is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RX_OVER_IF (UA_FSR[0]) and TX_OVER_IF (UA_FSR[24]) are cleared to 0 by writing 1 to RX_OVER_IF (UA_FSR[0]) and TX_OVER_IF (UA_FSR[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUF_ERR_INT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN (UA_IER[5]) and BUF_ERR_IF (UA_ISR[5]) are both set to 1.\n 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 LIN_IF LIN Bus Flag (Read Only)\nNote: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]), LIN_BKDET_F (UA_LIN_SR[8]), BIT_ERR_F (UA_LIN_SR[9]), LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all are cleared. 7 1 read-only 0 None of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #0 1 At least one of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #1 LIN_INT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF (UA_ISR[7]) are both set to 1.\n 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEM_IF MODEM Interrupt Flag (Read Only)\nNote: This bit is reset to 0 when bit DCTSF (UA_MSR[0]) is cleared by a write 1 on DCTSF (UA_MSR[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEM_INT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEM_IEN (UA_IER[3]) and MODEM_IF (UA_ISR[3]) are both set to 1.\n 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDA_IF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL (UA_FCR[7:4]) then the RDA_IF (UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL (UA_FCR[7:4])). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDA_INT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLS_IF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UA_FSR[6]), FEF (UA_FSR[5]) and PEF (UA_FSR[4]), is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated. Note2: This bit is read only and reset to 0 when all bits of BIF (UA_FSR[6]), FEF (UA_FSR[5]) and PEF (UA_FSR[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLS_INT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2] and RLS_IF (UA_ISR[2]) are both set to 1.\n 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 THRE_IF Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER [1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THRE_INT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1]) and THRE_IF (UA_ISR[1]) are both set to 1.\n 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TOUT_IF Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC (UA_TOR[7:0]). If TOUT_IEN (UA_IER [4]) is enabled, the time-out interrupt will be generated. \nNote: User can read UA_RBR (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 TOUT_INT Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN (UA_IER[4]) and TOUT_IF (UA_ISR[4]) are both set to 1.\n 12 1 read-only 0 No time-out interrupt is generated #0 1 Time-out interrupt is generated #1 UA_LCR UA_LCR UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote: This bit has effect only when PBE (UA_LCR[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of STOP Bit 2 1 read-write 0 One STOP bit is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-,7- and 8-bit word length, 2 STOP bit is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 No parity bit #0 1 Parity bit generated Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 WLS Word Length Selection\n 0 2 read-write 0 character length is 5-bit #00 1 character length is 6-bit #01 2 character length is 7-bit #10 3 character length is 8-bit #11 UA_LIN_CTL UA_LIN_CTL UART LIN Control Register 0x34 -1 read-write n 0x0 0x0 BIT_ERR_EN Bit Error Detect Enable Bit\n 12 1 read-write 0 Bit error detection function Disabled #0 1 Bit error detection Enabled #1 LINS_ARS_EN LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (DIV_X_EN (UA_BAUD [29]) and DIV_X_ONE (UA_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.12.5.9.4 (Slave mode with automatic resynchronization). 2 1 read-write 0 LIN automatic resynchronization Disabled #0 1 LIN automatic resynchronization Enabled #1 LINS_DUM_EN LIN Slave Divider Update Method Enable Bit\nNote2: This bit is used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.12.5.9.4 (Slave mode with automatic resynchronization). 3 1 read-write 0 UA_BAUD updated is writing by software (if no automatic resynchronization update occurs at the same time) #0 1 UA_BAUD is updated at the next received character. User must set the bit before checksum reception #1 LINS_EN LIN Slave Mode Enable Bit\n 0 1 read-write 0 LIN slave mode Disabled #0 1 LIN slave mode Enabled #1 LINS_HDET_EN LIN Slave Header Detection Enable Bit\n 1 1 read-write 0 LIN slave header detection Disabled #0 1 LIN slave header detection Enabled #1 LIN_BKDET_EN LIN Break Detection Enable Bit\n 10 1 read-write 0 LIN break detection Disabled #0 1 LIN break detection Enabled #1 LIN_BKFL LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL (UA_ALT_CSR[19:16]), User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16]).\nNote2: This break field length is LIN_BKFL + 1.\n 16 4 read-write LIN_BS_LEN LIN Break/Sync Delimiter Length\n\nNote: This bit is used for LIN master to sending header field. 20 2 read-write 0 The LIN break/sync delimiter length is 1 bit time #00 2 The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time #10 3 The LIN break/sync delimiter length is 4 bit time #11 LIN_HEAD_SEL LIN Header Select\n 22 2 read-write 0 The LIN header includes break field #00 1 The LIN header includes break field and sync field #01 2 The LIN header includes break field , sync field and frame ID field #10 3 Reserved #11 LIN_IDPEN LIN ID Parity Enable Bit\n 9 1 read-write 0 LIN frame ID parity Disabled #0 1 LIN frame ID parity Enabled #1 LIN_MUTE_EN LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in LIN slave mode. 4 1 read-write 0 LIN mute mode Disabled #0 1 LIN mute mode Enabled #1 LIN_PID LIN PID Register\nThis field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on LIN_IDPEN (UA_LIN_CTL[9]). \n\nNote1: User can filled any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode. 24 8 read-write LIN_RX_DIS LIN Receiver Disable Bit\n 11 1 read-write 0 LIN receiver Enabled #0 1 LIN receiver Disabled #1 LIN_SHD LIN TX Send Header Enable Bit The LIN TX header can be break field or break and sync field or break, sync and frame ID field , it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]). Note1: These registers are shadow registers of LIN_TX_EN (UA_ALT_CSR[7]) user can read/write it by setting LIN_TX_EN (UA_ALT_CSR[7]) or LIN_SHD (UA_LIN_CTL[8]). Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by LIN_HEAD_SEL (UA_LIN_CTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 8 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 UA_LIN_SR UA_LIN_SR UART LIN Status Register 0x38 read-write n 0x0 0x0 BIT_ERR_F Bit Error Detect Status Flag\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F (UA_LIN_SR[9]) will be set.\n 9 1 read-write LINS_HDET_F LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n 0 1 read-write 0 LIN header not detected #0 1 LIN header detected (break + sync + frame ID) #1 LINS_HERR_F LIN Slave Header Error Flag This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include break delimiter is too short , frame error in sync field or Identifier field , sync field data is not 0x55 without automatic resynchronization mode , sync field deviation error with automatic resynchronization mode , sync field measure time-out with automatic resynchronization mode and LIN header reception time-out . 1 1 read-write 0 LIN header error not detected #0 1 LIN header error detected #1 LINS_IDPERR_F LIN Slave ID Parity Error Flag\nThis bit is set by hardware when receipted frame ID parity is not correct.\n 2 1 read-write 0 no active #0 1 Receipted frame ID parity is not correct #1 LINS_SYNC_F LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in automatic resynchronization mode. When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is cleared by writing 1 to it.\nNote3: When user writing 1 to it, hardware will reload the initial baud-rate and re-search new frame header. 3 1 read-write 0 The current character is not at LIN sync state #0 1 The current character is at LIN sync state #1 LIN_BKDET_F LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it.\n 8 1 read-write 0 LIN break not detected #0 1 LIN break detected #1 UA_MCR UA_MCR UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 LEV_RTS nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 678 and Figure 679 for UART function mode.\nNote2: Refer to Figure 682 and Figure 683 for RS-485 function mode. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTS nRTS (Request-to-send) Signal\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with LEV_RTS bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTS_ST nRTS Pin State (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.\n 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UA_MSR UA_MSR UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTS_ST nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is low level voltage logic state #1 DCTSF Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER[3]) is set to 1.\nWrite 1 to clear this bit to 0 0 1 read-write LEV_CTS nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\n 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from UART_RXD pin (LSB first). 0 8 read-only UA_THR UA_THR UART Transmit Holding Register UA_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD pin. (LSB first) 0 8 write-only UA_TOR UA_TOR UART Time Out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time Out Interrupt Comparator\n 0 8 read-write WDT WDT Register Map WDT 0x0 0x0 0x8 registers n WTCR WTCR WDT Control Register 0x0 -1 read-write n 0x0 0x0 DBGACK_WDT ICE Debug Mode Acknowledge Disable (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the REGWRPROT register. 31 1 read-write 0 ICE debug mode acknowledgement affects WDT counting #0 1 ICE debug mode acknowledgement Disabled #1 WTE WDT Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the REGWRPROT register.\nNote2: If CWDTEN (Config0[31]) bits is configure to 0, this bit is forced as 1 and user cannot change this bit to 0. 7 1 read-write 0 WDT Disabled (This action will reset the internal up counter value) #0 1 WDT Enabled #1 WTIE WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. \nNote: This bit is write protected. Refer to the REGWRPROT register. 6 1 read-write 0 WDT time-out interrupt Disabled #0 1 WDT time-out interrupt Enabled #1 WTIF WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it. 3 1 read-write 0 WDT time-out interrupt did not occur #0 1 WDT time-out interrupt occurred #1 WTIS WDT Time-out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\nNote: This bit is write protected. Refer to the REGWRPROT register. 8 3 read-write 0 24 * WDT_CLK #000 1 26 * WDT_CLK #001 2 28 * WDT_CLK #010 3 210 * WDT_CLK #011 4 212 * WDT_CLK #100 5 214 * WDT_CLK #101 6 216 * WDT_CLK #110 7 218 * WDT_CLK #111 WTR Reset WDT Up Counter (Write Protect)\nNote1: This bit is write protected. Refer to the REGWRPROT register.\nNote2: This bit will be automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Reset the internal 18-bit WDT up counter value #1 WTRE WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected. Refer to the REGWRPROT register. 1 1 read-write 0 WDT time-out reset function Disabled #0 1 WDT time-out reset function Enabled #1 WTRF WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it. 2 1 read-write 0 WDT time-out reset did not occur #0 1 WDT time-out reset occurred #1 WTWKE WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1, while WDT time-out interrupt flag IF (WTCR[3]) is generated to 1 and interrupt enable bit WTIE (WTCR[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote1: This bit is write protected. Refer to the REGWRPROT register.\nNote2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC). 4 1 read-write 0 Wake-up trigger event Disabled if WDT time-out interrupt signal generated #0 1 Wake-up trigger event Enabled if WDT time-out interrupt signal generated #1 WTWKF WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the interrupt wake-up flag status of WDT\nNote1: This bit is write protected. Refer to the REGWRPROT register.\nNote2: This bit is cleared by writing 1 to it. 5 1 read-write 0 WDT does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated #1 WTCRALT WTCRALT WDT Alternative Control Register 0x4 read-write n 0x0 0x0 WTRDSEL WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting WTR (WTCR[0]) to prevent WDT time-out reset happened. User can select a suitable setting of WTRDSEL for different WDT Reset Delay Period.\nNote1: This bit is write protected. Refer to the REGWRPROT register.\nNote2: This register will be reset to 0 if WDT time-out reset happened. 0 2 read-write 0 WDT Reset Delay Period is 1026 * WDT_CLK #00 1 WDT Reset Delay Period is 130 * WDT_CLK #01 2 WDT Reset Delay Period is 18 * WDT_CLK #10 3 WDT Reset Delay Period is 3 * WDT_CLK #11 WWDT WWDT Register Map WWDT 0x0 0x0 0x10 registers n WWDTCR WWDTCR WWDT Control Register 0x4 -1 read-write n 0x0 0x0 DBGACK_WWDT ICE Debug Mode Acknowledge Disable Control\nWWDT down counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects WWDT counting #0 1 ICE debug mode acknowledgement Disabled #1 PERIODSEL WWDT Counter Prescale Period Selection\n 8 4 read-write 0 Pre-scale is 1 Max time-out period is 1 * 64 * WWDT_CLK #0000 1 Pre-scale is 2 Max time-out period is 2 * 64 * WWDT_CLK #0001 2 Pre-scale is 4 Max time-out period is 4 * 64 * WWDT_CLK #0010 3 Pre-scale is 8 Max time-out period is 8 * 64 * WWDT_CLK #0011 4 Pre-scale is 16 Max time-out period is 16 * 64 * WWDT_CLK #0100 5 Pre-scale is 32 Max time-out period is 32 * 64 * WWDT_CLK #0101 6 Pre-scale is 64 Max time-out period is 64 * 64 * WWDT_CLK #0110 7 Pre-scale is 128 Max time-out period is 128 * 64 * WWDT_CLK #0111 8 Pre-scale is 192 Max time-out period is 192 * 64 * WWDT_CLK #1000 9 Pre-scale is 256 Max time-out period is 256 * 64 * WWDT_CLK #1001 10 Pre-scale is 384 Max time-out period is 384 * 64 * WWDT_CLK #1010 11 Pre-scale is 512 Max time-out period is 512 * 64 * WWDT_CLK #1011 12 Pre-scale is 768 Max time-out period is 768 * 64 * WWDT_CLK #1100 13 Pre-scale is 1024 Max time-out period is 1024 * 64 * WWDT_CLK #1101 14 Pre-scale is 1536 Max time-out period is 1536 * 64 * WWDT_CLK #1110 15 Pre-scale is 2048 Max time-out period is 2048 * 64 * WWDT_CLK #1111 WINCMP WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: User can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If user writes WWDTRLD when current WWDT counter value larger than WINCMP, WWDT reset signal will generate immediately. 16 6 read-write WWDTEN WWDT Enable Bit\nSet this bit to enable WWDT counter counting\n 0 1 read-write 0 WWDT counter is stopped #0 1 WWDT counter is starting counting #1 WWDTIE WWDT Interrupt Enable Bit\nIf this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.\n 1 1 read-write 0 WWDT counter compare match interrupt Disabled #0 1 WWDT counter compare match interrupt Enabled #1 WWDTCVR WWDTCVR WWDT Counter Value Register 0xC -1 read-only n 0x0 0x0 WWDTCVAL WWDT Counter Value\nWWDTCVAL will be updated continuously to monitor 6-bit down counter value. 0 6 read-only WWDTRLD WWDTRLD WWDT Reload Counter Register 0x0 write-only n 0x0 0x0 WWDTRLD WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. \nNote: User can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP (WWDTCR[21:16]). If user writes WWDTRLD when current WWDT counter value is larger than WINCMP, WWDT reset signal will generate immediately. 0 32 write-only WWDTSR WWDTSR WWDT Status Register 0x8 read-write n 0x0 0x0 WWDTIF WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches WINCMP (WWDTCR[21:16]).\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 WWDT counter value matches WINCMP value #1 WWDTRF WWDT Time-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 WWDT time-out reset did not occur #0 1 WWDT time-out reset occurred #1