nuvoTon M051AN_v1 2024.04.27 M051AN_v1 SVD file 8 32 ADC ADC Register Map ADC 0x0 0x0 0x38 registers n ADCALR ADCALR A/D Calibration Register 0x34 read-write n 0x0 0x0 CALDONE Calibration is Done (read only)\nWhen 0 is written to CALEN bit, CALDONE bit is cleared by hardware immediately. It is a read only bit. 1 1 read-only 0 A/D converter has not been calibrated or calibration is in progress if CALEN bit is set #0 1 A/D converter self calibration is done #1 CALEN Self Calibration Enable\nSoftware can set this bit to 1 enables A/D converter to do self calibration function. It needs 127 ADC clocks to complete calibration. This bit must be kept at 1 after CALDONE asserted. Clearing this bit will disable self calibration function. 0 1 read-write 0 Disable self calibration #0 1 Enable self calibration #1 ADCHER ADCHER A/D Channel Enable Register 0x24 read-write n 0x0 0x0 CHEN0 Analog Input Channel 0 Enable\n 0 1 read-write 0 Disable #0 1 Enable #1 CHEN1 Analog Input Channel 1 Enable\n 1 1 read-write 0 Disable #0 1 Enable #1 CHEN2 Analog Input Channel 2 Enable\n 2 1 read-write 0 Disable #0 1 Enable #1 CHEN3 Analog Input Channel 3 Enable\n 3 1 read-write 0 Disable #0 1 Enable #1 CHEN4 Analog Input Channel 4 Enable\n 4 1 read-write 0 Disable #0 1 Enable #1 CHEN5 Analog Input Channel 5 Enable\n 5 1 read-write 0 Disable #0 1 Enable #1 CHEN6 Analog Input Channel 6 Enable\n 6 1 read-write 0 Disable #0 1 Enable #1 CHEN7 Analog Input Channel 7 Enable\n 7 1 read-write 0 Disable #0 1 Enable #1 PRESEL Analog Input Channel 7 select\nNote:\nWhen software select the band-gap voltage as the analog input source of ADC channel 7, ADC clock rate needs to be limited to lower than 300 KHz. 8 2 read-write 0 External Analog Input #00 1 Internal Bandgap voltage #01 2 Reserved #10 3 Reserved #11 ADCMPR0 ADCMPR0 A/D Compare Register 0 0x28 read-write n 0x0 0x0 CMPCH Compare Channel Selection\n 3 3 read-write 0 Channel 0 conversion result is selected to be compared #000 1 Channel 1 conversion result is selected to be compared #001 2 Channel 2 conversion result is selected to be compared #010 3 Channel 3 conversion result is selected to be compared #011 4 Channel 4 conversion result is selected to be compared #100 5 Channel 5 conversion result is selected to be compared #101 6 Channel 6 conversion result is selected to be compared #110 7 Channel 7 conversion result is selected to be compared #111 CMPCOND Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set. 2 1 read-write 0 Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one #0 1 Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one #1 CMPD Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel. 16 12 read-write CMPEN Compare Enable\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register. 0 1 read-write 0 Disable compare function #0 1 Enable compare function #1 CMPIE Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated. 1 1 read-write 0 Disable compare function interrupt #0 1 Enable compare function interrupt #1 CMPMATCNT Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set. 8 4 read-write ADCMPR1 ADCMPR1 A/D Compare Register 1 0x2C read-write n 0x0 0x0 ADCR ADCR A/D Control Register 0x20 read-write n 0x0 0x0 ADEN A/D Converter Enable\nBefore starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption. 0 1 read-write 0 Disable #0 1 Enable #1 ADIE A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1. 1 1 read-write 0 Disable A/D interrupt function #0 1 Enable A/D interrupt function #1 ADMD A/D Converter Operation Mode When changing the operation mode, software should disable ADST bit firstly. Note: In Burst Mode, the A/D result data always at Data Register 0. 2 2 read-write 0 Single conversion #00 1 Burst conversion #01 2 Single-cycle scan #10 3 Continuous scan #11 ADST A/D Conversion Start\nADST bit can be set to 1 from two sources: software and external pin STADC. ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan and burst modes, A/D conversion is continuously performed until software write 0 to this bit or chip reset. 11 1 read-write 0 Conversion stopped and A/D converter enter idle state #0 1 Conversion start #1 DIFFEN Differential Input Mode Enable\n 10 1 read-write 0 single-end analog input mode #0 1 differential analog input mode #1 TRGCOND External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.\n 6 2 read-write 0 Low level #00 1 High level #01 2 Falling edge #10 3 Rising edge #11 TRGEN External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin.\nADC external trigger function is only supported in single-cycle scan mode. 8 1 read-write 0 Disable #0 1 Enable #1 TRGS Hardware Trigger Source\nSoftware should disable TRGEN and ADST before change TRGS. \nIn hardware trigger mode, the ADST bit is set by the external trigger from STADC. 4 2 read-write 0 A/D conversion is started by external STADC pin #00 ADDR0 ADDR0 A/D Data Register 0 0x0 read-only n 0x0 0x0 OVERRUN Over Run Flag (Read Only)\nIf converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after ADDR register is read. 16 1 read-only 0 Data in RSLT[11:0] is recent conversion result #0 1 Data in RSLT[11:0] is overwrite #1 RSLT A/D Conversion Result\nThis field contains conversion result of ADC. 0 12 read-only VALID Valid Flag \nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit 17 1 read-only 0 Data in RSLT[11:0] bits is not valid #0 1 Data in RSLT[11:0] bits is valid #1 ADDR1 ADDR1 A/D Data Register 1 0x4 read-write n 0x0 0x0 ADDR2 ADDR2 A/D Data Register 2 0x8 read-write n 0x0 0x0 ADDR3 ADDR3 A/D Data Register 3 0xC read-write n 0x0 0x0 ADDR4 ADDR4 A/D Data Register 4 0x10 read-write n 0x0 0x0 ADDR5 ADDR5 A/D Data Register 5 0x14 read-write n 0x0 0x0 ADDR6 ADDR6 A/D Data Register 6 0x18 read-write n 0x0 0x0 ADDR7 ADDR7 A/D Data Register 7 0x1C read-write n 0x0 0x0 ADSR ADSR A/D Status Register 0x30 read-write n 0x0 0x0 ADF A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these three conditions:\nWhen A/D conversion ends in single mode\nWhen A/D conversion ends on all specified channels in scan mode.\nWhen more than 4 samples in FIFO in Burst mode.\nThis flag can be cleared by writing 1 to self. 0 1 read-write BUSY BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.\nIt is read only. 3 1 read-write 0 A/D converter is in idle state #0 1 A/D converter is busy at conversion #1 CHANNEL Current Conversion Channel\nIt is read only. 4 3 read-write CMPF0 Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.\n 1 1 read-write 0 Conversion result in ADDR does not meet ADCMPR0setting #0 1 Conversion result in ADDR meets ADCMPR0setting #1 CMPF1 Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.\n 2 1 read-write 0 Conversion result in ADDR does not meet ADCMPR1 setting #0 1 Conversion result in ADDR meets ADCMPR1 setting #1 OVERRUN Over Run flag (Read Only)\nIt is a mirror to OVERRUN bit in ADDRx\nWhen ADC in Burst Mode, and the FIFO is overrun, OVERRUN[7:0] will all set to 1. 16 8 read-only VALID Data Valid flag (Read Only)\nIt is a mirror of VALID bit in ADDRx\nWhen ADC in Burst Mode, and the FIFO is valid, VALID[7:0] will all set to 1. 8 8 read-only CLK CLK Register Map CLK 0x0 0x0 0x28 registers n AHBCLK AHBCLK AHB Devices Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 EBI_EN EBI Controller Clock Enable Control.\n 3 1 read-write 0 Disable the EBI controller clock #0 1 Enable the EBI controller clock #1 ISP_EN Flash ISP Controller Clock Enable Control.\n 2 1 read-write 0 To disable the Flash ISP controller clock #0 1 To enable the Flash ISP controller clock #1 APBCLK APBCLK APB Devices Clock Enable Control Register 0x8 read-write n 0x0 0x0 ADC_EN Analog-Digital-Converter (ADC) Clock Enable\n 28 1 read-write 0 Disable ADC clock #0 1 Enable ADC clock #1 FDIV_EN Clock Divider Clock Enable\n 6 1 read-write 0 Disable FDIV Clock #0 1 Enable FDIV Clock #1 I2C_EN I2C Clock Enable \n 8 1 read-write 0 Disable I2C Clock #0 1 Enable I2C Clock #1 PWM01_EN PWM_01 Clock Enable\n 20 1 read-write 0 Disable PWM01 clock #0 1 Enable PWM01 clock #1 PWM23_EN PWM_23 Clock Enable\n 21 1 read-write 0 Disable PWM23 clock #0 1 Enable PWM23 clock #1 PWM45_EN PWM_45 Clock Enable\n 22 1 read-write 0 Disable PWM45 clock #0 1 Enable PWM45 clock #1 PWM67_EN PWM_67 Clock Enable\n 23 1 read-write 0 Disable PWM67 clock #0 1 Enable PWM67 clock #1 SPI0_EN SPI0 Clock Enable\n 12 1 read-write 0 Disable SPI0 Clock #0 1 Enable SPI0 Clock #1 SPI1_EN SPI1 Clock Enable\n 13 1 read-write 0 Disable SPI1 Clock #0 1 Enable SPI1 Clock #1 TMR0_EN Timer0 Clock Enable\n 2 1 read-write 0 Disable Timer0 Clock #0 1 Enable Timer0 Clock #1 TMR1_EN Timer1 Clock Enable\n 3 1 read-write 0 Disable Timer1 Clock #0 1 Enable Timer1 Clock #1 TMR2_EN Timer2 Clock Enable\n 4 1 read-write 0 Disable Timer2 Clock #0 1 Enable Timer2 Clock #1 TMR3_EN Timer3 Clock Enable\n 5 1 read-write 0 Disable Timer3 Clock #0 1 Enable Timer3 Clock #1 UART0_EN UART0 Clock Enable\n 16 1 read-write 0 Disable UART0 clock #0 1 Enable UART0 clock #1 UART1_EN UART1 Clock Enable\n 17 1 read-write 0 Disable UART1 clock #0 1 Enable UART1 clock #1 WDT_EN Watchdog Timer Clock Enable. This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 0 1 read-write 0 Disable Watchdog Timer Clock #0 1 Enable Watchdog Timer Clock #1 CLKDIV CLKDIV Clock Divider Number Register 0x18 read-write n 0x0 0x0 ADC_N ADC clock divide number from ADC clock source\n 16 8 read-write HCLK_N HCLK clock divide number from HCLK clock source\n 0 4 read-write UART_N UART clock divide number from UART clock source\n 8 4 read-write CLKSEL0 CLKSEL0 Clock Source Select Control Register 0 0x10 -1 read-write n 0x0 0x0 HCLK_S HCLK clock source select. Note: Before clock switching, the related clock sources (both pre-select and new-select) must be turn on The 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b. These bits are protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 0 3 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #000 1 Reserved\nClock source from internal 22.1184 MHz high speed oscillator clock #001 2 Clock source from PLL clock #010 3 Clock source from internal 10 kHz low speed oscillator clock #011 STCLK_S MCU Cortex_M0 SysTick clock source select. This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 3 3 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #000 1 Reserved\nClock source from internal 22.1184 MHz high speed oscillator clock/2 #001 2 Clock source from external 4~24 MHz high speed crystal clock/2 #010 3 Clock source from HCLK/2 #011 CLKSEL1 CLKSEL1 Clock Source Select Control Register 1 0x14 -1 read-write n 0x0 0x0 ADC_S ADC clock source select.\n 2 2 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #00 1 Clock source from PLL clock Clock source from internal 22.1184 MHz high speed oscillator clock #01 PWM01_S PWM0 and PWM1 clock source select.\nPWM0 and PWM1 uses the same Engine clock source, both of them use the same pre-scalar\n 28 2 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #00 1 Reserved #01 2 Clock source from HCLK #10 3 Clock source from internal 22.1184 MHz high speed oscillator clock #11 PWM23_S PWM2 and PWM3 clock source select.\nPWM2 and PWM3 uses the same Engine clock source, both of them use the same pre-scalar\n 30 2 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #00 1 Reserved #01 2 Clock source from HCLK #10 3 Clock source from internal 22.1184 MHz high speed oscillator clock #11 TMR0_S TIMER0 clock source select.\n 8 3 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #000 1 Reserved\nClock source from internal 22.1184 MHz high speed oscillator clock #001 2 Clock source from HCLK #010 3 Reserved #011 TMR1_S TIMER1 clock source select.\n 12 3 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #000 1 Reserved\nClock source from internal 22.1184 MHz high speed oscillator clock #001 2 Clock source from HCLK #010 3 Reserved #011 TMR2_S TIMER2 clock source select.\n 16 3 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #000 1 Reserved\nClock source from internal 22.1184 MHz high speed oscillator clock #001 2 Clock source from HCLK #010 3 Reserved #011 TMR3_S TIMER3 clock source select.\n 20 3 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #000 1 Reserved\nClock source from internal 22.1184 MHz high speed oscillator clock #001 2 Clock source from HCLK #010 3 Reserved #011 UART_S UART clock source select.\n 24 2 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #00 1 Clock source from PLL clock Clock source from internal 22.1184 MHz high speed oscillator clock #01 WDT_S WDT clock source select. This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 0 2 read-write 0 Reserved #00 1 Reserved #01 2 Clock source from HCLK/2048 clock #10 3 Clock source from internal 10 kHz low speed oscillator clock #11 CLKSEL2 CLKSEL2 Clock Source Select Control Register 2 0x1C -1 read-write n 0x0 0x0 FRQDIV_S Clock Divider Clock Source Select\n 2 2 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #00 1 Reserved #01 2 Clock source from HCLK #10 3 Clock source from internal 22.1184 MHz high speed oscillator clock #11 PWM45_S PWM4 and PWM5 clock source select\nPWM4 and PWM5 used the same Engine clock source, both of them use the same pre-scalar\n 4 2 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #00 1 Reserved #01 2 Clock source from HCLK #10 3 Clock source from internal 22.1184 MHz high speed oscillator clock #11 PWM67_S PWM6 and PWM7 clock source select\nPWM6 and PWM7 used the same Engine clock source, both of them use the same pre-scalar\n 6 2 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #00 1 Reserved #01 2 Clock source from HCLK #10 3 Clock source from internal 22.1184 MHz high speed oscillator clock #11 CLKSTATUS CLKSTATUS Clock Status Monitor Register 0xC read-write n 0x0 0x0 CLK_SW_FAIL Clock Switch Fail Flag\nThis bit will be set when target switch clock source is not stable. \nWrite 1 to clear this bit to zero. 7 1 read-write 0 Clock switch if success #0 1 Clock switch if fail #1 OSC10K_STB Internal 10 kHz Low Speed Clock Source Stable Flag (Read Only)\n 3 1 read-only 0 Internal 10 kHz low speed oscillator clock is not stable or disable #0 1 Internal 10 kHz low speed oscillator clock is stable #1 OSC22M_STB Internal 22.1184 MHz High Speed Clock Source Stable Flag (Read Only)\n 4 1 read-only 0 Internal 22.1184 MHz high speed oscillator clock is not stable or disable #0 1 Internal 22.1184 MHz high speed oscillator clock is stable #1 PLL_STB PLL Clock Source Stable Flag (Read Only)\n 2 1 read-only 0 PLL clock is not stable or disable #0 1 PLL clock is stable #1 XTL12M_STB External 4~24 MHz High Speed Crystal Clock Source Stable Flag (Read Only)\n 0 1 read-only 0 External 4~24 MHz high speed crystal clock is not stable or disable #0 1 External 4~24 MHz high speed crystal clock is stable #1 FRQDIV FRQDIV Frequency Divider Control Register 0x24 read-write n 0x0 0x0 DIVIDER_EN Frequency Divider Enable Bit\n 4 1 read-write 0 Disable Frequency Divider #0 1 Enable Frequency Divider #1 FSEL Divider Output Frequency Selection Bits\nThe formula of output frequency is\nFin is the input clock frequency\nFout is the frequency of divider output clock\nN is the 4-bit value of FSEL[3:0]. 0 4 read-write PLLCON PLLCON PLL Control Register 0x20 -1 read-write n 0x0 0x0 BP PLL Bypass Control\n 17 1 read-write 0 PLL is in normal mode (default) #0 1 PLL clock output is same as clock input (XTALin) #1 FB_DV PLL Feedback Divider Control Pins 0 9 read-write IN_DV PLL Input Divider Control Pins 9 5 read-write OE PLL OE (FOUT enable) pin Control\n 18 1 read-write 0 PLL FOUT enable #0 1 PLL FOUT is fixed low #1 OUT_DV PLL Output Divider Control Pins 14 2 read-write PD Power Down Mode. If set the IDLE bit 1 in PWRCON register, the PLL will enter power down mode too 16 1 read-write 0 PLL is in normal mode #0 1 PLL is in power down mode (default) #1 PLL_SRC PLL Source Clock Select\n 19 1 read-write 0 PLL source clock from external 4~24 MHz high speed crystal #0 1 PLL source clock from internal 22.1184 MHz high speed oscillator #1 PWRCON PWRCON System Power Down Control Register 0x0 -1 read-write n 0x0 0x0 OSC10K_EN Internal 10 kHz Low Speed Oscillator enable (write-protected)\n 3 1 read-write 0 Internal 10 kHz low speed oscillator disable #0 1 Internal 10 kHz low speed oscillator enable #1 OSC22M_EN Internal 22.1184 MHz High Speed Oscillator enable (write-protected)\n 2 1 read-write 0 Internal 22.1184 MHz high speed oscillator disable #0 1 Internal 22.1184 MHz high speed oscillator enable #1 PD_WAIT_CPU This Bit Control the Power Down Entry Condition (write-protection bit)\n 8 1 read-write 0 Chip entry power down mode when the PWR_DOWN_EN bit is set to 1 #0 1 Chip enter power down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction #1 PD_WU_DLY Enable the wake up delay counter. (write-protected)\nWhen the chip wakes up from power down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator.\n 4 1 read-write 0 Disable clock cycles delay #0 1 Enable clock cycles delay #1 PD_WU_INT_EN Power down mode wake Up Interrupt Enable (write-protected)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high. 5 1 read-write 0 Disable #0 1 Enable. The interrupt will occur when power down mode wake-up #1 PD_WU_STS Chip power down wake up status flag Set by power down wake up , it indicates that resume from power down mode The flag is set if the GPIO(P0~P4), and UART wakeup Write 1 to clear this bit to zero. Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1. 6 1 read-write PWR_DOWN_EN System Power Down Enable Bit (write-protection bit)\nWhen this bit is set to 1, the chip power down mode is enabled and chip power down behavior will depends on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0, then the chip enters power down mode immediately after the PWR_DOWN_EN bit set.\n(b) if the PD_WAIT_CPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters power down mode\nWhen chip wakes up from power down mode, this bit is auto cleared. Users need to set this bit again for next power down.\nWhen in power down mode, external 4~24 MHz high speed crystal and the internal 22.1184 MHz high speed oscillator will be disabled in this mode, but the internal 10 kHz low speed oscillator are not controlled by power down mode.\nWhen in power down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by power down mode, if the peripheral clock source is from internal 10 kHz low speed oscillator.\n 7 1 read-write 0 Chip operating normally or chip in idle mode because of WFI command #0 1 Chip enter the power down mode instant or wait CPU sleep command WFI #1 XTL12M_EN External 4~24 MHz High Speed Crystal enable (write-protected) The bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically. 0 1 read-write 0 External 4~24 MHz high speed crystal disable #0 1 External 4~24 MHz high speed crystal enable #1 EBI_CTL EBI Register Map EBI 0x0 0x0 0x8 registers n EBICON EBICON External Bus Interface General Control Register 0x0 read-write n 0x0 0x0 ExtBW16 EBI data width 16 bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n 1 1 read-write 0 EBI data width is 8 bit #0 1 EBI data width is 16 bit #1 ExtEN EBI Enable\nThis bit is the functional enable bit for EBI.\n 0 1 read-write 0 EBI function is disabled #0 1 EBI function is enabled #1 ExttALE Expand Time of ALE\nThe ALE width (tALE) to latch the address can be controlled by ExttALE.\n 16 3 read-write MCLKDIV External Output Clock Divider\n 8 3 read-write EXTIME EXTIME External Bus Interface Timing Control Register 0x4 read-write n 0x0 0x0 ExtIR2R Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read, idle state is inserted and nCS return to high if ExtIR2R is not zero.\n 24 4 read-write ExtIW2X Idle State Cycle After Write\nWhen write action is finish, idle state is inserted and nCS return to high if ExtIW2X is not zero.\n 12 4 read-write ExttACC EBI Data Access Time\nExttACC define data access time (tACC).\n 3 5 read-write ExttAHD EBI Data Access Hold Time\nExttAHD define data access hold time (tAHD).\n 8 3 read-write FMC FMC Register Map FMC 0x0 0x0 0x1C registers n DFBADR DFBADR Data Flash Base Address 0x14 -1 read-only n 0x0 0x0 DFBADR Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nFor 8/16/32/64KB flash memory device, the data flash size is 4KB and it start address is fixed at 0x0001_F000 by hardware internally. 0 32 read-only FATCON FATCON Flash Access Time Control Register 0x18 read-write n 0x0 0x0 FATS Flash Access Time Window Select\n 1 3 read-write FPSEN Flash Power Save Enable\nIf CPU clock is slower than 24 MHz, then s/w can enable flash power saving function \n 0 1 read-write 0 Disable flash power saving #0 1 Enable flash power saving #1 LFOM Low Frequency Optimization Mode (write-protection bit)\nWhen chip operation frequency is lower than 25 MHz, chip can work more efficiently by setting this bit to 1\n 4 1 read-write 0 Disable flash low frequency optimization mode #0 1 Enable flash low frequency optimization mode #1 ISPADR ISPADR ISP Address Register 0x4 read-write n 0x0 0x0 ISPADR ISP Address \nNuMicro M051 series equips with a maximum 16kx32 embedded flash, it supports word program only. ISPADR[1:0] must be kept 00b for ISP operation. 0 32 read-write ISPCMD ISPCMD ISP Command Register 0xC read-write n 0x0 0x0 ISPCMD ISP Command \n 0 6 read-write ISPCON ISPCON ISP Control Register 0x0 read-write n 0x0 0x0 BS Boot Select This bit is protected bit. Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as MCU booting status flag, which can be used to check where MCU booted from. This bit is initiated with the inversed value of CBS in Config0 after power-on reset It keeps the same value at other reset. 1 1 read-write 0 boot from APROM #0 1 boot from LDROM #1 CFGUEN Config Update Enable\nWriting this bit to 1 enables s/w to update Config value by ISP procedure regardless of program code is running in APROM or LDROM.\n 4 1 read-write 0 Config update disable #0 1 Config update enable #1 ISPEN ISP Enable\nThis bit is protected bit. ISP function enable bit. Set this bit to enable ISP function.\n 0 1 read-write 0 Disable ISP function #0 1 Enable ISP function #1 ISPFF ISP Fail Flag\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself.\n(2) LDROM writes to itself. \n(3) Destination address is illegal, such as over an available range.\nNote: Write 1 to clear this bit to zero. 6 1 read-write LDUEN LDROM Update Enable\nLDROM update enable bit. \n 5 1 read-write 0 LDROM cannot be updated #0 1 LDROM can be updated when the MCU runs in APROM #1 ISPDAT ISPDAT ISP Data Register 0x8 read-write n 0x0 0x0 ISPDAT ISP Data Write data to this register before ISP program operation Read data from this register after ISP read operation 0 32 read-write ISPTRG ISPTRG ISP Trigger Control Register 0x10 read-write n 0x0 0x0 ISPGO ISP start trigger\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finish.\n 0 1 read-write 0 ISP done #0 1 ISP is on going #1 GCR GCR Register Map GCR 0x0 0x0 0x10 registers n 0x100 0x4 registers n 0x18 0x4 registers n 0x24 0x4 registers n 0x30 0x14 registers n BODCR BODCR Brown Out Detector Control Register 0x18 -1 read-write n 0x0 0x0 BOD_EN Brown Out Detector Enable (initiated and write-protected bit)\nThe default value is set by flash controller user configuration register config0 bit[23]\n 0 1 read-write 0 Brown Out Detector function is disabled #0 1 Brown Out Detector function is enabled #1 BOD_INTF Brown Out Detector Interrupt Flag\n 4 1 read-write 0 Brown Out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting #0 1 When Brown Out Detector detects the VDD is dropped through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the brown out interrupt is requested if brown out interrupt is enabled #1 BOD_LPM Brown Out Detector Low power Mode (write-protected bit)\nThe BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. 5 1 read-write 0 BOD operate in normal mode (default) #0 1 Enable the BOD low power mode #1 BOD_OUT The status for Brown Out Detector output state\n 6 1 read-write 0 Brown Out Detector status output is 0, the detected voltage is higher than BOD_VL setting #0 1 Brown Out Detector status output is 1, the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0 (disabled), this bit always response 0 #1 BOD_RSTEN Brown Out Reset Enable (initiated and write-protected bit) When the BOD_EN is enabled and the interrupt is assert, the interrupt will keep till to the BOD_EN set to 0 . The interrupt for CPU can be blocked by disable the NVIC in CPU for BOD interrupt or disable the interrupt source by disable the BOD_EN and then re-enable the BOD_EN function if the BOD function is required 3 1 read-write 0 Enable the Brown Out INTERRUPT function, when the Brown Out Detector function is enable and the detected voltage is lower than the threshold then assert a signal to interrupt the MCU Cortex-M0 #0 1 Enable the Brown Out RESET function, when the Brown Out Detector function is enable and the detected voltage is lower than the threshold then assert a signal to reset the chip #1 BOD_VL Brown Out Detector Threshold Voltage Selection (initiated and write-protected bit)\n 1 2 read-write LVR_EN Low Voltage Reset Enable (write-protected bit)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default. The typical value of LVR is about 2.0V.\n 7 1 read-write 0 Disabled Low Voltage Reset function #0 1 Enabled Low Voltage Reset function - After enable the bit, the LVR function will active with 100uS delay for LVR output stable.(default) #1 IPRSTC1 IPRSTC1 Peripheral Reset Control Register 1 0x8 read-write n 0x0 0x0 CHIP_RST CHIP one shot reset. Set this bit will reset the CHIP, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIP_RST is same as the POR reset , all the chip module is reset and the chip setting from flash are also reload This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 0 1 read-write 0 Normal #0 1 Reset CHIP #1 CPU_RST CPU kernel one shot reset. Set this bit will reset the Cortex-M0 CPU kernel and Flash memory controller (FMC). This bit will automatically return to 0 after the 2 clock cycles This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 1 1 read-write 0 Normal #0 1 Reset CPU #1 EBI_RST EBI Controller Reset Set these bit 1 will generate a reset signal to the EBI. User need to set this bit to 0 to release from the reset state This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 3 1 read-write 0 Normal operation #0 1 EBI IP reset #1 IPRSTC2 IPRSTC2 Peripheral Reset Control Register 2 0xC read-write n 0x0 0x0 ADC_RST ADC Controller Reset\n 28 1 read-write 0 ADC controller normal operation #0 1 ADC controller reset #1 GPIO_RST GPIO (P0~P4) controller Reset\n 1 1 read-write 0 GPIO controller normal operation #0 1 GPIO controller reset #1 I2C_RST I2C controller Reset\n 8 1 read-write 0 I2C controller normal operation #0 1 I2C controller reset #1 PWM03_RST PWM0~3 controller Reset\n 20 1 read-write 0 PWM0~3 controller normal operation #0 1 PWM0~3 controller reset #1 PWM47_RST PWM4~7 controller Reset\n 21 1 read-write 0 PWM4~7 controller normal operation #0 1 PWM4~7 controller reset #1 SPI0_RST SPI0 controller Reset\n 12 1 read-write 0 SPI0 controller normal operation #0 1 SPI0 controller reset #1 SPI1_RST SPI1 controller Reset\n 13 1 read-write 0 SPI1 controller normal operation #0 1 SPI1 controller reset #1 TMR0_RST Timer0 controller Reset\n 2 1 read-write 0 Timer0 controller normal operation #0 1 Timer0 controller reset #1 TMR1_RST Timer1 controller Reset\n 3 1 read-write 0 Timer1 controller normal operation #0 1 Timer1 controller reset #1 TMR2_RST Timer2 controller Reset\n 4 1 read-write 0 Timer2 controller normal operation #0 1 Timer2 controller reset #1 TMR3_RST Timer3 controller Reset\n 5 1 read-write 0 Timer3 controller normal operation #0 1 Timer3 controller reset #1 UART0_RST UART0 controller Reset\n 16 1 read-write 0 UART0 controller normal operation #0 1 UART0 controller reset #1 UART1_RST UART1 controller Reset\n 17 1 read-write 0 UART1 controller normal operation #0 1 UART1 controller reset #1 P0_MFP P0_MFP P0 Multiple Function and Input Type Control Register 0x30 read-write n 0x0 0x0 P0_ALT0 P0.0 alternate function Selection\n 8 1 read-write P0_ALT1 P0.1 alternate function Selection\n 9 1 read-write P0_ALT2 P0.2 alternate function Selection\n 10 1 read-write P0_ALT3 P0.3 alternate function Selection\n 11 1 read-write P0_ALT4 P0.4 alternate function Selection\n 12 1 read-write P0_ALT5 P0.5 alternate function Selection\n 13 1 read-write P0_ALT6 P0.6 alternate function Selection\n 14 1 read-write P0_ALT7 P0.7 alternate function Selection\n 15 1 read-write P0_MFP P0 multiple function Selection\nThe pin function of P0 depends on P0_MFP and P0_ALT.\nRefer to P0_ALT for details descriptions. 0 8 read-write P0_TYPEn P0[7:0] input Schmitt Trigger function Enable\n 16 8 read-write 0 P0[7:0] I/O input Schmitt Trigger function disable 0 1 P0[7:0] I/O input Schmitt Trigger function enable 1 P1_MFP P1_MFP P1 Multiple Function and Input Type Control Register 0x34 read-write n 0x0 0x0 P1_ALT0 P1.0 alternate function Selection\n 8 1 read-write P1_ALT1 P1.1 alternate function Selection\n 9 1 read-write P1_ALT2 P1.2 alternate function Selection\n 10 1 read-write P1_ALT3 P1.3 alternate function Selection\n 11 1 read-write P1_ALT4 P1.4 alternate function Selection\n 12 1 read-write P1_ALT5 P1.5 alternate function Selection\n 13 1 read-write P1_ALT6 P1.6 alternate function Selection\n 14 1 read-write P1_ALT7 P1.7 alternate function Selection\n 15 1 read-write P1_MFP P1 multiple function Selection\nThe pin function of P1 is depending on P1_MFP and P1_ALT.\nRefer to P1_ALT for details descriptions. 0 8 read-write P1_TYPEn P1[7:0] input Schmitt Trigger function Enable\n 16 8 read-write 0 P1[7:0] I/O input Schmitt Trigger function disable 0 1 P1[7:0] I/O input Schmitt Trigger function enable 1 P2_MFP P2_MFP P2 Multiple Function and Input Type Control Register 0x38 read-write n 0x0 0x0 P2_ALT0 P2.0 alternate function Selection\n 8 1 read-write P2_ALT1 P2.1 alternate function Selection\n 9 1 read-write P2_ALT2 P2.2 alternate function Selection\n 10 1 read-write P2_ALT3 P2.3 alternate function Selection\n 11 1 read-write P2_ALT4 P2.4 alternate function Selection\n 12 1 read-write P2_ALT5 P2.5 alternate function Selection\n 13 1 read-write P2_ALT6 P2.6 alternate function Selection\n 14 1 read-write P2_ALT7 P2.7 alternate function Selection\n 15 1 read-write P2_MFP P2 multiple function Selection\nThe pin function of P2 depends on P2_MFP and P2_ALT.\nRefer to P2_ALT for details descriptions. 0 8 read-write P2_TYPEn P2[7:0] input Schmitt Trigger function Enable\n 16 8 read-write 0 P2[7:0] I/O input Schmitt Trigger function disable 0 1 P2[7:0] I/O input Schmitt Trigger function enable 1 P3_MFP P3_MFP P3 Multiple Function and Input Type Control Register 0x3C read-write n 0x0 0x0 P3_ALT0 P3.0 alternate function Selection\n 8 1 read-write P3_ALT1 P3.1 alternate function Selection\n 9 1 read-write P3_ALT2 P3.2 alternate function Selection\n 10 1 read-write P3_ALT3 P3.3 alternate function Selection\n 11 1 read-write P3_ALT4 P3.4 alternate function Selection\n 12 1 read-write P3_ALT5 P3.5 alternate function Selection\n 13 1 read-write P3_ALT6 P3.6 alternate function Selection\n 14 1 read-write P3_ALT7 P3.7 alternate function Selection\n 15 1 read-write P3_MFP P3 multiple function Selection\nThe pin function of P3 is depending on P3_MFP and P3_ALT.\nRefer to P3_ALT for details descriptions. 0 8 read-write P3_TYPEn P3[7:0] input Schmitt Trigger function Enable\n 16 8 read-write 0 P3[7:0] I/O input Schmitt Trigger function disable 0 1 P3[7:0] I/O input Schmitt Trigger function enable 1 P4_MFP P4_MFP P4 Multiple Function and Input Type Control Register 0x40 -1 read-write n 0x0 0x0 P4_ALT0 P4.0 alternate function Selection\n 8 1 read-write P4_ALT1 P4.1 alternate function Selection\n 9 1 read-write P4_ALT2 P4.2 alternate function Selection\n 10 1 read-write P4_ALT3 P4.3 alternate function Selection\n 11 1 read-write P4_ALT4 P4.4 alternate function Selection\n 12 1 read-write P4_ALT5 P4.5 alternate function Selection\n 13 1 read-write P4_ALT6 P4.6 alternate function Selection\n 14 1 read-write P4_ALT7 P4.7 alternate function Selection\n 15 1 read-write P4_MFP P4 multiple function Selection\nThe pin function of P4 is depending on P4_MFP and P4_ALT.\nRefer to P4_ALT for details descriptions. 0 8 read-write P4_TYPEn P4[7:0] input Schmitt Trigger function Enable\n 16 8 read-write 0 P4[7:0] I/O input Schmitt Trigger function disable 0 1 P4[7:0] I/O input Schmitt Trigger function enable 1 PDID PDID Part Device Identification Number Register 0x0 -1 read-only n 0x0 0x0 PDID Part Device Identification Number\nThis register reflects device part number code. S/W can read this register to identify which device is used.\nFor example, M052LBN PDID code is 0x1000_5200. 0 32 read-only PORCR PORCR Power-On-reset Controller Register 0x24 read-write n 0x0 0x0 POR_DIS_CODE The register is used for the Power-On-Reset enable control (write-protected) When power on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. If set the POR_DIS_CODE equal to 0x5AA5, the POR reset function will be disabled and the POR function will re-active till the power voltage is lower to set the POR_DIS_CODE to another value or reset by chip other reset function. Include: /RESET, Watch dog, LVR reset BOD reset, ICE reset command and the software-chip reset function This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 0 16 read-write REGWRPROT REGWRPROT Register Write-protection Control Register 0x100 read-write n 0x0 0x0 REGWRPROT Register Write-Protected Code (Write Only)\n 0 8 read-write 0 Protection is enabled for writing protected registers. Any write to the protected register is ignored 0 1 Protection is disabled for writing protected registers 1 RSTSRC RSTSRC System Reset Source Register 0x4 read-write n 0x0 0x0 RSTS_BOD The RSTS_BOD flag is set by the reset signal from the Brown-Out-Detector module to indicate the previous reset source. This bit is cleared by writing 1 to itself. 4 1 read-write 0 No reset from BOD #0 1 The Brown-Out-Detector module had issued the reset signal to reset the system #1 RSTS_CPU The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) with a 1 to rest Cortex-M0 CPU kernel and Flash memory controller(FMC). This bit is cleared by writing 1 to itself. 7 1 read-write 0 No reset from CPU #0 1 The Cortex-M0 CPU kernel and FMC are reset by software set CPU_RST to 1 #1 RSTS_LVR The RSTS_LVR flag is set by the reset signal from the Low-Voltage-Reset module to indicate the previous reset source. This bit is cleared by writing 1 to itself. 3 1 read-write 0 No reset from LVR #0 1 The LVR module had issued the reset signal to reset the system #1 RSTS_MCU The RSTS_MCU flag is set by the reset signal from the MCU Cortex_M0 kernel to indicate the previous reset source. This bit is cleared by writing 1 to itself. 5 1 read-write 0 No reset from MCU #0 1 The MCU Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel #1 RSTS_POR The RSTS_POR flag is set by the reset signal , which is from the Power-On Reset(POR) module or bit CHIP_RST (IPRSTC1[0]) is set, to indicate the previous reset source. This bit is cleared by writing 1 to itself. 0 1 read-write 0 No reset from POR #0 1 The Power-On-Reset(POR) or CHIP_RST=1 had issued the reset signal to reset the system #1 RSTS_RESET The RSTS_RESET flag is set by the reset signal from the /RESET pin to indicate the previous reset source. This bit is cleared by writing 1 to itself. 1 1 read-write 0 No reset from Pin /RESET #0 1 The Pin /RESET had issued the reset signal to reset the system #1 RSTS_WDT The RSTS_WDT flag is set by the reset signal from the Watchdog timer to indicate the previous reset source. This bit is cleared by writing 1 to itself. 2 1 read-write 0 No reset from Watchdog timer #0 1 The Watchdog timer had issued the reset signal to reset the system #1 GP GPIO Register Map GPIO 0x0 0x0 0x24 registers n 0x100 0x24 registers n 0x180 0x4 registers n 0x200 0xA0 registers n 0x40 0x24 registers n 0x80 0x24 registers n 0xC0 0x24 registers n DBNCECON DBNCECON External Interrupt De-bounce Control 0x180 -1 read-write n 0x0 0x0 DBCLKSEL De-bounce sampling cycle selection\n 0 4 read-write DBCLKSRC De-bounce counter clock source select\n 4 1 read-write 0 De-bounce counter clock source is the HCLK #0 1 De-bounce counter clock source is the internal 10kHz low speed oscillator clock #1 ICLK_ON Interrupt clock On mode Set this bit 0 will disable the interrupt generate circuit clock, if the pin[n] interrupt is disabled 5 1 read-write 0 disable the clock if the P0/1/2/3/4[n] interrupt is disabled #0 1 interrupt generated circuit clock always enable #1 P00_PDIO P00_PDIO GPIO P0.n Pin Data Input/Output 0x200 read-write n 0x0 0x0 Pxn_PDIO GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\n 0 1 read-write 0 Set corresponding GPIO pin to low #0 1 Set corresponding GPIO pin to high #1 P01_PDIO P01_PDIO GPIO P0.n Pin Data Input/Output 0x204 read-write n 0x0 0x0 P02_PDIO P02_PDIO GPIO P0.n Pin Data Input/Output 0x208 read-write n 0x0 0x0 P03_PDIO P03_PDIO GPIO P0.n Pin Data Input/Output 0x20C read-write n 0x0 0x0 P04_PDIO P04_PDIO GPIO P0.n Pin Data Input/Output 0x210 read-write n 0x0 0x0 P05_PDIO P05_PDIO GPIO P0.n Pin Data Input/Output 0x214 read-write n 0x0 0x0 P06_PDIO P06_PDIO GPIO P0.n Pin Data Input/Output 0x218 read-write n 0x0 0x0 P07_PDIO P07_PDIO GPIO P0.n Pin Data Input/Output 0x21C read-write n 0x0 0x0 P0_DBEN P0_DBEN P0 De-bounce Enable 0x14 read-write n 0x0 0x0 DBEN0 Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt 0 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN1 Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt 1 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN2 Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt 2 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN3 Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt 3 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN4 Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt 4 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN5 Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt 5 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN6 Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt 6 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN7 Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt 7 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 P0_DMASK P0_DMASK P0 Data Output Write Mask 0xC read-write n 0x0 0x0 DMASK0 Px Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored 0 1 read-write 0 The corresponding Px_DOUT[n] bit is not masked #0 1 The corresponding Px_DOUT[n] bit is masked #1 DMASK1 Px Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored 1 1 read-write 0 The corresponding Px_DOUT[n] bit is not masked #0 1 The corresponding Px_DOUT[n] bit is masked #1 DMASK2 Px Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored 2 1 read-write 0 The corresponding Px_DOUT[n] bit is not masked #0 1 The corresponding Px_DOUT[n] bit is masked #1 DMASK3 Px Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored 3 1 read-write 0 The corresponding Px_DOUT[n] bit is not masked #0 1 The corresponding Px_DOUT[n] bit is masked #1 DMASK4 Px Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored 4 1 read-write 0 The corresponding Px_DOUT[n] bit is not masked #0 1 The corresponding Px_DOUT[n] bit is masked #1 DMASK5 Px Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored 5 1 read-write 0 The corresponding Px_DOUT[n] bit is not masked #0 1 The corresponding Px_DOUT[n] bit is masked #1 DMASK6 Px Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored 6 1 read-write 0 The corresponding Px_DOUT[n] bit is not masked #0 1 The corresponding Px_DOUT[n] bit is masked #1 DMASK7 Px Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored 7 1 read-write 0 The corresponding Px_DOUT[n] bit is not masked #0 1 The corresponding Px_DOUT[n] bit is masked #1 P0_DOUT P0_DOUT P0 Data Output Value 0x8 -1 read-write n 0x0 0x0 DOUT0 Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n 0 1 read-write 0 Px Pin[n] will drive Low if the corresponding output mode enabling bit is set #0 1 Px Pin[n] will drive High if the corresponding output mode enabling bit is set #1 DOUT1 Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n 1 1 read-write 0 Px Pin[n] will drive Low if the corresponding output mode enabling bit is set #0 1 Px Pin[n] will drive High if the corresponding output mode enabling bit is set #1 DOUT2 Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n 2 1 read-write 0 Px Pin[n] will drive Low if the corresponding output mode enabling bit is set #0 1 Px Pin[n] will drive High if the corresponding output mode enabling bit is set #1 DOUT3 Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n 3 1 read-write 0 Px Pin[n] will drive Low if the corresponding output mode enabling bit is set #0 1 Px Pin[n] will drive High if the corresponding output mode enabling bit is set #1 DOUT4 Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n 4 1 read-write 0 Px Pin[n] will drive Low if the corresponding output mode enabling bit is set #0 1 Px Pin[n] will drive High if the corresponding output mode enabling bit is set #1 DOUT5 Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n 5 1 read-write 0 Px Pin[n] will drive Low if the corresponding output mode enabling bit is set #0 1 Px Pin[n] will drive High if the corresponding output mode enabling bit is set #1 DOUT6 Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n 6 1 read-write 0 Px Pin[n] will drive Low if the corresponding output mode enabling bit is set #0 1 Px Pin[n] will drive High if the corresponding output mode enabling bit is set #1 DOUT7 Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n 7 1 read-write 0 Px Pin[n] will drive Low if the corresponding output mode enabling bit is set #0 1 Px Pin[n] will drive High if the corresponding output mode enabling bit is set #1 P0_IEN P0_IEN P0 Interrupt Enable 0x1C read-write n 0x0 0x0 IF_EN0 Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt. 0 1 read-write 0 Disable the Px[n] state low-level or high-to-low change interrupt #0 1 Enable the Px[n] state low-level or high-to-low change interrupt #1 IF_EN1 Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt. 1 1 read-write 0 Disable the Px[n] state low-level or high-to-low change interrupt #0 1 Enable the Px[n] state low-level or high-to-low change interrupt #1 IF_EN2 Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt. 2 1 read-write 0 Disable the Px[n] state low-level or high-to-low change interrupt #0 1 Enable the Px[n] state low-level or high-to-low change interrupt #1 IF_EN3 Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt. 3 1 read-write 0 Disable the Px[n] state low-level or high-to-low change interrupt #0 1 Enable the Px[n] state low-level or high-to-low change interrupt #1 IF_EN4 Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt. 4 1 read-write 0 Disable the Px[n] state low-level or high-to-low change interrupt #0 1 Enable the Px[n] state low-level or high-to-low change interrupt #1 IF_EN5 Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt. 5 1 read-write 0 Disable the Px[n] state low-level or high-to-low change interrupt #0 1 Enable the Px[n] state low-level or high-to-low change interrupt #1 IF_EN6 Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt. 6 1 read-write 0 Disable the Px[n] state low-level or high-to-low change interrupt #0 1 Enable the Px[n] state low-level or high-to-low change interrupt #1 IF_EN7 Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt. 7 1 read-write 0 Disable the Px[n] state low-level or high-to-low change interrupt #0 1 Enable the Px[n] state low-level or high-to-low change interrupt #1 IR_EN0 Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt. 16 1 read-write 0 Disable the Px[n] level-high or low-to-high interrupt #0 1 Enable the Px[n] level-high or low-to-high interrupt #1 IR_EN1 Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt. 17 1 read-write 0 Disable the Px[n] level-high or low-to-high interrupt #0 1 Enable the Px[n] level-high or low-to-high interrupt #1 IR_EN2 Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt. 18 1 read-write 0 Disable the Px[n] level-high or low-to-high interrupt #0 1 Enable the Px[n] level-high or low-to-high interrupt #1 IR_EN3 Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt. 19 1 read-write 0 Disable the Px[n] level-high or low-to-high interrupt #0 1 Enable the Px[n] level-high or low-to-high interrupt #1 IR_EN4 Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt. 20 1 read-write 0 Disable the Px[n] level-high or low-to-high interrupt #0 1 Enable the Px[n] level-high or low-to-high interrupt #1 IR_EN5 Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt. 21 1 read-write 0 Disable the Px[n] level-high or low-to-high interrupt #0 1 Enable the Px[n] level-high or low-to-high interrupt #1 IR_EN6 Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt. 22 1 read-write 0 Disable the Px[n] level-high or low-to-high interrupt #0 1 Enable the Px[n] level-high or low-to-high interrupt #1 IR_EN7 Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt. 23 1 read-write 0 Disable the Px[n] level-high or low-to-high interrupt #0 1 Enable the Px[n] level-high or low-to-high interrupt #1 P0_IMD P0_IMD P0 Interrupt Mode Control 0x18 read-write n 0x0 0x0 IMD0 Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n 0 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD1 Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n 1 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD2 Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n 2 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD3 Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n 3 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD4 Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n 4 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD5 Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n 5 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD6 Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n 6 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD7 Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n 7 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 P0_ISRC P0_ISRC P0 Interrupt Source Flag 0x20 read-write n 0x0 0x0 ISRC0 Port 0-4 Interrupt Trigger Source Indicator Read : 0 1 read-write 0 No interrupt at Px[n]\nNo action #0 1 Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC1 Port 0-4 Interrupt Trigger Source Indicator Read : 1 1 read-write 0 No interrupt at Px[n]\nNo action #0 1 Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC2 Port 0-4 Interrupt Trigger Source Indicator Read : 2 1 read-write 0 No interrupt at Px[n]\nNo action #0 1 Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC3 Port 0-4 Interrupt Trigger Source Indicator Read : 3 1 read-write 0 No interrupt at Px[n]\nNo action #0 1 Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC4 Port 0-4 Interrupt Trigger Source Indicator Read : 4 1 read-write 0 No interrupt at Px[n]\nNo action #0 1 Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC5 Port 0-4 Interrupt Trigger Source Indicator Read : 5 1 read-write 0 No interrupt at Px[n]\nNo action #0 1 Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC6 Port 0-4 Interrupt Trigger Source Indicator Read : 6 1 read-write 0 No interrupt at Px[n]\nNo action #0 1 Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC7 Port 0-4 Interrupt Trigger Source Indicator Read : 7 1 read-write 0 No interrupt at Px[n]\nNo action #0 1 Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt #1 P0_OFFD P0_OFFD P0 Bit OFF Digital Enable 0x4 read-write n 0x0 0x0 OFFD OFFD: Px Pin[n] OFF digital input path Enable\n 16 8 read-write 0 Enable IO digital input path 0 1 Disable IO digital input path (digital input tied to low) 1 P0_PIN P0_PIN P0 Pin Value 0x10 read-only n 0x0 0x0 PIN0 Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n 0 1 read-only PIN1 Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n 1 1 read-only PIN2 Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n 2 1 read-only PIN3 Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n 3 1 read-only PIN4 Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n 4 1 read-only PIN5 Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n 5 1 read-only PIN6 Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n 6 1 read-only PIN7 Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n 7 1 read-only P0_PMD P0_PMD P0 Pin I/O Mode Control 0x0 -1 read-write n 0x0 0x0 PMD0 Px I/O Pin[n] Mode Control Determine each I/O type of Px pins 0 2 read-write 0 Px [n] pin is in INPUT mode #00 1 Px [n] pin is in OUTPUT mode #01 2 Px [n] pin is in Open-Drain mode #10 3 Px [n] pin is in Quasi-bidirectional mode #11 PMD1 Px I/O Pin[n] Mode Control Determine each I/O type of Px pins 2 2 read-write 0 Px [n] pin is in INPUT mode #00 1 Px [n] pin is in OUTPUT mode #01 2 Px [n] pin is in Open-Drain mode #10 3 Px [n] pin is in Quasi-bidirectional mode #11 PMD2 Px I/O Pin[n] Mode Control Determine each I/O type of Px pins 4 2 read-write 0 Px [n] pin is in INPUT mode #00 1 Px [n] pin is in OUTPUT mode #01 2 Px [n] pin is in Open-Drain mode #10 3 Px [n] pin is in Quasi-bidirectional mode #11 PMD3 Px I/O Pin[n] Mode Control Determine each I/O type of Px pins 6 2 read-write 0 Px [n] pin is in INPUT mode #00 1 Px [n] pin is in OUTPUT mode #01 2 Px [n] pin is in Open-Drain mode #10 3 Px [n] pin is in Quasi-bidirectional mode #11 PMD4 Px I/O Pin[n] Mode Control Determine each I/O type of Px pins 8 2 read-write 0 Px [n] pin is in INPUT mode #00 1 Px [n] pin is in OUTPUT mode #01 2 Px [n] pin is in Open-Drain mode #10 3 Px [n] pin is in Quasi-bidirectional mode #11 PMD5 Px I/O Pin[n] Mode Control Determine each I/O type of Px pins 10 2 read-write 0 Px [n] pin is in INPUT mode #00 1 Px [n] pin is in OUTPUT mode #01 2 Px [n] pin is in Open-Drain mode #10 3 Px [n] pin is in Quasi-bidirectional mode #11 PMD6 Px I/O Pin[n] Mode Control Determine each I/O type of Px pins 12 2 read-write 0 Px [n] pin is in INPUT mode #00 1 Px [n] pin is in OUTPUT mode #01 2 Px [n] pin is in Open-Drain mode #10 3 Px [n] pin is in Quasi-bidirectional mode #11 PMD7 Px I/O Pin[n] Mode Control Determine each I/O type of Px pins 14 2 read-write 0 Px [n] pin is in INPUT mode #00 1 Px [n] pin is in OUTPUT mode #01 2 Px [n] pin is in Open-Drain mode #10 3 Px [n] pin is in Quasi-bidirectional mode #11 P10_PDIO P10_PDIO GPIO P1.n Pin Data Input/Output 0x220 read-write n 0x0 0x0 P11_PDIO P11_PDIO GPIO P1.n Pin Data Input/Output 0x224 read-write n 0x0 0x0 P12_PDIO P12_PDIO GPIO P1.n Pin Data Input/Output 0x228 read-write n 0x0 0x0 P13_PDIO P13_PDIO GPIO P1.n Pin Data Input/Output 0x22C read-write n 0x0 0x0 P14_PDIO P14_PDIO GPIO P1.n Pin Data Input/Output 0x230 read-write n 0x0 0x0 P15_PDIO P15_PDIO GPIO P1.n Pin Data Input/Output 0x234 read-write n 0x0 0x0 P16_PDIO P16_PDIO GPIO P1.n Pin Data Input/Output 0x238 read-write n 0x0 0x0 P17_PDIO P17_PDIO GPIO P1.n Pin Data Input/Output 0x23C read-write n 0x0 0x0 P1_DBEN P1_DBEN P1 De-bounce Enable 0x54 read-write n 0x0 0x0 P1_DMASK P1_DMASK P1 Data Output Write Mask 0x4C read-write n 0x0 0x0 P1_DOUT P1_DOUT P1 Data Output Value 0x48 read-write n 0x0 0x0 P1_IEN P1_IEN P1 Interrupt Enable 0x5C read-write n 0x0 0x0 P1_IMD P1_IMD P1 Interrupt Mode Control 0x58 read-write n 0x0 0x0 P1_ISRC P1_ISRC P1 Interrupt Source Flag 0x60 read-write n 0x0 0x0 P1_OFFD P1_OFFD P1 Bit OFF Digital Enable 0x44 read-write n 0x0 0x0 P1_PIN P1_PIN P1 Pin Value 0x50 read-write n 0x0 0x0 P1_PMD P1_PMD P1 Pin I/O Mode Control 0x40 read-write n 0x0 0x0 P20_PDIO P20_PDIO GPIO P2.n Pin Data Input/Output 0x240 read-write n 0x0 0x0 P21_PDIO P21_PDIO GPIO P2.n Pin Data Input/Output 0x244 read-write n 0x0 0x0 P22_PDIO P22_PDIO GPIO P2.n Pin Data Input/Output 0x248 read-write n 0x0 0x0 P23_PDIO P23_PDIO GPIO P2.n Pin Data Input/Output 0x24C read-write n 0x0 0x0 P24_PDIO P24_PDIO GPIO P2.n Pin Data Input/Output 0x250 read-write n 0x0 0x0 P25_PDIO P25_PDIO GPIO P2.n Pin Data Input/Output 0x254 read-write n 0x0 0x0 P26_PDIO P26_PDIO GPIO P2.n Pin Data Input/Output 0x258 read-write n 0x0 0x0 P27_PDIO P27_PDIO GPIO P2.n Pin Data Input/Output 0x25C read-write n 0x0 0x0 P2_DBEN P2_DBEN P2 De-bounce Enable 0x94 read-write n 0x0 0x0 P2_DMASK P2_DMASK P2 Data Output Write Mask 0x8C read-write n 0x0 0x0 P2_DOUT P2_DOUT P2 Data Output Value 0x88 read-write n 0x0 0x0 P2_IEN P2_IEN P2 Interrupt Enable 0x9C read-write n 0x0 0x0 P2_IMD P2_IMD P2 Interrupt Mode Control 0x98 read-write n 0x0 0x0 P2_ISRC P2_ISRC P2 Interrupt Source Flag 0xA0 read-write n 0x0 0x0 P2_OFFD P2_OFFD P2 Bit OFF Digital Enable 0x84 read-write n 0x0 0x0 P2_PIN P2_PIN P2 Pin Value 0x90 read-write n 0x0 0x0 P2_PMD P2_PMD P2 Pin I/O Mode Control 0x80 read-write n 0x0 0x0 P30_PDIO P30_PDIO GPIO P3.n Pin Data Input/Output 0x260 read-write n 0x0 0x0 P31_PDIO P31_PDIO GPIO P3.n Pin Data Input/Output 0x264 read-write n 0x0 0x0 P32_PDIO P32_PDIO GPIO P3.n Pin Data Input/Output 0x268 read-write n 0x0 0x0 P33_PDIO P33_PDIO GPIO P3.n Pin Data Input/Output 0x26C read-write n 0x0 0x0 P34_PDIO P34_PDIO GPIO P3.n Pin Data Input/Output 0x270 read-write n 0x0 0x0 P35_PDIO P35_PDIO GPIO P3.n Pin Data Input/Output 0x274 read-write n 0x0 0x0 P36_PDIO P36_PDIO GPIO P3.n Pin Data Input/Output 0x278 read-write n 0x0 0x0 P37_PDIO P37_PDIO GPIO P3.n Pin Data Input/Output 0x27C read-write n 0x0 0x0 P3_DBEN P3_DBEN P3 De-bounce Enable 0xD4 read-write n 0x0 0x0 P3_DMASK P3_DMASK P3 Data Output Write Mask 0xCC read-write n 0x0 0x0 P3_DOUT P3_DOUT P3 Data Output Value 0xC8 read-write n 0x0 0x0 P3_IEN P3_IEN P3 Interrupt Enable 0xDC read-write n 0x0 0x0 P3_IMD P3_IMD P3 Interrupt Mode Control 0xD8 read-write n 0x0 0x0 P3_ISRC P3_ISRC P3 Interrupt Source Flag 0xE0 read-write n 0x0 0x0 P3_OFFD P3_OFFD P3 Bit OFF Digital Enable 0xC4 read-write n 0x0 0x0 P3_PIN P3_PIN P3 Pin Value 0xD0 read-write n 0x0 0x0 P3_PMD P3_PMD P3 Pin I/O Mode Control 0xC0 read-write n 0x0 0x0 P40_PDIO P40_PDIO GPIO P4.n Pin Data Input/Output 0x280 read-write n 0x0 0x0 P41_PDIO P41_PDIO GPIO P4.n Pin Data Input/Output 0x284 read-write n 0x0 0x0 P42_PDIO P42_PDIO GPIO P4.n Pin Data Input/Output 0x288 read-write n 0x0 0x0 P43_PDIO P43_PDIO GPIO P4.n Pin Data Input/Output 0x28C read-write n 0x0 0x0 P44_PDIO P44_PDIO GPIO P4.n Pin Data Input/Output 0x290 read-write n 0x0 0x0 P45_PDIO P45_PDIO GPIO P4.n Pin Data Input/Output 0x294 read-write n 0x0 0x0 P46_PDIO P46_PDIO GPIO P4.n Pin Data Input/Output 0x298 read-write n 0x0 0x0 P47_PDIO P47_PDIO GPIO P4.n Pin Data Input/Output 0x29C read-write n 0x0 0x0 P4_DBEN P4_DBEN P4 De-bounce Enable 0x114 read-write n 0x0 0x0 P4_DMASK P4_DMASK P4 Data Output Write Mask 0x10C read-write n 0x0 0x0 P4_DOUT P4_DOUT P4 Data Output Value 0x108 read-write n 0x0 0x0 P4_IEN P4_IEN P4 Interrupt Enable 0x11C read-write n 0x0 0x0 P4_IMD P4_IMD P4 Interrupt Mode Control 0x118 read-write n 0x0 0x0 P4_ISRC P4_ISRC P4 Interrupt Source Flag 0x120 read-write n 0x0 0x0 P4_OFFD P4_OFFD P4 Bit OFF Digital Enable 0x104 read-write n 0x0 0x0 P4_PIN P4_PIN P4 Pin Value 0x110 read-write n 0x0 0x0 P4_PMD P4_PMD P4 Pin I/O Mode Control 0x100 read-write n 0x0 0x0 I2C I2C Register Map I2C 0x0 0x0 0x30 registers n I2CADDR0 I2CADDR0 I2C Slave Address Register0 0x4 read-write n 0x0 0x0 GC General Call Function\n 0 1 read-write 0 Disable General Call Function #0 1 Enable General Call Function #1 I2CADDR I2C Address Register\nThe content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched. 1 7 read-write I2CADDR1 I2CADDR1 I2C Slave Address Register1 0x18 read-write n 0x0 0x0 I2CADDR2 I2CADDR2 I2C Slave Address Register2 0x1C read-write n 0x0 0x0 I2CADDR3 I2CADDR3 I2C Slave Address Register3 0x20 read-write n 0x0 0x0 I2CADM0 I2CADM0 I2C Slave Address Mask Register0 0x24 read-write n 0x0 0x0 I2CADMx I2C Address Mask register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 1 7 read-write 0 Mask disable (the received corresponding register bit should be exact the same as address register.) 0 1 Mask enable (the received corresponding address bit is don't care.) 1 I2CADM1 I2CADM1 I2C Slave Address Mask Register1 0x28 read-write n 0x0 0x0 I2CADM2 I2CADM2 I2C Slave Address Mask Register2 0x2C read-write n 0x0 0x0 I2CADM3 I2CADM3 I2C Slave Address Mask Register3 0x30 read-write n 0x0 0x0 I2CDAT I2CDAT I2C DATA Register 0x8 read-write n 0x0 0x0 I2CDAT I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port. 0 8 read-write I2CLK I2CLK I2C Clock Divided Register 0x10 read-write n 0x0 0x0 I2CLK I2C clock divided Register\n 0 8 read-write I2CON I2CON I2C Control Register 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control Bit\n 2 1 read-write EI Enable Interrupt\n 7 1 read-write 0 Disable I2C interrupt #0 1 Enable I2C interrupt #1 ENS1 I2C Controller Enable Bit\n 6 1 read-write 0 Disable #0 1 Enable #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one to this bit. 3 1 read-write STA I2C START Control Bit\nSetting STA to logic 1 to enter master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control Bit In master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. 4 1 read-write I2CSTATUS I2CSTATUS I2C Status Register 0xC -1 read-only n 0x0 0x0 I2CSTATUS I2C Status Register\nThe status register of I2C:\n 0 8 read-only I2CTOC I2CTOC I2C Timeout Control Register 0x14 read-write n 0x0 0x0 DIV4 Time-Out counter input clock is divided by 4 \nWhen Enable, The time-Out period is extend 4 times. 1 1 read-write 0 Disable #0 1 Enable #1 ENTI Time-out counter is enabled/disable\nWhen Enable, the 14 bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared. 2 1 read-write 0 Disable #0 1 Enable #1 TIF Time-Out Flag\n 0 1 read-write 0 S/W can clear the flag #0 1 Time-Out flag is set by H/W. It can interrupt CPU #1 INT INT Register Map INT 0x0 0x0 0x88 registers n IRQ0_SRC IRQ0_SRC IRQ0 (BOD) Interrupt Source Identity 0x0 read-only n 0x0 0x0 INT_SRC Bit0 : BOD_INT 0 3 read-only IRQ10_SRC IRQ10_SRC IRQ10 (TMR2) Interrupt Source Identity 0x28 read-only n 0x0 0x0 INT_SRC Bit0: TMR2_INT 0 3 read-only IRQ11_SRC IRQ11_SRC IRQ11 (TMR3) Interrupt Source Identity 0x2C read-only n 0x0 0x0 INT_SRC Bit0: TMR3_INT 0 3 read-only IRQ12_SRC IRQ12_SRC IRQ12 (UART0) Interrupt Source Identity 0x30 read-only n 0x0 0x0 INT_SRC Bit0: UART0_INT 0 3 read-only IRQ13_SRC IRQ13_SRC IRQ13 (UART1) Interrupt Source Identity 0x34 read-only n 0x0 0x0 INT_SRC Bit0: UART1_INT 0 3 read-only IRQ14_SRC IRQ14_SRC IRQ14 (SPI0) Interrupt Source Identity 0x38 read-only n 0x0 0x0 INT_SRC Bit0: SPI0_INT 0 3 read-only IRQ15_SRC IRQ15_SRC IRQ15 (SPI1) Interrupt Source Identity 0x3C read-only n 0x0 0x0 INT_SRC Bit0: SPI1_INT 0 3 read-only IRQ16_SRC IRQ16_SRC Reserved 0x40 read-write n 0x0 0x0 IRQ17_SRC IRQ17_SRC Reserved 0x44 read-write n 0x0 0x0 IRQ18_SRC IRQ18_SRC IRQ18 (I2C) Interrupt Source Identity 0x48 read-only n 0x0 0x0 INT_SRC Bit0: I2C_INT 0 3 read-only IRQ19_SRC IRQ19_SRC Reserved 0x4C read-write n 0x0 0x0 IRQ1_SRC IRQ1_SRC IRQ1 (WDT) Interrupt Source Identity 0x4 read-only n 0x0 0x0 INT_SRC Bit0 : WDT_INT 0 3 read-only IRQ20_SRC IRQ20_SRC Reserved 0x50 read-write n 0x0 0x0 IRQ21_SRC IRQ21_SRC Reserved 0x54 read-write n 0x0 0x0 IRQ22_SRC IRQ22_SRC Reserved 0x58 read-write n 0x0 0x0 IRQ23_SRC IRQ23_SRC Reserved 0x5C read-write n 0x0 0x0 IRQ24_SRC IRQ24_SRC Reserved 0x60 read-write n 0x0 0x0 IRQ25_SRC IRQ25_SRC Reserved 0x64 read-write n 0x0 0x0 IRQ26_SRC IRQ26_SRC Reserved 0x68 read-write n 0x0 0x0 IRQ27_SRC IRQ27_SRC Reserved 0x6C read-write n 0x0 0x0 IRQ28_SRC IRQ28_SRC IRQ28 (PWRWU) Interrupt Source Identity 0x70 read-only n 0x0 0x0 INT_SRC Bit0: PWRWU_INT 0 3 read-only IRQ29_SRC IRQ29_SRC IRQ29 (ADC) Interrupt Source Identity 0x74 read-only n 0x0 0x0 INT_SRC Bit0: ADC_INT 0 3 read-only IRQ2_SRC IRQ2_SRC IRQ2 (EINT0) Interrupt Source Identity 0x8 read-only n 0x0 0x0 INT_SRC Bit0: EINT0 - external interrupt 0 from P3.2 0 3 read-only IRQ30_SRC IRQ30_SRC Reserved 0x78 read-write n 0x0 0x0 IRQ31_SRC IRQ31_SRC Reserved 0x7C read-write n 0x0 0x0 IRQ3_SRC IRQ3_SRC IRQ3 (EINT1) Interrupt Source Identity 0xC read-only n 0x0 0x0 INT_SRC Bit0: EINT1 - external interrupt 1 from P3.3 0 3 read-only IRQ4_SRC IRQ4_SRC IRQ4 (P0/1) Interrupt Source Identity 0x10 read-only n 0x0 0x0 INT_SRC Bit1: P1_INT\nBit0: P0_INT 0 3 read-only IRQ5_SRC IRQ5_SRC IRQ5 (P2/3/4) Interrupt Source Identity 0x14 read-only n 0x0 0x0 INT_SRC Bit2: P4_INT\nBit1: P3_INT\nBit0: P2_INT 0 3 read-only IRQ6_SRC IRQ6_SRC IRQ6 (PWMA) Interrupt Source Identity 0x18 read-only n 0x0 0x0 INT_SRC Bit3: PWM3_INT\nBit2: PWM2_INT\nBit1: PWM1_INT\nBit0: PWM0_INT 0 4 read-only IRQ7_SRC IRQ7_SRC IRQ7 (PWMB) Interrupt Source Identity 0x1C read-only n 0x0 0x0 INT_SRC Bit3: PWM7_INT\nBit2: PWM6_INT\nBit1: PWM5_INT\nBit0: PWM4_INT 0 4 read-only IRQ8_SRC IRQ8_SRC IRQ8 (TMR0) Interrupt Source Identity 0x20 read-only n 0x0 0x0 INT_SRC Bit0: TMR0_INT 0 3 read-only IRQ9_SRC IRQ9_SRC IRQ9 (TMR1) Interrupt Source Identity 0x24 read-only n 0x0 0x0 INT_SRC Bit0: TMR1_INT 0 3 read-only MCU_IRQ MCU_IRQ MCU Interrupt Request Source Register 0x84 -1 read-write n 0x0 0x0 MCU_IRQ MCU IRQ Source Register The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. There are two modes to generate interrupt to Cortex-M0, the normal mode and test mode. The MCU_IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0. When the MCU_IRQ[n] is 0 : Set MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 NVIC[n]. When the MCU_IRQ[n] is 1 (mean an interrupt is assert), set 1 to the MCU_bit[n] will clear the interrupt and set MCU_IRQ[n] 0 : no any effect 0 32 read-write NMI_SEL NMI_SEL NMI Source Interrupt Select Control Register 0x80 read-write n 0x0 0x0 NMI_SEL The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0]\nThe NMI_SEL bit[4:0] used to select the NMI interrupt source 0 5 read-write PWMA PWM Register Map PWM 0x0 0x0 0x3C registers n 0x40 0x8 registers n 0x50 0x30 registers n CAPENR CAPENR PWM Capture Input 0~3 Enable Register 0x78 read-write n 0x0 0x0 CAPENR Capture Input Enable Register There are four capture inputs from pad. Bit0~Bit3 are used to control each inputs ON or OFF. CAPENR Bit 3210 for PWM group A Bit xxx1 ( Capture channel 0 is from P2.0 Bit xx1x ( Capture channel 1 is from P2.1 Bit x1xx ( Capture channel 2 is from P2.2 Bit 1xxx ( Capture channel 3 is from P2.3 Bit 3210 for PWM group B Bit xxx1 ( Capture channel 0 is from P2.4 Bit xx1x ( Capture channel 1 is from P2.5 Bit x1xx ( Capture channel 2 is from P2.6 Bit 1xxx ( Capture channel 3 is from P2.7 0 4 read-write 0 OFF (PWMx multi-function pin input does not affect input capture function.) 0 1 ON (PWMx multi-function pin input will affect its input capture function.) 1 CCR0 CCR0 PWM Capture Control Register 0 0x50 read-write n 0x0 0x0 CAPCH0EN Capture Channel 0 transition Enable/Disable\nWhen Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt. 3 1 read-write 0 Disable capture function on PWM group channel 0 #0 1 Enable capture function on PWM group channel 0 #1 CAPCH1EN Capture PWM Group Channel 1 transition Enable/Disable\nWhen Enable, Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt. 19 1 read-write 0 Disable capture function on PWM group channel 1 #0 1 Enable capture function on PWM group channel 1 #1 CAPIF0 Capture0 Interrupt Indication Flag\n 4 1 read-write CAPIF1 Capture1 Interrupt Indication Flag\n 20 1 read-write CFLRI0 CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nClear this bit by writing a one to it. 7 1 read-write CFLRI1 CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nClear this bit by writing a one to it. 23 1 read-write CFL_IE0 PWM Group Channel 0 Falling Latch Interrupt Enable ON/OFF\nWhen Enable, if Capture detects PWM group channel 0 has falling transition, Capture issues an Interrupt. 2 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CFL_IE1 PWM Group Channel 1 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has falling transition, Capture issues an Interrupt. 18 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CRLRI0 CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware. \nClear this bit by writing a one to it. 6 1 read-write CRLRI1 CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nClear this bit by writing a one to it. 22 1 read-write CRL_IE0 PWM Group Channel 0 Rising Latch Interrupt Enable ON/OFF\nWhen Enable, if Capture detects PWM group channel 0 has rising transition, Capture issues an Interrupt. 1 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 CRL_IE1 PWM Group Channel 1 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has rising transition, Capture issues an Interrupt. 17 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 INV0 PWM Group Channel 0 Inverter ON/OFF\n 0 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 INV1 PWM Group Channel 1 Inverter ON/OFF\n 16 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 CCR2 CCR2 PWM Capture Control Register 2 0x54 read-write n 0x0 0x0 CAPCH2EN Capture Channel 2 transition Enable/Disable\nWhen Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt. 3 1 read-write 0 Disable capture function on PWM group channel 2 #0 1 Enable capture function on PWM group channel 2 #1 CAPCH3EN Capture Channel 3 transition Enable/Disable\nWhen Enable, Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt. 19 1 read-write 0 Disable capture function on PWM group channel 3 #0 1 Enable capture function on PWM group channel 3 #1 CAPIF2 Capture2 Interrupt Indication Flag\nNote: Write 1 to clear this bit to zero. 4 1 read-write CAPIF3 Capture3 Interrupt Indication Flag\nWrite 1 to clear this bit to zero. 20 1 read-write CFLRI2 CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to zero. 7 1 read-write CFLRI3 CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero. 23 1 read-write CFL_IE2 PWM Group Channel 2 Falling Latch Interrupt Enable ON/OFF\nWhen Enable, if Capture detects PWM group channel 2 has falling transition, Capture issues an Interrupt. 2 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CFL_IE3 PWM Group Channel 3 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 3 has falling transition, Capture issues an Interrupt. 18 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CRLRI2 CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to zero. 6 1 read-write CRLRI3 CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero. 22 1 read-write CRL_IE2 PWM Group Channel 2 Rising Latch Interrupt Enable ON/OFF\nWhen Enable, if Capture detects PWM group channel 2 has rising transition, Capture issues an Interrupt. 1 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 CRL_IE3 PWM Group Channel 3 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 3 has rising transition, Capture issues an Interrupt. 17 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 INV2 PWM Group Channel 2 Inverter ON/OFF\n 0 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 INV3 PWM Group Channel 3 Inverter ON/OFF\n 16 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 CFLR0 CFLR0 PWM Capture Falling Latch Register (Channel 0) 0x5C read-only n 0x0 0x0 CFLRx Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition. 0 16 read-only CFLR1 CFLR1 PWM Capture Falling Latch Register (Channel 1) 0x64 read-write n 0x0 0x0 CFLR2 CFLR2 PWM Capture Falling Latch Register (Channel 2) 0x6C read-write n 0x0 0x0 CFLR3 CFLR3 PWM Capture Falling Latch Register (Channel 3) 0x74 read-write n 0x0 0x0 CMR0 CMR0 PWM Comparator Register 0 0x10 read-write n 0x0 0x0 CMRx PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CMR will take effect in next PWM cycle. 0 16 read-write CMR1 CMR1 PWM Comparator Register 1 0x1C read-write n 0x0 0x0 CMR2 CMR2 PWM Comparator Register 2 0x28 read-write n 0x0 0x0 CMR3 CMR3 PWM Comparator Register 3 0x34 read-write n 0x0 0x0 CNR0 CNR0 PWM Counter Register 0 0xC read-write n 0x0 0x0 CNRx PWM Counter/Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle. 0 16 read-write CNR1 CNR1 PWM Counter Register 1 0x18 read-write n 0x0 0x0 CNR2 CNR2 PWM Counter Register 2 0x24 read-write n 0x0 0x0 CNR3 CNR3 PWM Counter Register 3 0x30 read-write n 0x0 0x0 CRLR0 CRLR0 PWM Capture Rising Latch Register (Channel 0) 0x58 read-only n 0x0 0x0 CRLRx Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition. 0 16 read-only CRLR1 CRLR1 PWM Capture Rising Latch Register (Channel 1) 0x60 read-write n 0x0 0x0 CRLR2 CRLR2 PWM Capture Rising Latch Register (Channel 2) 0x68 read-write n 0x0 0x0 CRLR3 CRLR3 PWM Capture Rising Latch Register (Channel 3) 0x70 read-write n 0x0 0x0 CSR CSR PWM Clock Select Register 0x4 read-write n 0x0 0x0 CSR0 Timer 0 Clock Source Selection (PWM timer 0 for group A and PWM timer 4 for group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3) 0 3 read-write CSR1 Timer 1 Clock Source Selection (PWM timer 1 for group A and PWM timer 5 for group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3) 4 3 read-write CSR2 Timer 2 Clock Source Selection (PWM timer 2 for group A and PWM timer 6 for group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3) 8 3 read-write CSR3 Timer 3 Clock Source Selection (PWM timer 3 for group A and PWM timer 7 for group B)\n 12 3 read-write PCR PCR PWM Control Register 0x8 read-write n 0x0 0x0 CH0EN PWM-Timer 0 Enable/Disable Start Run (PWM timer 0 for group A and PWM timer 4 for group B)\n 0 1 read-write 0 Stop corresponding PWM-Timer Running #0 1 Enable corresponding PWM-Timer Start Run #1 CH0INV PWM-Timer 0 Output Inverter ON/OFF (PWM timer 0 for group A and PWM timer 4 for group B)\n 2 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH0MOD PWM-Timer 0 Auto-reload/One-Shot Mode (PWM timer 0 for group A and PWM timer 4 for group B)\nNote: If there is a rising transition at this bit, it will cause CNR0 and CMR0 be clear. 3 1 read-write 0 One-Shot Mode #0 1 Auto-reload Mode #1 CH1EN PWM-Timer 1 Enable/Disable Start Run (PWM timer 1 for group A and PWM timer 5 for group B)\n 8 1 read-write 0 Stop corresponding PWM-Timer Running #0 1 Enable corresponding PWM-Timer Start Run #1 CH1INV PWM-Timer 1 Output Inverter ON/OFF (PWM timer 1 for group A and PWM timer 5 for group B)\n 10 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH1MOD PWM-Timer 1 Auto-reload/One-Shot Mode (PWM timer 1 for group A and PWM timer 5 for group B)\nNote: If there is a rising transition at this bit, it will cause CNR1 and CMR1 be clear. 11 1 read-write 0 One-Shot Mode #0 1 Auto-load Mode #1 CH2EN PWM-Timer 2 Enable/Disable Start Run (PWM timer 2 for group A and PWM timer 6 for group B)\n 16 1 read-write 0 Stop corresponding PWM-Timer Running #0 1 Enable corresponding PWM-Timer Start Run #1 CH2INV PWM-Timer 2 Output Inverter ON/OFF (PWM timer 2 for group A and PWM timer 6 for group B)\n 18 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH2MOD PWM-Timer 2 Auto-reload/One-Shot Mode (PWM timer 2 for group A and PWM timer 6 for group B)\nNote: If there is a rising transition at this bit, it will cause CNR2 and CMR2 be clear. 19 1 read-write 0 One-Shot Mode #0 1 Auto-reload Mode #1 CH3EN PWM-Timer 3 Enable/Disable Start Run (PWM timer 3 for group A and PWM timer 7 for group B)\n 24 1 read-write 0 Stop corresponding PWM-Timer Running #0 1 Enable corresponding PWM-Timer Start Run #1 CH3INV PWM-Timer 3 Output Inverter ON/OFF (PWM timer 3 for group A and PWM timer 7 for group B)\n 26 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH3MOD PWM-Timer 3 Auto-reload/One-Shot Mode (PWM timer 3 for group A and PWM timer 7 for group B)\nNote: If there is a rising transition at this bit, it will cause CNR3 and CMR3 be clear. 27 1 read-write 0 One-Shot Mode #0 1 Auto-reload Mode #1 DZEN01 Dead-Zone 0 Generator Enable/Disable (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nNote: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B. 4 1 read-write 0 Disable #0 1 Enable #1 DZEN23 Dead-Zone 2 Generator Enable/Disable (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nNote: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B. 5 1 read-write 0 Disable #0 1 Enable #1 PDR0 PDR0 PWM Data Register 0 0x14 read-only n 0x0 0x0 PDRx PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter. 0 16 read-only PDR1 PDR1 PWM Data Register 1 0x20 read-write n 0x0 0x0 PDR2 PDR2 PWM Data Register 2 0x2C read-write n 0x0 0x0 PDR3 PDR3 PWM Data Register 3 0x38 read-write n 0x0 0x0 PIER PIER PWM Interrupt Enable Register 0x40 read-write n 0x0 0x0 PWMIE0 PWM channel 0 Interrupt Enable\n 0 1 read-write 0 Disable #0 1 Enable #1 PWMIE1 PWM channel 1 Interrupt Enable\n 1 1 read-write 0 Disable #0 1 Enable #1 PWMIE2 PWM channel 2 Interrupt Enable\n 2 1 read-write 0 Disable #0 1 Enable #1 PWMIE3 PWM channel 3 Interrupt Enable\n 3 1 read-write 0 Disable #0 1 Enable #1 PIIR PIIR PWM Interrupt Indication Register 0x44 read-write n 0x0 0x0 PWMIF0 PWM channel 0 Interrupt Status\nFlag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing a one to it. 0 1 read-write PWMIF1 PWM channel 1 Interrupt Status\nFlag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing a one to it. 1 1 read-write PWMIF2 PWM channel 2 Interrupt Status\nFlag is set by hardware when PWM2 down counter reaches zero, software can clear this bit by writing a one to it. 2 1 read-write PWMIF3 PWM channel 3 Interrupt Status\nFlag is set by hardware when PWM3 down counter reaches zero, software can clear this bit by writing a one to it. 3 1 read-write POE POE PWM Output Enable Register for Channel 0~3 0x7C read-write n 0x0 0x0 PWM0 PWM Channel 0 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function 0 1 read-write 0 Disable PWM channel 0 output to pin #0 1 Enable PWM channel 0 output to pin #1 PWM1 PWM Channel 1 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function 1 1 read-write 0 Disable PWM channel 1 output to pin #0 1 Enable PWM channel 1 output to pin #1 PWM2 PWM Channel 2 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function 2 1 read-write 0 Disable PWM channel 2 output to pin #0 1 Enable PWM channel 2 output to pin #1 PWM3 PWM Channel 3 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function 3 1 read-write 0 Disable PWM channel 3 output to pin #0 1 Enable PWM channel 3 output to pin #1 PPR PPR PWM Pre-scale Register 0x0 read-write n 0x0 0x0 CP01 Clock prescaler 0 (PWM counter 0/1 for group A and PWM counter 4/ 5 for group B) Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter 0 8 read-write CP23 Clock prescaler 2 (PWM counter 2/ 3 for group A and PWM counter 6/ 7 for group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter\n 8 8 read-write DZI01 Dead zone interval register for pair of channel 0 and channel 1 (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from corresponding CSR bits. 16 8 read-write DZI23 Dead zone interval register for pair of channel2 and channel3 (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from corresponding CSR bits. 24 8 read-write PWMB PWM Register Map PWM 0x0 0x0 0x3C registers n 0x40 0x8 registers n 0x50 0x30 registers n CAPENR CAPENR PWM Capture Input 0~3 Enable Register 0x78 read-write n 0x0 0x0 CAPENR Capture Input Enable Register There are four capture inputs from pad. Bit0~Bit3 are used to control each inputs ON or OFF. CAPENR Bit 3210 for PWM group A Bit xxx1 ( Capture channel 0 is from P2.0 Bit xx1x ( Capture channel 1 is from P2.1 Bit x1xx ( Capture channel 2 is from P2.2 Bit 1xxx ( Capture channel 3 is from P2.3 Bit 3210 for PWM group B Bit xxx1 ( Capture channel 0 is from P2.4 Bit xx1x ( Capture channel 1 is from P2.5 Bit x1xx ( Capture channel 2 is from P2.6 Bit 1xxx ( Capture channel 3 is from P2.7 0 4 read-write 0 OFF (PWMx multi-function pin input does not affect input capture function.) 0 1 ON (PWMx multi-function pin input will affect its input capture function.) 1 CCR0 CCR0 PWM Capture Control Register 0 0x50 read-write n 0x0 0x0 CAPCH0EN Capture Channel 0 transition Enable/Disable\nWhen Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt. 3 1 read-write 0 Disable capture function on PWM group channel 0 #0 1 Enable capture function on PWM group channel 0 #1 CAPCH1EN Capture PWM Group Channel 1 transition Enable/Disable\nWhen Enable, Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt. 19 1 read-write 0 Disable capture function on PWM group channel 1 #0 1 Enable capture function on PWM group channel 1 #1 CAPIF0 Capture0 Interrupt Indication Flag\n 4 1 read-write CAPIF1 Capture1 Interrupt Indication Flag\n 20 1 read-write CFLRI0 CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nClear this bit by writing a one to it. 7 1 read-write CFLRI1 CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nClear this bit by writing a one to it. 23 1 read-write CFL_IE0 PWM Group Channel 0 Falling Latch Interrupt Enable ON/OFF\nWhen Enable, if Capture detects PWM group channel 0 has falling transition, Capture issues an Interrupt. 2 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CFL_IE1 PWM Group Channel 1 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has falling transition, Capture issues an Interrupt. 18 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CRLRI0 CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware. \nClear this bit by writing a one to it. 6 1 read-write CRLRI1 CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nClear this bit by writing a one to it. 22 1 read-write CRL_IE0 PWM Group Channel 0 Rising Latch Interrupt Enable ON/OFF\nWhen Enable, if Capture detects PWM group channel 0 has rising transition, Capture issues an Interrupt. 1 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 CRL_IE1 PWM Group Channel 1 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has rising transition, Capture issues an Interrupt. 17 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 INV0 PWM Group Channel 0 Inverter ON/OFF\n 0 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 INV1 PWM Group Channel 1 Inverter ON/OFF\n 16 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 CCR2 CCR2 PWM Capture Control Register 2 0x54 read-write n 0x0 0x0 CAPCH2EN Capture Channel 2 transition Enable/Disable\nWhen Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt. 3 1 read-write 0 Disable capture function on PWM group channel 2 #0 1 Enable capture function on PWM group channel 2 #1 CAPCH3EN Capture Channel 3 transition Enable/Disable\nWhen Enable, Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt. 19 1 read-write 0 Disable capture function on PWM group channel 3 #0 1 Enable capture function on PWM group channel 3 #1 CAPIF2 Capture2 Interrupt Indication Flag\nNote: Write 1 to clear this bit to zero. 4 1 read-write CAPIF3 Capture3 Interrupt Indication Flag\nWrite 1 to clear this bit to zero. 20 1 read-write CFLRI2 CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to zero. 7 1 read-write CFLRI3 CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero. 23 1 read-write CFL_IE2 PWM Group Channel 2 Falling Latch Interrupt Enable ON/OFF\nWhen Enable, if Capture detects PWM group channel 2 has falling transition, Capture issues an Interrupt. 2 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CFL_IE3 PWM Group Channel 3 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 3 has falling transition, Capture issues an Interrupt. 18 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CRLRI2 CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to zero. 6 1 read-write CRLRI3 CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero. 22 1 read-write CRL_IE2 PWM Group Channel 2 Rising Latch Interrupt Enable ON/OFF\nWhen Enable, if Capture detects PWM group channel 2 has rising transition, Capture issues an Interrupt. 1 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 CRL_IE3 PWM Group Channel 3 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 3 has rising transition, Capture issues an Interrupt. 17 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 INV2 PWM Group Channel 2 Inverter ON/OFF\n 0 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 INV3 PWM Group Channel 3 Inverter ON/OFF\n 16 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 CFLR0 CFLR0 PWM Capture Falling Latch Register (Channel 0) 0x5C read-only n 0x0 0x0 CFLRx Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition. 0 16 read-only CFLR1 CFLR1 PWM Capture Falling Latch Register (Channel 1) 0x64 read-write n 0x0 0x0 CFLR2 CFLR2 PWM Capture Falling Latch Register (Channel 2) 0x6C read-write n 0x0 0x0 CFLR3 CFLR3 PWM Capture Falling Latch Register (Channel 3) 0x74 read-write n 0x0 0x0 CMR0 CMR0 PWM Comparator Register 0 0x10 read-write n 0x0 0x0 CMRx PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CMR will take effect in next PWM cycle. 0 16 read-write CMR1 CMR1 PWM Comparator Register 1 0x1C read-write n 0x0 0x0 CMR2 CMR2 PWM Comparator Register 2 0x28 read-write n 0x0 0x0 CMR3 CMR3 PWM Comparator Register 3 0x34 read-write n 0x0 0x0 CNR0 CNR0 PWM Counter Register 0 0xC read-write n 0x0 0x0 CNRx PWM Counter/Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle. 0 16 read-write CNR1 CNR1 PWM Counter Register 1 0x18 read-write n 0x0 0x0 CNR2 CNR2 PWM Counter Register 2 0x24 read-write n 0x0 0x0 CNR3 CNR3 PWM Counter Register 3 0x30 read-write n 0x0 0x0 CRLR0 CRLR0 PWM Capture Rising Latch Register (Channel 0) 0x58 read-only n 0x0 0x0 CRLRx Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition. 0 16 read-only CRLR1 CRLR1 PWM Capture Rising Latch Register (Channel 1) 0x60 read-write n 0x0 0x0 CRLR2 CRLR2 PWM Capture Rising Latch Register (Channel 2) 0x68 read-write n 0x0 0x0 CRLR3 CRLR3 PWM Capture Rising Latch Register (Channel 3) 0x70 read-write n 0x0 0x0 CSR CSR PWM Clock Select Register 0x4 read-write n 0x0 0x0 CSR0 Timer 0 Clock Source Selection (PWM timer 0 for group A and PWM timer 4 for group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3) 0 3 read-write CSR1 Timer 1 Clock Source Selection (PWM timer 1 for group A and PWM timer 5 for group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3) 4 3 read-write CSR2 Timer 2 Clock Source Selection (PWM timer 2 for group A and PWM timer 6 for group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3) 8 3 read-write CSR3 Timer 3 Clock Source Selection (PWM timer 3 for group A and PWM timer 7 for group B)\n 12 3 read-write PCR PCR PWM Control Register 0x8 read-write n 0x0 0x0 CH0EN PWM-Timer 0 Enable/Disable Start Run (PWM timer 0 for group A and PWM timer 4 for group B)\n 0 1 read-write 0 Stop corresponding PWM-Timer Running #0 1 Enable corresponding PWM-Timer Start Run #1 CH0INV PWM-Timer 0 Output Inverter ON/OFF (PWM timer 0 for group A and PWM timer 4 for group B)\n 2 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH0MOD PWM-Timer 0 Auto-reload/One-Shot Mode (PWM timer 0 for group A and PWM timer 4 for group B)\nNote: If there is a rising transition at this bit, it will cause CNR0 and CMR0 be clear. 3 1 read-write 0 One-Shot Mode #0 1 Auto-reload Mode #1 CH1EN PWM-Timer 1 Enable/Disable Start Run (PWM timer 1 for group A and PWM timer 5 for group B)\n 8 1 read-write 0 Stop corresponding PWM-Timer Running #0 1 Enable corresponding PWM-Timer Start Run #1 CH1INV PWM-Timer 1 Output Inverter ON/OFF (PWM timer 1 for group A and PWM timer 5 for group B)\n 10 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH1MOD PWM-Timer 1 Auto-reload/One-Shot Mode (PWM timer 1 for group A and PWM timer 5 for group B)\nNote: If there is a rising transition at this bit, it will cause CNR1 and CMR1 be clear. 11 1 read-write 0 One-Shot Mode #0 1 Auto-load Mode #1 CH2EN PWM-Timer 2 Enable/Disable Start Run (PWM timer 2 for group A and PWM timer 6 for group B)\n 16 1 read-write 0 Stop corresponding PWM-Timer Running #0 1 Enable corresponding PWM-Timer Start Run #1 CH2INV PWM-Timer 2 Output Inverter ON/OFF (PWM timer 2 for group A and PWM timer 6 for group B)\n 18 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH2MOD PWM-Timer 2 Auto-reload/One-Shot Mode (PWM timer 2 for group A and PWM timer 6 for group B)\nNote: If there is a rising transition at this bit, it will cause CNR2 and CMR2 be clear. 19 1 read-write 0 One-Shot Mode #0 1 Auto-reload Mode #1 CH3EN PWM-Timer 3 Enable/Disable Start Run (PWM timer 3 for group A and PWM timer 7 for group B)\n 24 1 read-write 0 Stop corresponding PWM-Timer Running #0 1 Enable corresponding PWM-Timer Start Run #1 CH3INV PWM-Timer 3 Output Inverter ON/OFF (PWM timer 3 for group A and PWM timer 7 for group B)\n 26 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH3MOD PWM-Timer 3 Auto-reload/One-Shot Mode (PWM timer 3 for group A and PWM timer 7 for group B)\nNote: If there is a rising transition at this bit, it will cause CNR3 and CMR3 be clear. 27 1 read-write 0 One-Shot Mode #0 1 Auto-reload Mode #1 DZEN01 Dead-Zone 0 Generator Enable/Disable (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nNote: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B. 4 1 read-write 0 Disable #0 1 Enable #1 DZEN23 Dead-Zone 2 Generator Enable/Disable (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nNote: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B. 5 1 read-write 0 Disable #0 1 Enable #1 PDR0 PDR0 PWM Data Register 0 0x14 read-only n 0x0 0x0 PDRx PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter. 0 16 read-only PDR1 PDR1 PWM Data Register 1 0x20 read-write n 0x0 0x0 PDR2 PDR2 PWM Data Register 2 0x2C read-write n 0x0 0x0 PDR3 PDR3 PWM Data Register 3 0x38 read-write n 0x0 0x0 PIER PIER PWM Interrupt Enable Register 0x40 read-write n 0x0 0x0 PWMIE0 PWM channel 0 Interrupt Enable\n 0 1 read-write 0 Disable #0 1 Enable #1 PWMIE1 PWM channel 1 Interrupt Enable\n 1 1 read-write 0 Disable #0 1 Enable #1 PWMIE2 PWM channel 2 Interrupt Enable\n 2 1 read-write 0 Disable #0 1 Enable #1 PWMIE3 PWM channel 3 Interrupt Enable\n 3 1 read-write 0 Disable #0 1 Enable #1 PIIR PIIR PWM Interrupt Indication Register 0x44 read-write n 0x0 0x0 PWMIF0 PWM channel 0 Interrupt Status\nFlag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing a one to it. 0 1 read-write PWMIF1 PWM channel 1 Interrupt Status\nFlag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing a one to it. 1 1 read-write PWMIF2 PWM channel 2 Interrupt Status\nFlag is set by hardware when PWM2 down counter reaches zero, software can clear this bit by writing a one to it. 2 1 read-write PWMIF3 PWM channel 3 Interrupt Status\nFlag is set by hardware when PWM3 down counter reaches zero, software can clear this bit by writing a one to it. 3 1 read-write POE POE PWM Output Enable Register for Channel 0~3 0x7C read-write n 0x0 0x0 PWM0 PWM Channel 0 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function 0 1 read-write 0 Disable PWM channel 0 output to pin #0 1 Enable PWM channel 0 output to pin #1 PWM1 PWM Channel 1 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function 1 1 read-write 0 Disable PWM channel 1 output to pin #0 1 Enable PWM channel 1 output to pin #1 PWM2 PWM Channel 2 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function 2 1 read-write 0 Disable PWM channel 2 output to pin #0 1 Enable PWM channel 2 output to pin #1 PWM3 PWM Channel 3 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function 3 1 read-write 0 Disable PWM channel 3 output to pin #0 1 Enable PWM channel 3 output to pin #1 PPR PPR PWM Pre-scale Register 0x0 read-write n 0x0 0x0 CP01 Clock prescaler 0 (PWM counter 0/1 for group A and PWM counter 4/ 5 for group B) Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter 0 8 read-write CP23 Clock prescaler 2 (PWM counter 2/ 3 for group A and PWM counter 6/ 7 for group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter\n 8 8 read-write DZI01 Dead zone interval register for pair of channel 0 and channel 1 (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from corresponding CSR bits. 16 8 read-write DZI23 Dead zone interval register for pair of channel2 and channel3 (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from corresponding CSR bits. 24 8 read-write SCS SCS Register Map SCS 0x0 0x10 0xC registers n 0x100 0x4 registers n 0x180 0x4 registers n 0x200 0x4 registers n 0x280 0x4 registers n 0x400 0x20 registers n 0xD00 0x8 registers n 0xD0C 0x8 registers n 0xD1C 0x8 registers n AIRCR AIRCR Application Interrupt and Reset Control Register 0xD0C -1 read-write n 0x0 0x0 SYSRESETREQ Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence. 2 1 read-write VECTCLRACTIVE Set this bit to 1 will clears all active state information for fixed and configurable exceptions.\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack. 1 1 read-write VECTORKEY When write this register, this field should be 0x05FA, otherwise the write action will be unpredictable. 16 16 read-write CPUID CPUID CPUID Register 0xD00 -1 read-only n 0x0 0x0 IMPLEMENTER None 24 8 read-only PART Reads as 0xC for ARMv6-M parts 16 4 read-only PARTNO Reads as 0xC20. 4 12 read-only REVISION Reads as 0x0 0 4 read-only ICSR ICSR Interrupt Control and State Register 0xD04 read-write n 0x0 0x0 ISRPENDING Interrupt pending flag, excluding NMI and Faults:\nThis is a read only bit. 22 1 read-write 0 interrupt not pending #0 1 interrupt pending #1 ISRPREEMPT If set, a pending exception will be serviced on exit from the debug halt state.\nThis is a read only bit. 23 1 read-write NMIPENDSET NMI set-pending bit\nWrite:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 31 1 read-write 0 no effect\nNMI exception is not pending #0 1 changes NMI exception state to pending.\nNMI exception is pending #1 PENDSTCLR SysTick exception clear-pending bit.\nWrite:\nThis is a write only bit. On a register read its value is Unknown. 25 1 read-write 0 no effect #0 1 removes the pending state from the SysTick exception #1 PENDSTSET SysTick exception set-pending bit.\nWrite:\n 26 1 read-write 0 no effect\nSysTick exception is not pending #0 1 changes SysTick exception state to pending.\nSysTick exception is pending #1 PENDSVCLR PendSV clear-pending bit.\nWrite:\nThis is a write only bit. 27 1 read-write 0 no effect #0 1 removes the pending state from the PendSV exception #1 PENDSVSET PendSV set-pending bit.\nWrite:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending. 28 1 read-write 0 no effect\nPendSV exception is not pending #0 1 changes PendSV exception state to pending.\nPendSV exception is pending #1 VECTACTIVE Contains the active exception number\n 0 6 read-write 0 Thread mode 0 VECTPENDING Indicates the exception number of the highest priority pending enabled exception:\n 12 6 read-write 0 no pending exceptions 0 NVIC_ICER NVIC_ICER IRQ0 ~ IRQ31 Clear-enable Control Register 0x180 read-write n 0x0 0x0 CLRENA Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). \nWriting 1 will disable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with the current enable state. 0 32 read-write NVIC_ICPR NVIC_ICPR IRQ0 ~ IRQ31 Clear-pending Control Register 0x280 read-write n 0x0 0x0 CLRPEND Writing 1 to a bit un-pends the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the current pending state. 0 32 read-write NVIC_IPR0 NVIC_IPR0 IRQ0 ~ IRQ3 Interrupt Priority Control Register 0x400 read-write n 0x0 0x0 PRI_0 Priority of IRQ0 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_1 Priority of IRQ1 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_2 Priority of IRQ2 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_3 Priority of IRQ3 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR1 NVIC_IPR1 IRQ4 ~ IRQ7 Interrupt Priority Control Register 0x404 read-write n 0x0 0x0 PRI_4 Priority of IRQ4 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_5 Priority of IRQ5 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_6 Priority of IRQ6 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_7 Priority of IRQ7 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR2 NVIC_IPR2 IRQ8 ~ IRQ11 Interrupt Priority Control Register 0x408 read-write n 0x0 0x0 PRI_10 Priority of IRQ10 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_11 Priority of IRQ11 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write PRI_8 Priority of IRQ8 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_9 Priority of IRQ9 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write NVIC_IPR3 NVIC_IPR3 IRQ12 ~ IRQ15 Interrupt Priority Control Register 0x40C read-write n 0x0 0x0 PRI_12 Priority of IRQ12 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_13 Priority of IRQ13 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_14 Priority of IRQ14 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_15 Priority of IRQ15 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR4 NVIC_IPR4 IRQ16 ~ IRQ19 Interrupt Priority Control Register 0x410 read-write n 0x0 0x0 PRI_16 Priority of IRQ16 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_17 Priority of IRQ17 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_18 Priority of IRQ18 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_19 Priority of IRQ19 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR5 NVIC_IPR5 IRQ20 ~ IRQ23 Interrupt Priority Control Register 0x414 read-write n 0x0 0x0 PRI_20 Priority of IRQ20 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_21 Priority of IRQ21 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_22 Priority of IRQ22 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_23 Priority of IRQ23 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR6 NVIC_IPR6 IRQ24 ~ IRQ27 Interrupt Priority Control Register 0x418 read-write n 0x0 0x0 PRI_24 Priority of IRQ24 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_25 Priority of IRQ25 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_26 Priority of IRQ26 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_27 Priority of IRQ27 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR7 NVIC_IPR7 IRQ28 ~ IRQ31 Interrupt Priority Control Register 0x41C read-write n 0x0 0x0 PRI_28 Priority of IRQ28 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_29 Priority of IRQ29 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_30 Priority of IRQ30 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_31 Priority of IRQ31 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_ISER NVIC_ISER IRQ0 ~ IRQ31 Set-enable Control Register 0x100 read-write n 0x0 0x0 SETENA Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). \nWriting 1 will enable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with the current enable state. 0 32 read-write NVIC_ISPR NVIC_ISPR IRQ0 ~ IRQ31 Set-pending Control Register 0x200 read-write n 0x0 0x0 SETPEND Writing 1 to a bit to set pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the current pending state. 0 32 read-write SCR SCR System Control Register 0xD10 read-write n 0x0 0x0 SEVONPEND Send Event on Pending bit:\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event. 4 1 read-write 0 only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded #0 1 enabled events and all interrupts, including disabled interrupts, can wakeup the processor #1 SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low power mode:\n 2 1 read-write 0 sleep #0 1 deep sleep #1 SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 1 1 read-write 0 do not sleep when returning to Thread mode #0 1 enter sleep, or deep sleep, on return from an ISR to Thread mode #1 SHPR2 SHPR2 System Handler Priority Register 2 0xD1C read-write n 0x0 0x0 PRI_11 Priority of system handler 11 - SVCall 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write SHPR3 SHPR3 System Handler Priority Register 3 0xD20 read-write n 0x0 0x0 PRI_14 Priority of system handler 14 - PendSV 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_15 Priority of system handler 15 - SysTick 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write SYST_CSR SYST_CSR SysTick Control and Status Register 0x10 read-write n 0x0 0x0 CLKSRC None 2 1 read-write 0 Clock source is optional, refer to STCLK_S #0 1 Core clock used for SysTick #1 COUNTFLAG Returns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register. 16 1 read-write ENABLE None 0 1 read-write 0 The counter is disabled #0 1 The counter will operate in a multi-shot manner #1 TICKINT None 1 1 read-write 0 Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended #1 SYST_CVR SYST_CVR SysTick Current Value Register 0x18 read-write n 0x0 0x0 CURRENT Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value register). 0 24 read-write SYST_RVR SYST_RVR SysTick Reload Value Register 0x14 read-write n 0x0 0x0 RELOAD Value to load into the Current Value register when the counter reaches 0. 0 24 read-write SPI0 SPI Register Map SPI 0x0 0x0 0xC registers n 0x10 0x8 registers n 0x20 0x8 registers n 0x34 0x4 registers n SPI_CNTRL SPI_CNTRL Control and Status Register 0x0 -1 read-write n 0x0 0x0 CLKP Clock Polarity\n 11 1 read-write 0 SPICLK idle low #0 1 SPICLK idle high #1 GO_BUSY Go and Busy Status\nDuring the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNOTE: All registers should be set before writing 1 to this GO_BUSY bit. 0 1 read-write 0 Writing 0 to this bit to stop data transfer if SPI is transferring #0 1 In master mode, writing 1 to this bit to start the SPI data transfer in slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master #1 IE Interrupt Enable\n 17 1 read-write 0 Disable SPI Interrupt #0 1 Enable SPI Interrupt #1 IF Interrupt Flag\n 16 1 read-write 0 It indicates that the transfer dose not finish yet #0 1 It indicates that the transfer is done #1 LSB LSB First\n 10 1 read-write 0 The MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the TX_BIT_LEN field) #0 1 The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position in the RX register (bit 0 of SPI_RX0/1) #1 REORDER Reorder Mode Select\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\n2. In slave mode with level-trigger configuration, if the byte suspend function is enabled, the slave select pin must be kept at active state during the successive four bytes transfer. 19 2 read-write 0 Disable both Byte Reorder and byte suspend functions #00 1 Enable Byte Reorder function and insert a byte suspend interval (2~17 serial clock cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word) #01 2 Enable Byte Reorder function, but disable byte suspend function #10 3 Disable Byte Reorder function, but insert a suspend interval (2~17 serial clock cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word) #11 RX_NEG Receive At Negative Edge\n 1 1 read-write 0 The received data input signal is latched at the rising edge of SPICLK #0 1 The received data input signal is latched at the falling edge of SPICLK #1 SLAVE Slave Mode Indication\n 18 1 read-write 0 Master mode #0 1 Slave mode #1 SP_CYCLE Suspend Interval (Master Only)\n 12 4 read-write TX_BIT_LEN Transmit Bit Length\nThis field specifies how many bits are transmitted in one transaction. Up to 32 bits can be transmitted.\n 3 5 read-write TX_NEG Transmit At Negative Edge\n 2 1 read-write 0 The transmitted data output signal is changed at the rising edge of SPICLK #0 1 The transmitted data output signal is changed at the falling edge of SPICLK #1 TX_NUM Numbers of Transmit/Receive Word \nThis field specifies how many transmit/receive word numbers should be executed in one transfer.\nNote: in slave mode with level-trigger configuration, if TX_NUM is set to 01, the slave select pin must be kept at active state during the successive data transfer. 8 2 read-write 0 Only one transmit/receive word will be executed in one transfer #00 1 Two successive transmit/receive word will be executed in one transfer #01 2 Reserved #10 3 Reserved #11 VARCLK_EN Variable Clock Enable (Master Only)\nNote that when enable this VARCLK_EN bit, the setting of TX_BIT_LEN must be programmed as 0x10 (16 bits mode) 23 1 read-write 0 The serial clock output frequency is fixed and decided only by the value of DIVIDER #0 1 The serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2 #1 SPI_DIVIDER SPI_DIVIDER Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider Register (master only)\nThe value in this field is the frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIn slave mode, the period of SPI clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK. 0 16 read-write DIVIDER2 Clock Divider 2 Register (master only)\nThe value in this field is the 2nd frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIf VARCLK_EN is cleared to 0, this setting is unmeaning. 16 16 read-write SPI_RX0 SPI_RX0 Data Receive Register 0 0x10 read-only n 0x0 0x0 RX Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register. For example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. The values of the other bits are unknown.\nNOTE: The Data Receive Registers are read only registers. 0 32 read-only SPI_RX1 SPI_RX1 Data Receive Register 1 0x14 read-write n 0x0 0x0 SPI_SSR SPI_SSR Slave Select Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Select (Master only)\n 3 1 read-write 0 If this bit is cleared, slave select signal will be asserted and de-asserted by setting and clearing SSR[0] #0 1 If this bit is set, SPISS0/1 signal will be generated automatically. It means that device/slave select signal, which is set in SSR[0], will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished #1 LTRIG_FLAG Level Trigger Flag\nWhen the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only 5 1 read-write 0 The transaction number or the transferred bit length of one transaction does not meet the specified requirements #0 1 The transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN #1 SSR Slave Select Register (Master only) If AUTOSS bit is cleared, writing 1 to this bit sets the SPISSx line to an active state and writing 0 sets the line back to inactive state. If AUTOSS bit is set, writing 0 to this bit will keep the SPISSx line at inactive state writing 1 to this bit will select the SPISSx line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active state of SPISSx is specified in SS_LVL). Note: SPISSx is always defined as slave select input in slave mode. 0 1 read-write SS_LTRIG Slave Select Level Trigger (Slave only)\n 4 1 read-write 0 The input slave select signal is edge-trigger. This is the default value. It depends on SS_LVL to decide the signal is active at falling-edge or rising-edge #0 1 The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high #1 SS_LVL Slave Select Active Level \nIt defines the active state of slave select signal (SPISS0/1).\n 2 1 read-write 0 The slave select signal SPISS0/1 is active at low-level/falling-edge #0 1 The slave select signal SPISS0/1 is active at high-level/rising-edge #1 SPI_TX0 SPI_TX0 Data Transmit Register 0 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register. \nFor example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the SPI controller will perform two 32-bit transmit/receive successive using the same setting. The transmission sequence is TX0[31:0] first and then TX1[31:0]. 0 32 write-only SPI_TX1 SPI_TX1 Data Transmit Register 1 0x24 read-write n 0x0 0x0 SPI_VARCLK SPI_VARCLK Variable Clock Pattern Register 0x34 -1 read-write n 0x0 0x0 VARCLK Variable Clock Pattern \nThe value in this field is the frequency patterns of the SPI clock. If the bit pattern of VARCLK is '0', the output frequency of SPICLK is according the value of DIVIDER. If the bit patterns of VARCLK are '1', the output frequency of SPICLK is according the value of DIVIDER2. Refer to register SPI_DIVIDER.\nRefer to Figure 651 for Variable Clock timing diagram. 0 32 read-write SPI1 SPI Register Map SPI 0x0 0x0 0xC registers n 0x10 0x8 registers n 0x20 0x8 registers n 0x34 0x4 registers n SPI_CNTRL SPI_CNTRL Control and Status Register 0x0 -1 read-write n 0x0 0x0 CLKP Clock Polarity\n 11 1 read-write 0 SPICLK idle low #0 1 SPICLK idle high #1 GO_BUSY Go and Busy Status\nDuring the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNOTE: All registers should be set before writing 1 to this GO_BUSY bit. 0 1 read-write 0 Writing 0 to this bit to stop data transfer if SPI is transferring #0 1 In master mode, writing 1 to this bit to start the SPI data transfer in slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master #1 IE Interrupt Enable\n 17 1 read-write 0 Disable SPI Interrupt #0 1 Enable SPI Interrupt #1 IF Interrupt Flag\n 16 1 read-write 0 It indicates that the transfer dose not finish yet #0 1 It indicates that the transfer is done #1 LSB LSB First\n 10 1 read-write 0 The MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the TX_BIT_LEN field) #0 1 The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position in the RX register (bit 0 of SPI_RX0/1) #1 REORDER Reorder Mode Select\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\n2. In slave mode with level-trigger configuration, if the byte suspend function is enabled, the slave select pin must be kept at active state during the successive four bytes transfer. 19 2 read-write 0 Disable both Byte Reorder and byte suspend functions #00 1 Enable Byte Reorder function and insert a byte suspend interval (2~17 serial clock cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word) #01 2 Enable Byte Reorder function, but disable byte suspend function #10 3 Disable Byte Reorder function, but insert a suspend interval (2~17 serial clock cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word) #11 RX_NEG Receive At Negative Edge\n 1 1 read-write 0 The received data input signal is latched at the rising edge of SPICLK #0 1 The received data input signal is latched at the falling edge of SPICLK #1 SLAVE Slave Mode Indication\n 18 1 read-write 0 Master mode #0 1 Slave mode #1 SP_CYCLE Suspend Interval (Master Only)\n 12 4 read-write TX_BIT_LEN Transmit Bit Length\nThis field specifies how many bits are transmitted in one transaction. Up to 32 bits can be transmitted.\n 3 5 read-write TX_NEG Transmit At Negative Edge\n 2 1 read-write 0 The transmitted data output signal is changed at the rising edge of SPICLK #0 1 The transmitted data output signal is changed at the falling edge of SPICLK #1 TX_NUM Numbers of Transmit/Receive Word \nThis field specifies how many transmit/receive word numbers should be executed in one transfer.\nNote: in slave mode with level-trigger configuration, if TX_NUM is set to 01, the slave select pin must be kept at active state during the successive data transfer. 8 2 read-write 0 Only one transmit/receive word will be executed in one transfer #00 1 Two successive transmit/receive word will be executed in one transfer #01 2 Reserved #10 3 Reserved #11 VARCLK_EN Variable Clock Enable (Master Only)\nNote that when enable this VARCLK_EN bit, the setting of TX_BIT_LEN must be programmed as 0x10 (16 bits mode) 23 1 read-write 0 The serial clock output frequency is fixed and decided only by the value of DIVIDER #0 1 The serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2 #1 SPI_DIVIDER SPI_DIVIDER Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider Register (master only)\nThe value in this field is the frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIn slave mode, the period of SPI clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK. 0 16 read-write DIVIDER2 Clock Divider 2 Register (master only)\nThe value in this field is the 2nd frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIf VARCLK_EN is cleared to 0, this setting is unmeaning. 16 16 read-write SPI_RX0 SPI_RX0 Data Receive Register 0 0x10 read-only n 0x0 0x0 RX Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register. For example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. The values of the other bits are unknown.\nNOTE: The Data Receive Registers are read only registers. 0 32 read-only SPI_RX1 SPI_RX1 Data Receive Register 1 0x14 read-write n 0x0 0x0 SPI_SSR SPI_SSR Slave Select Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Select (Master only)\n 3 1 read-write 0 If this bit is cleared, slave select signal will be asserted and de-asserted by setting and clearing SSR[0] #0 1 If this bit is set, SPISS0/1 signal will be generated automatically. It means that device/slave select signal, which is set in SSR[0], will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished #1 LTRIG_FLAG Level Trigger Flag\nWhen the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only 5 1 read-write 0 The transaction number or the transferred bit length of one transaction does not meet the specified requirements #0 1 The transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN #1 SSR Slave Select Register (Master only) If AUTOSS bit is cleared, writing 1 to this bit sets the SPISSx line to an active state and writing 0 sets the line back to inactive state. If AUTOSS bit is set, writing 0 to this bit will keep the SPISSx line at inactive state writing 1 to this bit will select the SPISSx line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active state of SPISSx is specified in SS_LVL). Note: SPISSx is always defined as slave select input in slave mode. 0 1 read-write SS_LTRIG Slave Select Level Trigger (Slave only)\n 4 1 read-write 0 The input slave select signal is edge-trigger. This is the default value. It depends on SS_LVL to decide the signal is active at falling-edge or rising-edge #0 1 The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high #1 SS_LVL Slave Select Active Level \nIt defines the active state of slave select signal (SPISS0/1).\n 2 1 read-write 0 The slave select signal SPISS0/1 is active at low-level/falling-edge #0 1 The slave select signal SPISS0/1 is active at high-level/rising-edge #1 SPI_TX0 SPI_TX0 Data Transmit Register 0 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register. \nFor example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the SPI controller will perform two 32-bit transmit/receive successive using the same setting. The transmission sequence is TX0[31:0] first and then TX1[31:0]. 0 32 write-only SPI_TX1 SPI_TX1 Data Transmit Register 1 0x24 read-write n 0x0 0x0 SPI_VARCLK SPI_VARCLK Variable Clock Pattern Register 0x34 -1 read-write n 0x0 0x0 VARCLK Variable Clock Pattern \nThe value in this field is the frequency patterns of the SPI clock. If the bit pattern of VARCLK is '0', the output frequency of SPICLK is according the value of DIVIDER. If the bit patterns of VARCLK are '1', the output frequency of SPICLK is according the value of DIVIDER2. Refer to register SPI_DIVIDER.\nRefer to Figure 651 for Variable Clock timing diagram. 0 32 read-write TMR01 TIMER Register Map TIMER 0x0 0x0 0x10 registers n 0x20 0x10 registers n TCMPR0 TCMPR0 Timer0 Compare Register 0x4 read-write n 0x0 0x0 TCMP Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP. 0 24 read-write TCMPR1 TCMPR1 Timer1 Compare Register 0x24 read-write n 0x0 0x0 TCSR0 TCSR0 Timer0 Control and Status Register 0x0 -1 read-write n 0x0 0x0 CACT Timer Active Status Bit (Read only)\nThis bit indicates the status of timer.\n 25 1 read-only 0 Timer is not active #0 1 Timer is active #1 CEN Timer Enable Bit\n 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 CRST Timer Reset Bit\nSet this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0.\n 26 1 read-write 0 No effect #0 1 Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit #1 DBGACK_TMR ICE debug mode acknowledge Disable (write-protected)\nTIMER counter will be held while ICE debug mode acknowledged. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement disabled #1 IE Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated timer is equal to TCMPR. 29 1 read-write 0 Disable timer Interrupt #0 1 Enable timer Interrupt #1 MODE Timer Operating Mode\n 27 2 read-write PRESCALE Pre-scale Counter\n 0 8 read-write TDR_EN Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value. \n 16 1 read-write 0 Timer Data Register update disable #0 1 Timer Data Register update enable #1 TCSR1 TCSR1 Timer1 Control and Status Register 0x20 read-write n 0x0 0x0 TDR0 TDR0 Timer0 Data Register 0xC read-only n 0x0 0x0 TDR Timer Data Register\nWhen TCSR.TDR_EN is set to 1, the internal 24-bit up-timer value will be loaded into TDR. User can read this register for the up-timer value. 0 24 read-only TDR1 TDR1 Timer1 Data Register 0x2C read-write n 0x0 0x0 TISR0 TISR0 Timer0 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt status of Timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit. 0 1 read-write TISR1 TISR1 Timer1 Interrupt Status Register 0x28 read-write n 0x0 0x0 TMR23 TIMER Register Map TIMER 0x0 0x0 0x10 registers n 0x20 0x10 registers n TCMPR2 TCMPR2 Timer2 Compare Register 0x4 read-write n 0x0 0x0 TCMP Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP. 0 24 read-write TCMPR3 TCMPR3 Timer3 Compare Register 0x24 read-write n 0x0 0x0 TCSR2 TCSR2 Timer2 Control and Status Register 0x0 -1 read-write n 0x0 0x0 CACT Timer Active Status Bit (Read only)\nThis bit indicates the status of timer.\n 25 1 read-only 0 Timer is not active #0 1 Timer is active #1 CEN Timer Enable Bit\n 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 CRST Timer Reset Bit\nSet this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0.\n 26 1 read-write 0 No effect #0 1 Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit #1 DBGACK_TMR ICE debug mode acknowledge Disable (write-protected)\nTIMER counter will be held while ICE debug mode acknowledged. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement disabled #1 IE Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated timer is equal to TCMPR. 29 1 read-write 0 Disable timer Interrupt #0 1 Enable timer Interrupt #1 MODE Timer Operating Mode\n 27 2 read-write PRESCALE Pre-scale Counter\n 0 8 read-write TDR_EN Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value. \n 16 1 read-write 0 Timer Data Register update disable #0 1 Timer Data Register update enable #1 TCSR3 TCSR3 Timer3 Control and Status Register 0x20 read-write n 0x0 0x0 TDR2 TDR2 Timer2 Data Register 0xC read-only n 0x0 0x0 TDR Timer Data Register\nWhen TCSR.TDR_EN is set to 1, the internal 24-bit up-timer value will be loaded into TDR. User can read this register for the up-timer value. 0 24 read-only TDR3 TDR3 Timer3 Data Register 0x2C read-write n 0x0 0x0 TISR2 TISR2 Timer2 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt status of Timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit. 0 1 read-write TISR3 TISR3 Timer3 Interrupt Status Register 0x28 read-write n 0x0 0x0 UART0 UART Register Map UART 0x0 0x0 0x30 registers n UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ADDR_MATCH Address match value register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write RS_485_AAD RS-485 Auto Address Detection Operation Mode (AAD) \nNote: It can't be active with RS-485_NMM operation mode. 9 1 read-write 0 Disable RS-485 Auto Address Detection Operation Mode (AAD) #0 1 Enable RS-485 Auto Address Detection Operation Mode (AAD) #1 RS_485_ADD_EN RS-485 Address Detection Enable\nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode. 15 1 read-write 0 Disable address detection mode #0 1 Enable address detection mode #1 RS_485_AUD RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 Disable RS-485 Auto Direction Operation Mode (AUO) #0 1 Enable RS-485 Auto Direction Operation Mode (AUO) #1 RS_485_NMM RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It can't be active with RS-485_AAD operation mode. 8 1 read-write 0 Disable RS-485 Normal Multi-drop Operation Mode (NMM) #0 1 Enable RS-485 Normal Multi-drop Operation Mode (NMM) #1 UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 -1 read-write n 0x0 0x0 BRD Baud Rate Divider \nThe field indicated the baud rate divider 0 16 read-write DIVIDER_X Divider X\n 24 4 read-write DIV_X_EN Divider X Enable\nRefer to the Table 610 for more information.\nNOTE: When in IrDA mode, this bit must disable. 29 1 read-write 0 Disable divider X (the equation of M = 16) #0 1 Enable divider X (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 DIV_X_ONE Divider X equal 1\nRefer to the Table 610 for more information. 28 1 read-write 0 Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3) #1 UA_FCR UA_FCR UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt (INT_RDA) Trigger Level\n 4 4 read-write RFR RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles. 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the RX internal state machine and pointers #1 RTS_TRI_LEV RTS Trigger Level for Auto-flow Control Use \n 16 4 read-write RX_DIS Receiver Disable register.\nThe receiver is disabled or not (set 1 is disable receiver)\n1: Disable Receiver\n0: Enable Receiver\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed. 8 1 read-write TFR TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles. 2 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the TX internal state machine and pointers #1 UA_FSR UA_FSR UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 BIF Break Interrupt Flag (Read Only) This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit. NOTE: This bit is read only, but can be cleared by writing '1' to it. 6 1 read-only FEF Framing Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit. NOTE: This bit is read only, but can be cleared by writing '1' to it. 5 1 read-only PEF Parity Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit. NOTE: This bit is read only, but can be cleared by writing '1' to it. 4 1 read-only RS_485_ADD_DETF RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNOTE: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only RX_EMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only RX_OVER Receiver FIFO Over (Read Only)\nThis bit indicates RX FIFO overrunning or not.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 15 bytes of UART0/UART1, this bit will be set. Otherwise is cleared by hardware. 15 1 read-only RX_POINTER RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one. 8 6 read-only TE_FLAG Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only TX_EMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). 22 1 read-only TX_FULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to16(UART0/UART1), otherwise is cleared by hardware. 23 1 read-only TX_OVER_IF TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it. 24 1 read-only TX_POINTER TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one. 16 6 read-only UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUN_SEL Function Select Enable\n 0 2 read-write 0 UART Function #00 1 Reserved #01 2 Enable IrDA Function #10 3 Enable RS-485 Function #11 UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 AUTO_CTS_EN CTS Auto Flow Control Enable\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 read-write 0 Disable CTS auto flow control #0 1 Enable CTS auto flow control #1 AUTO_RTS_EN RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal. 12 1 read-write 0 Disable RTS auto flow control #0 1 Enable RTS auto flow control #1 MODEM_IEN Modem Status Interrupt Enable \n 3 1 read-write 0 Mask off INT_MODEM #0 1 Enable INT_MODEM #1 RDA_IEN Receive Data Available Interrupt Enable.\n 0 1 read-write 0 Mask off INT_RDA #0 1 Enable INT_RDA #1 RLS_IEN Receive Line Status Interrupt Enable \n 2 1 read-write 0 Mask off INT_RLS #0 1 Enable INT_RLS #1 RTO_IEN RX Time Out Interrupt Enable\n 4 1 read-write 0 Mask off INT_TOUT #0 1 Enable INT_TOUT #1 THRE_IEN Transmit Holding Register Empty Interrupt Enable\n 1 1 read-write 0 Mask off INT_THRE #0 1 Enable INT_THRE #1 TIME_OUT_EN Time Out Counter Enable\n 11 1 read-write 0 Disable Time-out counter #0 1 Enable Time-out counter #1 WAKE_EN UART Wake-up Function Enable\n 6 1 read-write 0 Disable UART wake-up function #0 1 Enable UART wake-up function, when the chip is in power down mode, an external CTS change will wake-up chip from power down mode #1 UA_IRCR UA_IRCR UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 INV_RX INV_RX\n 6 1 read-write 0 No inversion #0 1 Inverse RX input signal #1 INV_TX INV_TX\n 5 1 read-write 0 No inversion #0 1 Inverse TX output signal #1 TX_SELECT TX_SELECT\n 1 1 read-write 0 Enable IrDA receiver #0 1 Enable IrDA transmitter #1 UA_ISR UA_ISR UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 BUF_ERR_IF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. 5 1 read-only BUF_ERR_INT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n 13 1 read-only 0 No buffer error interrupt is generated #0 1 The buffer error interrupt is generated #1 MODEM_IF MODEM Interrupt Flag (Read Only)\nNOTE: Write 1 to clear this bit to zero. 3 1 read-only MODEM_INT MODEM Status Interrupt Indicator To Interrupt Controller (Read Only). \nAn AND output with inputs of MODEM_IEN and MODEM_IF 11 1 read-only RDA_IF Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNOTE: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL). 0 1 read-only RDA_INT Receive Data Available Interrupt Indicator To Interrupt Controller (Read Only).\nAn AND output with inputs of RDA_IEN and RDA_IF 8 1 read-only RLS_IF Receive Line Interrupt Flag (Read Only). This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated. NOTE: Write 1 to clear this bit to zero. 2 1 read-only RLS_INT Receive Line Status Interrupt Indicator To Interrupt Controller (Read Only). \nAn AND output with inputs of RLS_IEN and RLS_IF 10 1 read-only THRE_IF Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNOTE: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only THRE_INT Transmit Holding Register Empty Interrupt Indicator To Interrupt Controller (Read Only).\nAn AND output with inputs of THRE_IEN and THRE_IF 9 1 read-only TOUT_IF Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNOTE: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 4 1 read-only TOUT_INT Time Out Interrupt Indicator To Interrupt Controller (Read Only)\nAn AND output with inputs of RTO_IEN and TOUT_IF 12 1 read-only UA_LCR UA_LCR UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write EPE Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of STOP bit Two STOP bit is generated when 6-, 7- and 8-bit word length is selected. 2 1 read-write 0 One STOP bit is generated in the transmitted data #0 1 One and a half STOP bit is generated in the transmitted data when 5-bit word length is selected #1 PBE Parity Bit Enable\n 3 1 read-write 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 SPE Stick Parity Enable\n 5 1 read-write 0 Stick parity disabled #0 1 If bit 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0. If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1 #1 WLS Word Length Select\n 0 2 read-write UA_MCR UA_MCR UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 LEV_RTS RTS Trigger Level\n 9 1 read-write 0 low level triggered #0 1 high level triggered #1 RTS RTS (Request-To-Send) Signal \n1: Drive RTS pin to logic 1 (If the LEV_RTS set to high level triggered). 1 1 read-write 0 Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered) #0 1 Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered) #1 RTS_ST RTS Pin State (Read Only)\nThis bit is the output pin status of RTS. 13 1 read-only UA_MSR UA_MSR UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTS_ST CTS Pin Status (Read Only)\nThis bit is the pin status of CTS. 4 1 read-only DCTSF Detect CTS State Change Flag (Read Only) \nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nNOTE: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only LEV_CTS CTS Trigger Level\nThis bit can change the CTS trigger level to send TX_FIFO data.\n 8 1 read-write 0 high level triggered #0 1 low level triggered #1 UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first). 0 8 read-only UA_THR UA_THR UART Transmit Holding Register UA_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first). 0 8 write-only UA_TOR UA_TOR UART Time Out Register 0x20 read-write n 0x0 0x0 DLY TX Delay time value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit. 8 8 read-write TOIC Time Out Interrupt Comparator\n 0 7 read-write UART1 UART Register Map UART 0x0 0x0 0x30 registers n UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ADDR_MATCH Address match value register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write RS_485_AAD RS-485 Auto Address Detection Operation Mode (AAD) \nNote: It can't be active with RS-485_NMM operation mode. 9 1 read-write 0 Disable RS-485 Auto Address Detection Operation Mode (AAD) #0 1 Enable RS-485 Auto Address Detection Operation Mode (AAD) #1 RS_485_ADD_EN RS-485 Address Detection Enable\nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode. 15 1 read-write 0 Disable address detection mode #0 1 Enable address detection mode #1 RS_485_AUD RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 Disable RS-485 Auto Direction Operation Mode (AUO) #0 1 Enable RS-485 Auto Direction Operation Mode (AUO) #1 RS_485_NMM RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It can't be active with RS-485_AAD operation mode. 8 1 read-write 0 Disable RS-485 Normal Multi-drop Operation Mode (NMM) #0 1 Enable RS-485 Normal Multi-drop Operation Mode (NMM) #1 UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 -1 read-write n 0x0 0x0 BRD Baud Rate Divider \nThe field indicated the baud rate divider 0 16 read-write DIVIDER_X Divider X\n 24 4 read-write DIV_X_EN Divider X Enable\nRefer to the Table 610 for more information.\nNOTE: When in IrDA mode, this bit must disable. 29 1 read-write 0 Disable divider X (the equation of M = 16) #0 1 Enable divider X (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 DIV_X_ONE Divider X equal 1\nRefer to the Table 610 for more information. 28 1 read-write 0 Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3) #1 UA_FCR UA_FCR UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt (INT_RDA) Trigger Level\n 4 4 read-write RFR RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles. 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the RX internal state machine and pointers #1 RTS_TRI_LEV RTS Trigger Level for Auto-flow Control Use \n 16 4 read-write RX_DIS Receiver Disable register.\nThe receiver is disabled or not (set 1 is disable receiver)\n1: Disable Receiver\n0: Enable Receiver\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed. 8 1 read-write TFR TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles. 2 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the TX internal state machine and pointers #1 UA_FSR UA_FSR UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 BIF Break Interrupt Flag (Read Only) This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit. NOTE: This bit is read only, but can be cleared by writing '1' to it. 6 1 read-only FEF Framing Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit. NOTE: This bit is read only, but can be cleared by writing '1' to it. 5 1 read-only PEF Parity Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit. NOTE: This bit is read only, but can be cleared by writing '1' to it. 4 1 read-only RS_485_ADD_DETF RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNOTE: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only RX_EMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only RX_OVER Receiver FIFO Over (Read Only)\nThis bit indicates RX FIFO overrunning or not.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 15 bytes of UART0/UART1, this bit will be set. Otherwise is cleared by hardware. 15 1 read-only RX_POINTER RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one. 8 6 read-only TE_FLAG Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only TX_EMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). 22 1 read-only TX_FULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to16(UART0/UART1), otherwise is cleared by hardware. 23 1 read-only TX_OVER_IF TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it. 24 1 read-only TX_POINTER TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one. 16 6 read-only UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUN_SEL Function Select Enable\n 0 2 read-write 0 UART Function #00 1 Reserved #01 2 Enable IrDA Function #10 3 Enable RS-485 Function #11 UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 AUTO_CTS_EN CTS Auto Flow Control Enable\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 read-write 0 Disable CTS auto flow control #0 1 Enable CTS auto flow control #1 AUTO_RTS_EN RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal. 12 1 read-write 0 Disable RTS auto flow control #0 1 Enable RTS auto flow control #1 MODEM_IEN Modem Status Interrupt Enable \n 3 1 read-write 0 Mask off INT_MODEM #0 1 Enable INT_MODEM #1 RDA_IEN Receive Data Available Interrupt Enable.\n 0 1 read-write 0 Mask off INT_RDA #0 1 Enable INT_RDA #1 RLS_IEN Receive Line Status Interrupt Enable \n 2 1 read-write 0 Mask off INT_RLS #0 1 Enable INT_RLS #1 RTO_IEN RX Time Out Interrupt Enable\n 4 1 read-write 0 Mask off INT_TOUT #0 1 Enable INT_TOUT #1 THRE_IEN Transmit Holding Register Empty Interrupt Enable\n 1 1 read-write 0 Mask off INT_THRE #0 1 Enable INT_THRE #1 TIME_OUT_EN Time Out Counter Enable\n 11 1 read-write 0 Disable Time-out counter #0 1 Enable Time-out counter #1 WAKE_EN UART Wake-up Function Enable\n 6 1 read-write 0 Disable UART wake-up function #0 1 Enable UART wake-up function, when the chip is in power down mode, an external CTS change will wake-up chip from power down mode #1 UA_IRCR UA_IRCR UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 INV_RX INV_RX\n 6 1 read-write 0 No inversion #0 1 Inverse RX input signal #1 INV_TX INV_TX\n 5 1 read-write 0 No inversion #0 1 Inverse TX output signal #1 TX_SELECT TX_SELECT\n 1 1 read-write 0 Enable IrDA receiver #0 1 Enable IrDA transmitter #1 UA_ISR UA_ISR UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 BUF_ERR_IF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. 5 1 read-only BUF_ERR_INT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n 13 1 read-only 0 No buffer error interrupt is generated #0 1 The buffer error interrupt is generated #1 MODEM_IF MODEM Interrupt Flag (Read Only)\nNOTE: Write 1 to clear this bit to zero. 3 1 read-only MODEM_INT MODEM Status Interrupt Indicator To Interrupt Controller (Read Only). \nAn AND output with inputs of MODEM_IEN and MODEM_IF 11 1 read-only RDA_IF Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNOTE: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL). 0 1 read-only RDA_INT Receive Data Available Interrupt Indicator To Interrupt Controller (Read Only).\nAn AND output with inputs of RDA_IEN and RDA_IF 8 1 read-only RLS_IF Receive Line Interrupt Flag (Read Only). This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated. NOTE: Write 1 to clear this bit to zero. 2 1 read-only RLS_INT Receive Line Status Interrupt Indicator To Interrupt Controller (Read Only). \nAn AND output with inputs of RLS_IEN and RLS_IF 10 1 read-only THRE_IF Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNOTE: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only THRE_INT Transmit Holding Register Empty Interrupt Indicator To Interrupt Controller (Read Only).\nAn AND output with inputs of THRE_IEN and THRE_IF 9 1 read-only TOUT_IF Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNOTE: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 4 1 read-only TOUT_INT Time Out Interrupt Indicator To Interrupt Controller (Read Only)\nAn AND output with inputs of RTO_IEN and TOUT_IF 12 1 read-only UA_LCR UA_LCR UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write EPE Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of STOP bit Two STOP bit is generated when 6-, 7- and 8-bit word length is selected. 2 1 read-write 0 One STOP bit is generated in the transmitted data #0 1 One and a half STOP bit is generated in the transmitted data when 5-bit word length is selected #1 PBE Parity Bit Enable\n 3 1 read-write 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 SPE Stick Parity Enable\n 5 1 read-write 0 Stick parity disabled #0 1 If bit 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0. If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1 #1 WLS Word Length Select\n 0 2 read-write UA_MCR UA_MCR UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 LEV_RTS RTS Trigger Level\n 9 1 read-write 0 low level triggered #0 1 high level triggered #1 RTS RTS (Request-To-Send) Signal \n1: Drive RTS pin to logic 1 (If the LEV_RTS set to high level triggered). 1 1 read-write 0 Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered) #0 1 Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered) #1 RTS_ST RTS Pin State (Read Only)\nThis bit is the output pin status of RTS. 13 1 read-only UA_MSR UA_MSR UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTS_ST CTS Pin Status (Read Only)\nThis bit is the pin status of CTS. 4 1 read-only DCTSF Detect CTS State Change Flag (Read Only) \nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nNOTE: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only LEV_CTS CTS Trigger Level\nThis bit can change the CTS trigger level to send TX_FIFO data.\n 8 1 read-write 0 high level triggered #0 1 low level triggered #1 UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first). 0 8 read-only UA_THR UA_THR UART Transmit Holding Register UA_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first). 0 8 write-only UA_TOR UA_TOR UART Time Out Register 0x20 read-write n 0x0 0x0 DLY TX Delay time value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit. 8 8 read-write TOIC Time Out Interrupt Comparator\n 0 7 read-write WDT WDT Register Map WDT 0x0 0x0 0x4 registers n WTCR WTCR Watchdog Timer Control Register 0x0 -1 read-write n 0x0 0x0 DBGACK_WDT ICE debug mode acknowledge Disable (write-protected)\nWatchdog Timer counter will keep going no matter ICE debug mode acknowledged or not. 31 1 read-write 0 ICE debug mode acknowledgement effects Watchdog Timer counting #0 1 ICE debug mode acknowledgement disabled #1 WTE Watchdog Timer Enable (write protection bits) 7 1 read-write 0 Disable the Watchdog timer (This action will reset the internal counter) #0 1 Enable the Watchdog timer #1 WTIE Watchdog Timer Interrupt Enable (write protection bits) 6 1 read-write 0 Disable the Watchdog timer interrupt #0 1 Enable the Watchdog timer interrupt #1 WTIF Watchdog Timer Interrupt Flag\nIf the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. \nNote: This bit is cleared by writing 1 to this bit. 3 1 read-write 0 Watchdog timer interrupt did not occur #0 1 Watchdog timer interrupt occurs #1 WTIS Watchdog Timer Interval Select (write protection bits) 8 3 read-write WTR Clear Watchdog Timer (write-protection bit)\nSet this bit will clear the Watchdog timer.\nNote: This bit will auto clear after few clock cycle 0 1 read-write 0 Writing 0 to this bit has no effect #0 1 Reset the contents of the Watchdog timer #1 WTRE Watchdog Timer Reset Enable\nSetting this bit will enable the Watchdog timer reset function.\n 1 1 read-write 0 Disable Watchdog timer reset function #0 1 Enable Watchdog timer reset function #1 WTRF Watchdog Timer Reset Flag\nWhen the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If WTRE is disabled, then the Watchdog timer has no effect on this bit.\nNote: Write 1 to clear this bit to zero. 2 1 read-write 0 Watchdog timer reset did not occur #0 1 Watchdog timer reset occurs #1 WTWKE Watchdog Timer Wake-up Function Enable bit (write-protection bit)\nNote: Chip can wake-up by WDT only if WDT clock source select RC10K 4 1 read-write 0 Disable Watchdog timer wake-up chip function #0 1 Enable the Wake-up function that Watchdog timer timeout can wake-up chip from power down mode #1 WTWKF Watchdog Timer Wake-up Flag\nIf Watchdog timer causes chip wakes up from power down mode, this bit will be set to high. It must be cleared by software with a write 1 to this bit.\n 5 1 read-write 0 Watchdog timer does not cause chip wake-up #0 1 Chip wake-up from idle or power down mode by Watchdog timeout #1