nuvoTon
M05x_registers
2024.05.03
M05x_registers Microcontroller dummy device
8
32
ADC
Registers group
ADC
0x0
0x0
0x38
registers
n
ADCALR
A/D Calibration Register
0x34
read-write
n
0x0
0x0
CALDONE
Calibration is Done 1 = A/D converter self calibration is done. 0 = A/D converter has not been calibrated or calibration is in progress if CALEN bit is set. When 0 is written to CALEN bit, CALDONE bit is cleared by hardware immediately. It is a read only bit.
1
1
read-only
modify
CALEN
Self Calibration Enable 1 = Enable self calibration 0 = Disable self calibration Software can set this bit to 1 enables A/D converter to do self calibration function. It needs 127 ADC clocks to complete calibration. This bit must be kept at 1 after CALDONE asserted. Clearing this bit will disable self calibration function.
0
1
read-write
ADCHER
A/D Channel Enable Register
0x24
read-write
n
0x0
0x0
CHEN0
Analog Input Channel 0 Enable 1 = Enable 0 = Disable This channel is the default enabled channel if CHEN0~7 are set as 0s.
0
1
read-write
CHEN1
Analog Input Channel 1 Enable 1 = Enable 0 = Disable
1
1
read-write
CHEN2
Analog Input Channel 2 Enable 1 = Enable 0 = Disable
2
1
read-write
CHEN3
Analog Input Channel 3 Enable 1 = Enable 0 = Disable
3
1
read-write
CHEN4
Analog Input Channel 4 Enable 1 = Enable 0 = Disable
4
1
read-write
CHEN5
Analog Input Channel 5 Enable 1 = Enable 0 = Disable
5
1
read-write
CHEN6
Analog Input Channel 6 Enable 1 = Enable 0 = Disable
6
1
read-write
CHEN7
Analog Input Channel 7 Enable 1 = Enable 0 = Disable
7
1
read-write
PRESEL
Analog Input Channel 7 select 00: External analog input 01: Internal bandgap voltage 1x: Reserved
8
2
read-write
ADCMPR0
A/D Compare Register 0
0x28
read-write
n
0x0
0x0
CMPCH
Compare Channel Selection 000 = Channel 0 conversion result is selected to be compared. 001 = Channel 1 conversion result is selected to be compared. 010 = Channel 2 conversion result is selected to be compared. 011 = Channel 3 conversion result is selected to be compared. 100 = Channel 4 conversion result is selected to be compared. 101 = Channel 5 conversion result is selected to be compared. 110 = Channel 6 conversion result is selected to be compared. 111 = Channel 7 conversion result is selected to be compared.
3
3
read-write
CMPCOND
Compare Condition 1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD(ADCMPR0[27:16]), the internal match counter will increase one. 0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD(ADCMPR0[27:16]), the internal match counter will increase one. Note: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF0 bit will be set.
2
1
read-write
CMPD
Comparison Data The 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software.
16
12
read-write
CMPEN
Compare Enable 1 = Enable compare. 0 = Disable compare. Set this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register.
0
1
read-write
CMPIE
Compare Interrupt Enable 1 = Enable compare function interrupt. 0 = Disable compare function interrupt. If the compare function is enabled and the compare condition matches the settings of CMPCOND and CMPMATCNT, CMPF0 bit will be asserted. If CMPIE is set to 1, a compare interrupt request is generated.
1
1
read-write
CMPMATCNT
Compare Match Count When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF0 bit will be set.
8
4
read-write
ADCMPR1
A/D Compare Register 1
0x2C
read-write
n
0x0
0x0
CMPCH
Compare Channel Selection 000 = Channel 0 conversion result is selected to be compared. 001 = Channel 1 conversion result is selected to be compared. 010 = Channel 2 conversion result is selected to be compared. 011 = Channel 3 conversion result is selected to be compared. 100 = Channel 4 conversion result is selected to be compared. 101 = Channel 5 conversion result is selected to be compared. 110 = Channel 6 conversion result is selected to be compared. 111 = Channel 7 conversion result is selected to be compared.
3
3
read-write
CMPCOND
Compare Condition 1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD(ADCMPR1[27:16]), the internal match counter will increase one. 0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD(ADCMPR1[27:16]), the internal match counter will increase one. Note: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF1 bit will be set.
2
1
read-write
CMPD
Comparison Data The 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software.
16
12
read-write
CMPEN
Compare Enable 1 = Enable compare. 0 = Disable compare. Set this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register.
0
1
read-write
CMPIE
Compare Interrupt Enable 1 = Enable compare function interrupt. 0 = Disable compare function interrupt. If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF1 bit will be asserted. If CMPIE is set to 1, a compare interrupt request is generated.
1
1
read-write
CMPMATCNT
Compare Match Count When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF1 bit will be set.
8
4
read-write
ADCR
A/D Control Register
0x20
read-write
n
0x0
0x0
ADEN
A/D Converter Enable 1 = Enable 0 = Disable Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption.
0
1
read-write
ADIE
A/D Interrupt Enable 1 = Enable A/D interrupt function 0 = Disable A/D interrupt function A/D conversion end interrupt request is generated if ADIE bit is set to 1.
1
1
read-write
ADMD
A/D Converter Operation Mode 00 = Single conversion 01 = Burst conversion 10 = Single-cycle scan 11 = Continuous scan When changing the operation mode, software should disable ADST bit firstly. Note: In Burst Mode, the A/D result data always at Data Register 0.
2
2
read-write
ADST
A/D Conversion Start 1 = Conversion start. 0 = Conversion stopped and A/D converter enter idle state. ADST bit can be controlled by two sources: software write and external pin STADC. ADST is cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode on specified channels. In continuous scan mode, A/D conversion is continuously performed sequentially until this bit is cleared to 0 or chip reset.
11
1
read-write
DIFFEN
A/D Differential Input Mode Enable 1 = A/D is in differential analog input mode 0 = A/D is in single-end analog input mode Differential input voltage (Vdiff) = Vplus - Vminus The Vplus of differential input paired channel 0 is from ADC0 pin; Vminus is from ADC1 pin. The Vplus of differential input paired channel 1 is from ADC2 pin; Vminus is from ADC3 pin. The Vplus of differential input paired channel 2 is from ADC4 pin; Vminus is from ADC5 pin. The Vplus of differential input paired channel 3 is from ADC6 pin; Vminus is from ADC7 pin. In differential input mode, only one of the two corresponding channels needs to be enabled in ADCHER. The conversion result will be placed to the corresponding data register of the enabled channel. If both channels of a differential input paired channel are enabled, the ADC will convert it twice in scan mode. And then write the conversion result to the two corresponding data registers.
10
1
read-write
TRGCOND
External Trigger Condition These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state. 00 = Low level 01 = High level 10 = Falling edge 11 = Rising edge
6
2
read-write
TRGE
External Trigger Enable Enable or disable triggering of A/D conversion by external STADC pin. 1= Enable 0= Disable
8
1
read-write
TRGS
Hardware Trigger Source 00 = A/D conversion is started by external STADC pin. Others = Reserved Software should disable TRGE and ADST before change TRGS. In hardware trigger mode, the ADST bit is set by the external trigger from STADC.
4
2
read-write
ADDR0
A/D Data Register 0
0x0
read-only
n
0x0
0x0
OVERRUN
Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It will be cleared by hardware after ADDR register is read.
16
1
read-only
RSLT
A/D Conversion Result This field contains 12 bits conversion result.
0
12
read-only
VALID
Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
17
1
read-only
ADDR1
A/D Data Register 1
0x4
read-only
n
0x0
0x0
OVERRUN
Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It will be cleared by hardware after ADDR register is read.
16
1
read-only
RSLT
A/D Conversion Result This field contains 12 bits conversion result.
0
12
read-only
VALID
Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
17
1
read-only
ADDR2
A/D Data Register 2
0x8
read-only
n
0x0
0x0
OVERRUN
Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It will be cleared by hardware after ADDR register is read.
16
1
read-only
RSLT
A/D Conversion Result This field contains 12 bits conversion result.
0
12
read-only
VALID
Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
17
1
read-only
ADDR3
A/D Data Register 3
0xC
read-only
n
0x0
0x0
OVERRUN
Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It will be cleared by hardware after ADDR register is read.
16
1
read-only
RSLT
A/D Conversion Result This field contains 12 bits conversion result.
0
12
read-only
VALID
Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
17
1
read-only
ADDR4
A/D Data Register 4
0x10
read-only
n
0x0
0x0
OVERRUN
Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It will be cleared by hardware after ADDR register is read.
16
1
read-only
RSLT
A/D Conversion Result This field contains 12 bits conversion result.
0
12
read-only
VALID
Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
17
1
read-only
ADDR5
A/D Data Register 5
0x14
read-only
n
0x0
0x0
OVERRUN
Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It will be cleared by hardware after ADDR register is read.
16
1
read-only
RSLT
A/D Conversion Result This field contains 12 bits conversion result.
0
12
read-only
VALID
Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
17
1
read-only
ADDR6
A/D Data Register 6
0x18
read-only
n
0x0
0x0
OVERRUN
Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It will be cleared by hardware after ADDR register is read.
16
1
read-only
RSLT
A/D Conversion Result This field contains 12 bits conversion result.
0
12
read-only
VALID
Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
17
1
read-only
ADDR7
A/D Data Register 7
0x1C
read-only
n
0x0
0x0
OVERRUN
Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It will be cleared by hardware after ADDR register is read.
16
1
read-only
RSLT
A/D Conversion Result This field contains 12 bits conversion result.
0
12
read-only
VALID
Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
17
1
read-only
ADSR
A/D Status Register
0x30
read-write
n
0x0
0x0
ADF
A/D Conversion End Flag A status flag that indicates the end of A/D conversion. ADF is set to 1 at these two conditions: When A/D conversion ends in single mode When A/D conversion ends on all specified channels in scan mode. When more than 4 samples in FIFO in Burst mode. This bit can be cleared by writing 1 to itself.
0
1
read-write
oneToClear
BUSY
BUSY/IDLE 1 = A/D converter is busy at conversion. 0 = A/D converter is in idle state. This bit is mirror of as ADST bit in ADCR. It is read only.
3
1
read-only
CHANNEL
Current Conversion Channel This filed reflects current conversion channel when BUSY=1. When BUSY=0, it shows the next channel will be converted. It is read only.
4
3
read-only
CMPF0
Compare Flag When the selected channel A/D conversion result meets the setting conditions of ADCMPR0 then this bit will be set to 1. And it can be cleared by writing 1 to itself. 1 = Conversion result in ADDR meets ADCMPR0 setting 0 = Conversion result in ADDR does not meet ADCMPR0 setting
1
1
read-write
oneToClear
CMPF1
Compare Flag When the selected channel A/D conversion result meets the setting conditions of ADCMPR1 then this bit will be set to 1. And it can be cleared by writing 1 to itself. 1 = Conversion result in ADDR meets ADCMPR1 setting 0 = Conversion result in ADDR does not meet ADCMPR1 setting
2
1
read-write
oneToClear
OVERRUN
Over Run flag It is a mirror to OVERRUN bit in ADDRx When ADC is in Burst Mode, and the buffer is overrun, OVERRUN[7:0] will all set to 1.
16
8
read-only
modify
VALID
Data Valid flag It is a mirror of VALID bit in ADDRx When ADC is in Burst Mode, and there is at least one valid conversion result in buffer, VALID[7:0] will all set to 1.
8
8
read-only
modify
CLK
Registers group
CLK
0x0
0x0
0x28
registers
n
AHBCLK
AHB Devices Clock Enable Control Register
0x4
read-write
n
0x0
0x0
EBI_EN
EBI Controller Clock Enable Control. 1 = To enable the EBI Controller clock. 0 = To disable the EBI Controller clock.
3
1
read-write
ISP_EN
Flash ISP Controller Clock Enable Control. 1 = To enable the Flash ISP controller clock. 0 = To disable the Flash ISP controller clock.
2
1
read-write
APBCLK
APB Devices Clock Enable Control Register
0x8
read-write
n
0x0
0x0
ADC_EN
Analog-Digital-Converter (ADC) Clock Enable Control. 1 = Enable ADC clock 0 = Disable ADC clock
28
1
read-write
FDIV_EN
Clock Divider Clock Enable Control 0 = Disable FDIV Clock 1 = Enable FDIV Clock
6
1
read-write
I2C_EN
I2C Clock Enable Control. 0 = Disable I2C Clock 1 = Enable I2C Clock
8
1
read-write
PWM01_EN
PWM_01 Clock Enable Control. 1 = Enable PWM01 clock 0 = Disable PWM01 clock
20
1
read-write
PWM23_EN
PWM_23 Clock Enable Control. 1 = Enable PWM23 clock 0 = Disable PWM23 clock
21
1
read-write
PWM45_EN
PWM_45 Clock Enable Control. 1 = Enable PWM45 clock 0 = Disable PWM45 clock
22
1
read-write
PWM67_EN
PWM_67 Clock Enable Control. 1 = Enable PWM67 clock 0 = Disable PWM67 clock
23
1
read-write
SPI0_EN
SPI0 Clock Enable Control. 0 = Disable SPI0 Clock 1 = Enable SPI0 Clock
12
1
read-write
SPI1_EN
SPI1 Clock Enable Control. 0 = Disable SPI1 Clock 1 = Enable SPI1 Clock
13
1
read-write
TMR0_EN
Timer0 Clock Enable Control 0 = Disable Timer0 Clock 1 = Enable Timer0 Clock
2
1
read-write
TMR1_EN
Timer1 Clock Enable Control 0 = Disable Timer1 Clock 1 = Enable Timer1 Clock
3
1
read-write
TMR2_EN
Timer2 Clock Enable Control 0 = Disable Timer2 Clock 1 = Enable Timer2 Clock
4
1
read-write
TMR3_EN
Timer3 Clock Enable Control 0 = Disable Timer3 Clock 1 = Enable Timer3 Clock
5
1
read-write
UART0_EN
UART0 Clock Enable Control. 1 = Enable UART0 clock 0 = Disable UART0 clock
16
1
read-write
UART1_EN
UART1 Clock Enable Control. 1 = Enable UART1 clock 0 = Disable UART1 clock
17
1
read-write
WDT_EN
Watch Dog Timer Clock Enable. This bit is the protected bit, program this need a open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 0 = Disable Watchdog Timer Clock 1 = Enable Watchdog Timer Clock
0
1
read-write
CLKDIV
Clock Divider Number Register
0x18
read-write
n
0x0
0x0
ADC_N
ADC clock divide number from ADC clock source The ADC clock frequency = (ADC clock source frequency ) / (ADC_N + 1)
16
8
read-write
HCLK_N
HCLK clock divide number from HCLK clock source The HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1)
0
4
read-write
UART_N
UART clock divide number from UART clock source The UART clock frequency = (UART clock source frequency ) / (UART_N + 1)
8
4
read-write
CLKSEL0
Clock Source Select Control Register 0
0x10
read-write
n
0x0
0x0
HCLK_S
HCLK clock source select. Note: Before clock switch the related clock sources (pre-select and new-select) must be turn on The 3-bit default value is reloaded with the value of Config0.CFOSC[26:24] in user configuration register in Flash controller by any reset. Therefore the default value is either 000b or 111b. These bits are protected bit, program this need an open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 000 = clock source from external crystal clock (4 ~ 24MHz) 010 = clock source from PLL clock 011 = clock source from internal 10KHz oscillator clock 111 = clock source from internal 22.1184 MHz oscillator clock others = Reserved
0
3
read-write
STCLK_S
MCU Cortex_M0 SysTick clock source select. These bits are protected bit, program this need an open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 000 = Clock source from external crystal clock (4 ~ 24MHz) 010 = Clock source from external crystal clock (4 ~ 24MHz)/2 011 = clock source from HCLK/2 1xx = clock source from internal 22.1184 MHz oscillator clock/2
3
3
read-write
CLKSEL1
Clock Source Select Control Register 1
0x14
read-write
n
0x0
0x0
ADC_S
ADC clock source select. 00 = clock source from external crystal clock (4 ~ 24MHz). 01 = clock source from PLL clock 1x = clock source from internal 22.1184 MHz oscillator clock
2
2
read-write
PWM01_S
PWM0 and PWM1 clock source select. PWM0 and PWM1 uses the same Engine clock source, both of them with the same pre-scalar 00 = clock source from external crystal clock (4 ~ 24MHz) 10 = clock source from HCLK 11 = clock source from internal 22.1184 MHz oscillator clock
28
2
read-write
PWM23_S
PWM2 and PWM3 clock source select. PWM2 and PWM3 uses the same Engine clock source, both of them with the same pre-scalar 00 = clock source from external crystal clock (4 ~ 24MHz) 10 = clock source from HCLK 11 = clock source from internal 22.1184 MHz oscillator clock
30
2
read-write
TMR0_S
TIMER0 clock source select. 000 = clock source from external crystal clock (4 ~ 24MHz) 010 = clock source from HCLK 011 = clock source from external trigger 1xx = clock source from internal 22.1184 MHz oscillator clock
8
3
read-write
TMR1_S
TIMER1 clock source select. 000 = clock source from external crystal clock (4 ~ 24MHz) 010 = clock source from HCLK 011 = clock source from external trigger 1xx = clock source from internal 22.1184 MHz oscillator clock
12
3
read-write
TMR2_S
TIMER2 clock source select. 000 = clock source from external crystal clock (4 ~ 24MHz) 010 = clock source from HCLK 011 = clock source from external trigger 1xx = clock source from internal 22.1184 MHz oscillator clock
16
3
read-write
TMR3_S
TIMER3 clock source select. 000 = clock source from external crystal clock (4 ~ 24MHz) 010 = clock source from HCLK 011 = clock source from external trigger 1xx = clock source from internal 22.1184 MHz oscillator clock
20
3
read-write
UART_S
UART clock source select. 00 = clock source from external crystal clock (4 ~ 24MHz) 01 = clock source from PLL clock 1x = clock source from internal 22.1184 MHz oscillator clock
24
2
read-write
WDT_S
Watchdog Timer clock source select. These bits are protected bit, program this need a open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 00 = clock source from external crystal clock (4 ~ 24MHz). 10 = clock source from HCLK/2048 clock 11 = clock source from internal 10KHz oscillator clock
0
2
read-write
CLKSEL2
Clock Source Select Control Register 2
0x1C
read-write
n
0x0
0x0
FRQDIV_S
Clock Divider Clock Source Select 00 = clock source from external crystal clock (4 ~ 24MHz) 10 = clock source from HCLK 11 = clock source from internal 22.1184 MHz oscillator clock
2
2
read-write
PWM45_S
PWM4 and PWM5 clock source select. - PWM4 and PWM5 used the same Engine clock source, both of them with the same pre-scalar 00 = clock source from external crystal clock (4 ~ 24MHz) 10 = clock source from HCLK 11 = clock source from internal 22.1184 MHz oscillator clock
4
2
read-write
PWM67_S
PWM6 and PWM7 clock source select. - PWM6 and PWM7 used the same Engine clock source, both of them with the same pre-scalar 00 = clock source from external crystal clock (4 ~ 24MHz) 10 = clock source from HCLK 11 = clock source from internal 22.1184 MHz oscillator clock
6
2
read-write
CLKSTATUS
Clock status monitor Register
0xC
read-write
n
0x0
0x0
CLK_SW_FAIL
Clock switch fail flag 1 = Clock switch fail 0 = Clock switch success This bit will be set when target switch clock source is not stable. Write 1 to clear this bit to zero.
7
1
read-write
oneToClear
OSC10K_STB
OSC10K clock source stable flag 1 = OSC10K clock is stable 0 = OSC10K clock is not stable or not enable
3
1
read-only
OSC22M_STB
OSC22M clock source stable flag 1 = OSC22M clock is stable 0 = OSC22M clock is not stable or not enable
4
1
read-only
PLL_STB
PLL clock source stable flag 1 = PLL clock is stable 0 = PLL clock is not stable or not enable
2
1
read-only
XTL12M_STB
XTL12M clock source stable flag 1 = External Crystal clock is stable 0 = External Crystal clock is not stable or not enable
0
1
read-only
FRQDIV
Frequency Divider Control Register
0x24
read-write
n
0x0
0x0
DIVIDER_EN
Frequency Divider Enable Bit 0 = Disable Frequency Divider 1 = Enable Frequency Divider
4
1
read-write
FSEL
Divider Output Frequency Selection Bits The formula of output frequency is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the frequency of divider output clock, N is the 4-bit value of FSEL[3:0].
0
4
read-write
PLLCON
PLL Control Register
0x20
read-write
n
0x0
0x0
BP
PLL Bypass Control 0 = PLL is in normal mode (default) 1 = PLL clock output is same as clock input (XTALin)
17
1
read-write
FB_DV
PLL Feedback Divider Control Pins (PLL_F[8:0])
0
9
read-write
IN_DV
PLL Input Divider Control Pins (PLL_R[4:0])
9
5
read-write
OE
PLL OE (FOUT enable) pin Control 0 = PLL FOUT enable 1 = PLL FOUT is fixed low
18
1
read-write
OUT_DV
PLL Output Divider Control Pins (PLL_OD[1:0])
14
2
read-write
PD
Power Down Mode. If set the IDLE bit "1" in PWRCON register, the PLL will enter power down mode too 0 = PLL is in normal mode (default) 1 = PLL is in power-down mode
16
1
read-write
PLL_SRC
PLL Source Clock Select 1 = PLL source clock from 22.1184 MHz oscillator 0 = PLL source clock from external crystal clock (4 ~ 24 MHz)
19
1
read-write
PWRCON
System Power Down Control Register
0x0
read-write
n
0x0
0x0
OSC10K_EN
Internal 10KHz Oscillator Control 1 = 10KHz Oscillation enable 0 = 10KHz Oscillation disable
3
1
read-write
OSC22M_EN
Internal 22.1184 MHz Oscillator Control 1 = 22.1184 MHz Oscillation enable 0 = 22.1184 MHz Oscillation disable
2
1
read-write
PD_WAIT_CPU
This bit control the power down entry condition 1 = Chip entry power down mode when the both PWR_DOWN and CPU run WFI instruction. 0 = Chip entry power down mode when the PWR_DOWN bit is set to 1
8
1
read-write
PD_WU_DLY
Enable the wake up delay counter. When the chip wakes up from power down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip work at external crystal (4 ~ 24MHz), and 256 clock cycles when chip work at 22.1184 MHz oscillator. 1 = Enable the clock cycle delay 0 = Disable the clock cycle delay
4
1
read-write
PD_WU_INT_EN
Power down mode wake Up Interrupt Enable 0 = Disable 1 = Enable. The interrupt will occur when Power down mode (Deep Sleep Mode) wakeup.
5
1
read-write
PD_WU_STS
Chip power down wake up status flag Set by "power down wake up", it indicates that resume from power down mode The flag is set if the GPIO(P0~P4), UART wakeup Write 1 to clear the bit Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
6
1
read-write
oneToClear
PWR_DOWN_EN
System power down enable bit When set this bit "1", the chip power down mode is enabled and the chip power down active is depend on the PD_WAIT_CPU bit (a) if the PD_WAIT_CPU is "0" then the chip power down after the PWR_DOWN_EN bit set. (b) if the PD_WAIT_CPU is "1" then the chip keep active till the CPU sleep mode also active and then the chip power down When chip wake up from power down, this bit is auto cleared, user need to set this bit again for next power down. When in power down mode, external crystal (4~ 24MHz) and the 22.1184 MHz OSC will be disabled in this mode, but the 10 kHz OSC is not controlled by power down mode. When in power down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by power down mode, if the peripheral clock source is from 10 kHz oscillator. 1 = Chip enter the power down mode instant or wait CPU sleep command WFI 0 = Chip operate in normal mode or CPU in idle mode (sleep mode) because of WFI command
7
1
read-write
XTL12M_EN
External Crystal Oscillator Control The bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external crystal. The bit is auto set to "1" 1 = Crystal oscillation enable 0 = Crystal oscillation disable
0
1
read-write
EBI_CTL
Registers group
EBI_CTL
0x0
0x0
0x8
registers
n
EBICON
External Bus Interface General Control Register
0x0
read-write
n
0x0
0x0
ExtBW16
EBI data width 16 bit This bit defines if the data bus is 8-bit or 16-bit. 0 = EBI data width is 8 bit 1 = EBI data width is 16 bit
1
1
read-write
ExtEN
EBI Enable This bit is the functional enable bit for EBI. 0 = EBI function is disabled 1 = EBI function is enabled
0
1
read-write
ExttALE
Expand Time of ALE The ALE width (tALE) to latch the address can be controlled by ExttALE. tALE = (ExttALE + 1) * MCLK
16
3
read-write
MCLKDIV
External Output Clock Divider The frequency of EBI output clock is controlled by MCLKDIV. MCLKDIV Output clock (MCLK) 000 HCLK/1 001 HCLK/2 010 HCLK/4 011 HCLK/8 100 HCLK/16 101 HCKL/32 11X default Notice: Default value of output clock is HCLK/1
8
3
read-write
EXTIME
External Bus Interface 0 Timing Control Register
0x4
read-write
n
0x0
0x0
ExtIR2R
Idle State Cycle Between Read-Read When read action is finish and next action is going to read, idle state is inserted and nCS return to high if ExtIR2R is not zero. Idle state cycle = (ExtIR2R * MCLK)
24
4
read-write
ExtIW2X
Idle State Cycle After Write When write action is finish, idle state is inserted and nCS return to high if ExtIW2X is not zero. Idle state cycle = (ExtIW2X * MCLK)
12
4
read-write
ExttACC
EBI Data Accesss Time ExttACC define data access time (tACC). tACC = (ExttACC + 1) * MCLK
3
5
read-write
ExttAHD
EBI Data Access Hold Time ExttAHD define data access hold time (tAHD). tAHD = (ExttAHD + 1) * MCLK
8
3
read-write
FMC
Registers group
FMC
0x0
0x0
0x1C
registers
n
DFBADR
Data Flash Base Address
0x14
read-only
n
0x0
0x0
DFBA
Data Flash Base Address This register indicates data flash start address. It is a read only register. For 8/16/32/64kB flash memory device, the data flash size is 4kB and it start address is fixed at 0x01F000 by hardware internally.
0
32
read-only
FATCON
Flash Access Time Control Register
0x18
read-write
n
0x0
0x0
FATS
Flash Access Time Window Select These bits are used to decide flash sense amplifier active duration. FATS Access Time window (ns) 000 40 001 50 010 60 011 70 100 80 101 90 110 100 111 Reserved
1
3
read-write
FPSEN
Flash Power Save Enable If CPU clock is slower than 24 MHz, then s/w can enable flash power saving function. 1 = Enable flash power saving 0 = Disable flash power saving
0
1
read-write
L_SPEED
Flash Low Speed Mode Enable 1 = Flash access always no wait state (zero wait state) 0 = Insert wait state while Flash access discontinued address. Note: Set this bit only when HCLK <= 25MHz. If HCLK > 25MHz, CPU will fetch wrong code and cause fail result.
4
1
read-write
ISPADR
ISP Address Register
0x4
read-write
n
0x0
0x0
ISPADR
ISP Address NuMicro M051 series equips with a maximum 16kx32 embedded flash, it supports word program only. ISPARD[1:0] must be kept 2'b00 for ISP operation.
0
32
read-write
ISPCMD
ISP Command Register
0xC
read-write
n
0x0
0x0
FOEN_FCEN_FCTRL
ISP Command ISP command table is shown below: Operation Mode FOEN FCEN FCTRL[3:0] Read 0 0 0 0 0 0 Program 1 0 0 0 0 1 Page Erase 1 0 0 0 1 0
0
6
read-write
ISPCON
ISP Control Register
0x0
read-write
n
0x0
0x0
BS
Boot Select This bit is protected bit. Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as MCU booting status flag, which can be used to check where MCU booted from. This bit is initiated with the inversed value of CBS in Config0 after power-on reset; It keeps the same value at other reset. 1 = boot from LDROM 0 = boot from APROM
1
1
read-write
CFGUEN
Config Update Enable Writing this bit to 1 enables s/w to update Config value by ISP procedure regardless of program code is running in APROM or LDROM. 1 = Config update enable 0 = Config update disable
4
1
read-write
ET
Flash Erase Time ET[2] ET[1] ET[0] Erase Time (ms) 0 0 0 20 (default) 0 0 1 25 0 1 0 30 0 1 1 35 1 0 0 3 1 0 1 5 1 1 0 10 1 1 1 15
12
3
read-write
ISPEN
ISP Enable This bit is protected bit. ISP function enable bit. Set this bit to enable ISP function. 1 = Enable ISP function 0 = Disable ISP function
0
1
read-write
ISPFF
ISP Fail Flag This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself. (2) LDROM writes to itself. (3) Destination address is illegal, such as over an available range. Write 1 to clear.
6
1
read-write
oneToClear
LDUEN
LDROM Update Enable LDROM update enable bit. 1 = LDROM can be updated when the MCU runs in APROM. 0 = LDROM cannot be updated
5
1
read-write
PT
Flash Program Time PT[2] PT[1] PT[0] Program Time (us) 0 0 0 40 0 0 1 45 0 1 0 50 0 1 1 55 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35
8
3
read-write
SWRST
Software Reset Writing 1 to this bit to start software reset. It is cleared by hardware after reset is finished.
7
1
read-write
ISPDAT
ISP Data Register
0x8
read-write
n
0x0
0x0
ISPDAT
ISP Data Write data to this register before ISP program operation Read data from this register after ISP read operation
0
32
read-write
ISPTRG
ISP Trigger Control Register
0x10
read-write
n
0x0
0x0
ISPGO
ISP start trigger Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finish. 1 = ISP is on going 0 = ISP done
0
1
read-write
modify
GCR
Registers group
GCR
0x0
0x0
0x10
registers
n
0x100
0x4
registers
n
0x18
0x4
registers
n
0x24
0x4
registers
n
0x30
0x14
registers
n
BODCR
Brown Out Detector Control Register
0x18
read-write
n
0x0
0x0
BOD_EN
Brown Out Detector Enable (initiated & write-protected bit) The default value is set by flash controller user configuration register config0 bit[23] 1= Brown Out Detector function is enabled 0= Brown Out Detector function is disabled
0
1
read-write
BOD_INTF
Brown Out Detector Interrupt Flag 1= When Brown Out Detector detects the VDD is dropped through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to "1" and the brown out interrupt is requested if brown out interrupt is enabled. 0= Brown Out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting.
4
1
read-write
oneToClear
BOD_LPM
Brown Out Detector Low power Mode (write-protected bit) 1= Enable the BOD low power mode 0= BOD operate in normal mode (default) The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
5
1
read-write
BOD_OUT
The status for Brown Out Detector output state 1= Brown Out Detector status output is 1, the detected voltage is lower than BOD_VL setting. If the BOD_EN is "0"(disabled), this bit always response "0" 0= Brown Out Detector status output is 0, the detected voltage is higher than BOD_VL setting
6
1
read-only
BOD_RSTEN
Brown Out Reset Enable (initiated & write-protected bit) 1= Enable the Brown Out "RESET" function, when the Brown Out Detector function is enable and the detected voltage is lower than the threshold then assert a signal to reset the chip The default value is set by flash controller user configuration register config0 bit[20] 0= Enable the Brown Out "INTERRUPT" function, when the Brown Out Detector function is enable and the detected voltage is lower than the threshold then assert a signal to interrupt the MCU Cortex-M0 When the BOD_EN is enabled and the interrupt is assert, the interrupt will keep till to the BOD_EN set to "0". The interrupt for CPU can be blocked by disable the NVIC in CPU for BOD interrupt or disable the interrupt source by disable the BOD_EN and then re-enable the BOD_EN function if the BOD function is required
3
1
read-write
BOD_VL
Brown Out Detector Threshold Voltage Selection (initiated & write-protected bit) The default value is set by flash controller user configuration register config0 bit[22:21] BOV_VL[1] BOV_VL[0] Brown out voltage 1 1 4.5V 1 0 3.8V 0 1 2.7V 0 0 2.2V
1
2
read-write
LVR_EN
Low Voltage Reset Enable (write-protected bit) The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default. 1= Enabled Low Voltage Reset function - After enable the bit, the LVR function will active with 100uS delay for LVR output stable.(default). 0= Disabled Low Voltage Reset function
7
1
read-write
IPRSTC1
IP Reset Control Resister1
0x8
read-write
n
0x0
0x0
CHIP_RST
CHIP one shot reset. Set this bit will reset the CHIP, including CPU kernel and all peripherals, and this bit will automatically return to "0" after the 2 clock cycles. The CHIP_RST is same as the POR reset , all the chip module is reset and the chip setting from flash are also reload This bit is the protected bit, program this need an open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 0= Normal 1= Reset CHIP
0
1
read-write
modify
CPU_RST
CPU kernel one shot reset. Set this bit will reset the Cortex-M0 CPU kernel and Flash memory controller (FMC). This bit will automatically return to "0" after the 2 clock cycles This bit is the protected bit, program this need an open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 0= Normal 1= Reset CPU
1
1
read-write
modify
EBI_RST
EBI Controller Reset Set these bit "1" will generate a reset signal to the EBI. User need to set this bit to "0" to release from the reset state This bit is the protected bit, program this need an open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 0= Normal operation 1= EBI IP reset
3
1
read-write
IPRSTC2
IP Reset Control Resister 2
0xC
read-write
n
0x0
0x0
ADC_RST
ADC Controller Reset 0= ADC controller normal operation 1= ADC controller reset
28
1
read-write
GPIO_RST
GPIO (P0~P4) controller Reset 0= GPIO controller normal operation 1= GPIO controller reset
1
1
read-write
I2C_RST
I2C controller Reset 0= I2C controller normal operation 1= I2C controller reset
8
1
read-write
PWM03_RST
PWM0~3 controller Reset 0= PWM0~3 controller normal operation 1= PWM0~3 controller reset
20
1
read-write
PWM47_RST
PWM4~7 controller Reset 0= PWM4~7 controller normal operation 1= PWM4~7 controller reset
21
1
read-write
SPI0_RST
SPI0 controller Reset 0= SPI0 controller normal operation 1= SPI0 controller reset
12
1
read-write
SPI1_RST
SPI1 controller Reset 0= SPI1 controller normal operation 1= SPI1 controller reset
13
1
read-write
TMR0_RST
Timer0 controller Reset 0= Timer0 controller normal operation 1= Timer0 controller reset
2
1
read-write
TMR1_RST
Timer1 controller Reset 0= Timer1 controller normal operation 1= Timer1 controller reset
3
1
read-write
TMR2_RST
Timer2 controller Reset 0= Timer2 controller normal operation 1= Timer2 controller reset
4
1
read-write
TMR3_RST
Timer3 controller Reset 0= Timer3 controller normal operation 1= Timer3 controller reset
5
1
read-write
UART0_RST
UART0 controller Reset 0= UART0 controller Normal operation 1= UART0 controller reset
16
1
read-write
UART1_RST
UART1 controller Reset 0 = UART1 controller normal operation 1 = UART1 controller reset
17
1
read-write
P0_MFP
P0 multiple function and input type control register
0x30
read-write
n
0x0
0x0
P0_ALT0
P0.0 alternate function Selection The pin function of P0.0 is depend on P0_MFP[0] and P0_ALT[0]. P0_ALT[0] P0_MFP[0] P0.0function 0 0 P0.0 0 1 AD0(EBI) 1 0 CTS1(UART1) 1 1 Reserved
8
1
read-write
P0_ALT1
P0.1 alternate function Selection The pin function of P0.1 is depend on P0_MFP[1] and P0_ALT[1]. P0_ALT[1] P0_MFP[1] P0.1function 0 0 P0.1 0 1 AD1(EBI) 1 0 RTS1(UART1) 1 1 Reserved
9
1
read-write
P0_ALT2
P0.2 alternate function Selection The pin function of P0.2 is depend on P0_MFP[2] and P0_ALT[2]. P0_ALT[2] P0_MFP[2] P0.2function 0 0 P0.2 0 1 AD2(EBI) 1 0 CTS0(UART0) 1 1 Reserved
10
1
read-write
P0_ALT3
P0.3 alternate function Selection The pin function of P0.3 is depend on P0_MFP[3] and P0_ALT[3]. P0_ALT[3] P0_MFP[3] P0.3function 0 0 P0.3 0 1 AD3(EBI) 1 0 RTS0(UART0) 1 1 Reserved
11
1
read-write
P0_ALT4
P0.4 alternate function Selection The pin function of P0.4 is depend on P0_MFP[4] and P0_ALT[4]. P0_ALT[4] P0_MFP[4] P0.4function 0 0 P0.4 0 1 AD4(EBI) 1 0 SPISS1(SPI1) 1 1 Reserved
12
1
read-write
P0_ALT5
P0.5 alternate function Selection The pin function of P0.5 is depend on P0_MFP[5] and P0_ALT[5]. P0_ALT[5] P0_MFP[5] P0.5 function 0 0 P0.5 0 1 AD5(EBI) 1 0 MOSI_1(SPI1) 1 1 Reserved
13
1
read-write
P0_ALT6
P0.6 alternate function Selection The pin function of P0.6 is depend on P0_MFP[6] and P0_ALT[6]. P0_ALT[6] P0_MFP[6] P0.6 function 0 0 P0.6 0 1 AD6(EBI) 1 0 MISO_1(SPI1) 1 1 Reserved
14
1
read-write
P0_ALT7
P0.7 alternate function Selection The pin function of P0.7 is depend on P0_MFP[7] and P0_ALT[7]. P0_ALT[7] P0_MFP[7] P0.7 function 0 0 P0.7 0 1 AD7(EBI) 1 0 SPICLK1(SPI1) 1 1 Reserved
15
1
read-write
P0_MFP
P0 multiple function Selection The pin function of P0 is depending on P0_MFP and P0_ALT. Refer to P0_ALT descriptions in detail.
0
8
read-write
P0_TYPEn
P0[7:0] input Schmitt Trigger function Enable 1= P0[7:0] I/O input Schmitt Trigger function enable 0= P0[7:0] I/O input Schmitt Trigger function disable
16
8
read-write
P1_MFP
P1 multiple function and input type control register
0x34
read-write
n
0x0
0x0
P1_ALT0
P1.0 alternate function Selection The pin function of P1.0 is depend on P1_MFP[0] and P1_ALT[0]. P1_ALT[0] P1_MFP[0] P1.0function 0 0 P1.0 0 1 AIN0(ADC) 1 0 T2(Timer2) 1 1 Reserved
8
1
read-write
P1_ALT1
P1.1 alternate function Selection The pin function of P1.1 is depend on P1_MFP[1] and P1_ALT[1]. P1_ALT[1] P1_MFP[1] P1.1function 0 0 P1.1 0 1 AIN1(ADC) 1 0 T3(Timer3) 1 1 Reserved
9
1
read-write
P1_ALT2
P1.2 alternate function Selection The pin function of P1.2 is depend on P1_MFP[2] and P1_ALT[2]. P1_ALT[2] P1_MFP[2] P1.2function 0 0 P1.2 0 1 AIN2(ADC) 1 0 RXD1(UART1) 1 1 Reserved
10
1
read-write
P1_ALT3
P1.3 alternate function Selection The pin function of P1.3 is depend on P1_MFP[3] and P1_ALT[3]. P1_ALT[3] P1_MFP[3] P1.3function 0 0 P1.3 0 1 AIN3(ADC) 1 0 TXD1(UART1) 1 1 Reserved
11
1
read-write
P1_ALT4
P1.4 alternate function Selection The pin function of P1.4 is depend on P1_MFP[4] and P1_ALT[4]. P1_ALT[4] P1_MFP[4] P1.4function 0 0 P1.4 0 1 AIN4(ADC) 1 0 SPISS0(SPI0) 1 1 Reserved
12
1
read-write
P1_ALT5
P1.5 alternate function Selection The pin function of P1.5 is depend on P1_MFP[5] and P1_ALT[5]. P1_ALT[5] P1_MFP[5] P1.5 function 0 0 P1.5 0 1 AIN5(ADC) 1 0 MOSI_0(SPI0) 1 1 Reserved
13
1
read-write
P1_ALT6
P1.6 alternate function Selection The pin function of P1.6 is depend on P1_MFP[6] and P1_ALT[6]. P1_ALT[6] P1_MFP[6] P1.6 function 0 0 P1.6 0 1 AIN6(ADC) 1 0 MISO_0(SPI0) 1 1 Reserved
14
1
read-write
P1_ALT7
P1.7 alternate function Selection The pin function of P1.7 is depend on P1_MFP[7] and P1_ALT[7]. P1_ALT[7] P1_MFP[7] P1.7 function 0 0 P1.7 0 1 AIN7(ADC) 1 0 SPICLK0(SPI0) 1 1 Reserved
15
1
read-write
P1_MFP
P1 multiple function Selection The pin function of P1 is depending on P1_MFP and P1_ALT. Refer to P1_ALT descriptions in detail.
0
8
read-write
P1_TYPEn
P1[7:0] input Schmitt Trigger function Enable 1= P1[7:0] I/O input Schmitt Trigger function enable 0= P1[7:0] I/O input Schmitt Trigger function disable
16
8
read-write
P2_MFP
P2 multiple function and input type control register
0x38
read-write
n
0x0
0x0
P2_ALT0
P2.0 alternate function Selection The pin function of P2.0 is depend on P2_MFP[0] and P2_ALT[0]. P2_ALT[0] P2_MFP[0] P2.0function 0 0 P2.0 0 1 AD8(EBI) 1 0 PWM0(PWM generator 0) 1 1 Reserved
8
1
read-write
P2_ALT1
P2.1 alternate function Selection The pin function of P2.1 is depend on P2_MFP[1] and P2_ALT[1]. P2_ALT[1] P2_MFP[1] P2.1function 0 0 P2.1 0 1 AD9(EBI) 1 0 PWM1(PWM generator 0) 1 1 Reserved
9
1
read-write
P2_ALT2
P2.2 alternate function Selection The pin function of P2.2 is depend on P2_MFP[2] and P2_ALT[2]. P2_ALT[2] P2_MFP[2] P2.2function 0 0 P2.2 0 1 AD10(EBI) 1 0 PWM2(PWM generator 2) 1 1 Reserved
10
1
read-write
P2_ALT3
P2.3 alternate function Selection The pin function of P2.3 is depend on P2_MFP[3] and P2_ALT[3]. P2_ALT[3] P2_MFP[3] P2.3function 0 0 P2.3 0 1 AD11(EBI) 1 0 PWM3(PWM generator 2) 1 1 Reserved
11
1
read-write
P2_ALT4
P2.4 alternate function Selection The pin function of P2.4 is depend on P2_MFP[4] and P2_ALT[4]. P2_ALT[4] P2_MFP[4] P0.4function 0 0 P0.4 0 1 AD12(EBI) 1 0 PWM4(PWM generator 4) 1 1 Reserved
12
1
read-write
P2_ALT5
P2.5 alternate function Selection The pin function of P2.5 is depend on P2_MFP[5] and P2_ALT[5]. P2_ALT[5] P2_MFP[5] P2.5 function 0 0 P2.5 0 1 AD13(EBI) 1 0 PWM5(PWM generator 4) 1 1 Reserved
13
1
read-write
P2_ALT6
P2.6 alternate function Selection The pin function of P2.6 is depend on P2_MFP[6] and P2_ALT[6]. P2_ALT[6] P2_MFP[6] P2.6 function 0 0 P2.6 0 1 AD14(EBI) 1 0 PWM6(PWM generator 6) 1 1 Reserved
14
1
read-write
P2_ALT7
P2.7 alternate function Selection The pin function of P2.7 is depend on P2_MFP[7] and P2_ALT[7]. P2_ALT[7] P2_MFP[7] P2.7 function 0 0 P2.7 0 1 AD15(EBI) 1 0 PWM7(PWM generator 6) 1 1 Reserved
15
1
read-write
P2_MFP
P2 multiple function Selection The pin function of P2 is depending on P2_MFP and P2_ALT. Refer to P2_ALT descriptions in detail.
0
8
read-write
P2_TYPEn
P2[7:0] input Schmitt Trigger function Enable 1= P2[7:0] I/O input Schmitt Trigger function enable 0= P2[7:0] I/O input Schmitt Trigger function disable
16
8
read-write
P3_MFP
P3 multiple function and input type control register
0x3C
read-write
n
0x0
0x0
P3_ALT0
P3.0 alternate function Selection The pin function of P3.0 is depend on P3_MFP[0] and P3_ALT[0]. P3_ALT[0] P3_MFP[0] P3.0function 0 0 P3.0 0 1 RXD(UART0) 1 x Reserved
8
1
read-write
P3_ALT1
P3.1 alternate function Selection The pin function of P3.1 is depend on P3_MFP[1] and P3_ALT[1]. P3_ALT[1] P3_MFP[1] P3.1function 0 0 P3.1 0 1 TXD(UART0) 1 x Reserved
9
1
read-write
P3_ALT2
P3.2 alternate function Selection The pin function of P3.2 is depend on P3_MFP[2] and P3_ALT[2]. P3_ALT[2] P3_MFP[2] P3.2function 0 0 P3.2 0 1 /INT0 1 1 Reserved
10
1
read-write
P3_ALT3
P3.3 alternate function Selection The pin function of P3.3 is depend on P3_MFP[3] and P3_ALT[3]. P3_ALT[3] P3_MFP[3] P3.3function 0 0 P3.3 0 1 /INT1 1 0 MCLK(EBI) 1 x Reserved
11
1
read-write
P3_ALT4
P3.4 alternate function Selection The pin function of P3.4 is depend on P3_MFP[4] and P3_ALT[4]. P3_ALT[4] P3_MFP[4] P3.4function 0 0 P3.4 0 1 T0(Timer0) 1 0 SDA(I2C) 1 1 Reserved
12
1
read-write
P3_ALT5
P3.5 alternate function Selection The pin function of P3.5 is depend on P3_MFP[5] and P3_ALT[5]. P3_ALT[5] P3_MFP[5] P3.5 function 0 0 P3.5 0 1 T1(Timer1) 1 0 SCL(I2C) 1 1 Reserved
13
1
read-write
P3_ALT6
P3.6 alternate function Selection The pin function of P3.6 is depend on P3_MFP[6] and P3_ALT[6]. P3_ALT[6] P3_MFP[6] P3.6 function 0 0 P3.6 0 1 WR(EBI) 1 0 CKO(Clock Driver output) 1 1 Reserved
14
1
read-write
P3_ALT7
P3.7 alternate function Selection The pin function of P3.7 is depend on P3_MFP[7] and P3_ALT[7]. P3_ALT[7] P3_MFP[7] P3.7 function 0 0 P3.7 0 1 RD(EBI) 1 x Reserved
15
1
read-write
P3_MFP
P3 multiple function Selection The pin function of P3 is depending on P3_MFP and P3_ALT. Refer to P3_ALT descriptions in detail.
0
8
read-write
P3_TYPEn
P3[7:0] input Schmitt Trigger function Enable 1= P3[7:0] I/O input Schmitt Trigger function enable 0= P3[7:0] I/O input Schmitt Trigger function disable
16
8
read-write
P4_MFP
P4 input type control register
0x40
read-write
n
0x0
0x0
P4_ALT0
P4.0 alternate function Selection The pin function of P4.0 is depend on P4_MFP[0] and P4_ALT[0]. P4_ALT[0] P4_MFP[0] P4.0function 0 0 P4.0 0 1 PWM0(PWM generator 0) 1 x Reserved
8
1
read-write
P4_ALT1
P4.1 alternate function Selection The pin function of P4.1 is depend on P4_MFP[1] and P4_ALT[1]. P4_ALT[1] P4_MFP[1] P4.1function 0 0 P4.1 0 1 PWM1(PWM generator 0) 1 x Reserved
9
1
read-write
P4_ALT2
P4.2 alternate function Selection The pin function of P4.2 is depend on P4_MFP[2] and P4_ALT[2]. P4_ALT[2] P4_MFP[2] P4.2function 0 0 P4.2 0 1 PWM2(PWM generator 2) 1 x Reserved
10
1
read-write
P4_ALT3
P4.3 alternate function Selection The pin function of P4.3 is depend on P4_MFP[3] and P4_ALT[3]. P4_ALT[3] P4_MFP[3] P4.3function 0 0 P4.3 0 1 PWM3(PWM generator 2) 1 x Reserved
11
1
read-write
P4_ALT4
P4.4 alternate function Selection The pin function of P4.4 is depend on P4_MFP[4] and P4_ALT[4]. P4_ALT[4] P4_MFP[4] P4.4function 0 0 P4.4 0 1 /CS(EBI) 1 x Reserved
12
1
read-write
P4_ALT5
P4.5 alternate function Selection The pin function of P4.5 is depend on P4_MFP[5] and P4_ALT[5]. P4_ALT[5] P4_MFP[5] P4.5 function 0 0 P4.5 0 1 ALE(EBI) 1 x Reserved
13
1
read-write
P4_ALT6
P4.6 alternate function Selection The pin function of P4.6 is depend on P4_MFP[6] and P4_ALT[6]. P4_ALT[6] P4_MFP[6] P4.6 function 0 0 P4.6 0 1 ICE_CLK(ICE) 1 x Reserved
14
1
read-write
P4_ALT7
P4.7 alternate function Selection The pin function of P4.7 is depend on P4_MFP[7] and P4_ALT[7]. P4_ALT[7] P4_MFP[7] P4.7 function 0 0 P4.7 0 1 ICE_DAT(ICE) 1 x Reserved
15
1
read-write
P4_MFP
P4 multiple function Selection The pin function of P4 is depending on P4_MFP and P4_ALT. Refer to P4_ALT descriptions in detail.
0
8
read-write
P4_TYPEn
P4[7:0] input Schmitt Trigger function Enable 1= P4[7:0] I/O input Schmitt Trigger function enable 0= P4[7:0] I/O input Schmitt Trigger function disable
16
8
read-write
PDID
Part Device Identification number Register
0x0
read-only
n
0x0
0x0
PDID
This register reflects device part number code. S/W can read this register to identify which device is used.
0
32
read-only
PORCR
Power-On-Reset Controller Register
0x24
read-write
n
0x0
0x0
POR_DIS_CODE
The register is used for the Power-On-Reset enable control. When power on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. If set the POR_DIS_CODE equal to 0x5AA5, the POR reset function will be disabled and the POR function will re-active till the power voltage is lower to set the POR_DIS_CODE to another value or reset by chip other reset function. Include: PIN reset, Watch dog, LVR reset BOD reset, ICE reset command and the software-chip reset function This register is the protected register, program this need an open lock sequence, write "59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100
0
16
read-write
REGWRPROT
Register Lock Key address
0x100
read-write
n
0x0
0x0
REGPROTDIS
Register Write-Protected Disable index (Read only) 1 = Protection is disabled for writing protected registers 0 = Protection is enabled for writing protected registers. Any write to the protected register is ignored. The Write-Protected registers list are below table: Registers Address Note IPRSTC1 0x5000_0008 None BODCR 0x5000_0018 None PORCR 0x5000_001C None PWRCON 0x5000_0200 bit[6] is not protected for power wake-up interrupt clear APBCLK bit[0] 0x5000_0208 bit[0] is watch dog clock enable CLKSEL0 0x5000_0210 HCLK and CPU STCLK clock source select CLK_SEL1 bit[1:0] 0x5000_0214 Watch dog clock source select ISPCON 0x5000_C000 Flash ISP Control register WTCR 0x4000_4000 None FATCON 0x5000_C018 None
0
1
read-only
REGWRPROT
Register Write-Protected Code (Write Only) Some write-protected registers have to be disabled the protected function by writing the sequence value "59h", "16h", "88h" to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protected registers can be normal write.
0
8
write-only
RSTSRC
System Reset Source Register
0x4
read-write
n
0x0
0x0
RSTS_BOD
The RSTS_BOD flag is set by the "reset signal" from the Brown-Out-Detected module to indicate the previous reset source. 1= The Brown-Out-Detected module had issued the reset signal to reset the system. 0= No reset from BOD This bit is cleared by writing 1 to itself.
4
1
read-write
oneToClear
RSTS_CPU
The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) with a "1" to rest Cortex-M0 CPU kernel and Flash memory controller(FMC). 1= The Cortex-M0 CPU kernel and FMC are reset by software set CPU_RST to 1. 0= No reset from CPU This bit is cleared by writing 1 to itself.
7
1
read-write
oneToClear
RSTS_LVR
The RSTS_LVR flag is set by the "reset signal" from the Low-Voltage-Reset module to indicate the previous reset source. 1= The LVR module had issued the reset signal to reset the system. 0= No reset from LVR This bit is cleared by writing 1 to itself.
3
1
read-write
oneToClear
RSTS_MCU
The RSTS_MCU flag is set by the "reset signal" from the MCU Cortex_M0 kernel to indicate the previous reset source. 1= The MCU Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel. 0= No reset from MCU This bit is cleared by writing 1 to itself.
5
1
read-write
oneToClear
RSTS_POR
The RSTS_POR flag is set by the "reset signal" which is from the Power-On Reset (POR) module or bit CHIP_RST (IPRSTC1[0]) is set, to indicate the previous reset source. 1= The Power-On-Reset(POR) or CHIP_RST=1 had issued the reset signal to reset the system. 0= No reset from POR This bit is cleared by writing 1 to itself.
0
1
read-write
oneToClear
RSTS_RESET
The RSTS_RESET flag is set by the "reset signal" from the /RESET pin to indicate the previous reset source. 1= The Pin /RESET had issued the reset signal to reset the system. 0= No reset from Pin /RESET This bit is cleared by writing 1 to itself.
1
1
read-write
oneToClear
RSTS_WDT
The RSTS_WDT flag is set by the "reset signal" from the Watch Dog Timer to indicate the previous reset source. 1= The Watch Dog Timer had issued the reset signal to reset the system. 0= No reset from Watch-Dog This bit is cleared by writing 1 to itself.
2
1
read-write
oneToClear
GP0
Registers group
GPIO
0x0
0x0
0x24
registers
n
DBEN
De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
P0 Input Signal De-bounce Enable DBEN[0] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[0] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[0] de-bounce function is disabled 1 = The bit[0] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
0
1
read-write
DBEN1
P0 Input Signal De-bounce Enable DBEN[1] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[1] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[1] de-bounce function is disabled 1 = The bit[1] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
1
1
read-write
DBEN2
P0 Input Signal De-bounce Enable DBEN[2] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[2] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[2] de-bounce function is disabled 1 = The bit[2] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
2
1
read-write
DBEN3
P0 Input Signal De-bounce Enable DBEN[3] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[3] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[3] de-bounce function is disabled 1 = The bit[3] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
3
1
read-write
DBEN4
P0 Input Signal De-bounce Enable DBEN[4] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[4] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[4] de-bounce function is disabled 1 = The bit[4] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
4
1
read-write
DBEN5
P0 Input Signal De-bounce Enable DBEN[5] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[5] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[5] de-bounce function is disabled 1 = The bit[5] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
5
1
read-write
DBEN6
P0 Input Signal De-bounce Enable DBEN[6] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[6] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[6] de-bounce function is disabled 1 = The bit[6] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
6
1
read-write
DBEN7
P0 Input Signal De-bounce Enable DBEN[7] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[7] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[7] de-bounce function is disabled 1 = The bit[7] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
7
1
read-write
DMASK
Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[0]. When set the DMASK bit[0] to "1", the corresponding DOUT0 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[0] bit can be updated 1 = The corresponding P0_DOUT[0] bit is protected
0
1
read-write
DMASK1
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[1]. When set the DMASK bit[1] to "1", the corresponding DOUT1 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[1] bit can be updated 1 = The corresponding P0_DOUT[1] bit is protected
1
1
read-write
DMASK2
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[2]. When set the DMASK bit[2] to "1", the corresponding DOUT2 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[2] bit can be updated 1 = The corresponding P0_DOUT[2] bit is protected
2
1
read-write
DMASK3
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[3]. When set the DMASK bit[3] to "1", the corresponding DOUT3 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[3] bit can be updated 1 = The corresponding P0_DOUT[3] bit is protected
3
1
read-write
DMASK4
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[4]. When set the DMASK bit[4] to "1", the corresponding DOUT4 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[4] bit can be updated 1 = The corresponding P0_DOUT[4] bit is protected
4
1
read-write
DMASK5
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[6]. When set the DMASK bit[6] to "1", the corresponding DOUT6 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[6] bit can be updated 1 = The corresponding P0_DOUT[6] bit is protected
5
1
read-write
DMASK6
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[6]. When set the DMASK bit[6] to "1", the corresponding DOUT6 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[6] bit can be updated 1 = The corresponding P0_DOUT[6] bit is protected
6
1
read-write
DMASK7
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[7]. When set the DMASK bit[7] to "1", the corresponding DOUT7 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[7] bit can be updated 1 = The corresponding P0_DOUT[7] bit is protected
7
1
read-write
DOUT
Data Output Value
0x8
read-write
n
0x0
0x0
DOUT0
P0 Pin[0] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[0] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[0] will drive Low if the corresponding output mode enabling bit is set.
0
1
read-write
DOUT1
P0 Pin[1] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[1] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[1] will drive Low if the corresponding output mode enabling bit is set.
1
1
read-write
DOUT2
P0 Pin[2] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[2] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[2] will drive Low if the corresponding output mode enabling bit is set.
2
1
read-write
DOUT3
P0 Pin[3] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[3] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[3] will drive Low if the corresponding output mode enabling bit is set.
3
1
read-write
DOUT4
P0 Pin[4] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[4] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[4] will drive Low if the corresponding output mode enabling bit is set.
4
1
read-write
DOUT5
P0 Pin[5] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[5] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[5] will drive Low if the corresponding output mode enabling bit is set.
5
1
read-write
DOUT6
P0 Pin[6] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[6] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[6] will drive Low if the corresponding output mode enabling bit is set.
6
1
read-write
DOUT7
P0 Pin[7] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[7] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[7] will drive Low if the corresponding output mode enabling bit is set.
7
1
read-write
IEN
Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[0] used to enable the interrupt for each of the corresponding input P0[0]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[0] bit "1": If the interrupt is level mode trigger, the input P0[0] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[0] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[0] state low-level or high-to-low change interrupt 0 = Disable the P0[0] state low-level or high-to-low change interrupt
0
1
read-write
IF_EN1
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[1] used to enable the interrupt for each of the corresponding input P0[1]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[1] bit "1": If the interrupt is level mode trigger, the input P0[1] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[1] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[1] state low-level or high-to-low change interrupt 0 = Disable the P0[1] state low-level or high-to-low change interrupt
1
1
read-write
IF_EN2
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[2] used to enable the interrupt for each of the corresponding input P0[2]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[2] bit "1": If the interrupt is level mode trigger, the input P0[2] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[2] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[2] state low-level or high-to-low change interrupt 0 = Disable the P0[2] state low-level or high-to-low change interrupt
2
1
read-write
IF_EN3
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[3] used to enable the interrupt for each of the corresponding input P0[3]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[3] bit "1": If the interrupt is level mode trigger, the input P0[3] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[3] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[3] state low-level or high-to-low change interrupt 0 = Disable the P0[3] state low-level or high-to-low change interrupt
3
1
read-write
IF_EN4
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[4] used to enable the interrupt for each of the corresponding input P0[4]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[4] bit "1": If the interrupt is level mode trigger, the input P0[4] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[4] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[4] state low-level or high-to-low change interrupt 0 = Disable the P0[4] state low-level or high-to-low change interrupt
4
1
read-write
IF_EN5
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[5] used to enable the interrupt for each of the corresponding input P0[5]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[5] bit "1": If the interrupt is level mode trigger, the input P0[5] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[5] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[5] state low-level or high-to-low change interrupt 0 = Disable the P0[5] state low-level or high-to-low change interrupt
5
1
read-write
IF_EN6
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[6] used to enable the interrupt for each of the corresponding input P0[6]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[6] bit "1": If the interrupt is level mode trigger, the input P0[6] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[6] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[6] state low-level or high-to-low change interrupt 0 = Disable the P0[6] state low-level or high-to-low change interrupt
6
1
read-write
IF_EN7
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[7] used to enable the interrupt for each of the corresponding input P0[7]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[7] bit "1": If the interrupt is level mode trigger, the input P0[7] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[7] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[7] state low-level or high-to-low change interrupt 0 = Disable the P0[7] state low-level or high-to-low change interrupt
7
1
read-write
IR_EN0
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[0] used to enable the interrupt for each of the corresponding input P0[0]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[0] bit "1": If the interrupt is level mode trigger, the input P0[0] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[0] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[0] level-high or low-to-high interrupt 0 = Disable the P0[0] level-high or low-to-high interrupt
16
1
read-write
IR_EN1
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[1] used to enable the interrupt for each of the corresponding input P0[1]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[1] bit "1": If the interrupt is level mode trigger, the input P0[1] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[1] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[1] level-high or low-to-high interrupt 0 = Disable the P0[1] level-high or low-to-high interrupt
17
1
read-write
IR_EN2
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[2] used to enable the interrupt for each of the corresponding input P0[2]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[2] bit "1": If the interrupt is level mode trigger, the input P0[2] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[2] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[2] level-high or low-to-high interrupt 0 = Disable the P0[2] level-high or low-to-high interrupt
18
1
read-write
IR_EN3
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[3] used to enable the interrupt for each of the corresponding input P0[3]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[3] bit "1": If the interrupt is level mode trigger, the input P0[3] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[3] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[3] level-high or low-to-high interrupt 0 = Disable the P0[3] level-high or low-to-high interrupt
19
1
read-write
IR_EN4
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[4] used to enable the interrupt for each of the corresponding input P0[4]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[4] bit "1": If the interrupt is level mode trigger, the input P0[4] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[4] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[4] level-high or low-to-high interrupt 0 = Disable the P0[4] level-high or low-to-high interrupt
20
1
read-write
IR_EN5
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[5] used to enable the interrupt for each of the corresponding input P0[5]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[5] bit "1": If the interrupt is level mode trigger, the input P0[5] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[5] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[5] level-high or low-to-high interrupt 0 = Disable the P0[5] level-high or low-to-high interrupt
21
1
read-write
IR_EN6
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[6] used to enable the interrupt for each of the corresponding input P0[6]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[6] bit "1": If the interrupt is level mode trigger, the input P0[6] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[6] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[6] level-high or low-to-high interrupt 0 = Disable the P0[6] level-high or low-to-high interrupt
22
1
read-write
IR_EN7
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[7] used to enable the interrupt for each of the corresponding input P0[7]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[7] bit "1": If the interrupt is level mode trigger, the input P0[7] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[7] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[7] level-high or low-to-high interrupt 0 = Disable the P0[7] level-high or low-to-high interrupt
23
1
read-write
IMD
Interrupt Mode Control
0x18
read-write
n
0x0
0x0
IMD0
Port 0 Interrupt Mode Control IMD[0] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
0
1
read-write
IMD1
Port 0 Interrupt Mode Control IMD[1] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
1
1
read-write
IMD2
Port 0 Interrupt Mode Control IMD[2] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
2
1
read-write
IMD3
Port 0 Interrupt Mode Control IMD[3] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
3
1
read-write
IMD4
Port 0 Interrupt Mode Control IMD[4] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
4
1
read-write
IMD5
Port 0 Interrupt Mode Control IMD[5] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
5
1
read-write
IMD6
Port 0 Interrupt Mode Control IMD[6] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
6
1
read-write
IMD7
Port 0 Interrupt Mode Control IMD[7] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
7
1
read-write
ISRC
Interrupt Trigger Source
0x20
read-write
n
0x0
0x0
ISRC0
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[0] generate an interrupt 0 = No interrupt at P0[0] Write: 1 = Clear the correspond pending interrupt 0 = No action
0
1
read-write
oneToClear
ISRC1
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[1] generate an interrupt 0 = No interrupt at P0[1] Write: 1 = Clear the correspond pending interrupt 0 = No action
1
1
read-write
oneToClear
ISRC2
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[2] generate an interrupt 0 = No interrupt at P0[2] Write: 1 = Clear the correspond pending interrupt 0 = No action
2
1
read-write
oneToClear
ISRC3
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[3] generate an interrupt 0 = No interrupt at P0[3] Write: 1 = Clear the correspond pending interrupt 0 = No action
3
1
read-write
oneToClear
ISRC4
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[4] generate an interrupt 0 = No interrupt at P0[4] Write: 1 = Clear the correspond pending interrupt 0 = No action
4
1
read-write
oneToClear
ISRC5
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[5] generate an interrupt 0 = No interrupt at P0[5] Write: 1 = Clear the correspond pending interrupt 0 = No action
5
1
read-write
oneToClear
ISRC6
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[6] generate an interrupt 0 = No interrupt at P0[6] Write: 1 = Clear the correspond pending interrupt 0 = No action
6
1
read-write
oneToClear
ISRC7
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[7] generate an interrupt 0 = No interrupt at P0[7] Write: 1 = Clear the correspond pending interrupt 0 = No action
7
1
read-write
oneToClear
OFFD
Bit OFF Digital Enable
0x4
read-write
n
0x0
0x0
OFFD
OFFD: P0 Pin OFF digital input path Enable 1 = Disable IO digital input path (digital input tied to low) 0 = Enable IO digital input path
16
8
read-write
PIN
Pin Value
0x10
read-only
n
0x0
0x0
PIN0
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[0].
0
1
read-only
PIN1
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[1].
1
1
read-only
PIN2
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[2].
2
1
read-only
PIN3
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[3].
3
1
read-only
PIN4
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[4].
4
1
read-only
PIN5
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[5].
5
1
read-only
PIN6
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[6].
6
1
read-only
PIN7
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[7].
7
1
read-only
PMD
Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
P0 I/O Pin[0] Mode Control Determine each I/O type of P0 pins 00 = P0[0] pin is in INPUT mode. 01 = P0[0] pin is in OUTPUT mode. 10 = P0[0] pin is in Open-Drain mode. 11 = P0[0] pin is in Quasi-bidirectional mode.
0
2
read-write
PMD1
P0 I/O Pin[1] Mode Control Determine each I/O type of P0 pins 00 = P0[1] pin is in INPUT mode. 01 = P0[1] pin is in OUTPUT mode. 10 = P0[1] pin is in Open-Drain mode. 11 = P0[1] pin is in Quasi-bidirectional mode.
2
2
read-write
PMD2
P0 I/O Pin[2] Mode Control Determine each I/O type of P0 pins 00 = P0[2] pin is in INPUT mode. 01 = P0[2] pin is in OUTPUT mode. 10 = P0[2] pin is in Open-Drain mode. 11 = P0[2] pin is in Quasi-bidirectional mode.
4
2
read-write
PMD3
P0 I/O Pin[3] Mode Control Determine each I/O type of P0 pins 00 = P0[3] pin is in INPUT mode. 01 = P0[3] pin is in OUTPUT mode. 10 = P0[3] pin is in Open-Drain mode. 11 = P0[3] pin is in Quasi-bidirectional mode.
6
2
read-write
PMD4
P0 I/O Pin[4] Mode Control Determine each I/O type of P0 pins 00 = P0[4] pin is in INPUT mode. 01 = P0[4] pin is in OUTPUT mode. 10 = P0[4] pin is in Open-Drain mode. 11 = P0[4] pin is in Quasi-bidirectional mode.
8
2
read-write
PMD5
P0 I/O Pin[5] Mode Control Determine each I/O type of P0 pins 00 = P0[5] pin is in INPUT mode. 01 = P0[5] pin is in OUTPUT mode. 10 = P0[5] pin is in Open-Drain mode. 11 = P0[5] pin is in Quasi-bidirectional mode.
10
2
read-write
PMD6
P0 I/O Pin[6] Mode Control Determine each I/O type of P0 pins 00 = P0[6] pin is in INPUT mode. 01 = P0[6] pin is in OUTPUT mode. 10 = P0[6] pin is in Open-Drain mode. 11 = P0[6] pin is in Quasi-bidirectional mode.
12
2
read-write
PMD7
P0 I/O Pin[7] Mode Control Determine each I/O type of P0 pins 00 = P0[7] pin is in INPUT mode. 01 = P0[7] pin is in OUTPUT mode. 10 = P0[7] pin is in Open-Drain mode. 11 = P0[7] pin is in Quasi-bidirectional mode.
14
2
read-write
GP0_BITS
Registers group
GPIO_BITS
0x0
0x200
0x20
registers
n
Px0_DOUT
Px.0 Data Output Value
0x200
read-write
n
0x0
0x0
DOUT
P0.0 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px1_DOUT
Px.1 Data Output Value
0x204
read-write
n
0x0
0x0
DOUT
P0.1 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px2_DOUT
Px.2 Data Output Value
0x208
read-write
n
0x0
0x0
DOUT
P0.2 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px3_DOUT
Px.3 Data Output Value
0x20C
read-write
n
0x0
0x0
DOUT
P0.3 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px4_DOUT
Px.4 Data Output Value
0x210
read-write
n
0x0
0x0
DOUT
P0.4 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px5_DOUT
Px.5 Data Output Value
0x214
read-write
n
0x0
0x0
DOUT
P0.5 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px6_DOUT
Px.6 Data Output Value
0x218
read-write
n
0x0
0x0
DOUT
P0.6 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px7_DOUT
Px.7 Data Output Value
0x21C
read-write
n
0x0
0x0
DOUT
P0.7 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
GP1
Registers group
GPIO
0x0
0x0
0x24
registers
n
DBEN
De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
P0 Input Signal De-bounce Enable DBEN[0] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[0] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[0] de-bounce function is disabled 1 = The bit[0] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
0
1
read-write
DBEN1
P0 Input Signal De-bounce Enable DBEN[1] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[1] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[1] de-bounce function is disabled 1 = The bit[1] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
1
1
read-write
DBEN2
P0 Input Signal De-bounce Enable DBEN[2] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[2] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[2] de-bounce function is disabled 1 = The bit[2] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
2
1
read-write
DBEN3
P0 Input Signal De-bounce Enable DBEN[3] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[3] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[3] de-bounce function is disabled 1 = The bit[3] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
3
1
read-write
DBEN4
P0 Input Signal De-bounce Enable DBEN[4] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[4] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[4] de-bounce function is disabled 1 = The bit[4] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
4
1
read-write
DBEN5
P0 Input Signal De-bounce Enable DBEN[5] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[5] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[5] de-bounce function is disabled 1 = The bit[5] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
5
1
read-write
DBEN6
P0 Input Signal De-bounce Enable DBEN[6] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[6] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[6] de-bounce function is disabled 1 = The bit[6] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
6
1
read-write
DBEN7
P0 Input Signal De-bounce Enable DBEN[7] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[7] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[7] de-bounce function is disabled 1 = The bit[7] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
7
1
read-write
DMASK
Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[0]. When set the DMASK bit[0] to "1", the corresponding DOUT0 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[0] bit can be updated 1 = The corresponding P0_DOUT[0] bit is protected
0
1
read-write
DMASK1
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[1]. When set the DMASK bit[1] to "1", the corresponding DOUT1 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[1] bit can be updated 1 = The corresponding P0_DOUT[1] bit is protected
1
1
read-write
DMASK2
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[2]. When set the DMASK bit[2] to "1", the corresponding DOUT2 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[2] bit can be updated 1 = The corresponding P0_DOUT[2] bit is protected
2
1
read-write
DMASK3
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[3]. When set the DMASK bit[3] to "1", the corresponding DOUT3 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[3] bit can be updated 1 = The corresponding P0_DOUT[3] bit is protected
3
1
read-write
DMASK4
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[4]. When set the DMASK bit[4] to "1", the corresponding DOUT4 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[4] bit can be updated 1 = The corresponding P0_DOUT[4] bit is protected
4
1
read-write
DMASK5
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[6]. When set the DMASK bit[6] to "1", the corresponding DOUT6 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[6] bit can be updated 1 = The corresponding P0_DOUT[6] bit is protected
5
1
read-write
DMASK6
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[6]. When set the DMASK bit[6] to "1", the corresponding DOUT6 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[6] bit can be updated 1 = The corresponding P0_DOUT[6] bit is protected
6
1
read-write
DMASK7
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[7]. When set the DMASK bit[7] to "1", the corresponding DOUT7 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[7] bit can be updated 1 = The corresponding P0_DOUT[7] bit is protected
7
1
read-write
DOUT
Data Output Value
0x8
read-write
n
0x0
0x0
DOUT0
P0 Pin[0] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[0] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[0] will drive Low if the corresponding output mode enabling bit is set.
0
1
read-write
DOUT1
P0 Pin[1] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[1] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[1] will drive Low if the corresponding output mode enabling bit is set.
1
1
read-write
DOUT2
P0 Pin[2] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[2] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[2] will drive Low if the corresponding output mode enabling bit is set.
2
1
read-write
DOUT3
P0 Pin[3] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[3] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[3] will drive Low if the corresponding output mode enabling bit is set.
3
1
read-write
DOUT4
P0 Pin[4] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[4] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[4] will drive Low if the corresponding output mode enabling bit is set.
4
1
read-write
DOUT5
P0 Pin[5] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[5] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[5] will drive Low if the corresponding output mode enabling bit is set.
5
1
read-write
DOUT6
P0 Pin[6] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[6] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[6] will drive Low if the corresponding output mode enabling bit is set.
6
1
read-write
DOUT7
P0 Pin[7] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[7] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[7] will drive Low if the corresponding output mode enabling bit is set.
7
1
read-write
IEN
Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[0] used to enable the interrupt for each of the corresponding input P0[0]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[0] bit "1": If the interrupt is level mode trigger, the input P0[0] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[0] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[0] state low-level or high-to-low change interrupt 0 = Disable the P0[0] state low-level or high-to-low change interrupt
0
1
read-write
IF_EN1
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[1] used to enable the interrupt for each of the corresponding input P0[1]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[1] bit "1": If the interrupt is level mode trigger, the input P0[1] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[1] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[1] state low-level or high-to-low change interrupt 0 = Disable the P0[1] state low-level or high-to-low change interrupt
1
1
read-write
IF_EN2
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[2] used to enable the interrupt for each of the corresponding input P0[2]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[2] bit "1": If the interrupt is level mode trigger, the input P0[2] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[2] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[2] state low-level or high-to-low change interrupt 0 = Disable the P0[2] state low-level or high-to-low change interrupt
2
1
read-write
IF_EN3
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[3] used to enable the interrupt for each of the corresponding input P0[3]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[3] bit "1": If the interrupt is level mode trigger, the input P0[3] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[3] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[3] state low-level or high-to-low change interrupt 0 = Disable the P0[3] state low-level or high-to-low change interrupt
3
1
read-write
IF_EN4
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[4] used to enable the interrupt for each of the corresponding input P0[4]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[4] bit "1": If the interrupt is level mode trigger, the input P0[4] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[4] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[4] state low-level or high-to-low change interrupt 0 = Disable the P0[4] state low-level or high-to-low change interrupt
4
1
read-write
IF_EN5
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[5] used to enable the interrupt for each of the corresponding input P0[5]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[5] bit "1": If the interrupt is level mode trigger, the input P0[5] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[5] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[5] state low-level or high-to-low change interrupt 0 = Disable the P0[5] state low-level or high-to-low change interrupt
5
1
read-write
IF_EN6
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[6] used to enable the interrupt for each of the corresponding input P0[6]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[6] bit "1": If the interrupt is level mode trigger, the input P0[6] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[6] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[6] state low-level or high-to-low change interrupt 0 = Disable the P0[6] state low-level or high-to-low change interrupt
6
1
read-write
IF_EN7
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[7] used to enable the interrupt for each of the corresponding input P0[7]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[7] bit "1": If the interrupt is level mode trigger, the input P0[7] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[7] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[7] state low-level or high-to-low change interrupt 0 = Disable the P0[7] state low-level or high-to-low change interrupt
7
1
read-write
IR_EN0
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[0] used to enable the interrupt for each of the corresponding input P0[0]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[0] bit "1": If the interrupt is level mode trigger, the input P0[0] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[0] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[0] level-high or low-to-high interrupt 0 = Disable the P0[0] level-high or low-to-high interrupt
16
1
read-write
IR_EN1
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[1] used to enable the interrupt for each of the corresponding input P0[1]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[1] bit "1": If the interrupt is level mode trigger, the input P0[1] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[1] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[1] level-high or low-to-high interrupt 0 = Disable the P0[1] level-high or low-to-high interrupt
17
1
read-write
IR_EN2
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[2] used to enable the interrupt for each of the corresponding input P0[2]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[2] bit "1": If the interrupt is level mode trigger, the input P0[2] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[2] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[2] level-high or low-to-high interrupt 0 = Disable the P0[2] level-high or low-to-high interrupt
18
1
read-write
IR_EN3
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[3] used to enable the interrupt for each of the corresponding input P0[3]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[3] bit "1": If the interrupt is level mode trigger, the input P0[3] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[3] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[3] level-high or low-to-high interrupt 0 = Disable the P0[3] level-high or low-to-high interrupt
19
1
read-write
IR_EN4
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[4] used to enable the interrupt for each of the corresponding input P0[4]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[4] bit "1": If the interrupt is level mode trigger, the input P0[4] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[4] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[4] level-high or low-to-high interrupt 0 = Disable the P0[4] level-high or low-to-high interrupt
20
1
read-write
IR_EN5
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[5] used to enable the interrupt for each of the corresponding input P0[5]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[5] bit "1": If the interrupt is level mode trigger, the input P0[5] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[5] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[5] level-high or low-to-high interrupt 0 = Disable the P0[5] level-high or low-to-high interrupt
21
1
read-write
IR_EN6
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[6] used to enable the interrupt for each of the corresponding input P0[6]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[6] bit "1": If the interrupt is level mode trigger, the input P0[6] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[6] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[6] level-high or low-to-high interrupt 0 = Disable the P0[6] level-high or low-to-high interrupt
22
1
read-write
IR_EN7
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[7] used to enable the interrupt for each of the corresponding input P0[7]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[7] bit "1": If the interrupt is level mode trigger, the input P0[7] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[7] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[7] level-high or low-to-high interrupt 0 = Disable the P0[7] level-high or low-to-high interrupt
23
1
read-write
IMD
Interrupt Mode Control
0x18
read-write
n
0x0
0x0
IMD0
Port 0 Interrupt Mode Control IMD[0] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
0
1
read-write
IMD1
Port 0 Interrupt Mode Control IMD[1] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
1
1
read-write
IMD2
Port 0 Interrupt Mode Control IMD[2] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
2
1
read-write
IMD3
Port 0 Interrupt Mode Control IMD[3] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
3
1
read-write
IMD4
Port 0 Interrupt Mode Control IMD[4] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
4
1
read-write
IMD5
Port 0 Interrupt Mode Control IMD[5] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
5
1
read-write
IMD6
Port 0 Interrupt Mode Control IMD[6] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
6
1
read-write
IMD7
Port 0 Interrupt Mode Control IMD[7] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
7
1
read-write
ISRC
Interrupt Trigger Source
0x20
read-write
n
0x0
0x0
ISRC0
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[0] generate an interrupt 0 = No interrupt at P0[0] Write: 1 = Clear the correspond pending interrupt 0 = No action
0
1
read-write
oneToClear
ISRC1
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[1] generate an interrupt 0 = No interrupt at P0[1] Write: 1 = Clear the correspond pending interrupt 0 = No action
1
1
read-write
oneToClear
ISRC2
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[2] generate an interrupt 0 = No interrupt at P0[2] Write: 1 = Clear the correspond pending interrupt 0 = No action
2
1
read-write
oneToClear
ISRC3
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[3] generate an interrupt 0 = No interrupt at P0[3] Write: 1 = Clear the correspond pending interrupt 0 = No action
3
1
read-write
oneToClear
ISRC4
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[4] generate an interrupt 0 = No interrupt at P0[4] Write: 1 = Clear the correspond pending interrupt 0 = No action
4
1
read-write
oneToClear
ISRC5
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[5] generate an interrupt 0 = No interrupt at P0[5] Write: 1 = Clear the correspond pending interrupt 0 = No action
5
1
read-write
oneToClear
ISRC6
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[6] generate an interrupt 0 = No interrupt at P0[6] Write: 1 = Clear the correspond pending interrupt 0 = No action
6
1
read-write
oneToClear
ISRC7
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[7] generate an interrupt 0 = No interrupt at P0[7] Write: 1 = Clear the correspond pending interrupt 0 = No action
7
1
read-write
oneToClear
OFFD
Bit OFF Digital Enable
0x4
read-write
n
0x0
0x0
OFFD
OFFD: P0 Pin OFF digital input path Enable 1 = Disable IO digital input path (digital input tied to low) 0 = Enable IO digital input path
16
8
read-write
PIN
Pin Value
0x10
read-only
n
0x0
0x0
PIN0
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[0].
0
1
read-only
PIN1
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[1].
1
1
read-only
PIN2
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[2].
2
1
read-only
PIN3
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[3].
3
1
read-only
PIN4
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[4].
4
1
read-only
PIN5
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[5].
5
1
read-only
PIN6
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[6].
6
1
read-only
PIN7
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[7].
7
1
read-only
PMD
Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
P0 I/O Pin[0] Mode Control Determine each I/O type of P0 pins 00 = P0[0] pin is in INPUT mode. 01 = P0[0] pin is in OUTPUT mode. 10 = P0[0] pin is in Open-Drain mode. 11 = P0[0] pin is in Quasi-bidirectional mode.
0
2
read-write
PMD1
P0 I/O Pin[1] Mode Control Determine each I/O type of P0 pins 00 = P0[1] pin is in INPUT mode. 01 = P0[1] pin is in OUTPUT mode. 10 = P0[1] pin is in Open-Drain mode. 11 = P0[1] pin is in Quasi-bidirectional mode.
2
2
read-write
PMD2
P0 I/O Pin[2] Mode Control Determine each I/O type of P0 pins 00 = P0[2] pin is in INPUT mode. 01 = P0[2] pin is in OUTPUT mode. 10 = P0[2] pin is in Open-Drain mode. 11 = P0[2] pin is in Quasi-bidirectional mode.
4
2
read-write
PMD3
P0 I/O Pin[3] Mode Control Determine each I/O type of P0 pins 00 = P0[3] pin is in INPUT mode. 01 = P0[3] pin is in OUTPUT mode. 10 = P0[3] pin is in Open-Drain mode. 11 = P0[3] pin is in Quasi-bidirectional mode.
6
2
read-write
PMD4
P0 I/O Pin[4] Mode Control Determine each I/O type of P0 pins 00 = P0[4] pin is in INPUT mode. 01 = P0[4] pin is in OUTPUT mode. 10 = P0[4] pin is in Open-Drain mode. 11 = P0[4] pin is in Quasi-bidirectional mode.
8
2
read-write
PMD5
P0 I/O Pin[5] Mode Control Determine each I/O type of P0 pins 00 = P0[5] pin is in INPUT mode. 01 = P0[5] pin is in OUTPUT mode. 10 = P0[5] pin is in Open-Drain mode. 11 = P0[5] pin is in Quasi-bidirectional mode.
10
2
read-write
PMD6
P0 I/O Pin[6] Mode Control Determine each I/O type of P0 pins 00 = P0[6] pin is in INPUT mode. 01 = P0[6] pin is in OUTPUT mode. 10 = P0[6] pin is in Open-Drain mode. 11 = P0[6] pin is in Quasi-bidirectional mode.
12
2
read-write
PMD7
P0 I/O Pin[7] Mode Control Determine each I/O type of P0 pins 00 = P0[7] pin is in INPUT mode. 01 = P0[7] pin is in OUTPUT mode. 10 = P0[7] pin is in Open-Drain mode. 11 = P0[7] pin is in Quasi-bidirectional mode.
14
2
read-write
GP1_BITS
Registers group
GPIO_BITS
0x0
0x200
0x20
registers
n
Px0_DOUT
Px.0 Data Output Value
0x200
read-write
n
0x0
0x0
DOUT
P0.0 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px1_DOUT
Px.1 Data Output Value
0x204
read-write
n
0x0
0x0
DOUT
P0.1 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px2_DOUT
Px.2 Data Output Value
0x208
read-write
n
0x0
0x0
DOUT
P0.2 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px3_DOUT
Px.3 Data Output Value
0x20C
read-write
n
0x0
0x0
DOUT
P0.3 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px4_DOUT
Px.4 Data Output Value
0x210
read-write
n
0x0
0x0
DOUT
P0.4 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px5_DOUT
Px.5 Data Output Value
0x214
read-write
n
0x0
0x0
DOUT
P0.5 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px6_DOUT
Px.6 Data Output Value
0x218
read-write
n
0x0
0x0
DOUT
P0.6 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px7_DOUT
Px.7 Data Output Value
0x21C
read-write
n
0x0
0x0
DOUT
P0.7 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
GP2
Registers group
GPIO
0x0
0x0
0x24
registers
n
DBEN
De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
P0 Input Signal De-bounce Enable DBEN[0] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[0] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[0] de-bounce function is disabled 1 = The bit[0] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
0
1
read-write
DBEN1
P0 Input Signal De-bounce Enable DBEN[1] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[1] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[1] de-bounce function is disabled 1 = The bit[1] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
1
1
read-write
DBEN2
P0 Input Signal De-bounce Enable DBEN[2] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[2] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[2] de-bounce function is disabled 1 = The bit[2] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
2
1
read-write
DBEN3
P0 Input Signal De-bounce Enable DBEN[3] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[3] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[3] de-bounce function is disabled 1 = The bit[3] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
3
1
read-write
DBEN4
P0 Input Signal De-bounce Enable DBEN[4] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[4] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[4] de-bounce function is disabled 1 = The bit[4] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
4
1
read-write
DBEN5
P0 Input Signal De-bounce Enable DBEN[5] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[5] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[5] de-bounce function is disabled 1 = The bit[5] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
5
1
read-write
DBEN6
P0 Input Signal De-bounce Enable DBEN[6] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[6] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[6] de-bounce function is disabled 1 = The bit[6] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
6
1
read-write
DBEN7
P0 Input Signal De-bounce Enable DBEN[7] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[7] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[7] de-bounce function is disabled 1 = The bit[7] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
7
1
read-write
DMASK
Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[0]. When set the DMASK bit[0] to "1", the corresponding DOUT0 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[0] bit can be updated 1 = The corresponding P0_DOUT[0] bit is protected
0
1
read-write
DMASK1
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[1]. When set the DMASK bit[1] to "1", the corresponding DOUT1 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[1] bit can be updated 1 = The corresponding P0_DOUT[1] bit is protected
1
1
read-write
DMASK2
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[2]. When set the DMASK bit[2] to "1", the corresponding DOUT2 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[2] bit can be updated 1 = The corresponding P0_DOUT[2] bit is protected
2
1
read-write
DMASK3
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[3]. When set the DMASK bit[3] to "1", the corresponding DOUT3 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[3] bit can be updated 1 = The corresponding P0_DOUT[3] bit is protected
3
1
read-write
DMASK4
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[4]. When set the DMASK bit[4] to "1", the corresponding DOUT4 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[4] bit can be updated 1 = The corresponding P0_DOUT[4] bit is protected
4
1
read-write
DMASK5
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[6]. When set the DMASK bit[6] to "1", the corresponding DOUT6 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[6] bit can be updated 1 = The corresponding P0_DOUT[6] bit is protected
5
1
read-write
DMASK6
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[6]. When set the DMASK bit[6] to "1", the corresponding DOUT6 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[6] bit can be updated 1 = The corresponding P0_DOUT[6] bit is protected
6
1
read-write
DMASK7
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[7]. When set the DMASK bit[7] to "1", the corresponding DOUT7 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[7] bit can be updated 1 = The corresponding P0_DOUT[7] bit is protected
7
1
read-write
DOUT
Data Output Value
0x8
read-write
n
0x0
0x0
DOUT0
P0 Pin[0] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[0] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[0] will drive Low if the corresponding output mode enabling bit is set.
0
1
read-write
DOUT1
P0 Pin[1] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[1] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[1] will drive Low if the corresponding output mode enabling bit is set.
1
1
read-write
DOUT2
P0 Pin[2] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[2] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[2] will drive Low if the corresponding output mode enabling bit is set.
2
1
read-write
DOUT3
P0 Pin[3] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[3] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[3] will drive Low if the corresponding output mode enabling bit is set.
3
1
read-write
DOUT4
P0 Pin[4] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[4] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[4] will drive Low if the corresponding output mode enabling bit is set.
4
1
read-write
DOUT5
P0 Pin[5] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[5] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[5] will drive Low if the corresponding output mode enabling bit is set.
5
1
read-write
DOUT6
P0 Pin[6] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[6] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[6] will drive Low if the corresponding output mode enabling bit is set.
6
1
read-write
DOUT7
P0 Pin[7] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[7] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[7] will drive Low if the corresponding output mode enabling bit is set.
7
1
read-write
IEN
Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[0] used to enable the interrupt for each of the corresponding input P0[0]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[0] bit "1": If the interrupt is level mode trigger, the input P0[0] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[0] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[0] state low-level or high-to-low change interrupt 0 = Disable the P0[0] state low-level or high-to-low change interrupt
0
1
read-write
IF_EN1
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[1] used to enable the interrupt for each of the corresponding input P0[1]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[1] bit "1": If the interrupt is level mode trigger, the input P0[1] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[1] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[1] state low-level or high-to-low change interrupt 0 = Disable the P0[1] state low-level or high-to-low change interrupt
1
1
read-write
IF_EN2
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[2] used to enable the interrupt for each of the corresponding input P0[2]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[2] bit "1": If the interrupt is level mode trigger, the input P0[2] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[2] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[2] state low-level or high-to-low change interrupt 0 = Disable the P0[2] state low-level or high-to-low change interrupt
2
1
read-write
IF_EN3
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[3] used to enable the interrupt for each of the corresponding input P0[3]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[3] bit "1": If the interrupt is level mode trigger, the input P0[3] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[3] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[3] state low-level or high-to-low change interrupt 0 = Disable the P0[3] state low-level or high-to-low change interrupt
3
1
read-write
IF_EN4
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[4] used to enable the interrupt for each of the corresponding input P0[4]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[4] bit "1": If the interrupt is level mode trigger, the input P0[4] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[4] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[4] state low-level or high-to-low change interrupt 0 = Disable the P0[4] state low-level or high-to-low change interrupt
4
1
read-write
IF_EN5
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[5] used to enable the interrupt for each of the corresponding input P0[5]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[5] bit "1": If the interrupt is level mode trigger, the input P0[5] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[5] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[5] state low-level or high-to-low change interrupt 0 = Disable the P0[5] state low-level or high-to-low change interrupt
5
1
read-write
IF_EN6
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[6] used to enable the interrupt for each of the corresponding input P0[6]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[6] bit "1": If the interrupt is level mode trigger, the input P0[6] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[6] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[6] state low-level or high-to-low change interrupt 0 = Disable the P0[6] state low-level or high-to-low change interrupt
6
1
read-write
IF_EN7
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[7] used to enable the interrupt for each of the corresponding input P0[7]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[7] bit "1": If the interrupt is level mode trigger, the input P0[7] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[7] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[7] state low-level or high-to-low change interrupt 0 = Disable the P0[7] state low-level or high-to-low change interrupt
7
1
read-write
IR_EN0
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[0] used to enable the interrupt for each of the corresponding input P0[0]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[0] bit "1": If the interrupt is level mode trigger, the input P0[0] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[0] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[0] level-high or low-to-high interrupt 0 = Disable the P0[0] level-high or low-to-high interrupt
16
1
read-write
IR_EN1
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[1] used to enable the interrupt for each of the corresponding input P0[1]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[1] bit "1": If the interrupt is level mode trigger, the input P0[1] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[1] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[1] level-high or low-to-high interrupt 0 = Disable the P0[1] level-high or low-to-high interrupt
17
1
read-write
IR_EN2
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[2] used to enable the interrupt for each of the corresponding input P0[2]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[2] bit "1": If the interrupt is level mode trigger, the input P0[2] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[2] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[2] level-high or low-to-high interrupt 0 = Disable the P0[2] level-high or low-to-high interrupt
18
1
read-write
IR_EN3
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[3] used to enable the interrupt for each of the corresponding input P0[3]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[3] bit "1": If the interrupt is level mode trigger, the input P0[3] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[3] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[3] level-high or low-to-high interrupt 0 = Disable the P0[3] level-high or low-to-high interrupt
19
1
read-write
IR_EN4
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[4] used to enable the interrupt for each of the corresponding input P0[4]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[4] bit "1": If the interrupt is level mode trigger, the input P0[4] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[4] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[4] level-high or low-to-high interrupt 0 = Disable the P0[4] level-high or low-to-high interrupt
20
1
read-write
IR_EN5
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[5] used to enable the interrupt for each of the corresponding input P0[5]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[5] bit "1": If the interrupt is level mode trigger, the input P0[5] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[5] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[5] level-high or low-to-high interrupt 0 = Disable the P0[5] level-high or low-to-high interrupt
21
1
read-write
IR_EN6
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[6] used to enable the interrupt for each of the corresponding input P0[6]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[6] bit "1": If the interrupt is level mode trigger, the input P0[6] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[6] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[6] level-high or low-to-high interrupt 0 = Disable the P0[6] level-high or low-to-high interrupt
22
1
read-write
IR_EN7
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[7] used to enable the interrupt for each of the corresponding input P0[7]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[7] bit "1": If the interrupt is level mode trigger, the input P0[7] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[7] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[7] level-high or low-to-high interrupt 0 = Disable the P0[7] level-high or low-to-high interrupt
23
1
read-write
IMD
Interrupt Mode Control
0x18
read-write
n
0x0
0x0
IMD0
Port 0 Interrupt Mode Control IMD[0] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
0
1
read-write
IMD1
Port 0 Interrupt Mode Control IMD[1] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
1
1
read-write
IMD2
Port 0 Interrupt Mode Control IMD[2] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
2
1
read-write
IMD3
Port 0 Interrupt Mode Control IMD[3] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
3
1
read-write
IMD4
Port 0 Interrupt Mode Control IMD[4] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
4
1
read-write
IMD5
Port 0 Interrupt Mode Control IMD[5] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
5
1
read-write
IMD6
Port 0 Interrupt Mode Control IMD[6] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
6
1
read-write
IMD7
Port 0 Interrupt Mode Control IMD[7] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
7
1
read-write
ISRC
Interrupt Trigger Source
0x20
read-write
n
0x0
0x0
ISRC0
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[0] generate an interrupt 0 = No interrupt at P0[0] Write: 1 = Clear the correspond pending interrupt 0 = No action
0
1
read-write
oneToClear
ISRC1
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[1] generate an interrupt 0 = No interrupt at P0[1] Write: 1 = Clear the correspond pending interrupt 0 = No action
1
1
read-write
oneToClear
ISRC2
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[2] generate an interrupt 0 = No interrupt at P0[2] Write: 1 = Clear the correspond pending interrupt 0 = No action
2
1
read-write
oneToClear
ISRC3
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[3] generate an interrupt 0 = No interrupt at P0[3] Write: 1 = Clear the correspond pending interrupt 0 = No action
3
1
read-write
oneToClear
ISRC4
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[4] generate an interrupt 0 = No interrupt at P0[4] Write: 1 = Clear the correspond pending interrupt 0 = No action
4
1
read-write
oneToClear
ISRC5
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[5] generate an interrupt 0 = No interrupt at P0[5] Write: 1 = Clear the correspond pending interrupt 0 = No action
5
1
read-write
oneToClear
ISRC6
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[6] generate an interrupt 0 = No interrupt at P0[6] Write: 1 = Clear the correspond pending interrupt 0 = No action
6
1
read-write
oneToClear
ISRC7
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[7] generate an interrupt 0 = No interrupt at P0[7] Write: 1 = Clear the correspond pending interrupt 0 = No action
7
1
read-write
oneToClear
OFFD
Bit OFF Digital Enable
0x4
read-write
n
0x0
0x0
OFFD
OFFD: P0 Pin OFF digital input path Enable 1 = Disable IO digital input path (digital input tied to low) 0 = Enable IO digital input path
16
8
read-write
PIN
Pin Value
0x10
read-only
n
0x0
0x0
PIN0
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[0].
0
1
read-only
PIN1
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[1].
1
1
read-only
PIN2
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[2].
2
1
read-only
PIN3
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[3].
3
1
read-only
PIN4
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[4].
4
1
read-only
PIN5
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[5].
5
1
read-only
PIN6
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[6].
6
1
read-only
PIN7
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[7].
7
1
read-only
PMD
Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
P0 I/O Pin[0] Mode Control Determine each I/O type of P0 pins 00 = P0[0] pin is in INPUT mode. 01 = P0[0] pin is in OUTPUT mode. 10 = P0[0] pin is in Open-Drain mode. 11 = P0[0] pin is in Quasi-bidirectional mode.
0
2
read-write
PMD1
P0 I/O Pin[1] Mode Control Determine each I/O type of P0 pins 00 = P0[1] pin is in INPUT mode. 01 = P0[1] pin is in OUTPUT mode. 10 = P0[1] pin is in Open-Drain mode. 11 = P0[1] pin is in Quasi-bidirectional mode.
2
2
read-write
PMD2
P0 I/O Pin[2] Mode Control Determine each I/O type of P0 pins 00 = P0[2] pin is in INPUT mode. 01 = P0[2] pin is in OUTPUT mode. 10 = P0[2] pin is in Open-Drain mode. 11 = P0[2] pin is in Quasi-bidirectional mode.
4
2
read-write
PMD3
P0 I/O Pin[3] Mode Control Determine each I/O type of P0 pins 00 = P0[3] pin is in INPUT mode. 01 = P0[3] pin is in OUTPUT mode. 10 = P0[3] pin is in Open-Drain mode. 11 = P0[3] pin is in Quasi-bidirectional mode.
6
2
read-write
PMD4
P0 I/O Pin[4] Mode Control Determine each I/O type of P0 pins 00 = P0[4] pin is in INPUT mode. 01 = P0[4] pin is in OUTPUT mode. 10 = P0[4] pin is in Open-Drain mode. 11 = P0[4] pin is in Quasi-bidirectional mode.
8
2
read-write
PMD5
P0 I/O Pin[5] Mode Control Determine each I/O type of P0 pins 00 = P0[5] pin is in INPUT mode. 01 = P0[5] pin is in OUTPUT mode. 10 = P0[5] pin is in Open-Drain mode. 11 = P0[5] pin is in Quasi-bidirectional mode.
10
2
read-write
PMD6
P0 I/O Pin[6] Mode Control Determine each I/O type of P0 pins 00 = P0[6] pin is in INPUT mode. 01 = P0[6] pin is in OUTPUT mode. 10 = P0[6] pin is in Open-Drain mode. 11 = P0[6] pin is in Quasi-bidirectional mode.
12
2
read-write
PMD7
P0 I/O Pin[7] Mode Control Determine each I/O type of P0 pins 00 = P0[7] pin is in INPUT mode. 01 = P0[7] pin is in OUTPUT mode. 10 = P0[7] pin is in Open-Drain mode. 11 = P0[7] pin is in Quasi-bidirectional mode.
14
2
read-write
GP2_BITS
Registers group
GPIO_BITS
0x0
0x200
0x20
registers
n
Px0_DOUT
Px.0 Data Output Value
0x200
read-write
n
0x0
0x0
DOUT
P0.0 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px1_DOUT
Px.1 Data Output Value
0x204
read-write
n
0x0
0x0
DOUT
P0.1 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px2_DOUT
Px.2 Data Output Value
0x208
read-write
n
0x0
0x0
DOUT
P0.2 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px3_DOUT
Px.3 Data Output Value
0x20C
read-write
n
0x0
0x0
DOUT
P0.3 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px4_DOUT
Px.4 Data Output Value
0x210
read-write
n
0x0
0x0
DOUT
P0.4 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px5_DOUT
Px.5 Data Output Value
0x214
read-write
n
0x0
0x0
DOUT
P0.5 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px6_DOUT
Px.6 Data Output Value
0x218
read-write
n
0x0
0x0
DOUT
P0.6 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px7_DOUT
Px.7 Data Output Value
0x21C
read-write
n
0x0
0x0
DOUT
P0.7 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
GP3
Registers group
GPIO
0x0
0x0
0x24
registers
n
DBEN
De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
P0 Input Signal De-bounce Enable DBEN[0] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[0] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[0] de-bounce function is disabled 1 = The bit[0] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
0
1
read-write
DBEN1
P0 Input Signal De-bounce Enable DBEN[1] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[1] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[1] de-bounce function is disabled 1 = The bit[1] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
1
1
read-write
DBEN2
P0 Input Signal De-bounce Enable DBEN[2] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[2] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[2] de-bounce function is disabled 1 = The bit[2] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
2
1
read-write
DBEN3
P0 Input Signal De-bounce Enable DBEN[3] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[3] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[3] de-bounce function is disabled 1 = The bit[3] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
3
1
read-write
DBEN4
P0 Input Signal De-bounce Enable DBEN[4] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[4] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[4] de-bounce function is disabled 1 = The bit[4] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
4
1
read-write
DBEN5
P0 Input Signal De-bounce Enable DBEN[5] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[5] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[5] de-bounce function is disabled 1 = The bit[5] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
5
1
read-write
DBEN6
P0 Input Signal De-bounce Enable DBEN[6] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[6] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[6] de-bounce function is disabled 1 = The bit[6] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
6
1
read-write
DBEN7
P0 Input Signal De-bounce Enable DBEN[7] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[7] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[7] de-bounce function is disabled 1 = The bit[7] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
7
1
read-write
DMASK
Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[0]. When set the DMASK bit[0] to "1", the corresponding DOUT0 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[0] bit can be updated 1 = The corresponding P0_DOUT[0] bit is protected
0
1
read-write
DMASK1
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[1]. When set the DMASK bit[1] to "1", the corresponding DOUT1 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[1] bit can be updated 1 = The corresponding P0_DOUT[1] bit is protected
1
1
read-write
DMASK2
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[2]. When set the DMASK bit[2] to "1", the corresponding DOUT2 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[2] bit can be updated 1 = The corresponding P0_DOUT[2] bit is protected
2
1
read-write
DMASK3
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[3]. When set the DMASK bit[3] to "1", the corresponding DOUT3 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[3] bit can be updated 1 = The corresponding P0_DOUT[3] bit is protected
3
1
read-write
DMASK4
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[4]. When set the DMASK bit[4] to "1", the corresponding DOUT4 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[4] bit can be updated 1 = The corresponding P0_DOUT[4] bit is protected
4
1
read-write
DMASK5
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[6]. When set the DMASK bit[6] to "1", the corresponding DOUT6 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[6] bit can be updated 1 = The corresponding P0_DOUT[6] bit is protected
5
1
read-write
DMASK6
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[6]. When set the DMASK bit[6] to "1", the corresponding DOUT6 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[6] bit can be updated 1 = The corresponding P0_DOUT[6] bit is protected
6
1
read-write
DMASK7
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[7]. When set the DMASK bit[7] to "1", the corresponding DOUT7 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[7] bit can be updated 1 = The corresponding P0_DOUT[7] bit is protected
7
1
read-write
DOUT
Data Output Value
0x8
read-write
n
0x0
0x0
DOUT0
P0 Pin[0] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[0] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[0] will drive Low if the corresponding output mode enabling bit is set.
0
1
read-write
DOUT1
P0 Pin[1] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[1] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[1] will drive Low if the corresponding output mode enabling bit is set.
1
1
read-write
DOUT2
P0 Pin[2] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[2] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[2] will drive Low if the corresponding output mode enabling bit is set.
2
1
read-write
DOUT3
P0 Pin[3] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[3] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[3] will drive Low if the corresponding output mode enabling bit is set.
3
1
read-write
DOUT4
P0 Pin[4] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[4] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[4] will drive Low if the corresponding output mode enabling bit is set.
4
1
read-write
DOUT5
P0 Pin[5] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[5] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[5] will drive Low if the corresponding output mode enabling bit is set.
5
1
read-write
DOUT6
P0 Pin[6] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[6] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[6] will drive Low if the corresponding output mode enabling bit is set.
6
1
read-write
DOUT7
P0 Pin[7] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[7] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[7] will drive Low if the corresponding output mode enabling bit is set.
7
1
read-write
IEN
Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[0] used to enable the interrupt for each of the corresponding input P0[0]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[0] bit "1": If the interrupt is level mode trigger, the input P0[0] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[0] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[0] state low-level or high-to-low change interrupt 0 = Disable the P0[0] state low-level or high-to-low change interrupt
0
1
read-write
IF_EN1
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[1] used to enable the interrupt for each of the corresponding input P0[1]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[1] bit "1": If the interrupt is level mode trigger, the input P0[1] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[1] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[1] state low-level or high-to-low change interrupt 0 = Disable the P0[1] state low-level or high-to-low change interrupt
1
1
read-write
IF_EN2
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[2] used to enable the interrupt for each of the corresponding input P0[2]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[2] bit "1": If the interrupt is level mode trigger, the input P0[2] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[2] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[2] state low-level or high-to-low change interrupt 0 = Disable the P0[2] state low-level or high-to-low change interrupt
2
1
read-write
IF_EN3
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[3] used to enable the interrupt for each of the corresponding input P0[3]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[3] bit "1": If the interrupt is level mode trigger, the input P0[3] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[3] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[3] state low-level or high-to-low change interrupt 0 = Disable the P0[3] state low-level or high-to-low change interrupt
3
1
read-write
IF_EN4
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[4] used to enable the interrupt for each of the corresponding input P0[4]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[4] bit "1": If the interrupt is level mode trigger, the input P0[4] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[4] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[4] state low-level or high-to-low change interrupt 0 = Disable the P0[4] state low-level or high-to-low change interrupt
4
1
read-write
IF_EN5
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[5] used to enable the interrupt for each of the corresponding input P0[5]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[5] bit "1": If the interrupt is level mode trigger, the input P0[5] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[5] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[5] state low-level or high-to-low change interrupt 0 = Disable the P0[5] state low-level or high-to-low change interrupt
5
1
read-write
IF_EN6
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[6] used to enable the interrupt for each of the corresponding input P0[6]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[6] bit "1": If the interrupt is level mode trigger, the input P0[6] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[6] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[6] state low-level or high-to-low change interrupt 0 = Disable the P0[6] state low-level or high-to-low change interrupt
6
1
read-write
IF_EN7
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[7] used to enable the interrupt for each of the corresponding input P0[7]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[7] bit "1": If the interrupt is level mode trigger, the input P0[7] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[7] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[7] state low-level or high-to-low change interrupt 0 = Disable the P0[7] state low-level or high-to-low change interrupt
7
1
read-write
IR_EN0
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[0] used to enable the interrupt for each of the corresponding input P0[0]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[0] bit "1": If the interrupt is level mode trigger, the input P0[0] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[0] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[0] level-high or low-to-high interrupt 0 = Disable the P0[0] level-high or low-to-high interrupt
16
1
read-write
IR_EN1
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[1] used to enable the interrupt for each of the corresponding input P0[1]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[1] bit "1": If the interrupt is level mode trigger, the input P0[1] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[1] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[1] level-high or low-to-high interrupt 0 = Disable the P0[1] level-high or low-to-high interrupt
17
1
read-write
IR_EN2
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[2] used to enable the interrupt for each of the corresponding input P0[2]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[2] bit "1": If the interrupt is level mode trigger, the input P0[2] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[2] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[2] level-high or low-to-high interrupt 0 = Disable the P0[2] level-high or low-to-high interrupt
18
1
read-write
IR_EN3
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[3] used to enable the interrupt for each of the corresponding input P0[3]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[3] bit "1": If the interrupt is level mode trigger, the input P0[3] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[3] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[3] level-high or low-to-high interrupt 0 = Disable the P0[3] level-high or low-to-high interrupt
19
1
read-write
IR_EN4
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[4] used to enable the interrupt for each of the corresponding input P0[4]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[4] bit "1": If the interrupt is level mode trigger, the input P0[4] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[4] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[4] level-high or low-to-high interrupt 0 = Disable the P0[4] level-high or low-to-high interrupt
20
1
read-write
IR_EN5
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[5] used to enable the interrupt for each of the corresponding input P0[5]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[5] bit "1": If the interrupt is level mode trigger, the input P0[5] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[5] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[5] level-high or low-to-high interrupt 0 = Disable the P0[5] level-high or low-to-high interrupt
21
1
read-write
IR_EN6
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[6] used to enable the interrupt for each of the corresponding input P0[6]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[6] bit "1": If the interrupt is level mode trigger, the input P0[6] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[6] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[6] level-high or low-to-high interrupt 0 = Disable the P0[6] level-high or low-to-high interrupt
22
1
read-write
IR_EN7
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[7] used to enable the interrupt for each of the corresponding input P0[7]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[7] bit "1": If the interrupt is level mode trigger, the input P0[7] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[7] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[7] level-high or low-to-high interrupt 0 = Disable the P0[7] level-high or low-to-high interrupt
23
1
read-write
IMD
Interrupt Mode Control
0x18
read-write
n
0x0
0x0
IMD0
Port 0 Interrupt Mode Control IMD[0] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
0
1
read-write
IMD1
Port 0 Interrupt Mode Control IMD[1] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
1
1
read-write
IMD2
Port 0 Interrupt Mode Control IMD[2] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
2
1
read-write
IMD3
Port 0 Interrupt Mode Control IMD[3] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
3
1
read-write
IMD4
Port 0 Interrupt Mode Control IMD[4] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
4
1
read-write
IMD5
Port 0 Interrupt Mode Control IMD[5] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
5
1
read-write
IMD6
Port 0 Interrupt Mode Control IMD[6] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
6
1
read-write
IMD7
Port 0 Interrupt Mode Control IMD[7] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
7
1
read-write
ISRC
Interrupt Trigger Source
0x20
read-write
n
0x0
0x0
ISRC0
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[0] generate an interrupt 0 = No interrupt at P0[0] Write: 1 = Clear the correspond pending interrupt 0 = No action
0
1
read-write
oneToClear
ISRC1
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[1] generate an interrupt 0 = No interrupt at P0[1] Write: 1 = Clear the correspond pending interrupt 0 = No action
1
1
read-write
oneToClear
ISRC2
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[2] generate an interrupt 0 = No interrupt at P0[2] Write: 1 = Clear the correspond pending interrupt 0 = No action
2
1
read-write
oneToClear
ISRC3
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[3] generate an interrupt 0 = No interrupt at P0[3] Write: 1 = Clear the correspond pending interrupt 0 = No action
3
1
read-write
oneToClear
ISRC4
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[4] generate an interrupt 0 = No interrupt at P0[4] Write: 1 = Clear the correspond pending interrupt 0 = No action
4
1
read-write
oneToClear
ISRC5
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[5] generate an interrupt 0 = No interrupt at P0[5] Write: 1 = Clear the correspond pending interrupt 0 = No action
5
1
read-write
oneToClear
ISRC6
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[6] generate an interrupt 0 = No interrupt at P0[6] Write: 1 = Clear the correspond pending interrupt 0 = No action
6
1
read-write
oneToClear
ISRC7
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[7] generate an interrupt 0 = No interrupt at P0[7] Write: 1 = Clear the correspond pending interrupt 0 = No action
7
1
read-write
oneToClear
OFFD
Bit OFF Digital Enable
0x4
read-write
n
0x0
0x0
OFFD
OFFD: P0 Pin OFF digital input path Enable 1 = Disable IO digital input path (digital input tied to low) 0 = Enable IO digital input path
16
8
read-write
PIN
Pin Value
0x10
read-only
n
0x0
0x0
PIN0
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[0].
0
1
read-only
PIN1
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[1].
1
1
read-only
PIN2
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[2].
2
1
read-only
PIN3
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[3].
3
1
read-only
PIN4
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[4].
4
1
read-only
PIN5
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[5].
5
1
read-only
PIN6
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[6].
6
1
read-only
PIN7
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[7].
7
1
read-only
PMD
Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
P0 I/O Pin[0] Mode Control Determine each I/O type of P0 pins 00 = P0[0] pin is in INPUT mode. 01 = P0[0] pin is in OUTPUT mode. 10 = P0[0] pin is in Open-Drain mode. 11 = P0[0] pin is in Quasi-bidirectional mode.
0
2
read-write
PMD1
P0 I/O Pin[1] Mode Control Determine each I/O type of P0 pins 00 = P0[1] pin is in INPUT mode. 01 = P0[1] pin is in OUTPUT mode. 10 = P0[1] pin is in Open-Drain mode. 11 = P0[1] pin is in Quasi-bidirectional mode.
2
2
read-write
PMD2
P0 I/O Pin[2] Mode Control Determine each I/O type of P0 pins 00 = P0[2] pin is in INPUT mode. 01 = P0[2] pin is in OUTPUT mode. 10 = P0[2] pin is in Open-Drain mode. 11 = P0[2] pin is in Quasi-bidirectional mode.
4
2
read-write
PMD3
P0 I/O Pin[3] Mode Control Determine each I/O type of P0 pins 00 = P0[3] pin is in INPUT mode. 01 = P0[3] pin is in OUTPUT mode. 10 = P0[3] pin is in Open-Drain mode. 11 = P0[3] pin is in Quasi-bidirectional mode.
6
2
read-write
PMD4
P0 I/O Pin[4] Mode Control Determine each I/O type of P0 pins 00 = P0[4] pin is in INPUT mode. 01 = P0[4] pin is in OUTPUT mode. 10 = P0[4] pin is in Open-Drain mode. 11 = P0[4] pin is in Quasi-bidirectional mode.
8
2
read-write
PMD5
P0 I/O Pin[5] Mode Control Determine each I/O type of P0 pins 00 = P0[5] pin is in INPUT mode. 01 = P0[5] pin is in OUTPUT mode. 10 = P0[5] pin is in Open-Drain mode. 11 = P0[5] pin is in Quasi-bidirectional mode.
10
2
read-write
PMD6
P0 I/O Pin[6] Mode Control Determine each I/O type of P0 pins 00 = P0[6] pin is in INPUT mode. 01 = P0[6] pin is in OUTPUT mode. 10 = P0[6] pin is in Open-Drain mode. 11 = P0[6] pin is in Quasi-bidirectional mode.
12
2
read-write
PMD7
P0 I/O Pin[7] Mode Control Determine each I/O type of P0 pins 00 = P0[7] pin is in INPUT mode. 01 = P0[7] pin is in OUTPUT mode. 10 = P0[7] pin is in Open-Drain mode. 11 = P0[7] pin is in Quasi-bidirectional mode.
14
2
read-write
GP3_BITS
Registers group
GPIO_BITS
0x0
0x200
0x20
registers
n
Px0_DOUT
Px.0 Data Output Value
0x200
read-write
n
0x0
0x0
DOUT
P0.0 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px1_DOUT
Px.1 Data Output Value
0x204
read-write
n
0x0
0x0
DOUT
P0.1 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px2_DOUT
Px.2 Data Output Value
0x208
read-write
n
0x0
0x0
DOUT
P0.2 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px3_DOUT
Px.3 Data Output Value
0x20C
read-write
n
0x0
0x0
DOUT
P0.3 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px4_DOUT
Px.4 Data Output Value
0x210
read-write
n
0x0
0x0
DOUT
P0.4 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px5_DOUT
Px.5 Data Output Value
0x214
read-write
n
0x0
0x0
DOUT
P0.5 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px6_DOUT
Px.6 Data Output Value
0x218
read-write
n
0x0
0x0
DOUT
P0.6 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px7_DOUT
Px.7 Data Output Value
0x21C
read-write
n
0x0
0x0
DOUT
P0.7 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
GP4
Registers group
GPIO
0x0
0x0
0x24
registers
n
DBEN
De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
P0 Input Signal De-bounce Enable DBEN[0] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[0] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[0] de-bounce function is disabled 1 = The bit[0] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
0
1
read-write
DBEN1
P0 Input Signal De-bounce Enable DBEN[1] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[1] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[1] de-bounce function is disabled 1 = The bit[1] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
1
1
read-write
DBEN2
P0 Input Signal De-bounce Enable DBEN[2] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[2] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[2] de-bounce function is disabled 1 = The bit[2] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
2
1
read-write
DBEN3
P0 Input Signal De-bounce Enable DBEN[3] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[3] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[3] de-bounce function is disabled 1 = The bit[3] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
3
1
read-write
DBEN4
P0 Input Signal De-bounce Enable DBEN[4] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[4] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[4] de-bounce function is disabled 1 = The bit[4] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
4
1
read-write
DBEN5
P0 Input Signal De-bounce Enable DBEN[5] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[5] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[5] de-bounce function is disabled 1 = The bit[5] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
5
1
read-write
DBEN6
P0 Input Signal De-bounce Enable DBEN[6] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[6] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[6] de-bounce function is disabled 1 = The bit[6] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
6
1
read-write
DBEN7
P0 Input Signal De-bounce Enable DBEN[7] used to enable the de-bounce function for each corresponding bit. if the input signal pulse width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[7] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 0 = The bit[7] de-bounce function is disabled 1 = The bit[7] de-bounce function is enabled The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
7
1
read-write
DMASK
Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[0]. When set the DMASK bit[0] to "1", the corresponding DOUT0 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[0] bit can be updated 1 = The corresponding P0_DOUT[0] bit is protected
0
1
read-write
DMASK1
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[1]. When set the DMASK bit[1] to "1", the corresponding DOUT1 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[1] bit can be updated 1 = The corresponding P0_DOUT[1] bit is protected
1
1
read-write
DMASK2
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[2]. When set the DMASK bit[2] to "1", the corresponding DOUT2 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[2] bit can be updated 1 = The corresponding P0_DOUT[2] bit is protected
2
1
read-write
DMASK3
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[3]. When set the DMASK bit[3] to "1", the corresponding DOUT3 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[3] bit can be updated 1 = The corresponding P0_DOUT[3] bit is protected
3
1
read-write
DMASK4
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[4]. When set the DMASK bit[4] to "1", the corresponding DOUT4 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[4] bit can be updated 1 = The corresponding P0_DOUT[4] bit is protected
4
1
read-write
DMASK5
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[6]. When set the DMASK bit[6] to "1", the corresponding DOUT6 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[6] bit can be updated 1 = The corresponding P0_DOUT[6] bit is protected
5
1
read-write
DMASK6
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[6]. When set the DMASK bit[6] to "1", the corresponding DOUT6 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[6] bit can be updated 1 = The corresponding P0_DOUT[6] bit is protected
6
1
read-write
DMASK7
P0 Data Output Write Mask These bits are used to protect the corresponding register of P0_DOUT bit[7]. When set the DMASK bit[7] to "1", the corresponding DOUT7 bit is protected. The write signal is masked, write data to the protect bit is ignored 0 = The corresponding P0_DOUT[7] bit can be updated 1 = The corresponding P0_DOUT[7] bit is protected
7
1
read-write
DOUT
Data Output Value
0x8
read-write
n
0x0
0x0
DOUT0
P0 Pin[0] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[0] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[0] will drive Low if the corresponding output mode enabling bit is set.
0
1
read-write
DOUT1
P0 Pin[1] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[1] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[1] will drive Low if the corresponding output mode enabling bit is set.
1
1
read-write
DOUT2
P0 Pin[2] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[2] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[2] will drive Low if the corresponding output mode enabling bit is set.
2
1
read-write
DOUT3
P0 Pin[3] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[3] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[3] will drive Low if the corresponding output mode enabling bit is set.
3
1
read-write
DOUT4
P0 Pin[4] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[4] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[4] will drive Low if the corresponding output mode enabling bit is set.
4
1
read-write
DOUT5
P0 Pin[5] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[5] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[5] will drive Low if the corresponding output mode enabling bit is set.
5
1
read-write
DOUT6
P0 Pin[6] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[6] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[6] will drive Low if the corresponding output mode enabling bit is set.
6
1
read-write
DOUT7
P0 Pin[7] Output Value Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain and quasi-mode. 1 = P0 Pin[7] will drive High if the corresponding output mode enabling bit is set. 0 = P0 Pin[7] will drive Low if the corresponding output mode enabling bit is set.
7
1
read-write
IEN
Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[0] used to enable the interrupt for each of the corresponding input P0[0]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[0] bit "1": If the interrupt is level mode trigger, the input P0[0] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[0] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[0] state low-level or high-to-low change interrupt 0 = Disable the P0[0] state low-level or high-to-low change interrupt
0
1
read-write
IF_EN1
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[1] used to enable the interrupt for each of the corresponding input P0[1]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[1] bit "1": If the interrupt is level mode trigger, the input P0[1] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[1] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[1] state low-level or high-to-low change interrupt 0 = Disable the P0[1] state low-level or high-to-low change interrupt
1
1
read-write
IF_EN2
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[2] used to enable the interrupt for each of the corresponding input P0[2]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[2] bit "1": If the interrupt is level mode trigger, the input P0[2] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[2] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[2] state low-level or high-to-low change interrupt 0 = Disable the P0[2] state low-level or high-to-low change interrupt
2
1
read-write
IF_EN3
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[3] used to enable the interrupt for each of the corresponding input P0[3]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[3] bit "1": If the interrupt is level mode trigger, the input P0[3] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[3] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[3] state low-level or high-to-low change interrupt 0 = Disable the P0[3] state low-level or high-to-low change interrupt
3
1
read-write
IF_EN4
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[4] used to enable the interrupt for each of the corresponding input P0[4]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[4] bit "1": If the interrupt is level mode trigger, the input P0[4] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[4] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[4] state low-level or high-to-low change interrupt 0 = Disable the P0[4] state low-level or high-to-low change interrupt
4
1
read-write
IF_EN5
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[5] used to enable the interrupt for each of the corresponding input P0[5]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[5] bit "1": If the interrupt is level mode trigger, the input P0[5] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[5] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[5] state low-level or high-to-low change interrupt 0 = Disable the P0[5] state low-level or high-to-low change interrupt
5
1
read-write
IF_EN6
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[6] used to enable the interrupt for each of the corresponding input P0[6]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[6] bit "1": If the interrupt is level mode trigger, the input P0[6] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[6] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[6] state low-level or high-to-low change interrupt 0 = Disable the P0[6] state low-level or high-to-low change interrupt
6
1
read-write
IF_EN7
Port0 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[7] used to enable the interrupt for each of the corresponding input P0[7]. Set bit "1" also enable the pin wakeup function. When set the IF_EN[7] bit "1": If the interrupt is level mode trigger, the input P0[7] state at level "low" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[7] state change from "high-to-low" will generate the interrupt. 1 = Enable the P0[7] state low-level or high-to-low change interrupt 0 = Disable the P0[7] state low-level or high-to-low change interrupt
7
1
read-write
IR_EN0
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[0] used to enable the interrupt for each of the corresponding input P0[0]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[0] bit "1": If the interrupt is level mode trigger, the input P0[0] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[0] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[0] level-high or low-to-high interrupt 0 = Disable the P0[0] level-high or low-to-high interrupt
16
1
read-write
IR_EN1
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[1] used to enable the interrupt for each of the corresponding input P0[1]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[1] bit "1": If the interrupt is level mode trigger, the input P0[1] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[1] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[1] level-high or low-to-high interrupt 0 = Disable the P0[1] level-high or low-to-high interrupt
17
1
read-write
IR_EN2
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[2] used to enable the interrupt for each of the corresponding input P0[2]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[2] bit "1": If the interrupt is level mode trigger, the input P0[2] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[2] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[2] level-high or low-to-high interrupt 0 = Disable the P0[2] level-high or low-to-high interrupt
18
1
read-write
IR_EN3
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[3] used to enable the interrupt for each of the corresponding input P0[3]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[3] bit "1": If the interrupt is level mode trigger, the input P0[3] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[3] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[3] level-high or low-to-high interrupt 0 = Disable the P0[3] level-high or low-to-high interrupt
19
1
read-write
IR_EN4
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[4] used to enable the interrupt for each of the corresponding input P0[4]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[4] bit "1": If the interrupt is level mode trigger, the input P0[4] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[4] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[4] level-high or low-to-high interrupt 0 = Disable the P0[4] level-high or low-to-high interrupt
20
1
read-write
IR_EN5
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[5] used to enable the interrupt for each of the corresponding input P0[5]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[5] bit "1": If the interrupt is level mode trigger, the input P0[5] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[5] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[5] level-high or low-to-high interrupt 0 = Disable the P0[5] level-high or low-to-high interrupt
21
1
read-write
IR_EN6
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[6] used to enable the interrupt for each of the corresponding input P0[6]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[6] bit "1": If the interrupt is level mode trigger, the input P0[6] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[6] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[6] level-high or low-to-high interrupt 0 = Disable the P0[6] level-high or low-to-high interrupt
22
1
read-write
IR_EN7
Port 0 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[7] used to enable the interrupt for each of the corresponding input P0[7]. Set bit "1" also enable the pin wakeup function. When set the IR_EN[7] bit "1": If the interrupt is level mode trigger, the input P0[7] state at level "high" will generate the interrupt. If the interrupt is edge mode trigger, the input P0[7] state change from "low-to-high" will generate the interrupt. 1 = Enable the P0[7] level-high or low-to-high interrupt 0 = Disable the P0[7] level-high or low-to-high interrupt
23
1
read-write
IMD
Interrupt Mode Control
0x18
read-write
n
0x0
0x0
IMD0
Port 0 Interrupt Mode Control IMD[0] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
0
1
read-write
IMD1
Port 0 Interrupt Mode Control IMD[1] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
1
1
read-write
IMD2
Port 0 Interrupt Mode Control IMD[2] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
2
1
read-write
IMD3
Port 0 Interrupt Mode Control IMD[3] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
3
1
read-write
IMD4
Port 0 Interrupt Mode Control IMD[4] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
4
1
read-write
IMD5
Port 0 Interrupt Mode Control IMD[5] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
5
1
read-write
IMD6
Port 0 Interrupt Mode Control IMD[6] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
6
1
read-write
IMD7
Port 0 Interrupt Mode Control IMD[7] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt 0 = Edge trigger interrupt 1 = Level trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored.
7
1
read-write
ISRC
Interrupt Trigger Source
0x20
read-write
n
0x0
0x0
ISRC0
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[0] generate an interrupt 0 = No interrupt at P0[0] Write: 1 = Clear the correspond pending interrupt 0 = No action
0
1
read-write
oneToClear
ISRC1
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[1] generate an interrupt 0 = No interrupt at P0[1] Write: 1 = Clear the correspond pending interrupt 0 = No action
1
1
read-write
oneToClear
ISRC2
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[2] generate an interrupt 0 = No interrupt at P0[2] Write: 1 = Clear the correspond pending interrupt 0 = No action
2
1
read-write
oneToClear
ISRC3
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[3] generate an interrupt 0 = No interrupt at P0[3] Write: 1 = Clear the correspond pending interrupt 0 = No action
3
1
read-write
oneToClear
ISRC4
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[4] generate an interrupt 0 = No interrupt at P0[4] Write: 1 = Clear the correspond pending interrupt 0 = No action
4
1
read-write
oneToClear
ISRC5
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[5] generate an interrupt 0 = No interrupt at P0[5] Write: 1 = Clear the correspond pending interrupt 0 = No action
5
1
read-write
oneToClear
ISRC6
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[6] generate an interrupt 0 = No interrupt at P0[6] Write: 1 = Clear the correspond pending interrupt 0 = No action
6
1
read-write
oneToClear
ISRC7
Port 0 Interrupt Trigger Source Indicator Read: 1 = Indicates P0[7] generate an interrupt 0 = No interrupt at P0[7] Write: 1 = Clear the correspond pending interrupt 0 = No action
7
1
read-write
oneToClear
OFFD
Bit OFF Digital Enable
0x4
read-write
n
0x0
0x0
OFFD
OFFD: P0 Pin OFF digital input path Enable 1 = Disable IO digital input path (digital input tied to low) 0 = Enable IO digital input path
16
8
read-write
PIN
Pin Value
0x10
read-only
n
0x0
0x0
PIN0
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[0].
0
1
read-only
PIN1
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[1].
1
1
read-only
PIN2
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[2].
2
1
read-only
PIN3
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[3].
3
1
read-only
PIN4
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[4].
4
1
read-only
PIN5
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[5].
5
1
read-only
PIN6
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[6].
6
1
read-only
PIN7
P0 Pin Values The value read from each of these bit reflects the actual status of the respective P0 Pin[7].
7
1
read-only
PMD
Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
P0 I/O Pin[0] Mode Control Determine each I/O type of P0 pins 00 = P0[0] pin is in INPUT mode. 01 = P0[0] pin is in OUTPUT mode. 10 = P0[0] pin is in Open-Drain mode. 11 = P0[0] pin is in Quasi-bidirectional mode.
0
2
read-write
PMD1
P0 I/O Pin[1] Mode Control Determine each I/O type of P0 pins 00 = P0[1] pin is in INPUT mode. 01 = P0[1] pin is in OUTPUT mode. 10 = P0[1] pin is in Open-Drain mode. 11 = P0[1] pin is in Quasi-bidirectional mode.
2
2
read-write
PMD2
P0 I/O Pin[2] Mode Control Determine each I/O type of P0 pins 00 = P0[2] pin is in INPUT mode. 01 = P0[2] pin is in OUTPUT mode. 10 = P0[2] pin is in Open-Drain mode. 11 = P0[2] pin is in Quasi-bidirectional mode.
4
2
read-write
PMD3
P0 I/O Pin[3] Mode Control Determine each I/O type of P0 pins 00 = P0[3] pin is in INPUT mode. 01 = P0[3] pin is in OUTPUT mode. 10 = P0[3] pin is in Open-Drain mode. 11 = P0[3] pin is in Quasi-bidirectional mode.
6
2
read-write
PMD4
P0 I/O Pin[4] Mode Control Determine each I/O type of P0 pins 00 = P0[4] pin is in INPUT mode. 01 = P0[4] pin is in OUTPUT mode. 10 = P0[4] pin is in Open-Drain mode. 11 = P0[4] pin is in Quasi-bidirectional mode.
8
2
read-write
PMD5
P0 I/O Pin[5] Mode Control Determine each I/O type of P0 pins 00 = P0[5] pin is in INPUT mode. 01 = P0[5] pin is in OUTPUT mode. 10 = P0[5] pin is in Open-Drain mode. 11 = P0[5] pin is in Quasi-bidirectional mode.
10
2
read-write
PMD6
P0 I/O Pin[6] Mode Control Determine each I/O type of P0 pins 00 = P0[6] pin is in INPUT mode. 01 = P0[6] pin is in OUTPUT mode. 10 = P0[6] pin is in Open-Drain mode. 11 = P0[6] pin is in Quasi-bidirectional mode.
12
2
read-write
PMD7
P0 I/O Pin[7] Mode Control Determine each I/O type of P0 pins 00 = P0[7] pin is in INPUT mode. 01 = P0[7] pin is in OUTPUT mode. 10 = P0[7] pin is in Open-Drain mode. 11 = P0[7] pin is in Quasi-bidirectional mode.
14
2
read-write
GP4_BITS
Registers group
GPIO_BITS
0x0
0x200
0x20
registers
n
Px0_DOUT
Px.0 Data Output Value
0x200
read-write
n
0x0
0x0
DOUT
P0.0 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px1_DOUT
Px.1 Data Output Value
0x204
read-write
n
0x0
0x0
DOUT
P0.1 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px2_DOUT
Px.2 Data Output Value
0x208
read-write
n
0x0
0x0
DOUT
P0.2 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px3_DOUT
Px.3 Data Output Value
0x20C
read-write
n
0x0
0x0
DOUT
P0.3 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px4_DOUT
Px.4 Data Output Value
0x210
read-write
n
0x0
0x0
DOUT
P0.4 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px5_DOUT
Px.5 Data Output Value
0x214
read-write
n
0x0
0x0
DOUT
P0.5 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px6_DOUT
Px.6 Data Output Value
0x218
read-write
n
0x0
0x0
DOUT
P0.6 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
Px7_DOUT
Px.7 Data Output Value
0x21C
read-write
n
0x0
0x0
DOUT
P0.7 I/O Pin Bit Output Control Set this bit can control one GPIO pin output value 1 = Set corresponding GPIO bit to high 0 = Set corresponding GPIO bit to low
0
1
read-write
GPIO
Registers group
GPIO_GCR
0x0
0x0
0x4
registers
n
DBNCECON
Interrupt De-bounce Cycle Control
0x0
read-write
n
0x0
0x0
DBCLKSEL
De-bounce sampling cycle selection DBCLKSEL Description 0 Sample interrupt input once per 1 clocks 1 Sample interrupt input once per 2 clocks 2 Sample interrupt input once per 4 clocks 3 Sample interrupt input once per 8 clocks 4 Sample interrupt input once per 16 clocks 5 Sample interrupt input once per 32 clocks 6 Sample interrupt input once per 64 clocks 7 Sample interrupt input once per 128 clocks 8 Sample interrupt input once per 256 clocks 9 Sample interrupt input once per 2*256 clocks 10 Sample interrupt input once per 4*256clocks 11 Sample interrupt input once per 8*256 clocks 12 Sample interrupt input once per 16*256 clocks 13 Sample interrupt input once per 32*256 clocks 14 Sample interrupt input once per 64*256 clocks 15 Sample interrupt input once per 128*256 clocks
0
4
read-write
DBCLKSRC
De-bounce counter clock source select 1 = De-bounce counter clock source is the internal 10KHz clock 0 = De-bounce counter clock source is the HCLK
4
1
read-write
ICLK_ON
Interrupt clock On mode Set this bit "0" will disable the interrupt generate circuit clock, if the pin[n] interrupt is disabled 0 = disable the clock if the P0/1/2/3/4[n] interrupt is disabled 1 = interrupt generated circuit clock always enable n=0~7
5
1
read-write
I2C
Registers group
I2C
0x0
0x0
0x30
registers
n
I2CADDR0
I2C slave Address Register0
0x4
read-write
n
0x0
0x0
GC
General Call Function 0 = Disable General Call Function. 1 = Enable General Call Function.
0
1
read-write
I2CADDR
I2C Address Register The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
I2CADDR1
I2C slave Address Register1
0x18
read-write
n
0x0
0x0
GC
General Call Function 0 = Disable General Call Function. 1 = Enable General Call Function.
0
1
read-write
I2CADDR
I2C Address Register The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
I2CADDR2
I2C slave Address Register2
0x1C
read-write
n
0x0
0x0
GC
General Call Function 0 = Disable General Call Function. 1 = Enable General Call Function.
0
1
read-write
I2CADDR
I2C Address Register The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
I2CADDR3
I2C slave Address Register3
0x20
read-write
n
0x0
0x0
GC
General Call Function 0 = Disable General Call Function. 1 = Enable General Call Function.
0
1
read-write
I2CADDR
I2C Address Register The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
I2CADM0
I2C Slave address Mask Register0
0x24
read-write
n
0x0
0x0
I2ADMx
I2C Address Mask register 1 = Mask enable (the received corresponding address bit is don't care.) 0 = Mask disable (the received corresponding register bit should be exact the same as address register.) I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
I2CADM1
I2C Slave address Mask Register1
0x28
read-write
n
0x0
0x0
I2ADMx
I2C Address Mask register 1 = Mask enable (the received corresponding address bit is don't care.) 0 = Mask disable (the received corresponding register bit should be exact the same as address register.) I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
I2CADM2
I2C Slave address Mask Register2
0x2C
read-write
n
0x0
0x0
I2ADMx
I2C Address Mask register 1 = Mask enable (the received corresponding address bit is don't care.) 0 = Mask disable (the received corresponding register bit should be exact the same as address register.) I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
I2CADM3
I2C Slave address Mask Register3
0x30
read-write
n
0x0
0x0
I2ADMx
I2C Address Mask register 1 = Mask enable (the received corresponding address bit is don't care.) 0 = Mask disable (the received corresponding register bit should be exact the same as address register.) I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
I2CDAT
I2C DATA Register
0x8
read-write
n
0x0
0x0
I2CDAT
I2C Data Register Bit[7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2CLK
I2C clock divided Register
0x10
read-write
n
0x0
0x0
I2CLK
I2C clock divided Register The I2C clock rate bits: Data Baud Rate of I2C = PCLK /(4x(I2CLK+1)).
0
8
read-write
I2CON
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge control bit. When AA=1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter. When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
2
1
read-write
EI
Enable interrupt. 1 = Enable I2C interrupt. 0 = Disable I2C interrupt.
7
1
read-write
ENSI
I2C controller is enabled/disable 1 = Enable 0 = Disable Set to enable I2C serial function block. When ENS=1 the I2C serial function enables. The multi-function pin function of SDA and SCL must set to I2C function first.
6
1
read-write
SI
I2C Interrupt Flag. When a new SIO state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one to this bit.
3
1
read-write
oneToClear
STA
I2C START Flag. Setting STA to logic 1 to enter master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Flag. In master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this flag will be cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2CSTATUS
I2C Status Register
0xC
read-only
n
0x0
0x0
I2CSTATUS
I2C Status Register The status register of I2C: The three least significant bits are always 0. The five most significant bits contain the status code. There are 26 possible status codes. When I2STATUS contains F8H, no serial interrupt is requested. All other I2STATUS values correspond to defined I2C states. When each of these states is entered, a status interrupt is requested (SI = 1). A valid status code is present in I2STATUS one machine cycle after SI is set by hardware and is still present one machine cycle after SI has been reset by software. In addition, states 00H stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame. Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
0
8
read-only
I2CTOC
I2C Time out control Register
0x14
read-write
n
0x0
0x0
DIV4
Time-Out counter input clock is divider by 4 1 = Enable 0 = Disable When Enable, The time-Out period is prolong 4 times.
1
1
read-write
ENTI
Time-out counter is enabled/disable 1 = Enable 0 = Disable When Enable, the 14 bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
2
1
read-write
TIF
Time-Out flag. 1 = Time-Out falg is set by H/W. It can interrupt CPU. 0 = S/W can clear the flag.
0
1
read-write
oneToClear
INT
Registers group
INT
0x0
0x0
0x40
registers
n
0x48
0x4
registers
n
0x54
0x8
registers
n
0x70
0xC
registers
n
0x80
0x8
registers
n
IRQ0_SRC
MCU IRQ0 (BOD) interrupt source identify
0x0
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1 = 0 Bit0: BOD_INT
0
3
read-only
IRQ10_SRC
MCU IRQ10 (TMR2) interrupt source identify
0x28
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1 = 0 Bit0: TMR2_INT
0
3
read-only
IRQ11_SRC
MCU IRQ11 (TMR3) interrupt source identify
0x2C
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1 = 0 Bit0: TMR3_INT
0
3
read-only
IRQ12_SRC
MCU IRQ12 (URT0) interrupt source identify
0x30
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1 = 0 Bit0: URT0_INT
0
3
read-only
IRQ13_SRC
MCU IRQ13 (URT1) interrupt source identify
0x34
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1 = 0 Bit0: URT1_INT
0
3
read-only
IRQ14_SRC
MCU IRQ14 (SPI0) interrupt source identify
0x38
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1 = 0 Bit0: SPI0_INT
0
3
read-only
IRQ15_SRC
MCU IRQ15 (SPI1) interrupt source identify
0x3C
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1 = 0 Bit0: SPI1_INT
0
3
read-only
IRQ18_SRC
MCU IRQ18 (I2C) interrupt source identify
0x48
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1 = 0 Bit0: I2C_INT
0
3
read-only
IRQ1_SRC
MCU IRQ1 (WDT) interrupt source identify
0x4
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1 = 0 Bit0: WDT_INT
0
3
read-only
IRQ21_SRC
MCU IRQ21 (Reserved) interrupt source identify
0x54
read-only
n
0x0
0x0
INT_SRC
Reserved
0
3
read-only
IRQ22_SRC
MCU IRQ22 (Reserved) interrupt source identify
0x58
read-only
n
0x0
0x0
INT_SRC
Reserved
0
3
read-only
IRQ28_SRC
MCU IRQ28 (PWRWU) interrupt source identify
0x70
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1 = 0 Bit0: PWRWU_INT
0
3
read-only
IRQ29_SRC
MCU IRQ29 (ADC) interrupt source identify
0x74
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1 = 0 Bit0: ADC_INT
0
3
read-only
IRQ2_SRC
MCU IRQ2 ((EINT0) interrupt source identify
0x8
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1 = 0 Bit0: EINT0 - external interrupt 0 from P3.2
0
3
read-only
IRQ30_SRC
MCU IRQ30 (Reserved) interrupt source identify
0x78
read-only
n
0x0
0x0
INT_SRC
Reserved
0
3
read-only
IRQ3_SRC
MCU IRQ3 (EINT1) interrupt source identify
0xC
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1 = 0 Bit0: EINT1 - external interrupt 1 from P3.3
0
3
read-only
IRQ4_SRC
MCU IRQ4 (P0/1) interrupt source identify
0x10
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1: P1_INT Bit0: P0_INT
0
3
read-only
IRQ5_SRC
MCU IRQ5 (P2/3/4) interrupt source identify
0x14
read-only
n
0x0
0x0
INT_SRC
Bit2: P4_INT Bit1: P3_INT Bit0: P2_INT
0
3
read-only
IRQ6_SRC
MCU IRQ6 (PWMA) interrupt source identify
0x18
read-only
n
0x0
0x0
INT_SRC
Bit3: PWM3_INT Bit2: PWM2_INT Bit1: PWM1_INT Bit0: PWM0_INT
0
4
read-only
IRQ7_SRC
MCU IRQ7 (PWMB) interrupt source identify
0x1C
read-only
n
0x0
0x0
INT_SRC
Bit3: PWM7_INT Bit2: PWM6_INT Bit1: PWM5_INT Bit0: PWM4_INT
0
4
read-only
IRQ8_SRC
MCU IRQ8 (TMR0) interrupt source identify
0x20
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1 = 0 Bit0: TMR0_INT
0
3
read-only
IRQ9_SRC
MCU IRQ9 (TMR1) interrupt source identify
0x24
read-only
n
0x0
0x0
INT_SRC
Bit2 = 0 Bit1 = 0 Bit0: TMR1_INT
0
3
read-only
MCU_IRQ
MCU IRQ Number identify register
0x84
read-write
n
0x0
0x0
MCU_IRQ
MCU IRQ Source Register The MCU_IRQ collect all the interrupts from the peripherals and generate the synchronous interrupt to MCU Cortex-M0. There are two modes to generate interrupt to MCU Cortex-M0, the normal mode and test mode. The MCU_IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0. When the MCU_IRQ[n] is "0": Set MCU_IRQ[n] "1" will generate an interrupt to Cortex_M0 NVIC[n]. When the MCU_IRQ[n] is "1"(mean an interrupt is assert) set 1 the MCU_bit[n] will clear the interrupt Set MCU_IRQ[n] "0": no any effect
0
32
read-write
oneToClear
NMI_SEL
NMI source interrupt select control register
0x80
read-write
n
0x0
0x0
NMI_SEL
The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0] The NMI_SEL bit[4:0] used to select the NMI interrupt source
0
5
read-write
PWMA
Registers group
PWM
0x0
0x0
0x3C
registers
n
0x40
0x8
registers
n
0x50
0x30
registers
n
CAPENR
Capture Input Enable Register
0x78
read-write
n
0x0
0x0
CAPENR
Capture Input Enable Register There are four capture inputs from pad. Bit0~Bit3 are used to control each inputs ON or OFF. 0 = OFF (PWMx multi-function pin input does not affect input capture function.) 1 = (PWMx multi-function pin input will affect its input capture function.) CAPENR Bit 3210 for PWM group A Bit xxx1 -> Capture channel 0 is from P2 [0] Bit xx1x -> Capture channel 1 is from P2 [1] Bit x1xx -> Capture channel 2 is from P2 [2] Bit 1xxx -> Capture channel 3 is from P2 [3] Bit 3210 for PWM group B Bit xxx1 -> Capture channel 0 is from P2 [4] Bit xx1x -> Capture channel 1 is from P2 [5] Bit x1xx -> Capture channel 2 is from P2 [6] Bit 1xxx -> Capture channel 3 is from P2 [7]
0
4
read-write
CCR0
Capture Control Register
0x50
read-write
n
0x0
0x0
CAPCH0EN
Capture Channel 0 transition Enable/Disable 1 = Enable capture function on PWM group channel 0. 0 = Disable capture function on PWM group channel 0 When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.
3
1
read-write
CAPCH1EN
Capture Channel 1 transition Enable/Disable 1 = Enable capture function on PWM group channel 1. 0 = Disable capture function on PWM group channel 1 When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.
19
1
read-write
CAPIF0
Capture0 Interrupt Indication Flag If PWM group channel 0 rising latch interrupt is enabled (CRL_IE0=1), a rising transition occurs at PWM group channel 0 will result in CAPIF0 to high; Similarly, a falling transition will cause CAPIF0 to be set high if PWM group channel 0 falling latch interrupt is enabled (CFL_IE0=1). This flag is clear by software with a write 1 to itself.
4
1
read-write
oneToClear
CAPIF1
Capture1 Interrupt Indication Flag If PWM group channel 1 rising latch interrupt is enabled (CRL_IE1=1), a rising transition occurs at PWM group channel 1 will result in CAPIF1 to high; Similarly, a falling transition will cause CAPIF1 to be set high if PWM group channel 1 falling latch interrupt is enabled (CFL_IE1=1). This flag is clear by software with a write 1 to itself.
20
1
read-write
oneToClear
CFLRI0
CFLR0 Latched Indicator Bit When PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
7
1
read-write
oneToClear
CFLRI1
CFLR1 Latched Indicator Bit When PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
23
1
read-write
oneToClear
CFL_IE0
PWM Group Channel 0 Falling Latch Interrupt Enable ON/OFF 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 0 has falling transition, Capture issues an Interrupt.
2
1
read-write
CFL_IE1
PWM Group Channel 1 Falling Latch Interrupt Enable ON/OFF 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 1 has falling transition, Capture issues an Interrupt.
18
1
read-write
CRLRI0
CRLR0 Latched Indicator Bit When PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
6
1
read-write
oneToClear
CRLRI1
CRLR1 Latched Indicator Bit When PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
22
1
read-write
oneToClear
CRL_IE0
PWM Group Channel 0 Rising Latch Interrupt Enable ON/OFF 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 0 has rising transition, Capture issues an Interrupt.
1
1
read-write
CRL_IE1
PWM Group Channel 1 Rising Latch Interrupt Enable ON/OFF 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 1 has rising transition, Capture issues an Interrupt.
17
1
read-write
INV0
PWM Group Channel 0 Inverter ON/OFF 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter OFF
0
1
read-write
INV1
PWM Group Channel 1 Inverter ON/OFF 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter OFF
16
1
read-write
CCR2
Capture Control Register
0x54
read-write
n
0x0
0x0
CAPCH2EN
Capture Channel 2 transition Enable/Disable 1 = Enable capture function on PWM group channel 2. 0 = Disable capture function on PWM group channel 2 When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.
3
1
read-write
CAPCH3EN
Capture Channel 3 transition Enable/Disable 1 = Enable capture function on PWM group channel 3. 0 = Disable capture function on PWM group channel 3 When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.
19
1
read-write
CAPIF2
Capture2 Interrupt Indication Flag If PWM group channel 2 rising latch interrupt is enabled (CRL_IE2=1), a rising transition occurs at PWM group channel 2 will result in CAPIF2 to high; Similarly, a falling transition will cause CAPIF2 to be set high if PWM group channel 2 falling latch interrupt is enabled (CFL_IE2=1). This flag is clear by software with a write 1 to itself.
4
1
read-write
oneToClear
CAPIF3
Capture3 Interrupt Indication Flag If PWM group channel 3 rising latch interrupt is enabled (CRL_IE3=1), a rising transition occurs at PWM group channel 3 will result in CAPIF3 to high; Similarly, a falling transition will cause CAPIF3 to be set high if PWM group channel 3 falling latch interrupt is enabled (CFL_IE3=1). This flag is clear by software with a write 1 to itself.
20
1
read-write
oneToClear
CFLRI2
CFLR2 Latched Indicator Bit When PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
7
1
read-write
oneToClear
CFLRI3
CFLR3 Latched Indicator Bit When PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
23
1
read-write
oneToClear
CFL_IE2
PWM Group Channel 2 Falling Latch Interrupt Enable ON/OFF 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 2 has falling transition, Capture issues an Interrupt.
2
1
read-write
CFL_IE3
PWM Group Channel 3 Falling Latch Interrupt Enable ON/OFF 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 3 has falling transition, Capture issues an Interrupt.
18
1
read-write
CRLRI2
CRLR2 Latched Indicator Bit When PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
6
1
read-write
oneToClear
CRLRI3
CRLR3 Latched Indicator Bit When PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
22
1
read-write
oneToClear
CRL_IE2
PWM Group Channel 2 Rising Latch Interrupt Enable ON/OFF 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 2 has rising transition, Capture issues an Interrupt.
1
1
read-write
CRL_IE3
PWM Group Channel 3 Rising Latch Interrupt Enable ON/OFF 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 3 has rising transition, Capture issues an Interrupt.
17
1
read-write
INV2
PWM Group Channel 2 Inverter ON/OFF 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter OFF
0
1
read-write
INV3
PWM Group Channel 3 Inverter ON/OFF 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter OFF
16
1
read-write
CFLR0
Capture Falling Latch Register (Channel 0)
0x5C
read-only
n
0x0
0x0
CFLR
Capture Falling Latch Register Latch the PWM counter when Channel 01/2/3 has Falling transition.
0
16
read-only
CFLR1
Capture Falling Latch Register (Channel 1)
0x64
read-only
n
0x0
0x0
CFLR
Capture Falling Latch Register Latch the PWM counter when Channel 01/2/3 has Falling transition.
0
16
read-only
CFLR2
Capture Falling Latch Register (channel 2)
0x6C
read-only
n
0x0
0x0
CFLR
Capture Falling Latch Register Latch the PWM counter when Channel 0/1/2/3 has Falling transition.
0
16
read-only
CFLR3
Capture Falling Latch Register (channel 3)
0x74
read-only
n
0x0
0x0
CFLR
Capture Falling Latch Register Latch the PWM counter when Channel 0/1/2/3 has Falling transition.
0
16
read-only
CMR0
PWM Comparator Register 0
0x10
read-write
n
0x0
0x0
CMR
PWM Comparator Register CNR determines the PWM duty. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CMR1
PWM Comparator Register 1
0x1C
read-write
n
0x0
0x0
CMR
PWM Comparator Register CNR determines the PWM duty. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CMR2
PWM Comparator Register 2
0x28
read-write
n
0x0
0x0
CMR
PWM Comparator Register CNR determines the PWM duty. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CMR3
PWM Comparator Register 3
0x34
read-write
n
0x0
0x0
CMR
PWM Comparator Register CNR determines the PWM duty. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CNR0
PWM Counter Register 0
0xC
read-write
n
0x0
0x0
CNR
PWM Counter/Timer Loaded Value CNR determines the PWM period. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CNR1
PWM Counter Register 1
0x18
read-write
n
0x0
0x0
CNR
PWM Counter/Timer Loaded Value CNR determines the PWM period. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CNR2
PWM Counter Register 2
0x24
read-write
n
0x0
0x0
CNR
PWM Counter/Timer Loaded Value CNR determines the PWM period. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CNR3
PWM Counter Register 3
0x30
read-write
n
0x0
0x0
CNR
PWM Counter/Timer Loaded Value CNR determines the PWM period. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CRLR0
Capture Rising Latch Register (Channel 0)
0x58
read-only
n
0x0
0x0
CRLR
Capture Rising Latch Register Latch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CRLR1
Capture Rising Latch Register (Channel 1)
0x60
read-only
n
0x0
0x0
CRLR
Capture Rising Latch Register Latch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CRLR2
Capture Rising Latch Register (channel 2)
0x68
read-only
n
0x0
0x0
CRLR
Capture Rising Latch Register Latch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CRLR3
Capture Rising Latch Register (channel 3)
0x70
read-only
n
0x0
0x0
CRLR
Capture Rising Latch Register Latch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CSR
PWM Clock Select Register
0x4
read-write
n
0x0
0x0
CSR0
Timer 0 Clock Source Selection(PWM timer 0 for group A and PWM timer 4 for group B) Select clock input for timer. (Table is the same as CSR3)
0
3
read-write
CSR1
Timer 1 Clock Source Selection(PWM timer 1 for group A and PWM timer 5 for group B) Select clock input for timer. (Table is the same as CSR3)
4
3
read-write
CSR2
Timer 2 Clock Source Selection(PWM timer 2 for group A and PWM timer 6 for group B) Select clock input for timer. (Table is the same as CSR3)
8
3
read-write
CSR3
Timer 3 Clock Source Selection (PWM timer 3 for group A and PWM timer 7 for group B) Select clock input for timer. CSR3 [14:12] Input clock divided by 100 1 011 16 010 8 001 4 000 2
12
3
read-write
PCR
PWM Control Register
0x8
read-write
n
0x0
0x0
CH0EN
PWM-Timer 0 Enable/Disable Start Run (PWM timer 0 for group A and PWM timer 4 for group B) 1 = Enable corresponding PWM-Timer Start Run 0 = Stop corresponding PWM-Timer Running
0
1
read-write
CH0INV
PWM-Timer 0 Output Inverter ON/OFF(PWM timer 0 for group A and PWM timer 4 for group B) 1 = Inverter ON 0 = Inverter OFF
2
1
read-write
CH0MOD
PWM-Timer 0 Auto-reload/One-Shot Mode(PWM timer 0 for group A and PWM timer 4 for group B) 1 = Auto-reload Mode 0 = One-Shot Mode Note: If there is a rising transition at this bit, it will cause CNR0 and CMR0 be clear.
3
1
read-write
CH1EN
PWM-Timer 1 Enable/Disable Start Run (PWM timer 1 for group A and PWM timer 5 for group B) 1 = Enable corresponding PWM-Timer Start Run 0 = Stop corresponding PWM-Timer Running
8
1
read-write
CH1INV
PWM-Timer 1 Output Inverter ON/OFF(PWM timer 1 for group A and PWM timer 5 for group B) 1 = Inverter ON 0 = Inverter OFF
10
1
read-write
CH1MOD
PWM-Timer 1 Auto-reload/One-Shot Mode(PWM timer 1 for group A and PWM timer 5 for group B) 1 = Auto-reload Mode 0 = One-Shot Mode Note: If there is a rising transition at this bit, it will cause CNR1 and CMR1 be clear.
11
1
read-write
CH2EN
PWM-Timer 2 Enable/Disable Start Run (PWM timer 2 for group A and PWM timer 6 for group B) 1 = Enable corresponding PWM-Timer Start Run 0 = Stop corresponding PWM-Timer Running
16
1
read-write
CH2INV
PWM-Timer 2 Output Inverter ON/OFF(PWM timer 2 for group A and PWM timer 6 for group B) 1 = Inverter ON 0 = Inverter OFF
18
1
read-write
CH2MOD
PWM-Timer 2 Auto-reload/One-Shot Mode(PWM timer 2 for group A and PWM timer 6 for group B) 1 = Auto-reload Mode 0 = One-Shot Mode Note: If there is a rising transition at this bit, it will cause CNR2 and CMR2 be clear.
19
1
read-write
CH3EN
PWM-Timer 3 Enable/Disable Start Run (PWM timer 3 for group A and PWM timer 7 for group B) 1 = Enable corresponding PWM-Timer Start Run 0 = Stop corresponding PWM-Timer Running
24
1
read-write
CH3INV
PWM-Timer 3 Output Inverter ON/OFF(PWM timer 3 for group A and PWM timer 7 for group B) 1 = Inverter ON 0 = Inverter OFF
26
1
read-write
CH3MOD
PWM-Timer 3 Auto-reload/One-Shot Mode(PWM timer 3 for group A and PWM timer 7 for group B) 1 = Auto-reload Mode 0 = One-Shot Mode Note: If there is a rising transition at this bit, it will cause CNR3 and CMR3 be clear.
27
1
read-write
DZEN01
Dead-Zone 0 Generator Enable/Disable(PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B) 1 = Enable 0 = Disable Note: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B.
4
1
read-write
DZEN23
Dead-Zone 2 Generator Enable/Disable(PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B) 1 = Enable 0 = Disable Note: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B.
5
1
read-write
PDR0
PWM Data Register 0
0x14
read-only
n
0x0
0x0
PDR
PWM Data Register User can monitor PDR to know the current value in 16-bit down counter.
0
16
read-only
PDR1
PWM Data Register 1
0x20
read-only
n
0x0
0x0
PDR
PWM Data Register User can monitor PDR to know the current value in 16-bit down counter.
0
16
read-only
PDR2
PWM Data Register 2
0x2C
read-only
n
0x0
0x0
PDR
PWM Data Register User can monitor PDR to know the current value in 16-bit down counter.
0
16
read-only
PDR3
PWM Data Register 3
0x38
read-only
n
0x0
0x0
PDR
PWM Data Register User can monitor PDR to know the current value in 16-bit down counter.
0
16
read-only
PIER
PWM Interrupt Enable Register
0x40
read-write
n
0x0
0x0
PWMIE0
PWM channel 0 Interrupt Enable 1 = Enable 0 = Disable
0
1
read-write
PWMIE1
PWM channel 1 Interrupt Enable 1 = Enable 0 = Disable
1
1
read-write
PWMIE2
PWM channel 2 Interrupt Enable 1 = Enable 0 = Disable
2
1
read-write
PWMIE3
PWM channel 3 Interrupt Enable 1 = Enable 0 = Disable
3
1
read-write
PIIR
PWM Interrupt Indication Register
0x44
read-write
n
0x0
0x0
PWMIF0
PWM channel 0 Interrupt Status Flag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing a one to it.
0
1
read-write
oneToClear
PWMIF1
PWM channel 1 Interrupt Status Flag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing a one to it.
1
1
read-write
oneToClear
PWMIF2
PWM channel 2 Interrupt Status Flag is set by hardware when PWM2 down counter reaches zero, software can clear this bit by writing a one to it.
2
1
read-write
oneToClear
PWMIF3
PWM channel 3 Interrupt Status Flag is set by hardware when PWM3 down counter reaches zero, software can clear this bit by writing a one to it.
3
1
read-write
oneToClear
POE
PWM Output Enable
0x7C
read-write
n
0x0
0x0
PWM0
PWM Channel 0 Output Enable Register 1 = Enable PWM channel 0 output to pin. 0 = Disable PWM channel 0 output to pin. Note: The corresponding GPIO pin also must be switched to PWM function.
0
1
read-write
PWM1
PWM Channel 1 Output Enable Register 1 = Enable PWM channel 1 output to pin. 0 = Disable PWM channel 1 output to pin. Note: The corresponding GPIO pin also must be switched to PWM function.
1
1
read-write
PWM2
PWM Channel 2 Output Enable Register 1 = Enable PWM channel 2 output to pin. 0 = Disable PWM channel 2 output to pin. Note: The corresponding GPIO pin also must be switched to PWM function.
2
1
read-write
PWM3
PWM Channel 3 Output Enable Register 1 = Enable PWM channel 3 output to pin. 0 = Disable PWM channel 3 output to pin. Note: The corresponding GPIO pin also must be switched to PWM function.
3
1
read-write
PPR
PWM Pre-scalar Register
0x0
read-write
n
0x0
0x0
CP01
Clock pre-scalar 0(PWM counter 0 & 1 for group A and PWM counter 4 & 5 for group B) Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter If CP01=0, then the pre-scalar 0 output clock will be stopped. So corresponding PWM counter will be stopped also.
0
8
read-write
CP23
Clock pre-scalar 2(PWM counter 2 & 3 for group A and PWM counter 6 & 7 for group B) Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter If CP23=0, then the pre-scalar 2 output clock will be stopped. So corresponding PWM counter will be stopped also.
8
8
read-write
DZI01
Dead zone interval register for pair of channel 0 and channel 1(PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B) These 8 bits determine dead zone length. The unit time of dead zone length is received from corresponding CSR bits.
16
8
read-write
DZI23
Dead zone interval register for pair of channel 2 and channel 3(PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B) These 8 bits determine dead zone length. The unit time of dead zone length is received from corresponding CSR bits.
24
8
read-write
PWMB
Registers group
PWM
0x0
0x0
0x3C
registers
n
0x40
0x8
registers
n
0x50
0x30
registers
n
CAPENR
Capture Input Enable Register
0x78
read-write
n
0x0
0x0
CAPENR
Capture Input Enable Register There are four capture inputs from pad. Bit0~Bit3 are used to control each inputs ON or OFF. 0 = OFF (PWMx multi-function pin input does not affect input capture function.) 1 = (PWMx multi-function pin input will affect its input capture function.) CAPENR Bit 3210 for PWM group A Bit xxx1 -> Capture channel 0 is from P2 [0] Bit xx1x -> Capture channel 1 is from P2 [1] Bit x1xx -> Capture channel 2 is from P2 [2] Bit 1xxx -> Capture channel 3 is from P2 [3] Bit 3210 for PWM group B Bit xxx1 -> Capture channel 0 is from P2 [4] Bit xx1x -> Capture channel 1 is from P2 [5] Bit x1xx -> Capture channel 2 is from P2 [6] Bit 1xxx -> Capture channel 3 is from P2 [7]
0
4
read-write
CCR0
Capture Control Register
0x50
read-write
n
0x0
0x0
CAPCH0EN
Capture Channel 0 transition Enable/Disable 1 = Enable capture function on PWM group channel 0. 0 = Disable capture function on PWM group channel 0 When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.
3
1
read-write
CAPCH1EN
Capture Channel 1 transition Enable/Disable 1 = Enable capture function on PWM group channel 1. 0 = Disable capture function on PWM group channel 1 When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.
19
1
read-write
CAPIF0
Capture0 Interrupt Indication Flag If PWM group channel 0 rising latch interrupt is enabled (CRL_IE0=1), a rising transition occurs at PWM group channel 0 will result in CAPIF0 to high; Similarly, a falling transition will cause CAPIF0 to be set high if PWM group channel 0 falling latch interrupt is enabled (CFL_IE0=1). This flag is clear by software with a write 1 to itself.
4
1
read-write
oneToClear
CAPIF1
Capture1 Interrupt Indication Flag If PWM group channel 1 rising latch interrupt is enabled (CRL_IE1=1), a rising transition occurs at PWM group channel 1 will result in CAPIF1 to high; Similarly, a falling transition will cause CAPIF1 to be set high if PWM group channel 1 falling latch interrupt is enabled (CFL_IE1=1). This flag is clear by software with a write 1 to itself.
20
1
read-write
oneToClear
CFLRI0
CFLR0 Latched Indicator Bit When PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
7
1
read-write
oneToClear
CFLRI1
CFLR1 Latched Indicator Bit When PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
23
1
read-write
oneToClear
CFL_IE0
PWM Group Channel 0 Falling Latch Interrupt Enable ON/OFF 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 0 has falling transition, Capture issues an Interrupt.
2
1
read-write
CFL_IE1
PWM Group Channel 1 Falling Latch Interrupt Enable ON/OFF 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 1 has falling transition, Capture issues an Interrupt.
18
1
read-write
CRLRI0
CRLR0 Latched Indicator Bit When PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
6
1
read-write
oneToClear
CRLRI1
CRLR1 Latched Indicator Bit When PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
22
1
read-write
oneToClear
CRL_IE0
PWM Group Channel 0 Rising Latch Interrupt Enable ON/OFF 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 0 has rising transition, Capture issues an Interrupt.
1
1
read-write
CRL_IE1
PWM Group Channel 1 Rising Latch Interrupt Enable ON/OFF 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 1 has rising transition, Capture issues an Interrupt.
17
1
read-write
INV0
PWM Group Channel 0 Inverter ON/OFF 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter OFF
0
1
read-write
INV1
PWM Group Channel 1 Inverter ON/OFF 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter OFF
16
1
read-write
CCR2
Capture Control Register
0x54
read-write
n
0x0
0x0
CAPCH2EN
Capture Channel 2 transition Enable/Disable 1 = Enable capture function on PWM group channel 2. 0 = Disable capture function on PWM group channel 2 When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.
3
1
read-write
CAPCH3EN
Capture Channel 3 transition Enable/Disable 1 = Enable capture function on PWM group channel 3. 0 = Disable capture function on PWM group channel 3 When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.
19
1
read-write
CAPIF2
Capture2 Interrupt Indication Flag If PWM group channel 2 rising latch interrupt is enabled (CRL_IE2=1), a rising transition occurs at PWM group channel 2 will result in CAPIF2 to high; Similarly, a falling transition will cause CAPIF2 to be set high if PWM group channel 2 falling latch interrupt is enabled (CFL_IE2=1). This flag is clear by software with a write 1 to itself.
4
1
read-write
oneToClear
CAPIF3
Capture3 Interrupt Indication Flag If PWM group channel 3 rising latch interrupt is enabled (CRL_IE3=1), a rising transition occurs at PWM group channel 3 will result in CAPIF3 to high; Similarly, a falling transition will cause CAPIF3 to be set high if PWM group channel 3 falling latch interrupt is enabled (CFL_IE3=1). This flag is clear by software with a write 1 to itself.
20
1
read-write
oneToClear
CFLRI2
CFLR2 Latched Indicator Bit When PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
7
1
read-write
oneToClear
CFLRI3
CFLR3 Latched Indicator Bit When PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
23
1
read-write
oneToClear
CFL_IE2
PWM Group Channel 2 Falling Latch Interrupt Enable ON/OFF 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 2 has falling transition, Capture issues an Interrupt.
2
1
read-write
CFL_IE3
PWM Group Channel 3 Falling Latch Interrupt Enable ON/OFF 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 3 has falling transition, Capture issues an Interrupt.
18
1
read-write
CRLRI2
CRLR2 Latched Indicator Bit When PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
6
1
read-write
oneToClear
CRLRI3
CRLR3 Latched Indicator Bit When PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware. Clear this bit by writing a one to it.
22
1
read-write
oneToClear
CRL_IE2
PWM Group Channel 2 Rising Latch Interrupt Enable ON/OFF 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 2 has rising transition, Capture issues an Interrupt.
1
1
read-write
CRL_IE3
PWM Group Channel 3 Rising Latch Interrupt Enable ON/OFF 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 3 has rising transition, Capture issues an Interrupt.
17
1
read-write
INV2
PWM Group Channel 2 Inverter ON/OFF 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter OFF
0
1
read-write
INV3
PWM Group Channel 3 Inverter ON/OFF 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter OFF
16
1
read-write
CFLR0
Capture Falling Latch Register (Channel 0)
0x5C
read-only
n
0x0
0x0
CFLR
Capture Falling Latch Register Latch the PWM counter when Channel 01/2/3 has Falling transition.
0
16
read-only
CFLR1
Capture Falling Latch Register (Channel 1)
0x64
read-only
n
0x0
0x0
CFLR
Capture Falling Latch Register Latch the PWM counter when Channel 01/2/3 has Falling transition.
0
16
read-only
CFLR2
Capture Falling Latch Register (channel 2)
0x6C
read-only
n
0x0
0x0
CFLR
Capture Falling Latch Register Latch the PWM counter when Channel 0/1/2/3 has Falling transition.
0
16
read-only
CFLR3
Capture Falling Latch Register (channel 3)
0x74
read-only
n
0x0
0x0
CFLR
Capture Falling Latch Register Latch the PWM counter when Channel 0/1/2/3 has Falling transition.
0
16
read-only
CMR0
PWM Comparator Register 0
0x10
read-write
n
0x0
0x0
CMR
PWM Comparator Register CNR determines the PWM duty. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CMR1
PWM Comparator Register 1
0x1C
read-write
n
0x0
0x0
CMR
PWM Comparator Register CNR determines the PWM duty. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CMR2
PWM Comparator Register 2
0x28
read-write
n
0x0
0x0
CMR
PWM Comparator Register CNR determines the PWM duty. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CMR3
PWM Comparator Register 3
0x34
read-write
n
0x0
0x0
CMR
PWM Comparator Register CNR determines the PWM duty. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CNR0
PWM Counter Register 0
0xC
read-write
n
0x0
0x0
CNR
PWM Counter/Timer Loaded Value CNR determines the PWM period. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CNR1
PWM Counter Register 1
0x18
read-write
n
0x0
0x0
CNR
PWM Counter/Timer Loaded Value CNR determines the PWM period. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CNR2
PWM Counter Register 2
0x24
read-write
n
0x0
0x0
CNR
PWM Counter/Timer Loaded Value CNR determines the PWM period. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CNR3
PWM Counter Register 3
0x30
read-write
n
0x0
0x0
CNR
PWM Counter/Timer Loaded Value CNR determines the PWM period. PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CRLR0
Capture Rising Latch Register (Channel 0)
0x58
read-only
n
0x0
0x0
CRLR
Capture Rising Latch Register Latch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CRLR1
Capture Rising Latch Register (Channel 1)
0x60
read-only
n
0x0
0x0
CRLR
Capture Rising Latch Register Latch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CRLR2
Capture Rising Latch Register (channel 2)
0x68
read-only
n
0x0
0x0
CRLR
Capture Rising Latch Register Latch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CRLR3
Capture Rising Latch Register (channel 3)
0x70
read-only
n
0x0
0x0
CRLR
Capture Rising Latch Register Latch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CSR
PWM Clock Select Register
0x4
read-write
n
0x0
0x0
CSR0
Timer 0 Clock Source Selection(PWM timer 0 for group A and PWM timer 4 for group B) Select clock input for timer. (Table is the same as CSR3)
0
3
read-write
CSR1
Timer 1 Clock Source Selection(PWM timer 1 for group A and PWM timer 5 for group B) Select clock input for timer. (Table is the same as CSR3)
4
3
read-write
CSR2
Timer 2 Clock Source Selection(PWM timer 2 for group A and PWM timer 6 for group B) Select clock input for timer. (Table is the same as CSR3)
8
3
read-write
CSR3
Timer 3 Clock Source Selection (PWM timer 3 for group A and PWM timer 7 for group B) Select clock input for timer. CSR3 [14:12] Input clock divided by 100 1 011 16 010 8 001 4 000 2
12
3
read-write
PCR
PWM Control Register
0x8
read-write
n
0x0
0x0
CH0EN
PWM-Timer 0 Enable/Disable Start Run (PWM timer 0 for group A and PWM timer 4 for group B) 1 = Enable corresponding PWM-Timer Start Run 0 = Stop corresponding PWM-Timer Running
0
1
read-write
CH0INV
PWM-Timer 0 Output Inverter ON/OFF(PWM timer 0 for group A and PWM timer 4 for group B) 1 = Inverter ON 0 = Inverter OFF
2
1
read-write
CH0MOD
PWM-Timer 0 Auto-reload/One-Shot Mode(PWM timer 0 for group A and PWM timer 4 for group B) 1 = Auto-reload Mode 0 = One-Shot Mode Note: If there is a rising transition at this bit, it will cause CNR0 and CMR0 be clear.
3
1
read-write
CH1EN
PWM-Timer 1 Enable/Disable Start Run (PWM timer 1 for group A and PWM timer 5 for group B) 1 = Enable corresponding PWM-Timer Start Run 0 = Stop corresponding PWM-Timer Running
8
1
read-write
CH1INV
PWM-Timer 1 Output Inverter ON/OFF(PWM timer 1 for group A and PWM timer 5 for group B) 1 = Inverter ON 0 = Inverter OFF
10
1
read-write
CH1MOD
PWM-Timer 1 Auto-reload/One-Shot Mode(PWM timer 1 for group A and PWM timer 5 for group B) 1 = Auto-reload Mode 0 = One-Shot Mode Note: If there is a rising transition at this bit, it will cause CNR1 and CMR1 be clear.
11
1
read-write
CH2EN
PWM-Timer 2 Enable/Disable Start Run (PWM timer 2 for group A and PWM timer 6 for group B) 1 = Enable corresponding PWM-Timer Start Run 0 = Stop corresponding PWM-Timer Running
16
1
read-write
CH2INV
PWM-Timer 2 Output Inverter ON/OFF(PWM timer 2 for group A and PWM timer 6 for group B) 1 = Inverter ON 0 = Inverter OFF
18
1
read-write
CH2MOD
PWM-Timer 2 Auto-reload/One-Shot Mode(PWM timer 2 for group A and PWM timer 6 for group B) 1 = Auto-reload Mode 0 = One-Shot Mode Note: If there is a rising transition at this bit, it will cause CNR2 and CMR2 be clear.
19
1
read-write
CH3EN
PWM-Timer 3 Enable/Disable Start Run (PWM timer 3 for group A and PWM timer 7 for group B) 1 = Enable corresponding PWM-Timer Start Run 0 = Stop corresponding PWM-Timer Running
24
1
read-write
CH3INV
PWM-Timer 3 Output Inverter ON/OFF(PWM timer 3 for group A and PWM timer 7 for group B) 1 = Inverter ON 0 = Inverter OFF
26
1
read-write
CH3MOD
PWM-Timer 3 Auto-reload/One-Shot Mode(PWM timer 3 for group A and PWM timer 7 for group B) 1 = Auto-reload Mode 0 = One-Shot Mode Note: If there is a rising transition at this bit, it will cause CNR3 and CMR3 be clear.
27
1
read-write
DZEN01
Dead-Zone 0 Generator Enable/Disable(PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B) 1 = Enable 0 = Disable Note: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B.
4
1
read-write
DZEN23
Dead-Zone 2 Generator Enable/Disable(PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B) 1 = Enable 0 = Disable Note: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B.
5
1
read-write
PDR0
PWM Data Register 0
0x14
read-only
n
0x0
0x0
PDR
PWM Data Register User can monitor PDR to know the current value in 16-bit down counter.
0
16
read-only
PDR1
PWM Data Register 1
0x20
read-only
n
0x0
0x0
PDR
PWM Data Register User can monitor PDR to know the current value in 16-bit down counter.
0
16
read-only
PDR2
PWM Data Register 2
0x2C
read-only
n
0x0
0x0
PDR
PWM Data Register User can monitor PDR to know the current value in 16-bit down counter.
0
16
read-only
PDR3
PWM Data Register 3
0x38
read-only
n
0x0
0x0
PDR
PWM Data Register User can monitor PDR to know the current value in 16-bit down counter.
0
16
read-only
PIER
PWM Interrupt Enable Register
0x40
read-write
n
0x0
0x0
PWMIE0
PWM channel 0 Interrupt Enable 1 = Enable 0 = Disable
0
1
read-write
PWMIE1
PWM channel 1 Interrupt Enable 1 = Enable 0 = Disable
1
1
read-write
PWMIE2
PWM channel 2 Interrupt Enable 1 = Enable 0 = Disable
2
1
read-write
PWMIE3
PWM channel 3 Interrupt Enable 1 = Enable 0 = Disable
3
1
read-write
PIIR
PWM Interrupt Indication Register
0x44
read-write
n
0x0
0x0
PWMIF0
PWM channel 0 Interrupt Status Flag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing a one to it.
0
1
read-write
oneToClear
PWMIF1
PWM channel 1 Interrupt Status Flag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing a one to it.
1
1
read-write
oneToClear
PWMIF2
PWM channel 2 Interrupt Status Flag is set by hardware when PWM2 down counter reaches zero, software can clear this bit by writing a one to it.
2
1
read-write
oneToClear
PWMIF3
PWM channel 3 Interrupt Status Flag is set by hardware when PWM3 down counter reaches zero, software can clear this bit by writing a one to it.
3
1
read-write
oneToClear
POE
PWM Output Enable
0x7C
read-write
n
0x0
0x0
PWM0
PWM Channel 0 Output Enable Register 1 = Enable PWM channel 0 output to pin. 0 = Disable PWM channel 0 output to pin. Note: The corresponding GPIO pin also must be switched to PWM function.
0
1
read-write
PWM1
PWM Channel 1 Output Enable Register 1 = Enable PWM channel 1 output to pin. 0 = Disable PWM channel 1 output to pin. Note: The corresponding GPIO pin also must be switched to PWM function.
1
1
read-write
PWM2
PWM Channel 2 Output Enable Register 1 = Enable PWM channel 2 output to pin. 0 = Disable PWM channel 2 output to pin. Note: The corresponding GPIO pin also must be switched to PWM function.
2
1
read-write
PWM3
PWM Channel 3 Output Enable Register 1 = Enable PWM channel 3 output to pin. 0 = Disable PWM channel 3 output to pin. Note: The corresponding GPIO pin also must be switched to PWM function.
3
1
read-write
PPR
PWM Pre-scalar Register
0x0
read-write
n
0x0
0x0
CP01
Clock pre-scalar 0(PWM counter 0 & 1 for group A and PWM counter 4 & 5 for group B) Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter If CP01=0, then the pre-scalar 0 output clock will be stopped. So corresponding PWM counter will be stopped also.
0
8
read-write
CP23
Clock pre-scalar 2(PWM counter 2 & 3 for group A and PWM counter 6 & 7 for group B) Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter If CP23=0, then the pre-scalar 2 output clock will be stopped. So corresponding PWM counter will be stopped also.
8
8
read-write
DZI01
Dead zone interval register for pair of channel 0 and channel 1(PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B) These 8 bits determine dead zone length. The unit time of dead zone length is received from corresponding CSR bits.
16
8
read-write
DZI23
Dead zone interval register for pair of channel 2 and channel 3(PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B) These 8 bits determine dead zone length. The unit time of dead zone length is received from corresponding CSR bits.
24
8
read-write
SCS
Registers group
SCS
0x0
0x10
0xC
registers
n
0x100
0x4
registers
n
0x180
0x4
registers
n
0x200
0x4
registers
n
0x280
0x4
registers
n
0x400
0x20
registers
n
0xD00
0x8
registers
n
0xD0C
0x8
registers
n
0xD1C
0x8
registers
n
AIRCR
Application Interrupt and Reset Control Register
0xD0C
read-write
n
0x0
0x0
SYSRESETREQ
Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested. The bit is a write only bit and self-clears as part of the reset sequence.
2
1
write-only
modify
VECTCLRACTIVE
Set this bit to 1 will clears all active state information for fixed and configurable exceptions. The bit is a write only bit and can only be written when the core is halted. Note: It is the debugger's responsibility to re-initialize the stack.
1
1
write-only
modify
VECTORKEY
When write this register, this field should be 0x05FA, otherwise the write action will be unpredictable.
16
16
read-write
CPUID
CPUID Base Register
0xD00
read-only
n
0x0
0x0
IMPLEMENTER
Implementer code assigned by ARM. ( ARM = 0x41)
24
8
read-only
PART
Reads as 0xC for ARMv6-M parts
16
4
read-only
PARTNO
Reads as 0xC20.
4
12
read-only
REVISION
Reads as 0x0
0
4
read-only
ICSR
Interrupt Control State Register
0xD04
read-write
n
0x0
0x0
ISRPENDING
Indicates if an external configurable (NVIC generated) interrupt is pending.
22
1
read-only
ISRPREEMPT
If set, a pending exception will be serviced on exit from the debug halt state.
23
1
read-only
NMIPENDSET
Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not).
31
1
read-write
PENDSTCLR
Write 1 to clear a pending SysTick.
25
1
write-only
PENDSTSET
Set a pending SysTick. Reads back with current state (1 if Pending, 0 if not).
26
1
read-write
PENDSVCLR
Write 1 to clear a pending PendSV interrupt.
27
1
write-only
PENDSVSET
Set a pending PendSV interrupt. This is normally used to request a context switch. Reads back with current state (1 if Pending, 0 if not).
28
1
read-write
VECTACTIVE
0 = Thread mode value > 1: the exception number for the current executing exception.
0
9
read-only
VECTPENDING
Indicates the exception number for the highest priority pending exception. The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A value of zero indicates no pending exceptions.
12
9
read-only
NVIC_ICER
IRQ0 ~ IRQ31 Clear-Enable Control Register
0x180
read-write
n
0x0
0x0
CLRENA
Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 1 will disable the associated interrupt. Writing 0 has no effect. The register reads back with the current enable state.
0
32
read-write
oneToClear
NVIC_ICPR
IRQ0 ~ IRQ31 Clear-Pending Control Register
0x280
read-write
n
0x0
0x0
CLRPEND
Writing 1 to a bit un-pends the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 0 has no effect. The register reads back with the current pending state.
0
32
read-write
oneToClear
NVIC_IPR0
IRQ0 ~ IRQ3 Priority Control Register
0x400
read-write
n
0x0
0x0
PRI_0
Priority of IRQ0 "0" denotes the highest priority & "3" denotes lowest priority
6
2
read-write
PRI_1
Priority of IRQ1 "0" denotes the highest priority & "3" denotes lowest priority
14
2
read-write
PRI_2
Priority of IRQ2 "0" denotes the highest priority & "3" denotes lowest priority
22
2
read-write
PRI_3
Priority of IRQ3 "0" denotes the highest priority & "3" denotes lowest priority
30
2
read-write
NVIC_IPR1
IRQ4 ~ IRQ7 Priority Control Register
0x404
read-write
n
0x0
0x0
PRI_4
Priority of IRQ4 "0" denotes the highest priority & "3" denotes lowest priority
6
2
read-write
PRI_5
Priority of IRQ5 "0" denotes the highest priority & "3" denotes lowest priority
14
2
read-write
PRI_6
Priority of IRQ6 "0" denotes the highest priority & "3" denotes lowest priority
22
2
read-write
PRI_7
Priority of IRQ7 "0" denotes the highest priority & "3" denotes lowest priority
30
2
read-write
NVIC_IPR2
IRQ8 ~ IRQ11 Priority Control Register
0x408
read-write
n
0x0
0x0
PRI_10
Priority of IRQ10 "0" denotes the highest priority & "3" denotes lowest priority
22
2
read-write
PRI_11
Priority of IRQ11 "0" denotes the highest priority & "3" denotes lowest priority
30
2
read-write
PRI_8
Priority of IRQ8 "0" denotes the highest priority & "3" denotes lowest priority
6
2
read-write
PRI_9
Priority of IRQ9 "0" denotes the highest priority & "3" denotes lowest priority
14
2
read-write
NVIC_IPR3
IRQ12 ~ IRQ15 Priority Control Register
0x40C
read-write
n
0x0
0x0
PRI_12
Priority of IRQ12 "0" denotes the highest priority & "3" denotes lowest priority
6
2
read-write
PRI_13
Priority of IRQ13 "0" denotes the highest priority & "3" denotes lowest priority
14
2
read-write
PRI_14
Priority of IRQ14 "0" denotes the highest priority & "3" denotes lowest priority
22
2
read-write
PRI_15
Priority of IRQ15 "0" denotes the highest priority & "3" denotes lowest priority
30
2
read-write
NVIC_IPR4
IRQ16 ~ IRQ19 Priority Control Register
0x410
read-write
n
0x0
0x0
PRI_16
Priority of IRQ16 "0" denotes the highest priority & "3" denotes lowest priority
6
2
read-write
PRI_17
Priority of IRQ17 "0" denotes the highest priority & "3" denotes lowest priority
14
2
read-write
PRI_18
Priority of IRQ18 "0" denotes the highest priority & "3" denotes lowest priority
22
2
read-write
PRI_19
Priority of IRQ19 "0" denotes the highest priority & "3" denotes lowest priority
30
2
read-write
NVIC_IPR5
IRQ20 ~ IRQ23 Priority Control Register
0x414
read-write
n
0x0
0x0
PRI_20
Priority of IRQ20 "0" denotes the highest priority & "3" denotes lowest priority
6
2
read-write
PRI_21
Priority of IRQ21 "0" denotes the highest priority & "3" denotes lowest priority
14
2
read-write
PRI_22
Priority of IRQ22 "0" denotes the highest priority & "3" denotes lowest priority
22
2
read-write
PRI_23
Priority of IRQ23 "0" denotes the highest priority & "3" denotes lowest priority
30
2
read-write
NVIC_IPR6
IRQ24 ~ IRQ27 Priority Control Register
0x418
read-write
n
0x0
0x0
PRI_24
Priority of IRQ24 "0" denotes the highest priority & "3" denotes lowest priority
6
2
read-write
PRI_25
Priority of IRQ25 "0" denotes the highest priority & "3" denotes lowest priority
14
2
read-write
PRI_26
Priority of IRQ26 "0" denotes the highest priority & "3" denotes lowest priority
22
2
read-write
PRI_27
Priority of IRQ27 "0" denotes the highest priority & "3" denotes lowest priority
30
2
read-write
NVIC_IPR7
IRQ28 ~ IRQ31 Priority Control Register
0x41C
read-write
n
0x0
0x0
PRI_28
Priority of IRQ28 "0" denotes the highest priority & "3" denotes lowest priority
6
2
read-write
PRI_29
Priority of IRQ29 "0" denotes the highest priority & "3" denotes lowest priority
14
2
read-write
PRI_30
Priority of IRQ30 "0" denotes the highest priority & "3" denotes lowest priority
22
2
read-write
PRI_31
Priority of IRQ31 "0" denotes the highest priority & "3" denotes lowest priority
30
2
read-write
NVIC_ISER
IRQ0 ~ IRQ31 Set-Enable Control Register
0x100
read-write
n
0x0
0x0
SETENA
Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 1 will enable the associated interrupt. Writing 0 has no effect. The register reads back with the current enable state.
0
32
read-write
oneToSet
NVIC_ISPR
IRQ0 ~ IRQ31 Set-Pending Control Register
0x200
read-write
n
0x0
0x0
SETPEND
Writing 1 to a bit pends the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 0 has no effect. The register reads back with the current pending state.
0
32
read-write
oneToSet
SCR
System Control Register
0xD10
read-write
n
0x0
0x0
SEVONPEND
When enabled, interrupt transitions from Inactive to Pending are included in the list of wakeup events for the WFE instruction.
4
1
read-write
SLEEPDEEP
A qualifying hint that indicates waking from sleep might take longer.
2
1
read-write
SLEEPONEXIT
When set to 1, the core can enter a sleep state on an exception return to Thread mode. This is the mode and exception level entered at reset, the base level of execution.
1
1
read-write
SHPR2
System Handler Priority Register 2
0xD1C
read-write
n
0x0
0x0
PRI_11
Priority of system handler 11 - SVCall "0" denotes the highest priority & "3" denotes lowest priority
30
2
read-write
SHPR3
System Handler Priority Register 3
0xD20
read-write
n
0x0
0x0
PRI_14
Priority of system handler 14 - PendSV "0" denotes the highest priority & "3" denotes lowest priority
22
2
read-write
PRI_15
Priority of system handler 15 - SysTick "0" denotes the highest priority & "3" denotes lowest priority
30
2
read-write
SYST_CSR
SysTick Control and Status Register
0x10
read-write
n
0x0
0x0
CLKSRC
1 = Core clock used for SysTick. 0 = Clock source is optional, refer to STCLK_S.
2
1
read-write
COUNTFLAG
Returns 1 if timer counted to 0 since last time this register was read. COUNTFLAG is set by a count transition from 1 to 0. COUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-only
modify
ENABLE
1 = The counter will operate in a multi-shot manner. 0 = The counter is disabled
0
1
read-write
TICKINT
1 = Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended. 0 = Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred.
1
1
read-write
SYST_CVR
SysTick Current value Register
0x18
read-write
n
0x0
0x0
CURRENT
Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value register).
0
24
read-write
modify
SYST_RVR
SysTick Reload value Register
0x14
read-write
n
0x0
0x0
RELOAD
Value to load into the Current Value register when the counter reaches 0.
0
24
read-write
SPI0
Registers group
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x4
registers
n
SPI_CNTRL
Control and Status Register
0x0
read-write
n
0x0
0x0
CLKP
Clock Polarity 1 = SPICLK idle high. 0 = SPICLK idle low.
11
1
read-write
GO_BUSY
Go and Busy Status 1 = In master mode, writing 1 to this bit to start the SPI data transfer; in slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master. 0 = Writing 0 to this bit to stop data transfer if SPI is transferring. During the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. NOTE: All registers should be set before writing 1 to this GO_BUSY bit. The transfer result will be unpredictable if software changes related settings when GO_BUSY bit is 1.
0
1
read-write
modify
IE
Interrupt Enable 1 = Enable MICROWIRE/SPI Interrupt. 0 = Disable MICROWIRE/SPI Interrupt.
17
1
read-write
IF
Interrupt Flag 1 = It indicates that the transfer is done. The interrupt flag is set if it was enable. 0 = It indicates that the transfer does not finish yet. NOTE: This bit can be cleared by writing 1 to itself.
16
1
read-write
oneToClear
LSB
LSB First 1 = The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1). 0 = The MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the TX_BIT_LEN field).
10
1
read-write
REORDER
Reorder Mode Select 00 = Disable both byte reorder and byte suspend functions. 01 = Enable byte reorder function and insert a byte suspend interval (2~17 SPICLK cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word). 10 = Enable byte reorder function, but disable byte suspend function. 11 = Disable byte reorder function, but insert a suspend interval (2~17 SPICLK cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word). Byte reorder function is only available if TX_BIT_LEN is defined as 16, 24 and 32.
19
2
read-write
RX_NEG
Receive At Negative Edge 1 = The received data input signal is latched at the falling edge of SPICLK. 0 = The received data input signal is latched at the rising edge of SPICLK.
1
1
read-write
SLAVE
SLAVE Mode Indication 1 = Slave mode. 0 = Master mode.
18
1
read-write
SP_CYCLE
Suspend Interval (master only) These four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKP = 0. If CLKP = 1, the interval is from the rising clock edge to the falling clock edge. The default value is 0x0. When TX_NUM = 00b, setting this field has no effect on transfer. The desired suspend interval is obtained according to the following equation: (SP_CYCLE[3:0] + 2)*period of SPI clock SP_CYCLE = 0x0 ... 2 SPICLK clock cycle SP_CYCLE = 0x1 ... 3 SPICLK clock cycle ...... SP_CYCLE = 0xe ... 16 SPICLK clock cycle SP_CYCLE = 0xf ... 17 SPICLK clock cycle
12
4
read-write
TX_BIT_LEN
Transmit Bit Length This field specifies how many bits are transmitted in one transaction. Up to 32 bits can be transmitted. TX_BIT_LEN = 0x01 ... 1 bit TX_BIT_LEN = 0x02 ... 2 bits ...... TX_BIT_LEN = 0x1f ... 31 bits TX_BIT_LEN = 0x00 .. 32 bits
3
5
read-write
TX_NEG
Transmit At Negative Edge 1 = The transmitted data output signal is changed at the falling edge of SPICLK. 0 = The transmitted data output signal is changed at the rising edge of SPICLK.
2
1
read-write
TX_NUM
Numbers of Transmit/Receive Word This field specifies how many transmit/receive word numbers should be executed in one transfer. 00 = Only one transmit/receive word will be executed in one transfer. 01 = Two successive transmit/receive words will be executed in one transfer. (burst mode) 10 = Reserved. 11 = Reserved.
8
2
read-write
VARCLK_EN
Variable Clock Enable (master only) 1 = The serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2. 0 = The serial clock output frequency is fixed and decided only by the value of DIVIDER. Note that when enable this VARCLK_EN bit, the setting of TX_BIT_LEN must be programmed as 0x10 (16 bits mode)
23
1
read-write
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register (master only) The value in this field is the frequency divider of the system clock, PCLK, to generate the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation: fsclk = fpclk / ((DIVIDER+1)*2) In slave mode, the period of SPI clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK.
0
16
read-write
DIVIDER2
Clock Divider 2 Register (master only) The value in this field is the 2nd frequency divider of the system clock, PCLK, to generate the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation: fsclk = fpclk / ((DIVIDER2+1)*2)
16
16
read-write
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer. The number of valid bits depend on the transmit bit length field in the SPI_CNTRL register. For example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. NOTE: The Data Receive Registers are read only registers.
0
32
read-only
SPI_RX1
Data Receive Register 1
0x14
read-only
n
0x0
0x0
RX
Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer. The number of valid bits depend on the transmit bit length field in the SPI_CNTRL register. For example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. NOTE: The Data Receive Registers are read only registers.
0
32
read-only
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select (master only) 1 = If this bit is set, SPISSx signal is generated automatically. It means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and is de-asserted after each transmit/receive is finished. 0 = If this bit is cleared, slave select signal will be asserted and de-asserted by setting and clearing SSR[0].
3
1
read-write
LTRIG_FLAG
Level Trigger Flag When the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not. 1 = The transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN. 0 = The transaction number or the transferred bit length of one transaction doesn't meet the specified requirements. Note: This bit is READ only
5
1
read-only
SSR
Slave Select Register (master only) If AUTOSS bit is cleared, writing 1 to this bit sets the SPISSx line to active state and writing 0 sets the line back to inactive state. If AUTOSS bit is set, writing 1 to this bit will select the SPISSx line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active level of SPISSx0/1 is specified in SS_LVL).
0
1
read-write
SS_LTRIG
Slave Select Level Trigger (slave only) 1: The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high. 0: The input slave select signal is edge-trigger. This is default value.
4
1
read-write
SS_LVL
Slave Select Active Level It defines the active level of slave select signal (SPISSx). 1 = The slave select signal SPISSx is active at high-level/rising-edge. 0 = The slave select signal SPISSx is active at low-level/falling-edge.
2
1
read-write
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depend on the transmit bit length field in the CNTRL register. For example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the core will perform two successive 32-bit transmit/receive using the same setting (the order is TX0[31:0], TX1[31:0]).
0
32
write-only
SPI_TX1
Data Transmit Register 1
0x24
write-only
n
0x0
0x0
TX
Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depend on the transmit bit length field in the CNTRL register. For example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the core will perform two successive 32-bit transmit/receive using the same setting (the order is TX0[31:0], TX1[31:0]).
0
32
write-only
SPI_VARCLK
Variable Clock Pattern Register
0x34
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern The value in this field is the frequency patterns of the SPI clock. If the bit patterns of VARCLK are 0, the output frequency of SPICLK is according the value of DIVIDER. If the bit patterns of VARCLK are 1, the output frequency of SPICLK is according the value of DIVIDER2. Refer to register SPI_DIVIDER.
0
32
read-write
SPI1
Registers group
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x4
registers
n
SPI_CNTRL
Control and Status Register
0x0
read-write
n
0x0
0x0
CLKP
Clock Polarity 1 = SPICLK idle high. 0 = SPICLK idle low.
11
1
read-write
GO_BUSY
Go and Busy Status 1 = In master mode, writing 1 to this bit to start the SPI data transfer; in slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master. 0 = Writing 0 to this bit to stop data transfer if SPI is transferring. During the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. NOTE: All registers should be set before writing 1 to this GO_BUSY bit. The transfer result will be unpredictable if software changes related settings when GO_BUSY bit is 1.
0
1
read-write
modify
IE
Interrupt Enable 1 = Enable MICROWIRE/SPI Interrupt. 0 = Disable MICROWIRE/SPI Interrupt.
17
1
read-write
IF
Interrupt Flag 1 = It indicates that the transfer is done. The interrupt flag is set if it was enable. 0 = It indicates that the transfer does not finish yet. NOTE: This bit can be cleared by writing 1 to itself.
16
1
read-write
oneToClear
LSB
LSB First 1 = The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1). 0 = The MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the TX_BIT_LEN field).
10
1
read-write
REORDER
Reorder Mode Select 00 = Disable both byte reorder and byte suspend functions. 01 = Enable byte reorder function and insert a byte suspend interval (2~17 SPICLK cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word). 10 = Enable byte reorder function, but disable byte suspend function. 11 = Disable byte reorder function, but insert a suspend interval (2~17 SPICLK cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word). Byte reorder function is only available if TX_BIT_LEN is defined as 16, 24 and 32.
19
2
read-write
RX_NEG
Receive At Negative Edge 1 = The received data input signal is latched at the falling edge of SPICLK. 0 = The received data input signal is latched at the rising edge of SPICLK.
1
1
read-write
SLAVE
SLAVE Mode Indication 1 = Slave mode. 0 = Master mode.
18
1
read-write
SP_CYCLE
Suspend Interval (master only) These four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKP = 0. If CLKP = 1, the interval is from the rising clock edge to the falling clock edge. The default value is 0x0. When TX_NUM = 00b, setting this field has no effect on transfer. The desired suspend interval is obtained according to the following equation: (SP_CYCLE[3:0] + 2)*period of SPI clock SP_CYCLE = 0x0 ... 2 SPICLK clock cycle SP_CYCLE = 0x1 ... 3 SPICLK clock cycle ...... SP_CYCLE = 0xe ... 16 SPICLK clock cycle SP_CYCLE = 0xf ... 17 SPICLK clock cycle
12
4
read-write
TX_BIT_LEN
Transmit Bit Length This field specifies how many bits are transmitted in one transaction. Up to 32 bits can be transmitted. TX_BIT_LEN = 0x01 ... 1 bit TX_BIT_LEN = 0x02 ... 2 bits ...... TX_BIT_LEN = 0x1f ... 31 bits TX_BIT_LEN = 0x00 .. 32 bits
3
5
read-write
TX_NEG
Transmit At Negative Edge 1 = The transmitted data output signal is changed at the falling edge of SPICLK. 0 = The transmitted data output signal is changed at the rising edge of SPICLK.
2
1
read-write
TX_NUM
Numbers of Transmit/Receive Word This field specifies how many transmit/receive word numbers should be executed in one transfer. 00 = Only one transmit/receive word will be executed in one transfer. 01 = Two successive transmit/receive words will be executed in one transfer. (burst mode) 10 = Reserved. 11 = Reserved.
8
2
read-write
VARCLK_EN
Variable Clock Enable (master only) 1 = The serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2. 0 = The serial clock output frequency is fixed and decided only by the value of DIVIDER. Note that when enable this VARCLK_EN bit, the setting of TX_BIT_LEN must be programmed as 0x10 (16 bits mode)
23
1
read-write
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register (master only) The value in this field is the frequency divider of the system clock, PCLK, to generate the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation: fsclk = fpclk / ((DIVIDER+1)*2) In slave mode, the period of SPI clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK.
0
16
read-write
DIVIDER2
Clock Divider 2 Register (master only) The value in this field is the 2nd frequency divider of the system clock, PCLK, to generate the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation: fsclk = fpclk / ((DIVIDER2+1)*2)
16
16
read-write
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer. The number of valid bits depend on the transmit bit length field in the SPI_CNTRL register. For example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. NOTE: The Data Receive Registers are read only registers.
0
32
read-only
SPI_RX1
Data Receive Register 1
0x14
read-only
n
0x0
0x0
RX
Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer. The number of valid bits depend on the transmit bit length field in the SPI_CNTRL register. For example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. NOTE: The Data Receive Registers are read only registers.
0
32
read-only
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select (master only) 1 = If this bit is set, SPISSx signal is generated automatically. It means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and is de-asserted after each transmit/receive is finished. 0 = If this bit is cleared, slave select signal will be asserted and de-asserted by setting and clearing SSR[0].
3
1
read-write
LTRIG_FLAG
Level Trigger Flag When the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not. 1 = The transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN. 0 = The transaction number or the transferred bit length of one transaction doesn't meet the specified requirements. Note: This bit is READ only
5
1
read-only
SSR
Slave Select Register (master only) If AUTOSS bit is cleared, writing 1 to this bit sets the SPISSx line to active state and writing 0 sets the line back to inactive state. If AUTOSS bit is set, writing 1 to this bit will select the SPISSx line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active level of SPISSx0/1 is specified in SS_LVL).
0
1
read-write
SS_LTRIG
Slave Select Level Trigger (slave only) 1: The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high. 0: The input slave select signal is edge-trigger. This is default value.
4
1
read-write
SS_LVL
Slave Select Active Level It defines the active level of slave select signal (SPISSx). 1 = The slave select signal SPISSx is active at high-level/rising-edge. 0 = The slave select signal SPISSx is active at low-level/falling-edge.
2
1
read-write
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depend on the transmit bit length field in the CNTRL register. For example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the core will perform two successive 32-bit transmit/receive using the same setting (the order is TX0[31:0], TX1[31:0]).
0
32
write-only
SPI_TX1
Data Transmit Register 1
0x24
write-only
n
0x0
0x0
TX
Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depend on the transmit bit length field in the CNTRL register. For example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the core will perform two successive 32-bit transmit/receive using the same setting (the order is TX0[31:0], TX1[31:0]).
0
32
write-only
SPI_VARCLK
Variable Clock Pattern Register
0x34
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern The value in this field is the frequency patterns of the SPI clock. If the bit patterns of VARCLK are 0, the output frequency of SPICLK is according the value of DIVIDER. If the bit patterns of VARCLK are 1, the output frequency of SPICLK is according the value of DIVIDER2. Refer to register SPI_DIVIDER.
0
32
read-write
TMR0
Registers group
TMR
0x0
0x0
0x10
registers
n
TCMPR
Timer0 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value TCMP is a 24-bit compared register. When the internal 24-bit up-timer counts and its value is equal to TCMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TCSR.IE[29]=1. The TCMP value defines the timer counting cycle time. Time out period = (Period of timer clock input) * (8-bit PRESCALE + 1) * (24-bit TCMP) NOTE1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state. NOTE2: No matter CEN is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count.
0
24
read-write
TCSR
Timer0 Control and Status Register
0x0
read-write
n
0x0
0x0
CACT
Timer Active Status Bit (Read only) This bit indicates the up-timer status. 0 = Timer is not active. 1 = Timer is active.
25
1
read-only
CEN
Timer Enable Bit 1 = Starts counting 0 = Stops/Suspends counting Note1: In stop status, and then set CEN to 1 will enables the 24-bit up-timer keeps up counting from the last stop counting value. Note2: This bit is auto-cleared by hardware in one-shot mode (MODE[28:27]=00) when the associated timer interrupt is generated (IE[29]=1).
30
1
read-write
CRST
Timer Reset Bit Set this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0. 0 = No effect. 1 = Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit.
26
1
read-write
IE
Interrupt Enable Bit 1 = Enable timer Interrupt. 0 = Disable timer Interrupt. If timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR.
29
1
read-write
MODE
Timer Operating Mode MODE Timer Operating Mode 00 The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if IE is enabled) and CEN is automatically cleared by hardware. 01 The timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if IE is enabled). 10 The timer is operating in the toggle mode. The interrupt signal is generated periodically (if IE is enabled). And the associated signal (tout) is changing back and forth with 50% duty cycle. 11 Reserved
27
2
read-write
PRESCALE
Pre-scale Counter Clock input is divided by PRESCALE+1 before it is fed to the counter. If PRESCALE=0, then there is no scaling.
0
8
read-write
TDR_EN
Data Load Enable When TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting. 1 = Timer Data Register update enable. 0 = Timer Data Register update disable.
16
1
read-write
TDR
Timer0 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register When TCSR.TDR_EN is set to 1, the internal 24-bit up-timer value will be loaded into TDR. User can read this register for the up-timer value.
0
24
read-only
TISR
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag This bit indicates the interrupt status of Timer. TIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit.
0
1
read-write
oneToClear
TMR1
Registers group
TMR
0x0
0x0
0x10
registers
n
TCMPR
Timer0 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value TCMP is a 24-bit compared register. When the internal 24-bit up-timer counts and its value is equal to TCMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TCSR.IE[29]=1. The TCMP value defines the timer counting cycle time. Time out period = (Period of timer clock input) * (8-bit PRESCALE + 1) * (24-bit TCMP) NOTE1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state. NOTE2: No matter CEN is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count.
0
24
read-write
TCSR
Timer0 Control and Status Register
0x0
read-write
n
0x0
0x0
CACT
Timer Active Status Bit (Read only) This bit indicates the up-timer status. 0 = Timer is not active. 1 = Timer is active.
25
1
read-only
CEN
Timer Enable Bit 1 = Starts counting 0 = Stops/Suspends counting Note1: In stop status, and then set CEN to 1 will enables the 24-bit up-timer keeps up counting from the last stop counting value. Note2: This bit is auto-cleared by hardware in one-shot mode (MODE[28:27]=00) when the associated timer interrupt is generated (IE[29]=1).
30
1
read-write
CRST
Timer Reset Bit Set this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0. 0 = No effect. 1 = Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit.
26
1
read-write
IE
Interrupt Enable Bit 1 = Enable timer Interrupt. 0 = Disable timer Interrupt. If timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR.
29
1
read-write
MODE
Timer Operating Mode MODE Timer Operating Mode 00 The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if IE is enabled) and CEN is automatically cleared by hardware. 01 The timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if IE is enabled). 10 The timer is operating in the toggle mode. The interrupt signal is generated periodically (if IE is enabled). And the associated signal (tout) is changing back and forth with 50% duty cycle. 11 Reserved
27
2
read-write
PRESCALE
Pre-scale Counter Clock input is divided by PRESCALE+1 before it is fed to the counter. If PRESCALE=0, then there is no scaling.
0
8
read-write
TDR_EN
Data Load Enable When TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting. 1 = Timer Data Register update enable. 0 = Timer Data Register update disable.
16
1
read-write
TDR
Timer0 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register When TCSR.TDR_EN is set to 1, the internal 24-bit up-timer value will be loaded into TDR. User can read this register for the up-timer value.
0
24
read-only
TISR
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag This bit indicates the interrupt status of Timer. TIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit.
0
1
read-write
oneToClear
TMR2
Registers group
TMR
0x0
0x0
0x10
registers
n
TCMPR
Timer0 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value TCMP is a 24-bit compared register. When the internal 24-bit up-timer counts and its value is equal to TCMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TCSR.IE[29]=1. The TCMP value defines the timer counting cycle time. Time out period = (Period of timer clock input) * (8-bit PRESCALE + 1) * (24-bit TCMP) NOTE1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state. NOTE2: No matter CEN is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count.
0
24
read-write
TCSR
Timer0 Control and Status Register
0x0
read-write
n
0x0
0x0
CACT
Timer Active Status Bit (Read only) This bit indicates the up-timer status. 0 = Timer is not active. 1 = Timer is active.
25
1
read-only
CEN
Timer Enable Bit 1 = Starts counting 0 = Stops/Suspends counting Note1: In stop status, and then set CEN to 1 will enables the 24-bit up-timer keeps up counting from the last stop counting value. Note2: This bit is auto-cleared by hardware in one-shot mode (MODE[28:27]=00) when the associated timer interrupt is generated (IE[29]=1).
30
1
read-write
CRST
Timer Reset Bit Set this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0. 0 = No effect. 1 = Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit.
26
1
read-write
IE
Interrupt Enable Bit 1 = Enable timer Interrupt. 0 = Disable timer Interrupt. If timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR.
29
1
read-write
MODE
Timer Operating Mode MODE Timer Operating Mode 00 The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if IE is enabled) and CEN is automatically cleared by hardware. 01 The timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if IE is enabled). 10 The timer is operating in the toggle mode. The interrupt signal is generated periodically (if IE is enabled). And the associated signal (tout) is changing back and forth with 50% duty cycle. 11 Reserved
27
2
read-write
PRESCALE
Pre-scale Counter Clock input is divided by PRESCALE+1 before it is fed to the counter. If PRESCALE=0, then there is no scaling.
0
8
read-write
TDR_EN
Data Load Enable When TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting. 1 = Timer Data Register update enable. 0 = Timer Data Register update disable.
16
1
read-write
TDR
Timer0 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register When TCSR.TDR_EN is set to 1, the internal 24-bit up-timer value will be loaded into TDR. User can read this register for the up-timer value.
0
24
read-only
TISR
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag This bit indicates the interrupt status of Timer. TIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit.
0
1
read-write
oneToClear
TMR3
Registers group
TMR
0x0
0x0
0x10
registers
n
TCMPR
Timer0 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value TCMP is a 24-bit compared register. When the internal 24-bit up-timer counts and its value is equal to TCMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TCSR.IE[29]=1. The TCMP value defines the timer counting cycle time. Time out period = (Period of timer clock input) * (8-bit PRESCALE + 1) * (24-bit TCMP) NOTE1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state. NOTE2: No matter CEN is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count.
0
24
read-write
TCSR
Timer0 Control and Status Register
0x0
read-write
n
0x0
0x0
CACT
Timer Active Status Bit (Read only) This bit indicates the up-timer status. 0 = Timer is not active. 1 = Timer is active.
25
1
read-only
CEN
Timer Enable Bit 1 = Starts counting 0 = Stops/Suspends counting Note1: In stop status, and then set CEN to 1 will enables the 24-bit up-timer keeps up counting from the last stop counting value. Note2: This bit is auto-cleared by hardware in one-shot mode (MODE[28:27]=00) when the associated timer interrupt is generated (IE[29]=1).
30
1
read-write
CRST
Timer Reset Bit Set this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0. 0 = No effect. 1 = Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit.
26
1
read-write
IE
Interrupt Enable Bit 1 = Enable timer Interrupt. 0 = Disable timer Interrupt. If timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR.
29
1
read-write
MODE
Timer Operating Mode MODE Timer Operating Mode 00 The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if IE is enabled) and CEN is automatically cleared by hardware. 01 The timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if IE is enabled). 10 The timer is operating in the toggle mode. The interrupt signal is generated periodically (if IE is enabled). And the associated signal (tout) is changing back and forth with 50% duty cycle. 11 Reserved
27
2
read-write
PRESCALE
Pre-scale Counter Clock input is divided by PRESCALE+1 before it is fed to the counter. If PRESCALE=0, then there is no scaling.
0
8
read-write
TDR_EN
Data Load Enable When TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting. 1 = Timer Data Register update enable. 0 = Timer Data Register update disable.
16
1
read-write
TDR
Timer0 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register When TCSR.TDR_EN is set to 1, the internal 24-bit up-timer value will be loaded into TDR. User can read this register for the up-timer value.
0
24
read-only
TISR
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag This bit indicates the interrupt status of Timer. TIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit.
0
1
read-write
oneToClear
UART0
Registers group
UART
0x0
0x0
0x30
registers
n
UA_ACT_CSR
UART0 RS485 Control State Register.
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address match value register This field contains the RS-485 address match values. Note: This field is used for RS-485 auto address detection mode.
24
8
read-write
oneToSet
RS_485_AAD
RS-485 Auto Address Detection Operation Mode (AAD) 1: Enable RS-485 Auto Address Detection Operation Mode (AAD) 0: Disable RS-485 Auto Address Detection Operation Mode (AAD) Note: It can't be active with RS-485_NMM operation mode.
9
1
read-write
oneToSet
RS_485_Add_EN
RS-485 Address Detection Enable This bit is use to enable RS-485 address detection mode. 1: Enable address detection mode 0: Disable address detection mode Note: This field is used for RS-485 any operation mode.
15
1
read-write
oneToSet
RS_485_AUD
RS-485 Auto Direction Mode (AUD) 1: Enable RS-485 Auto Direction Mode (AUD) 0: Disable RS-485 Auto Direction Mode (AUD) Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
oneToSet
RS_485_NMM
RS-485 Normal Multi-drop Operation Mode (NMM) 1: Enable RS-485 Normal Multi-drop Operation Mode (NMM) 0: Disable RS-485 Normal Multi-drop Operation Mode (NMM) Note: It can't be active with RS-485_AAD operation mode.
8
1
read-write
oneToSet
UA_BAUD
UART0 Baud Rate Divisor Register
0x24
read-write
n
0x0
0x0
BRD_HighByte
Baud Rate Divider The high byte of the baud rate divider
8
8
read-write
oneToSet
BRD_LowByte
Baud Rate Divider The low byte of the baud rate divider
0
8
read-write
oneToSet
Divider_X
Divider X The baud rate divider M = X+1.
24
4
read-write
oneToSet
DIV_X_EN
Divider X Enable The BRD = Baud Rate Divider, and the baud rate equation is Baud Rate = Clock / [ M * (BRD + 2) ] ; The default value of M is 16. 0 = Disable divider X (the equation of M = 16) 1 = Enable divider X (the equation of M = X+1, but Divider_X[27:24 must > 8). NOTE: When in IrDA mode, this bit must disable. Mode DIV_X_EN DIV_X_ONE DIVIDER X BRD Baud rate equation 0 Disable 0 B A UART_CLK / [16 * (A+2)] 1 Enable 0 B A UART_CLK/[(B+1)*(A+2)],B must >= 8 2 Enable 1 Don't Care A UART_CLK / (A+2), A must >=3
29
1
read-write
oneToSet
DIV_X_ONE
Divider X equal 1 0 = Divider M = X (the equation of M = X+1, but Divider_X[27:24] must > 8) 1 = Divider M = 1 (the equation of M = 1, but BRD[15:0] must > 3). Mode DIV_X_EN DIV_X_ONE DIVIDER X BRD Baud rate equation 0 Disable 0 B A UART_CLK / [16 * (A+2)] 1 Enable 0 B A UART_CLK/[(B+1)*(A+2)],B must >= 8 2 Enable 1 Don't Care A UART_CLK / (A+2), A must >=3
28
1
read-write
oneToSet
UA_FCR
UART0 FIFO Control Register.
0x8
read-write
n
0x0
0x0
RFITL
Word Length Select RFITL INTR_RDA Tigger Level(Bytes) 0000 01 0001 04 0010 08 0011 14
4
4
read-write
oneToSet
RFR
Rx Software Reset When Rx_RST is set, all the bytes in the transmit FIFO and Rx internal state machine are cleared. 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit will reset the Rx internal state machine and pointers. Note: This bit will auto clear and takes at least 3 UART engine clock cycles.
1
1
read-write
oneToClear
RTS_Tri_Lev
Word Length Select RTS_Tri_Lev Trigger Level(Bytes) 0000 01 0001 04 0010 08 0011 14
16
4
read-write
oneToSet
RX_DIS
Receiver Disable register. The receiver is disabled or not (set 1 is disable receiver) 1: Disable Receiver 0: Enable Receiver Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485 enable function in UA_FUN_SEL. FUN_SEL is programmed.
8
1
read-write
oneToSet
TFR
Tx Software Reset When Tx_RST is set, all the bytes in the transmit FIFO and Tx internal state machine are cleared. 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit will reset the Tx internal state machine and pointers. Note: This bit will auto clear and takes at least 3 UART engine clock cycles.
2
1
read-write
oneToClear
UA_FSR
UART0 FIFO Status Register.
0x18
read-only
n
0x0
0x0
BIF
Break Interrupt Flag This bit is set to a logic 1 whenever the received data input(Rx) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
6
1
read-only
FEF
Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
5
1
read-only
PEF
Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.
4
1
read-only
RS_485_Add_Det
RS-485 Address Byte Detection Flag This bit is set to logic 1 and set UA_RS-485_CSR [RS-485_Add_EN] whenever in RS-485 mode the receiver detect any address byte received address byte character (bit9 = '1') bit", and it is reset whenever the CPU writes 1 to this bit. Note: This field is used for RS-485 mode.
3
1
read-only
Rx_Empty
Receiver FIFO Empty (Read Only) This bit initiate Rx FIFO empty or not. When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
Rx_Full
Receiver FIFO Full (Read Only) This bit initiates Rx FIFO full or not. This bit is set when Rx_Pointer is equal to 16(UART0/UART1), otherwise is cleared by hardware.
15
1
read-only
Rx_Over_IF
Rx overflow Error IF (Read Only) This bit is set when Rx FIFO overflow. If the number of bytes of received data is greater than Rx FIFO(UA_RBR) size, 16 bytes of UART0/UART1, this bit will be set. NOTE: This bit is cleared by writing 1 to itself.
0
1
read-only
Rx_Pointer
Rx FIFO pointer (Read Only) This field indicates the Rx FIFO Buffer Pointer. When UART receives one byte from external device, Rx_Pointer increases one. When one byte of Rx FIFO is read by CPU, Rx_Pointer decreases one.
8
6
read-only
TE_Flag
Transmitter Empty Flag (Read Only) Bit is set by hardware when Tx FIFO(UA_THR) is empty and the STOP bit of the last byte has been transmitted. Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed. NOTE: This bit is read only.
28
1
read-only
Tx_Empty
Transmitter FIFO Empty (Read Only) This bit indicates Tx FIFO empty or not. When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (Tx FIFO not empty).
22
1
read-only
Tx_Full
Transmitter FIFO Full (Read Only) This bit indicates Tx FIFO full or not. This bit is set when Tx_Pointer is equal to 64/16(UART0/UART1), otherwise is cleared by hardware.
23
1
read-only
Tx_Over_IF
Tx Overflow Error Interrupt Flag (Read Only) If Tx FIFO(UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. NOTE: This bit is cleared by writing 1 to itself.
24
1
read-only
Tx_Pointer
TX FIFO Pointer (Read Only) This field indicates the Tx FIFO Buffer Pointer. When CPU write one byte into UA_THR, Tx_Pointer increases one. When one byte of Tx FIFO is transferred to Transmitter Shift Register, Tx_Pointer decreases one.
16
6
read-only
UA_FUN_SEL
UART0 Function Select Register.
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable 00 = UART Function. 01 = Reserved. 10 = Enable IrDA Function. 11 = Enable RS-485 Function.
0
2
read-write
oneToSet
UA_IER
UART0 Interrupt Enable Register.
0x4
read-write
n
0x0
0x0
Auto_CTS_EN
CTS Auto Flow Control Enable 1 = Enable CTS auto flow control. 0 = Disable CTS auto flow control. When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
oneToSet
Auto_RTS_EN
RTS Auto Flow Control Enable 1 = Enable RTS auto flow control. 0 = Disable RTS auto flow control. When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals the UA_FCR [RTS_Tri_Lev], the UART will dessert RTS signal.
12
1
read-write
oneToSet
BUF_ERR_IEN
Buffer Error Interrupt Enable 0 = Mask off INT_Buf_err 1 = Enable INT_Buf_err
5
1
read-write
oneToSet
Modem_IEN
Modem Status Interrupt Enable 0 = Mask off INT_MOS 1 = Enable INT_MOS
3
1
read-write
oneToSet
RDA_IEN
Receive Data Available Interrupt Enable. 0 = Mask off INT_RDA 1 = Enable INT_RDA
0
1
read-write
oneToSet
RLS_IEN
Receive Line Status Interrupt Enable 0 = Mask off INT_RLS 1 = Enable INT_RLS
2
1
read-write
oneToSet
RTO_IEN
Rx Time out Interrupt Enable 0 = Mask off INT_tout 1 = Enable INT_tout
4
1
read-write
oneToSet
THRE_IEN
Transmit Holding Register Empty Interrupt Enable 0 = Mask off INT_THRE 1 = Enable INT_THRE
1
1
read-write
oneToSet
Time_Out_EN
Time-Out Counter Enable 1 = Enable Time-out counter. 0 = Disable Time-out counter.
11
1
read-write
oneToSet
Wake_EN
Wake up CPU function enable 0 = Disable UART wake up CPU function 1 = Enable wake up function, when the system is in deep sleep mode, an external /CTS change will wake up CPU from deep sleep mode.
6
1
read-write
oneToSet
UA_IRCR
UART0 IrDA Control Register.
0x28
read-write
n
0x0
0x0
INV_Rx
INV_Rx 1= Inverse Rx input signal 0= No inversion
6
1
read-write
oneToSet
INV_Tx
INV_Tx 1= Inverse Tx output signal 0= No inversion
5
1
read-write
oneToSet
LB
IrDA loop back mode for self test. 1: Enable IrDA loop back mode 0: Disable IrDA loop back mode
2
1
read-write
oneToSet
Tx_SELECT
Tx_SELECT 1: Enable IrDA transmitter 0: Enable IrDA receiver
1
1
read-write
oneToSet
UA_ISR
UART0 Interrupt Status Register.
0x1C
read-only
n
0x0
0x0
Buf_Err_IF
Buffer Error Interrupt Flag (Read Only) This bit is set when the Tx or Rx FIFO overflows (Tx_Over_IF or Rx_Over_IF is set). When Buf_Err_IF is set, the transfer maybe not correct. If IER[Buf_Err_IEN] is enabled, the buffer error interrupt will be generated. NOTE: This bit is cleared when both Tx_Over_IF and Rx_Over_IF are cleared.
5
1
read-only
Buf_Err_INT
Buffer Error Interrupt Indicator to Interrupt Controller (INT_Buf_err) An AND output with inputs of BUF_ERR_IEN and Buf_Err_IF
13
1
read-only
Modem_IF
MODEM Interrupt Flag (Read Only) This bit is set when the CTS pin has state change (DCTSF=1). If IER[Modem_IEN] is enabled, the Modem interrupt will be generated. NOTE: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
3
1
read-only
Modem_INT
MODEM Status Interrupt Indicator to Interrupt Controller (INT_MOS). An AND output with inputs of Modem_IEN and Modem_IF
11
1
read-only
RDA_IF
Receive Data Available Interrupt Flag (Read Only). When the number of bytes in the Rx FIFO equals the RFITL then the RDA_IF will be set. If IER[RDA_IEN] is enabled, the RDA interrupt will be generated. NOTE: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL).
0
1
read-only
RDA_INT
Receive Data Available Interrupt Indicator to Interrupt Controller (INT_RDA). An AND output with inputs of RDA_IEN and RDA_IF
8
1
read-only
RLS_IF
Receive Line Interrupt Flag (Read Only). In UART mode this bit is set when the Rx receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). In RS-485 mode, the field includes RS-485 Address Byte Detection Flag. If IER[RLS_IEN] is enabled, the RLS interrupt will be generated. NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF, PEF and RS-485_Add_Det are cleared.
2
1
read-only
RLS_INT
Receive Line Status Interrupt Indicator to Interrupt Controller (INT_RLS). An AND output with inputs of RLS_IEN and RLS_IF Note: In RS-485 mode, the field includes RS-485 Address Byte Detection Flag.
10
1
read-only
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only). This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If IER[THRE_IEN] is enabled, the THRE interrupt will be generated. NOTE: This bit is read only and it will be cleared when writing data into THR (Tx FIFO not empty).
1
1
read-only
THRE_INT
Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller (INT_THRE). An AND output with inputs of THRE_IEN and THRE_IF
9
1
read-only
Tout_IF
Time Out Interrupt Flag (Read Only) This bit is set when the Rx FIFO is not empty and no activities occur in the Rx FIFO and the time out counter equal to TOIC. If IER [Tout_IEN] is enabled, the Tout interrupt will be generated. NOTE: This bit is read only and user can read UA_RBR (Rx is in active) to clear it.
4
1
read-only
Tout_INT
Time Out Interrupt Indicator to Interrupt Controller (INT_Tout) An AND output with inputs of RTO_IEN and Tout_IF
12
1
read-only
UA_LCR
UART0 Line Control Register.
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit When this bit is set to logic 1, the serial data output (Tx) is forced to the Spacing State (logic 0). This bit acts only on Tx and has no effect on the transmitter logic.
6
1
read-write
oneToSet
EPE
Even Parity Enable 0 = Odd number of logic 1's are transmitted or checked in the data word and parity bits. 1 = Even number of logic 1's are transmitted or checked in the data word and parity bits. This bit has effect only when bit 3 (parity bit enable) is set.
4
1
read-write
oneToSet
NSB
Number of "STOP bit" 0= One "STOP bit" is generated in the transmitted data 1= One and a half "STOP bit" is generated in the transmitted data when 5-bit word length is selected; Two "STOP bit" is generated when 6-, 7- and 8-bit word length is selected.
2
1
read-write
oneToSet
PBE
Parity Bit Enable 0 = Parity bit is not generated (transmit data) or checked (receive data) during transfer. 1 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
3
1
read-write
oneToSet
SPE
Stick Parity Enable 0 = Disable stick parity 1 = When bits PBE , EPE and SPE are set, the parity bit is transmitted and checked as cleared. When PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as set.
5
1
read-write
oneToSet
WLS
Word Length Select WLS[1:0] Character length 00 5 bits 01 6 bits 10 7 bits 11 8 bits
0
2
read-write
oneToSet
UA_MCR
UART0 Modem Control Register.
0x10
read-write
n
0x0
0x0
Lev_RTS
RTS Trigger Level This bit can change the RTS trigger level. 0= low level triggered 1= high level triggered
9
1
read-write
oneToSet
RTS
RTS (Request-To-Send) Signal 0: Drive RTS pin to logic 1 (If the Lev_RTS set to low level triggered). 1: Drive RTS pin to logic 0 (If the Lev_RTS set to low level triggered). 0: Drive RTS pin to logic 0 (If the Lev_RTS set to high level triggered). 1: Drive RTS pin to logic 1 (If the Lev_RTS set to high level triggered).
1
1
read-write
oneToSet
RTS_St
RTS Pin State This bit is the pin status of RTS.
13
1
read-only
UA_MSR
UART0 Modem Status Register.
0x14
read-write
n
0x0
0x0
CTS_St
CTS Pin Status This bit is the pin status of CTS.
4
1
read-only
DCTSF
Detect CTS State Change Flag This bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when IER [Modem_IEN]. NOTE: This bit is cleared by writing 1 to itself.
0
1
read-only
oneToClear
Lev_CTS
CTS Trigger Level This bit can change the CTS trigger level. 0= low level triggered 1= high level triggered
8
1
read-write
oneToSet
UA_RBR
UART0 Receive Buffer Register.
0x0
read-only
n
0x0
0x0
_8_bitReceivedData
Receive Buffer Register By reading this register, the UART will return an 8-bit data received from Rx pin (LSB first).
0
8
read-only
UA_THR
UART0 Transmit Holding Register.
UA_RBR
0x0
read-write
n
0x0
0x0
_8_bitTransmittedData
Transmit Holding Register By writing to this register, the UART will send out an 8-bit data through the Tx pin (LSB first).
0
8
write-only
UA_TOR
UART0 Time Out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay time value This field is use to programming the transfer delay time between the last stop bit leaving the TX-FIFO and the de-assertion of by setting UA_TOR. DLY register.
8
8
read-write
oneToSet
TOIC
Time Out Interrupt Comparator The time out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (INT_TOUT) is generated if UA_IER [RTO_IEN]. A new incoming data word or RX FIFO empty clears INT_TOUT.
0
7
read-write
UART1
Registers group
UART
0x0
0x0
0x30
registers
n
UA_ACT_CSR
UART0 RS485 Control State Register.
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address match value register This field contains the RS-485 address match values. Note: This field is used for RS-485 auto address detection mode.
24
8
read-write
oneToSet
RS_485_AAD
RS-485 Auto Address Detection Operation Mode (AAD) 1: Enable RS-485 Auto Address Detection Operation Mode (AAD) 0: Disable RS-485 Auto Address Detection Operation Mode (AAD) Note: It can't be active with RS-485_NMM operation mode.
9
1
read-write
oneToSet
RS_485_Add_EN
RS-485 Address Detection Enable This bit is use to enable RS-485 address detection mode. 1: Enable address detection mode 0: Disable address detection mode Note: This field is used for RS-485 any operation mode.
15
1
read-write
oneToSet
RS_485_AUD
RS-485 Auto Direction Mode (AUD) 1: Enable RS-485 Auto Direction Mode (AUD) 0: Disable RS-485 Auto Direction Mode (AUD) Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
oneToSet
RS_485_NMM
RS-485 Normal Multi-drop Operation Mode (NMM) 1: Enable RS-485 Normal Multi-drop Operation Mode (NMM) 0: Disable RS-485 Normal Multi-drop Operation Mode (NMM) Note: It can't be active with RS-485_AAD operation mode.
8
1
read-write
oneToSet
UA_BAUD
UART0 Baud Rate Divisor Register
0x24
read-write
n
0x0
0x0
BRD_HighByte
Baud Rate Divider The high byte of the baud rate divider
8
8
read-write
oneToSet
BRD_LowByte
Baud Rate Divider The low byte of the baud rate divider
0
8
read-write
oneToSet
Divider_X
Divider X The baud rate divider M = X+1.
24
4
read-write
oneToSet
DIV_X_EN
Divider X Enable The BRD = Baud Rate Divider, and the baud rate equation is Baud Rate = Clock / [ M * (BRD + 2) ] ; The default value of M is 16. 0 = Disable divider X (the equation of M = 16) 1 = Enable divider X (the equation of M = X+1, but Divider_X[27:24 must > 8). NOTE: When in IrDA mode, this bit must disable. Mode DIV_X_EN DIV_X_ONE DIVIDER X BRD Baud rate equation 0 Disable 0 B A UART_CLK / [16 * (A+2)] 1 Enable 0 B A UART_CLK/[(B+1)*(A+2)],B must >= 8 2 Enable 1 Don't Care A UART_CLK / (A+2), A must >=3
29
1
read-write
oneToSet
DIV_X_ONE
Divider X equal 1 0 = Divider M = X (the equation of M = X+1, but Divider_X[27:24] must > 8) 1 = Divider M = 1 (the equation of M = 1, but BRD[15:0] must > 3). Mode DIV_X_EN DIV_X_ONE DIVIDER X BRD Baud rate equation 0 Disable 0 B A UART_CLK / [16 * (A+2)] 1 Enable 0 B A UART_CLK/[(B+1)*(A+2)],B must >= 8 2 Enable 1 Don't Care A UART_CLK / (A+2), A must >=3
28
1
read-write
oneToSet
UA_FCR
UART0 FIFO Control Register.
0x8
read-write
n
0x0
0x0
RFITL
Word Length Select RFITL INTR_RDA Tigger Level(Bytes) 0000 01 0001 04 0010 08 0011 14
4
4
read-write
oneToSet
RFR
Rx Software Reset When Rx_RST is set, all the bytes in the transmit FIFO and Rx internal state machine are cleared. 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit will reset the Rx internal state machine and pointers. Note: This bit will auto clear and takes at least 3 UART engine clock cycles.
1
1
read-write
oneToClear
RTS_Tri_Lev
Word Length Select RTS_Tri_Lev Trigger Level(Bytes) 0000 01 0001 04 0010 08 0011 14
16
4
read-write
oneToSet
RX_DIS
Receiver Disable register. The receiver is disabled or not (set 1 is disable receiver) 1: Disable Receiver 0: Enable Receiver Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485 enable function in UA_FUN_SEL. FUN_SEL is programmed.
8
1
read-write
oneToSet
TFR
Tx Software Reset When Tx_RST is set, all the bytes in the transmit FIFO and Tx internal state machine are cleared. 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit will reset the Tx internal state machine and pointers. Note: This bit will auto clear and takes at least 3 UART engine clock cycles.
2
1
read-write
oneToClear
UA_FSR
UART0 FIFO Status Register.
0x18
read-only
n
0x0
0x0
BIF
Break Interrupt Flag This bit is set to a logic 1 whenever the received data input(Rx) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
6
1
read-only
FEF
Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
5
1
read-only
PEF
Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.
4
1
read-only
RS_485_Add_Det
RS-485 Address Byte Detection Flag This bit is set to logic 1 and set UA_RS-485_CSR [RS-485_Add_EN] whenever in RS-485 mode the receiver detect any address byte received address byte character (bit9 = '1') bit", and it is reset whenever the CPU writes 1 to this bit. Note: This field is used for RS-485 mode.
3
1
read-only
Rx_Empty
Receiver FIFO Empty (Read Only) This bit initiate Rx FIFO empty or not. When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
Rx_Full
Receiver FIFO Full (Read Only) This bit initiates Rx FIFO full or not. This bit is set when Rx_Pointer is equal to 16(UART0/UART1), otherwise is cleared by hardware.
15
1
read-only
Rx_Over_IF
Rx overflow Error IF (Read Only) This bit is set when Rx FIFO overflow. If the number of bytes of received data is greater than Rx FIFO(UA_RBR) size, 16 bytes of UART0/UART1, this bit will be set. NOTE: This bit is cleared by writing 1 to itself.
0
1
read-only
Rx_Pointer
Rx FIFO pointer (Read Only) This field indicates the Rx FIFO Buffer Pointer. When UART receives one byte from external device, Rx_Pointer increases one. When one byte of Rx FIFO is read by CPU, Rx_Pointer decreases one.
8
6
read-only
TE_Flag
Transmitter Empty Flag (Read Only) Bit is set by hardware when Tx FIFO(UA_THR) is empty and the STOP bit of the last byte has been transmitted. Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed. NOTE: This bit is read only.
28
1
read-only
Tx_Empty
Transmitter FIFO Empty (Read Only) This bit indicates Tx FIFO empty or not. When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (Tx FIFO not empty).
22
1
read-only
Tx_Full
Transmitter FIFO Full (Read Only) This bit indicates Tx FIFO full or not. This bit is set when Tx_Pointer is equal to 64/16(UART0/UART1), otherwise is cleared by hardware.
23
1
read-only
Tx_Over_IF
Tx Overflow Error Interrupt Flag (Read Only) If Tx FIFO(UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. NOTE: This bit is cleared by writing 1 to itself.
24
1
read-only
Tx_Pointer
TX FIFO Pointer (Read Only) This field indicates the Tx FIFO Buffer Pointer. When CPU write one byte into UA_THR, Tx_Pointer increases one. When one byte of Tx FIFO is transferred to Transmitter Shift Register, Tx_Pointer decreases one.
16
6
read-only
UA_FUN_SEL
UART0 Function Select Register.
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable 00 = UART Function. 01 = Reserved. 10 = Enable IrDA Function. 11 = Enable RS-485 Function.
0
2
read-write
oneToSet
UA_IER
UART0 Interrupt Enable Register.
0x4
read-write
n
0x0
0x0
Auto_CTS_EN
CTS Auto Flow Control Enable 1 = Enable CTS auto flow control. 0 = Disable CTS auto flow control. When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
oneToSet
Auto_RTS_EN
RTS Auto Flow Control Enable 1 = Enable RTS auto flow control. 0 = Disable RTS auto flow control. When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals the UA_FCR [RTS_Tri_Lev], the UART will dessert RTS signal.
12
1
read-write
oneToSet
BUF_ERR_IEN
Buffer Error Interrupt Enable 0 = Mask off INT_Buf_err 1 = Enable INT_Buf_err
5
1
read-write
oneToSet
Modem_IEN
Modem Status Interrupt Enable 0 = Mask off INT_MOS 1 = Enable INT_MOS
3
1
read-write
oneToSet
RDA_IEN
Receive Data Available Interrupt Enable. 0 = Mask off INT_RDA 1 = Enable INT_RDA
0
1
read-write
oneToSet
RLS_IEN
Receive Line Status Interrupt Enable 0 = Mask off INT_RLS 1 = Enable INT_RLS
2
1
read-write
oneToSet
RTO_IEN
Rx Time out Interrupt Enable 0 = Mask off INT_tout 1 = Enable INT_tout
4
1
read-write
oneToSet
THRE_IEN
Transmit Holding Register Empty Interrupt Enable 0 = Mask off INT_THRE 1 = Enable INT_THRE
1
1
read-write
oneToSet
Time_Out_EN
Time-Out Counter Enable 1 = Enable Time-out counter. 0 = Disable Time-out counter.
11
1
read-write
oneToSet
Wake_EN
Wake up CPU function enable 0 = Disable UART wake up CPU function 1 = Enable wake up function, when the system is in deep sleep mode, an external /CTS change will wake up CPU from deep sleep mode.
6
1
read-write
oneToSet
UA_IRCR
UART0 IrDA Control Register.
0x28
read-write
n
0x0
0x0
INV_Rx
INV_Rx 1= Inverse Rx input signal 0= No inversion
6
1
read-write
oneToSet
INV_Tx
INV_Tx 1= Inverse Tx output signal 0= No inversion
5
1
read-write
oneToSet
LB
IrDA loop back mode for self test. 1: Enable IrDA loop back mode 0: Disable IrDA loop back mode
2
1
read-write
oneToSet
Tx_SELECT
Tx_SELECT 1: Enable IrDA transmitter 0: Enable IrDA receiver
1
1
read-write
oneToSet
UA_ISR
UART0 Interrupt Status Register.
0x1C
read-only
n
0x0
0x0
Buf_Err_IF
Buffer Error Interrupt Flag (Read Only) This bit is set when the Tx or Rx FIFO overflows (Tx_Over_IF or Rx_Over_IF is set). When Buf_Err_IF is set, the transfer maybe not correct. If IER[Buf_Err_IEN] is enabled, the buffer error interrupt will be generated. NOTE: This bit is cleared when both Tx_Over_IF and Rx_Over_IF are cleared.
5
1
read-only
Buf_Err_INT
Buffer Error Interrupt Indicator to Interrupt Controller (INT_Buf_err) An AND output with inputs of BUF_ERR_IEN and Buf_Err_IF
13
1
read-only
Modem_IF
MODEM Interrupt Flag (Read Only) This bit is set when the CTS pin has state change (DCTSF=1). If IER[Modem_IEN] is enabled, the Modem interrupt will be generated. NOTE: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
3
1
read-only
Modem_INT
MODEM Status Interrupt Indicator to Interrupt Controller (INT_MOS). An AND output with inputs of Modem_IEN and Modem_IF
11
1
read-only
RDA_IF
Receive Data Available Interrupt Flag (Read Only). When the number of bytes in the Rx FIFO equals the RFITL then the RDA_IF will be set. If IER[RDA_IEN] is enabled, the RDA interrupt will be generated. NOTE: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL).
0
1
read-only
RDA_INT
Receive Data Available Interrupt Indicator to Interrupt Controller (INT_RDA). An AND output with inputs of RDA_IEN and RDA_IF
8
1
read-only
RLS_IF
Receive Line Interrupt Flag (Read Only). In UART mode this bit is set when the Rx receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). In RS-485 mode, the field includes RS-485 Address Byte Detection Flag. If IER[RLS_IEN] is enabled, the RLS interrupt will be generated. NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF, PEF and RS-485_Add_Det are cleared.
2
1
read-only
RLS_INT
Receive Line Status Interrupt Indicator to Interrupt Controller (INT_RLS). An AND output with inputs of RLS_IEN and RLS_IF Note: In RS-485 mode, the field includes RS-485 Address Byte Detection Flag.
10
1
read-only
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only). This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If IER[THRE_IEN] is enabled, the THRE interrupt will be generated. NOTE: This bit is read only and it will be cleared when writing data into THR (Tx FIFO not empty).
1
1
read-only
THRE_INT
Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller (INT_THRE). An AND output with inputs of THRE_IEN and THRE_IF
9
1
read-only
Tout_IF
Time Out Interrupt Flag (Read Only) This bit is set when the Rx FIFO is not empty and no activities occur in the Rx FIFO and the time out counter equal to TOIC. If IER [Tout_IEN] is enabled, the Tout interrupt will be generated. NOTE: This bit is read only and user can read UA_RBR (Rx is in active) to clear it.
4
1
read-only
Tout_INT
Time Out Interrupt Indicator to Interrupt Controller (INT_Tout) An AND output with inputs of RTO_IEN and Tout_IF
12
1
read-only
UA_LCR
UART0 Line Control Register.
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit When this bit is set to logic 1, the serial data output (Tx) is forced to the Spacing State (logic 0). This bit acts only on Tx and has no effect on the transmitter logic.
6
1
read-write
oneToSet
EPE
Even Parity Enable 0 = Odd number of logic 1's are transmitted or checked in the data word and parity bits. 1 = Even number of logic 1's are transmitted or checked in the data word and parity bits. This bit has effect only when bit 3 (parity bit enable) is set.
4
1
read-write
oneToSet
NSB
Number of "STOP bit" 0= One "STOP bit" is generated in the transmitted data 1= One and a half "STOP bit" is generated in the transmitted data when 5-bit word length is selected; Two "STOP bit" is generated when 6-, 7- and 8-bit word length is selected.
2
1
read-write
oneToSet
PBE
Parity Bit Enable 0 = Parity bit is not generated (transmit data) or checked (receive data) during transfer. 1 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
3
1
read-write
oneToSet
SPE
Stick Parity Enable 0 = Disable stick parity 1 = When bits PBE , EPE and SPE are set, the parity bit is transmitted and checked as cleared. When PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as set.
5
1
read-write
oneToSet
WLS
Word Length Select WLS[1:0] Character length 00 5 bits 01 6 bits 10 7 bits 11 8 bits
0
2
read-write
oneToSet
UA_MCR
UART0 Modem Control Register.
0x10
read-write
n
0x0
0x0
Lev_RTS
RTS Trigger Level This bit can change the RTS trigger level. 0= low level triggered 1= high level triggered
9
1
read-write
oneToSet
RTS
RTS (Request-To-Send) Signal 0: Drive RTS pin to logic 1 (If the Lev_RTS set to low level triggered). 1: Drive RTS pin to logic 0 (If the Lev_RTS set to low level triggered). 0: Drive RTS pin to logic 0 (If the Lev_RTS set to high level triggered). 1: Drive RTS pin to logic 1 (If the Lev_RTS set to high level triggered).
1
1
read-write
oneToSet
RTS_St
RTS Pin State This bit is the pin status of RTS.
13
1
read-only
UA_MSR
UART0 Modem Status Register.
0x14
read-write
n
0x0
0x0
CTS_St
CTS Pin Status This bit is the pin status of CTS.
4
1
read-only
DCTSF
Detect CTS State Change Flag This bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when IER [Modem_IEN]. NOTE: This bit is cleared by writing 1 to itself.
0
1
read-only
oneToClear
Lev_CTS
CTS Trigger Level This bit can change the CTS trigger level. 0= low level triggered 1= high level triggered
8
1
read-write
oneToSet
UA_RBR
UART0 Receive Buffer Register.
0x0
read-only
n
0x0
0x0
_8_bitReceivedData
Receive Buffer Register By reading this register, the UART will return an 8-bit data received from Rx pin (LSB first).
0
8
read-only
UA_THR
UART0 Transmit Holding Register.
UA_RBR
0x0
read-write
n
0x0
0x0
_8_bitTransmittedData
Transmit Holding Register By writing to this register, the UART will send out an 8-bit data through the Tx pin (LSB first).
0
8
write-only
UA_TOR
UART0 Time Out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay time value This field is use to programming the transfer delay time between the last stop bit leaving the TX-FIFO and the de-assertion of by setting UA_TOR. DLY register.
8
8
read-write
oneToSet
TOIC
Time Out Interrupt Comparator The time out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (INT_TOUT) is generated if UA_IER [RTO_IEN]. A new incoming data word or RX FIFO empty clears INT_TOUT.
0
7
read-write
WDT
Registers group
WDT
0x0
0x0
0x4
registers
n
WTCR
Watchdog Timer Control Register
0x0
read-write
n
0x0
0x0
WTE
Watchdog Timer Enable 0= Disable the Watchdog timer (This action will reset the internal counter) 1= Enable the Watchdog timer
7
1
read-write
WTIE
Watchdog Timer Interrupt Enable 0= Disable the Watchdog timer interrupt 1= Enable the Watchdog timer interrupt
6
1
read-write
WTIF
Watchdog Timer Interrupt Flag If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed. 0= Watchdog timer interrupt does not occur 1= Watchdog timer interrupt occurs NOTE: Write 1 to clear this bit to zero.
3
1
read-write
oneToClear
WTIS
Watchdog Timer Interval Select (write protection bit) These three bits select the timeout interval for the Watchdog timer. WTIS Timeout Interval Selection Interrupt Period WTR Timeout Interval (WDT_CLK=12MHz) 000 2^4 * WDT_CLK (2^4 + 1024) * WDT_CLK 1.33 us ~ 86.67 us 001 2^6 * WDT_CLK (2^6 + 1024) * WDT_CLK 5.33 us ~ 90.67 us 010 2^8 * WDT_CLK (2^8 + 1024) * WDT_CLK 21.33 us ~ 106.67 us 011 2^10 * WDT_CLK (2^10 + 1024) * WDT_CLK 85.33 us ~ 170.67 us 100 2^12 * WDT_CLK (2^12 + 1024) * WDT_CLK 341.33 us ~ 426.67 us 101 2^14 * WDT_CLK (2^14 + 1024) * WDT_CLK 1.36 ms ~ 1.45 ms 110 2^16 * WDT_CLK (2^16 + 1024) * WDT_CLK 5.46 ms ~ 5.55 ms 111 2^18 * WDT_CLK (2^18 + 1024) * WDT_CLK 21.84 ms ~ 21.93 ms
8
3
read-write
WTR
Clear Watchdog Timer Set this bit will clear the Watchdog timer. 0= Writing 0 to this bit has no effect 1= Reset the contents of the Watchdog timer NOTE: This bit will auto clear after few clock cycle
0
1
read-write
modify
WTRE
Watchdog Timer Reset Enable Setting this bit will enable the Watchdog timer reset function. 0= Disable Watchdog timer reset function 1= Enable Watchdog timer reset function
1
1
read-write
WTRF
Watchdog Timer Reset Flag When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If WTRE is disabled, then the Watchdog timer has no effect on this bit. 0= Watchdog timer reset does not occur 1= Watchdog timer reset occurs NOTE: This bit is cleared by writing 1 to this bit.
2
1
read-write
oneToClear
WTWKE
Watchdog Timer Wakeup Function Enable bit 0 = Disable Watchdog timer Wakeup CPU function. 1 = Enable the Wakeup function that Watchdog timer timeout can wake up CPU from power-down mode.
4
1
read-write
WTWKF
Watchdog Timer Wakeup Flag If Watchdog timer causes CPU wakes up from power-down mode, this bit will be set to high. It must be cleared by software with a write 1 to this bit. 1 = CPU wake up from sleep or power-down mode by Watchdog timeout. 0 = Watchdog timer does not cause CPU wakeup. NOTE: Write 1 to clear this bit to zero.
5
1
read-write
oneToClear