nuvoTon M0A21EB1AC 2024.04.28 M0A21EB1AC Cortex-M0 r1p0 little 3 false ACMP01 ACMP Register Map ACMP 0x0 0x0 0x10 registers n ACMP_CTL0 ACMP_CTL0 Analog Comparator 0 Control Register 0x0 -1 read-write n 0x0 0x0 ACMPEN Comparator Enable Bit 0 1 read-write 0 Comparator 0 Disabled #0 1 Comparator 0 Enabled #1 ACMPIE Comparator Interrupt Enable Bit 1 1 read-write 0 Comparator 0 interrupt Disabled #0 1 Comparator 0 interrupt Enabled. If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well #1 ACMPOINV Comparator Output Inverse 3 1 read-write 0 Comparator 0 output inverse Disabled #0 1 Comparator 0 output inverse Enabled #1 FILTSEL Comparator Output Filter Count Selection 13 3 read-write 0 Filter function is Disabled #000 1 ACMP0 output is sampled 1 consecutive PCLK #001 2 ACMP0 output is sampled 2 consecutive PCLKs #010 3 ACMP0 output is sampled 4 consecutive PCLKs #011 4 ACMP0 output is sampled 8 consecutive PCLKs #100 5 ACMP0 output is sampled 16 consecutive PCLKs #101 6 ACMP0 output is sampled 32 consecutive PCLKs #110 7 ACMP0 output is sampled 64 consecutive PCLKs #111 HYSBYPASS Hysteresis Adjust Function Selection 30 1 read-write 0 Enable adjust function #0 1 Bypass adjust function #1 HYSSEL Hysteresis Mode Selection 24 2 read-write 0 Hysteresis is 0mV #00 3 Hysteresis is 30mV #11 INTPOL Interrupt Condition Polarity Selection ACMPIF0 will be set to 1 when comparator output edge condition is detected. 20 2 read-write 0 Rising edge or falling edge #00 1 Rising edge #01 2 Falling edge #10 3 Reserved. #11 NEGSEL Comparator Negative Input Selection 4 3 read-write 0 All negative input disbaled #000 1 ACMP0_N0 #001 2 ACMP0_N1 #010 3 ACMP0_N2 #011 4 ACMP0_N3 #100 5 Comparator Reference Voltage (CRV) #101 OUTSEL Comparator Output Select 12 1 read-write 0 Comparator 0 output to ACMP0_O pin is unfiltered comparator output #0 1 Comparator 0 output to ACMP0_O pin is from filter output #1 POSSEL Comparator Positive Input Selection 8 3 read-write 0 All positive input disabled #000 1 Input from ACMP0_P0 #001 2 Comparator Reference Voltage (CRV) #010 3 DAC0 output #011 WCMPSEL Window Compare Mode Selection 18 1 read-write 0 Window Compare Mode Disabled #0 1 Window Compare Mode Selected #1 WKEN Power-down Wake-up Enable Bit 16 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 WLATEN Window Latch Mode Enable Bit 17 1 read-write 0 Window Latch Mode Disabled #0 1 Window Latch Mode Enabled #1 ACMP_CTL1 ACMP_CTL1 Analog Comparator 1 Control Register 0x4 -1 read-write n 0x0 0x0 ACMPEN Comparator Enable Bit 0 1 read-write 0 Comparator 1 Disabled #0 1 Comparator 1 Enabled #1 ACMPIE Comparator Interrupt Enable Bit 1 1 read-write 0 Comparator 1 interrupt Disabled #0 1 Comparator 1 interrupt Enabled. If WKEN (ACMP_CTL1[16]) is set to 1, the wake-up interrupt function will be enabled as well #1 ACMPOINV Comparator Output Inverse Control 3 1 read-write 0 Comparator 1 output inverse Disabled #0 1 Comparator 1 output inverse Enabled #1 FILTSEL Comparator Output Filter Count Selection 13 3 read-write 0 Filter function is Disabled #000 1 ACMP1 output is sampled 1 consecutive PCLK #001 2 ACMP1 output is sampled 2 consecutive PCLKs #010 3 ACMP1 output is sampled 4 consecutive PCLKs #011 4 ACMP1 output is sampled 8 consecutive PCLKs #100 5 ACMP1 output is sampled 16 consecutive PCLKs #101 6 ACMP1 output is sampled 32 consecutive PCLKs #110 7 ACMP1 output is sampled 64 consecutive PCLKs #111 HYSSEL Hysteresis Mode Selection 24 2 read-write 0 Hysteresis is 0mV #00 3 Hysteresis is 30mV #11 INTPOL Interrupt Condition Polarity Selection ACMPIF0 will be set to 1 when comparator output edge condition is detected. 20 2 read-write 0 Rising edge or falling edge #00 1 Rising edge #01 2 Falling edge #10 3 Reserved. #11 NEGSEL Comparator Negative Input Selection 4 3 read-write 0 All negative input disbaled #000 1 ACMP1_N0 #001 2 ACMP1_N1 #010 3 ACMP1_N2 #011 4 ACMP1_N3 #100 5 Comparator Reference Voltage (CRV) #101 OUTSEL Comparator Output Select 12 1 read-write 0 Comparator 1 output to ACMP1_O pin is unfiltered comparator output #0 1 Comparator 1 output to ACMP1_O pin is from filter output #1 POSSEL Comparator Positive Input Selection 8 3 read-write 0 All positive input disabled #000 1 Input from ACMP1_P0 #001 2 Comparator Reference Voltage (CRV) #010 3 DAC0 output #011 WCMPSEL Window Compare Mode Selection 18 1 read-write 0 Window Compare Mode Disabled #0 1 Window Compare Mode Selected #1 WKEN Power-down Wakeup Enable Bit 16 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 WLATEN Window Latch Mode Enable Bit 17 1 read-write 0 Window Latch Mode Disabled #0 1 Window Latch Mode Enabled #1 ACMP_STATUS ACMP_STATUS Analog Comparator Status Register 0x8 -1 read-write n 0x0 0x0 ACMPIF0 Comparator 0 Interrupt Flag This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[21:20]) is detected on comparator 0 output. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1. Note: Write 1 to clear this bit to 0. 0 1 read-write ACMPIF1 Comparator 1 Interrupt Flag This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[21:20]) is detected on comparator 1 output. This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1. Note: Write 1 to clear this bit to 0. 1 1 read-write ACMPO0 Comparator 0 Output Synchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0. 4 1 read-write ACMPO1 Comparator 1 Output Synchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0. 5 1 read-write ACMPS0 Comparator 0 Status Synchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0. 12 1 read-write ACMPS1 Comparator 1 Status Synchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0. 13 1 read-write ACMPWO Comparator Window Output This bit shows the output status of window compare mode 16 1 read-write 0 The positive input voltage is outside the window #0 1 The positive input voltage is in the window #1 WKIF0 Comparator 0 Power-down Wake-up Interrupt Flag This bit will be set to 1 when ACMP0 wake-up interrupt event occurs. Note: Write 1 to clear this bit to 0. 8 1 read-write 0 No power-down wake-up occurred #0 1 Power-down wake-up occurred #1 WKIF1 Comparator 1 Power-down Wake-up Interrupt Flag This bit will be set to 1 when ACMP1 wake-up interrupt event occurs. Note: Write 1 to clear this bit to 0. 9 1 read-write 0 No power-down wake-up occurred #0 1 Power-down wake-up occurred #1 ACMP_VREF ACMP_VREF Analog Comparator Reference Voltage Control Register 0xC -1 read-write n 0x0 0x0 COMPEN Comparator Bias Enable Bit 9 1 read-write 0 Comparator bias Disabled #0 1 Comparator bias Enabled #1 CRVCTL Comparator Reference Voltage Setting 0 4 read-write CRVEN CRV Function Enable Bit 8 1 read-write 0 CRV function Disabled #0 1 CRV function Enabled #1 CRVSSEL CRV Source Voltage Selection 6 1 read-write 0 AVDD (voltage of VDD pin)is selected as CRV source voltage #0 1 Internal VREF is selected as as CRV source voltage #1 ADC ADC Register Map ADC 0x0 0x0 0x44 registers n 0x100 0x4 registers n 0x68 0x8 registers n 0x74 0x8 registers n 0x80 0x20 registers n ADCHER ADC_ADCHER ADC Channel Enable Register 0x84 -1 read-write n 0x0 0x0 CHEN Analog Input Channel Enable Control Set ADC_ ADCHER[16:0] bits to enable the corresponding analog input channel 16 ~ 0. If DIFFEN bit is set to 1, only the even number channel needs to be enabled. Besides, set ADC_ ADCHER[26], ADC_ ADCHER[27], ADC_ ADCHER[29], ADC_ ADCHER[30] bits will enable internal channel for internal reference voltage, DAC0_OUT, band-gap voltage and temperature sensor respectively. Other bits are reserved. Note 1: If the internal channel for band-gap voltage (CHEN[29]) is active, the maximum sampling rate will be 300k SPS. Note 2: If the internal channel for temperature sensor (CHEN[30]) is active, the maximum sampling rate will be 300k SPS. 0 32 read-write 0 Channel Disabled 0 1 Channel Enabled 1 ADCMPR0 ADC_ADCMPR0 ADC Compare Register 0 0x88 -1 read-write n 0x0 0x0 CMPCH Compare Channel Selection 3 5 read-write 0 Channel 0 conversion result is selected to be compared #00000 1 Channel 1 conversion result is selected to be compared #00001 2 Channel 2 conversion result is selected to be compared #00010 3 Channel 3 conversion result is selected to be compared #00011 4 Channel 4 conversion result is selected to be compared #00100 5 Channel 5 conversion result is selected to be compared #00101 6 Channel 6 conversion result is selected to be compared #00110 7 Channel 7 conversion result is selected to be compared #00111 8 Channel 8 conversion result is selected to be compared #01000 9 Channel 9 conversion result is selected to be compared #01001 10 Channel 10 conversion result is selected to be compared #01010 11 Channel 11 conversion result is selected to be compared #01011 12 Channel 12 conversion result is selected to be compared #01100 13 Channel 13 conversion result is selected to be compared #01101 14 Channel 14 conversion result is selected to be compared #01110 15 Channel 15 conversion result is selected to be compared #01111 16 Channel 16 conversion result is selected to be compared #10000 26 Internal reference voltage conversion result is selected to be compared #11010 27 DAC0 output conversion result is selected to be compared #11011 29 Band-gap voltage conversion result is selected to be compared #11101 30 Temperature sensor conversion result is selected to be compared #11110 CMPCOND Compare Condition Note: When the internal counter reaches to (CMPMATCNT +1), the CMPFx bit will be set. 2 1 read-write 0 Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD bits, the internal match counter will increase one #0 1 Set the compare condition as that when a 12-bit A/D conversion result is greater than or equal to the 12-bit CMPD bits, the internal match counter will increase one #1 CMPD Comparison Data The 12-bit data is used to compare with conversion result of specified channel. Note: CMPD bits should be filled in unsigned format (straight binary format). 16 12 read-write CMPEN Compare Enable Control Set this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register. 0 1 read-write 0 Compare function Disabled #0 1 Compare function Enabled #1 CMPIE Compare Interrupt Enable Control If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE bit is set to 1, a compare interrupt request is generated. 1 1 read-write 0 Compare function interrupt Disabled #0 1 Compare function interrupt Enabled #1 CMPMATCNT Compare Match Count When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit, the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set. 8 4 read-write CMPWEN Compare Window Mode Enable Bit Note: This bit is only presented in ADCMPR0 register. 15 1 read-write 0 Compare Window Mode Disabled #0 1 Compare Window Mode Enabled #1 ADCMPR1 ADC_ADCMPR1 ADC Compare Register 1 0x8C -1 read-write n 0x0 0x0 ADCR ADC_ADCR ADC Control Register 0x80 -1 read-write n 0x0 0x0 ADEN A/D Converter Enable Bit Note: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption. 0 1 read-write 0 A/D converter Disabled #0 1 A/D converter Enabled #1 ADIE A/D Interrupt Enable Control A/D conversion end interrupt request is generated if ADIE bit is set to 1. 1 1 read-write 0 A/D interrupt function Disabled #0 1 A/D interrupt function Enabled #1 ADMD A/D Converter Operation Mode Control Note 1: When changing the operation mode, software should clear ADST bit first. Note 2: In Burst mode, the A/D result data is always at ADC Data Register 0. 2 2 read-write 0 Single conversion #00 1 Burst conversion #01 2 Single-cycle Scan #10 3 Continuous Scan #11 ADST A/D Conversion Start ADST bit can be set to 1 from four sources: software, external pin STADC, PWM trigger and Timer trigger. ADST bit will be cleared to 0 by hardware automatically at the ends of Single mode and Single-cycle Scan mode. In Continuous Scan mode and Burst mode, A/D conversion is continuously performed until software writes 0 to this bit or chip is reset. 11 1 read-write 0 Conversion stops and A/D converter enters idle state #0 1 Conversion starts #1 DIFFEN Differential Input Mode Control 10 1 read-write 0 Single-end analog input mode #0 1 Differential analog input mode #1 DMOF Differential Input Mode Output Format If user enables differential input mode, the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format). 31 1 read-write 0 A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format (straight binary format) #0 1 A/D Conversion result will be filled in RSLT at ADDRx registers with 2's complement format #1 PTEN PDMA Transfer Enable Bit When A/D conversion is completed, the converted data is loaded into ADDR0~16 ADDR26, ADDR27, ADDR29, ADDR30. Software can enable this bit to generate a PDMA data transfer request. 9 1 read-write 0 PDMA data transfer Disabled #0 1 PDMA data transfer in ADDR0~16, ADDR26, ADDR27, ADDR29, ADDR30 Enabled #1 SMPTSEL ADC Internal Sampling Time Selection 16 3 read-write 0 4 ADC clock for sampling 16 ADC clock for complete conversion #000 1 5 ADC clock for sampling 17 ADC clock for complete conversion #001 2 6 ADC clock for sampling 18 ADC clock for complete conversion #010 3 7 ADC clock for sampling 19 ADC clock for complete conversion #011 4 8 ADC clock for sampling 20 ADC clock for complete conversion #100 5 9 ADC clock for sampling 21 ADC clock for complete conversion #101 6 10 ADC clock for sampling 22 ADC clock for complete conversion #110 7 11 ADC clock for sampling 23 ADC clock for complete conversion #111 TRGCOND External Trigger Condition These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger. 6 2 read-write 0 Low level #00 1 High level #01 2 Falling edge #10 3 Rising edge #11 TRGEN External Trigger Enable Control Enable or disable triggering of A/D conversion by external STADC pin, PWM trigger and Timer trigger. If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source. Note: The ADC external trigger function is only supported in Single-cycle Scan mode. 8 1 read-write 0 External trigger Disabled #0 1 External trigger Enabled #1 TRGS Hardware Trigger Source Note: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits. 4 2 read-write 0 A/D conversion is started by external STADC pin #00 1 Timer0 ~ Timer3 overflow pulse trigger #01 2 Reserved. #10 3 A/D conversion is started by PWM trigger #11 ADDR0 ADC_ADDR0 ADC Data Register 0 0x0 -1 read-only n 0x0 0x0 OVERRUN Overrun Flag (Read Only) If converted data in RSLT bits has not been read before new conversion result is loaded to this register, OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read. 16 1 read-only 0 Data in RSLT bits is not overwrote #0 1 Data in RSLT bits is overwrote #1 RSLT A/D Conversion Result (Read Only) This field contains conversion result of ADC. 0 16 read-only VALID Valid Flag (Read Only) This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read. 17 1 read-only 0 Data in RSLT bits is not valid #0 1 Data in RSLT bits is valid #1 ADDR1 ADC_ADDR1 ADC Data Register 1 0x4 -1 read-write n 0x0 0x0 ADDR10 ADC_ADDR10 ADC Data Register 10 0x28 -1 read-write n 0x0 0x0 ADDR11 ADC_ADDR11 ADC Data Register 11 0x2C -1 read-write n 0x0 0x0 ADDR12 ADC_ADDR12 ADC Data Register 12 0x30 -1 read-write n 0x0 0x0 ADDR13 ADC_ADDR13 ADC Data Register 13 0x34 -1 read-write n 0x0 0x0 ADDR14 ADC_ADDR14 ADC Data Register 14 0x38 -1 read-write n 0x0 0x0 ADDR15 ADC_ADDR15 ADC Data Register 15 0x3C -1 read-write n 0x0 0x0 ADDR16 ADC_ADDR16 ADC Data Register 16 0x40 -1 read-write n 0x0 0x0 ADDR2 ADC_ADDR2 ADC Data Register 2 0x8 -1 read-write n 0x0 0x0 ADDR26 ADC_ADDR26 ADC Data Register 26 0x68 -1 read-write n 0x0 0x0 ADDR27 ADC_ADDR27 ADC Data Register 27 0x6C -1 read-write n 0x0 0x0 ADDR29 ADC_ADDR29 ADC Data Register 29 0x74 -1 read-write n 0x0 0x0 ADDR3 ADC_ADDR3 ADC Data Register 3 0xC -1 read-write n 0x0 0x0 ADDR30 ADC_ADDR30 ADC Data Register 30 0x78 -1 read-write n 0x0 0x0 ADDR4 ADC_ADDR4 ADC Data Register 4 0x10 -1 read-write n 0x0 0x0 ADDR5 ADC_ADDR5 ADC Data Register 5 0x14 -1 read-write n 0x0 0x0 ADDR6 ADC_ADDR6 ADC Data Register 6 0x18 -1 read-write n 0x0 0x0 ADDR7 ADC_ADDR7 ADC Data Register 7 0x1C -1 read-write n 0x0 0x0 ADDR8 ADC_ADDR8 ADC Data Register 8 0x20 -1 read-write n 0x0 0x0 ADDR9 ADC_ADDR9 ADC Data Register 9 0x24 -1 read-write n 0x0 0x0 ADPDMA ADC_ADPDMA ADC PDMA Current Transfer Data Register 0x100 -1 read-only n 0x0 0x0 CURDAT ADC PDMA Current Transfer Data Register (Read Only) When PDMA transferring, read this register can monitor current PDMA transfer data. Current PDMA transfer data could be the content of ADDR0 ~ ADDR16 and ADDR26, ADDR27, and ADDR29, ADDR30 registers. 0 18 read-only ADSR0 ADC_ADSR0 ADC Status Register0 0x90 -1 read-write n 0x0 0x0 ADF A/D Conversion End Flag A status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit. ADF bit is set to 1 at the following three conditions: When A/D conversion ends in Single mode. When A/D conversion ends on all specified channels in Single-cycle Scan mode and Continuous Scan mode. When more than or equal to 8 samples in FIFO in Burst mode. 0 1 read-write BUSY BUSY/IDLE (Read Only) This bit is a mirror of ADST bit in ADCR register. 7 1 read-only 0 A/D converter is in idle state #0 1 A/D converter is busy at conversion #1 CHANNEL Current Conversion Channel (Read Only) 27 5 read-only CMPF0 Compare Flag 0 When the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1. This bit is cleared by writing 1 to it. 1 1 read-write 0 Conversion result in ADDR does not meet ADCMPR0 setting #0 1 Conversion result in ADDR meets ADCMPR0 setting #1 CMPF1 Compare Flag 1 When the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register then this bit is set to 1 it is cleared by writing 1 to it 2 1 read-write 0 Conversion result in ADDR does not meet ADCMPR1 setting #0 1 Conversion result in ADDR meets ADCMPR1 setting #1 OVERRUNF Overrun Flag (Read Only) If any one of OVERRUN (ADDRx[16]) is set, this flag will be set to 1. Note: When ADC is in burst mode and the FIFO is overrun, this flag will be set to 1. 16 1 read-only VALIDF Data Valid Flag (Read Only) If any one of VALID (ADDRx[17]) is set, this flag will be set to 1. Note: When ADC is in burst mode and any conversion result is valid, this flag will be set to 1. 8 1 read-only ADSR1 ADC_ADSR1 ADC Status Register1 0x94 -1 read-only n 0x0 0x0 VALID Data Valid Flag (Read Only) VALID[30:29], VALID[27:26], VALID[16:0] are the mirror of the VALID bits in ADDR30[17], ADDR29[17], ADDR27[17], ADDR26[17], ADDR16[17]~ ADDR0[17]. The other bits are reserved. Note: When ADC is in burst mode and any conversion result is valid, VALID[30:29], VALID[27:26], VALID[16:0] will be set to 1. 0 32 read-only ADSR2 ADC_ADSR2 ADC Status Register2 0x98 -1 read-only n 0x0 0x0 OVERRUN Overrun Flag (Read Only) OVERRUN[30:29], OVERRUN[27:26], OVERRUN[16:0] are the mirror of the OVERRUN bit in ADDR30[16], ADDR29[16], ADDR27[16], ADDR26[16], ADDR16[16] ~ ADDR0[16]. The other bits are reserved. Note: When ADC is in burst mode and the FIFO is overrun, OVERRUN[30:29], OVERRUN[27:26], OVERRUN[16:0] will be set to 1. 0 32 read-only ADTDCR ADC_ADTDCR ADC Trigger Delay Control Register 0x9C -1 read-write n 0x0 0x0 PTDT PWM Trigger Delay Time Set this field will delay ADC start conversion time after PWM trigger. PWM trigger delay time is (4 * PTDT) * system clock 0 8 read-write CAN CAN Register Map CAN 0x0 0x0 0x1C registers n 0x100 0x8 registers n 0x120 0x8 registers n 0x140 0x8 registers n 0x160 0x10 registers n 0x20 0x2C registers n 0x80 0x2C registers n BRPE CAN_BRPE Baud Rate Prescaler Extension Register 0x18 -1 read-write n 0x0 0x0 BRPE BRPE: Baud Rate Prescaler Extension 0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023. The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used. 0 4 read-write BTIME CAN_BTIME Bit Timing Register 0xC -1 read-write n 0x0 0x0 BRP Baud Rate Prescaler 0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are [0...63]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 0 6 read-write SJW (Re)Synchronization Jump Width 0x0-0x3: Valid programmed values are [0...3]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 6 2 read-write TSeg1 Time Segment Before the Sample Point Minus Sync_Seg 0x01-0x0F: valid values for TSeg1 are [1...15]. The actual interpretation by the hardware of this value is such that one more than the value programmed is used. 8 4 read-write TSeg2 Time Segment After Sample Point 0x0-0x7: Valid values for TSeg2 are [0...7]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 12 3 read-write CON CAN_CON CAN Control Register 0x0 -1 read-write n 0x0 0x0 CCE Configuration Change Enable Bit 6 1 read-write 0 No write access to the Bit Timing Register #0 1 Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1) #1 DAR Automatic Re-transmission Disable Bit 5 1 read-write 0 Automatic Retransmission of disturbed messages Enabled #0 1 Automatic Retransmission Disabled #1 EIE Error Interrupt Enable Bit 3 1 read-write 0 Disabled - No Error Status Interrupt will be generated #0 1 Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt #1 IE Module Interrupt Enable Bit 1 1 read-write 0 Funcrion interrupt Disabled #0 1 Funcrion interrupt Enabled #1 Init Init Initialization 0 1 read-write 0 Normal Operation #0 1 Initialization is started #1 SIE Status Change Interrupt Enable Bit 2 1 read-write 0 Disabled - No Status Change Interrupt will be generated #0 1 Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected #1 Test Test Mode Enable Bit 7 1 read-write 0 Normal Operation #0 1 Test Mode #1 ERR CAN_ERR CAN Error Counter Register 0x8 -1 read-only n 0x0 0x0 REC Receive Error Counter Actual state of the Receive Error Counter. Values between 0 and 127. 8 7 read-only RP Receive Error Passive 15 1 read-only 0 The Receive Error Counter is below the error passive level #0 1 The Receive Error Counter has reached the error passive level as defined in the CAN Specification #1 TEC Transmit Error Counter Actual state of the Transmit Error Counter. Values between 0 and 255. 0 8 read-only IF1_ARB1 CAN_IF1_ARB1 IFn Arbitration 1 Registers 0x30 -1 read-write n 0x0 0x0 ID Message Identifier 15-0 ID28 - ID0, 29-bit Identifier ('Extended Frame'). ID28 - ID18, 11-bit Identifier ('Standard Frame') 0 16 read-write IF1_ARB2 CAN_IF1_ARB2 IFn Arbitration 2 Registers 0x34 -1 read-write n 0x0 0x0 Dir Message Direction 13 1 read-write 0 Direction is receive #0 1 Direction is transmit #1 ID Message Identifier 28-16 ID28 - ID0, 29-bit Identifier ('Extended Frame'). ID28 - ID18, 11-bit Identifier ('Standard Frame') 0 13 read-write MsgVal Message Valid Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]). This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_ARB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required. 15 1 read-write 0 The Message Object is ignored by the Message Handler #0 1 The Message Object is configured and should be considered by the Message Handler #1 Xtd Extended Identifier 14 1 read-write 0 The 11-bit ('standard') Identifier will be used for this Message Object #0 1 The 29-bit ('extended') Identifier will be used for this Message Object #1 IF1_CMASK CAN_IF1_CMASK IFn Command Mask Registers 0x24 -1 read-write n 0x0 0x0 Arb Access Arbitration Bits Write Operation: 5 1 read-write 0 Arbitration bits unchanged #0 1 Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_ARB2[15]) to Message Object. Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register #1 ClrIntPnd Clear Interrupt Pending Bit Write Operation: When writing to a Message Object, this bit is ignored. Read Operation: 3 1 read-write 0 IntPnd bit (CAN_IFn_MCON[13]) remains unchanged #0 1 Clear IntPnd bit in the Message Object #1 Control Control Access Control Bits Write Operation: 4 1 read-write 0 Control Bits unchanged #0 1 Transfer Control Bits to Message Object. Transfer Control Bits to IFn Message Buffer Register #1 DAT_A Access Data Bytes [3:0] Write Operation: 1 1 read-write 0 Data Bytes [3:0] unchanged #0 1 Transfer Data Bytes [3:0] to Message Object. Transfer Data Bytes [3:0] to IFn Message Buffer Register #1 DAT_B Access Data Bytes [7:4] Write Operation: 0 1 read-write 0 Data Bytes [7:4] unchanged #0 1 Transfer Data Bytes [7:4] to Message Object. Transfer Data Bytes [7:4] to IFn Message Buffer Register #1 Mask Access Mask Bits Write Operation: 6 1 read-write 0 Mask bits unchanged #0 1 Transfer Identifier Mask + MDir + MXtd to Message Object. Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register #1 TxRqst_NewDat Access Transmission Request Bit When Write Operation Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits. 2 1 read-write 0 TxRqst bit unchanged. NewDat bit remains unchanged #0 1 Set TxRqst bit. Clear NewDat bit in the Message Object #1 WR_RD Write and Read Mode 7 1 read-write 0 Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers #0 1 Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register #1 IF1_CREQ CAN_IF1_CREQ IFn (Register Map Note 2) Command Request Registers 0x20 -1 read-write n 0x0 0x0 Busy Busy Flag 15 1 read-write 0 Read/write action has finished #0 1 Writing to the IFn Command Request Register is in progress. This bit can only be read by the software #1 MessageNumber Message Number 0x01-0x20: Valid Message Number, the Message Object in the Message RAM is selected for data transfer. 0x00: Not a valid Message Number, interpreted as 0x20. 0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F. 0 6 read-write IF1_DAT_A1 CAN_IF1_DAT_A1 IFn Data A1 Registers (Register Map Note 3) 0x3C -1 read-write n 0x0 0x0 Data_0 Data Byte 0 1st data byte of a CAN Data Frame 0 8 read-write Data_1 Data Byte 1 2nd data byte of a CAN Data Frame 8 8 read-write IF1_DAT_A2 CAN_IF1_DAT_A2 IFn Data A2 Registers (Register Map Note 3) 0x40 -1 read-write n 0x0 0x0 Data_2 Data Byte 2 3rd data byte of CAN Data Frame 0 8 read-write Data_3 Data Byte 3 4th data byte of CAN Data Frame 8 8 read-write IF1_DAT_B1 CAN_IF1_DAT_B1 IFn Data B1 Registers (Register Map Note 3) 0x44 -1 read-write n 0x0 0x0 Data_4 Data Byte 4 5th data byte of CAN Data Frame 0 8 read-write Data_5 Data Byte 5 6th data byte of CAN Data Frame 8 8 read-write IF1_DAT_B2 CAN_IF1_DAT_B2 IFn Data B2 Registers (Register Map Note 3) 0x48 -1 read-write n 0x0 0x0 Data_6 Data Byte 6 7th data byte of CAN Data Frame. 0 8 read-write Data_7 Data Byte 7 8th data byte of CAN Data Frame. 8 8 read-write IF1_MASK1 CAN_IF1_MASK1 IFn Mask 1 Registers 0x28 -1 read-write n 0x0 0x0 Msk Identifier Mask 15-0 0 16 read-write 0 The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering 0 1 The corresponding identifier bit is used for acceptance filtering 1 IF1_MASK2 CAN_IF1_MASK2 IFn Mask 2 Registers 0x2C -1 read-write n 0x0 0x0 MDir Mask Message Direction 14 1 read-write 0 The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering #0 1 The message direction bit (Dir) is used for acceptance filtering #1 Msk Identifier Mask 28-16 0 13 read-write 0 The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering 0 1 The corresponding identifier bit is used for acceptance filtering 1 MXtd Mask Extended Identifier Note: When 11-bit ('standard') Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]). For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered. 15 1 read-write 0 The extended identifier bit (IDE) has no effect on the acceptance filtering #0 1 The extended identifier bit (IDE) is used for acceptance filtering #1 IF1_MCON CAN_IF1_MCON IFn Message Control Registers 0x38 -1 read-write n 0x0 0x0 DLC Data Length Code 0-8: Data Frame has 0-8 data bytes. 9-15: Data Frame has 8 data bytes Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. Data(0): 1st data byte of a CAN Data Frame Data(1): 2nd data byte of a CAN Data Frame Data(2): 3rd data byte of a CAN Data Frame Data(3): 4th data byte of a CAN Data Frame Data(4): 5th data byte of a CAN Data Frame Data(5): 6th data byte of a CAN Data Frame Data(6): 7th data byte of a CAN Data Frame Data(7): 8th data byte of a CAN Data Frame Note: The Data(0) byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data(7) byte is the last. When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object. If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values. 0 4 read-write EoB End of Buffer Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one. 7 1 read-write 0 Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer #0 1 Single Message Object or last Message Object of a FIFO Buffer #1 IntPnd Interrupt Pending 13 1 read-write 0 This message object is not the source of an interrupt #0 1 This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority #1 MsgLst Message Lost 14 1 read-write 0 No message lost since last time this bit was reset by the CPU #0 1 The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message #1 NewDat New Data 15 1 read-write 0 No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software #0 1 The Message Handler or the application software has written new data into the data portion of this Message Object #1 RmtEn Remote Enable Bit 9 1 read-write 0 At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged #0 1 At the reception of a Remote Frame, TxRqst is set #1 RxIE Receive Interrupt Enable Bit 10 1 read-write 0 IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame #0 1 IntPnd will be set after a successful reception of a frame #1 TxIE Transmit Interrupt Enable Bit 11 1 read-write 0 IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame #0 1 IntPnd will be set after a successful transmission of a frame #1 TxRqst Transmit Request 8 1 read-write 0 This Message Object is not waiting for transmission #0 1 The transmission of this Message Object is requested and is not yet done #1 UMask Use Acceptance Mask Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one. 12 1 read-write 0 Mask ignored #0 1 Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering #1 IF2_ARB1 CAN_IF2_ARB1 IFn Arbitration 1 Registers 0x90 -1 read-write n 0x0 0x0 IF2_ARB2 CAN_IF2_ARB2 IFn Arbitration 2 Registers 0x94 -1 read-write n 0x0 0x0 IF2_CMASK CAN_IF2_CMASK IFn Command Mask Registers 0x84 -1 read-write n 0x0 0x0 IF2_CREQ CAN_IF2_CREQ IFn (Register Map Note 2) Command Request Registers 0x80 -1 read-write n 0x0 0x0 IF2_DAT_A1 CAN_IF2_DAT_A1 IFn Data A1 Registers (Register Map Note 3) 0x9C -1 read-write n 0x0 0x0 IF2_DAT_A2 CAN_IF2_DAT_A2 IFn Data A2 Registers (Register Map Note 3) 0xA0 -1 read-write n 0x0 0x0 IF2_DAT_B1 CAN_IF2_DAT_B1 IFn Data B1 Registers (Register Map Note 3) 0xA4 -1 read-write n 0x0 0x0 IF2_DAT_B2 CAN_IF2_DAT_B2 IFn Data B2 Registers (Register Map Note 3) 0xA8 -1 read-write n 0x0 0x0 IF2_MASK1 CAN_IF2_MASK1 IFn Mask 1 Registers 0x88 -1 read-write n 0x0 0x0 IF2_MASK2 CAN_IF2_MASK2 IFn Mask 2 Registers 0x8C -1 read-write n 0x0 0x0 IF2_MCON CAN_IF2_MCON IFn Message Control Registers 0x98 -1 read-write n 0x0 0x0 IIDR CAN_IIDR Interrupt Identifier Register 0x10 -1 read-only n 0x0 0x0 IntId Interrupt Identifier (Indicates the Source of the Interrupt) If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the application software has cleared it. If IntId is different from 0x0000 and IE (CAN_CON[1]) is set, the IRQ interrupt signal to the EIC is active. The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset. The Status Interrupt has the highest priority. Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number. A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]). The Status Interrupt is cleared by reading the Status Register. 0 16 read-only IPND1 CAN_IPND1 Interrupt Pending Register 1 0x140 -1 read-only n 0x0 0x0 IntPnd16_1 Interrupt Pending Bits 16-1 (of All Message Objects) 0 16 read-only 0 This message object is not the source of an interrupt 0 1 This message object is the source of an interrupt 1 IPND2 CAN_IPND2 Interrupt Pending Register 2 0x144 -1 read-only n 0x0 0x0 IntPnd32_17 Interrupt Pending Bits 32-17 (of All Message Objects) 0 16 read-only 0 This message object is not the source of an interrupt 0 1 This message object is the source of an interrupt 1 MVLD1 CAN_MVLD1 Message Valid Register 1 0x160 -1 read-only n 0x0 0x0 MsgVal16_1 Message Valid Bits 16-1 (of All Message Objects) (Read Only) Note: CAN_MVLD1[0] means Message object No.1 is valid or not. If CAN_MVLD1[0] is set, message object No.1 is configured. 0 16 read-only 0 This Message Object is ignored by the Message Handler 0 1 This Message Object is configured and should be considered by the Message Handler 1 MVLD2 CAN_MVLD2 Message Valid Register 2 0x164 -1 read-only n 0x0 0x0 MsgVal32_17 Message Valid Bits 32-17 (of All Message Objects) (Read Only) Note: CAN_MVLD2[15] means Message object No.32 is valid or not. If CAN_MVLD2[15] is set, message object No.32 is configured. 0 16 read-only 0 This Message Object is ignored by the Message Handler 0 1 This Message Object is configured and should be considered by the Message Handler 1 NDAT1 CAN_NDAT1 New Data Register 1 0x120 -1 read-only n 0x0 0x0 NewData16_1 New Data Bits 16-1 (of All Message Objects) 0 16 read-only 0 No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software 0 1 The Message Handler or the application software has written new data into the data portion of this Message Object 1 NDAT2 CAN_NDAT2 New Data Register 2 0x124 -1 read-only n 0x0 0x0 NewData32_17 New Data Bits 32-17 (of All Message Objects) 0 16 read-only 0 No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software 0 1 The Message Handler or the application software has written new data into the data portion of this Message Object 1 STATUS CAN_STATUS CAN Status Register 0x4 -1 read-write n 0x0 0x0 BOff Bus-off Status (Read Only) 7 1 read-only 0 The CAN module is not in bus-off state #0 1 The CAN module is in bus-off state #1 EPass Error Passive (Read Only) 5 1 read-only 0 The CAN Core is error active #0 1 The CAN Core is in the error passive state as defined in the CAN Specification #1 EWarn Error Warning Status (Read Only) 6 1 read-only 0 Both error counters are below the error warning limit of 96 #0 1 At least one of the error counters in the EML has reached the error warning limit of 96 #1 LEC Last Error Code (Type of the Last Error to Occur on the CAN Bus) The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. The unused code '7' may be written by the CPU to check for updates. Table 6.165 Last Error Codedescribes the error code. 0 3 read-write RxOK Received a Message Successfully 4 1 read-write 0 No message has been successfully received since this bit was last reset by the CPU. This bit is never reset by the CAN Core #0 1 A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering) #1 TxOK Transmitted a Message Successfully 3 1 read-write 0 Since this bit was reset by the CPU, no message has been successfully transmitted. This bit is never reset by the CAN Core #0 1 Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted #1 TEST CAN_TEST Test Register (Register Map Note 1) 0x14 -1 read-write n 0x0 0x0 Basic Basic Mode 2 1 read-write 0 Basic Mode Disabled #0 1 IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer #1 LBack Loop Back Mode Enable Bit 4 1 read-write 0 Loop Back Mode Disabled #0 1 Loop Back Mode Enabled #1 Rx Monitors the Actual Value of CAN_RX Pin (Read Only) *(1) 7 1 read-only 0 The CAN bus is dominant (CAN_RX = '0') #0 1 The CAN bus is recessive (CAN_RX = '1') #1 Silent Silent Mode 3 1 read-write 0 Normal operation #0 1 The module is in Silent Mode #1 Tx Tx[1:0]: Control of CAN_TX Pin 5 2 read-write 0 Reset value, CAN_TX pin is controlled by the CAN Core #00 1 Sample Point can be monitored at CAN_TX pin #01 2 CAN_TX pin drives a dominant ('0') value #10 3 CAN_TX pin drives a recessive ('1') value #11 TXREQ1 CAN_TXREQ1 Transmission Request Register 1 0x100 -1 read-only n 0x0 0x0 TxRqst16_1 Transmission Request Bits 16-1 (of All Message Objects) (Read Only) 0 16 read-only 0 This Message Object is not waiting for transmission 0 1 The transmission of this Message Object is requested and is not yet done 1 TXREQ2 CAN_TXREQ2 Transmission Request Register 2 0x104 -1 read-only n 0x0 0x0 TxRqst32_17 Transmission Request Bits 32-17 (of All Message Objects) (Read Only) 0 16 read-only 0 This Message Object is not waiting for transmission 0 1 The transmission of this Message Object is requested and is not yet done 1 WU_EN CAN_WU_EN Wake-up Enable Control Register 0x168 -1 read-write n 0x0 0x0 WAKUP_EN Wake-up Enable Bit Note: User can wake up system when there is a falling edge in the CAN_Rx pin. 0 1 read-write 0 The wake-up function Disabled #0 1 The wake-up function Enabled #1 WU_STATUS CAN_WU_STATUS Wake-up Status Register 0x16C -1 read-write n 0x0 0x0 WAKUP_STS Wake-up Status Note: This bit can be cleared by writing '0' to it. 0 1 read-write 0 No wake-up event occurred #0 1 Wake-up event occurred #1 CLK CLK Register Map CLK 0x0 0x0 0x1C registers n 0x20 0x4 registers n 0x34 0x4 registers n 0x50 0x4 registers n 0x60 0x4 registers n 0x70 0x10 registers n 0xB4 0x4 registers n AHBCLK CLK_AHBCLK AHB Devices Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 CRCCKEN CRC Generator Controller Clock Enable Bit 7 1 read-write 0 CRC peripheral clock Disabled #0 1 CRC peripheral clock Enabled #1 HDIV_EN Divider Controller Clock Enable Control 4 1 read-write 0 Divider controller peripheral clock Disabled #0 1 Divider controller peripheral clock Enabled #1 ISPCKEN Flash ISP Controller Clock Enable Bit 2 1 read-write 0 Flash ISP peripheral clock Disabled #0 1 Flash ISP peripheral clock Enabled #1 PDMACKEN PDMA Controller Clock Enable Bit 1 1 read-write 0 PDMA peripheral clock Disabled #0 1 PDMA peripheral clock Enabled #1 APBCLK0 CLK_APBCLK0 APB Devices Clock Enable Control Register 0 0x8 -1 read-write n 0x0 0x0 ACMP01CKEN Analog Comparator 0/1 Clock Enable Bit 7 1 read-write 0 Analog comparator 0/1 clock Disabled #0 1 Analog comparator 0/1 clock Enabled #1 ADCCKEN Analog-digital-converter Clock Enable Bit 28 1 read-write 0 ADC clock Disabled #0 1 ADC clock Enabled #1 CAN0CKEN CAN0 Clock Enable Bit 24 1 read-write 0 CAN0 clock Disabled #0 1 CAN0 clock Enabled #1 CLKOCKEN CLKO Clock Enable Bit 6 1 read-write 0 CLKO clock Disabled #0 1 CLKO clock Enabled #1 TMR0CKEN Timer0 Clock Enable Bit 2 1 read-write 0 Timer0 clock Disabled #0 1 Timer0 clock Enabled #1 TMR1CKEN Timer1 Clock Enable Bit 3 1 read-write 0 Timer1 clock Disabled #0 1 Timer1 clock Enabled #1 TMR2CKEN Timer2 Clock Enable Bit 4 1 read-write 0 Timer2 clock Disabled #0 1 Timer2 clock Enabled #1 TMR3CKEN Timer3 Clock Enable Bit 5 1 read-write 0 Timer3 clock Disabled #0 1 Timer3 clock Enabled #1 UART0CKEN UART0 Clock Enable Bit 16 1 read-write 0 UART0 clock Disabled #0 1 UART0 clock Enabled #1 UART1CKEN UART1 Clock Enable Bit 17 1 read-write 0 UART1 clock Disabled #0 1 UART1 clock Enabled #1 WDTCKEN Watchdog Timer Clock Enable Bit (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: This bit is reset by power on reset, Watchdog reset or software chip reset. 0 1 read-write 0 Watchdog timer clock Disabled #0 1 Watchdog timer clock Enabled #1 APBCLK1 CLK_APBCLK1 APB Devices Clock Enable Control Register 1 0xC -1 read-write n 0x0 0x0 DACCKEN DAC Clock Enable Bit 12 1 read-write 0 DAC clock Disabled #0 1 DAC clock Enabled #1 PWM0CKEN PWM0 Clock Enable Bit 16 1 read-write 0 PWM0 clock Disabled #0 1 PWM0 clock Enabled #1 USCI0CKEN USCI0 Clock Enable Bit 8 1 read-write 0 USCI0 clock Disabled #0 1 USCI0 clock Enabled #1 USCI1CKEN USCI1 Clock Enable Bit 9 1 read-write 0 USCI1 clock Disabled #0 1 USCI1 clock Enabled #1 CDLOWB CLK_CDLOWB Clock Frequency Range Detector Lower Boundary Register 0x7C -1 read-write n 0x0 0x0 LOWERBD HXT Clock Frequency Range Detector Lower Boundary Value The bits define the minimum value of frequency range detector window. When HXT frequency is lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will be set to 1. 0 10 read-write CDUPB CLK_CDUPB Clock Frequency Range Detector Upper Boundary Register 0x78 -1 read-write n 0x0 0x0 UPERBD HXT Clock Frequency Range Detector Upper Boundary Value The bits define the maximum value of frequency range detector window. When HXT frequency is higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will be set to 1. 0 10 read-write CLKDCTL CLK_CLKDCTL Clock Fail Detector Control Register 0x70 -1 read-write n 0x0 0x0 HXTFDEN HXT Clock Fail Detector Enable Bit 4 1 read-write 0 External high speed crystal oscillator (HXT) clock fail detector Disabled #0 1 External high speed crystal oscillator (HXT) clock fail detector Enabled #1 HXTFIEN HXT Clock Fail Interrupt Enable Bit 5 1 read-write 0 External high speed crystal oscillator (HXT) clock fail interrupt Disabled #0 1 External high speed crystal oscillator (HXT) clock fail interrupt Enabled #1 HXTFQDEN HXT Clock Frequency Range Detector Enable Bit 16 1 read-write 0 External high speed crystal oscillator (HXT) clock frequency range detector Disabled #0 1 External high speed crystal oscillator (HXT) clock frequency range detector Enabled #1 HXTFQIEN HXT Clock Frequency Range Detector Interrupt Enable Bit 17 1 read-write 0 External high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled #0 1 External high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled #1 LXTFDEN LXT Clock Fail Detector Enable Bit 12 1 read-write 0 External low speed crystal oscillator (LXT) clock fail detector Disabled #0 1 External low speed crystal oscillator (LXT) clock fail detector Enabled #1 LXTFIEN LXT Clock Fail Interrupt Enable Bit 13 1 read-write 0 External low speed crystal oscillator (LXT) clock fail interrupt Disabled #0 1 External low speed crystal oscillator (LXT) clock fail interrupt Enabled #1 CLKDIV0 CLK_CLKDIV0 Clock Divider Number Register 0 0x20 -1 read-write n 0x0 0x0 ADCDIV ADC Clock Divide Number From ADC Clock Source 16 8 read-write HCLKDIV HCLK Clock Divide Number From HCLK Clock Source 0 4 read-write UART0DIV UART0 Clock Divide Number From UART0 Clock Source 8 4 read-write UART1DIV UART1 Clock Divide Number From UART1 Clock Source 12 4 read-write CLKDSTS CLK_CLKDSTS Clock Fail Detector Status Register 0x74 -1 read-write n 0x0 0x0 HXTFIF HXT Clock Fail Interrupt Flag (Write Protect) Note: Write 1 to clear the bit to 0. 0 1 read-write 0 External high speed crystal oscillator (HXT) clock is normal #0 1 External high speed crystal oscillator (HXT) clock stops #1 HXTFQIF HXT Clock Frequency Range Detector Interrupt Flag (Write Protect) Note: Write 1 to clear the bit to 0. 8 1 read-write 0 External high speed crystal oscillator (HXT) clock frequency is normal #0 1 External high speed crystal oscillator (HXT) clock frequency is abnormal #1 LXTFIF LXT Clock Fail Interrupt Flag (Write Protect) Note: Write 1 to clear the bit to 0. 1 1 read-write 0 External low speed crystal oscillator (LXT) clock is normal #0 1 External low speed crystal oscillator (LXT) stops #1 CLKOCTL CLK_CLKOCTL Clock Output Control Register 0x60 -1 read-write n 0x0 0x0 CLKOEN Clock Output Enable Bit 4 1 read-write 0 Clock Output function Disabled #0 1 Clock Output function Enabled #1 DIV1EN Clock Output Divide One Enable Bit 5 1 read-write 0 Clock Output will output clock with source frequency divided by FREQSEL #0 1 Clock Output will output clock with source frequency #1 FREQSEL Clock Output Frequency Selection The formula of output frequency is Fin is the input clock frequency. Fout is the frequency of divider output clock. N is the 4-bit value of FREQSEL[3:0]. 0 4 read-write CLKSEL0 CLK_CLKSEL0 Clock Source Select Control Register 0 0x10 -1 read-write n 0x0 0x0 HCLKSEL HCLK Clock Source Selection (Write Protect) Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by power on reset 0 3 read-write 0 Clock source from HXT #000 1 Clock source from LXT #001 3 Clock source from LIRC #011 7 Clock source from HIRC #111 STCLKSEL Cortex-M0 SysTick Clock Source Selection (Write Protect) Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 3 3 read-write 0 Clock source from HXT #000 1 Clock source from LXT #001 2 Clock source from HXT/2 #010 3 Clock source from HCLK/2 #011 7 Clock source from HIRC/2 #111 CLKSEL1 CLK_CLKSEL1 Clock Source Select Control Register 1 0x14 -1 read-write n 0x0 0x0 CLKOSEL Clock Divider Clock Source Selection 4 3 read-write 0 Clock source from external high speed crystal oscillator (HXT) #000 1 Clock source from external low speed crystal oscillator (LXT) #001 2 Clock source from HCLK #010 4 Clock source from internal low speed RC oscillator (LIRC) #100 5 Clock source from internal high speed RC oscillator (HIRC) #101 TMR0SEL TIMER0 Clock Source Selection 8 3 read-write 0 Clock source from external high speed crystal oscillator (HXT) #000 1 Clock source from external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK0 #010 3 Clock source from external clock T0 pin #011 5 Clock source from internal low speed RC oscillator (LIRC) #101 7 Clock source from internal high speed RC oscillator (HIRC) #111 TMR1SEL TIMER1 Clock Source Selection 12 3 read-write 0 Clock source from external high speed crystal oscillator (HXT) #000 1 Clock source from external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK0 #010 3 Clock source from external clock T1 pin #011 5 Clock source from internal low speed RC oscillator (LIRC) #101 7 Clock source from internal high speed RC oscillator (HIRC) #111 TMR2SEL TIMER2 Clock Source Selection 16 3 read-write 0 Clock source from external high speed crystal oscillator (HXT) #000 1 Clock source from external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK1 #010 3 Clock source from external clock T2 pin #011 5 Clock source from internal low speed RC oscillator (LIRC) #101 7 Clock source from internal high speed RC oscillator (HIRC) #111 TMR3SEL TIMER3 Clock Source Selection 20 3 read-write 0 Clock source from external high speed crystal oscillator (HXT) #000 1 Clock source from external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK1 #010 3 Clock source from external clock T3 pin #011 5 Clock source from internal low speed RC oscillator (LIRC) #101 7 Clock source from internal high speed RC oscillator (HIRC) #111 UART0SEL UART0 Clock Source Selection 24 3 read-write 0 Clock source from external high speed crystal oscillator (HXT) #000 2 Clock source from external low speed crystal oscillator (LXT) #010 3 Clock source from internal high speed RC oscillator (HIRC) #011 4 Clock source from PCLK0 #100 5 Clock source from internal low speed RC oscillator (LIRC) #101 UART1SEL UART1 Clock Source Selection 28 3 read-write 0 Clock source from external high speed crystal oscillator (HXT) #000 2 Clock source from external low speed crystal oscillator (LXT) #010 3 Clock source from internal high speed RC oscillator (HIRC) #011 4 Clock source from PCLK1 #100 5 Clock source from internal low speed RC oscillator (LIRC) #101 WDTSEL Watchdog Timer Clock Source Selection (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2. It will be forced to 11 when CONFIG0[31], CONFIG0[4], CONFIG0[3] are all ones. 0 2 read-write 1 Clock source from external low speed crystal oscillator (LXT) #01 2 Clock source from HCLK/2048 #10 3 Clock source from internal low speed RC oscillator (LIRC) #11 WWDTSEL Window Watchdog Timer Clock Source Selection (Write Protect) 2 2 read-write 2 Clock source from HCLK/2048 #10 3 Clock source from internal low speed RC oscillator (LIRC) #11 CLKSEL2 CLK_CLKSEL2 Clock Source Select Control Register 2 0x18 -1 read-write n 0x0 0x0 ADCSEL ADC Clock Source Selection 20 2 read-write 0 Clock source from external high speed crystal oscillator (HXT) clock #00 1 Reserved. #01 2 Clock source from PCLK1 #10 3 Clock source from internal high speed RC oscillator (HIRC) clock #11 HXTFSEL CLK_HXTFSEL HXT Filter Select Control Register 0xB4 -1 read-write n 0x0 0x0 HXTFSEL HXT Filter Select Note: This bit should not be changed during HXT running. 0 1 read-write 0 HXT frequency is greater than12 MHz #0 1 HXT frequency is less than or equal to 12 MHz #1 PCLKDIV CLK_PCLKDIV APB Clock Divider Register 0x34 -1 read-write n 0x0 0x0 APB0DIV APB0 Clock DIvider APB0 clock can be divided from HCLK Others: Reserved. 0 3 read-write APB1DIV APB1 Clock DIvider APB1 clock can be divided from HCLK Others: Reserved. 4 3 read-write PWRCTL CLK_PWRCTL System Power-down Control Register 0x0 -1 read-write n 0x0 0x0 HIRCEN HIRC Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 Internal high speed RC oscillator (HIRC) Disabled #0 1 Internal high speed RC oscillator (HIRC) Enabled #1 HXTEN HXT Enable Bit (Write Protect) Note 1: Reset by power on reset. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Eexternal high speed crystal (HXT) Disabled #0 1 External high speed crystal (HXT) Enabled #1 HXTGAIN HXT Gain Control Bit (Write Protect) Please refer to HXT Charateristic. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 28 3 read-write HXTSELXT HXT Crystal Mode Selection Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 HXT works as external clock mode. PA.5 is configured as external clock input pin #0 1 HXT works as crystal mode. PA.4 and PA.5 are configured as high speed crystal (HXT) pins #1 LIRCEN LIRC Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 Internal low speed RC oscillator (LIRC) Disabled #0 1 Internal low speed RC oscillator (LIRC) Enabled #1 LXTEN LXT Enable Bit (Write Protect) Note 1: Reset by power on reset. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 External low speed crystal (LXT) Disabled #0 1 External low speed crystal (LXT) Enabled #1 LXTGAIN LXT Gain Control Bit (Write Protect) Please refer to LXT Charateristic. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 24 3 read-write LXTSELXT LXT Crystal Mode Selection Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 27 1 read-write 0 LXT works as external clock mode. PC.5 is configured as external clock input pin #0 1 LXT works as crystal mode. PC.4 and PC.5 are configured as low speed crystal (LXT) pins #1 PDEN System Power-down Enable (Write Protect) When this bit is set to 1, Power-down mode is enabled and chip keeps active utill the CPU sleep mode is also active and then the chip enters Power-down mode. When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down. In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. If user disable LIRC before entering power-down mode, this bit should be set after LIRC disabled 50us. In Power-down mode, system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Chip operating normally or chip in idle mode because of WFI command #0 1 Chip enters Power-down mode instant or wait CPU sleep command WFI #1 PDWKDLY Enable the Wake-up Delay Counter (Write Protect) When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip works at external high speed crystal oscillator (HXT), and 512 clock cycles when chip works at internal high speed RC oscillator (HIRC). Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 Clock cycles delay Disabled #0 1 Clock cycles delay Enabled #1 PDWKIEN Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) Note 1: The interrupt will occur when both PDWKIF and PDWKIEN are high. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 Power-down mode wake-up interrupt Disabled #0 1 Power-down mode wake-up interrupt Enabled #1 PDWKIF Power-down Mode Wake-up Interrupt Status Set by 'Power-down wake-up event', it indicates that resume from Power-down mode' The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter. Note 1: Write 1 to clear the bit to 0. Note 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. 6 1 read-write STATUS CLK_STATUS Clock Status Monitor Register 0x50 -1 read-only n 0x0 0x0 CLKSFAIL Clock Switching Fail Flag (Read Only) This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1. Note: Write 1 to clear the bit to 0. 7 1 read-only 0 Clock switching success #0 1 Clock switching failure #1 HIRCSTB HIRC Clock Source Stable Flag (Read Only) 4 1 read-only 0 Internal high speed RC oscillator (HIRC) clock is not stable or disabled #0 1 Internal high speed RC oscillator (HIRC) clock is stable and enabled #1 HXTSTB HXT Clock Source Stable Flag (Read Only) 0 1 read-only 0 External high speed crystal oscillator (HXT) clock is not stable or disabled #0 1 External high speed crystal oscillator (HXT) clock is stable and enabled #1 LIRCSTB LIRC Clock Source Stable Flag (Read Only) 3 1 read-only 0 Internal low speed RC oscillator (LIRC) clock is not stable or disabled #0 1 Internal low speed RC oscillator (LIRC) clock is stable and enabled #1 LXTSTB LXT Clock Source Stable Flag (Read Only) 1 1 read-only 0 External low speed crystal oscillator (LXT) clock is not stable or disabled #0 1 External low speed crystal oscillator (LXT) clock is stabled and enabled #1 CRC CRC Register Map CRC 0x0 0x0 0x10 registers n CHECKSUM CRC_CHECKSUM CRC Checksum Register 0xC -1 read-only n 0x0 0x0 CHECKSUM CRC Checksum Results This field indicates the CRC checksum result. Note: Data in CRC_CHECKSUM register has different length when user chooses different operation polynomial modes. For example: If final checksum result is 0x12 in CRC-8 polynomial mode, the CHECKSUM[31:0] value will be read as 0x12121212, only CHECKSUM[7:0] is valid in this mode. If final checksum result is 0x1234 in CRC-CCITT or CRC-16 mode, the CHECKSUM[31:0] value will be read as 0x12341234, only CHECKSUM[15:0] is valid in this mode. And the CHECKSUM[31:0] is valid for CRC-32 mode. 0 32 read-only CTL CRC_CTL CRC Control Register 0x0 -1 read-write n 0x0 0x0 CHKSFMT Checksum 1's Complement This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. 27 1 read-write 0 1's complement for CRC checksum Disabled #0 1 1's complement for CRC checksum Enabled #1 CHKSINIT Checksum Initialization Note: This bit will be cleared automatically. 1 1 read-write 0 No effect #0 1 Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value #1 CHKSREV Checksum Bit Order Reverse This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register. Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB. 25 1 read-write 0 Bit order reverse for CRC checksum Disabled #0 1 Bit order reverse for CRC checksum Enabled #1 CRCEN CRC Channel Enable Bit 0 1 read-write 0 No effect #0 1 CRC operation Enabled #1 CRCMODE CRC Polynomial Mode This field indicates the CRC operation polynomial mode. 30 2 read-write 0 CRC-CCITT Polynomial mode #00 1 CRC-8 Polynomial mode #01 2 CRC-16 Polynomial mode #10 3 CRC-32 Polynomial mode #11 DATFMT Write Data 1's Complement This bit is used to enable the 1's complement function for write data value in CRC_DAT register. 26 1 read-write 0 1's complement for CRC writes data in Disabled #0 1 1's complement for CRC writes data in Enabled #1 DATLEN CPU Write Data Length This field indicates the write data length. Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. 28 2 read-write 0 Data length is 8-bit mode #00 1 Data length is 16-bit mode. Data length is 32-bit mode #01 DATREV Write Data Bit Order Reverse This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register. Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB. 24 1 read-write 0 Bit order reversed for CRC write data in Disabled #0 1 Bit order reversed for CRC write data in Enabled (per byte) #1 DAT CRC_DAT CRC Write Data Register 0x4 -1 read-write n 0x0 0x0 DATA CRC Write Data Bits User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. 0 32 read-write SEED CRC_SEED CRC Seed Register 0x8 -1 read-write n 0x0 0x0 SEED CRC Seed Value This field indicates the CRC seed value. Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]). 0 32 read-write DAC DAC Register Map DAC 0x0 0x0 0x18 registers n CTL DAC_CTL DAC Control Register 0x0 -1 read-write n 0x0 0x0 DACEN DAC Enable Bit 0 1 read-write 0 DAC Disabled #0 1 DAC Enabled #1 DACIEN DAC Interrupt Enable Bit 1 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 DACPSEL DAC Reference Voltage Selection 9 1 read-write 0 Select AVDD (voltage of VDD pin) #0 1 Select VREF #1 DMAEN DMA Mode Enable Bit 2 1 read-write 0 DMA mode Disabled #0 1 DMA mode Enabled #1 DMAURIEN DMA Under-run Interrupt Enable Bit 3 1 read-write 0 DMA underrun interrupt Disabled #0 1 DMA underrun interrupt Enabled #1 OUTPUTOE DAC Output Enable 8 1 read-write 0 DAC output to PAD disabled #0 1 DAC otuput to PAD Enabled #1 TRGEN Trigger Mode Enable Bit 4 1 read-write 0 DAC event trigger mode Disabled #0 1 DAC event trigger mode Enabled #1 TRGSEL Trigger Source Selection 5 3 read-write 0 Software trigger #000 1 Reserved. #001 2 Timer 0 trigger #010 3 Timer 1 trigger #011 4 Timer 2 trigger #100 5 Timer 3 trigger #101 6 Reserved. #110 7 Reserved. #111 DAT DAC_DAT DAC Data Holding Register 0x8 -1 read-write n 0x0 0x0 DACDAT DAC 5-bit Holding Data These bits are written by user software which specifies 5-bit conversion data for DAC output. 0 5 read-write DATOUT DAC_DATOUT DAC Data Output Register 0xC -1 read-only n 0x0 0x0 DATOUT DAC 5-bit Output Data These bits are current digital data for DAC output conversion. It is loaded from DAC_DAT register and user cannot write it directly. 0 5 read-only STATUS DAC_STATUS DAC Status Register 0x10 -1 read-write n 0x0 0x0 BUSY DAC Busy Flag (Read Only) This is read only bit. 8 1 read-only 0 DAC is ready for next conversion #0 1 DAC is busy in conversion #1 DMAUDR DMA Under Run Interrupt Flag User writes 1 to clear this bit. 1 1 read-write 0 No DMA under-run error condition occurred #0 1 DMA under-run error condition occurred #1 FINISH DAC Conversion Complete Finish Flag This bit set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. User writes 1 to clear this bit to 0. 0 1 read-write 0 DAC is in conversion state #0 1 DAC conversion finish #1 SWTRG DAC_SWTRG DAC Software Trigger Control Register 0x4 -1 read-write n 0x0 0x0 SWTRG Software Trigger User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically Reading this bit will always get 0. 0 1 read-write 0 Software trigger Disabled #0 1 Software trigger Enabled #1 TCTL DAC_TCTL DAC Timing Control Register 0x14 -1 read-write n 0x0 0x0 SETTLET DAC Output Settling Time User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed. For example, DAC controller clock speed is 72 MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x48. 0 10 read-write FMC FMC Register Map FMC 0x0 0x0 0x18 registers n 0x40 0x4 registers n DFBA FMC_DFBA Data Flash Base Address 0x14 -1 read-only n 0x0 0x0 DFBA Data Flash Base Address This register indicates Data Flash start address. It is a read only register. The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1. 0 32 read-only ISPADDR FMC_ISPADDR ISP Address Register 0x4 -1 read-write n 0x0 0x0 ISPADDR ISP Address The M0A21/M0A23 is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. For CRC32 Checksum Calculation command, this field is the Flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation. 16/32 Kbytes Flash: ISPADR[8:0] must be kept all 0 for Vector Page Remap Command. 0 32 read-write ISPCMD FMC_ISPCMD ISP Command Register 0xC -1 read-write n 0x0 0x0 CMD ISP CMD ISP command table is shown below: The other commands are invalid. 0 7 read-write 0 Flash 32-bit Read 0x00 4 Read Unique ID 0x04 11 Read Company ID 0x0b 13 Read CRC32 Checksum 0x0d 33 Flash 32-bit Program 0x21 34 Flash Page Erase 0x22 45 Run CRC32 Checksum Calculation 0x2d 46 Vector Remap 0x2e ISPCTL FMC_ISPCTL ISP Control Register 0x0 -1 read-write n 0x0 0x0 APUEN APROM Update Enable Bit (Write Protect) Note: This bit is write-protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 APROM cannot be updated when the chip runs in APROM #0 1 APROM can be updated when the chip runs in APROM #1 BS Boot Selection (Write Protect) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened Note: This bit is write-protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Booting from APROM #0 1 Booting from LDROM #1 CFGUEN CONFIG Update Enable Bit (Write Protect) Note: This bit is write-protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 CONFIG cannot be updated #0 1 CONFIG can be updated #1 ISPEN ISP Enable Bit (Write Protect) Note: This bit is write-protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 ISP function Disabled #0 1 ISP function Enabled #1 ISPFF ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: APROM writes to itself if APUEN is set to 0. LDROM writes to itself if LDUEN is set to 0. CONFIG is erased/programmed if CFGUEN is set to 0. Page Erase command at LOCK mode with ICE connection. Erase or Program command at brown-out detected. Destination address is illegal, such as over an available range. Invalid ISP commands. This bit needs to be cleared by writing 1 to it. Note: This bit is write-protected. Refer to the SYS_REGLCTL register. 6 1 read-write LDUEN LDROM Update Enable Bit (Write Protect) LDROM update enable bit. Note: This bit is write-protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 LDROM cannot be updated #0 1 LDROM can be updated #1 ISPDAT FMC_ISPDAT ISP Data Register 0x8 -1 read-write n 0x0 0x0 ISPDAT ISP Data Write data to this register before ISP program operation. Read data from this register after ISP read operation. 0 32 read-write ISPSTS FMC_ISPSTS ISP Status Register 0x40 -1 read-write n 0x0 0x0 CBS Boot Selection of CONFIG (Read Only) This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened. 1 2 read-only 0 LDROM with IAP mode #00 1 LDROM without IAP mode #01 2 APROM with IAP mode #10 3 APROM without IAP mode #11 ISPBUSY ISP BUSY (Read Only) 0 1 read-only 0 ISP operation is finished #0 1 ISP operation is busy #1 ISPFF ISP Fail Flag (Write Protect) This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions: APROM writes to itself if APUEN is set to 0. LDROM writes to itself if LDUEN is set to 0. CONFIG is erased/programmed if CFGUEN is set to 0. Page Erase command at LOCK mode with ICE connection Erase or Program command at brown-out detected Destination address is illegal, such as over an available range. Invalid ISP commands 6 1 read-write VECMAP Vector Page Mapping Address (Read Only) All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}. VECMAP [18:12] should be 0. 9 21 read-only ISPTRG FMC_ISPTRG ISP Trigger Control Register 0x10 -1 read-write n 0x0 0x0 ISPGO ISP Start Trigger (Write Protect) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 0 1 read-write 0 ISP operation is finished #0 1 ISP is progressed.Note: This bit is write-protected. Refer to the SYS_REGLCTL register #1 GPIO GPIO Register Map GPIO 0x0 0x0 0x28 registers n 0x30 0x4 registers n 0x40 0x28 registers n 0x440 0x8 registers n 0x70 0x4 registers n 0x80 0x28 registers n 0x800 0x18 registers n 0x850 0x10 registers n 0x880 0x20 registers n 0x8C0 0x20 registers n 0xB0 0x4 registers n 0xC0 0x28 registers n 0xF0 0x4 registers n CLKON GPIO_CLKON GPIO Clock On-off Register 0x444 -1 read-write n 0x0 0x0 GPxOn GPIO Group Clock On-off The GPIO port clock can be disabled to reduce power consumption by setting GPIO_CLKON if the GPIO port isn't used. When GPxOn is set to 0 to diable GPIO port clock, the GPIO register, pin control and PDIO function are not workable. Only GPIO_CLKON and GPIO_DBCTL register can be updated 0 4 read-write 0 Disable GPIO group clock, include register pin control PDIO circuit 0 1 Enable GPIO group clock, include register pin control PDIO circuit 1 DBCTL GPIO_DBCTL Interrupt De-bounce Control Register 0x440 -1 read-write n 0x0 0x0 DBCLKSEL De-bounce Sampling Cycle Selection 0 4 read-write 0 Sample interrupt input once per 1 clocks #0000 1 Sample interrupt input once per 2 clocks #0001 2 Sample interrupt input once per 4 clocks #0010 3 Sample interrupt input once per 8 clocks #0011 4 Sample interrupt input once per 16 clocks #0100 5 Sample interrupt input once per 32 clocks #0101 6 Sample interrupt input once per 64 clocks #0110 7 Sample interrupt input once per 128 clocks #0111 8 Sample interrupt input once per 256 clocks #1000 9 Sample interrupt input once per 2*256 clocks #1001 10 Sample interrupt input once per 4*256 clocks #1010 11 Sample interrupt input once per 8*256 clocks #1011 12 Sample interrupt input once per 16*256 clocks #1100 13 Sample interrupt input once per 32*256 clocks #1101 14 Sample interrupt input once per 64*256 clocks #1110 15 Sample interrupt input once per 128*256 clocks #1111 DBCLKSRC De-bounce Counter Clock Source Selection 4 1 read-write 0 De-bounce counter clock source is the HCLK #0 1 De-bounce counter clock source is the 38.4 kHz internal low speed RC oscillator (LIRC) #1 ICLKONx Interrupt Clock on Mode Note: It is recommended to disable this bit to save system power if no special application concern. Each bit control each GPIO group. 16 4 read-write 0 Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1 0 1 All I/O pins edge detection circuit is always active after reset 1 PA0_PDIO PA0_PDIO GPIO PA.n Pin Data Input/Output Register 0x800 -1 read-write n 0x0 0x0 PDIO GPIO Px.n Pin Data Input/Output Writing this bit can control one GPIO pin output value. Read this register to get GPIO pin status. For example, writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]), reading PA0_PDIO will return the value of PIN (PA_PIN[0]). Note 1: The writing operation will not be affected by register DATMSK (Px_DATMSK[n]). Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3:The GPA.3 is a input pin. 0 1 read-write 0 Corresponding GPIO pin set to low #0 1 Corresponding GPIO pin set to high #1 PA1_PDIO PA1_PDIO GPIO PA.n Pin Data Input/Output Register 0x804 -1 read-write n 0x0 0x0 PA2_PDIO PA2_PDIO GPIO PA.n Pin Data Input/Output Register 0x808 -1 read-write n 0x0 0x0 PA3_PDIO PA3_PDIO GPIO PA.n Pin Data Input/Output Register 0x80C -1 read-write n 0x0 0x0 PA4_PDIO PA4_PDIO GPIO PA.n Pin Data Input/Output Register 0x810 -1 read-write n 0x0 0x0 PA5_PDIO PA5_PDIO GPIO PA.n Pin Data Input/Output Register 0x814 -1 read-write n 0x0 0x0 PA_DATMSK PA_DATMSK PA Data Output Write Mask 0xC -1 read-write n 0x0 0x0 DATMSK0 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 0 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK1 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 1 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK10 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 10 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK11 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 11 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK12 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 12 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK13 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 13 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK14 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 14 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK15 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 15 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK2 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 2 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK3 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 3 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK4 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 4 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK5 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 5 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK6 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 6 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK7 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 7 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK8 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 8 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK9 Port A-D Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 9 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 PA_DBEN PA_DBEN PA De-bounce Enable Control Register 0x14 -1 read-write n 0x0 0x0 DBEN0 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 0 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN1 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 1 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN10 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 10 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN11 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 11 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN12 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 12 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN13 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 13 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN14 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 14 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN15 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 15 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN2 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 2 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN3 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 3 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN4 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 4 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN5 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 5 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN6 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 6 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN7 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 7 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN8 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 8 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN9 Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 9 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 PA_DINOFF PA_DINOFF PA Digital Input Path Disable Control 0x4 -1 read-write n 0x0 0x0 DINOFF0 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 16 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF1 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 17 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF10 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 26 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF11 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 27 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF12 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 28 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF13 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 29 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF14 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 30 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF15 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 31 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF2 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 18 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF3 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 19 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF4 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 20 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF5 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 21 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF6 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 22 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF7 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 23 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF8 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 24 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF9 Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 25 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 PA_DOUT PA_DOUT PA Data Output Value 0x8 -1 read-write n 0x0 0x0 DOUT0 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 0 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT1 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 1 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT10 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 10 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT11 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 11 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT12 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 12 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT13 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 13 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT14 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 14 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT15 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 15 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT2 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 2 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT3 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 3 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT4 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 4 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT5 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 5 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT6 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 6 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT7 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 7 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT8 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 8 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT9 Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin. 9 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 PA_INTEN PA_INTEN PA Interrupt Enable Control Register 0x1C -1 read-write n 0x0 0x0 FLIEN0 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 0 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN1 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 1 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN10 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 10 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN11 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 11 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN12 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 12 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN13 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 13 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN14 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 14 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN15 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 15 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN2 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 2 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN3 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 3 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN4 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 4 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN5 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 5 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN6 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 6 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN7 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 7 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN8 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 8 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN9 Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 9 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 RHIEN0 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 16 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN1 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 17 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN10 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 26 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN11 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 27 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN12 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 28 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN13 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 29 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN14 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 30 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN15 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 31 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN2 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 18 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN3 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 19 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN4 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 20 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN5 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 21 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN6 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 22 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN7 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 23 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN8 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 24 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN9 Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 25 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 PA_INTSRC PA_INTSRC PA Interrupt Source Flag 0x20 -1 read-write n 0x0 0x0 INTSRC0 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 0 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC1 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 1 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC10 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 10 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC11 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 11 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC12 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 12 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC13 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 13 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC14 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 14 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC15 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 15 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC2 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 2 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC3 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 3 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC4 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 4 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC5 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 5 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC6 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 6 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC7 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 7 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC8 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 8 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC9 Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 9 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 PA_INTTYPE PA_INTTYPE PA Interrupt Trigger Type Control 0x18 -1 read-write n 0x0 0x0 TYPE0 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 0 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE1 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 1 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE10 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 10 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE11 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 11 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE12 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 12 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE13 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 13 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE14 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 14 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE15 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 15 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE2 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 2 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE3 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 3 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE4 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 4 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE5 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 5 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE6 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 6 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE7 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 7 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE8 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 8 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE9 Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 9 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 PA_MODE PA_MODE PA I/O Mode Control 0x0 -1 read-write n 0x0 0x0 MODE0 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 0 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE1 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 2 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE10 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 20 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE11 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 22 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE12 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 24 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE13 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 26 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE14 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 28 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE15 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 30 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE2 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 4 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE3 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 6 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE4 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 8 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE5 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 10 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE6 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 12 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE7 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 14 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE8 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 16 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE9 Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored. 18 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 PA_PIN PA_PIN PA Pin Value 0x10 -1 read-only n 0x0 0x0 PIN0 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 0 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PIN1 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 1 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PIN10 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 10 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PIN11 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 11 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PIN12 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 12 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PIN13 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 13 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PIN14 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 14 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PIN15 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 15 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PIN2 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 2 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PIN3 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 3 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PIN4 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 4 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PIN5 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 5 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PIN6 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 6 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PIN7 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 7 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PIN8 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 8 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PIN9 Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 9 1 read-only 0 The corresponding pin status is low #0 1 The corresponding pin status is high #1 PA_PUSEL PA_PUSEL PA Pull-up Selection Register 0x30 -1 read-write n 0x0 0x0 PUSEL0 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 0 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL1 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 1 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL10 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 10 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL11 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 11 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL12 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 12 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL13 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 13 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL14 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 14 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL15 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 15 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL2 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 2 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL3 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 3 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL4 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 4 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL5 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 5 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL6 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 6 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL7 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 7 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL8 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 8 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL9 Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 9 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PA_SMTEN PA_SMTEN PA Input Schmitt Trigger Enable Register 0x24 -1 read-write n 0x0 0x0 SMTEN0 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 0 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN1 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 1 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN10 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 10 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN11 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 11 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN12 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 12 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN13 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 13 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN14 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 14 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN15 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 15 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN2 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 2 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN3 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 3 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN4 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 4 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN5 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 5 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN6 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 6 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN7 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 7 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN8 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 8 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN9 Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. 9 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 PB4_PDIO PB4_PDIO GPIO PB.n Pin Data Input/Output Register 0x850 -1 read-write n 0x0 0x0 PB5_PDIO PB5_PDIO GPIO PB.n Pin Data Input/Output Register 0x854 -1 read-write n 0x0 0x0 PB6_PDIO PB6_PDIO GPIO PB.n Pin Data Input/Output Register 0x858 -1 read-write n 0x0 0x0 PB7_PDIO PB7_PDIO GPIO PB.n Pin Data Input/Output Register 0x85C -1 read-write n 0x0 0x0 PB_DATMSK PB_DATMSK PB Data Output Write Mask 0x4C -1 read-write n 0x0 0x0 PB_DBEN PB_DBEN PB De-bounce Enable Control Register 0x54 -1 read-write n 0x0 0x0 PB_DINOFF PB_DINOFF PB Digital Input Path Disable Control 0x44 -1 read-write n 0x0 0x0 PB_DOUT PB_DOUT PB Data Output Value 0x48 -1 read-write n 0x0 0x0 PB_INTEN PB_INTEN PB Interrupt Enable Control Register 0x5C -1 read-write n 0x0 0x0 PB_INTSRC PB_INTSRC PB Interrupt Source Flag 0x60 -1 read-write n 0x0 0x0 PB_INTTYPE PB_INTTYPE PB Interrupt Trigger Type Control 0x58 -1 read-write n 0x0 0x0 PB_MODE PB_MODE PB I/O Mode Control 0x40 -1 read-write n 0x0 0x0 PB_PIN PB_PIN PB Pin Value 0x50 -1 read-write n 0x0 0x0 PB_PUSEL PB_PUSEL PB Pull-up Selection Register 0x70 -1 read-write n 0x0 0x0 PB_SMTEN PB_SMTEN PB Input Schmitt Trigger Enable Register 0x64 -1 read-write n 0x0 0x0 PC0_PDIO PC0_PDIO GPIO PC.n Pin Data Input/Output Register 0x880 -1 read-write n 0x0 0x0 PC1_PDIO PC1_PDIO GPIO PC.n Pin Data Input/Output Register 0x884 -1 read-write n 0x0 0x0 PC2_PDIO PC2_PDIO GPIO PC.n Pin Data Input/Output Register 0x888 -1 read-write n 0x0 0x0 PC3_PDIO PC3_PDIO GPIO PC.n Pin Data Input/Output Register 0x88C -1 read-write n 0x0 0x0 PC4_PDIO PC4_PDIO GPIO PC.n Pin Data Input/Output Register 0x890 -1 read-write n 0x0 0x0 PC5_PDIO PC5_PDIO GPIO PC.n Pin Data Input/Output Register 0x894 -1 read-write n 0x0 0x0 PC6_PDIO PC6_PDIO GPIO PC.n Pin Data Input/Output Register 0x898 -1 read-write n 0x0 0x0 PC7_PDIO PC7_PDIO GPIO PC.n Pin Data Input/Output Register 0x89C -1 read-write n 0x0 0x0 PC_DATMSK PC_DATMSK PC Data Output Write Mask 0x8C -1 read-write n 0x0 0x0 PC_DBEN PC_DBEN PC De-bounce Enable Control Register 0x94 -1 read-write n 0x0 0x0 PC_DINOFF PC_DINOFF PC Digital Input Path Disable Control 0x84 -1 read-write n 0x0 0x0 PC_DOUT PC_DOUT PC Data Output Value 0x88 -1 read-write n 0x0 0x0 PC_INTEN PC_INTEN PC Interrupt Enable Control Register 0x9C -1 read-write n 0x0 0x0 PC_INTSRC PC_INTSRC PC Interrupt Source Flag 0xA0 -1 read-write n 0x0 0x0 PC_INTTYPE PC_INTTYPE PC Interrupt Trigger Type Control 0x98 -1 read-write n 0x0 0x0 PC_MODE PC_MODE PC I/O Mode Control 0x80 -1 read-write n 0x0 0x0 PC_PIN PC_PIN PC Pin Value 0x90 -1 read-write n 0x0 0x0 PC_PUSEL PC_PUSEL PC Pull-up Selection Register 0xB0 -1 read-write n 0x0 0x0 PC_SMTEN PC_SMTEN PC Input Schmitt Trigger Enable Register 0xA4 -1 read-write n 0x0 0x0 PD0_PDIO PD0_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C0 -1 read-write n 0x0 0x0 PD1_PDIO PD1_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C4 -1 read-write n 0x0 0x0 PD2_PDIO PD2_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C8 -1 read-write n 0x0 0x0 PD3_PDIO PD3_PDIO GPIO PD.n Pin Data Input/Output Register 0x8CC -1 read-write n 0x0 0x0 PD4_PDIO PD4_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D0 -1 read-write n 0x0 0x0 PD5_PDIO PD5_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D4 -1 read-write n 0x0 0x0 PD6_PDIO PD6_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D8 -1 read-write n 0x0 0x0 PD7_PDIO PD7_PDIO GPIO PD.n Pin Data Input/Output Register 0x8DC -1 read-write n 0x0 0x0 PD_DATMSK PD_DATMSK PD Data Output Write Mask 0xCC -1 read-write n 0x0 0x0 PD_DBEN PD_DBEN PD De-bounce Enable Control Register 0xD4 -1 read-write n 0x0 0x0 PD_DINOFF PD_DINOFF PD Digital Input Path Disable Control 0xC4 -1 read-write n 0x0 0x0 PD_DOUT PD_DOUT PD Data Output Value 0xC8 -1 read-write n 0x0 0x0 PD_INTEN PD_INTEN PD Interrupt Enable Control Register 0xDC -1 read-write n 0x0 0x0 PD_INTSRC PD_INTSRC PD Interrupt Source Flag 0xE0 -1 read-write n 0x0 0x0 PD_INTTYPE PD_INTTYPE PD Interrupt Trigger Type Control 0xD8 -1 read-write n 0x0 0x0 PD_MODE PD_MODE PD I/O Mode Control 0xC0 -1 read-write n 0x0 0x0 PD_PIN PD_PIN PD Pin Value 0xD0 -1 read-write n 0x0 0x0 PD_PUSEL PD_PUSEL PD Pull-up Selection Register 0xF0 -1 read-write n 0x0 0x0 PD_SMTEN PD_SMTEN PD Input Schmitt Trigger Enable Register 0xE4 -1 read-write n 0x0 0x0 HDIV HDIV Register Map HDIV 0x0 0x0 0x14 registers n DIVIDEND DIVIDEND Dividend Source Register 0x0 -1 read-write n 0x0 0x0 DIVIDEND Dividend Source This register is given the dividend of divider before calculation started. 0 32 read-write DIVISOR DIVISOR Divisor Source Resister 0x4 -1 read-write n 0x0 0x0 DIVISOR Divisor Source This register is given the divisor of divider before calculation starts. Note: When this register is written, hardware divider will start calculation. 0 16 read-write DIVQUO DIVQUO Quotient Result Resister 0x8 -1 read-write n 0x0 0x0 QUOTIENT Quotient Result This register holds the quotient result of divider after calculation is complete. 0 32 read-write DIVREM DIVREM Remainder Result Register 0xC -1 read-write n 0x0 0x0 REMAINDER15_0 Remainder Result This register holds the remainder result of divider after calculation is complete. 0 16 read-write REMAINDER31_16 Sign Extension of REMAINDER[15:0] The remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]) with sign extension (REMAINDER[31:16]) to 32-bit integer. 16 16 read-write DIVSTS DIVSTS Divider Status Register 0x10 -1 read-only n 0x0 0x0 DIV0 Divisor Zero Warning (Read Only) Note: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written. This register is read only. 1 1 read-only 0 The divisor is not 0 #0 1 The divisor is 0 #1 NMI NMI Register Map NMI 0x0 0x0 0x8 registers n NMIEN NMIEN NMI Source Interrupt Enable Register 0x0 -1 read-write n 0x0 0x0 BODOUT BOD NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 BOD NMI source Disabled #0 1 BOD NMI source Enabled #1 CLKFAIL Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 Clock fail detected and IRC Auto Trim interrupt NMI source Disabled #0 1 Clock fail detected and IRC Auto Trim interrupt NMI source Enabled #1 EINT0 External Interrupt From PA.3 or PB.5 Pin NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 8 1 read-write 0 External interrupt from PA.3 or PB.5 pin NMI source Disabled #0 1 External interrupt from PA.3 or PB.5 pin NMI source Enabled #1 EINT1 External Interrupt From PC.5 Pin NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 9 1 read-write 0 External interrupt from PC.5 pin NMI source Disabled #0 1 External interrupt from PC.5 pin NMI source Enabled #1 EINT2 External Interrupt From PC.4 Pin NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 10 1 read-write 0 External interrupt from PC.4 pin NMI source Disabled #0 1 External interrupt from PC.4 pin NMI source Enabled #1 EINT3 External Interrupt From PC.3 Pin NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 11 1 read-write 0 External interrupt from PC.3 pin NMI source Disabled #0 1 External interrupt from PC.3 pin NMI source Enabled #1 EINT4 External Interrupt From PC.6 Pin NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 12 1 read-write 0 External interrupt from PC.6 pin NMI source Disabled #0 1 External interrupt from PC.6 pin NMI source Enabled #1 EINT5 External Interrupt From PC.7 Pin NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 13 1 read-write 0 External interrupt from PC.7 pin NMI source Disabled #0 1 External interrupt from PC.7 pin NMI source Enabled #1 IRC_INT IRC TRIM NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 IRC TRIM NMI source Disabled #0 1 IRC TRIM NMI source Enabled #1 PWRWU_INT Power-down Mode Wake-up NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 Power-down mode wake-up NMI source Disabled #0 1 Power-down mode wake-up NMI source Enabled #1 UART0_INT UART0 NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 14 1 read-write 0 UART0 NMI source Disabled #0 1 UART0 NMI source Enabled #1 UART1_INT UART1 NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 15 1 read-write 0 UART1 NMI source Disabled #0 1 UART1 NMI source Enabled #1 NMISTS NMISTS NMI Source Interrupt Status Register 0x4 -1 read-only n 0x0 0x0 BODOUT BOD Interrupt Flag (Read Only) 0 1 read-only 0 BOD interrupt is deasserted #0 1 BOD interrupt is asserted #1 CLKFAIL Clock Fail Detected or IRC Auto Trim Interrupt Flag (Read Only) 4 1 read-only 0 Clock fail detected or IRC Auto Trim interrupt is deasserted #0 1 Clock fail detected or IRC Auto Trim interrupt is asserted #1 EINT0 External Interrupt From PA.3 or PB.5 Pin Interrupt Flag (Read Only) 8 1 read-only 0 External Interrupt from PA.3 or PB.5 interrupt is deasserted #0 1 External Interrupt from PA.3 or PB.5 interrupt is asserted #1 EINT1 External Interrupt From PC.5 Pin Interrupt Flag (Read Only) 9 1 read-only 0 External Interrupt from PC.5 interrupt is deasserted #0 1 External Interrupt from PC.5 interrupt is asserted #1 EINT2 External Interrupt From PC.4 Pin Interrupt Flag (Read Only) 10 1 read-only 0 External Interrupt from PC.4 interrupt is deasserted #0 1 External Interrupt from PC.4 interrupt is asserted #1 EINT3 External Interrupt From PC.3 Pin Interrupt Flag (Read Only) 11 1 read-only 0 External Interrupt from PC.3 interrupt is deasserted #0 1 External Interrupt from PC.3 interrupt is asserted #1 EINT4 External Interrupt From PC.6 Pin Interrupt Flag (Read Only) 12 1 read-only 0 External Interrupt from PC.6 interrupt is deasserted #0 1 External Interrupt from PC.6 interrupt is asserted #1 EINT5 External Interrupt From PC.7 Pin Interrupt Flag (Read Only) 13 1 read-only 0 External Interrupt from PC.7 interrupt is deasserted #0 1 External Interrupt from PC.7 interrupt is asserted #1 IRC_INT IRC TRIM Interrupt Flag (Read Only) 1 1 read-only 0 HIRC TRIM interrupt is deasserted #0 1 HIRC TRIM interrupt is asserted #1 PWRWU_INT Power-down Mode Wake-up Interrupt Flag (Read Only) 2 1 read-only 0 Power-down mode wake-up interrupt is deasserted #0 1 Power-down mode wake-up interrupt is asserted #1 UART0_INT UART0 Interrupt Flag (Read Only) 14 1 read-only 0 UART1 interrupt is deasserted #0 1 UART1 interrupt is asserted #1 UART1_INT UART1 Interrupt Flag (Read Only) 15 1 read-only 0 UART1 interrupt is deasserted #0 1 UART1 interrupt is asserted #1 NVIC NVIC Register Map NVIC 0x0 0x0 0x4 registers n 0x100 0x4 registers n 0x180 0x4 registers n 0x200 0x4 registers n 0x80 0x4 registers n IABR0 NVIC_IABR0 IRQ0 ~ IRQ31 Active Bit Register 0x200 -1 read-write n 0x0 0x0 ACTIVE Interrupt Active Flags The NVIC_IABR0 registers indicate which interrupts are active. 0 32 read-write 0 interrupt not active 0 1 interrupt active 1 ICER0 NVIC_ICER0 IRQ0 ~ IRQ31 Clear-enable Control Register 0x80 -1 read-write n 0x0 0x0 CALENA Interrupt Clear Enable Bit The NVIC_ICER0 registers disable interrupts, and show which interrupts are enabled. Write Operation: 0 32 read-write 0 No effect. Interrupt Disabled 0 1 Interrupt Disabled. Interrupt Enabled 1 ICPR0 NVIC_ICPR0 IRQ0 ~ IRQ31 Clear-pending Control Register 0x180 -1 read-write n 0x0 0x0 CALPEND Interrupt Clear-pending The NVIC_ICPR0 registers remove the pending state from interrupts, and show which interrupts are pending Write Operation: 0 32 read-write 0 No effect. Interrupt is not pending 0 1 Removes pending state an interrupt. Interrupt is pending 1 ISER0 NVIC_ISER0 IRQ0 ~ IRQ31 Set-enable Control Register 0x0 -1 read-write n 0x0 0x0 SETENA Interrupt Set Enable Bit The NVIC_ISER0 registers enable interrupts, and show which interrupts are enabled Write Operation: 0 32 read-write 0 No effect. Interrupt Disabled 0 1 Interrupt Enabled 1 ISPR0 NVIC_ISPR0 IRQ0 ~ IRQ31 Set-pending Control Register 0x100 -1 read-write n 0x0 0x0 SETPEND Interrupt Set-pending The NVIC_ISPR0 registers force interrupts into the pending state, and show which interrupts are pending Write Operation: 0 32 read-write 0 No effect. Interrupt is not pending 0 1 Changes interrupt state to pending. Interrupt is pending 1 PDMA PDMA Register Map PDMA 0x0 0x0 0x50 registers n 0x100 0x14 registers n 0x400 0x44 registers n 0x460 0x4 registers n 0x480 0x8 registers n ABTSTS PDMA_ABTSTS PDMA Channel Read/Write Target Abort Flag Register 0x420 -1 read-write n 0x0 0x0 ABTIF0 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. 0 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF1 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. 1 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF2 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. 2 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF3 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. 3 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF4 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. 4 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ALIGN PDMA_ALIGN PDMA Transfer Alignment Status Register 0x428 -1 read-write n 0x0 0x0 ALIGN0 Transfer Alignment Flag This bit indicates whether source and destination address both follow transfer width setting, user can write 1 to clear these bits. 0 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN1 Transfer Alignment Flag This bit indicates whether source and destination address both follow transfer width setting, user can write 1 to clear these bits. 1 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN2 Transfer Alignment Flag This bit indicates whether source and destination address both follow transfer width setting, user can write 1 to clear these bits. 2 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN3 Transfer Alignment Flag This bit indicates whether source and destination address both follow transfer width setting, user can write 1 to clear these bits. 3 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN4 Transfer Alignment Flag This bit indicates whether source and destination address both follow transfer width setting, user can write 1 to clear these bits. 4 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 CHCTL PDMA_CHCTL PDMA Channel Control Register 0x400 -1 read-write n 0x0 0x0 CHEN0 PDMA Channel Enable Bits Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 0 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN1 PDMA Channel Enable Bits Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 1 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN2 PDMA Channel Enable Bits Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 2 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN3 PDMA Channel Enable Bits Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 3 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN4 PDMA Channel Enable Bits Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 4 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHRST PDMA_CHRST PDMA Channel Reset Register 0x460 -1 read-write n 0x0 0x0 CHnRST Channel n Reset 0 5 read-write 0 corresponding channel n is not reset 0 1 corresponding channel n is reset 1 CURSCAT0 PDMA_CURSCAT0 Current Scatter-gather Descriptor Table Address of PDMA Channel n 0x100 -1 read-only n 0x0 0x0 CURADDR PDMA Current Description Address (Read Only) This field indicates a 32-bit current external description address of PDMA controller. Note: This field is read only and used for Scatter-Gather mode only to indicate the current external description address. 0 32 read-only CURSCAT1 PDMA_CURSCAT1 Current Scatter-gather Descriptor Table Address of PDMA Channel n 0x104 -1 read-write n 0x0 0x0 CURSCAT2 PDMA_CURSCAT2 Current Scatter-gather Descriptor Table Address of PDMA Channel n 0x108 -1 read-write n 0x0 0x0 CURSCAT3 PDMA_CURSCAT3 Current Scatter-gather Descriptor Table Address of PDMA Channel n 0x10C -1 read-write n 0x0 0x0 CURSCAT4 PDMA_CURSCAT4 Current Scatter-gather Descriptor Table Address of PDMA Channel n 0x110 -1 read-write n 0x0 0x0 DSCT0_CTL PDMA_DSCT0_CTL Descriptor Table Control Register of PDMA Channel n 0x0 -1 read-write n 0x0 0x0 BURSIZE Burst Size Note: This field is only useful in burst transfer type. 4 3 read-write 0 128 Transfers #000 1 64 Transfers #001 2 32 Transfers #010 3 16 Transfers #011 4 8 Transfers #100 5 4 Transfers #101 6 2 Transfers #110 7 1 Transfers #111 DAINC Destination Address Increment This field is used to set the destination address increment size. Note: The fixed address function does not support in memory to memory transfer type. 10 2 read-write 3 No increment (fixed address) #11 OPMODE PDMA Operation Mode Selection Note: Before filling new transfer task in the Descriptor Table, user must check the PDMA_INTSTS[1] to make sure the curren task is complete. 0 2 read-write 0 Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically #00 1 Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[1] will be asserted #01 2 Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register PDMA controller will ignore this task, then load the next task to execute #10 3 Reserved. #11 SAINC Source Address Increment This field is used to set the source address increment size. Note: The fixed address function does not support in memory to memory transfer type. 8 2 read-write 3 No increment (fixed address) #11 TBINTDIS Table Interrupt Disable Bit This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[4:0]) when PDMA controller finishes transfer task. Note: This function is only for scatter-gather mode. 7 1 read-write 0 Table interrupt Enabled #0 1 Table interrupt Disabled #1 TXCNT Transfer Count The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 16384, every transfer may be byte, half-word or word that is dependent on TXWIDTH field. Note: When PDMA finishes each transfer data, this field will be decrease immediately. 16 16 read-write TXTYPE Transfer Type 2 1 read-write 0 Burst transfer type #0 1 Single transfer type #1 TXWIDTH Transfer Width Selection This field is used for transfer width. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection 12 2 read-write 0 One byte (8 bit) is transferred for every operation #00 1 One half-word (16 bit) is transferred for every operation #01 2 One word (32-bit) is transferred for every operation #10 3 Reserved. #11 DSCT0_DA PDMA_DSCT0_DA Destination Address Register of PDMA Channel n 0x8 -1 read-write n 0x0 0x0 DA PDMA Transfer Destination Address This field indicates a 32-bit destination address of PDMA controller. 0 32 read-write DSCT0_NEXT PDMA_DSCT0_NEXT Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n 0xC -1 read-write n 0x0 0x0 EXENEXT PDMA Execution Next Descriptor Table Offset This field indicates the offset of next descriptor table address of current execution descriptor table in system memory. Note: Write operation is useless in this field. 16 16 read-write NEXT PDMA Next Descriptor Table Offset This field indicates the offset of the next descriptor table address in system memory. Write Operation: If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100. Read Operation: When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory. Note 1: The descriptor table address must be word boundary. Note 2: Before filling transfer task in the descriptor table, user must check if the descriptor table is complete. 0 16 read-write DSCT0_SA PDMA_DSCT0_SA Source Address Register of PDMA Channel n 0x4 -1 read-write n 0x0 0x0 SA PDMA Transfer Source Address This field indicates a 32-bit source address of PDMA controller. 0 32 read-write DSCT1_CTL PDMA_DSCT1_CTL Descriptor Table Control Register of PDMA Channel n 0x10 -1 read-write n 0x0 0x0 DSCT1_DA PDMA_DSCT1_DA Destination Address Register of PDMA Channel n 0x18 -1 read-write n 0x0 0x0 DSCT1_NEXT PDMA_DSCT1_NEXT Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n 0x1C -1 read-write n 0x0 0x0 DSCT1_SA PDMA_DSCT1_SA Source Address Register of PDMA Channel n 0x14 -1 read-write n 0x0 0x0 DSCT2_CTL PDMA_DSCT2_CTL Descriptor Table Control Register of PDMA Channel n 0x20 -1 read-write n 0x0 0x0 DSCT2_DA PDMA_DSCT2_DA Destination Address Register of PDMA Channel n 0x28 -1 read-write n 0x0 0x0 DSCT2_NEXT PDMA_DSCT2_NEXT Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n 0x2C -1 read-write n 0x0 0x0 DSCT2_SA PDMA_DSCT2_SA Source Address Register of PDMA Channel n 0x24 -1 read-write n 0x0 0x0 DSCT3_CTL PDMA_DSCT3_CTL Descriptor Table Control Register of PDMA Channel n 0x30 -1 read-write n 0x0 0x0 DSCT3_DA PDMA_DSCT3_DA Destination Address Register of PDMA Channel n 0x38 -1 read-write n 0x0 0x0 DSCT3_NEXT PDMA_DSCT3_NEXT Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n 0x3C -1 read-write n 0x0 0x0 DSCT3_SA PDMA_DSCT3_SA Source Address Register of PDMA Channel n 0x34 -1 read-write n 0x0 0x0 DSCT4_CTL PDMA_DSCT4_CTL Descriptor Table Control Register of PDMA Channel n 0x40 -1 read-write n 0x0 0x0 DSCT4_DA PDMA_DSCT4_DA Destination Address Register of PDMA Channel n 0x48 -1 read-write n 0x0 0x0 DSCT4_NEXT PDMA_DSCT4_NEXT Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n 0x4C -1 read-write n 0x0 0x0 DSCT4_SA PDMA_DSCT4_SA Source Address Register of PDMA Channel n 0x44 -1 read-write n 0x0 0x0 INTEN PDMA_INTEN PDMA Interrupt Enable Register 0x418 -1 read-write n 0x0 0x0 INTEN0 PDMA Interrupt Enable Bits This field is used to enable PDMA channel[n] interrupt. Note: The interrupt flag is time-out, abort, transfer done and align. 0 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN1 PDMA Interrupt Enable Bits This field is used to enable PDMA channel[n] interrupt. Note: The interrupt flag is time-out, abort, transfer done and align. 1 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN2 PDMA Interrupt Enable Bits This field is used to enable PDMA channel[n] interrupt. Note: The interrupt flag is time-out, abort, transfer done and align. 2 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN3 PDMA Interrupt Enable Bits This field is used to enable PDMA channel[n] interrupt. Note: The interrupt flag is time-out, abort, transfer done and align. 3 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN4 PDMA Interrupt Enable Bits This field is used to enable PDMA channel[n] interrupt. Note: The interrupt flag is time-out, abort, transfer done and align. 4 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTSTS PDMA_INTSTS PDMA Interrupt Status Register 0x41C -1 read-write n 0x0 0x0 ABTIF PDMA Read/Write Target Abort Interrupt Flag (Read Only) This bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error. 0 1 read-only 0 No AHB bus ERROR response received #0 1 AHB bus ERROR response received #1 ALIGNF Transfer Alignment Interrupt Flag (Read Only) 2 1 read-only 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 REQTOF0 Request Time-out Flag for Channel 0 This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits. Note: Please disable time-out function before clearing this bit. 8 1 read-write 0 No request time-out #0 1 Peripheral request time-out #1 REQTOF1 Request Time-out Flag for Channel 1 This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits. Note: Please disable time-out function before clearing this bit. 9 1 read-write 0 No request time-out #0 1 Peripheral request time-out #1 TDIF Transfer Done Interrupt Flag (Read Only) This bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer. 1 1 read-only 0 Not finished yet #0 1 PDMA channel has finished transmission #1 PAUSE PDMA_PAUSE PDMA Transfer Pause Control Register 0x404 -1 write-only n 0x0 0x0 PAUSE0 PDMA Channel n Transfer Pause Control (Write Only) 0 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE1 PDMA Channel n Transfer Pause Control (Write Only) 1 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE2 PDMA Channel n Transfer Pause Control (Write Only) 2 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE3 PDMA Channel n Transfer Pause Control (Write Only) 3 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE4 PDMA Channel n Transfer Pause Control (Write Only) 4 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PRICLR PDMA_PRICLR PDMA Fixed Priority Clear Register 0x414 -1 write-only n 0x0 0x0 FPRICLR0 PDMA Fixed Priority Clear Bits (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority. 0 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR1 PDMA Fixed Priority Clear Bits (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority. 1 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR2 PDMA Fixed Priority Clear Bits (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority. 2 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR3 PDMA Fixed Priority Clear Bits (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority. 3 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR4 PDMA Fixed Priority Clear Bits (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority. 4 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 PRISET PDMA_PRISET PDMA Fixed Priority Setting Register 0x410 -1 read-write n 0x0 0x0 FPRISET0 PDMA Fixed Priority Setting Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register. 0 1 read-write 0 No effect. Corresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel. Corresponding PDMA channel is fixed priority #1 FPRISET1 PDMA Fixed Priority Setting Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register. 1 1 read-write 0 No effect. Corresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel. Corresponding PDMA channel is fixed priority #1 FPRISET2 PDMA Fixed Priority Setting Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register. 2 1 read-write 0 No effect. Corresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel. Corresponding PDMA channel is fixed priority #1 FPRISET3 PDMA Fixed Priority Setting Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register. 3 1 read-write 0 No effect. Corresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel. Corresponding PDMA channel is fixed priority #1 FPRISET4 PDMA Fixed Priority Setting Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register. 4 1 read-write 0 No effect. Corresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel. Corresponding PDMA channel is fixed priority #1 REQSEL0_3 PDMA_REQSEL0_3 PDMA Request Source Select Register 0 0x480 -1 read-write n 0x0 0x0 REQSRC0 Channel 0 Request Source Selection This filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0. Note 1: A peripheral cannot be assigned to two channels at the same time. Note 2: This field is useless when transfer between memory and memory. 0 6 read-write 0 Disable PDMA peripheral request 0 1 Channel connects to DAC0_TX 1 10 Channel connects to USCI0_TX 10 11 Channel connects to USCI0_RX 11 12 Channel connects to USCI1_TX 12 13 Channel connects to USCI1_RX 13 14 Reserved. 14 15 Reserved. 15 16 Reserved. 16 17 Reserved. 17 18 Reserved. 18 19 Reserved. 19 20 Channel connects to ADC_RX 20 21 Channel connects to PWM0_P1_RX 21 22 Channel connects to PWM0_P2_RX 22 23 Channel connects to PWM0_P3_RX 23 24 Reserved. 24 25 Reserved. 25 26 Reserved. 26 27 Reserved. 27 28 Reserved. 28 29 Reserved. 29 30 Reserved. 30 31 Reserved. 31 32 Channel connects to TMR0 32 33 Channel connects to TMR1 33 34 Channel connects to TMR2 34 35 Channel connects to TMR3 35 4 Channel connects to UART0_TX 4 5 Channel connects to UART0_RX 5 6 Channel connects to UART1_TX 6 7 Channel connects to UART1_RX 7 8 Reserved. 8 9 Reserved. 9 REQSRC1 Channel 1 Request Source Selection This filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 8 6 read-write REQSRC2 Channel 2 Request Source Selection This filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 16 6 read-write REQSRC3 Channel 3 Request Source Selection This filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 24 6 read-write REQSEL4 PDMA_REQSEL4 PDMA Request Source Select Register 1 0x484 -1 read-write n 0x0 0x0 REQSRC4 Channel 4 Request Source Selection This filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 0 6 read-write SCATBA PDMA_SCATBA PDMA Scatter-gather Descriptor Table Base Address Register 0x43C -1 read-write n 0x0 0x0 SCATBA PDMA Scatter-gather Descriptor Table Address In Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is Note: Only useful in Scatter-Gather mode. 16 16 read-write SWREQ PDMA_SWREQ PDMA Software Request Register 0x408 -1 write-only n 0x0 0x0 SWREQ0 PDMA Software Request (Write Only) Set this bit to 1 to generate a software request to PDMA [n]. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored. 0 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ1 PDMA Software Request (Write Only) Set this bit to 1 to generate a software request to PDMA [n]. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored. 1 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ2 PDMA Software Request (Write Only) Set this bit to 1 to generate a software request to PDMA [n]. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored. 2 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ3 PDMA Software Request (Write Only) Set this bit to 1 to generate a software request to PDMA [n]. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored. 3 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ4 PDMA Software Request (Write Only) Set this bit to 1 to generate a software request to PDMA [n]. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored. 4 1 write-only 0 No effect #0 1 Generate a software request #1 TACTSTS PDMA_TACTSTS PDMA Transfer Active Flag Register 0x42C -1 read-only n 0x0 0x0 TXACTF0 Transfer on Active Flag (Read Only) This bit indicates which PDMA channel is in active. 0 1 read-only 0 PDMA channel is finished #0 1 PDMA channel is active #1 TXACTF1 Transfer on Active Flag (Read Only) This bit indicates which PDMA channel is in active. 1 1 read-only 0 PDMA channel is finished #0 1 PDMA channel is active #1 TXACTF2 Transfer on Active Flag (Read Only) This bit indicates which PDMA channel is in active. 2 1 read-only 0 PDMA channel is finished #0 1 PDMA channel is active #1 TXACTF3 Transfer on Active Flag (Read Only) This bit indicates which PDMA channel is in active. 3 1 read-only 0 PDMA channel is finished #0 1 PDMA channel is active #1 TXACTF4 Transfer on Active Flag (Read Only) This bit indicates which PDMA channel is in active. 4 1 read-only 0 PDMA channel is finished #0 1 PDMA channel is active #1 TDSTS PDMA_TDSTS PDMA Channel Transfer Done Flag Register 0x424 -1 read-write n 0x0 0x0 TDIF0 Transfer Done Flag This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 0 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF1 Transfer Done Flag This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 1 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF2 Transfer Done Flag This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 2 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF3 Transfer Done Flag This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 3 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF4 Transfer Done Flag This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 4 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TOC0_1 PDMA_TOC0_1 PDMA Time-out Counter Ch1 and Ch0 Register 0x440 -1 read-write n 0x0 0x0 TOC0 Time-out Counter for Channel 0 0 16 read-write TOC1 Time-out Counter for Channel 1 This controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[6:4]) clock. For the example of time-out period, refer to TOC0 bit description. 16 16 read-write TOUTEN PDMA_TOUTEN PDMA Time-out Enable Register 0x434 -1 read-write n 0x0 0x0 TOUTEN0 PDMA Time-out Enable Bits 0 1 read-write 0 PDMA Channel n time-out function Disabled #0 1 PDMA Channel n time-out function Enabled #1 TOUTEN1 PDMA Time-out Enable Bits 1 1 read-write 0 PDMA Channel n time-out function Disabled #0 1 PDMA Channel n time-out function Enabled #1 TOUTIEN PDMA_TOUTIEN PDMA Time-out Interrupt Enable Register 0x438 -1 read-write n 0x0 0x0 TOUTIEN0 PDMA Time-out Interrupt Enable Bits 0 1 read-write 0 PDMA Channel n time-out interrupt Disabled #0 1 PDMA Channel n time-out interrupt Enabled #1 TOUTIEN1 PDMA Time-out Interrupt Enable Bits 1 1 read-write 0 PDMA Channel n time-out interrupt Disabled #0 1 PDMA Channel n time-out interrupt Enabled #1 TOUTPSC PDMA_TOUTPSC PDMA Time-out Prescaler Register 0x430 -1 read-write n 0x0 0x0 TOUTPSC0 PDMA Channel 0 Time-out Clock Source Prescaler Bits 0 3 read-write 0 PDMA channel 0 time-out clock source is HCLK/28 #000 1 PDMA channel 0 time-out clock source is HCLK/29 #001 2 PDMA channel 0 time-out clock source is HCLK/210 #010 3 PDMA channel 0 time-out clock source is HCLK/211 #011 4 PDMA channel 0 time-out clock source is HCLK/212 #100 5 PDMA channel 0 time-out clock source is HCLK/213 #101 6 PDMA channel 0 time-out clock source is HCLK/214 #110 7 PDMA channel 0 time-out clock source is HCLK/215 #111 TOUTPSC1 PDMA Channel 1 Time-out Clock Source Prescaler Bits 4 3 read-write 0 PDMA channel 1 time-out clock source is HCLK/28 #000 1 PDMA channel 1 time-out clock source is HCLK/29 #001 2 PDMA channel 1 time-out clock source is HCLK/210 #010 3 PDMA channel 1 time-out clock source is HCLK/211 #011 4 PDMA channel 1 time-out clock source is HCLK/212 #100 5 PDMA channel 1 time-out clock source is HCLK/213 #101 6 PDMA channel 1 time-out clock source is HCLK/214 #110 7 PDMA channel 1 time-out clock source is HCLK/215 #111 TRGSTS PDMA_TRGSTS PDMA Channel Request Status Register 0x40C -1 read-only n 0x0 0x0 REQSTS0 PDMA Channel Request Status (Read Only) This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 0 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS1 PDMA Channel Request Status (Read Only) This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 1 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS2 PDMA Channel Request Status (Read Only) This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 2 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS3 PDMA Channel Request Status (Read Only) This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 3 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS4 PDMA Channel Request Status (Read Only) This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 4 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 PWM PWM Register Map PWM 0x0 0x0 0x8 registers n 0x10 0x18 registers n 0x110 0x8 registers n 0x120 0x4 registers n 0x200 0x4C registers n 0x250 0x8 registers n 0x30 0x4 registers n 0x304 0x4 registers n 0x30C 0x4 registers n 0x314 0x4 registers n 0x31C 0x18 registers n 0x38 0x4 registers n 0x40 0x4 registers n 0x50 0x18 registers n 0x70 0xC registers n 0x90 0x4 registers n 0x98 0x4 registers n 0xA0 0x4 registers n 0xB0 0x40 registers n 0xF8 0x8 registers n ADCTS0 PWM_ADCTS0 PWM Trigger ADC Source Select Register 0 0xF8 -1 read-write n 0x0 0x0 TRGEN0 PWM_CH0 Trigger ADC Enable Bit 7 1 read-write 0 PWM_CH0 Trigger ADC function Disabled #0 1 PWM_CH0 Trigger ADC function Enabled #1 TRGEN1 PWM_CH1 Trigger ADC Enable Bit 15 1 read-write 0 PWM_CH1 Trigger ADC function Disabled #0 1 PWM_CH1 Trigger ADC function Enabled #1 TRGEN2 PWM_CH2 Trigger ADC Enable Bit 23 1 read-write 0 PWM_CH2 Trigger ADC function Disabled #0 1 PWM_CH2 Trigger ADC function Enabled #1 TRGEN3 PWM_CH3 Trigger ADC Enable Bit 31 1 read-write 0 PWM_CH3 Trigger ADC function Disabled #0 1 PWM_CH3 Trigger ADC function Enabled #1 TRGSEL0 PWM_CH0 Trigger ADC Source Select 0 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count CMPDAT point #0011 4 PWM_CH0 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 PWM_CH1 up-count CMPDAT point #1000 9 PWM_CH1 down-count CMPDAT point #1001 TRGSEL1 PWM_CH1 Trigger ADC Source Select 8 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count CMPDAT point #0011 4 PWM_CH0 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 PWM_CH1 up-count CMPDAT point #1000 9 PWM_CH1 down-count CMPDAT point #1001 TRGSEL2 PWM_CH2 Trigger ADC Source Select 16 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count CMPDAT point #0011 4 PWM_CH2 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 PWM_CH3 up-count CMPDAT point #1000 9 PWM_CH3 down-count CMPDAT point #1001 TRGSEL3 PWM_CH3 Trigger ADC Source Select 24 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count CMPDAT point #0011 4 PWM_CH2 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 PWM_CH3 up-count CMPDAT point #1000 9 PWM_CH3 down-count CMPDAT point #1001 ADCTS1 PWM_ADCTS1 PWM Trigger ADC Source Select Register 1 0xFC -1 read-write n 0x0 0x0 TRGEN4 PWM_CH4 Trigger ADC Enable Bit 7 1 read-write 0 PWM_CH4 Trigger ADC function Disabled #0 1 PWM_CH4 Trigger ADC function Enabled #1 TRGEN5 PWM_CH5 Trigger ADC Enable Bit 15 1 read-write 0 PWM_CH5 Trigger ADC function Disabled #0 1 PWM_CH5 Trigger ADC function Enabled #1 TRGSEL4 PWM_CH4 Trigger ADC Source Select 0 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count CMPDAT point #0011 4 PWM_CH4 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 PWM_CH5 up-count CMPDAT point #1000 9 PWM_CH5 down-count CMPDAT point #1001 TRGSEL5 PWM_CH5 Trigger ADC Source Select 8 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count CMPDAT point #0011 4 PWM_CH4 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 PWM_CH5 up-count CMPDAT point #1000 9 PWM_CH5 down-count CMPDAT point #1001 BNF PWM_BNF PWM Brake Noise Filter Register 0xC0 -1 read-write n 0x0 0x0 BK0SRC Brake 0 Pin Source Select For PWM0 setting: 16 1 read-write 0 Brake 0 pin source come from PWM0_BRAKE0 #0 1 Reserved. #1 BK1SRC Brake 1 Pin Source Select For PWM0 setting: 24 1 read-write 0 Brake 1 pin source come from PWM0_BRAKE1 #0 1 Reserved. #1 BRK0FCNT Brake 0 Edge Detector Filter Count The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. 4 3 read-write BRK0NFEN PWM Brake 0 Noise Filter Enable Bit 0 1 read-write 0 Noise filter of PWM Brake 0 Disabled #0 1 Noise filter of PWM Brake 0 Enabled #1 BRK0NFSEL Brake 0 Edge Detector Filter Clock Selection 1 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK0PINV Brake 0 Pin Inverse 7 1 read-write 0 The state of pin PWMx_BRAKE0 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector #1 BRK1FCNT Brake 1 Edge Detector Filter Count The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 12 3 read-write BRK1NFEN PWM Brake 1 Noise Filter Enable Bit 8 1 read-write 0 Noise filter of PWM Brake 1 Disabled #0 1 Noise filter of PWM Brake 1 Enabled #1 BRK1NFSEL Brake 1 Edge Detector Filter Clock Selection 9 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK1PINV Brake 1 Pin Inverse 15 1 read-write 0 The state of pin PWMx_BRAKE1 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector #1 BRKCTL0_1 PWM_BRKCTL0_1 PWM Brake Edge Detect Control Register 0/1 0xC8 -1 read-write n 0x0 0x0 BRKAEVEN PWM Brake Action Select for Even Channel (Write Protect) Note: These bits are write protected. Refer to SYS_REGLCTL register. 16 2 read-write 0 PWM even channel level-detect brake function not affect channel output #00 1 PWM even channel output tri-state when level-detect brake happened #01 2 PWM even channel output low level when level-detect brake happened #10 3 PWM even channel output high level when level-detect brake happened #11 BRKAODD PWM Brake Action Select for Odd Channel (Write Protect) Note: These bits are write protected. Refer to SYS_REGLCTL register. 18 2 read-write 0 PWM odd channel level-detect brake function not affect channel output #00 1 PWM odd channel output tri-state when level-detect brake happened #01 2 PWM odd channel output low level when level-detect brake happened #10 3 PWM odd channel output high level when level-detect brake happened #11 BRKP0EEN Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 BKP0 pin as edge-detect brake source Disabled #0 1 BKP0 pin as edge-detect brake source Enabled #1 BRKP0LEN Enable BKP0 Pin As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 PWMx_BRAKE0 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE0 pin as level-detect brake source Enabled #1 BRKP1EEN Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 BKP1 pin as edge-detect brake source Disabled #0 1 BKP1 pin as edge-detect brake source Enabled #1 BRKP1LEN Enable BKP1 Pin As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 PWMx_BRAKE1 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE1 pin as level-detect brake source Enabled #1 CPO0EBEN Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) Note: This register is write protected. Refer toSYS_REGLCTL register. 0 1 read-write 0 ACMP0_O as edge-detect brake source Disabled #0 1 ACMP0_O as edge-detect brake source Enabled #1 CPO0LBEN Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) Note: This register is write protected. Refer toSYS_REGLCTL register. 8 1 read-write 0 ACMP0_O as level-detect brake source Disabled #0 1 ACMP0_O as level-detect brake source Enabled #1 CPO1EBEN Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) Note: This register is write protected. Refer toSYS_REGLCTL register. 1 1 read-write 0 ACMP1_O as edge-detect brake source Disabled #0 1 ACMP1_O as edge-detect brake source Enabled #1 CPO1LBEN Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) Note: This register is write protected. Refer toSYS_REGLCTL register. 9 1 read-write 0 ACMP1_O as level-detect brake source Disabled #0 1 ACMP1_O as level-detect brake source Enabled #1 SYSEBEN Enable System Fail As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 7 1 read-write 0 System Fail condition as edge-detect brake source Disabled #0 1 System Fail condition as edge-detect brake source Enabled #1 SYSLBEN Enable System Fail As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 15 1 read-write 0 System Fail condition as level-detect brake source Disabled #0 1 System Fail condition as level-detect brake source Enabled #1 BRKCTL2_3 PWM_BRKCTL2_3 PWM Brake Edge Detect Control Register 2/3 0xCC -1 read-write n 0x0 0x0 BRKCTL4_5 PWM_BRKCTL4_5 PWM Brake Edge Detect Control Register 4/5 0xD0 -1 read-write n 0x0 0x0 CAPCTL PWM_CAPCTL PWM Capture Control Register 0x204 -1 read-write n 0x0 0x0 CAPEN0 Capture Function Enable Bits 0 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN1 Capture Function Enable Bits 1 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN2 Capture Function Enable Bits 2 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN3 Capture Function Enable Bits 3 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN4 Capture Function Enable Bits 4 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN5 Capture Function Enable Bits 5 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPINV0 Capture Inverter Enable Bits 8 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV1 Capture Inverter Enable Bits 9 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV2 Capture Inverter Enable Bits 10 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV3 Capture Inverter Enable Bits 11 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV4 Capture Inverter Enable Bits 12 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV5 Capture Inverter Enable Bits 13 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 FCRLDEN0 Falling Capture Reload Enable Bits 24 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN1 Falling Capture Reload Enable Bits 25 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN2 Falling Capture Reload Enable Bits 26 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN3 Falling Capture Reload Enable Bits 27 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN4 Falling Capture Reload Enable Bits 28 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN5 Falling Capture Reload Enable Bits 29 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 RCRLDEN0 Rising Capture Reload Enable Bits 16 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN1 Rising Capture Reload Enable Bits 17 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN2 Rising Capture Reload Enable Bits 18 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN3 Rising Capture Reload Enable Bits 19 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN4 Rising Capture Reload Enable Bits 20 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN5 Rising Capture Reload Enable Bits 21 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 CAPIEN PWM_CAPIEN PWM Capture Interrupt Enable Register 0x250 -1 read-write n 0x0 0x0 CAPFIEN0 PWM Capture Falling Latch Interrupt Enable Bits 8 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN1 PWM Capture Falling Latch Interrupt Enable Bits 9 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN2 PWM Capture Falling Latch Interrupt Enable Bits 10 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN3 PWM Capture Falling Latch Interrupt Enable Bits 11 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN4 PWM Capture Falling Latch Interrupt Enable Bits 12 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN5 PWM Capture Falling Latch Interrupt Enable Bits 13 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPRIEN0 PWM Capture Rising Latch Interrupt Enable Bits 0 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN1 PWM Capture Rising Latch Interrupt Enable Bits 1 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN2 PWM Capture Rising Latch Interrupt Enable Bits 2 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN3 PWM Capture Rising Latch Interrupt Enable Bits 3 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN4 PWM Capture Rising Latch Interrupt Enable Bits 4 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN5 PWM Capture Rising Latch Interrupt Enable Bits 5 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPIF PWM_CAPIF PWM Capture Interrupt Flag Register 0x254 -1 read-write n 0x0 0x0 CFLIF0 PWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 8 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF1 PWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 9 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF2 PWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 10 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF3 PWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 11 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF4 PWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 12 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF5 PWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 13 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CRLIF0 PWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 0 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF1 PWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 1 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF2 PWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 2 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF3 PWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 3 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF4 PWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 4 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF5 PWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 5 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPINEN PWM_CAPINEN PWM Capture Input Enable Register 0x200 -1 read-write n 0x0 0x0 CAPINEN0 Capture Input Enable Bits 0 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPINEN1 Capture Input Enable Bits 1 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPINEN2 Capture Input Enable Bits 2 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPINEN3 Capture Input Enable Bits 3 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPINEN4 Capture Input Enable Bits 4 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPINEN5 Capture Input Enable Bits 5 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPSTS PWM_CAPSTS PWM Capture Status Register 0x208 -1 read-only n 0x0 0x0 CFLIFOV0 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIF is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIF. 8 1 read-only CFLIFOV1 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIF is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIF. 9 1 read-only CFLIFOV2 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIF is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIF. 10 1 read-only CFLIFOV3 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIF is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIF. 11 1 read-only CFLIFOV4 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIF is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIF. 12 1 read-only CFLIFOV5 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIF is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIF. 13 1 read-only CRLIFOV0 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIF is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIF. 0 1 read-only CRLIFOV1 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIF is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1 1 read-only CRLIFOV2 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIF is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIF. 2 1 read-only CRLIFOV3 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIF is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIF. 3 1 read-only CRLIFOV4 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIF is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIF. 4 1 read-only CRLIFOV5 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIF is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIF. 5 1 read-only CLKPSC0_1 PWM_CLKPSC0_1 PWM Clock Prescale Register 0/1 0x14 -1 read-write n 0x0 0x0 CLKPSC PWM Counter Clock Prescale The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1). 0 12 read-write CLKPSC2_3 PWM_CLKPSC2_3 PWM Clock Prescale Register 2/3 0x18 -1 read-write n 0x0 0x0 CLKPSC4_5 PWM_CLKPSC4_5 PWM Clock Prescale Register 4/5 0x1C -1 read-write n 0x0 0x0 CLKSRC PWM_CLKSRC PWM Clock Source Register 0x10 -1 read-write n 0x0 0x0 ECLKSRC0 PWM_CH01 External Clock Source Select 0 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC2 PWM_CH23 External Clock Source Select 8 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC4 PWM_CH45 External Clock Source Select 16 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 CMPBUF0 PWM_CMPBUF0 PWM CMPDAT0 Buffer 0x31C -1 read-only n 0x0 0x0 CMPBUF PWM Comparator Register Buffer (Read Only) Used as CMP active register. 0 16 read-only CMPBUF1 PWM_CMPBUF1 PWM CMPDAT1 Buffer 0x320 -1 read-write n 0x0 0x0 CMPBUF2 PWM_CMPBUF2 PWM CMPDAT2 Buffer 0x324 -1 read-write n 0x0 0x0 CMPBUF3 PWM_CMPBUF3 PWM CMPDAT3 Buffer 0x328 -1 read-write n 0x0 0x0 CMPBUF4 PWM_CMPBUF4 PWM CMPDAT4 Buffer 0x32C -1 read-write n 0x0 0x0 CMPBUF5 PWM_CMPBUF5 PWM CMPDAT5 Buffer 0x330 -1 read-write n 0x0 0x0 CMPDAT0 PWM_CMPDAT0 PWM Comparator Register 0 0x50 -1 read-write n 0x0 0x0 CMP PWM Comparator Register CMP is used to compare with CNTR to generate PWM waveform, interrupt and trigger ADC. In independent mode, PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point. In complementary mode, PWM_CMPDAT0, 2, 4 denote as first compared point, and PWM_CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5. 0 16 read-write CMPDAT1 PWM_CMPDAT1 PWM Comparator Register 1 0x54 -1 read-write n 0x0 0x0 CMPDAT2 PWM_CMPDAT2 PWM Comparator Register 2 0x58 -1 read-write n 0x0 0x0 CMPDAT3 PWM_CMPDAT3 PWM Comparator Register 3 0x5C -1 read-write n 0x0 0x0 CMPDAT4 PWM_CMPDAT4 PWM Comparator Register 4 0x60 -1 read-write n 0x0 0x0 CMPDAT5 PWM_CMPDAT5 PWM Comparator Register 5 0x64 -1 read-write n 0x0 0x0 CNT0 PWM_CNT0 PWM Counter Register 0 0x90 -1 read-only n 0x0 0x0 CNT PWM Data Register (Read Only) User can monitor CNTR to know the current value in 16-bit period counter. 0 16 read-only DIRF PWM Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is counting down #0 1 Counter is counting up #1 CNT2 PWM_CNT2 PWM Counter Register 2 0x98 -1 read-write n 0x0 0x0 CNT4 PWM_CNT4 PWM Counter Register 4 0xA0 -1 read-write n 0x0 0x0 CNTCLR PWM_CNTCLR PWM Clear Counter Register 0x24 -1 read-write n 0x0 0x0 CNTCLR0 Clear PWM Counter Control Bit 0 It is automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0000H #1 CNTCLR2 Clear PWM Counter Control Bit 2 It is automatically cleared by hardware. 2 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0000H #1 CNTCLR4 Clear PWM Counter Control Bit 4 It is automatically cleared by hardware. 4 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0000H #1 CNTEN PWM_CNTEN PWM Counter Enable Register 0x20 -1 read-write n 0x0 0x0 CNTEN0 PWM Counter Enable Bit 0 0 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN2 PWM Counter Enable Bit 2 2 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN4 PWM Counter Enable Bit 4 4 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CTL0 PWM_CTL0 PWM Control Register 0 0x0 -1 read-write n 0x0 0x0 CTRLDn Center Load Enable Bits In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 1 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect) If counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. Note: This bit is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disable #0 1 ICE debug mode counter halt Enable #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable Bit (Write Protect) PWM pin will keep output no matter ICE debug mode acknowledged or not. Note: This bit is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects PWM output #0 1 ICE debug mode acknowledgement disabled #1 IMMLDENn Immediately Load Enable Bits Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 16 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 CTL1 PWM_CTL1 PWM Control Register 1 0x4 -1 read-write n 0x0 0x0 CNTTYPE0 PWM Counter Behavior Type 0 The two bits control channel1 and channel0 0 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE2 PWM Counter Behavior Type 2 The two bits control channel3 and channel2 4 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE4 PWM Counter Behavior Type 4 The two bits control channel5 and channel4 8 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 OUTMODEn PWM Output Mode Each bit n controls the output mode of corresponding PWM channel n. Note: When operating in group function, these bits must all set to the same mode. 24 3 read-write 0 PWM independent mode 0 1 PWM complementary mode 1 DTCTL0_1 PWM_DTCTL0_1 PWM Dead-time Control Register 0/1 0x70 -1 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect) Note: This bit is write protected. Refer to REGWRPROT register. 24 1 read-write 0 Dead-time clock source from PWM_CLK #0 1 Dead-time clock source from prescaler output #1 DTCNT Dead-time Counter (Write Protect) The dead-time can be calculated from the following formula: Note: This bit is write protected. Refer to SYS_REGLCTL register. 0 12 read-write DTEN Enable Dead-time Insertion for PWM Pair (Write Protect) PWM_CH0 andPWM_CH1 PWM_CH2 andPWM_CH3 PWM_CH4 andPWM_CH5 Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. Note: This bit is write protected. Refer to SYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 DTCTL2_3 PWM_DTCTL2_3 PWM Dead-time Control Register 2/3 0x74 -1 read-write n 0x0 0x0 DTCTL4_5 PWM_DTCTL4_5 PWM Dead-time Control Register 4/5 0x78 -1 read-write n 0x0 0x0 FAILBRK PWM_FAILBRK PWM System Fail Brake Control Register 0xC4 -1 read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger PWM Brake Function 0 Enable Bit 1 1 read-write 0 Brake Function triggered by BOD Disabled #0 1 Brake Function triggered by BOD Enabled #1 CORBRKEN Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit 3 1 read-write 0 Brake Function triggered by Core lockup detection Disabled #0 1 Brake Function triggered by Core lockup detection Enabled #1 CSSBRKEN Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit 0 1 read-write 0 Brake Function triggered by CSS detection Disabled #0 1 Brake Function triggered by CSS detection Enabled #1 FCAPDAT0 PWM_FCAPDAT0 PWM Falling Capture Data Register 0 0x210 -1 read-only n 0x0 0x0 FCAPDAT PWM Falling Capture Data Register (Read Only) When falling capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only FCAPDAT1 PWM_FCAPDAT1 PWM Falling Capture Data Register 1 0x218 -1 read-write n 0x0 0x0 FCAPDAT2 PWM_FCAPDAT2 PWM Falling Capture Data Register 2 0x220 -1 read-write n 0x0 0x0 FCAPDAT3 PWM_FCAPDAT3 PWM Falling Capture Data Register 3 0x228 -1 read-write n 0x0 0x0 FCAPDAT4 PWM_FCAPDAT4 PWM Falling Capture Data Register 4 0x230 -1 read-write n 0x0 0x0 FCAPDAT5 PWM_FCAPDAT5 PWM Falling Capture Data Register 5 0x238 -1 read-write n 0x0 0x0 INTEN0 PWM_INTEN0 PWM Interrupt Enable Register 0 0xE0 -1 read-write n 0x0 0x0 CMPDIEN0 PWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 24 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN1 PWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 25 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN2 PWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 26 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN3 PWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 27 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN4 PWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 28 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN5 PWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 29 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPUIEN0 PWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding PWM channel n. Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 16 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN1 PWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding PWM channel n. Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 17 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN2 PWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding PWM channel n. Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 18 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN3 PWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding PWM channel n. Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 19 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN4 PWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding PWM channel n. Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 20 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN5 PWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding PWM channel n. Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 21 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 PIEN0 PWM Period Point Interrupt Enable Bit 0 Note: When up-down counter type, period point means center point. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN2 PWM Period Point Interrupt Enable Bit 2 Note: When up-down counter type, period point means center point. 10 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN4 PWM Period Point Interrupt Enable Bit 4 Note: When up-down counter type, period point means center point. 12 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 PWM Zero Point Interrupt Enable Bit 0 Note: Odd channels will always read 0 at complementary mode. 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN2 PWM Zero Point Interrupt Enable Bit 2 Note: Odd channels will always read 0 at complementary mode. 2 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN4 PWM Zero Point Interrupt Enable Bit 4 Note: Odd channels will read always 0 at complementary mode. 4 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 INTEN1 PWM_INTEN1 PWM Interrupt Enable Register 1 0xE4 -1 read-write n 0x0 0x0 BRKEIEN0_1 PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 Edge-detect Brake interrupt for channel0/1 Disabled #0 1 Edge-detect Brake interrupt for channel0/1 Enabled #1 BRKEIEN2_3 PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 Edge-detect Brake interrupt for channel2/3 Disabled #0 1 Edge-detect Brake interrupt for channel2/3 Enabled #1 BRKEIEN4_5 PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) Note: This bitr is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 Edge-detect Brake interrupt for channel4/5 Disabled #0 1 Edge-detect Brake interrupt for channel4/5 Enabled #1 BRKLIEN0_1 PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 Level-detect Brake interrupt for channel0/1 Disabled #0 1 Level-detect Brake interrupt for channel0/1 Enabled #1 BRKLIEN2_3 PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 Level-detect Brake interrupt for channel2/3 Disabled #0 1 Level-detect Brake interrupt for channel2/3 Enabled #1 BRKLIEN4_5 PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 Level-detect Brake interrupt for channel4/5 Disabled #0 1 Level-detect Brake interrupt for channel4/5 Enabled #1 INTSTS0 PWM_INTSTS0 PWM Interrupt Flag Register 0 0xE8 -1 read-write n 0x0 0x0 CMPDIF0 PWM Compare Down Count Interrupt Flag Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 24 1 read-write CMPDIF1 PWM Compare Down Count Interrupt Flag Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 25 1 read-write CMPDIF2 PWM Compare Down Count Interrupt Flag Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 26 1 read-write CMPDIF3 PWM Compare Down Count Interrupt Flag Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 27 1 read-write CMPDIF4 PWM Compare Down Count Interrupt Flag Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 28 1 read-write CMPDIF5 PWM Compare Down Count Interrupt Flag Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 29 1 read-write CMPUIFn PWM Compare Up Count Interrupt Flag Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 16 6 read-write PIF0 PWM Period Point Interrupt Flag 0 This bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0. Note: This bit can be cleared to 0 by software writing 1. 8 1 read-write PIF2 PWM Period Point Interrupt Flag 2 This bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2. Note: This bit can be cleared to 0 by software writing 1. 10 1 read-write PIF4 PWM Period Point Interrupt Flag 4 This bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4. Note: This bit can be cleared to 0 by software writing 1. 12 1 read-write ZIF0 PWM Zero Point Interrupt Flag 0 This bit is set by hardware when PWM_CH0 counter reaches 0. Note: This bit can be cleared to 0 by software writing 1. 0 1 read-write ZIF2 PWM Zero Point Interrupt Flag 2 This bit is set by hardware when PWM_CH2 counter reaches 0. Note: This bit can be cleared to 0 by software writing 1. 2 1 read-write ZIF4 PWM Zero Point Interrupt Flag 4 This bit is set by hardware when PWM_CH4 counter reaches 0. Note: This bit can be cleared to 0 by software writing 1. 4 1 read-write INTSTS1 PWM_INTSTS1 PWM Interrupt Flag Register 1 0xEC -1 read-write n 0x0 0x0 BRKEIF0 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF1 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF2 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF3 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 3 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF4 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF5 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKESTS0 PWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 16 1 read-only 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKESTS1 PWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 17 1 read-only 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKESTS2 PWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 18 1 read-only 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKESTS3 PWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 19 1 read-only 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKESTS4 PWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 20 1 read-only 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKESTS5 PWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 21 1 read-only 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLIF0 PWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 PWM channel n level-detect brake event do not happened #0 1 When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF1 PWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 PWM channel n level-detect brake event do not happened #0 1 When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF2 PWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 PWM channel n level-detect brake event do not happened #0 1 When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF3 PWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 11 1 read-write 0 PWM channel n level-detect brake event do not happened #0 1 When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF4 PWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 PWM channel n level-detect brake event do not happened #0 1 When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF5 PWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 PWM channel n level-detect brake event do not happened #0 1 When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLSTS0 PWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source returns to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 24 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLSTS1 PWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source returns to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 25 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLSTS2 PWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source returns to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 26 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLSTS3 PWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source returns to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 27 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLSTS4 PWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source returns to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 28 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLSTS5 PWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source returns to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 29 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 MSK PWM_MSK PWM Mask Data Register 0xBC -1 read-write n 0x0 0x0 MSKDAT0 PWM Mask Data Bit This data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 0 1 read-write 0 Output logic low to PWM channel n #0 1 Output logic high to PWM channel n #1 MSKDAT1 PWM Mask Data Bit This data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 1 1 read-write 0 Output logic low to PWM channel n #0 1 Output logic high to PWM channel n #1 MSKDAT2 PWM Mask Data Bit This data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 2 1 read-write 0 Output logic low to PWM channel n #0 1 Output logic high to PWM channel n #1 MSKDAT3 PWM Mask Data Bit This data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 3 1 read-write 0 Output logic low to PWM channel n #0 1 Output logic high to PWM channel n #1 MSKDAT4 PWM Mask Data Bit This data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 4 1 read-write 0 Output logic low to PWM channel n #0 1 Output logic high to PWM channel n #1 MSKDAT5 PWM Mask Data Bit This data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 5 1 read-write 0 Output logic low to PWM channel n #0 1 Output logic high to PWM channel n #1 MSKEN PWM_MSKEN PWM Mask Enable Register 0xB8 -1 read-write n 0x0 0x0 MSKEN0 PWM Mask Enable Bits The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. 0 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 MSKEN1 PWM Mask Enable Bits The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. 1 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 MSKEN2 PWM Mask Enable Bits The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. 2 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 MSKEN3 PWM Mask Enable Bits The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. 3 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 MSKEN4 PWM Mask Enable Bits The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. 4 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 MSKEN5 PWM Mask Enable Bits The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. 5 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 PBUF0 PWM_PBUF0 PWM PERIOD0 Buffer 0x304 -1 read-only n 0x0 0x0 PBUF PWM Period Register Buffer (Read Only) Used as PERIOD active register. 0 16 read-only PBUF2 PWM_PBUF2 PWM PERIOD2 Buffer 0x30C -1 read-write n 0x0 0x0 PBUF4 PWM_PBUF4 PWM PERIOD4 Buffer 0x314 -1 read-write n 0x0 0x0 PDMACAP0_1 PWM_PDMACAP0_1 PWM Capture Channel 01 PDMA Register 0x240 -1 read-only n 0x0 0x0 CAPBUF PWM Capture PDMA Register (Read Only) This register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA. Note: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M0A21/M0A23 Series Selection Guide for detailed information. 0 16 read-only PDMACAP2_3 PWM_PDMACAP2_3 PWM Capture Channel 23 PDMA Register 0x244 -1 read-write n 0x0 0x0 PDMACAP4_5 PWM_PDMACAP4_5 PWM Capture Channel 45 PDMA Register 0x248 -1 read-write n 0x0 0x0 PDMACTL PWM_PDMACTL PWM PDMA Control Register 0x23C -1 read-write n 0x0 0x0 CAPMOD0_1 Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer Note: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M0A21/M0A23 Series Selection Guide for detailed information. 1 2 read-write 0 Reserved. #00 1 PWM_RCAPDAT0/1 #01 2 PWM_FCAPDAT0/1 #10 3 Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1 #11 CAPMOD2_3 Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer Note: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M0A21/M0A23 Series Selection Guide for detailed information. 9 2 read-write 0 Reserved. #00 1 PWM_RCAPDAT2/3 #01 2 PWM_FCAPDAT2/3 #10 3 Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3 #11 CAPMOD4_5 Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer Note: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M0A21/M0A23 Series Selection Guide for detailed information. 17 2 read-write 0 Reserved. #00 1 PWM_RCAPDAT4/5 #01 2 PWM_FCAPDAT4/5 #10 3 Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5 #11 CAPORD0_1 Capture Channel 0/1 Rising/Falling Order Note: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M0A21/M0A23 Series Selection Guide for detailed information. 3 1 read-write 0 PWM_FCAPDAT0/1 is the first captured data to memory #0 1 PWM_RCAPDAT0/1 is the first captured data to memory #1 CAPORD2_3 Capture Channel 2/3 Rising/Falling Order Note: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M0A21/M0A23 Series Selection Guide for detailed information. 11 1 read-write 0 PWM_FCAPDAT2/3 is the first captured data to memory #0 1 PWM_RCAPDAT2/3 is the first captured data to memory #1 CAPORD4_5 Capture Channel 4/5 Rising/Falling Order Note: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M0A21/M0A23 Series Selection Guide for detailed information. 19 1 read-write 0 PWM_FCAPDAT4/5 is the first captured data to memory #0 1 PWM_RCAPDAT4/5 is the first captured data to memory #1 CHEN0_1 Channel 0/1 PDMA Enable Bit Note: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M0A21/M0A23 Series Selection Guide for detailed information. 0 1 read-write 0 Channel 0/1 PDMA function Disabled #0 1 Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory #1 CHEN2_3 Channel 2/3 PDMA Enable Bit Note: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M0A21/M0A23 Series Selection Guide for detailed information. 8 1 read-write 0 Channel 2/3 PDMA function Disabled #0 1 Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory #1 CHEN4_5 Channel 4/5 PDMA Enable Bit Note: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M0A21/M0A23 Series Selection Guide for detailed information. 16 1 read-write 0 Channel 4/5 PDMA function Disabled #0 1 Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory #1 CHSEL0_1 Select Channel 0/1 to Do PDMA Transfer Note: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M0A21/M0A23 Series Selection Guide for detailed information. 4 1 read-write 0 Channel0 #0 1 Channel1 #1 CHSEL2_3 Select Channel 2/3 to Do PDMA Transfer Note: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M0A21/M0A23 Series Selection Guide for detailed information. 12 1 read-write 0 Channel2 #0 1 Channel3 #1 CHSEL4_5 Select Channel 4/5 to Do PDMA Transfer Note: If the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2 NuMicro M0A21/M0A23 Series Selection Guide for detailed information. 20 1 read-write 0 Channel4 #0 1 Channel5 #1 PERIOD0 PWM_PERIOD0 PWM Period Register 0 0x30 -1 read-write n 0x0 0x0 PERIOD PWM Period Register Up-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0. Down-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD. 0 16 read-write PERIOD2 PWM_PERIOD2 PWM Period Register 2 0x38 -1 read-write n 0x0 0x0 PERIOD4 PWM_PERIOD4 PWM Period Register 4 0x40 -1 read-write n 0x0 0x0 POEN PWM_POEN PWM Output Enable Register 0xD8 -1 read-write n 0x0 0x0 POEN0 PWM Pin Output Enable Bits 0 1 read-write 0 PWM pin at tri-state #0 1 PWM pin in output mode #1 POEN1 PWM Pin Output Enable Bits 1 1 read-write 0 PWM pin at tri-state #0 1 PWM pin in output mode #1 POEN2 PWM Pin Output Enable Bits 2 1 read-write 0 PWM pin at tri-state #0 1 PWM pin in output mode #1 POEN3 PWM Pin Output Enable Bits 3 1 read-write 0 PWM pin at tri-state #0 1 PWM pin in output mode #1 POEN4 PWM Pin Output Enable Bits 4 1 read-write 0 PWM pin at tri-state #0 1 PWM pin in output mode #1 POEN5 PWM Pin Output Enable Bits 5 1 read-write 0 PWM pin at tri-state #0 1 PWM pin in output mode #1 POLCTL PWM_POLCTL PWM Pin Polar Inverse Register 0xD4 -1 read-write n 0x0 0x0 PINV0 PWM PIN Polar Inverse Control The register controls polarity state of PWM output. 0 1 read-write 0 PWM output polar inverse Disabled #0 1 PWM output polar inverse Enabled #1 PINV1 PWM PIN Polar Inverse Control The register controls polarity state of PWM output. 1 1 read-write 0 PWM output polar inverse Disabled #0 1 PWM output polar inverse Enabled #1 PINV2 PWM PIN Polar Inverse Control The register controls polarity state of PWM output. 2 1 read-write 0 PWM output polar inverse Disabled #0 1 PWM output polar inverse Enabled #1 PINV3 PWM PIN Polar Inverse Control The register controls polarity state of PWM output. 3 1 read-write 0 PWM output polar inverse Disabled #0 1 PWM output polar inverse Enabled #1 PINV4 PWM PIN Polar Inverse Control The register controls polarity state of PWM output. 4 1 read-write 0 PWM output polar inverse Disabled #0 1 PWM output polar inverse Enabled #1 PINV5 PWM PIN Polar Inverse Control The register controls polarity state of PWM output. 5 1 read-write 0 PWM output polar inverse Disabled #0 1 PWM output polar inverse Enabled #1 RCAPDAT0 PWM_RCAPDAT0 PWM Rising Capture Data Register 0 0x20C -1 read-only n 0x0 0x0 RCAPDAT PWM Rising Capture Data Register (Read Only) When rising capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only RCAPDAT1 PWM_RCAPDAT1 PWM Rising Capture Data Register 1 0x214 -1 read-write n 0x0 0x0 RCAPDAT2 PWM_RCAPDAT2 PWM Rising Capture Data Register 2 0x21C -1 read-write n 0x0 0x0 RCAPDAT3 PWM_RCAPDAT3 PWM Rising Capture Data Register 3 0x224 -1 read-write n 0x0 0x0 RCAPDAT4 PWM_RCAPDAT4 PWM Rising Capture Data Register 4 0x22C -1 read-write n 0x0 0x0 RCAPDAT5 PWM_RCAPDAT5 PWM Rising Capture Data Register 5 0x234 -1 read-write n 0x0 0x0 SSCTL PWM_SSCTL PWM Synchronous Start Control Register 0x110 -1 read-write n 0x0 0x0 SSEN0 PWM Synchronous Start Function Enable Bit 0 When synchronous start function is enabled, the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). 0 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN2 PWM Synchronous Start Function Enable Bit 2 When synchronous start function is enabled, the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). 2 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN4 PWM Synchronous Start Function Enable Bit 4 When synchronous start function is enabled, the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). 4 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSRC PWM Synchronous Start Source Select Bits 8 2 read-write 0 Synchronous start source come from PWM0 #00 1 Reserved. #01 2 Reserved. #10 3 Reserved. #11 SSTRG PWM_SSTRG PWM Synchronous Start Trigger Register 0x114 -1 write-only n 0x0 0x0 CNTSEN PWM Counter Synchronous Start Enable (Write Only) PWM counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx) start counting at the same time. Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled. 0 1 write-only STATUS PWM_STATUS PWM Status Register 0x120 -1 read-write n 0x0 0x0 ADCTRG0 ADC Start of Conversion Status Note: This bit can be cleared by software writing 1. 16 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 An ADC start of conversion trigger event has occurred #1 ADCTRG1 ADC Start of Conversion Status Note: This bit can be cleared by software writing 1. 17 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 An ADC start of conversion trigger event has occurred #1 ADCTRG2 ADC Start of Conversion Status Note: This bit can be cleared by software writing 1. 18 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 An ADC start of conversion trigger event has occurred #1 ADCTRG3 ADC Start of Conversion Status Note: This bit can be cleared by software writing 1. 19 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 An ADC start of conversion trigger event has occurred #1 ADCTRG4 ADC Start of Conversion Status Note: This bit can be cleared by software writing 1. 20 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 An ADC start of conversion trigger event has occurred #1 ADCTRG5 ADC Start of Conversion Status Note: This bit can be cleared by software writing 1. 21 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 An ADC start of conversion trigger event has occurred #1 CNTMAX0 Time-base Counter 0 Equal to 0xFFFF Latched Flag Note: This bit can be cleared by software writing 1. 0 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value #1 CNTMAX2 Time-base Counter 2 Equal to 0xFFFF Latched Flag Note: This bit can be cleared by software writing 1. 2 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value #1 CNTMAX4 Time-base Counter 4 Equal to 0xFFFF Latched Flag Note: This bit can be cleared by software writing 1. 4 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 SWBRK PWM_SWBRK PWM Software Brake Control Register 0xDC -1 write-only n 0x0 0x0 BRKETRG0 PWM Edge Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 write-only BRKETRG2 PWM Edge Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 write-only BRKETRG4 PWM Edge Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 write-only BRKLTRG0 PWM Level Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 write-only BRKLTRG2 PWM Level Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 write-only BRKLTRG4 PWM Level Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 write-only WGCTL0 PWM_WGCTL0 PWM Generation Register 0 0xB0 -1 read-write n 0x0 0x0 PRDPCTL0 PWM Period or CenterPoint Control Note 1: PWM can control output level when PWM counter counts to (PERIODn+1). Note 2: This bit is center point control when PWM counter operating in up-down counter type. 16 2 read-write 0 Do nothing #00 1 PWM period orcente point output Low #01 2 PWM period orcenter point output High #10 3 PWM period orcenter point output Toggle #11 PRDPCTL1 PWM Period or CenterPoint Control Note 1: PWM can control output level when PWM counter counts to (PERIODn+1). Note 2: This bit is center point control when PWM counter operating in up-down counter type. 18 2 read-write 0 Do nothing #00 1 PWM period orcente point output Low #01 2 PWM period orcenter point output High #10 3 PWM period orcenter point output Toggle #11 PRDPCTL2 PWM Period or CenterPoint Control Note 1: PWM can control output level when PWM counter counts to (PERIODn+1). Note 2: This bit is center point control when PWM counter operating in up-down counter type. 20 2 read-write 0 Do nothing #00 1 PWM period orcente point output Low #01 2 PWM period orcenter point output High #10 3 PWM period orcenter point output Toggle #11 PRDPCTL3 PWM Period or CenterPoint Control Note 1: PWM can control output level when PWM counter counts to (PERIODn+1). Note 2: This bit is center point control when PWM counter operating in up-down counter type. 22 2 read-write 0 Do nothing #00 1 PWM period orcente point output Low #01 2 PWM period orcenter point output High #10 3 PWM period orcenter point output Toggle #11 PRDPCTL4 PWM Period or CenterPoint Control Note 1: PWM can control output level when PWM counter counts to (PERIODn+1). Note 2: This bit is center point control when PWM counter operating in up-down counter type. 24 2 read-write 0 Do nothing #00 1 PWM period orcente point output Low #01 2 PWM period orcenter point output High #10 3 PWM period orcenter point output Toggle #11 PRDPCTL5 PWM Period or CenterPoint Control Note 1: PWM can control output level when PWM counter counts to (PERIODn+1). Note 2: This bit is center point control when PWM counter operating in up-down counter type. 26 2 read-write 0 Do nothing #00 1 PWM period orcente point output Low #01 2 PWM period orcenter point output High #10 3 PWM period orcenter point output Toggle #11 ZPCTL0 PWM Zero Point Control Note: PWM can control output level when PWM counter counts to 0. 0 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL1 PWM Zero Point Control Note: PWM can control output level when PWM counter counts to 0. 2 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL2 PWM Zero Point Control Note: PWM can control output level when PWM counter counts to 0. 4 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL3 PWM Zero Point Control Note: PWM can control output level when PWM counter counts to 0. 6 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL4 PWM Zero Point Control Note: PWM can control output level when PWM counter counts to 0. 8 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL5 PWM Zero Point Control Note: PWM can control output level when PWM counter counts to 0. 10 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 WGCTL1 PWM_WGCTL1 PWM Generation Register 1 0xB4 -1 read-write n 0x0 0x0 CMPDCTL0 PWM Compare Down Point Control Note 1: PWM can control output level when PWM counter counts down to CMPDAT. Note 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 16 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL1 PWM Compare Down Point Control Note 1: PWM can control output level when PWM counter counts down to CMPDAT. Note 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 18 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL2 PWM Compare Down Point Control Note 1: PWM can control output level when PWM counter counts down to CMPDAT. Note 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 20 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL3 PWM Compare Down Point Control Note 1: PWM can control output level when PWM counter counts down to CMPDAT. Note 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 22 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL4 PWM Compare Down Point Control Note 1: PWM can control output level when PWM counter counts down to CMPDAT. Note 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 24 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL5 PWM Compare Down Point Control Note 1: PWM can control output level when PWM counter counts down to CMPDAT. Note 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 26 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPUCTL0 PWM Compare Up Point Control Note 1: PWM can control output level when PWM counter counts up to CMPDAT. Note 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 0 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL1 PWM Compare Up Point Control Note 1: PWM can control output level when PWM counter counts up to CMPDAT. Note 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 2 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL2 PWM Compare Up Point Control Note 1: PWM can control output level when PWM counter counts up to CMPDAT. Note 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 4 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL3 PWM Compare Up Point Control Note 1: PWM can control output level when PWM counter counts up to CMPDAT. Note 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 6 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL4 PWM Compare Up Point Control Note 1: PWM can control output level when PWM counter counts up to CMPDAT. Note 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 8 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL5 PWM Compare Up Point Control Note 1: PWM can control output level when PWM counter counts up to CMPDAT. Note 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 10 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 SCS SYST_SCR Register Map SYST_SCR 0x0 0x10 0xC registers n 0xD04 0x10 registers n 0xD18 0xC registers n AIRCR AIRCR Application Interrupt and Reset Control Register 0xD0C -1 read-write n 0x0 0x0 ENDIANNESS Data Endianness 15 1 read-write 0 Little-endian #0 1 Big-endian #1 PRIGROUP Interrupt Priority Grouping This field determines the Split Of Group priority from subpriority, 8 3 read-write SYSRESETREQ System Reset Request Writing This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested This bit is write only and self-cleared as part of the reset sequence. 2 1 read-write VECTCLRACTIVE Exception Active Status Clear Bit Setting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions This bit is write only and can only be written when the core is halted. Note: It is the debugger's responsibility to re-initialize the stack. 1 1 read-write VECTORKEY Register Access Key When writing this register, this field should be 0x05FA, otherwise the write action will be unpredictable. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status. 16 16 read-write VECTRESET Reserved. 0 1 read-write ICSR ICSR Interrupt Control and State Register 0xD04 -1 read-write n 0x0 0x0 ISRPENDING Interrupt Pending Flag, Excluding NMI and Faults (Read Only) 22 1 read-only 0 Interrupt not pending #0 1 Interrupt pending #1 ISRPREEMPT Interrupt Preempt Bit (Read Only) If set, a pending exception will be serviced on exit from the debug halt state. 23 1 read-only NMIPENDSET NMI Set-pending Bit Write Operation: Note: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 31 1 read-write 0 No effect. NMI exception is not pending #0 1 Changes NMI exception state to pending. NMI exception is pending #1 PENDSTCLR SysTick Exception Clear-pending Bit Write Operation: Note: This is a write only bit. To clear the PENDST bit, you must 'write 0 to PENDSTSET and write 1 to PENDSTRTC_CAL' at the same time. 25 1 read-write 0 No effect #0 1 Removes the pending state from the SysTick exception #1 PENDSTSET SysTick Exception Set-pending Bit Write Operation: 26 1 read-write 0 No effect. SysTick exception is not pending #0 1 Changes SysTick exception state to pending. SysTick exception is pending #1 PENDSVCLR PendSV Clear-pending Bit Write Operation: Note: This is a write only bit. To clear the PENDSV bit, you must 'write 0 to PENDSVSET and write 1 to PENDSVRTC_CAL' at the same time. 27 1 read-write 0 No effect #0 1 Removes the pending state from the PendSV exception #1 PENDSVSET PendSV Set-pending Bit Write Operation: Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending. 28 1 read-write 0 No effect. PendSV exception is not pending #0 1 Changes PendSV exception state to pending. PendSV exception is pending #1 RETTOBASE Preempted Active Exceptions Indicator Indicate whether There are Preempted Active Exceptions 11 1 read-write 0 there are preempted active exceptions to execute #0 1 there are no active exceptions, or the currently-executing exception is the only active exception #1 VECTACTIVE Number of the Current Active Exception 0 6 read-write 0 Thread mode 0 VECTPENDING Number of the Highest Pended Exception Indicate the Exception Number of the Highest Priority Pending Enabled Exception The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register. 12 6 read-write 0 no pending exceptions 0 SCR SCR System Control Register 0xD10 -1 read-write n 0x0 0x0 SEVONPEND Send Event on Pending When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. 4 1 read-write 0 Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded #0 1 Enabled events and all interrupts, including disabled interrupts, can wake up the processor #1 SLEEPDEEP Processor Deep Sleep and Sleep Mode Selection Control Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode. 2 1 read-write 0 Sleep #0 1 Deep sleep #1 SLEEPONEXIT Sleep-on-exit Enable Control This bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode. Note: Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 1 1 read-write 0 Do not sleep when returning to Thread mode #0 1 Enter sleep, or deep sleep, on return from an ISR to Thread mode #1 SHPR1 SHPR1 System Handler Priority Register 1 0xD18 -1 read-write n 0x0 0x0 PRI_4 Priority of system handler 4, MemManage 0 8 read-write PRI_5 Priority of system handler 5, BusFault 8 8 read-write PRI_6 Priority of system handler 6, UsageFault 16 8 read-write SHPR2 SHPR2 System Handler Priority Register 2 0xD1C -1 read-write n 0x0 0x0 PRI_11 Priority of System Handler 11 - SVCall '0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write SHPR3 SHPR3 System Handler Priority Register 3 0xD20 -1 read-write n 0x0 0x0 PRI_14 Priority of System Handler 14 - PendSV '0' denotes the highest priority and '3' denotes the lowest priority. 22 2 read-write PRI_15 Priority of System Handler 15 - SysTick '0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write SYST_CTRL SYST_CTRL SysTick Control and Status Register 0x10 -1 read-write n 0x0 0x0 CLKSRC System Tick Clock Source Selection 2 1 read-write 0 Clock source is the (optional) external reference clock #0 1 Core clock used for SysTick #1 COUNTFLAG System Tick Counter Flag Returns 1 if timer counted to 0 since last time this register was read. COUNTFLAG is set by a count transition from 1 to 0. COUNTFLAG is cleared on read or by a write to the Current Value register. 16 1 read-write ENABLE System Tick Counter Enabled 0 1 read-write 0 Counter Disabled #0 1 Counter will operate in a multi-shot manner #1 TICKINT System Tick Interrupt Enabled 1 1 read-write 0 Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended #1 SYST_LOAD SYST_LOAD SysTick Reload Value Register 0x14 -1 read-write n 0x0 0x0 RELOAD System Tick Reload Value The value to load into the Current Value register when the counter reaches 0. 0 24 read-write SYST_VAL SYST_VAL SysTick Current Value Register 0x18 -1 read-write n 0x0 0x0 CURRENT System Tick Current Value Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. 0 24 read-write VTOR VTOR Vector Table Offset Register 0xD08 -1 read-write n 0x0 0x0 TBLOFF Table Offset Bits The vector table address for the selected Security state. 7 25 read-write SYS SYS Register Map SYS 0x0 0x0 0x14 registers n 0x100 0x4 registers n 0x18 0x8 registers n 0x1EC 0x4 registers n 0x24 0x8 registers n 0x30 0x8 registers n 0x44 0x4 registers n 0x50 0x8 registers n 0x60 0x8 registers n 0xB0 0x10 registers n 0xD0 0x8 registers n 0xE8 0x4 registers n 0xF0 0xC registers n BODCTL SYS_BODCTL Brown-out Detector Control Register 0x18 -1 read-write n 0x0 0x0 BODDGSEL Brown-out Detector Output De-glitch Time Select (Write Protect) Note: These bits are write protected. Refer to the SYS_REGLCTL register. 8 3 read-write 0 BOD output is sampled by RC32K clock #000 1 64 system clock (HCLK) #001 2 128 system clock (HCLK) #010 3 256 system clock (HCLK) #011 4 512 system clock (HCLK) #100 5 1024 system clock (HCLK) #101 6 2048 system clock (HCLK) #110 7 4096 system clock (HCLK) #111 BODEN Brown-out Detector Enable Bit (Write Protect) The default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]). Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by powr on reset. 0 1 read-write 0 Brown-out Detector function Disabled #0 1 Brown-out Detector function Enabled #1 BODIF Brown-out Detector Interrupt Flag Note: Write 1 to clear this bit to 0. 4 1 read-write 0 Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting #0 1 When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled #1 BODLPM Brown-out Detector Low Power Mode (Write Protect) Note 1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 BOD operate in normal mode (default) #0 1 BOD Low Power mode Enabled #1 BODOUT Brown-out Detector Output Status It means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled, this bit always responds 0000. 6 1 read-write 0 Brown-out Detector output status is 0 #0 1 Brown-out Detector output status is 1 #1 BODRSTEN Brown-out Reset Enable Bit (Write Protect) The default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit . Note 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. Note 3: Reset by powr on reset. 3 1 read-write 0 Brown-out 'INTERRUPT' function Enabled #0 1 Brown-out 'RESET' function Enabled #1 BODVL Brown-out Detector Threshold Voltage Selection (Write Protect) The default value is set by Flash controller user configuration register CBOV (CONFIG0 [22:21]). Note: This bit is write protected. Refer to the SYS_REGLCTL register. Note : reset by powr on reset 16 2 read-write 0 Brown-Out Detector threshold voltage is 2.3V #00 1 Brown-Out Detector threshold voltage is 2.7V #01 2 Brown-Out Detector threshold voltage is 3.7V #10 3 Brown-Out Detector threshold voltage is 4.4V #11 LVRDGSEL LVR Output De-glitch Time Select (Write Protect) Note: These bits are write protected. Refer to the SYS_REGLCTL register. 12 3 read-write 0 Without de-glitch function #000 1 64 system clock (HCLK) #001 2 128 system clock (HCLK) #010 3 256 system clock (HCLK) #011 4 512 system clock (HCLK) #100 5 1024 system clock (HCLK) #101 6 2048 system clock (HCLK) #110 7 4096 system clock (HCLK) #111 LVREN Low Voltage Reset Enable Bit (Write Protect) The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. Note 1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default). Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Low Voltage Reset function Disabled #0 1 Low Voltage Reset function Enabled #1 GPA_MFOS SYS_GPA_MFOS GPIOA Multiple Function Output Select Register 0xB0 -1 read-write n 0x0 0x0 MFOS0 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 0 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS1 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 1 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS10 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 10 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS11 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 11 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS12 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 12 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS13 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 13 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS14 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 14 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS15 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 15 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS2 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 2 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS3 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 3 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS4 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 4 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS5 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 5 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS6 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 6 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS7 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 7 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS8 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 8 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS9 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO. 9 1 read-write 0 Multiple funtion pin output mode type is unchanged #0 1 Multiple funtion pin output mode type is Open-drain mode #1 GPA_MFP0 SYS_GPA_MFP0 GPIOA Multiple Function Control Register 0 0x30 -1 read-write n 0x0 0x0 GPA0MFP PA.0 Multi-function Pin Selection 0 8 read-write GPA1MFP PA.1 Multi-function Pin Selection 8 8 read-write GPA2MFP PA.2 Multi-function Pin Selection 16 8 read-write GPA3MFP PA.3 Multi-function Pin Selection 24 8 read-write GPA_MFP1 SYS_GPA_MFP1 GPIOA Multiple Function Control Register 1 0x34 -1 read-write n 0x0 0x0 GPA4MFP PA.4 Multi-function Pin Selection 0 8 read-write GPA5MFP PA.5 Multi-function Pin Selection 8 8 read-write GPB_MFOS SYS_GPB_MFOS GPIOB Multiple Function Output Select Register 0xB4 -1 read-write n 0x0 0x0 GPB_MFP1 SYS_GPB_MFP1 GPIOB Multiple Function Control Register 1 0x44 -1 read-write n 0x0 0x0 GPB4MFP PB.4 Multi-function Pin Selection 0 8 read-write GPB5MFP PB.5 Multi-function Pin Selection 8 8 read-write GPB6MFP PB.6 Multi-function Pin Selection 16 8 read-write GPB7MFP PB.7 Multi-function Pin Selection 24 8 read-write GPC_MFOS SYS_GPC_MFOS GPIOC Multiple Function Output Select Register 0xB8 -1 read-write n 0x0 0x0 GPC_MFP0 SYS_GPC_MFP0 GPIOC Multiple Function Control Register 0 0x50 -1 read-write n 0x0 0x0 GPC0MFP PC.0 Multi-function Pin Selection 0 8 read-write GPC1MFP PC.1 Multi-function Pin Selection 8 8 read-write GPC2MFP PC.2 Multi-function Pin Selection 16 8 read-write GPC3MFP PC3 Multi-function Pin Selection 24 8 read-write GPC_MFP1 SYS_GPC_MFP1 GPIOC Multiple Function Control Register 1 0x54 -1 read-write n 0x0 0x0 GPC4MFP PC.4 Multi-function Pin Selection 0 8 read-write GPC5MFP PC.5 Multi-function Pin Selection 8 8 read-write GPC6MFP PC.6 Multi-function Pin Selection 16 8 read-write GPC7MFP PC.7Multi-function Pin Selection 24 8 read-write GPD_MFOS SYS_GPD_MFOS GPIOD Multiple Function Output Select Register 0xBC -1 read-write n 0x0 0x0 GPD_MFP0 SYS_GPD_MFP0 GPIOD Multiple Function Control Register 0 0x60 -1 read-write n 0x0 0x0 GPD0MFP PD.0 Multi-function Pin Selection 0 8 read-write GPD1MFP PD.1 Multi-function Pin Selection 8 8 read-write GPD2MFP PD.2 Multi-function Pin Selection 16 8 read-write GPD3MFP PD3 Multi-function Pin Selection 24 8 read-write GPD_MFP1 SYS_GPD_MFP1 GPIOD Multiple Function Control Register 1 0x64 -1 read-write n 0x0 0x0 GPD4MFP PD.4 Multi-function Pin Selection 0 8 read-write GPD5MFP PD.5 Multi-function Pin Selection 8 8 read-write GPD6MFP PD.6 Multi-function Pin Selection 16 8 read-write GPD7MFP PD.7Multi-function Pin Selection 24 8 read-write HIRCTRIMCTL SYS_HIRCTRIMCTL HIRC Trim Control Register 0xF0 -1 read-write n 0x0 0x0 BOUNDARY Boundary Selection Fill the boundary range from 0x1 to 0x1F, 0x0 is reserved. Note: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enable. 16 5 read-write BOUNDEN Boundary Enable Bit 9 1 read-write 0 Boundary function Disabled #0 1 Boundary function Enabled #1 CESTOPEN Clock Error Stop Enable Bit 8 1 read-write 0 The trim operation is keep going if clock is inaccuracy #0 1 The trim operation is stopped if clock is inaccuracy #1 FREQSEL Trim Frequency Selection This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim. During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 0 2 read-write 0 Disable HIRC auto trim function #00 1 Enable HIRC auto trim function and trim HIRC to 48 MHz #01 2 Reserved. #10 3 Reserved. #11 LOOPSEL Trim Calculation Loop Selection This field defines that trim value calculation is based on how many reference clocks. Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 4 2 read-write 0 Trim value calculation is based on average difference in 4 clocks of reference clock #00 1 Trim value calculation is based on average difference in 8 clocks of reference clock #01 2 Trim value calculation is based on average difference in 16 clocks of reference clock #10 3 Trim value calculation is based on average difference in 32 clocks of reference clock #11 REFCKSEL Reference Clock Selection Note: If there is no reference clock (LXT) when the rc_trim is enabled, CLKERIF (SYS_HIRCTRIMCTL[2]) will be set to 1. 10 1 read-write 0 HIRC trim reference clock is from LXT (32.768 kHz) #0 1 Reserved. #1 RETRYCNT Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. Once the HIRC locked, the internal trim value update counter will be reset. If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 6 2 read-write 0 Trim retry count limitation is 64 loops #00 1 Trim retry count limitation is 128 loops #01 2 Trim retry count limitation is 256 loops #10 3 Trim retry count limitation is 512 loops #11 HIRCTRIMIEN SYS_HIRCTRIMIEN HIRC Trim Interrupt Enable Register 0xF4 -1 read-write n 0x0 0x0 CLKEIEN Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. If this bit is set to1, and CLKERRIF(SYS_HIRCTRIMSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 2 1 read-write 0 Disable CLKERRIF(SYS_HIRCTRIMSTS[2]) status to trigger an interrupt to CPU #0 1 Enable CLKERRIF(SYS_HIRCTRIMSTS[2]) status to trigger an interrupt to CPU #1 TFALIEN Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTRIMCTL[1:0]). If this bit is high and TFAILIF(SYS_HIRCTRIMSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 1 1 read-write 0 Disable TFAILIF(SYS_HIRCTRIMSTS[1]) status to trigger an interrupt to CPU #0 1 Enable TFAILIF(SYS_HIRCTRIMSTS[1]) status to trigger an interrupt to CPU #1 HIRCTRIMSTS SYS_HIRCTRIMSTS HIRC Trim Interrupt Status Register 0xF8 -1 read-write n 0x0 0x0 CLKERIF Clock Error Interrupt Status When the frequency relation between reference clock and 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_HIRCTRIMCTL[8]) is set to 1. If this bit is set and CLKEIEN(SYS_HIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0. Note : reset by powr on reset 2 1 read-write 0 Clock frequency is accuracy #0 1 Clock frequency is inaccuracy #1 FREQLOCK HIRC Frequency Lock Status This bit indicates the HIRC frequency is locked. This is a status bit and doesn't trigger any interrupt Write 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled. Note : Reset by powr on reset. 0 1 read-write 0 The internal high-speed oscillator frequency doesn't lock at 48 MHz yet #0 1 The internal high-speed oscillator frequency locked at 48 MHz #1 OVBDIF Over Boundary Status When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. Note: Write 1 to clear this flag. 3 1 read-write 0 Over boundary coundition did not occur #0 1 Over boundary coundition occurred #1 TFAILIF Trim Failure Interrupt Status This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically. If this bit is set and TFAILIEN(SYS_HIRCIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0. Note : reset by powr on reset 1 1 read-write 0 Trim value update limitation count does not reach #0 1 Trim value update limitation count reached and HIRC frequency still not locked #1 IPRST0 SYS_IPRST0 Peripheral Reset Control Register 0 0x8 -1 read-write n 0x0 0x0 CHIPRST Chip One-shot Reset (Write Protect) Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload. About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2 Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by powr on reset. 0 1 read-write 0 Chip normal operation #0 1 Chip one-shot reset #1 CPURST Processor Core One-shot Reset (Write Protect) Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Processor core normal operation #0 1 Processor core one-shot reset #1 CRCRST CRC Calculation Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 CRC calculation controller normal operation #0 1 CRC calculation controller reset #1 HDIV_RST HDIV Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the hardware divider. User need to set this bit to 0 to release from the reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 Hardware divider controller normal operation #0 1 Hardware divider controller reset #1 PDMARST PDMA Controller Reset (Write Protect) Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 PDMA controller normal operation #0 1 PDMA controller reset #1 IPRST1 SYS_IPRST1 Peripheral Reset Control Register 1 0xC -1 read-write n 0x0 0x0 ACMP01RST Analog Comparator 0/1 Controller Reset 7 1 read-write 0 Analog Comparator 0/1 controller normal operation #0 1 Analog Comparator 0/1 controller reset #1 ADCRST ADC Controller Reset 28 1 read-write 0 ADC controller normal operation #0 1 ADC controller reset #1 CAN0RST CAN0 Controller Reset 24 1 read-write 0 CAN0 controller normal operation #0 1 CAN0 controller reset #1 GPIORST GPIO Controller Reset 1 1 read-write 0 GPIO controller normal operation #0 1 GPIO controller reset #1 TMR0RST Timer0 Controller Reset 2 1 read-write 0 Timer0 controller normal operation #0 1 Timer0 controller reset #1 TMR1RST Timer1 Controller Reset 3 1 read-write 0 Timer1 controller normal operation #0 1 Timer1 controller reset #1 TMR2RST Timer2 Controller Reset 4 1 read-write 0 Timer2 controller normal operation #0 1 Timer2 controller reset #1 TMR3RST Timer3 Controller Reset 5 1 read-write 0 Timer3 controller normal operation #0 1 Timer3 controller reset #1 UART0RST UART0 Controller Reset 16 1 read-write 0 UART0 controller normal operation #0 1 UART0 controller reset #1 UART1RST UART1 Controller Reset 17 1 read-write 0 UART1 controller normal operation #0 1 UART1 controller reset #1 IPRST2 SYS_IPRST2 Peripheral Reset Control Register 2 0x10 -1 read-write n 0x0 0x0 DAC0RST DAC0 Controller Reset 12 1 read-write 0 DAC0 controller normal operation #0 1 DAC0 controller reset #1 PWM0RST PWM0 Controller Reset 16 1 read-write 0 PWM0 controller normal operation #0 1 PWM0 controller reset #1 USCI0RST USCI0 Controller Reset 8 1 read-write 0 USCI0 controller normal operation #0 1 USCI0 controller reset #1 USCI1RST USCI1 Controller Reset 9 1 read-write 0 USCI1 controller normal operation #0 1 USCI1 controller reset #1 IVSCTL SYS_IVSCTL Internal Voltage Source Control Register 0x1C -1 read-write n 0x0 0x0 VTEMPEN Temperature Sensor Enable Bit This bit is used to enable/disable temperature sensor function. Note: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function chapter for details. 0 1 read-write 0 Temperature sensor function Disabled (default) #0 1 Temperature sensor function Enabled #1 MODCTL SYS_MODCTL Modulation Control Register 0xE8 -1 read-write n 0x0 0x0 MODEN Modulation Function Enable Bit This bit enables modulation funcion by modulating with PWM0 channel output and USCI0(USCI0_DAT0) or UART0(UART0_TXD) output. 0 1 read-write 0 Modulation Function Disabled #0 1 Modulation Function Enabled #1 MODH Modulation at Data High Select modulation pulse(PWM0) at high or low of UART0_TXD or USCI0_DAT0 1 1 read-write 0 Modulation pulse at UART0_TXD low or USCI0_DAT0 low #0 1 Modulation pulse at UART0_TXD high or USCI0_DAT0 high #1 MODPWMSEL PWM0 Channel Select for Modulation Select the PWM0 channel to modulate with the UART0_TXD or USCI0_DAT0. 0000: PWM0 Channel 0 modulate with UART0_TXD. 0001: PWM0 Channel 1 modulate with UART0_TXD. 0010: PWM0 Channel 2 modulate with UART0_TXD. 0011: PWM0 Channel 3 modulete with UART0_TXD. 0100: PWM0 Channel 4 modulete with UART0_TXD. 0101: PWM0 Channel 5 modulete with UART0_TXD. 0110: Reserved. 0111: Reserved. 1000: PWM0 Channel 0 modulate with USCI0_DAT0. 1001: PWM0 Channel 1 modulate with USCI0_DAT0. 1010: PWM0 Channel 2 modulate with USCI0_DAT0. 1011: PWM0 Channel 3 modulete with USCI0_DAT0. 1100: PWM0 Channel 4 modulete with USCI0_DAT0. 1101: PWM0 Channel 5 modulete with USCI0_DAT0. 1110: Reserved. 1111: Reserved. Note: This bis is valid while MODEN (SYS_MODCTL[0]) is set to 1. 4 4 read-write PDID SYS_PDID Part Device Identification Number Register 0x0 -1 read-only n 0x0 0x0 PDID Part Device Identification Number (Read Only) This register reflects device part number code. Software can read this register to identify which device is used. 0 32 read-only PORCTL SYS_PORCTL Power-On-reset Controller Register 0x24 -1 read-write n 0x0 0x0 POROFF Power-on Reset Enable Bit (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 16 read-write PORDISAN SYS_PORDISAN Analog POR Disable Control Register 0x1EC -1 read-write n 0x0 0x0 POROFFAN Power-on Reset Enable Bit (Write Protect) After powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field. The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 16 read-write REGLCTL SYS_REGLCTL Register Lock Control Register 0x100 -1 read-write n 0x0 0x0 REGLCTL Register Lock Control Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. REGLCTL[0] Register Lock Control Disable Index (Read Only) 0 8 write-only 0 Write-protection Enabled for writing protected registers. Any write to the protected register is ignored 0 1 Write-protection Disabled for writing protected registers 1 RSTSTS SYS_RSTSTS System Reset Status Register 0x4 -1 read-write n 0x0 0x0 BODRF BOD Reset Flag The BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 4 1 read-write 0 No reset from BOD #0 1 The BOD had issued the reset signal to reset the system #1 CPULKRF CPU Lockup Reset Flag Note: Write 1 to clear this bit to 0. Note 2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset. 8 1 read-write 0 No reset from CPU lockup happened #0 1 The Cortex-M0 lockup happened and chip is reset #1 CPURF CPU Reset Flag The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex- M0 Core and Flash Memory Controller (FMC). Note: Write to clear this bit to 0. 7 1 read-write 0 No reset from CPU #0 1 The Cortex-M0 Core and FMC are reset by software setting CPURST to 1 #1 LVRF LVR Reset Flag The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 3 1 read-write 0 No reset from LVR #0 1 LVR controller had issued the reset signal to reset the system #1 PINRF NRESET Pin Reset Flag The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 1 1 read-write 0 No reset from nRESET pin #0 1 Pin nRESET had issued the reset signal to reset the system #1 PORF POR Reset Flag The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 0 1 read-write 0 No reset from POR or CHIPRST #0 1 Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system #1 SYSRF System Reset Flag The system reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 5 1 read-write 0 No reset from Cortex-M0 #0 1 The Cortex- M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core #1 WDTRF WDT Reset Flag The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. Note 1: Write 1 to clear this bit to 0. Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. 2 1 read-write 0 No reset from watchdog timer or window watchdog timer #0 1 The watchdog timer or window watchdog timer had issued the reset signal to reset the system #1 SRAM_BISTCTL SYS_SRAM_BISTCTL System SRAM BIST Test Control Register 0xD0 -1 read-write n 0x0 0x0 PDMABIST PDMA BIST Enable Bit (Write Protect) This bit enables BIST test for PDMA RAM Note: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 system PDMA BIST Disabled #0 1 system PDMA BIST Enabled #1 SRAM_BISTSTS SYS_SRAM_BISTSTS System SRAM BIST Test Status Register 0xD4 -1 read-only n 0x0 0x0 PDMABISTF PDMA SRAM BIST Failed Flag 7 1 read-only 0 PDMA SRAM BIST pass #0 1 PDMA SRAM BIST failed #1 PDMAEND PDMA SRAM BIST Test Finish 23 1 read-only 0 PDMA SRAM BIST is active #0 1 PDMA SRAM BIST test finished #1 VREFCTL SYS_VREFCTL VREF Control Register 0x28 -1 read-write n 0x0 0x0 ADCPRESEL ADC Voltage Reference Note: These bits is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 ADC positive reference voltage comes from AVDD (voltage of VDD pin) #0 1 ADC positive reference voltage comes from internal or external VREF #1 PRELOADSEL Pre-load Timing Selection (Write Protect) Note: These bits is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 Pre-load time is 60us for 0.1uF Capacitor #0 1 Pre-load time is 310us for 1uF Capacitor #1 VREFCTL VREF Control Bits (Write Protect) Note 1: GPA1 needs to keep folating if Internal voltage reference is enabled. Note 2: These bits are write protected. Refer to the SYS_REGLCTL register. 0 4 read-write 0 VREF is from external pin #0000 1 VREF is internal 1.536V #0001 3 VREF is internal 2.048V #0011 5 VREF is internal 2.56V #0101 7 VREF is internal 3.072V #0111 9 VREF is internal 4.096V #1001 TMR01 TIMER Register Map TIMER 0x0 0x0 0x1C registers n 0x20 0x1C registers n TIMER0_CAP TIMER0_CAP Timer0 Capture Data Register 0x10 -1 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register When CAPEN (TIMERx_EXTCTL[3]) bit is set, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 0 24 read-only TIMER0_CMP TIMER0_CMP Timer0 Comparator Register 0x4 -1 read-write n 0x0 0x0 CMPDAT Timer Comparator Value CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using the newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. 0 24 read-write TIMER0_CNT TIMER0_CNT Timer0 Data Register 0xC -1 read-only n 0x0 0x0 CNT Timer Data Register Read this register to get CNT value. For example: If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value. If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value. 0 24 read-only TIMER0_CTL TIMER0_CTL Timer0 Control Register 0x0 -1 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only) This bit indicates the 24-bit up counter status. Note: This bit may be active when CNT 0 transition to CNT 1. 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CAPSRC Capture Pin Source Selection 16 1 read-write 0 Capture Function source is from TMx_EXT (x= 0~3) pin #0 1 Capture Function source is from internal ACMP output signal or LIRC. User can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which internal ACMP output signal or LIRC is timer capture source #1 CNTEN Timer Counting Enable Bit Note 3: Setting enable/disable this bit needs 2 * TMR_CLK period to become active. User can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 EXTCNTEN Event Counter Mode Enable Bit This bit is for external counting pin function enabled. Note 2: When TMR0/TMR2 INTRGEN is set to 1, this bit is forced to 1. When INTRGEN is 1 and TMR1/TMR3 CAPIF (TIMERx_EINTSTS[0]) is 1, this bit is forced to 0. 24 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 ICEDEBUG ICE Debug Mode Acknowledge Disable Bit (Write Protect) TIMER counter will keep going no matter CPU is held by ICE or not. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN Timer Interrupt Enable Bit Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer time-out interrupt Disabled #0 1 Timer time-out interrupt Enabled #1 INTRGEN Inter-timer Trigger Mode Enable Bit Setting this bit will enable the inter-timer trigger capture function. The Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function. Note: For Timer1/3, this bit is ignored and the read back value is always 0. 10 1 read-write 0 Inter-Timer Trigger mode Disabled #0 1 Inter-Timer Trigger mode Enabled #1 OPMODE Timer Counting Mode Select 27 2 read-write 0 The timer controller is operated in One-shot mode #00 1 The timer controller is operated in Periodic mode #01 2 The timer controller is operated in Toggle-output mode #10 3 The timer controller is operated in Continuous Counting mode #11 PSC Prescale Counter Note: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. 0 8 read-write RSTCNT Timer Counter Reset Bit Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1. Note: This bit will be auto cleared. 26 1 read-write 0 No effect #0 1 Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit #1 TGLPINSEL Toggle-output Pin Select 22 1 read-write 0 Toggle mode output to Tx (Timer Event Counter Pin) #0 1 Toggle mode output to Tx_EXT (Timer External Capture Pin) #1 TRGADC Trigger ADC Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC. 21 1 read-write 0 Timer interrupt trigger ADC Disabled #0 1 Timer interrupt trigger ADC Enabled #1 TRGDAC Trigger DAC Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger DAC. 20 1 read-write 0 Timer interrupt trigger DAC Disabled #0 1 Timer interrupt trigger DAC Enabled #1 TRGPDMA Trigger PDMA Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA. 8 1 read-write 0 Timer interrupt trigger PDMA Disabled #0 1 Timer interrupt trigger PDMA Enabled #1 TRGPWM Trigger PWM Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM. 19 1 read-write 0 Timer interrupt trigger PWM Disabled #0 1 Timer interrupt trigger PWM Enabled #1 TRGSSEL Trigger Source Select Bit This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal. 18 1 read-write 0 Timer time-out interrupt signal is used to trigger PWM, DAC, ADC and PDMA #0 1 Capture interrupt signal is used to trigger PWM, DAC, ADC and PDMA #1 WKEN Wake-up Function Enable Bit If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. 23 1 read-write 0 Wake-up function Disabled if timer interrupt signal generated #0 1 Wake-up function Enabled if timer interrupt signal generated #1 TIMER0_EINTSTS TIMER0_EINTSTS Timer0 External Interrupt Status Register 0x18 -1 read-write n 0x0 0x0 CAPIF Timer External Capture Interrupt Flag This bit indicates the timer external capture interrupt flag status. Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 0 1 read-write 0 TMx_EXT (x= 0~3) pin interrupt did not occur #0 1 TMx_EXT (x= 0~3) pin interrupt occurred #1 TIMER0_EXTCTL TIMER0_EXTCTL Timer0 External Control Register 0x14 -1 read-write n 0x0 0x0 CAPDBEN Timer External Capture Pin De-bounce Enable Bit Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. 6 1 read-write 0 TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled #0 1 TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled #1 CAPEDGE Timer External Capture Pin Edge Detect When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) will be set to 0. Disable Single Pulse Mode : 12 3 read-write 0 Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin. Measure falling edge ( falling edge transfer on TMx_EXT (x= 0~3) pin #000 1 Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin. Measure rising edge ( rising edge transfer on TMx_EXT (x= 0~3) pin #001 2 Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer #010 3 Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer #011 6 First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin. Measure falling edge ( rising edge transfer on TMx_EXT (x= 0~3) pin #110 7 First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin. Measure rising edge ( falling edge transfer on TMx_EXT (x= 0~3) pin #111 CAPEN Timer Capture Enable Bit This bit enables the capture input function. Note: TMR1/TMR3 CAPEN will be forced to 1 when TMR0/TMR2 INTRGEN is enabled. 3 1 read-write 0 Capture source Disabled #0 1 Capture source Enabled #1 CAPFUNCS Capture Function Selection 4 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 CAPIEN Timer External Capture Interrupt Enable Bit 5 1 read-write 0 TMx_EXT (x= 0~3) pin, LIRC, or ACMP detection Interrupt Disabled #0 1 TMx_EXT (x= 0~3) pin, LIRC, or ACMP detection Interrupt Enabled #1 CASIGMEN Capture Single Measure Mode Enable Bit Note: these bits only available when CAPEN (TIMERx_EXTCTL[3]) is 1. 20 1 read-write 0 Single Measure Mode Disabled #0 1 Single Measure Mode Enabled #1 CNTDBEN Timer Counter Pin De-bounce Enable Bit Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. 7 1 read-write 0 TMx (x= 0~3) pin de-bounce Disabled #0 1 TMx (x= 0~3) pin de-bounce Enabled #1 CNTPHASE Timer External Count Phase 0 1 read-write 0 A falling edge of external counting pin will be counted #0 1 A rising edge of external counting pin will be counted #1 ECNTSSEL Event Counter Source Selection to Trigger Event Counter Function 16 1 read-write 0 Event Counter input source is from TMx (x= 0~3) pin #0 1 Reserved. #1 INTERCAPSEL Internal Capture Source Selection to Trigger Capture Function Note: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1. 8 3 read-write 0 Capture Function source is from internal ACMP0 output signal #000 1 Capture Function source is from internal ACMP1 output signal #001 5 Capture Function source is from LIRC #101 SIGST Single Measure Start Bit User can write 1'b1 to this bit to let timer start measure TMx_EXT pin. When capture measure event finishes this bit will auto clear by hardware. 21 1 read-write TIMER0_INTSTS TIMER0_INTSTS Timer0 Interrupt Status Register 0x8 -1 read-write n 0x0 0x0 TIF Timer Interrupt Flag This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value. Note: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT value matches the CMPDAT value #1 TWKF Timer Wake-up Flag This bit indicates the interrupt wake-up flag status of timer. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated #1 TIMER1_CAP TIMER1_CAP Timer1 Capture Data Register 0x30 -1 read-write n 0x0 0x0 TIMER1_CMP TIMER1_CMP Timer1 Comparator Register 0x24 -1 read-write n 0x0 0x0 TIMER1_CNT TIMER1_CNT Timer1 Data Register 0x2C -1 read-write n 0x0 0x0 TIMER1_CTL TIMER1_CTL Timer1 Control Register 0x20 -1 read-write n 0x0 0x0 TIMER1_EINTSTS TIMER1_EINTSTS Timer1 External Interrupt Status Register 0x38 -1 read-write n 0x0 0x0 TIMER1_EXTCTL TIMER1_EXTCTL Timer1 External Control Register 0x34 -1 read-write n 0x0 0x0 TIMER1_INTSTS TIMER1_INTSTS Timer1 Interrupt Status Register 0x28 -1 read-write n 0x0 0x0 TMR23 TIMER Register Map TIMER 0x0 0x0 0x1C registers n 0x20 0x1C registers n TIMER2_CAP TIMER2_CAP Timer2 Capture Data Register 0x10 -1 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register When CAPEN (TIMERx_EXTCTL[3]) bit is set, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 0 24 read-only TIMER2_CMP TIMER2_CMP Timer2 Comparator Register 0x4 -1 read-write n 0x0 0x0 CMPDAT Timer Comparator Value CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using the newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. 0 24 read-write TIMER2_CNT TIMER2_CNT Timer2 Data Register 0xC -1 read-only n 0x0 0x0 CNT Timer Data Register Read this register to get CNT value. For example: If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value. If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value. 0 24 read-only TIMER2_CTL TIMER2_CTL Timer2 Control Register 0x0 -1 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only) This bit indicates the 24-bit up counter status. Note: This bit may be active when CNT 0 transition to CNT 1. 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CAPSRC Capture Pin Source Selection 16 1 read-write 0 Capture Function source is from TMx_EXT (x= 0~3) pin #0 1 Capture Function source is from internal ACMP output signal or LIRC. User can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which internal ACMP output signal or LIRC is timer capture source #1 CNTEN Timer Counting Enable Bit Note 3: Setting enable/disable this bit needs 2 * TMR_CLK period to become active. User can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 EXTCNTEN Event Counter Mode Enable Bit This bit is for external counting pin function enabled. Note 2: When TMR0/TMR2 INTRGEN is set to 1, this bit is forced to 1. When INTRGEN is 1 and TMR1/TMR3 CAPIF (TIMERx_EINTSTS[0]) is 1, this bit is forced to 0. 24 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 ICEDEBUG ICE Debug Mode Acknowledge Disable Bit (Write Protect) TIMER counter will keep going no matter CPU is held by ICE or not. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN Timer Interrupt Enable Bit Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer time-out interrupt Disabled #0 1 Timer time-out interrupt Enabled #1 INTRGEN Inter-timer Trigger Mode Enable Bit Setting this bit will enable the inter-timer trigger capture function. The Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function. Note: For Timer1/3, this bit is ignored and the read back value is always 0. 10 1 read-write 0 Inter-Timer Trigger mode Disabled #0 1 Inter-Timer Trigger mode Enabled #1 OPMODE Timer Counting Mode Select 27 2 read-write 0 The timer controller is operated in One-shot mode #00 1 The timer controller is operated in Periodic mode #01 2 The timer controller is operated in Toggle-output mode #10 3 The timer controller is operated in Continuous Counting mode #11 PSC Prescale Counter Note: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. 0 8 read-write RSTCNT Timer Counter Reset Bit Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1. Note: This bit will be auto cleared. 26 1 read-write 0 No effect #0 1 Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit #1 TGLPINSEL Toggle-output Pin Select 22 1 read-write 0 Toggle mode output to Tx (Timer Event Counter Pin) #0 1 Toggle mode output to Tx_EXT (Timer External Capture Pin) #1 TRGADC Trigger ADC Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC. 21 1 read-write 0 Timer interrupt trigger ADC Disabled #0 1 Timer interrupt trigger ADC Enabled #1 TRGDAC Trigger DAC Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger DAC. 20 1 read-write 0 Timer interrupt trigger DAC Disabled #0 1 Timer interrupt trigger DAC Enabled #1 TRGPDMA Trigger PDMA Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA. 8 1 read-write 0 Timer interrupt trigger PDMA Disabled #0 1 Timer interrupt trigger PDMA Enabled #1 TRGPWM Trigger PWM Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM. 19 1 read-write 0 Timer interrupt trigger PWM Disabled #0 1 Timer interrupt trigger PWM Enabled #1 TRGSSEL Trigger Source Select Bit This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal. 18 1 read-write 0 Timer time-out interrupt signal is used to trigger PWM, DAC, ADC and PDMA #0 1 Capture interrupt signal is used to trigger PWM, DAC, ADC and PDMA #1 WKEN Wake-up Function Enable Bit If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. 23 1 read-write 0 Wake-up function Disabled if timer interrupt signal generated #0 1 Wake-up function Enabled if timer interrupt signal generated #1 TIMER2_EINTSTS TIMER2_EINTSTS Timer2 External Interrupt Status Register 0x18 -1 read-write n 0x0 0x0 CAPIF Timer External Capture Interrupt Flag This bit indicates the timer external capture interrupt flag status. Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 0 1 read-write 0 TMx_EXT (x= 0~3) pin interrupt did not occur #0 1 TMx_EXT (x= 0~3) pin interrupt occurred #1 TIMER2_EXTCTL TIMER2_EXTCTL Timer2 External Control Register 0x14 -1 read-write n 0x0 0x0 CAPDBEN Timer External Capture Pin De-bounce Enable Bit Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. 6 1 read-write 0 TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled #0 1 TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled #1 CAPEDGE Timer External Capture Pin Edge Detect When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) will be set to 0. Disable Single Pulse Mode : 12 3 read-write 0 Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin. Measure falling edge ( falling edge transfer on TMx_EXT (x= 0~3) pin #000 1 Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin. Measure rising edge ( rising edge transfer on TMx_EXT (x= 0~3) pin #001 2 Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer #010 3 Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer #011 6 First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin. Measure falling edge ( rising edge transfer on TMx_EXT (x= 0~3) pin #110 7 First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin. Measure rising edge ( falling edge transfer on TMx_EXT (x= 0~3) pin #111 CAPEN Timer Capture Enable Bit This bit enables the capture input function. Note: TMR1/TMR3 CAPEN will be forced to 1 when TMR0/TMR2 INTRGEN is enabled. 3 1 read-write 0 Capture source Disabled #0 1 Capture source Enabled #1 CAPFUNCS Capture Function Selection 4 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 CAPIEN Timer External Capture Interrupt Enable Bit 5 1 read-write 0 TMx_EXT (x= 0~3) pin, LIRC, or ACMP detection Interrupt Disabled #0 1 TMx_EXT (x= 0~3) pin, LIRC, or ACMP detection Interrupt Enabled #1 CASIGMEN Capture Single Measure Mode Enable Bit Note: these bits only available when CAPEN (TIMERx_EXTCTL[3]) is 1. 20 1 read-write 0 Single Measure Mode Disabled #0 1 Single Measure Mode Enabled #1 CNTDBEN Timer Counter Pin De-bounce Enable Bit Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. 7 1 read-write 0 TMx (x= 0~3) pin de-bounce Disabled #0 1 TMx (x= 0~3) pin de-bounce Enabled #1 CNTPHASE Timer External Count Phase 0 1 read-write 0 A falling edge of external counting pin will be counted #0 1 A rising edge of external counting pin will be counted #1 ECNTSSEL Event Counter Source Selection to Trigger Event Counter Function 16 1 read-write 0 Event Counter input source is from TMx (x= 0~3) pin #0 1 Reserved. #1 INTERCAPSEL Internal Capture Source Selection to Trigger Capture Function Note: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1. 8 3 read-write 0 Capture Function source is from internal ACMP0 output signal #000 1 Capture Function source is from internal ACMP1 output signal #001 5 Capture Function source is from LIRC #101 SIGST Single Measure Start Bit User can write 1'b1 to this bit to let timer start measure TMx_EXT pin. When capture measure event finishes this bit will auto clear by hardware. 21 1 read-write TIMER2_INTSTS TIMER2_INTSTS Timer2 Interrupt Status Register 0x8 -1 read-write n 0x0 0x0 TIF Timer Interrupt Flag This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value. Note: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT value matches the CMPDAT value #1 TWKF Timer Wake-up Flag This bit indicates the interrupt wake-up flag status of timer. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated #1 TIMER3_CAP TIMER3_CAP Timer3 Capture Data Register 0x30 -1 read-write n 0x0 0x0 TIMER3_CMP TIMER3_CMP Timer3 Comparator Register 0x24 -1 read-write n 0x0 0x0 TIMER3_CNT TIMER3_CNT Timer3 Data Register 0x2C -1 read-write n 0x0 0x0 TIMER3_CTL TIMER3_CTL Timer3 Control Register 0x20 -1 read-write n 0x0 0x0 TIMER3_EINTSTS TIMER3_EINTSTS Timer3 External Interrupt Status Register 0x38 -1 read-write n 0x0 0x0 TIMER3_EXTCTL TIMER3_EXTCTL Timer3 External Control Register 0x34 -1 read-write n 0x0 0x0 TIMER3_INTSTS TIMER3_INTSTS Timer3 Interrupt Status Register 0x28 -1 read-write n 0x0 0x0 UART0 UART Register Map UART 0x0 0x0 0x54 registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length Note : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit Note : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF (UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit This bit is used to enable RS-485 Address Detection mode. Note: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value This field contains the RS-485 address match values. Note: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length This field indicates a 4-bit LIN TX break field count. Note1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit Note: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD) Note: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) Note: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0 This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.114. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1 This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.114. Note: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.114. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1 This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.114. 24 4 read-write UART_BRCOMP UART_BRCOMP UART Baud Rate Compensation Register 0x3C -1 read-write n 0x0 0x0 BRCOMP Baud Rate Compensation Patten These 9-bits are used to define the relative bit is compensated or not. BRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8]). 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 -1 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer Write Operation: By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read Operation: By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY Parity Bit Receive/Transmit Buffer Write Operation: By writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. Read Operation: If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit. Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Incoming Data Wake-up Compensation Register 0x48 -1 read-write n 0x0 0x0 STCOMP Start Bit Compensation Value These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode. Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Note: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit The receiver is disabled or not (set 1 to disable receiver). Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag This bit is set to logic '1' when auto-baud rate detect function is finished. Note: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. Note: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. Note2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits). Note: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. Note: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only) This bit initiate RX FIFO empty or not. Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only) This bit initiates RX FIFO full or not. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only) This bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag This bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only) This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one. The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only) This bit indicates TX FIFO empty or not. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only) This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only) This bit indicates TX FIFO full or not. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. Note: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only) This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only) This bit indicates TX and RX are active or inactive. Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 -1 read-write n 0x0 0x0 DGE Deglitch Enable Bit Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic. 6 1 read-write 0 Deglitch Disabled #0 1 Deglitch Enabled #1 FUNCSEL Function Select 0 3 read-write 0 UART function #000 1 LIN function #001 2 IrDA function #010 3 RS-485 function #011 4 UART Single-wire function #100 TXRXDIS TX and RX Disable Bit Setting this bit can disable TX and RX. Note: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 -1 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit Note: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit This bit can enable or disable RX PDMA service. Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 SWBEIEN Single-wire Bit Error Detection Interrupt Enable Bit Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT (UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF (UART_INTSTS[16]) is set. Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. 16 1 read-write 0 Single-wire Bit Error Detect Inerrupt Disabled #0 1 Single-wire Bit Error Detect Inerrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only) This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only) This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared if both of RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF (UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF (UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF (UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag Note: This bit is cleared when SLVHDETF (UART_LINSTS[0]), SLVHEF (UART_LINSTS[1]), SLVIDPEF (UART_LINSTS[2]), SLVHTOF (UART_LINSTS[4]), RTOUTF (UART_LINSTS[5]), BRKDETF (UART_LINSTS[8]), and BITEF (UART_LINSTS[9]) all are cleared and software writing '1' to LINIF (UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, SLVHEF, SLVIDPEF, SLVHTOF, RTOUTF, BITEF, and BRKDETF is generated #0 1 At least one of SLVHDETF, SLVHEF, SLVIDPEF, SLVHTOF, RTOUTF, BITEF, and BRKDETF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only) This bit is set if LINIEN (UART_INTEN[8]) and LINIF (UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and MODEMIF (UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated. #1 RDAIF Receive Data Available Interrupt Flag When the number of bytes in the RX FIFO equals the RFITL then the RDAIF (UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-write 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only) This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 SWBEIF Single-wire Bit Error Detection Interrupt Flag This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode. Note1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. Note2: This bit can be cleared by writing '1' to it. 16 1 read-write 0 No single-wire bit error detection interrupt flag is generated #0 1 Single-wire bit error detection interrupt flag is generated #1 SWBEINT Single-wire Bit Error Detect Interrupt Indicator (Read Only) This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1. 24 1 read-only 0 No Single-wire Bit Error Detection Interrupt generated #0 1 Single-wire Bit Error Detection Interrupt generated #1 THREIF Transmit Holding Register Empty Interrupt Flag This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-write 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only) This bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-write 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF (UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only) This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF (UART_WKSTS[0]) is set to 1. Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only) This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINCTL UART_LINCTL UART LIN Control Register 0x34 -1 read-write n 0x0 0x0 BITERREN Bit Error Detect Enable Bit 12 1 read-write 0 Bit error detection function Disabled #0 1 Bit error detection function Enabled #1 BRKDETEN LIN Break Detection Enable Bit 10 1 read-write 0 LIN break detection Disabled #0 1 LIN break detection Enabled #1 BRKFL LIN Break Field Length This field indicates a 4-bit LIN TX break field count. Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]). Note2: This break field length is BRKFL + 1. 16 4 read-write BSL LIN Break/Sync Delimiter Length Note: This bit used for LIN master to sending header field. 20 2 read-write 0 The LIN break/sync delimiter length is 1-bit time #00 1 The LIN break/sync delimiter length is 2-bit time #01 2 The LIN break/sync delimiter length is 3-bit time #10 3 The LIN break/sync delimiter length is 4-bit time #11 HSEL LIN Header Select 22 2 read-write 0 The LIN header includes 'break field' #00 1 The LIN header includes 'break field' and 'sync field' #01 2 The LIN header includes 'break field', 'sync field' and 'frame ID field' #10 3 Reserved. #11 IDPEN LIN ID Parity Enable Bit 9 1 read-write 0 LIN frame ID parity Disabled #0 1 LIN frame ID parity Enabled #1 LINRXOFF LIN Receiver Disable Bit 11 1 read-write 0 LIN receiver Enabled #0 1 LIN receiver Disabled #1 MUTE LIN Mute Mode Enable Bit Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.11.5.10 (LIN slave mode). 4 1 read-write 0 LIN mute mode Disabled #0 1 LIN mute mode Enabled #1 PID LIN PID Bits If the parity generated by hardware, user fill ID0~ID5 (PID[29:24]), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field. Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first). Note2: This field can be used for LIN master mode or slave mode. 24 8 read-write RTOUTEN LIN Response Time-out Detection Enable Bit 5 1 read-write 0 LIN response time-out detection Disabled #0 1 LIN response time-out detection Enabled #1 SENDH LIN TX Send Header Enable Bit The LIN TX header can be 'break field' or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]). Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL[7]) user can read/write it by setting LINTXEN (UART_ALTCTL[7]) or SENDH (UART_LINCTL[8]). Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 8 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 SLVAREN LIN Slave Automatic Resynchronization Mode Enable Bit Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1). Note3: The control and interactions of this field are explained in 6.11.5.10 (Slave mode with automatic resynchronization). 2 1 read-write 0 LIN automatic resynchronization Disabled #0 1 LIN automatic resynchronization Enabled #1 SLVDUEN LIN Slave Divider Update Method Enable Bit Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) Note3: The control and interactions of this field are explained in 6.11.5.10 (Slave mode with automatic resynchronization). 3 1 read-write 0 UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time) #0 1 UART_BAUD is updated at the next received character. User must set the bit before checksum reception #1 SLVEN LIN Slave Mode Enable Bit 0 1 read-write 0 LIN slave mode Disabled #0 1 LIN slave mode Enabled #1 SLVHDEN LIN Slave Header Detection Enable Bit 1 1 read-write 0 LIN slave header detection Disabled #0 1 LIN slave header detection Enabled #1 UART_LINE UART_LINE UART Line Control Register 0xC -1 read-write n 0x0 0x0 BCB Break Control Bit Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit Note: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE Parity Bit Enable Bit Note: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 Parity bit generated Disabled #0 1 Parity bit generated Enabled #1 PSS Parity Bit Source Selection The parity bit can be selected to be generated and checked automatically or by software. Note1: This bit has effect only when PBE (UART_LINE[3]) is set. Note2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 Parity bit generated and checked by software #1 RXDINV RX Data Inverted Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART, LIN, or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART, LIN, or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection This field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_LINRTOUT UART_LINRTOUT UART LIN Response Time-out Register 0x4C -1 read-write n 0x0 0x0 LINRTOIC LIN Response Time-out Comparator 0 24 read-write UART_LINSTS UART_LINSTS UART LIN Status Register 0x38 -1 read-write n 0x0 0x0 BITEF Bit Error Detect Status Flag At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. 9 1 read-write 0 Bit error not detected #0 1 Bit error detected #1 BRKDETF LIN Break Detection Flag This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. 8 1 read-write 0 LIN break not detected #0 1 LIN break detected #1 RTOUTF LIN Response Time-out Flag This bit is set when no LIN response received and the time-out counter equal to or bigger than LINRTOIC (UART_LINRTOUT[23:0]). If LINIEN (UART_INTEN[8]) is enabled, the LIN Bus Interrupt will be generated. Note1: This bit can be cleared by writing 1 to it. 5 1 read-write 0 LIN response time-out not detected #0 1 LIN response time-out detected #1 SLVHDETF LIN Slave Header Detection Flag This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it. Note3: When enable ID parity check IDPEN (UART_LINCTL[9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not. 0 1 read-write 0 LIN header not detected #0 1 LIN header detected (break + sync + frame ID) #1 SLVHEF LIN Slave Header Error Flag This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', 'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', 'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'. 1 1 read-write 0 LIN header error not detected #0 1 LIN header error detected #1 SLVHTOF LIN Slave Header Time-out Flag This bit is set by hardware when a LIN header reception time-out is detected in LIN slave mode and be cleared by writing 1 to it. When this bit is set, SLVHEF (UART_LINSTS[1]) will also be set. 4 1 read-write 0 LIN header time-out not detected #0 1 LIN header time-out detected #1 SLVIDPEF LIN Slave ID Parity Error Flag This bit is set by hardware when receipted frame ID parity is not correct. 2 1 read-write 0 No active #0 1 Receipted frame ID parity is not correct #1 SLVSYNCF LIN Slave Sync Field This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. 3 1 read-write 0 The current character is not at LIN sync state #0 1 The current character is at LIN sync state #1 UART_LINWKCTL UART_LINWKCTL UART LIN Wake-up Control Register 0x50 -1 read-write n 0x0 0x0 LINWKC LIN Send Wake-up Signal Length Counter 0 24 read-write LINWKEN LIN Wake-up Enable Bit Note1: When the system is in Power-down mode, LIN wake-up event will wake up system from Power-down mode. 28 1 read-write 0 LIN wake-up system function Disabled #0 1 LIN wake-up system function Enabled #1 LINWKF LIN Wake-up Flag This bit is set if chip wake-up from power-down state by LIN wake-up. Note1: If LINWKEN (UART_LINWKCTL[28]) is enabled, the LIN wake-up event will cause this bit set to '1'. Note2: This bit can be cleared by writing '1' to it. 29 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by LIN wake-up #1 SENDLINW LIN Send Wake-up Enable Bit Note1: When this bit is set, the UART will send LIN wake-up automatically. When LIN wake-up transfer operation finished, this bit will be cleared automatically. 24 1 read-write 0 Send LIN Wake-up Disabled #0 1 Send LIN Wake-up Enabled #1 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. Note1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. Note2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. Note3: Single-wire mode supports this feature. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level This bit defines the active level state of nRTS pin output. Note1: Refer to Figure 6.1113 and Figure 6.1114 for UART function mode. Note2: Refer to Figure 6.1124 and Figure 6.1125 for RS-485 function mode. Note3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only) This bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level This bit defines the active level state of nCTS pin input. Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only) This bit mirror from nCTS pin input of voltage logic status. Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 -1 read-write n 0x0 0x0 DLY TX Delay Time Value This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 -1 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit Note:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode. 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit Note:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit Note1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. Note2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit Note1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode. Note2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 -1 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag This bit is set if chip wake-up from power-down state by nCTS wake-up. Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag This bit is set if chip wake-up from power-down state by data wake-up. Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up. Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out #1 UART1 UART Register Map UART 0x0 0x0 0x54 registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length Note : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit Note : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF (UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit This bit is used to enable RS-485 Address Detection mode. Note: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value This field contains the RS-485 address match values. Note: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length This field indicates a 4-bit LIN TX break field count. Note1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit Note: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD) Note: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) Note: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0 This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.114. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1 This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.114. Note: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.114. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1 This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.114. 24 4 read-write UART_BRCOMP UART_BRCOMP UART Baud Rate Compensation Register 0x3C -1 read-write n 0x0 0x0 BRCOMP Baud Rate Compensation Patten These 9-bits are used to define the relative bit is compensated or not. BRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8]). 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 -1 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer Write Operation: By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read Operation: By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY Parity Bit Receive/Transmit Buffer Write Operation: By writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. Read Operation: If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit. Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Incoming Data Wake-up Compensation Register 0x48 -1 read-write n 0x0 0x0 STCOMP Start Bit Compensation Value These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode. Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Note: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit The receiver is disabled or not (set 1 to disable receiver). Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag This bit is set to logic '1' when auto-baud rate detect function is finished. Note: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. Note: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. Note2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits). Note: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. Note: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only) This bit initiate RX FIFO empty or not. Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only) This bit initiates RX FIFO full or not. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only) This bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag This bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only) This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one. The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only) This bit indicates TX FIFO empty or not. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only) This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only) This bit indicates TX FIFO full or not. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. Note: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only) This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only) This bit indicates TX and RX are active or inactive. Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 -1 read-write n 0x0 0x0 DGE Deglitch Enable Bit Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic. 6 1 read-write 0 Deglitch Disabled #0 1 Deglitch Enabled #1 FUNCSEL Function Select 0 3 read-write 0 UART function #000 1 LIN function #001 2 IrDA function #010 3 RS-485 function #011 4 UART Single-wire function #100 TXRXDIS TX and RX Disable Bit Setting this bit can disable TX and RX. Note: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 -1 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit Note: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit This bit can enable or disable RX PDMA service. Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 SWBEIEN Single-wire Bit Error Detection Interrupt Enable Bit Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT (UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF (UART_INTSTS[16]) is set. Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. 16 1 read-write 0 Single-wire Bit Error Detect Inerrupt Disabled #0 1 Single-wire Bit Error Detect Inerrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only) This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only) This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared if both of RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF (UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF (UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF (UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag Note: This bit is cleared when SLVHDETF (UART_LINSTS[0]), SLVHEF (UART_LINSTS[1]), SLVIDPEF (UART_LINSTS[2]), SLVHTOF (UART_LINSTS[4]), RTOUTF (UART_LINSTS[5]), BRKDETF (UART_LINSTS[8]), and BITEF (UART_LINSTS[9]) all are cleared and software writing '1' to LINIF (UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, SLVHEF, SLVIDPEF, SLVHTOF, RTOUTF, BITEF, and BRKDETF is generated #0 1 At least one of SLVHDETF, SLVHEF, SLVIDPEF, SLVHTOF, RTOUTF, BITEF, and BRKDETF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only) This bit is set if LINIEN (UART_INTEN[8]) and LINIF (UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and MODEMIF (UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag When the number of bytes in the RX FIFO equals the RFITL then the RDAIF (UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-write 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only) This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 SWBEIF Single-wire Bit Error Detection Interrupt Flag This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode. Note1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. Note2: This bit can be cleared by writing '1' to it. 16 1 read-write 0 No single-wire bit error detection interrupt flag is generated #0 1 Single-wire bit error detection interrupt flag is generated #1 SWBEINT Single-wire Bit Error Detect Interrupt Indicator (Read Only) This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1. 24 1 read-only 0 No Single-wire Bit Error Detection Interrupt generated #0 1 Single-wire Bit Error Detection Interrupt generated #1 THREIF Transmit Holding Register Empty Interrupt Flag This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-write 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only) This bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-write 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF (UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only) This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF (UART_WKSTS[0]) is set to 1. Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only) This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINCTL UART_LINCTL UART LIN Control Register 0x34 -1 read-write n 0x0 0x0 BITERREN Bit Error Detect Enable Bit 12 1 read-write 0 Bit error detection function Disabled #0 1 Bit error detection function Enabled #1 BRKDETEN LIN Break Detection Enable Bit 10 1 read-write 0 LIN break detection Disabled #0 1 LIN break detection Enabled #1 BRKFL LIN Break Field Length This field indicates a 4-bit LIN TX break field count. Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]). Note2: This break field length is BRKFL + 1. 16 4 read-write BSL LIN Break/Sync Delimiter Length Note: This bit used for LIN master to sending header field. 20 2 read-write 0 The LIN break/sync delimiter length is 1-bit time #00 1 The LIN break/sync delimiter length is 2-bit time #01 2 The LIN break/sync delimiter length is 3-bit time #10 3 The LIN break/sync delimiter length is 4-bit time #11 HSEL LIN Header Select 22 2 read-write 0 The LIN header includes 'break field' #00 1 The LIN header includes 'break field' and 'sync field' #01 2 The LIN header includes 'break field', 'sync field' and 'frame ID field' #10 3 Reserved. #11 IDPEN LIN ID Parity Enable Bit 9 1 read-write 0 LIN frame ID parity Disabled #0 1 LIN frame ID parity Enabled #1 LINRXOFF LIN Receiver Disable Bit 11 1 read-write 0 LIN receiver Enabled #0 1 LIN receiver Disabled #1 MUTE LIN Mute Mode Enable Bit Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.11.5.10 (LIN slave mode). 4 1 read-write 0 LIN mute mode Disabled #0 1 LIN mute mode Enabled #1 PID LIN PID Bits If the parity generated by hardware, user fill ID0~ID5 (PID[29:24]), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field. Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first). Note2: This field can be used for LIN master mode or slave mode. 24 8 read-write RTOUTEN LIN Response Time-out Detection Enable Bit 5 1 read-write 0 LIN response time-out detection Disabled #0 1 LIN response time-out detection Enabled #1 SENDH LIN TX Send Header Enable Bit The LIN TX header can be 'break field' or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]). Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL[7]) user can read/write it by setting LINTXEN (UART_ALTCTL[7]) or SENDH (UART_LINCTL[8]). Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 8 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 SLVAREN LIN Slave Automatic Resynchronization Mode Enable Bit Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1). Note3: The control and interactions of this field are explained in 6.11.5.10 (Slave mode with automatic resynchronization). 2 1 read-write 0 LIN automatic resynchronization Disabled #0 1 LIN automatic resynchronization Enabled #1 SLVDUEN LIN Slave Divider Update Method Enable Bit Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) Note3: The control and interactions of this field are explained in 6.11.5.10 (Slave mode with automatic resynchronization). 3 1 read-write 0 UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time) #0 1 UART_BAUD is updated at the next received character. User must set the bit before checksum reception #1 SLVEN LIN Slave Mode Enable Bit 0 1 read-write 0 LIN slave mode Disabled #0 1 LIN slave mode Enabled #1 SLVHDEN LIN Slave Header Detection Enable Bit 1 1 read-write 0 LIN slave header detection Disabled #0 1 LIN slave header detection Enabled #1 UART_LINE UART_LINE UART Line Control Register 0xC -1 read-write n 0x0 0x0 BCB Break Control Bit Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit Note: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE Parity Bit Enable Bit Note: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 Parity bit generated Disabled #0 1 Parity bit generated Enabled #1 PSS Parity Bit Source Selection The parity bit can be selected to be generated and checked automatically or by software. Note1: This bit has effect only when PBE (UART_LINE[3]) is set. Note2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 Parity bit generated and checked by software #1 RXDINV RX Data Inverted Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART, LIN, or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART, LIN, or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection This field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_LINRTOUT UART_LINRTOUT UART LIN Response Time-out Register 0x4C -1 read-write n 0x0 0x0 LINRTOIC LIN Response Time-out Comparator 0 24 read-write UART_LINSTS UART_LINSTS UART LIN Status Register 0x38 -1 read-write n 0x0 0x0 BITEF Bit Error Detect Status Flag At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. 9 1 read-write 0 Bit error not detected #0 1 Bit error detected #1 BRKDETF LIN Break Detection Flag This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. 8 1 read-write 0 LIN break not detected #0 1 LIN break detected #1 RTOUTF LIN Response Time-out Flag This bit is set when no LIN response received and the time-out counter equal to or bigger than LINRTOIC (UART_LINRTOUT[23:0]). If LINIEN (UART_INTEN[8]) is enabled, the LIN Bus Interrupt will be generated. Note1: This bit can be cleared by writing 1 to it. 5 1 read-write 0 LIN response time-out not detected #0 1 LIN response time-out detected #1 SLVHDETF LIN Slave Header Detection Flag This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it. Note3: When enable ID parity check IDPEN (UART_LINCTL[9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not. 0 1 read-write 0 LIN header not detected #0 1 LIN header detected (break + sync + frame ID) #1 SLVHEF LIN Slave Header Error Flag This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', 'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', 'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'. 1 1 read-write 0 LIN header error not detected #0 1 LIN header error detected #1 SLVHTOF LIN Slave Header Time-out Flag This bit is set by hardware when a LIN header reception time-out is detected in LIN slave mode and be cleared by writing 1 to it. When this bit is set, SLVHEF (UART_LINSTS[1]) will also be set. 4 1 read-write 0 LIN header time-out not detected #0 1 LIN header time-out detected #1 SLVIDPEF LIN Slave ID Parity Error Flag This bit is set by hardware when receipted frame ID parity is not correct. 2 1 read-write 0 No active #0 1 Receipted frame ID parity is not correct #1 SLVSYNCF LIN Slave Sync Field This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. 3 1 read-write 0 The current character is not at LIN sync state #0 1 The current character is at LIN sync state #1 UART_LINWKCTL UART_LINWKCTL UART LIN Wake-up Control Register 0x50 -1 read-write n 0x0 0x0 LINWKC LIN Send Wake-up Signal Length Counter 0 24 read-write LINWKEN LIN Wake-up Enable Bit Note1: When the system is in Power-down mode, LIN wake-up event will wake up system from Power-down mode. 28 1 read-write 0 LIN wake-up system function Disabled #0 1 LIN wake-up system function Enabled #1 LINWKF LIN Wake-up Flag This bit is set if chip wake-up from power-down state by LIN wake-up. Note1: If LINWKEN (UART_LINWKCTL[28]) is enabled, the LIN wake-up event will cause this bit set to '1'. Note2: This bit can be cleared by writing '1' to it. 29 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by LIN wake-up #1 SENDLINW LIN Send Wake-up Enable Bit Note1: When this bit is set, the UART will send LIN wake-up automatically. When LIN wake-up transfer operation finished, this bit will be cleared automatically. 24 1 read-write 0 Send LIN Wake-up Disabled #0 1 Send LIN Wake-up Enabled #1 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. Note1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. Note2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. Note3: Single-wire mode supports this feature. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level This bit defines the active level state of nRTS pin output. Note1: Refer to Figure 6.1113 and Figure 6.1114 for UART function mode. Note2: Refer to Figure 6.1124 and Figure 6.1125 for RS-485 function mode. Note3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only) This bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level This bit defines the active level state of nCTS pin input. Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only) This bit mirror from nCTS pin input of voltage logic status. Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 -1 read-write n 0x0 0x0 DLY TX Delay Time Value This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 -1 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit Note:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode. 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit Note:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit Note1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. Note2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit Note1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode. Note2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 -1 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag This bit is set if chip wake-up from power-down state by nCTS wake-up. Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag This bit is set if chip wake-up from power-down state by data wake-up. Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up. Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out #1 UI2C0 UI2CI2C Register Map UI2CI2C 0x0 0x0 0x4 registers n 0x2C 0xC registers n 0x44 0x24 registers n 0x8 0x4 registers n 0x88 0x8 registers n UI2C_ADDRMSK0 UI2C_ADDRMSK0 USCI Device Address Mask Register 0 0x4C -1 read-write n 0x0 0x0 ADDRMSK USCI Device Address Mask USCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 0 10 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 UI2C_ADDRMSK1 UI2C_ADDRMSK1 USCI Device Address Mask Register 1 0x50 -1 read-write n 0x0 0x0 UI2C_ADMAT UI2C_ADMAT I2C Slave Match Address Register 0x88 -1 read-write n 0x0 0x0 ADMAT0 USCI Address 0 Match Status Register When address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 0 1 read-write ADMAT1 USCI Address 1 Match Status Register When address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 1 1 read-write UI2C_BRGEN UI2C_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider 16 10 read-write DSCNT Denominator for Sample Counter This bit field defines the divide ratio of the sample clock fSAMP_CLK. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection This bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection This bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved. #1 SPCLKSEL Sample Clock Source Selection This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit This bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter Disabled #0 1 Time measurement counter Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 UI2C_CTL UI2C_CTL USCI Control Register 0x0 -1 read-write n 0x0 0x0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE. Note: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UI2C_DEVADDR0 UI2C_DEVADDR0 USCI Device Address Register 0 0x44 -1 read-write n 0x0 0x0 DEVADDR Device Address In I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0]. Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode. Note 2: When software set 10'h000, the address can not be used. 0 10 read-write UI2C_DEVADDR1 UI2C_DEVADDR1 USCI Device Address Register 1 0x48 -1 read-write n 0x0 0x0 UI2C_LINECTL UI2C_LINECTL USCI Line Control Register 0x2C -1 read-write n 0x0 0x0 DWIDTH Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits. 0x0: The data word contains 16 bits located at bit positions [15:0]. 0x1: Reserved. 0x2: Reserved. 0x3: Reserved. 0x4: The data word contains 4 bits located at bit positions [3:0]. 0x5: The data word contains 5 bits located at bit positions [4:0]. ... 0xF: The data word contains 15 bits located at bit positions [14:0]. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UI2C_PROTCTL UI2C_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 AA Assert Acknowledge Control 1 1 read-write ADDR10EN Address 10-bit Function Enable Bit 4 1 read-write 0 Address match 10 bit function Disabled #0 1 Address match 10 bit function Enabled #1 GCFUNC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 MONEN Monitor Mode Enable Bit This bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. 9 1 read-write 0 The monitor mode Disabled #0 1 The monitor mode Enabled #1 PROTEN I2C Protocol Enable Bit 31 1 read-write 0 I2C Protocol Disabled #0 1 I2C Protocol Enabled #1 PTRG I2C Protocol Trigger (Write Only) When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. 5 1 write-only 0 I2C's stretch disabled and the I2C protocol function will go ahead #0 1 I2C's stretch active #1 SCLOUTEN SCL Output Enable Bit This bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt. 8 1 read-write 0 SCL output will be forced high due to open drain mechanism #0 1 I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt #1 STA I2C START Control Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 3 1 read-write STO I2C STOP Control 2 1 read-write TOCNT Time-out Clock Cycle This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode. 16 10 read-write UI2C_PROTIEN UI2C_PROTIEN USCI Protocol Interrupt Enable Register 0x60 -1 read-write n 0x0 0x0 ACKIEN Acknowledge Interrupt Enable Bit This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. 6 1 read-write 0 The acknowledge interrupt Disabled #0 1 The acknowledge interrupt Enabled #1 ARBLOIEN Arbitration Lost Interrupt Enable Bit This bit enables the generation of a protocol interrupt if an arbitration lost event is detected. 4 1 read-write 0 The arbitration lost interrupt Disabled #0 1 The arbitration lost interrupt Enabled #1 ERRIEN Error Interrupt Enable Bit This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERRIF (UI2C_PROTSTS [12])). 5 1 read-write 0 The error interrupt Disabled #0 1 The error interrupt Enabled #1 NACKIEN Non - Acknowledge Interrupt Enable Bit This bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master. 3 1 read-write 0 The non - acknowledge interrupt Disabled #0 1 The non - acknowledge interrupt Enabled #1 STARIEN START Condition Received Interrupt Enable Bit This bit enables the generation of a protocol interrupt if a START condition is detected. 1 1 read-write 0 The start condition interrupt Disabled #0 1 The start condition interrupt Enabled #1 STORIEN STOP Condition Received Interrupt Enable Bit This bit enables the generation of a protocol interrupt if a STOP condition is detected. 2 1 read-write 0 The stop condition interrupt Disabled #0 1 The stop condition interrupt Enabled #1 TOIEN Time-out Interrupt Enable Bit In I2C protocol, this bit enables the interrupt generation in case of a time-out event. 0 1 read-write 0 The time-out interrupt Disabled #0 1 The time-out interrupt Enabled #1 UI2C_PROTSTS UI2C_PROTSTS USCI Protocol Status Register 0x64 -1 read-write n 0x0 0x0 ACKIF Acknowledge Received Interrupt Flag Note: It is cleared by software writing 1 into this bit 13 1 read-write 0 An acknowledge has not been received #0 1 An acknowledge has been received #1 ARBLOIF Arbitration Lost Interrupt Flag Note: It is cleared by software writing 1 into this bit 11 1 read-write 0 An arbitration has not been lost #0 1 An arbitration has been lost #1 BUSHANG Bus Hang-up This bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. 18 1 read-write 0 The bus is normal status for transmission #0 1 The bus is hang-up status for transmission #1 ERRARBLO Error Arbitration Lost This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. 19 1 read-write 0 The bus is normal status for transmission #0 1 The bus is error arbitration lost status for transmission #1 ERRIF Error Interrupt Flag Note 1: It is cleared by software writing 1 into this bit Note 2: This bit is set for slave mode, and user must write 1 into STO register to the defined 'not addressed' slave mode. 12 1 read-write 0 An I2C error has not been detected #0 1 An I2C error has been detected #1 NACKIF Non - Acknowledge Received Interrupt Flag Note: It is cleared by software writing 1 into this bit 10 1 read-write 0 A non - acknowledge has not been received #0 1 A non - acknowledge has been received #1 ONBUSY On Bus Busy Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 6 1 read-write 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 SLAREAD Slave Read Request Status This bit indicates that a slave read request has been detected. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. 15 1 read-write 0 A slave R/W bit is 1 has not been detected #0 1 A slave R/W bit is 1 has been detected #1 SLASEL Slave Select Status This bit indicates that this device has been selected as slave. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. 14 1 read-write 0 The device is not selected as slave #0 1 The device is selected as slave #1 STARIF Start Condition Received Interrupt Flag This bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode. Note: It is cleared by software writing 1 into this bit 8 1 read-write 0 A start condition has not yet been detected #0 1 A start condition has been detected #1 STORIF Stop Condition Received Interrupt Flag Note 1: It is cleared by software writing 1 into this bit 9 1 read-write 0 A stop condition has not yet been detected #0 1 A stop condition has been detected #1 TOIF Time-out Interrupt Flag Note: It is cleared by software writing 1 into this bit 5 1 read-write 0 A time-out interrupt status has not occurred #0 1 A time-out interrupt status has occurred #1 WKAKDONE Wake-up Address Frame Acknowledge Bit Done Note: This bit can't clear when WKF is not be clear. 16 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WRSTSWK Read/Write Status Bit in Address Wake-up Frame 17 1 read-write 0 Write command be record on the address match wake-up frame #0 1 Read command be record on the address match wake-up frame #1 UI2C_RXDAT UI2C_RXDAT USCI Receive Data Register 0x34 -1 read-only n 0x0 0x0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer. Note: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C. 0 16 read-only UI2C_TMCTL UI2C_TMCTL I2C Timing Configure Control Register 0x8C -1 read-write n 0x0 0x0 HTCTL Hold Time Configure Control This field is used to adjust SDA transfer timing. which master will transfer SDA after SCL fallinng edge. Note: Hold time adjust function can only work in master mode, when slave mode, this field should set as 0 16 9 read-write STCTL Setup Time Configure Control This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode. 0 9 read-write UI2C_TXDAT UI2C_TXDAT USCI Transmit Data Register 0x30 -1 write-only n 0x0 0x0 TXDAT Transmit Data Software can use this bit field to write 16-bit transmit data for transmission. 0 16 write-only UI2C_WKCTL UI2C_WKCTL USCI Wake-up Control Register 0x54 -1 read-write n 0x0 0x0 WKADDREN Wake-up Address Match Enable Bit 1 1 read-write 0 The chip is woken up according data toggle #0 1 The chip is woken up according address match #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UI2C_WKSTS UI2C_WKSTS USCI Wake-up Status Register 0x58 -1 read-write n 0x0 0x0 WKF Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write UI2C1 UI2CI2C Register Map UI2CI2C 0x0 0x0 0x4 registers n 0x2C 0xC registers n 0x44 0x24 registers n 0x8 0x4 registers n 0x88 0x8 registers n UI2C_ADDRMSK0 UI2C_ADDRMSK0 USCI Device Address Mask Register 0 0x4C -1 read-write n 0x0 0x0 ADDRMSK USCI Device Address Mask USCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 0 10 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 UI2C_ADDRMSK1 UI2C_ADDRMSK1 USCI Device Address Mask Register 1 0x50 -1 read-write n 0x0 0x0 UI2C_ADMAT UI2C_ADMAT I2C Slave Match Address Register 0x88 -1 read-write n 0x0 0x0 ADMAT0 USCI Address 0 Match Status Register When address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 0 1 read-write ADMAT1 USCI Address 1 Match Status Register When address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 1 1 read-write UI2C_BRGEN UI2C_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider 16 10 read-write DSCNT Denominator for Sample Counter This bit field defines the divide ratio of the sample clock fSAMP_CLK. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection This bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection This bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved. #1 SPCLKSEL Sample Clock Source Selection This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit This bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter Disabled #0 1 Time measurement counter Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 UI2C_CTL UI2C_CTL USCI Control Register 0x0 -1 read-write n 0x0 0x0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE. Note: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UI2C_DEVADDR0 UI2C_DEVADDR0 USCI Device Address Register 0 0x44 -1 read-write n 0x0 0x0 DEVADDR Device Address In I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0]. Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode. Note 2: When software set 10'h000, the address can not be used. 0 10 read-write UI2C_DEVADDR1 UI2C_DEVADDR1 USCI Device Address Register 1 0x48 -1 read-write n 0x0 0x0 UI2C_LINECTL UI2C_LINECTL USCI Line Control Register 0x2C -1 read-write n 0x0 0x0 DWIDTH Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits. 0x0: The data word contains 16 bits located at bit positions [15:0]. 0x1: Reserved. 0x2: Reserved. 0x3: Reserved. 0x4: The data word contains 4 bits located at bit positions [3:0]. 0x5: The data word contains 5 bits located at bit positions [4:0]. ... 0xF: The data word contains 15 bits located at bit positions [14:0]. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UI2C_PROTCTL UI2C_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 AA Assert Acknowledge Control 1 1 read-write ADDR10EN Address 10-bit Function Enable Bit 4 1 read-write 0 Address match 10 bit function Disabled #0 1 Address match 10 bit function Enabled #1 GCFUNC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 MONEN Monitor Mode Enable Bit This bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. 9 1 read-write 0 The monitor mode Disabled #0 1 The monitor mode Enabled #1 PROTEN I2C Protocol Enable Bit 31 1 read-write 0 I2C Protocol Disabled #0 1 I2C Protocol Enabled #1 PTRG I2C Protocol Trigger (Write Only) When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. 5 1 write-only 0 I2C's stretch disabled and the I2C protocol function will go ahead #0 1 I2C's stretch active #1 SCLOUTEN SCL Output Enable Bit This bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt. 8 1 read-write 0 SCL output will be forced high due to open drain mechanism #0 1 I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt #1 STA I2C START Control Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 3 1 read-write STO I2C STOP Control 2 1 read-write TOCNT Time-out Clock Cycle This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode. 16 10 read-write UI2C_PROTIEN UI2C_PROTIEN USCI Protocol Interrupt Enable Register 0x60 -1 read-write n 0x0 0x0 ACKIEN Acknowledge Interrupt Enable Bit This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. 6 1 read-write 0 The acknowledge interrupt Disabled #0 1 The acknowledge interrupt Enabled #1 ARBLOIEN Arbitration Lost Interrupt Enable Bit This bit enables the generation of a protocol interrupt if an arbitration lost event is detected. 4 1 read-write 0 The arbitration lost interrupt Disabled #0 1 The arbitration lost interrupt Enabled #1 ERRIEN Error Interrupt Enable Bit This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERRIF (UI2C_PROTSTS [12])). 5 1 read-write 0 The error interrupt Disabled #0 1 The error interrupt Enabled #1 NACKIEN Non - Acknowledge Interrupt Enable Bit This bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master. 3 1 read-write 0 The non - acknowledge interrupt Disabled #0 1 The non - acknowledge interrupt Enabled #1 STARIEN START Condition Received Interrupt Enable Bit This bit enables the generation of a protocol interrupt if a START condition is detected. 1 1 read-write 0 The start condition interrupt Disabled #0 1 The start condition interrupt Enabled #1 STORIEN STOP Condition Received Interrupt Enable Bit This bit enables the generation of a protocol interrupt if a STOP condition is detected. 2 1 read-write 0 The stop condition interrupt Disabled #0 1 The stop condition interrupt Enabled #1 TOIEN Time-out Interrupt Enable Bit In I2C protocol, this bit enables the interrupt generation in case of a time-out event. 0 1 read-write 0 The time-out interrupt Disabled #0 1 The time-out interrupt Enabled #1 UI2C_PROTSTS UI2C_PROTSTS USCI Protocol Status Register 0x64 -1 read-write n 0x0 0x0 ACKIF Acknowledge Received Interrupt Flag Note: It is cleared by software writing 1 into this bit 13 1 read-write 0 An acknowledge has not been received #0 1 An acknowledge has been received #1 ARBLOIF Arbitration Lost Interrupt Flag Note: It is cleared by software writing 1 into this bit 11 1 read-write 0 An arbitration has not been lost #0 1 An arbitration has been lost #1 BUSHANG Bus Hang-up This bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. 18 1 read-write 0 The bus is normal status for transmission #0 1 The bus is hang-up status for transmission #1 ERRARBLO Error Arbitration Lost This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. 19 1 read-write 0 The bus is normal status for transmission #0 1 The bus is error arbitration lost status for transmission #1 ERRIF Error Interrupt Flag Note 1: It is cleared by software writing 1 into this bit Note 2: This bit is set for slave mode, and user must write 1 into STO register to the defined 'not addressed' slave mode. 12 1 read-write 0 An I2C error has not been detected #0 1 An I2C error has been detected #1 NACKIF Non - Acknowledge Received Interrupt Flag Note: It is cleared by software writing 1 into this bit 10 1 read-write 0 A non - acknowledge has not been received #0 1 A non - acknowledge has been received #1 ONBUSY On Bus Busy Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 6 1 read-write 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 SLAREAD Slave Read Request Status This bit indicates that a slave read request has been detected. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. 15 1 read-write 0 A slave R/W bit is 1 has not been detected #0 1 A slave R/W bit is 1 has been detected #1 SLASEL Slave Select Status This bit indicates that this device has been selected as slave. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. 14 1 read-write 0 The device is not selected as slave #0 1 The device is selected as slave #1 STARIF Start Condition Received Interrupt Flag This bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode. Note: It is cleared by software writing 1 into this bit 8 1 read-write 0 A start condition has not yet been detected #0 1 A start condition has been detected #1 STORIF Stop Condition Received Interrupt Flag Note 1: It is cleared by software writing 1 into this bit 9 1 read-write 0 A stop condition has not yet been detected #0 1 A stop condition has been detected #1 TOIF Time-out Interrupt Flag Note: It is cleared by software writing 1 into this bit 5 1 read-write 0 A time-out interrupt status has not occurred #0 1 A time-out interrupt status has occurred #1 WKAKDONE Wake-up Address Frame Acknowledge Bit Done Note: This bit can't clear when WKF is not be clear. 16 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WRSTSWK Read/Write Status Bit in Address Wake-up Frame 17 1 read-write 0 Write command be record on the address match wake-up frame #0 1 Read command be record on the address match wake-up frame #1 UI2C_RXDAT UI2C_RXDAT USCI Receive Data Register 0x34 -1 read-only n 0x0 0x0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer. Note: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C. 0 16 read-only UI2C_TMCTL UI2C_TMCTL I2C Timing Configure Control Register 0x8C -1 read-write n 0x0 0x0 HTCTL Hold Time Configure Control This field is used to adjust SDA transfer timing. which master will transfer SDA after SCL fallinng edge. Note: Hold time adjust function can only work in master mode, when slave mode, this field should set as 0 16 9 read-write STCTL Setup Time Configure Control This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode. 0 9 read-write UI2C_TXDAT UI2C_TXDAT USCI Transmit Data Register 0x30 -1 write-only n 0x0 0x0 TXDAT Transmit Data Software can use this bit field to write 16-bit transmit data for transmission. 0 16 write-only UI2C_WKCTL UI2C_WKCTL USCI Wake-up Control Register 0x54 -1 read-write n 0x0 0x0 WKADDREN Wake-up Address Match Enable Bit 1 1 read-write 0 The chip is woken up according data toggle #0 1 The chip is woken up according address match #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UI2C_WKSTS UI2C_WKSTS USCI Wake-up Status Register 0x58 -1 read-write n 0x0 0x0 WKF Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write USPI0 USCISPI Register Map USCISPI 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x1C registers n 0x54 0x14 registers n USPI_BRGEN USPI_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider 16 10 read-write PTCLKSEL Protocol Clock Source Selection This bit selects the source of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection This bit selects the source of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved. #1 SPCLKSEL Sample Clock Source Selection This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fDIV_CLK #00 1 fPROT_CLK #01 2 fSCLK #10 3 fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit This bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter Disabled #0 1 Time measurement counter Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 USPI_BUFCTL USPI_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 -1 read-write n 0x0 0x0 RXCLR Clear Receive Buffer Note: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Interrupt Enable Bit 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset Note: It is cleared automatically after one PCLK cycle. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer Note: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 TXUDRIEN Slave Transmit Under Run Interrupt Enable Bit 6 1 read-write 0 Transmit under-run interrupt Disabled #0 1 Transmit under-run interrupt Enabled #1 USPI_BUFSTS USPI_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-only n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Over-run Interrupt Status This bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit. 3 1 read-only 0 A receive buffer overrun event has not been detected #0 1 A receive buffer overrun event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty and available for the next transmission datum #1 TXFULL Transmit Buffer Full Indicator 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 TXUDRIF Transmit Buffer Under-run Interrupt Status This bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit 11 1 read-only 0 A transmit buffer under-run event has not been detected #0 1 A transmit buffer under-run event has been detected #1 USPI_CLKIN USPI_CLKIN USCI Input Clock Signal Configuration Register 0x28 -1 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit. Note: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_CTL USPI_CTL USCI Control Register 0x0 -1 read-write n 0x0 0x0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE. Note: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 USPI_CTLIN0 USPI_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 -1 read-write n 0x0 0x0 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit. Note: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_DATIN0 USPI_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 -1 read-write n 0x0 0x0 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. Note: In SPI protocol, it is suggested this bit should be set as 0. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit. Note: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_INTEN USPI_INTEN USCI Interrupt Enable Register 0x4 -1 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit This bit enables the interrupt generation in case of a receive finish event. Note: The receive finish event happens when hardware receives the last bit of RX data into shift data unit. 4 1 read-write 0 The receive end interrupt Disabled #0 1 The receive end interrupt Enabled #1 RXSTIEN Receive Start Interrupt Enable Bit This bit enables the interrupt generation in case of a receive start event. Note: For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master. 3 1 read-write 0 The receive start interrupt Disabled #0 1 The receive start interrupt Enabled #1 TXENDIEN Transmit End Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit finish event. Note: The transmit finish event happens when hardware sends the last bit of TX data from shift data unit. 2 1 read-write 0 The transmit finish interrupt Disabled #0 1 The transmit finish interrupt Enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit start event. Note: The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit. 1 1 read-write 0 The transmit start interrupt Disabled #0 1 The transmit start interrupt Enabled #1 USPI_LINECTL USPI_LINECTL USCI Line Control Register 0x2C -1 read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection This bit defines the relation between the internal control signal and the output control signal. Note: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pins. 5 1 read-write 0 Data output values of USCIx_DAT0/1 pins are not inverted #0 1 Data output values of USCIx_DAT0/1 pins are inverted #1 DWIDTH Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits. 0x0: The data word contains 16 bits located at bit positions [15:0]. 0x1: Reserved. 0x2: Reserved. 0x3: Reserved. 0x4: The data word contains 4 bits located at bit positions [3:0]. 0x5: The data word contains 5 bits located at bit positions [4:0]. ... 0xF: The data word contains 15 bits located at bit positions [14:0]. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 USPI_PDMACTL USPI_PDMACTL USCI PDMA Control Register 0x40 -1 read-write n 0x0 0x0 PDMAEN PDMA Mode Enable Bit 3 1 read-write 0 PDMA function Disabled #0 1 PDMA function Enabled #1 PDMARST PDMA Reset 0 1 read-write 0 No effect #0 1 Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically #1 RXPDMAEN PDMA Receive Channel Available 2 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN PDMA Transmit Channel Available 1 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 USPI_PROTCTL USPI_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable Note: Master only 3 1 read-write 0 Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit #0 1 Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 PROTEN SPI Protocol Enable Bit 31 1 read-write 0 SPI Protocol Disabled #0 1 SPI Protocol Enabled #1 SCLKMODE Serial Bus Clock Mode This bit field defines the SCLK idle status, data transmit, and data receive edge. 6 2 read-write SLAVE Slave Mode Selection 0 1 read-write 0 Master mode #0 1 Slave mode #1 SLV3WIRE Slave 3-wire Mode Selection The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. Note: Slave only 1 1 read-write 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 SLVTOCNT Slave Mode Time-out Period In Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function. Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. Note: Slave only 16 10 read-write SS Slave Select Control If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select back to inactive state. Note: In SPI protocol, the internal slave select signal is active high. Note: Master only 2 1 read-write SUSPITV Suspend Interval This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation. (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle Example: Note: Master only 8 4 read-write TSMSEL Transmit Data Mode Selection This bit field describes how receive and transmit data is shifted in and out. Other values are reserved. Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. 12 3 read-write TXUDRPOL Transmit Under-run Data Polarity This bit defines the transmitting data value of USCIx_DAT1 when no data is available for transferring. Note: for Slave 28 1 read-write 0 The output data value is 0 if TX under run event occurs #0 1 The output data value is 1 if TX under run event occurs #1 USPI_PROTIEN USPI_PROTIEN USCI Protocol Interrupt Enable Register 0x60 -1 read-write n 0x0 0x0 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]). Bit count error event occurs. 3 1 read-write 0 The Slave mode bit count error interrupt Disabled #0 1 The Slave mode bit count error interrupt Enabled #1 SLVTOIEN Slave Time-out Interrupt Enable Bit In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. 2 1 read-write 0 The Slave time-out interrupt Disabled #0 1 The Slave time-out interrupt Enabled #1 SSACTIEN Slave Select Active Interrupt Enable Bit This bit enables/disables the generation of a slave select interrupt if the slave select changes to active. 1 1 read-write 0 Slave select active interrupt generation Disabled #0 1 Slave select active interrupt generation Enabled #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. 0 1 read-write 0 Slave select inactive interrupt generation Disabled #0 1 Slave select inactive interrupt generation Enabled #1 USPI_PROTSTS USPI_PROTSTS USCI Protocol Status Register 0x64 -1 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 17 1 read-only 0 SPI is in idle state #0 1 SPI is in busy state #1 RXENDIF Receive End Interrupt Flag Note: It is cleared by software write 1 to this bit. The receive end event happens when hardware receives the last bit of RX data into shift data unit. 4 1 read-write 0 Receive end event did not occur #0 1 Receive end event occurred #1 RXSTIF Receive Start Interrupt Flag Note: It is cleared by software write 1 to this bit. For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master. 3 1 read-write 0 Receive start event did not occur #0 1 Receive start event occurred #1 SLVBEIF Slave Bit Count Error Interrupt Flag Note: It is cleared by software write 1 to this bit. If the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]), bit count error event occurs. Note: for Slave only 6 1 read-write 0 Slave bit count error event did not occur #0 1 Slave bit count error event occurred #1 SLVTOIF Slave Time-out Interrupt Flag Note: It is cleared by software write 1 to this bit Note: for Slave only 5 1 read-write 0 Slave time-out event did not occur #0 1 Slave time-out event occurred #1 SLVUDR Slave Mode Transmit Under-run Status (Read Only) In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. 18 1 read-only 0 Slave transmit under run event does not occur #0 1 Slave transmit under run event occurs #1 SSACTIF Slave Select Active Interrupt Flag This bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit Note: The internal slave select signal is active high. Note: Slave only 9 1 read-write 0 The slave select signal has not changed to active #0 1 The slave select signal has changed to active #1 SSINAIF Slave Select Inactive Interrupt Flag This bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit Note: The internal slave select signal is active high. Note: for Slave only 8 1 read-write 0 The slave select signal has not changed to inactive #0 1 The slave select signal has changed to inactive #1 SSLINE Slave Select Line Bus Status (Read Only) This bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus. 16 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXENDIF Transmit End Interrupt Flag Note: It is cleared by software write 1 to this bit. The transmit end event happens when hardware sends the last bit of TX data from shift data unit. 2 1 read-write 0 Transmit end event did not occur #0 1 Transmit end event occurred #1 TXSTIF Transmit Start Interrupt Flag Note: It is cleared by software write 1 to this bit. The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit. 1 1 read-write 0 Transmit start event did not occur #0 1 Transmit start event occurred #1 USPI_RXDAT USPI_RXDAT USCI Receive Data Register 0x34 -1 read-only n 0x0 0x0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer. 0 16 read-only USPI_TXDAT USPI_TXDAT USCI Transmit Data Register 0x30 -1 write-only n 0x0 0x0 PORTDIR Port Direction Control 16 1 write-only 0 The data pin is configured as output mode #0 1 The data pin is configured as input mode #1 TXDAT Transmit Data Software can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. 0 16 write-only USPI_WKCTL USPI_WKCTL USCI Wake-up Control Register 0x54 -1 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 USPI_WKSTS USPI_WKSTS USCI Wake-up Status Register 0x58 -1 read-write n 0x0 0x0 WKF Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write USPI1 USCISPI Register Map USCISPI 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x1C registers n 0x54 0x14 registers n USPI_BRGEN USPI_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider 16 10 read-write PTCLKSEL Protocol Clock Source Selection This bit selects the source of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection This bit selects the source of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved. #1 SPCLKSEL Sample Clock Source Selection This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fDIV_CLK #00 1 fPROT_CLK #01 2 fSCLK #10 3 fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit This bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter Disabled #0 1 Time measurement counter Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 USPI_BUFCTL USPI_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 -1 read-write n 0x0 0x0 RXCLR Clear Receive Buffer Note: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Interrupt Enable Bit 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset Note: It is cleared automatically after one PCLK cycle. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer Note: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 TXUDRIEN Slave Transmit Under Run Interrupt Enable Bit 6 1 read-write 0 Transmit under-run interrupt Disabled #0 1 Transmit under-run interrupt Enabled #1 USPI_BUFSTS USPI_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-only n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Over-run Interrupt Status This bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit. 3 1 read-only 0 A receive buffer overrun event has not been detected #0 1 A receive buffer overrun event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty and available for the next transmission datum #1 TXFULL Transmit Buffer Full Indicator 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 TXUDRIF Transmit Buffer Under-run Interrupt Status This bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit 11 1 read-only 0 A transmit buffer under-run event has not been detected #0 1 A transmit buffer under-run event has been detected #1 USPI_CLKIN USPI_CLKIN USCI Input Clock Signal Configuration Register 0x28 -1 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit. Note: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_CTL USPI_CTL USCI Control Register 0x0 -1 read-write n 0x0 0x0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE. Note: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 USPI_CTLIN0 USPI_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 -1 read-write n 0x0 0x0 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit. Note: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_DATIN0 USPI_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 -1 read-write n 0x0 0x0 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. Note: In SPI protocol, it is suggested this bit should be set as 0. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit. Note: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_INTEN USPI_INTEN USCI Interrupt Enable Register 0x4 -1 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit This bit enables the interrupt generation in case of a receive finish event. Note: The receive finish event happens when hardware receives the last bit of RX data into shift data unit. 4 1 read-write 0 The receive end interrupt Disabled #0 1 The receive end interrupt Enabled #1 RXSTIEN Receive Start Interrupt Enable Bit This bit enables the interrupt generation in case of a receive start event. Note: For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master. 3 1 read-write 0 The receive start interrupt Disabled #0 1 The receive start interrupt Enabled #1 TXENDIEN Transmit End Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit finish event. Note: The transmit finish event happens when hardware sends the last bit of TX data from shift data unit. 2 1 read-write 0 The transmit finish interrupt Disabled #0 1 The transmit finish interrupt Enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit start event. Note: The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit. 1 1 read-write 0 The transmit start interrupt Disabled #0 1 The transmit start interrupt Enabled #1 USPI_LINECTL USPI_LINECTL USCI Line Control Register 0x2C -1 read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection This bit defines the relation between the internal control signal and the output control signal. Note: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pins. 5 1 read-write 0 Data output values of USCIx_DAT0/1 pins are not inverted #0 1 Data output values of USCIx_DAT0/1 pins are inverted #1 DWIDTH Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits. 0x0: The data word contains 16 bits located at bit positions [15:0]. 0x1: Reserved. 0x2: Reserved. 0x3: Reserved. 0x4: The data word contains 4 bits located at bit positions [3:0]. 0x5: The data word contains 5 bits located at bit positions [4:0]. ... 0xF: The data word contains 15 bits located at bit positions [14:0]. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 USPI_PDMACTL USPI_PDMACTL USCI PDMA Control Register 0x40 -1 read-write n 0x0 0x0 PDMAEN PDMA Mode Enable Bit 3 1 read-write 0 PDMA function Disabled #0 1 PDMA function Enabled #1 PDMARST PDMA Reset 0 1 read-write 0 No effect #0 1 Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically #1 RXPDMAEN PDMA Receive Channel Available 2 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN PDMA Transmit Channel Available 1 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 USPI_PROTCTL USPI_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable Note: Master only 3 1 read-write 0 Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit #0 1 Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 PROTEN SPI Protocol Enable Bit 31 1 read-write 0 SPI Protocol Disabled #0 1 SPI Protocol Enabled #1 SCLKMODE Serial Bus Clock Mode This bit field defines the SCLK idle status, data transmit, and data receive edge. 6 2 read-write SLAVE Slave Mode Selection 0 1 read-write 0 Master mode #0 1 Slave mode #1 SLV3WIRE Slave 3-wire Mode Selection The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. Note: Slave only 1 1 read-write 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 SLVTOCNT Slave Mode Time-out Period In Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function. Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. Note: Slave only 16 10 read-write SS Slave Select Control If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select back to inactive state. Note: In SPI protocol, the internal slave select signal is active high. Note: Master only 2 1 read-write SUSPITV Suspend Interval This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation. (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle Example: Note: Master only 8 4 read-write TSMSEL Transmit Data Mode Selection This bit field describes how receive and transmit data is shifted in and out. Other values are reserved. Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. 12 3 read-write TXUDRPOL Transmit Under-run Data Polarity This bit defines the transmitting data value of USCIx_DAT1 when no data is available for transferring. Note: for Slave 28 1 read-write 0 The output data value is 0 if TX under run event occurs #0 1 The output data value is 1 if TX under run event occurs #1 USPI_PROTIEN USPI_PROTIEN USCI Protocol Interrupt Enable Register 0x60 -1 read-write n 0x0 0x0 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]). Bit count error event occurs. 3 1 read-write 0 The Slave mode bit count error interrupt Disabled #0 1 The Slave mode bit count error interrupt Enabled #1 SLVTOIEN Slave Time-out Interrupt Enable Bit In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. 2 1 read-write 0 The Slave time-out interrupt Disabled #0 1 The Slave time-out interrupt Enabled #1 SSACTIEN Slave Select Active Interrupt Enable Bit This bit enables/disables the generation of a slave select interrupt if the slave select changes to active. 1 1 read-write 0 Slave select active interrupt generation Disabled #0 1 Slave select active interrupt generation Enabled #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. 0 1 read-write 0 Slave select inactive interrupt generation Disabled #0 1 Slave select inactive interrupt generation Enabled #1 USPI_PROTSTS USPI_PROTSTS USCI Protocol Status Register 0x64 -1 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 17 1 read-only 0 SPI is in idle state #0 1 SPI is in busy state #1 RXENDIF Receive End Interrupt Flag Note: It is cleared by software write 1 to this bit. The receive end event happens when hardware receives the last bit of RX data into shift data unit. 4 1 read-write 0 Receive end event did not occur #0 1 Receive end event occurred #1 RXSTIF Receive Start Interrupt Flag Note: It is cleared by software write 1 to this bit. For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master. 3 1 read-write 0 Receive start event did not occur #0 1 Receive start event occurred #1 SLVBEIF Slave Bit Count Error Interrupt Flag Note: It is cleared by software write 1 to this bit. If the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]), bit count error event occurs. Note: for Slave only 6 1 read-write 0 Slave bit count error event did not occur #0 1 Slave bit count error event occurred #1 SLVTOIF Slave Time-out Interrupt Flag Note: It is cleared by software write 1 to this bit Note: for Slave only 5 1 read-write 0 Slave time-out event did not occur #0 1 Slave time-out event occurred #1 SLVUDR Slave Mode Transmit Under-run Status (Read Only) In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. 18 1 read-only 0 Slave transmit under run event does not occur #0 1 Slave transmit under run event occurs #1 SSACTIF Slave Select Active Interrupt Flag This bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit Note: The internal slave select signal is active high. Note: Slave only 9 1 read-write 0 The slave select signal has not changed to active #0 1 The slave select signal has changed to active #1 SSINAIF Slave Select Inactive Interrupt Flag This bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit Note: The internal slave select signal is active high. Note: for Slave only 8 1 read-write 0 The slave select signal has not changed to inactive #0 1 The slave select signal has changed to inactive #1 SSLINE Slave Select Line Bus Status (Read Only) This bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus. 16 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXENDIF Transmit End Interrupt Flag Note: It is cleared by software write 1 to this bit. The transmit end event happens when hardware sends the last bit of TX data from shift data unit. 2 1 read-write 0 Transmit end event did not occur #0 1 Transmit end event occurred #1 TXSTIF Transmit Start Interrupt Flag Note: It is cleared by software write 1 to this bit. The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit. 1 1 read-write 0 Transmit start event did not occur #0 1 Transmit start event occurred #1 USPI_RXDAT USPI_RXDAT USCI Receive Data Register 0x34 -1 read-only n 0x0 0x0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer. 0 16 read-only USPI_TXDAT USPI_TXDAT USCI Transmit Data Register 0x30 -1 write-only n 0x0 0x0 PORTDIR Port Direction Control 16 1 write-only 0 The data pin is configured as output mode #0 1 The data pin is configured as input mode #1 TXDAT Transmit Data Software can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. 0 16 write-only USPI_WKCTL USPI_WKCTL USCI Wake-up Control Register 0x54 -1 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 USPI_WKSTS USPI_WKSTS USCI Wake-up Status Register 0x58 -1 read-write n 0x0 0x0 WKF Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write UUART0 USCIUART Register Map USCIUART 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x1C registers n 0x54 0x14 registers n UUART_BRGEN UUART_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write DSCNT Denominator for Sample Counter This bit field defines the divide ratio of the sample clock fSAMP_CLK. Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection This bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection This bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved. #1 SPCLKSEL Sample Clock Source Selection This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Timing Measurement Counter Enable Bit This bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Timing measurement counter is Disabled #0 1 Timing measurement counter is Enabled #1 TMCNTSRC Timing Measurement Counter Clock Source Selection 5 1 read-write 0 Timing measurement counter with fPROT_CLK #0 1 Timing measurement counter with fDIV_CLK #1 UUART_BUFCTL UUART_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 -1 read-write n 0x0 0x0 RXCLR Clear Receive Buffer Note: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Error Interrupt Enable Bit 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset Note 1: It is cleared automatically after one PCLK cycle. Note 2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer Note: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset Note: It is cleared automatically after one PCLK cycle. 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 UUART_BUFSTS UUART_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-only n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Over-run Error Interrupt Status This bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit. 3 1 read-only 0 A receive buffer overrun error event has not been detected #0 1 A receive buffer overrun error event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 TXFULL Transmit Buffer Full Indicator 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 UUART_CLKIN UUART_CLKIN USCI Input Clock Signal Configuration Register 0x28 -1 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_CTL UUART_CTL USCI Control Register 0x0 -1 read-write n 0x0 0x0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE. Note: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UUART_CTLIN0 UUART_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 -1 read-write n 0x0 0x0 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_DATIN0 UUART_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 -1 read-write n 0x0 0x0 EDGEDET Input Signal Edge Detection Mode This bit field selects which edge actives the trigger event of input data signal. Note: In UART function mode, it is suggested to set this bit field as 10. 3 2 read-write 0 The trigger event activation is disabled #00 1 A rising edge activates the trigger event of input data signal #01 2 A falling edge activates the trigger event of input data signal #10 3 Both edges activate the trigger event of input data signal #11 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_INTEN UUART_INTEN USCI Interrupt Enable Register 0x4 -1 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit This bit enables the interrupt generation in case of a receive finish event. 4 1 read-write 0 The receive end interrupt Disabled #0 1 The receive end interrupt Enabled #1 RXSTIEN Receive Start Interrupt Enable BIt This bit enables the interrupt generation in case of a receive start event. 3 1 read-write 0 The receive start interrupt Disabled #0 1 The receive start interrupt Enabled #1 TXENDIEN Transmit End Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit finish event. 2 1 read-write 0 The transmit finish interrupt Disabled #0 1 The transmit finish interrupt Enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit start event. 1 1 read-write 0 The transmit start interrupt Disabled #0 1 The transmit start interrupt Enabled #1 UUART_LINECTL UUART_LINECTL USCI Line Control Register 0x2C -1 read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection This bit defines the relation between the internal control signal and the output control signal. Note: In UART protocol, the control signal means nRTS signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. 5 1 read-write 0 The value of USCIx_DAT1 is equal to the data shift register #0 1 The value of USCIx_DAT1 is the inversion of data shift register #1 DWIDTH Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits. 0x0: The data word contains 16 bits located at bit positions[15:0]. 0x1: Reserved. 0x2: Reserved. 0x3: Reserved. 0x4: The data word contains 4 bits located at bit positions[3:0]. 0x5: The data word contains 5 bits located at bit positions[4:0]. ... 0xF: The data word contains 15 bits located at bit positions[14:0]. Note: In UART protocol, the length can be configured as 6~13 bits. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UUART_PDMACTL UUART_PDMACTL USCI PDMA Control Register 0x40 -1 read-write n 0x0 0x0 PDMAEN PDMA Mode Enable Bit 3 1 read-write 0 PDMA function Disabled #0 1 PDMA function Enabled #1 PDMARST PDMA Reset 0 1 read-write 0 No effect #0 1 Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically #1 RXPDMAEN PDMA Receive Channel Available 2 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN PDMA Transmit Channel Available 1 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 UUART_PROTCTL UUART_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 ABREN Auto-baud Rate Detect Enable Bit Note: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN[1]) is enabled). 6 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 BCEN Transmit Break Control Enable Bit Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 29 1 read-write 0 Transmit Break Control Disabled #0 1 Transmit Break Control Enabled #1 BRDETITV Baud Rate Detection Interval This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN[5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTSTS[9]) is set. Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV. 16 9 read-write CTSAUTOEN nCTS Auto-flow Control Enable Bit When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). 4 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 CTSWKEN nCTS Wake-up Mode Enable Bit 10 1 read-write 0 nCTS wake-up mode Disabled #0 1 nCTS wake-up mode Enabled #1 DATWKEN Data Wake-up Mode Enable Bit 9 1 read-write 0 Data wake-up mode Disabled #0 1 Data wake-up mode Enabled #1 DGE Deglitch Enable Bit Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic. 30 1 read-write 0 Deglitch Disabled #0 1 Deglitch Enabled #1 EVENPARITY Even Parity Enable Bit Note: This bit has effect only when PARITYEN is set. 2 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 PARITYEN Parity Enable Bit This bit defines the parity bit is enabled in an UART frame. 1 1 read-write 0 The parity bit Disabled #0 1 The parity bit Enabled #1 PROTEN UART Protocol Enable Bit 31 1 read-write 0 UART Protocol Disabled #0 1 UART Protocol Enabled #1 RTSAUDIREN nRTS Auto Direction Enable Bit When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically. Note 1: This bit is used for nRTS auto direction control for RS485. Note 2: This bit has effect only when the RTSAUTOEN is not set. 5 1 read-write 0 nRTS auto direction control Disabled #0 1 nRTS auto direction control Enabled #1 RTSAUTOEN nRTS Auto-flow Control Enable Bit Note: This bit has effect only when the RTSAUDIREN is not set. 3 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 STICKEN Stick Parity Enable Bit Note: Refer to RS-485 Support section for detailed information. 26 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 STOPB Stop Bits This bit defines the number of stop bits in an UART frame. 0 1 read-write 0 The number of stop bits is 1 #0 1 The number of stop bits is 2 #1 WAKECNT Wake-up Counter These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. 11 4 read-write UUART_PROTIEN UUART_PROTIEN USCI Protocol Interrupt Enable Register 0x60 -1 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 1 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. 2 1 read-write 0 Receive line status interrupt Disabled #0 1 Receive line status interrupt Enabled #1 UUART_PROTSTS UUART_PROTSTS USCI Protocol Status Register 0x64 -1 read-write n 0x0 0x0 ABERRSTS Auto-baud Rate Error Status This bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again. Note 1: This bit is set at the same time of ABRDETIF. Note 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS. 11 1 read-write 0 Auto-baud rate detect counter is not overrun #0 1 Auto-baud rate detect counter is overrun #1 ABRDETIF Auto-baud Rate Interrupt Flag This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. Note: This bit can be cleared by writing '1' to it. 9 1 read-write 0 Auto-baud rate detect function is not done #0 1 One Bit auto-baud rate detect function is done #1 BREAK Break Flag This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits). Note: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits. 7 1 read-write 0 No Break is generated #0 1 Break is generated in the receiver bus #1 CTSLV nCTS Pin Status (Read Only) This bit used to monitor the current status of nCTS pin input. 17 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 CTSSYNCLV nCTS Synchronized Level Status (Read Only) This bit used to indicate the current status of the internal synchronized nCTS signal. 16 1 read-only 0 The internal synchronized nCTS is low #0 1 The internal synchronized nCTS is high #1 FRMERR Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits. 6 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PARITYERR Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. Note: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits. 5 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXBUSY RX Bus Status Flag (Read Only) This bit indicates the busy status of the receiver. 10 1 read-only 0 The receiver is Idle #0 1 The receiver is BUSY #1 RXENDIF Receive End Interrupt Flag Note: It is cleared by software writing 1 into this bit. 4 1 read-write 0 A receive finish interrupt status has not occurred #0 1 A receive finish interrupt status has occurred #1 RXSTIF Receive Start Interrupt Flag Note: It is cleared by software writing 1 into this bit. 3 1 read-write 0 A receive start interrupt status has not occurred #0 1 A receive start interrupt status has occurred #1 TXENDIF Transmit End Interrupt Flag Note: It is cleared by software writing 1 into this bit. 2 1 read-write 0 A transmit end interrupt status has not occurred #0 1 A transmit end interrupt status has occurred #1 TXSTIF Transmit Start Interrupt Flag Note 1: It is cleared by software writing one into this bit. Note 2: Used for user to load next transmit data when there is no data in transmit buffer. 1 1 read-write 0 A transmit start interrupt status has not occurred #0 1 A transmit start interrupt status has occurred #1 UUART_RXDAT UUART_RXDAT USCI Receive Data Register 0x34 -1 read-only n 0x0 0x0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer. Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]). 0 16 read-only UUART_TXDAT UUART_TXDAT USCI Transmit Data Register 0x30 -1 write-only n 0x0 0x0 TXDAT Transmit Data Software can use this bit field to write 16-bit transmit data for transmission. 0 16 write-only UUART_WKCTL UUART_WKCTL USCI Wake-up Control Register 0x54 -1 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UUART_WKSTS UUART_WKSTS USCI Wake-up Status Register 0x58 -1 read-write n 0x0 0x0 WKF Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write UUART1 USCIUART Register Map USCIUART 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x1C registers n 0x54 0x14 registers n UUART_BRGEN UUART_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write DSCNT Denominator for Sample Counter This bit field defines the divide ratio of the sample clock fSAMP_CLK. Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection This bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection This bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved. #1 SPCLKSEL Sample Clock Source Selection This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Timing Measurement Counter Enable Bit This bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Timing measurement counter is Disabled #0 1 Timing measurement counter is Enabled #1 TMCNTSRC Timing Measurement Counter Clock Source Selection 5 1 read-write 0 Timing measurement counter with fPROT_CLK #0 1 Timing measurement counter with fDIV_CLK #1 UUART_BUFCTL UUART_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 -1 read-write n 0x0 0x0 RXCLR Clear Receive Buffer Note: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Error Interrupt Enable Bit 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset Note 1: It is cleared automatically after one PCLK cycle. Note 2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer Note: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset Note: It is cleared automatically after one PCLK cycle. 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 UUART_BUFSTS UUART_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-only n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Over-run Error Interrupt Status This bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit. 3 1 read-only 0 A receive buffer overrun error event has not been detected #0 1 A receive buffer overrun error event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 TXFULL Transmit Buffer Full Indicator 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 UUART_CLKIN UUART_CLKIN USCI Input Clock Signal Configuration Register 0x28 -1 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_CTL UUART_CTL USCI Control Register 0x0 -1 read-write n 0x0 0x0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE. Note: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UUART_CTLIN0 UUART_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 -1 read-write n 0x0 0x0 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_DATIN0 UUART_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 -1 read-write n 0x0 0x0 EDGEDET Input Signal Edge Detection Mode This bit field selects which edge actives the trigger event of input data signal. Note: In UART function mode, it is suggested to set this bit field as 10. 3 2 read-write 0 The trigger event activation is disabled #00 1 A rising edge activates the trigger event of input data signal #01 2 A falling edge activates the trigger event of input data signal #10 3 Both edges activate the trigger event of input data signal #11 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_INTEN UUART_INTEN USCI Interrupt Enable Register 0x4 -1 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit This bit enables the interrupt generation in case of a receive finish event. 4 1 read-write 0 The receive end interrupt Disabled #0 1 The receive end interrupt Enabled #1 RXSTIEN Receive Start Interrupt Enable BIt This bit enables the interrupt generation in case of a receive start event. 3 1 read-write 0 The receive start interrupt Disabled #0 1 The receive start interrupt Enabled #1 TXENDIEN Transmit End Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit finish event. 2 1 read-write 0 The transmit finish interrupt Disabled #0 1 The transmit finish interrupt Enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit start event. 1 1 read-write 0 The transmit start interrupt Disabled #0 1 The transmit start interrupt Enabled #1 UUART_LINECTL UUART_LINECTL USCI Line Control Register 0x2C -1 read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection This bit defines the relation between the internal control signal and the output control signal. Note: In UART protocol, the control signal means nRTS signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. 5 1 read-write 0 The value of USCIx_DAT1 is equal to the data shift register #0 1 The value of USCIx_DAT1 is the inversion of data shift register #1 DWIDTH Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits. 0x0: The data word contains 16 bits located at bit positions[15:0]. 0x1: Reserved. 0x2: Reserved. 0x3: Reserved. 0x4: The data word contains 4 bits located at bit positions[3:0]. 0x5: The data word contains 5 bits located at bit positions[4:0]. ... 0xF: The data word contains 15 bits located at bit positions[14:0]. Note: In UART protocol, the length can be configured as 6~13 bits. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UUART_PDMACTL UUART_PDMACTL USCI PDMA Control Register 0x40 -1 read-write n 0x0 0x0 PDMAEN PDMA Mode Enable Bit 3 1 read-write 0 PDMA function Disabled #0 1 PDMA function Enabled #1 PDMARST PDMA Reset 0 1 read-write 0 No effect #0 1 Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically #1 RXPDMAEN PDMA Receive Channel Available 2 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN PDMA Transmit Channel Available 1 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 UUART_PROTCTL UUART_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 ABREN Auto-baud Rate Detect Enable Bit Note: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN[1]) is enabled). 6 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 BCEN Transmit Break Control Enable Bit Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 29 1 read-write 0 Transmit Break Control Disabled #0 1 Transmit Break Control Enabled #1 BRDETITV Baud Rate Detection Interval This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN[5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTSTS[9]) is set. Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV. 16 9 read-write CTSAUTOEN nCTS Auto-flow Control Enable Bit When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). 4 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 CTSWKEN nCTS Wake-up Mode Enable Bit 10 1 read-write 0 nCTS wake-up mode Disabled #0 1 nCTS wake-up mode Enabled #1 DATWKEN Data Wake-up Mode Enable Bit 9 1 read-write 0 Data wake-up mode Disabled #0 1 Data wake-up mode Enabled #1 DGE Deglitch Enable Bit Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic. 30 1 read-write 0 Deglitch Disabled #0 1 Deglitch Enabled #1 EVENPARITY Even Parity Enable Bit Note: This bit has effect only when PARITYEN is set. 2 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 PARITYEN Parity Enable Bit This bit defines the parity bit is enabled in an UART frame. 1 1 read-write 0 The parity bit Disabled #0 1 The parity bit Enabled #1 PROTEN UART Protocol Enable Bit 31 1 read-write 0 UART Protocol Disabled #0 1 UART Protocol Enabled #1 RTSAUDIREN nRTS Auto Direction Enable Bit When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically. Note 1: This bit is used for nRTS auto direction control for RS485. Note 2: This bit has effect only when the RTSAUTOEN is not set. 5 1 read-write 0 nRTS auto direction control Disabled #0 1 nRTS auto direction control Enabled #1 RTSAUTOEN nRTS Auto-flow Control Enable Bit Note: This bit has effect only when the RTSAUDIREN is not set. 3 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 STICKEN Stick Parity Enable Bit Note: Refer to RS-485 Support section for detailed information. 26 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 STOPB Stop Bits This bit defines the number of stop bits in an UART frame. 0 1 read-write 0 The number of stop bits is 1 #0 1 The number of stop bits is 2 #1 WAKECNT Wake-up Counter These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. 11 4 read-write UUART_PROTIEN UUART_PROTIEN USCI Protocol Interrupt Enable Register 0x60 -1 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 1 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. 2 1 read-write 0 Receive line status interrupt Disabled #0 1 Receive line status interrupt Enabled #1 UUART_PROTSTS UUART_PROTSTS USCI Protocol Status Register 0x64 -1 read-write n 0x0 0x0 ABERRSTS Auto-baud Rate Error Status This bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again. Note 1: This bit is set at the same time of ABRDETIF. Note 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS. 11 1 read-write 0 Auto-baud rate detect counter is not overrun #0 1 Auto-baud rate detect counter is overrun #1 ABRDETIF Auto-baud Rate Interrupt Flag This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. Note: This bit can be cleared by writing '1' to it. 9 1 read-write 0 Auto-baud rate detect function is not done #0 1 One Bit auto-baud rate detect function is done #1 BREAK Break Flag This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits). Note: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits. 7 1 read-write 0 No Break is generated #0 1 Break is generated in the receiver bus #1 CTSLV nCTS Pin Status (Read Only) This bit used to monitor the current status of nCTS pin input. 17 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 CTSSYNCLV nCTS Synchronized Level Status (Read Only) This bit used to indicate the current status of the internal synchronized nCTS signal. 16 1 read-only 0 The internal synchronized nCTS is low #0 1 The internal synchronized nCTS is high #1 FRMERR Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits. 6 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PARITYERR Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. Note: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits. 5 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXBUSY RX Bus Status Flag (Read Only) This bit indicates the busy status of the receiver. 10 1 read-only 0 The receiver is Idle #0 1 The receiver is BUSY #1 RXENDIF Receive End Interrupt Flag Note: It is cleared by software writing 1 into this bit. 4 1 read-write 0 A receive finish interrupt status has not occurred #0 1 A receive finish interrupt status has occurred #1 RXSTIF Receive Start Interrupt Flag Note: It is cleared by software writing 1 into this bit. 3 1 read-write 0 A receive start interrupt status has not occurred #0 1 A receive start interrupt status has occurred #1 TXENDIF Transmit End Interrupt Flag Note: It is cleared by software writing 1 into this bit. 2 1 read-write 0 A transmit end interrupt status has not occurred #0 1 A transmit end interrupt status has occurred #1 TXSTIF Transmit Start Interrupt Flag Note 1: It is cleared by software writing one into this bit. Note 2: Used for user to load next transmit data when there is no data in transmit buffer. 1 1 read-write 0 A transmit start interrupt status has not occurred #0 1 A transmit start interrupt status has occurred #1 UUART_RXDAT UUART_RXDAT USCI Receive Data Register 0x34 -1 read-only n 0x0 0x0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer. Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]). 0 16 read-only UUART_TXDAT UUART_TXDAT USCI Transmit Data Register 0x30 -1 write-only n 0x0 0x0 TXDAT Transmit Data Software can use this bit field to write 16-bit transmit data for transmission. 0 16 write-only UUART_WKCTL UUART_WKCTL USCI Wake-up Control Register 0x54 -1 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UUART_WKSTS UUART_WKSTS USCI Wake-up Status Register 0x58 -1 read-write n 0x0 0x0 WKF Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write WDT WDT Register Map WDT 0x0 0x0 0xC registers n ALTCTL WDT_ALTCTL WDT Alternative Control Register 0x4 -1 read-write n 0x0 0x0 RSTDSEL WDT Reset Delay Selection (Write Protect) When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT (WDT_RSTCNT[31:0]) to prevent WDT time-out reset happened. User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period. Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: This register will be reset to 0 if WDT time-out reset happened. 0 2 read-write 0 WDT Reset Delay Period is 1026 * WDT_CLK #00 1 WDT Reset Delay Period is 130 * WDT_CLK #01 2 WDT Reset Delay Period is 18 * WDT_CLK #10 3 WDT Reset Delay Period is 3 * WDT_CLK #11 CTL WDT_CTL WDT Control Register 0x0 -1 read-write n 0x0 0x0 ICEDEBUG ICE Debug Mode Acknowledge Disable Bit (Write Protect) WDT up counter will keep going no matter CPU is held by ICE or not. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement affects WDT counting #0 1 ICE debug mode acknowledgement Disabled #1 IF WDT Time-out Interrupt Flag This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval Note: This bit is cleared by writing 1 to it. 3 1 read-write 0 WDT time-out interrupt did not occur #0 1 WDT time-out interrupt occurred #1 INTEN WDT Time-out Interrupt Enable Bit (Write Protect) If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 WDT time-out interrupt Disabled #0 1 WDT time-out interrupt Enabled #1 RSTEN WDT Time-out Reset Enable Bit (Write Protect) Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 WDT time-out reset function Disabled #0 1 WDT time-out reset function Enabled #1 RSTF WDT Time-out Reset Flag This bit indicates the system has been reset by WDT time-out reset or not. Note: This bit is cleared by writing 1 to it. 2 1 read-write 0 WDT time-out reset did not occur #0 1 WDT time-out reset occurred #1 SYNC WDT Enable Control SYNC Flag Indicator (Read Only) If user executes enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not. Note: Performing enable or disable WDTEN bit needs 2 * WDT_CLK period to become active. 30 1 read-only 0 Set WDTEN bit is completed #0 1 Set WDTEN bit is synchronizing and not become active yet #1 TOUTSEL WDT Time-out Interval Selection (Write Protect) These four bits select the time-out interval period for the WDT. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 8 4 read-write 0 24 * WDT_CLK #0000 1 26 * WDT_CLK #0001 2 28 * WDT_CLK #0010 3 210 * WDT_CLK #0011 4 212 * WDT_CLK #0100 5 214 * WDT_CLK #0101 6 216 * WDT_CLK #0110 7 218 * WDT_CLK #0111 8 220 * WDT_CLK #1000 WDTEN WDT Enable Bit (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111, this bit is forced as 1 and user cannot change this bit to 0. 7 1 read-write 0 WDT Disabled (This action will reset the internal up counter value) #0 1 WDT Enabled #1 WKEN WDT Time-out Wake-up Function Control (Write Protect) If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Chip can be woken up by WDT time-out interrupt signal generated only if WDT clock source is selected to 38.4 kHz internal low speed RC oscillator (LIRC) or LXT. 4 1 read-write 0 Wake-up trigger event Disabled if WDT time-out interrupt signal generated #0 1 Wake-up trigger event Enabled if WDT time-out interrupt signal generated #1 WKF WDT Time-out Wake-up Flag (Write Protect) This bit indicates the interrupt wake-up flag status of WDT Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: This bit is cleared by writing 1 to it. 5 1 read-write 0 WDT does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated #1 RSTCNT WDT_RSTCNT WDT Reset Counter Register 0x8 -1 write-only n 0x0 0x0 RSTCNT WDT Reset Counter Register Writing 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0. Note: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active. 0 32 write-only WWDT WWDT Register Map WWDT 0x0 0x0 0x10 registers n CNT WWDT_CNT WWDT Counter Value Register 0xC -1 read-only n 0x0 0x0 CNTDAT WWDT Counter Value CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. 0 6 read-only CTL WWDT_CTL WWDT Control Register 0x4 -1 read-write n 0x0 0x0 CMPDAT WWDT Window Compare Register Set this register to adjust the valid reload window. Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT register when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generatec immediately. 16 6 read-write ICEDEBUG ICE Debug Mode Acknowledge Disable Bit Note: WWDT down counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects WWDT counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN WWDT Interrupt Enable Bit If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU. 1 1 read-write 0 WWDT counter compare match interrupt Disabled #0 1 WWDT counter compare match interrupt Enabled #1 PSCSEL WWDT Counter Prescale Period Selection 8 4 read-write 0 Pre-scale is 1 Max time-out period is 1 * 64 * WWDT_CLK #0000 1 Pre-scale is 2 Max time-out period is 2 * 64 * WWDT_CLK #0001 2 Pre-scale is 4 Max time-out period is 4 * 64 * WWDT_CLK #0010 3 Pre-scale is 8 Max time-out period is 8 * 64 * WWDT_CLK #0011 4 Pre-scale is 16 Max time-out period is 16 * 64 * WWDT_CLK #0100 5 Pre-scale is 32 Max time-out period is 32 * 64 * WWDT_CLK #0101 6 Pre-scale is 64 Max time-out period is 64 * 64 * WWDT_CLK #0110 7 Pre-scale is 128 Max time-out period is 128 * 64 * WWDT_CLK #0111 8 Pre-scale is 192 Max time-out period is 192 * 64 * WWDT_CLK #1000 9 Pre-scale is 256 Max time-out period is 256 * 64 * WWDT_CLK #1001 10 Pre-scale is 384 Max time-out period is 384 * 64 * WWDT_CLK #1010 11 Pre-scale is 512 Max time-out period is 512 * 64 * WWDT_CLK #1011 12 Pre-scale is 768 Max time-out period is 768 * 64 * WWDT_CLK #1100 13 Pre-scale is 1024 Max time-out period is 1024 * 64 * WWDT_CLK #1101 14 Pre-scale is 1536 Max time-out period is 1536 * 64 * WWDT_CLK #1110 15 Pre-scale is 2048 Max time-out period is 2048 * 64 * WWDT_CLK #1111 WWDTEN WWDT Enable Bit 0 1 read-write 0 WWDT counter is stopped #0 1 WWDT counter starts counting #1 RLDCNT WWDT_RLDCNT WWDT Reload Counter Register 0x0 -1 write-only n 0x0 0x0 RLDCNT WWDT Reload Counter Register Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]). If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated immediately. 0 32 write-only STATUS WWDT_STATUS WWDT Status Register 0x8 -1 read-write n 0x0 0x0 WWDTIF WWDT Compare Match Interrupt Flag This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]). Note: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 WWDT counter value matches CMPDAT #1 WWDTRF WWDT Timer-out Reset Flag This bit indicates the system has been reset by WWDT time-out reset or not. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 WWDT time-out reset did not occur #0 1 WWDT time-out reset occurred #1