nuvoTon
M253
2024.04.29
M253 SVD file
8
32
BPWM
BPWM Register Map
BPWM
0x0
0x0
0x8
registers
n
0x10
0x8
registers
n
0x120
0x4
registers
n
0x20
0x8
registers
n
0x200
0x3C
registers
n
0x250
0x8
registers
n
0x30
0x4
registers
n
0x304
0x4
registers
n
0x31C
0x18
registers
n
0x50
0x18
registers
n
0x90
0x4
registers
n
0xB0
0x10
registers
n
0xD4
0x8
registers
n
0xE0
0x4
registers
n
0xE8
0x4
registers
n
0xF8
0x8
registers
n
CAPCTL
BPWM_CAPCTL
BPWM Capture Control Register
0x204
-1
read-write
n
0x0
0x0
CAPEN0
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN1
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN2
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN3
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN4
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN5
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPINV0
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
8
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
9
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV2
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
10
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
11
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV4
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
12
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV5
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
13
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
FCRLDEN0
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN1
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN2
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN3
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN4
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN5
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
RCRLDEN0
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN1
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN2
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN3
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN4
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN5
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
CAPIEN
BPWM_CAPIEN
BPWM Capture Interrupt Enable Register
0x250
-1
read-write
n
0x0
0x0
CAPFIENn
BPWM Capture Falling Latch Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
8
6
read-write
0
Capture falling edge latch interrupt Disabled
0
1
Capture falling edge latch interrupt Enabled
1
CAPRIENn
BPWM Capture Rising Latch Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
6
read-write
0
Capture rising edge latch interrupt Disabled
0
1
Capture rising edge latch interrupt Enabled
1
CAPIF
BPWM_CAPIF
BPWM Capture Interrupt Flag Register
0x254
-1
read-write
n
0x0
0x0
CAPFIF0
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
8
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF1
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
9
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF2
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
10
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF3
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
11
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF4
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
12
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF5
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
13
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPRIF0
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF1
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF2
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
2
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF3
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
3
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF4
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
4
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF5
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
5
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPINEN
BPWM_CAPINEN
BPWM Capture Input Enable Register
0x200
-1
read-write
n
0x0
0x0
CAPINEN0
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN1
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN2
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN3
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN4
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN5
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPSTS
BPWM_CAPSTS
BPWM Capture Status Register
0x208
-1
read-only
n
0x0
0x0
CFIFOV0
Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
8
1
read-only
CFIFOV1
Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
9
1
read-only
CFIFOV2
Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
10
1
read-only
CFIFOV3
Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
11
1
read-only
CFIFOV4
Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
12
1
read-only
CFIFOV5
Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
13
1
read-only
CRIFOV0
Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
0
1
read-only
CRIFOV1
Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
1
1
read-only
CRIFOV2
Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
2
1
read-only
CRIFOV3
Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
3
1
read-only
CRIFOV4
Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
4
1
read-only
CRIFOV5
Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
5
1
read-only
CLKPSC
BPWM_CLKPSC
BPWM Clock Prescale Register
0x14
-1
read-write
n
0x0
0x0
CLKPSC
BPWM Counter Clock Prescale
The clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1).
0
12
read-write
CLKSRC
BPWM_CLKSRC
BPWM Clock Source Register
0x10
-1
read-write
n
0x0
0x0
ECLKSRC0
BPWM_CH01 External Clock Source Select
0
3
read-write
0
BPWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
CMPBUF0
BPWM_CMPBUF0
BPWM CMPDAT 0 Buffer
0x31C
-1
read-only
n
0x0
0x0
CMPBUF
BPWM Comparator Buffer (Read Only)
Used as CMP active register.
0
16
read-only
CMPBUF1
BPWM_CMPBUF1
BPWM CMPDAT 1 Buffer
0x320
-1
read-write
n
0x0
0x0
CMPBUF2
BPWM_CMPBUF2
BPWM CMPDAT 2 Buffer
0x324
-1
read-write
n
0x0
0x0
CMPBUF3
BPWM_CMPBUF3
BPWM CMPDAT 3 Buffer
0x328
-1
read-write
n
0x0
0x0
CMPBUF4
BPWM_CMPBUF4
BPWM CMPDAT 4 Buffer
0x32C
-1
read-write
n
0x0
0x0
CMPBUF5
BPWM_CMPBUF5
BPWM CMPDAT 5 Buffer
0x330
-1
read-write
n
0x0
0x0
CMPDAT0
BPWM_CMPDAT0
BPWM Comparator Register 0
0x50
-1
read-write
n
0x0
0x0
CMPDAT
BPWM Comparator Register
CMPDAT use to compare with CNT to generate BPWM waveform, interrupt and trigger EADC.
In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.
0
16
read-write
CMPDAT1
BPWM_CMPDAT1
BPWM Comparator Register 1
0x54
-1
read-write
n
0x0
0x0
CMPDAT2
BPWM_CMPDAT2
BPWM Comparator Register 2
0x58
-1
read-write
n
0x0
0x0
CMPDAT3
BPWM_CMPDAT3
BPWM Comparator Register 3
0x5C
-1
read-write
n
0x0
0x0
CMPDAT4
BPWM_CMPDAT4
BPWM Comparator Register 4
0x60
-1
read-write
n
0x0
0x0
CMPDAT5
BPWM_CMPDAT5
BPWM Comparator Register 5
0x64
-1
read-write
n
0x0
0x0
CNT
BPWM_CNT
BPWM Counter Register
0x90
-1
read-only
n
0x0
0x0
CNT
BPWM Data Register (Read Only)
Monitor CNT to know the current value in 16-bit period counter.
0
16
read-only
DIRF
BPWM Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is down counting
#0
1
Counter is up counting
#1
CNTCLR
BPWM_CNTCLR
BPWM Clear Counter Register
0x24
-1
read-write
n
0x0
0x0
CNTCLR0
Clear BPWM Counter Control Bit 0
Note: It is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit BPWM counter to 0000H
#1
CNTEN
BPWM_CNTEN
BPWM Counter Enable Register
0x20
-1
read-write
n
0x0
0x0
CNTEN0
BPWM Counter 0 Enable Bit
0
1
read-write
0
BPWM Counter and clock prescaler stop running
#0
1
BPWM Counter and clock prescaler start running
#1
CTL0
BPWM_CTL0
BPWM Control Register 0
0x0
-1
read-write
n
0x0
0x0
CTRLD0
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
0
1
read-write
CTRLD1
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
1
1
read-write
CTRLD2
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
2
1
read-write
CTRLD3
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
3
1
read-write
CTRLD4
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
4
1
read-write
CTRLD5
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
5
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)
If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode.
Note: This bit is write protected. Refer to SYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt Disabled
#0
1
ICE debug mode counter halt Enabled
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable (Write Protect)
BPWM pin will keep output no matter ICE debug mode acknowledged or not.
Note: This bit is write protected. Refer to SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects BPWM output
#0
1
ICE debug mode acknowledgement Disabled
#1
IMMLDEN0
Immediately Load Enable Bits
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
16
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software updates PERIOD/CMPDAT
#1
IMMLDEN1
Immediately Load Enable Bits
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
17
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software updates PERIOD/CMPDAT
#1
IMMLDEN2
Immediately Load Enable Bits
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
18
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software updates PERIOD/CMPDAT
#1
IMMLDEN3
Immediately Load Enable Bits
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
19
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software updates PERIOD/CMPDAT
#1
IMMLDEN4
Immediately Load Enable Bits
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
20
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software updates PERIOD/CMPDAT
#1
IMMLDEN5
Immediately Load Enable Bits
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
21
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software updates PERIOD/CMPDAT
#1
CTL1
BPWM_CTL1
BPWM Control Register 1
0x4
-1
read-write
n
0x0
0x0
CNTTYPE0
BPWM Counter Behavior Type 0
Each bit n controls corresponding BPWM channel n.
0
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
EADCTS0
BPWM_EADCTS0
BPWM Trigger EADC Source Select Register 0
0xF8
-1
read-write
n
0x0
0x0
TRGEN0
BPWM_CH0 Trigger EADC Enable Bit
7
1
read-write
0
BPWM Channel 0 Trigger EADC function Disabled
#0
1
BPWM Channel 0 Trigger EADC function Enabled
#1
TRGEN1
BPWM_CH1 Trigger EADC Enable Bit
15
1
read-write
0
BPWM Channel 1 Trigger EADC function Disabled
#0
1
BPWM Channel 1 Trigger EADC function Enabled
#1
TRGEN2
BPWM_CH2 Trigger EADC Enable Bit
23
1
read-write
0
BPWM Channel 2 Trigger EADC function Disabled
#0
1
BPWM Channel 2 Trigger EADC function Enabled
#1
TRGEN3
BPWM_CH3 Trigger EADC Enable Bit
31
1
read-write
0
BPWM Channel 3 Trigger EADC function Disabled
#0
1
BPWM Channel 3 Trigger EADC function Enabled
#1
TRGSEL0
BPWM_CH0 Trigger EADC Source Select
Others reserved
0
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count CMPDAT point
#0011
4
BPWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH1 up-count CMPDAT point
#1000
9
BPWM_CH1 down-count CMPDAT point
#1001
TRGSEL1
BPWM_CH1 Trigger EADC Source Select
Others reserved
8
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count CMPDAT point
#0011
4
BPWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH1 up-count CMPDAT point
#1000
9
BPWM_CH1 down-count CMPDAT point
#1001
TRGSEL2
BPWM_CH2 Trigger EADC Source Select
Others reserved
16
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count CMPDAT point
#0011
4
BPWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH3 up-count CMPDAT point
#1000
9
BPWM_CH3 down-count CMPDAT point
#1001
TRGSEL3
BPWM_CH3 Trigger EADC Source Select
Others reserved.
24
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count CMPDAT point
#0011
4
BPWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH3 up-count CMPDAT point
#1000
9
BPWM_CH3 down-count CMPDAT point
#1001
EADCTS1
BPWM_EADCTS1
BPWM Trigger EADC Source Select Register 1
0xFC
-1
read-write
n
0x0
0x0
TRGEN4
BPWM_CH4 Trigger EADC Enable Bit
7
1
read-write
0
BPWM Channel 4 Trigger EADC function Disabled
#0
1
BPWM Channel 4 Trigger EADC function Enabled
#1
TRGEN5
BPWM_CH5 Trigger EADC Enable Bit
15
1
read-write
0
BPWM Channel 5 Trigger EADC function Disabled
#0
1
BPWM Channel 5 Trigger EADC function Enabled
#1
TRGSEL4
BPWM_CH4 Trigger EADC Source Select
Others reserved.
0
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count CMPDAT point
#0011
4
BPWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH5 up-count CMPDAT point
#1000
9
BPWM_CH5 down-count CMPDAT point
#1001
TRGSEL5
BPWM_CH5 Trigger EADC Source Select
Others reserved.
8
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count CMPDAT point
#0011
4
BPWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH5 up-count CMPDAT point
#1000
9
BPWM_CH5 down-count CMPDAT point
#1001
FCAPDAT0
BPWM_FCAPDAT0
BPWM Falling Capture Data Register 0
0x210
-1
read-only
n
0x0
0x0
FCAPDAT
BPWM Falling Capture Data (Read Only)
When falling capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
FCAPDAT1
BPWM_FCAPDAT1
BPWM Falling Capture Data Register 1
0x218
-1
read-write
n
0x0
0x0
FCAPDAT2
BPWM_FCAPDAT2
BPWM Falling Capture Data Register 2
0x220
-1
read-write
n
0x0
0x0
FCAPDAT3
BPWM_FCAPDAT3
BPWM Falling Capture Data Register 3
0x228
-1
read-write
n
0x0
0x0
FCAPDAT4
BPWM_FCAPDAT4
BPWM Falling Capture Data Register 4
0x230
-1
read-write
n
0x0
0x0
FCAPDAT5
BPWM_FCAPDAT5
BPWM Falling Capture Data Register 5
0x238
-1
read-write
n
0x0
0x0
INTEN
BPWM_INTEN
BPWM Interrupt Enable Register
0xE0
-1
read-write
n
0x0
0x0
CMPDIEN0
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN1
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN2
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN3
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN4
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN5
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN0
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN1
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN2
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN3
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN4
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN5
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN0
BPWM Period Point Interrupt 0 Enable Bit
Note: Up-down counter type period point means center point.
8
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN0
BPWM Zero Point Interrupt 0 Enable Bit
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
INTSTS
BPWM_INTSTS
BPWM Interrupt Flag Register
0xE8
-1
read-write
n
0x0
0x0
CMPDIF0
BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag does not work in down counter type selection.
24
1
read-write
CMPDIF1
BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag does not work in down counter type selection.
25
1
read-write
CMPDIF2
BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag does not work in down counter type selection.
26
1
read-write
CMPDIF3
BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag does not work in down counter type selection.
27
1
read-write
CMPDIF4
BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag does not work in down counter type selection.
28
1
read-write
CMPDIF5
BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag does not work in down counter type selection.
29
1
read-write
CMPUIF0
BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.
Note: If CMPDAT is equal to PERIOD, this flag does not work in up counter type selection.
16
1
read-write
CMPUIF1
BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.
Note: If CMPDAT is equal to PERIOD, this flag does not work in up counter type selection.
17
1
read-write
CMPUIF2
BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.
Note: If CMPDAT is equal to PERIOD, this flag does not work in up counter type selection.
18
1
read-write
CMPUIF3
BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.
Note: If CMPDAT is equal to PERIOD, this flag does not work in up counter type selection.
19
1
read-write
CMPUIF4
BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.
Note: If CMPDAT is equal to PERIOD, this flag does not work in up counter type selection.
20
1
read-write
CMPUIF5
BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.
Note: If CMPDAT is equal to PERIOD, this flag does not work in up counter type selection.
21
1
read-write
PIF0
BPWM Period Point Interrupt Flag 0
This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0 software can write 1 to clear this bit to 0.
8
1
read-write
ZIF0
BPWM Zero Point Interrupt Flag 0
This bit is set by hardware when BPWM_CH0 counter reaches 0 software can write 1 to clear this bit to 0.
0
1
read-write
MSK
BPWM_MSK
BPWM Mask Data Register
0xBC
-1
read-write
n
0x0
0x0
MSKDAT0
BPWM Mask Data Bit
This data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT1
BPWM Mask Data Bit
This data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT2
BPWM Mask Data Bit
This data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT3
BPWM Mask Data Bit
This data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT4
BPWM Mask Data Bit
This data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT5
BPWM Mask Data Bit
This data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKEN
BPWM_MSKEN
BPWM Mask Enable Register
0xB8
-1
read-write
n
0x0
0x0
MSKEN0
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
0
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN1
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
1
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN2
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
2
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN3
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
3
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN4
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
4
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN5
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
5
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
PBUF
BPWM_PBUF
BPWM PERIOD Buffer
0x304
-1
read-only
n
0x0
0x0
PBUF
BPWM Period Buffer (Read Only)
Used as PERIOD active register.
0
16
read-only
PERIOD
BPWM_PERIOD
BPWM Period Register
0x30
-1
read-write
n
0x0
0x0
PERIOD
BPWM Period Register
Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.
Down-Count mode:
In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
0
16
read-write
POEN
BPWM_POEN
BPWM Output Enable Register
0xD8
-1
read-write
n
0x0
0x0
POEN0
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN1
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN2
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN3
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN4
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN5
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POLCTL
BPWM_POLCTL
BPWM Pin Polar Inverse Register
0xD4
-1
read-write
n
0x0
0x0
PINV0
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
PINV1
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
PINV2
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
PINV3
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
PINV4
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
PINV5
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
RCAPDAT0
BPWM_RCAPDAT0
BPWM Rising Capture Data Register 0
0x20C
-1
read-only
n
0x0
0x0
RCAPDAT
BPWM Rising Capture Data (Read Only)
When rising capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
RCAPDAT1
BPWM_RCAPDAT1
BPWM Rising Capture Data Register 1
0x214
-1
read-write
n
0x0
0x0
RCAPDAT2
BPWM_RCAPDAT2
BPWM Rising Capture Data Register 2
0x21C
-1
read-write
n
0x0
0x0
RCAPDAT3
BPWM_RCAPDAT3
BPWM Rising Capture Data Register 3
0x224
-1
read-write
n
0x0
0x0
RCAPDAT4
BPWM_RCAPDAT4
BPWM Rising Capture Data Register 4
0x22C
-1
read-write
n
0x0
0x0
RCAPDAT5
BPWM_RCAPDAT5
BPWM Rising Capture Data Register 5
0x234
-1
read-write
n
0x0
0x0
STATUS
BPWM_STATUS
BPWM Status Register
0x120
-1
read-write
n
0x0
0x0
CNTMAX0
Time-base Counter 0 Equal to 0xFFFF Latched Status
Note: This bit can be cleared by software write 1.
0
1
read-write
0
The time-base counter never reached its maximum value 0xFFFF
#0
1
The time-base counter reached its maximum value
#1
EADCTRG0
EADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
Note: This bit can be cleared by software write 1.
16
1
read-write
0
No EADC start of conversion trigger event occurred
#0
1
An EADC start of conversion trigger event occurred
#1
EADCTRG1
EADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
Note: This bit can be cleared by software write 1.
17
1
read-write
0
No EADC start of conversion trigger event occurred
#0
1
An EADC start of conversion trigger event occurred
#1
EADCTRG2
EADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
Note: This bit can be cleared by software write 1.
18
1
read-write
0
No EADC start of conversion trigger event occurred
#0
1
An EADC start of conversion trigger event occurred
#1
EADCTRG3
EADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
Note: This bit can be cleared by software write 1.
19
1
read-write
0
No EADC start of conversion trigger event occurred
#0
1
An EADC start of conversion trigger event occurred
#1
EADCTRG4
EADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
Note: This bit can be cleared by software write 1.
20
1
read-write
0
No EADC start of conversion trigger event occurred
#0
1
An EADC start of conversion trigger event occurred
#1
EADCTRG5
EADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
Note: This bit can be cleared by software write 1.
21
1
read-write
0
No EADC start of conversion trigger event occurred
#0
1
An EADC start of conversion trigger event occurred
#1
WGCTL0
BPWM_WGCTL0
BPWM Generation Register 0
0xB0
-1
read-write
n
0x0
0x0
PRDPCTL0
BPWM Period or Center Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
16
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL1
BPWM Period or Center Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
18
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL2
BPWM Period or Center Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
20
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL3
BPWM Period or Center Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
22
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL4
BPWM Period or Center Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
24
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL5
BPWM Period or Center Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
26
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
ZPCTL0
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
0
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL1
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
2
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL2
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
4
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL3
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
6
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL4
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
8
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL5
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
10
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
WGCTL1
BPWM_WGCTL1
BPWM Generation Register 1
0xB4
-1
read-write
n
0x0
0x0
CMPDCTL0
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
16
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL1
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
18
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL2
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
20
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL3
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
22
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL4
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
24
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL5
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
26
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPUCTL0
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
0
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL1
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
2
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL2
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
4
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL3
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
6
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL4
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
8
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL5
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
10
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CANFDx
CANFD Register Map
CANFD
0x0
0x40
0xC
registers
n
0x50
0x10
registers
n
0x80
0xC
registers
n
0x90
0x58
registers
n
0xC
0x24
registers
n
0xF0
0xC
registers
n
CANFD_CCCR
CANFD_CCCR
CC Control Register (Pp*)
0x18
-1
read-write
n
0x0
0x0
ASM
Restricted Operation Mode
Bit ASM can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the software at any time. This bit will be set automatically set to 1 when the Tx handler was not able to read data from the message RAM in time. For a description of the Restricted Operation Mode refer to Restricted Operation Mode.
2
1
read-write
0
Normal CAN operation
#0
1
Restricted Operation Mode active
#1
BRSE
Bit Rate Switch Enable
9
1
read-write
0
Bit rate switching for transmissions Disabled
#0
1
Bit rate switching for transmissions Enabled
#1
CCE
Configuration Change Enable
1
1
read-write
0
The CPU has no write access to the protected configuration registers
#0
1
The CPU has write access to the protected configuration registers (while CANFD_INIT (CANFD_CCCR[0]) = 1)
#1
CSA
Clock Stop Acknowledge
3
1
read-write
0
No clock stop acknowledged
#0
1
The Controller may be set in power down by stopping AHB clock and CAN Core clock
#1
CSR
Clock Stop Request
4
1
read-write
0
No clock stop is requested
#0
1
Clock stop requested. When clock stop is requested, rst INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle
#1
DAR
Disable Automatic Retransmission
6
1
read-write
0
Automatic retransmission of messages not transmitted successfully Enabled
#0
1
Automatic retransmission Disabled
#1
EFBI
Edge Filtering during Bus Integration
13
1
read-write
0
Edge filtering Disabled
#0
1
Two consecutive dominant tq required to detect an edge f or hard synchronization
#1
FDOE
FD Operation Enable
8
1
read-write
0
FD operation Disabled
#0
1
FD operation Enabled
#1
INIT
Initialization
Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value.
0
1
read-write
0
Normal Operation
#0
1
Initialization is started
#1
MON
Bus Monitoring Mode
Bit MON can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the Host at any time.
5
1
read-write
0
Bus Monitoring Mode Disabled
#0
1
Bus Monitoring Mode Enabled
#1
NISO
Non ISO Operation
If this bit is set, the CAN FD controller uses the CAN FD frame format as speci ed by the Bosch CAN FD Speci cation V1.0.
15
1
read-write
0
CAN FD frame format according to ISO 11898-1:2015
#0
1
CAN FD frame format according to Bosch CAN FD Speci cation V1.0
#1
PXHD
Protocol Exception Handling Disable
Note: When protocol exception handling is disabled, the controller will transmit an error frame when it detects a protocol exception condition.
12
1
read-write
0
Protocol exception handling Enabled
#0
1
Protocol exception handling Disabled
#1
TEST
Test Mode Enable
7
1
read-write
0
Normal operation, register TEST holds reset values
#0
1
Test Mode, write access to register TEST enabled
#1
TXP
Transmit Pause
If this bit is set, the CAN FD controller pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (refer to Tx Handling section).
14
1
read-write
0
Transmit pause Disabled
#0
1
Transmit pause Enabled
#1
CANFD_DBTP
CANFD_DBTP
Data Bit Timing Prescaler Register (P*)
0xC
-1
read-only
n
0x0
0x0
DBRP
Data Bit Rate Prescaler
16
5
read-only
DSJW
Data Re-Synchronization Jump Width
0
4
read-only
DTSEG1
Data time segment before sample point
8
5
read-only
DTSEG2
Data time segment after sample point
4
4
read-only
TDC
Transmitter Delay Compensation
23
1
read-only
0
Transmitter Delay Compensation Disabled
#0
1
Transmitter Delay Compensation Enabled
#1
CANFD_ECR
CANFD_ECR
Error Counter Register (X*)
0x40
-1
read-only
n
0x0
0x0
CEL
CAN Error Logging
The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC.
The counter is reset by read access to CEL. The counter stops at 0xFF the next increment of TEC or REC sets interrupt flag ELO (CANFD_IR[22]).
16
8
read-only
REC
Receive Error Counter
Actual state of the Receive Error Counter, values between 0 and 127.
8
7
read-only
RP
Receive Error Passive
15
1
read-only
0
The Receive Error Counter is below the error passive level of 128
#0
1
The Receive Error Counter has reached the error passive level of 128
#1
TEC
Transmit Error Counter
Actual state of the Transmit Error Counter, values between 0 and 255.
Note: When ASM (CANFD_CCCR[2]) is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.
0
8
read-only
CANFD_GFC
CANFD_GFC
Global Filter Configuration (P*)
0x80
-1
read-only
n
0x0
0x0
ANFE
Accept Non-matching Frames Extended
De nes how received messages with 29-bit IDs that do not match any element of the filter list are treated.
2
2
read-only
0
Accept in Rx FIFO 0
#00
1
Accept in Rx FIFO 1
#01
2
Reject
#10
3
Reject
#11
ANFS
Accept Non-matching Frames Standard
De nes how received messages with 11-bit IDs that do not match any element of the filter list are treated.
4
2
read-only
0
Accept in Rx FIFO 0
#00
1
Accept in Rx FIFO 1
#01
2
Reject
#10
3
Reject
#11
RRFE
Reject Remote Frames Extended
0
1
read-only
0
Filter remote frames with 29-bit extended IDs
#0
1
Reject all remote frames with 29-bit extended IDs
#1
RRFS
Reject Remote Frames Standard
1
1
read-only
0
Filter remote frames with 11-bit standard IDs
#0
1
Reject all remote frames with 11-bit standard IDs
#1
CANFD_HPMS
CANFD_HPMS
High Priority Message Status
0x94
-1
read-only
n
0x0
0x0
BIDX
Buffer Index
0
6
read-only
FIDX
Filter Index
Index of matching filter element. Range is 0 to CANFD_SIDFC.LSS - 1 or CANFD_XIDFC.LSE - 1
8
7
read-only
FLST
Filter List
Indicates the filter list of the matching filter element.
15
1
read-only
0
Standard Filter List
#0
1
Extended Filter List
#1
MSI
Message Storage Indicator
6
2
read-only
0
No FIFO selected
#00
1
FIFO message lost
#01
2
Message stored in FIFO 0
#10
3
Message stored in FIFO 1
#11
CANFD_IE
CANFD_IE
Interrupt Enable
0x54
-1
read-write
n
0x0
0x0
ARAE
Access to Reserved Address Enable
29
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
BECE
Bit Error Corrected Interrupt Enable
20
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
BEUE
Bit Error Uncorrected Interrupt Enable
21
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
BOE
Bus_Off Status Interrupt Enable
25
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
DRXE
Message stored to Dedicated Rx Buffer Interrupt Enable
19
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
ELOE
Error Logging Overflow Interrupt Enable
22
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
EPE
Error Passive Interrupt Enable
23
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
EWE
Warning Status Interrupt Enable
24
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
HPME
High Priority Message Interrupt Enable
8
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
MRAFE
Message RAM Access Failure Interrupt Enable
17
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PEAE
Protocol Error in Arbitration Phase Enable
27
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PEDE
Protocol Error in Data Phase Enable
28
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RF0FE
Rx FIFO 0 Full Interrupt Enable
2
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RF0LE
Rx FIFO 0 Message Lost Interrupt Enable
3
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RF0NE
Rx FIFO 0 New Message Interrupt Enable
0
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RF0WE
Rx FIFO 0 Watermark Reached Interrupt Enable
1
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RF1FE
Rx FIFO 1 Full Interrupt Enable
6
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RF1LE
Rx FIFO 1 Message Lost Interrupt Enable
7
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RF1NE
Rx FIFO 1 New Message Interrupt Enable
4
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RF1WE
Rx FIFO 1 Watermark Reached Interrupt Enable
5
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TCE
Transmission Completed Interrupt Enable
9
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TCFE
Transmission Cancellation Finished Interrupt Enable
10
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TEFFE
Tx Event FIFO Full Interrupt Enable
14
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TEFLE
Tx Event FIFO Event Lost Interrupt Enable
15
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TEFNE
Tx Event FIFO New Entry Interrupt Enable
12
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TEFWE
Tx Event FIFO Watermark Reached Interrupt Enable
13
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TFEE
Tx FIFO Empty Interrupt Enable
11
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TOOE
Timeout Occurred Interrupt Enable
18
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TSWE
Timestamp Wraparound Interrupt Enable
16
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
WDIE
Watchdog Interrupt Enable
26
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
CANFD_ILE
CANFD_ILE
Interrupt Line Enable
0x5C
-1
read-write
n
0x0
0x0
ENT0
Enable Interrupt Line 0
0
1
read-write
0
Interrupt line canfd_int0 Disabled
#0
1
Interrupt line canfd_int0 Enabled
#1
ENT1
Enable Interrupt Line 1
1
1
read-write
0
Interrupt line canfd_int1 Disabled
#0
1
Interrupt line canfd_int1 Enabled
#1
CANFD_ILS
CANFD_ILS
Interrupt Line Select
0x58
-1
read-write
n
0x0
0x0
ARAL
Access to Reserved Address Line
29
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
BOL
Bus_Off Status Interrupt Line
25
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
DRXL
Message stored to Dedicated Rx Buffer Interrupt Line
19
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
ELOL
Error Logging Overflow Interrupt Line
22
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
EPL
Error Passive Interrupt Line
23
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
EWL
Warning Status Interrupt Line
24
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
HPML
High Priority Message Interrupt Line
8
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
MRAFL
Message RAM Access Failure Interrupt Line
17
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
PEAL
Protocol Error in Arbitration Phase Line
27
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
PEDL
Protocol Error in Data Phase Line
28
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
RF0FL
Rx FIFO 0 Full Interrupt Line
2
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
RF0LL
Rx FIFO 0 Message Lost Interrupt Line
3
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
RF0NL
Rx FIFO 0 New Message Interrupt Line
0
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
RF0WL
Rx FIFO 0 Watermark Reached Interrupt Line
1
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
RF1FL
Rx FIFO 1 Full Interrupt Line
6
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
RF1LL
Rx FIFO 1 Message Lost Interrupt Line
7
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
RF1NL
Rx FIFO 1 New Message Interrupt Line
4
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
RF1WL
Rx FIFO 1 Watermark Reached Interrupt Line
5
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
TCFL
Transmission Cancellation Finished Interrupt Line
10
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
TCL
Transmission Completed Interrupt Line
9
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
TEFFL
Tx Event FIFO Full Interrupt Line
14
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
TEFLL
Tx Event FIFO Event Lost Interrupt Line
15
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
TEFNL
Tx Event FIFO New Entry Interrupt Line
12
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
TEFWL
Tx Event FIFO Watermark Reached Interrupt Line
13
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
TFEL
Tx FIFO Empty Interrupt Line
11
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
TOOL
Timeout Occurred Interrupt Line
18
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
TSWL
Timestamp Wraparound Interrupt Line
16
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
WDIL
Watchdog Interrupt Line
26
1
read-write
0
Interrupt assigned to CAN interrupt line 0
#0
1
Interrupt assigned to CAN interrupt line 1
#1
CANFD_IR
CANFD_IR
Interrupt Register
0x50
-1
read-write
n
0x0
0x0
ARA
Access to Reserved Address
29
1
read-write
0
No access to reserved address occurred
#0
1
Access to reserved address occurred
#1
BO
Bus_Off Status
25
1
read-write
0
Bus_Off status unchanged
#0
1
Bus_Off status changed
#1
DRX
Message stored to Dedicated Rx Buffer
The flag is set whenever a received message has been stored into a dedicated Rx Buffer.
19
1
read-write
0
No Rx Buffer updated
#0
1
At least one received message stored into an Rx Buffer
#1
ELO
Error Logging Overflow
22
1
read-write
0
CAN Error Logging Counter did not overflow
#0
1
Overflow of CAN Error Logging Counter occurred
#1
EP
Error Passive
23
1
read-write
0
Error_Passive status unchanged
#0
1
Error_Passive status changed
#1
EW
Warning Status
24
1
read-write
0
Error_Warning status unchanged
#0
1
Error_Warning status changed
#1
HPM
High Priority Message
8
1
read-write
0
No high priority message received
#0
1
High priority message received
#1
MRAF
Message RAM Access Failure
The flag is set, when the Rx Handler
• Has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.
• Was not able to write a message to the Message RAM. In this case message storage is aborted.
In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location.
The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the CAN FD controller is switched into Restricted Operation Mode (refer to Restricted Operation Mode). To leave Restricted Operation Mode, the Host CPU has to reset CANFD_ASM (CANFD_CCCR[2]).
17
1
read-write
0
No Message RAM access failure occurred
#0
1
Message RAM access failure occurred
#1
PEA
Protocol Error in Arbitration Phase
Note: Nominal bit time is used.
27
1
read-write
0
No protocol error in arbitration phase
#0
1
Protocol error in arbitration phase detected (CANFD_LEC (CANFD_PSR[2:0]) no equal 0 or 7)
#1
PED
Protocol Error in Data Phase
Note: Data bit time is used.
28
1
read-write
0
No protocol error in data phase
#0
1
Protocol error in data phase detected (DLEC (CANFD_PSR[10:8]) no equal 0 or 7)
#1
RF0F
Rx FIFO 0 Full
2
1
read-write
0
Rx FIFO 0 not full
#0
1
Rx FIFO 0 full
#1
RF0L
Rx FIFO 0 Message Lost
3
1
read-write
0
No Rx FIFO 0 message lost
#0
1
Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero
#1
RF0N
Rx FIFO 0 New Message
0
1
read-write
0
No new message written to Rx FIFO 0
#0
1
New message written to Rx FIFO 0
#1
RF0W
Rx FIFO 0 Watermark Reached
1
1
read-write
0
Rx FIFO 0 ll level below watermark
#0
1
Rx FIFO 0 ll level reached watermark
#1
RF1F
Rx FIFO 1 Full
6
1
read-write
0
Rx FIFO 1 not full
#0
1
Rx FIFO 1 full
#1
RF1L
Rx FIFO 1 Message Lost
7
1
read-write
0
No Rx FIFO 1 message lost
#0
1
Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero
#1
RF1N
Rx FIFO 1 New Message
4
1
read-write
0
No new message written to Rx FIFO 1
#0
1
New message written to Rx FIFO 1
#1
RF1W
Rx FIFO 1 Watermark Reached
5
1
read-write
0
Rx FIFO 1 ll level below watermark
#0
1
Rx FIFO 1 ll level reached watermark
#1
TC
Transmission Completed
9
1
read-write
0
No transmission completed
#0
1
Transmission completed
#1
TCF
Transmission Cancellation Finished
10
1
read-write
0
No transmission cancellation finished
#0
1
Transmission cancellation finished
#1
TEFF
Tx Event FIFO Full
14
1
read-write
0
Tx Event FIFO not full
#0
1
Tx Event FIFO full
#1
TEFL
Tx Event FIFO Element Lost
15
1
read-write
0
No Tx Event FIFO element lost
#0
1
Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero
#1
TEFN
Tx Event FIFO New Entry
12
1
read-write
0
Tx Event FIFO unchanged
#0
1
Tx Handler wrote Tx Event FIFO element
#1
TEFW
Tx Event FIFO Watermark Reached
13
1
read-write
0
Tx Event FIFO ll level below watermark
#0
1
Tx Event FIFO ll level reached watermark
#1
TFE
Tx FIFO Empty
11
1
read-write
0
Tx FIFO non-empty
#0
1
Tx FIFO empty
#1
TOO
Timeout Occurred
18
1
read-write
0
No timeout
#0
1
Timeout reached
#1
TSW
Timestamp Wraparound
16
1
read-write
0
No timestamp counter wrap-around
#0
1
Timestamp counter wrapped around
#1
WDI
Watchdog Interrupt
26
1
read-write
0
No Message RAM Watchdog event occurred
#0
1
Message RAM Watchdog event due to missing READY
#1
CANFD_NBTP
CANFD_NBTP
Nominal Bit Timing Prescaler Register (P*)
0x1C
-1
read-only
n
0x0
0x0
NBRP
Nominal Bit Rate Prescaler
The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used
16
9
read-only
NSJW
Nominal Re-Synchronization Jump Width
25
7
read-only
NTSEG1
Nominal Time Segment before Sample Point
8
8
read-only
NTSEG2
Nominal Time Segment after Sample Point
Note: With a CAN Core clock (cclk) of 8 MHz, the reset value of 0x06000A03 configures the controller for a bit rate of 500 kBit/s.
0
7
read-only
CANFD_NDAT1
CANFD_NDAT1
New Data 1
0x98
-1
read-write
n
0x0
0x0
NDn
New Data
The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register.
0
32
read-write
0
Rx Buffer not updated
0
1
Rx Buffer updated from new message
1
CANFD_NDAT2
CANFD_NDAT2
New Data 2
0x9C
-1
read-write
n
0x0
0x0
NDn
New Data
The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register.
0
32
read-write
0
Rx Buffer not updated
0
1
Rx Buffer updated from new message
1
CANFD_PSR
CANFD_PSR
Protocol Status Register (XS*)
0x44
-1
read-only
n
0x0
0x0
ACT
Activity
Monitors the module's CAN communication state.
3
2
read-only
0
Synchronizing - node is synchronizing on CAN communication
#00
1
Idle - node is neither receiver nor transmitter
#01
2
Receiver - node is operating as receiver
#10
3
Transmitter - node is operating as transmitter
#11
BO
Bus_Off Status
7
1
read-only
0
The CAN FD controller is not Bus_Off
#0
1
The CAN FD controller is in Bus_Off state
#1
DLEC
Data Phase Last Error Code
Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to 0 when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.
8
3
read-only
EP
Error Passive
5
1
read-only
0
The CAN FD controller is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected
#0
1
The CAN FD controller is in the Error_Passive state
#1
EW
Warning Status
6
1
read-only
0
Both error counters are below the Error_Warning limit of 96
#0
1
At least one of error counter has reached the Error_Warning limit of 96
#1
LEC
Last Error Code
The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error.
0
3
read-only
0
No Error: No error occurred since LEC has been reset by successful reception or transmission
#000
1
Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed
#001
2
Form Error: A fixed format part of a received frame has the wrong format
#010
3
AckError: The message transmitted by the CANFD CONTROLLER was not acknowledged by another node
#011
4
Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant
#100
5
Bit0Error : During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed)
#101
6
CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data
#110
7
NoChange: Any read access to the Protocol Status Register re-initializes the LEC to 7.When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the Protocol Status Register
#111
PXE
Protocol Exception Event
14
1
read-only
0
No protocol exception event occurred since last read access
#0
1
Protocol exception event occurred
#1
RBRS
BRS flag of last received CAN FD Message
This bit is set together with RFDF, independent of acceptance filtering.
Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact.
12
1
read-only
0
Last received CAN FD message did not have its BRS flag set
#0
1
Last received CAN FD message had its BRS flag set
#1
RESI
ESI flag of last received CAN FD Message
This bit is set together with RFDF, independent of acceptance filtering.
11
1
read-only
0
Last received CAN FD message did not have its ESI flag set
#0
1
Last received CAN FD message had its ESI flag set
#1
RFDF
Received a CAN FD Message
This bit is set independent of acceptance filtering.
Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact.
13
1
read-only
0
Since this bit was reset by the CPU, no CAN FD message has been received
#0
1
Message in CAN FD format with FDF flag set has been received
#1
TDCV
Transmitter Delay Compensation Value
Position of the secondary sample point, de ned by the sum of the measured delay from CANx_TXD to CANx_RXD and TDCO (TDCR[[14:8]). The SSP position is, in the data phase, the number of minimum time quata (mtq) between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq.
16
7
read-only
CANFD_RWD
CANFD_RWD
RAM Watchdog (P*)
0x14
-1
read-only
n
0x0
0x0
WDC
Watchdog Configuration
Start value of the Message RAM Watchdog Counter. With the reset value of 00 the counter is disabled.
0
8
read-only
WDV
Watchdog Value
Actual Message RAM Watchdog Counter Value.
8
8
read-only
CANFD_RXBC
CANFD_RXBC
Rx Buffer Configuration (P*)
0xAC
-1
read-only
n
0x0
0x0
RBSA
Rx Buffer Start Address
Con gures the start address of the Rx Buffers section in the Message RAM (32-bit word address).
2
14
read-only
CANFD_RXESC
CANFD_RXESC
Rx Buffer / FIFO Element Size Configuration (P*)
0xBC
-1
read-only
n
0x0
0x0
F0DS
Rx FIFO 0 Data Field Size
Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by CANFD_RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame data field is ignored.
0
3
read-only
0
8 byte data field
#000
1
12 byte data field
#001
2
16 byte data field
#010
3
20 byte data field
#011
4
24 byte data field
#100
5
32 byte data field
#101
6
48 byte data field
#110
7
64 byte data field
#111
F1DS
Rx FIFO 1 Data Field Size
4
3
read-only
0
8 byte data field
#000
1
12 byte data field
#001
2
16 byte data field
#010
3
20 byte data field
#011
4
24 byte data field
#100
5
32 byte data field
#101
6
48 byte data field
#110
7
64 byte data field
#111
RBDS
Rx Buffer Data Field Size
8
3
read-only
0
8 byte data field
#000
1
12 byte data field
#001
2
16 byte data field
#010
3
20 byte data field
#011
4
24 byte data field
#100
5
32 byte data field
#101
6
48 byte data field
#110
7
64 byte data field
#111
CANFD_RXF0A
CANFD_RXF0A
Rx FIFO 0 Acknowledge
0xA8
-1
read-write
n
0x0
0x0
F0A
Rx FIFO 0 Acknowledge Index
After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index F0GI (CANFD_RXF0S[13:8]) to F0AI (CANFD_RXF0A[5:0]) + 1 and update the FIFO 0 Fill Level CANFD_RXF0S.F0FL.
0
6
read-write
CANFD_RXF0C
CANFD_RXF0C
Rx FIFO 0 Configuration (P*)
0xA0
-1
read-only
n
0x0
0x0
F0OM
FIFO 0 Operation Mode
FIFO 0 can be operated in blocking or in overwrite mode (refer to Rx FIFOs).
31
1
read-only
0
FIFO 0 blocking mode
#0
1
FIFO 0 overwrite mode
#1
F0S
Rx FIFO 0 Size
The Rx FIFO 0 elements are indexed from 0 to F0S-1
16
7
read-only
0
No Rx FIFO 0
0
F0SA
Rx FIFO 0 Start Address
Start address of Rx FIFO 0 in Message RAM (32-bit word address).
2
14
read-only
F0WM
Rx FIFO 0 Watermark
24
7
read-only
0
Watermark interrupt Disabled
0
CANFD_RXF0S
CANFD_RXF0S
Rx FIFO 0 Status
0xA4
-1
read-only
n
0x0
0x0
F0F
Rx FIFO 0 Full
24
1
read-only
0
Rx FIFO 0 not full
#0
1
Rx FIFO 0 full
#1
F0FL
Rx FIFO 0 Fill Level
Number of elements stored in Rx FIFO 0, range 0 to 64
0
7
read-only
F0GI
Rx FIFO 0 Get Index
Rx FIFO 0 read index pointer, range 0 to 63.
8
6
read-only
F0PI
Rx FIFO 0 Put Index
Rx FIFO 0 write index pointer, range 0 to 63.
16
6
read-only
RF0L
Rx FIFO 0 Message Lost
25
1
read-only
1
Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero
#1
CANFD_RXF1A
CANFD_RXF1A
Rx FIFO 1 Acknowledge
0xB8
-1
read-write
n
0x0
0x0
F1A
Rx FIFO 1 Acknowledge Index
After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index F1GI (CANFD_RXF1S[13:8]) to F1AI (CANFD_RXF1A[5:0]) + 1 and update the FIFO 1 Fill Level F1FL (CANFD_RXF1S[6:0]).
0
6
read-write
CANFD_RXF1C
CANFD_RXF1C
Rx FIFO 1 Configuration (P*)
0xB0
-1
read-only
n
0x0
0x0
F1OM
FIFO 1 Operation Mode
FIFO 1 can be operated in blocking or in overwrite mode (refer to Rx FIFOs).
31
1
read-only
0
FIFO 1 blocking mode
#0
1
FIFO 1 overwrite mode
#1
F1S
Rx FIFO 1 Size
The Rx FIFO 1 elements are indexed from 0 to F1S - 1
16
7
read-only
0
No Rx FIFO 1
0
F1SA
Rx FIFO 1 Start Address
Start address of Rx FIFO 1 in Message RAM (32-bit word address, refer to Figure 6.2011).
2
14
read-only
F1WM
Rx FIFO 1 Watermark
24
7
read-only
0
Watermark interrupt Disabled
0
CANFD_RXF1S
CANFD_RXF1S
Rx FIFO 1 Status
0xB4
-1
read-only
n
0x0
0x0
F1F
Rx FIFO 1 Full
24
1
read-only
0
Rx FIFO 1 not full
#0
1
Rx FIFO 1 full
#1
F1FL
Rx FIFO 1 Fill Level
Number of elements stored in Rx FIFO 1, range 0 to 64
0
7
read-only
F1G
Rx FIFO 1 Get Index
Rx FIFO 1 read index pointer, range 0 to 63.
8
6
read-only
F1P
Rx FIFO 1 Fill Level
Number of elements stored in Rx FIFO 1, range 0 to 64.
16
6
read-only
RF1L
Rx FIFO 1 Message Lost
25
1
read-only
1
Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero
#1
CANFD_SIDFC
CANFD_SIDFC
Standard ID Filter Configuration (P*)
0x84
-1
read-only
n
0x0
0x0
FLSSA
Filter List Standard Start Address
Start address of standard Message ID filter list (32-bit word address, refer to Figure 6.2011).
2
14
read-only
LSS
List Size Standard
16
8
read-only
0
No standard Message ID filter
0
CANFD_TDCR
CANFD_TDCR
Transmitter Delay Compensation Register (P*)
0x48
-1
read-only
n
0x0
0x0
TDCF
Transmitter Delay Compensation Filter Window Length
De nes the minimum value for the SSP position, dominant edges on CANx_RXD that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq.
0
7
read-only
TDCO
Transmitter Delay Compensation SSP Offset
Offset value de ning the distance between the measured delay from CANx_TXD to CANx_RXD and the secondary sample point. Valid values are 0 to 127 mtq.
8
7
read-only
CANFD_TEST
CANFD_TEST
Test Register (P*)
0x10
-1
read-only
n
0x0
0x0
LBCK
Loop Back Mode
4
1
read-only
0
Reset value, Loop Back Mode Disabled
#0
1
Loop Back Mode Enabled (refer to TEST Mode in the Operation Mode section)
#1
RX
Receive Pin
Monitors the actual value of pin CANx_RXD
7
1
read-only
0
The CAN bus is dominant (CANx_RXD = 0)
#0
1
The CAN bus is recessive (CANx_RXD = 1)
#1
TX
Control of Transmit Pin
5
2
read-only
0
Reset value, CANx_TXD controlled by the CAN Core, updated at the end of the CAN bit time
#00
1
Sample Point can be monitored at pin CANx_TXD
#01
2
Dominant ('0') level at pin CANx_TXD
#10
3
Recessive ('1') level at pin CANx_TXD
#11
CANFD_TOCC
CANFD_TOCC
Timeout Counter Configuration (P*)
0x28
-1
read-only
n
0x0
0x0
ETOC
Enable Timeout Counter
Note: For use of timeout function with CAN FD, refer to Timeout Counter section.
0
1
read-only
0
Timeout Counter Disabled
#0
1
Timeout Counter Enabled
#1
TOP
Timeout Period
Start value of the Timeout Counter (down-counter). Con gures the Timeout Period.
16
16
read-only
TOS
Timeout Select
When operating in Continuous mode, a write to CANFD_TOCV presets the counter to the value con gured by CANFD_TOP (TOCC[31:16]) and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value con gured by CANFD_TOP (TOCC[31:16]). Down-counting is started when the rst FIFO element is stored.
1
2
read-only
0
Continuous operation
#00
1
Timeout controlled by Tx Event FIFO
#01
2
Timeout controlled by Rx FIFO 0
#10
3
Timeout controlled by Rx FIFO 1
#11
CANFD_TOCV
CANFD_TOCV
Timeout Counter Value (C*)
0x2C
-1
read-only
n
0x0
0x0
TOC
Timeout Counter
The filed is decremented in multiples of CAN bit times [ 1...16 ] depending on the configuration of TCP (CANFD_TSCC[19:16]). When decremented to 0, interrupt flag TOO (CANFD_IR[18]) is set and the timeout counter is stopped. Start and reset/restart conditions are con gured via TOS (CANFD_TOCC[1:0]).
0
16
read-only
CANFD_TSCC
CANFD_TSCC
Timestamp Counter Configuration (P*)
0x20
-1
read-only
n
0x0
0x0
TCP
Timestamp Counter Prescaler
Con gures the timestamp and timeout counters time unit in multiples of CAN bit times [ 1...16 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
16
4
read-only
TSS
Timestamp Select
0
2
read-only
0
Timestamp counter value always 0x0000
#00
1
Timestamp counter value incremented according to TCP
#01
2
Reserved.
#10
3
Same as '00'
#11
CANFD_TSCV
CANFD_TSCV
Timestamp Counter Value (C*)
0x24
-1
read-only
n
0x0
0x0
TSC
Timestamp Counter
Note: A 'wrap around' is a change of the Timestamp Counter value from non-zero to 0 not caused by write access to CANFD_TSCV.
0
16
read-only
CANFD_TXBAR
CANFD_TXBAR
Tx Buffer Add Request
0xD0
-1
read-write
n
0x0
0x0
ARn
Add RequestEach Tx Buffer has its own Add Request bit Writing a 1 will set the corresponding Add Request bit writing a 0 has no impact This enables the Host to set transmission requests for multiple Tx Buffers with one write to CANFD_TXBAR CANFD_TXBAR bits are set only for those Tx Buffers con gured via CANFD_TXBC When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed.
Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding CANFD_TXBRP bit already set), this add request is ignored.
0
32
read-write
0
No transmission request added
0
1
Transmission requested added
1
CANFD_TXBC
CANFD_TXBC
Tx Buffer Configuration (P*)
0xC0
-1
read-only
n
0x0
0x0
NDTB
Number of Dedicated Transmit Buffers
16
6
read-only
0
No Dedicated Tx Buffers
0
TBSA
Tx Buffers Start Address
Start address of Tx Buffers section in Message RAM (32-bit word address, refer to Figure 6.2011).
Note: The sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers.
2
14
read-only
TFQM
Tx FIFO/Queue Mode
30
1
read-only
0
Tx FIFO operation
#0
1
Tx Queue operation
#1
TFQS
Transmit FIFO/Queue Size
24
6
read-only
0
No Tx FIFO/Queue
0
CANFD_TXBCF
CANFD_TXBCF
Tx Buffer Cancellation Finished
0xDC
-1
read-only
n
0x0
0x0
CFn
Cancellation Finished
Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a cancellation was requested via CANFD_TXBCR. In case the corresponding CANFD_TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register CANFD_TXBAR.
0
32
read-only
0
No transmit buffer cancellation
0
1
Transmit buffer cancellation finished
1
CANFD_TXBCIE
CANFD_TXBCIE
Tx Buffer Cancellation Finished Interrupt Enable
0xE4
-1
read-write
n
0x0
0x0
CFIEn
Cancellation Finished Interrupt Enable
Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0
32
read-write
0
Cancellation finished interrupt Disabled
0
1
Cancellation finished interrupt Enabled
1
CANFD_TXBCR
CANFD_TXBCR
Tx Buffer Cancellation Request
0xD4
-1
read-write
n
0x0
0x0
CRn
Cancellation Request
Each Tx Buffer has its own Cancellation Request bit. Writing a 1 will set the corresponding Cancellation Request bit writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to CANFD_TXBCR. CANFD_TXBCR bits are set only for those Tx Buffers con gured via CANFD_TXBC. The bits remain set until the corresponding bit of CANFD_TXBRP is reset.
0
32
read-write
0
No cancellation pending
0
1
Cancellation pending
1
CANFD_TXBRP
CANFD_TXBRP
Tx Buffer Request Pending
0xCC
-1
read-only
n
0x0
0x0
TRPn
Transmission Request PendingEach Tx Buffer has its own Transmission Request Pending bit The bits are set via register CANFD_TXBAR The bits are reset after a requested transmission has completed or has been cancelled via register CANFD_TXBCR.
CANFD_TXBRP bits are set only for those Tx Buffers con gured via CANFD_TXBC. After a CANFD_TXBRP bit has been set, a Tx scan (refer to Tx Handling section) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID).
A cancellation request resets the corresponding transmission request pending bit of register CANFD_TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding CANFD_TXBRP bit has been reset.
After a cancellation has been requested, a finished cancellation is signaled via CANFD_TXBCF
• after successful transmission together with the corresponding CANFD_TXBTO bit
• when the transmission has not yet been started at the point of cancellation
• when the transmission has been aborted due to lost arbitration
• when an error occurred during frame transmission
In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding CANFD_TXBCF bit is set for all unsuccessful transmissions.
Note: CANFD_TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding CANFD_TXBRP bit is reset.
0
32
read-only
0
No transmission request pending
0
1
Transmission request pending
1
CANFD_TXBTIE
CANFD_TXBTIE
Tx Buffer Transmission Interrupt Enable
0xE0
-1
read-write
n
0x0
0x0
TIEn
Transmission Interrupt Enable
Each Tx Buffer has its own Transmission Interrupt Enable bit.
0
32
read-write
0
Transmission interrupt Disabled
0
1
Transmission interrupt Enabled
1
CANFD_TXBTO
CANFD_TXBTO
Tx Buffer Transmission Occurred
0xD8
-1
read-only
n
0x0
0x0
TOn
Transmission Occurred
Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register CANFD_TXBAR.
0
32
read-only
0
No transmission occurred
0
1
Transmission occurred
1
CANFD_TXEFA
CANFD_TXEFA
Tx Event FIFO Acknowledge
0xF8
-1
read-write
n
0x0
0x0
EFA
Event FIFO Acknowledge Index
After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index EFGI (CANFD_TXEFS[12:8]) to EFAI + 1 and update the Event FIFO Fill Level EFFL (CANFD_TXEFS[5:0])
0
5
read-write
CANFD_TXEFC
CANFD_TXEFC
Tx Event FIFO Configuration (P*)
0xF0
-1
read-only
n
0x0
0x0
EFS
Event FIFO Size
The Tx Event FIFO elements are indexed from 0 to EFS - 1
16
6
read-only
0
Tx Event FIFO Disabled
0
EFSA
Event FIFO Start Address
Start address of Tx Event FIFO in Message RAM (32-bit word address, refer to Figure 6.2011).
2
14
read-only
EFWN
Event FIFO Watermark
24
6
read-only
0
Watermark interrupt Disabled
0
CANFD_TXEFS
CANFD_TXEFS
Tx Event FIFO Status
0xF4
-1
read-only
n
0x0
0x0
EFF
Event FIFO Full
24
1
read-only
0
Tx Event FIFO not full
#0
1
Tx Event FIFO full
#1
EFFL
Event FIFO Fill Level
Number of elements stored in Tx Event FIFO, range 0 to 32
0
6
read-only
EFG
Event FIFO Get Index
Tx Event FIFO read index pointer, range 0 to 31
8
5
read-only
EFP
Event FIFO Put Index
Tx Event FIFO write index pointer, range 0 to 31
16
5
read-only
TEFL
Tx Event FIFO Element Lost
This bit is a copy of interrupt flag TEFL (CANFD_IR[15]). When TEFL is reset, this bit is also reset.
25
1
read-only
0
No Tx Event FIFO element lost
#0
1
Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero
#1
CANFD_TXESC
CANFD_TXESC
Tx Buffer Element Size Configuration (P*)
0xC8
-1
read-only
n
0x0
0x0
TBDS
Tx Buffer Data Field Size
Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size CANFD_TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as 0xCC (padding bytes).
0
3
read-only
0
8 byte data field
#000
1
12 byte data field
#001
2
16 byte data field
#010
3
20 byte data field
#011
4
24 byte data field
#100
5
32 byte data field
#101
6
48 byte data field
#110
7
64 byte data field
#111
CANFD_TXFQS
CANFD_TXFQS
Tx FIFO/Queue Status
0xC4
-1
read-only
n
0x0
0x0
TFFL
Tx FIFO Free Level
Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.
Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.
0
6
read-only
TFG
Tx FIFO Get Index
8
5
read-only
TFQF
Tx FIFO/Queue Full
21
1
read-only
0
Tx FIFO/Queue not full
#0
1
Tx FIFO/Queue full
#1
TFQP
Tx FIFO/Queue Put Index
Tx FIFO/Queue write index pointer, range 0 to 31.
16
5
read-only
CANFD_XIDAM
CANFD_XIDAM
Extended ID AND Mask (P*)
0x90
-1
read-only
n
0x0
0x0
EIDM
Extended ID Mask
For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active.
0
29
read-only
CANFD_XIDFC
CANFD_XIDFC
Extended ID Filter Configuration (P*)
0x88
-1
read-only
n
0x0
0x0
FLESA
Filter List Extended Start Address
Start address of extended Message ID filter list (32-bit word address, refer to Figure 6.2011).
2
14
read-only
LSE
List Size Extended
16
7
read-only
0
No extended Message ID filter
0
CLK
CLK Register Map
CLK
0x0
0x0
0x24
registers
n
0x30
0x8
registers
n
0x50
0x4
registers
n
0x60
0x4
registers
n
0x70
0x10
registers
n
0x90
0x4
registers
n
0xB4
0x4
registers
n
AHBCLK
CLK_AHBCLK
AHB Devices Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
CANFD0CKEN
CANFD0 Clock Enable Bit
23
1
read-write
0
CANFD0 clock Disabled
#0
1
CANFD0 clock Enabled
#1
CRCCKEN
CRC Generator Controller Clock Enable Bit
7
1
read-write
0
CRC peripheral clock Disabled
#0
1
CRC peripheral clock Enabled
#1
EXSTCKEN
External System Tick Clock Enable Bit
4
1
read-write
0
External System tick clock Disabled
#0
1
External System tick clock Enabled
#1
FMCIDLE
Flash Memory Controller Clock Enable Bit in IDLE Mode
15
1
read-write
0
FMC clock Disabled when chip is under IDLE mode in this case, PDMA cannot access FMC memory
#0
1
FMC clock Enabled when chip is under IDLE mode PDMA can access FMC memory
#1
GPACKEN
GPIOA Clock Enable Bit
24
1
read-write
0
GPIOA port clock Disabled
#0
1
GPIOA port clock Enabled
#1
GPBCKEN
GPIOB Clock Enable Bit
25
1
read-write
0
GPIOB port clock Disabled
#0
1
GPIOB port clock Enabled
#1
GPCCKEN
GPIOC Clock Enable Bit
26
1
read-write
0
GPIOC port clock Disabled
#0
1
GPIOC port clock Enabled
#1
GPFCKEN
GPIOF Clock Enable Bit
29
1
read-write
0
GPIOF port clock Disabled
#0
1
GPIOF port clock Enabled
#1
ISPCKEN
Flash ISP Controller Clock Enable Bit
2
1
read-write
0
Flash ISP peripheral clock Disabled
#0
1
Flash ISP peripheral clock Enabled
#1
PDMACKEN
PDMA Controller Clock Enable Bit
1
1
read-write
0
PDMA peripheral clock Disabled
#0
1
PDMA peripheral clock Enabled
#1
APBCLK0
CLK_APBCLK0
APB Devices Clock Enable Control Register 0
0x8
-1
read-write
n
0x0
0x0
CLKOCKEN
CLKO Clock Enable Bit
6
1
read-write
0
CLKO clock Disabled
#0
1
CLKO clock Enabled
#1
EADCCKEN
Enhanced Analog-digital-converter (EADC) Clock Enable Bit
28
1
read-write
0
EADC clock Disabled
#0
1
EADC clock Enabled
#1
I2C0CKEN
I2C0 Clock Enable Bit
8
1
read-write
0
I2C0 clock Disabled
#0
1
I2C0 clock Enabled
#1
I2C1CKEN
I2C1 Clock Enable Bit
9
1
read-write
0
I2C1 clock Disabled
#0
1
I2C1 clock Enabled
#1
RTCCKEN
Real-time-clock APB Interface Clock Enable Bit
This bit is used to control the RTC APB clock.
1
1
read-write
0
RTC clock Disabled
#0
1
RTC clock Enabled
#1
SPI0CKEN
SPI0 Clock Enable Bit
13
1
read-write
0
SPI0 clock Disabled
#0
1
SPI0 clock Enabled
#1
TMR0CKEN
Timer0 Clock Enable Bit
2
1
read-write
0
Timer0 clock Disabled
#0
1
Timer0 clock Enabled
#1
TMR1CKEN
Timer1 Clock Enable Bit
3
1
read-write
0
Timer1 clock Disabled
#0
1
Timer1 clock Enabled
#1
TMR2CKEN
Timer2 Clock Enable Bit
4
1
read-write
0
Timer2 clock Disabled
#0
1
Timer2 clock Enabled
#1
TMR3CKEN
Timer3 Clock Enable Bit
5
1
read-write
0
Timer3 clock Disabled
#0
1
Timer3 clock Enabled
#1
UART0CKEN
UART0 Clock Enable Bit
16
1
read-write
0
UART0 clock Disabled
#0
1
UART0 clock Enabled
#1
UART1CKEN
UART1 Clock Enable Bit
17
1
read-write
0
UART1 clock Disabled
#0
1
UART1 clock Enabled
#1
UART2CKEN
UART2 Clock Enable Bit
18
1
read-write
0
UART2 clock Disabled
#0
1
UART2 clock Enabled
#1
UART3CKEN
UART3 Clock Enable Bit
19
1
read-write
0
UART3 clock Disabled
#0
1
UART3 clock Enabled
#1
UART4CKEN
UART4 Clock Enable Bit
20
1
read-write
0
UART4 clock Disabled
#0
1
UART4 clock Enabled
#1
USBDCKEN
USB Device Clock Enable Bit
27
1
read-write
0
USB Device clock Disabled
#0
1
USB Device clock Enabled
#1
WDTCKEN
Watchdog Timer Clock Enable Bit (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: This bit is forced to 1 when CONFIG0[3] or CONFIG0[4] or CONFIG0[31] is 0.
Note 3: Reset by power on reset or watchdog reset or software chip reset.
0
1
read-write
0
Watchdog timer clock Disabled
#0
1
Watchdog timer clock Enabled
#1
APBCLK1
CLK_APBCLK1
APB Devices Clock Enable Control Register 1
0xC
-1
read-write
n
0x0
0x0
BPWM0CKEN
BPWM0 Clock Enable Bit
18
1
read-write
0
BPWM0 clock Disabled
#0
1
BPWM0 clock Enabled
#1
USCI0CKEN
USCI0 Clock Enable Bit
8
1
read-write
0
USCI0 clock Disabled
#0
1
USCI0 clock Enabled
#1
CDLOWB
CLK_CDLOWB
Clock Frequency Range Detector Lower Boundary Register
0x7C
-1
read-write
n
0x0
0x0
LOWERBD
HXT Clock Frequency Range Detector Lower Boundary Value
The bits define the minimum value of frequency range detector window.
When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
Note :The frequency out of range will be asserted when HIRC_period*512 HXT_period*CLK_DUPB or HIRC_period*512 HXT_period*CLK_CDLOWB.
0
10
read-write
CDUPB
CLK_CDUPB
Clock Frequency Range Detector Upper Boundary Register
0x78
-1
read-write
n
0x0
0x0
UPERBD
HXT Clock Frequency Range Detector Upper Boundary Value
The bits define the maximum value of frequency range detector window.
When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
Note :Frequency out of range will be asserted when HIRC_period*512 HXT_period*CLK_DUPB or HIRC_period*512 HXT_period*CLK_CDLOWB.
0
10
read-write
CLKDCTL
CLK_CLKDCTL
Clock Fail Detector Control Register
0x70
-1
read-write
n
0x0
0x0
HXTFDEN
HXT Clock Fail Detector Enable Bit
4
1
read-write
0
4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled
#0
1
4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled
#1
HXTFIEN
HXT Clock Fail Interrupt Enable Bit
5
1
read-write
0
4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled
#0
1
4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled
#1
HXTFQDEN
HXT Clock Frequency Range Detector Enable Bit
16
1
read-write
0
4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled
#0
1
4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled
#1
HXTFQIEN
HXT Clock Frequency Range Detector Interrupt Enable Bit
17
1
read-write
0
4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled
#0
1
4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled
#1
LXTFDEN
LXT Clock Fail Detector Enable Bit
12
1
read-write
0
32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled
#0
1
32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled
#1
LXTFIEN
LXT Clock Fail Interrupt Enable Bit
13
1
read-write
0
32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled
#0
1
32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled
#1
CLKDIV0
CLK_CLKDIV0
Clock Divider Number Register 0
0x20
-1
read-write
n
0x0
0x0
EADCDIV
EADC Clock Divide Number From EADC Clock Source
16
8
read-write
HCLKDIV
HCLK Clock Divide Number From HCLK Clock Source
Note: This field is only reset by power on reset.
0
4
read-write
UART0DIV
UART0 Clock Divide Number From UART0 Clock Source
8
4
read-write
UART1DIV
UART1 Clock Divide Number From UART1 Clock Source
12
4
read-write
CLKDIV4
CLK_CLKDIV4
Clock Divider Number Register 4
0x30
-1
read-write
n
0x0
0x0
CANFD0DIV
CANFD0 Clock Divide Number From CANFD0 Clock Source
16
2
read-write
UART2DIV
UART2 Clock Divide Number From UART2 Clock Source
0
4
read-write
UART3DIV
UART3 Clock Divide Number From UART3 Clock Source
4
4
read-write
UART4DIV
UART4 Clock Divide Number From UART4 Clock Source
8
4
read-write
CLKDSTS
CLK_CLKDSTS
Clock Fail Detector Status Register
0x74
-1
read-write
n
0x0
0x0
HXTFIF
HXT Clock Fail Interrupt Flag (Write Protect)
Note: Write 1 to clear the bit to 0.
0
1
read-write
0
4~32 MHz external high speed crystal oscillator (HXT) clock is normal
#0
1
4~32 MHz external high speed crystal oscillator (HXT) clock stops
#1
HXTFQIF
HXT Clock Frequency Range Detector Interrupt Flag (Write Protect)
Note: Write 1 to clear the bit to 0.
8
1
read-write
0
4~32 MHz external high speed crystal oscillator (HXT) clock frequency is normal
#0
1
4~32 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal
#1
LXTFIF
LXT Clock Fail Interrupt Flag (Write Protect)
Note: Write 1 to clear the bit to 0.
1
1
read-write
0
32.768 kHz external low speed crystal oscillator (LXT) clock is normal
#0
1
32.768 kHz external low speed crystal oscillator (LXT) stops
#1
CLKOCTL
CLK_CLKOCTL
Clock Output Control Register
0x60
-1
read-write
n
0x0
0x0
CLK1HZEN
Clock Output 1Hz Enable Bit
6
1
read-write
0
1 Hz clock output for 32.768 kHz frequency compensation Disabled
#0
1
1 Hz clock output for 32.768 kHz frequency compensation Enabled
#1
DIV1EN
Clock Output Divide One Enable Bit
5
1
read-write
0
Clock Output will output clock with source frequency divided by FREQSEL
#0
1
Clock Output will output clock with source frequency
#1
FREQSEL
Clock Output Frequency Selection
The formula of output frequency is
Fin is the input clock frequency.
Fout is the frequency of divider output clock.
N is the 4-bit value of FREQSEL[3:0].
0
4
read-write
CLKSEL0
CLK_CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
CANFD0SEL
CANFD0 Clock Source Selection
24
1
read-write
0
Clock source from HCLK
#0
1
Clock source from HXT
#1
HCLKSEL
HCLK Clock Source Selection (Write Protect)
Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by power on reset.
0
3
read-write
0
Clock source from HXT
#000
1
Clock source from LXT
#001
3
Clock source from LIRC
#011
5
Clock source from MIRC
#101
7
Clock source from HIRC
#111
STCLKSEL
Cortex-M23 SysTick Clock Source Selection (Write Protect)
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
3
3
read-write
0
Clock source from HXT
#000
1
Clock source from LXT
#001
2
Clock source from HXT/2
#010
3
Clock source from HCLK/2
#011
7
Clock source from HIRC/2
#111
CLKSEL1
CLK_CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
CLKOSEL
Clock Divider Clock Source Selection
4
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#001
2
Clock source from HCLK
#010
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#011
4
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#100
5
Clock source from 4 MHz internal medium speed RC oscillator (MIRC)
#101
7
Clock source from USB SOF
#111
TMR0SEL
TIMER0 Clock Source Selection
8
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK0
#010
3
Clock source from external clock T0 pin
#011
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#111
TMR1SEL
TIMER1 Clock Source Selection
12
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK0
#010
3
Clock source from external clock T1 pin
#011
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#111
TMR2SEL
TIMER2 Clock Source Selection
16
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK1
#010
3
Clock source from external clock T2 pin
#011
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#111
TMR3SEL
TIMER3 Clock Source Selection
20
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK1
#010
3
Clock source from external clock T3 pin
#011
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#111
UART0SEL
UART0 Clock Source Selection
24
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK0
#100
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
UART1SEL
UART1 Clock Source Selection
28
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK1
#100
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
WDTSEL
Watchdog Timer Clock Source Selection (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: This bit is forced to 11 when CONFIG0[31] or CONFIG0[4] or CONFIG0[3] is 0.
0
2
read-write
0
Reserved.
#00
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#01
2
Clock source from HCLK/2048
#10
3
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#11
WWDTSEL
Window Watchdog Timer Clock Source Selection (Write Protect)
2
2
read-write
2
Clock source from HCLK/2048
#10
3
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#11
CLKSEL2
CLK_CLKSEL2
Clock Source Select Control Register 2
0x18
-1
read-write
n
0x0
0x0
SPI0SEL
SPI0 Clock Source Selection
4
2
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#00
1
Reserved.
#01
2
Clock source from PCLK1
#10
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#11
CLKSEL3
CLK_CLKSEL3
Clock Source Select Control Register 3
0x1C
-1
read-write
n
0x0
0x0
UART2SEL
UART2 Clock Source Selection
24
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK0
#100
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
UART3SEL
UART3 Clock Source Selection
28
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK1
#100
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
UART4SEL
UART4 Clock Source Selection
4
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK0
#100
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
HXTFSEL
CLK_HXTFSEL
HXT Filter Select Control Register
0xB4
-1
read-write
n
0x0
0x0
HXTFSEL
HXT Filter Select
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: This bit should not be changed during HXT running.
0
1
read-write
0
HXT frequency is greater than 12 MHz
#0
1
HXT frequency is less than or equal to 12 MHz
#1
PCLKDIV
CLK_PCLKDIV
APB Clock Divider Register
0x34
-1
read-write
n
0x0
0x0
APB0DIV
APB0 Clock DIvider
APB0 clock can be divided from HCLK
Others: Reserved.
0
3
read-write
APB1DIV
APB1 Clock DIvider
APB1 clock can be divided from HCLK
Others: Reserved.
4
3
read-write
PMUCTL
CLK_PMUCTL
Power Manager Control Register
0x90
-1
read-write
n
0x0
0x0
PDMSEL
Power-down Mode Selection (Write Protect)
This is a protected register. Please refer to open lock sequence to program it.
These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
3
read-write
0
Power-down mode is selected. (PD)
#000
2
fast wake up
#010
6
Deep Power-down mode is selected (DPD)
#110
PWRCTL
CLK_PWRCTL
System Power-down Control Register
0x0
-1
read-write
n
0x0
0x0
HIRCEN
HIRC Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
48 MHz internal high speed RC oscillator (HIRC) Disabled
#0
1
48 MHz internal high speed RC oscillator (HIRC) Enabled
#1
HXTEN
HXT Enable Bit (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by powr on reset.
0
1
read-write
0
4~32 MHz external high speed crystal (HXT) Disabled
#0
1
4~32 MHz external high speed crystal (HXT) Enabled
#1
HXTGAIN
HXT Gain Control Bit (Write Protect)
This is a protected register. Please refer to open lock sequence to program it.
Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off.
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by power on reset.
20
3
read-write
0
HXT frequency 1~4 MHz
#000
1
HXT frequency 4~8 MHz
#001
2
HXT frequency 8~12 MHz
#010
3
HXT frequency 12~ 16 MHz
#011
4
HXT frequency 16~24 MHz
#100
5
HXT frequency 24~32 MHz
#101
6
HXT frequency 24~32 MHz
#110
7
HXT frequency 24~32 MHz
#111
LIRCEN
LIRC Enable Bit (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: LIRC will also be forced on when 1. Power down and ~(CONFIG0[3] CONFIG0[4] ~CONFIG0[31] CONFIG0[30]) 2. Not power down and ~(CONFIG0[3] CONFIG0[4] CONFIG0[31])
3
1
read-write
0
38.4 kHz internal low speed RC oscillator (LIRC) Disabled
#0
1
38.4 kHz internal low speed RC oscillator (LIRC) Enabled
#1
LXTEN
LXT Enable Bit (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by RTC powr on reset.
1
1
read-write
0
32.768 kHz external low speed crystal (LXT) Disabled
#0
1
32.768 kHz external low speed crystal (LXT) Enabled
#1
MIRCEN
MIRC Enable Bit (Write Protect)
19
1
read-write
0
4 MHz internal high speed RC oscillator (MIRC) Disabled
#0
1
4 MHz internal high speed RC oscillator (MIRC) Enabled
#1
PDEN
System Power-down Enable (Write Protect)
When this bit is set to 1, Power-down mode is enabled, chip enters Power-down mode immediately after the PDEN bit set. When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.
In Power-down mode, HXT ,MIRC and HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.
In Power-down mode, the HCLK, PCLK0 and PCLK1 clocks are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
Chip operating normally or chip in idle mode because of WFI command
#0
1
Chip enters Power-down mode instantly or wait CPU sleep command WFI
#1
PDWKDLY
Enable the Wake-up Delay Counter (Write Protect)
When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip works at 4~32 MHz external high speed crystal oscillator (HXT),
The delayed clock cycle is 512 clock cycles when chip works at 48 MHz internal high speed RC oscillator (HIRC)
The delayed clock cycle is 32 clock cycles when chip works at 4 MHz internal median speed RC oscillator (MIRC)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
Clock cycles delay Disabled
#0
1
Clock cycles delay Enabled
#1
PDWKIEN
Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
Note 1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
Power-down mode wake-up interrupt Disabled
#0
1
Power-down mode wake-up interrupt Enabled
#1
PDWKIF
Power-down Mode Wake-up Interrupt Status
Set by 'Power-down wake-up event' indicates that resume from Power-down mode'
The flag is set if any wake-up source is occurred. Refer to Power Modes and Wake-up Sources section.
Note 1: Write 1 to clear the bit to 0.
Note 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) is set to 1.
6
1
read-write
STATUS
CLK_STATUS
Clock Status Monitor Register
0x50
-1
read-only
n
0x0
0x0
CLKSFAIL
Clock Switching Fail Flag
This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.
Note: Write 1 to clear the bit to 0.
7
1
read-only
0
Clock switching success
#0
1
Clock switching failure
#1
HIRCSTB
HIRC Clock Source Stable Flag (Read Only)
4
1
read-only
0
48 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled
#0
1
48 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled
#1
HXTSTB
HXT Clock Source Stable Flag (Read Only)
0
1
read-only
0
4~32 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled
#0
1
4~32 MHz external high speed crystal oscillator (HXT) clock is stable and enabled
#1
LIRCSTB
LIRC Clock Source Stable Flag (Read Only)
3
1
read-only
0
38.4 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled
#0
1
38.4 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled
#1
LXTSTB
LXT Clock Source Stable Flag (Read Only)
1
1
read-only
0
32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled
#0
1
32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled
#1
MIRCSTB
MIRC Clock Source Stable Flag (Read Only)
6
1
read-only
0
4 MHz internal mid speed RC oscillator (MIRC) clock is not stable or disabled
#0
1
4 MHz internal mid speed RC oscillator (MIRC) clock is stable and enabled
#1
CRC
CRC Register Map
CRC
0x0
0x0
0x10
registers
n
CHECKSUM
CRC_CHECKSUM
CRC Checksum Register
0xC
-1
read-only
n
0x0
0x0
CHECKSUM
CRC Checksum Results
This field indicates the CRC checksum result.
0
32
read-only
CTL
CRC_CTL
CRC Control Register
0x0
-1
read-write
n
0x0
0x0
CHKSFMT
Checksum 1's Complement
This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
27
1
read-write
0
1's complement for CRC checksum Disabled
#0
1
1's complement for CRC checksum Enabled
#1
CHKSINIT
Checksum Initialization
Note: This bit will be cleared automatically.
1
1
read-write
0
No effect
#0
1
Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value
#1
CHKSREV
Checksum Bit Order Reverse
This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
25
1
read-write
0
Bit order reverse for CRC checksum Disabled
#0
1
Bit order reverse for CRC checksum Enabled
#1
CRCEN
CRC Channel Enable Bit
0
1
read-write
0
No effect
#0
1
CRC operation Enabled
#1
CRCMODE
CRC Polynomial Mode
This field indicates the CRC operation polynomial mode.
30
2
read-write
0
CRC-CCITT Polynomial mode
#00
1
CRC-8 Polynomial mode
#01
2
CRC-16 Polynomial mode
#10
3
CRC-32 Polynomial mode
#11
DATFMT
Write Data 1's Complement
This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
26
1
read-write
0
1's complement for CRC writes data in Disabled
#0
1
1's complement for CRC writes data in Enabled
#1
DATLEN
CPU Write Data Length
This field indicates the write data length.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
28
2
read-write
0
Data length is 8-bit mode
#00
1
Data length is 16-bit mode.
Data length is 32-bit mode
#01
DATREV
Write Data Bit Order Reverse
This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
24
1
read-write
0
Bit order reversed for CRC write data in Disabled
#0
1
Bit order reversed for CRC write data in Enabled (per byte)
#1
DAT
CRC_DAT
CRC Write Data Register
0x4
-1
read-write
n
0x0
0x0
DATA
CRC Write Data Bits
User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
0
32
read-write
SEED
CRC_SEED
CRC Seed Register
0x8
-1
read-write
n
0x0
0x0
SEED
CRC Seed Value
This field indicates the CRC seed value.
Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
0
32
read-write
EADC
EADC Register Map
EADC
0x0
0x0
0x10
registers
n
0x110
0x4
registers
n
0x130
0x4
registers
n
0x140
0x10
registers
n
0x208
0x4
registers
n
0x40
0x8
registers
n
0x4C
0x14
registers
n
0x80
0x10
registers
n
0xC0
0x8
registers
n
0xD0
0x30
registers
n
CMP0
EADC_CMP0
ADC Result Compare Register 0
0xE0
-1
read-write
n
0x0
0x0
CMPCOND
Compare Condition
2
1
read-write
0
Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one
#0
1
Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one
#1
CMPDAT
Comparison Data
The 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
16
12
read-write
CMPMCNT
Compare Match Count
8
4
read-write
CMPSPL
Compare Sample Module Selection
3
5
read-write
0
Sample Module 0 conversion result EADC_DAT0 is selected to be compared
#00000
1
Sample Module 1 conversion result EADC_DAT1 is selected to be compared
#00001
2
Sample Module 2 conversion result EADC_DAT2 is selected to be compared
#00010
3
Sample Module 3 conversion result EADC_DAT3 is selected to be compared
#00011
4
Sample Module 4 conversion result EADC_DAT4 is selected to be compared
#00100
5
Sample Module 5 conversion result EADC_DAT5 is selected to be compared
#00101
6
Sample Module 6 conversion result EADC_DAT6 is selected to be compared
#00110
7
Sample Module 7 conversion result EADC_DAT7 is selected to be compared
#00111
8
Sample Module 8 conversion result EADC_DAT8 is selected to be compared
#01000
9
Sample Module 9 conversion result EADC_DAT9 is selected to be compared
#01001
10
Sample Module 10 conversion result EADC_DAT10 is selected to be compared
#01010
11
Sample Module 11 conversion result EADC_DAT11 is selected to be compared
#01011
12
Sample Module 12 conversion result EADC_DAT12 is selected to be compared
#01100
13
Sample Module 13 conversion result EADC_DAT13 is selected to be compared
#01101
14
Sample Module 14 conversion result EADC_DAT14 is selected to be compared
#01110
15
Sample Module 15 conversion result EADC_DAT15 is selected to be compared
#01111
16
Sample Module 16 conversion result EADC_DAT16 is selected to be compared
#10000
17
Sample Module 17 conversion result EADC_DAT17 is selected to be compared
#10001
18
Sample Module 18 conversion result EADC_DAT18 is selected to be compared
#10010
CMPWEN
Compare Window Mode Enable Bit
Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
15
1
read-write
0
EADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched. EADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched
#0
1
EADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. EADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched
#1
EADCMPEN
ADC Result Compare Enable Bit
0
1
read-write
0
Compare Disabled
#0
1
Compare Enabled
#1
EADCMPIE
ADC Result Compare Interrupt Enable Bit
1
1
read-write
0
Compare function interrupt Disabled
#0
1
Compare function interrupt Enabled
#1
CMP1
EADC_CMP1
ADC Result Compare Register 1
0xE4
-1
read-write
n
0x0
0x0
CMP2
EADC_CMP2
ADC Result Compare Register 2
0xE8
-1
read-write
n
0x0
0x0
CMP3
EADC_CMP3
ADC Result Compare Register 3
0xEC
-1
read-write
n
0x0
0x0
CTL
EADC_CTL
ADC Control Register
0x50
-1
read-write
n
0x0
0x0
EADCEN
ADC Converter Enable Bit
Note: Before starting ADC conversion function, this bit should be set to 1. Clear it to 0 to disable ADC converter analog circuit power consumption.
0
1
read-write
0
Disabled EADC
#0
1
Enabled EADC
#1
EADCIEN0
Specific Sample Module ADC ADINT0 Interrupt Enable Bit
The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion. If EADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
2
1
read-write
0
Specific sample module ADC ADINT0 interrupt function Disabled
#0
1
Specific sample module ADC ADINT0 interrupt function Enabled
#1
EADCIEN1
Specific Sample Module ADC ADINT1 Interrupt Enable Bit
The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion. If EADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
3
1
read-write
0
Specific sample module ADC ADINT1 interrupt function Disabled
#0
1
Specific sample module ADC ADINT1 interrupt function Enabled
#1
EADCIEN2
Specific Sample Module ADC ADINT2 Interrupt Enable Bit
The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion. If EADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
4
1
read-write
0
Specific sample module ADC ADINT2 interrupt function Disabled
#0
1
Specific sample module ADC ADINT2 interrupt function Enabled
#1
EADCIEN3
Specific Sample Module ADC ADINT3 Interrupt Enable Bit
The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion. If EADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
5
1
read-write
0
Specific sample module ADC ADINT3 interrupt function Disabled
#0
1
Specific sample module ADC ADINT3 interrupt function Enabled
#1
EADCRST
EADC ADC Converter Control Circuits Reset
Note: EADCRST bit remains 1 during EADC reset. When EADC reset end, the EADCRST bit is automatically cleared to 0.
1
1
read-write
0
No effect
#0
1
Cause EADC control circuits reset to initial state, but not change the EADC registers value
#1
CURDAT
EADC_CURDAT
EADC PDMA Current Transfer Data Register
0x4C
-1
read-only
n
0x0
0x0
CURDAT
EADC PDMA Current Transfer Data (Read Only)
Note: After PDMA reads this register, the VAILD of the shadow EADC_DAT register will be automatically cleared.
0
19
read-only
DAT0
EADC_DAT0
ADC Data Register 0 for Sample Module 0
0x0
-1
read-only
n
0x0
0x0
OV
Overrun Flag
If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
Note: It is cleared by hardware after EADC_DAT register is read.
16
1
read-only
0
Data in RESULT[11:0] is recent conversion result
#0
1
Data in RESULT[11:0] is overwrite
#1
RESULT
ADC Conversion Result
This field contains 12 bits conversion result.
0
16
read-only
VALID
Valid Flag
This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
17
1
read-only
0
Data in RESULT[11:0] bits is not valid
#0
1
Data in RESULT[11:0] bits is valid
#1
DAT1
EADC_DAT1
ADC Data Register 1 for Sample Module 1
0x4
-1
read-write
n
0x0
0x0
DAT16
EADC_DAT16
ADC Data Register 16 for Sample Module 16
0x40
-1
read-write
n
0x0
0x0
DAT17
EADC_DAT17
ADC Data Register 17 for Sample Module 17
0x44
-1
read-write
n
0x0
0x0
DAT2
EADC_DAT2
ADC Data Register 2 for Sample Module 2
0x8
-1
read-write
n
0x0
0x0
DAT3
EADC_DAT3
ADC Data Register 3 for Sample Module 3
0xC
-1
read-write
n
0x0
0x0
INTSRC0
EADC_INTSRC0
EADC Interrupt 0 Source Enable Control Register.
0xD0
-1
read-write
n
0x0
0x0
SPLIE0
Sample Module 0 Interrupt Enable Bit
0
1
read-write
0
Sample Module 0 interrupt Disabled
#0
1
Sample Module 0 interrupt Enabled
#1
SPLIE1
Sample Module 1 Interrupt Enable Bit
1
1
read-write
0
Sample Module 1 interrupt Disabled
#0
1
Sample Module 1 interrupt Enabled
#1
SPLIE2
Sample Module 2 Interrupt Enable Bit
2
1
read-write
0
Sample Module 2 interrupt Disabled
#0
1
Sample Module 2 interrupt Enabled
#1
SPLIE3
Sample Module 3 Interrupt Enable Bit
3
1
read-write
0
Sample Module 3 interrupt Disabled
#0
1
Sample Module 3 interrupt Enabled
#1
INTSRC1
EADC_INTSRC1
EADC Interrupt 1 Source Enable Control Register.
0xD4
-1
read-write
n
0x0
0x0
INTSRC2
EADC_INTSRC2
EADC Interrupt 2 Source Enable Control Register.
0xD8
-1
read-write
n
0x0
0x0
INTSRC3
EADC_INTSRC3
EADC Interrupt 3 Source Enable Control Register.
0xDC
-1
read-write
n
0x0
0x0
M0CTL1
EADC_M0CTL1
EADC Sample Module0 Control Register 1
0x140
-1
read-write
n
0x0
0x0
ACU
Number of Accumulated Conversion Results Selection
4
4
read-write
0
1 conversion result will be accumulated
#0000
1
2 conversion result will be accumulated
#0001
2
4 conversion result will be accumulated
#0010
3
8 conversion result will be accumulated
#0011
4
16 conversion result will be accumulated
#0100
5
32 conversion result will be accumulated
#0101
6
64 conversion result will be accumulated
#0110
7
128 conversion result will be accumulated
#0111
8
256 conversion result will be accumulated
#1000
ALIGN
Alignment Selection
0
1
read-write
0
The conversion result will be right aligned in data register
#0
1
The conversion result will be left aligned in data register
#1
AVG
Average Mode Selection
1
1
read-write
0
Conversion results will be stored in data register without averaging
#0
1
Conversion results in data register will be averaged
#1
M1CTL1
EADC_M1CTL1
EADC Sample Module1 Control Register 1
0x144
-1
read-write
n
0x0
0x0
M2CTL1
EADC_M2CTL1
EADC Sample Module2 Control Register 1
0x148
-1
read-write
n
0x0
0x0
M3CTL1
EADC_M3CTL1
EADC Sample Module3 Control Register 1
0x14C
-1
read-write
n
0x0
0x0
OFFSETCAL
EADC_OFFSETCAL
ADC Result Offset Cancellation Register
0x208
-1
read-write
n
0x0
0x0
OFFSETCANCEL
ADC Offset Cancellation Trim Bits
When CALEN(EADC_CTL[8]) is set to 1, the offset cancellation trim bits will compensate ADC result offset. When this bit is set to 0, the offset cancellation trim bits have no effect to ADC result.
Note 1: These 5 bits trim value wouldn't latched into EADC_OFFSETCAL automatically when Flash initialization. User must read DCR2 by ISP command first, then write the value to OFFSETCANCEL.
Note 2: OFFSETCANCEL is signed format. OFFSETCANCEL will sign extension to 12 bit by hardware to perform signed addition with EADC conversion result if CALEN is enabled.
0
5
read-write
OVSTS
EADC_OVSTS
ADC Sample Module Start of Conversion Overrun Flag Register
0x5C
-1
read-write
n
0x0
0x0
INTSPOVF
ADC SAMPLE16,17 Overrun Flag
Note: This bit is cleared by writing 1 to it.
16
2
read-write
0
No sample module event overrun
0
1
Indicates a new sample module event is generated while an old one event is pending
1
SPOVF
ADC SAMPLE0~3 Overrun Flag
Note: This bit is cleared by writing 1 to it.
0
4
read-write
0
No sample module event overrun
0
1
Indicates a new sample module event is generated while an old one event is pending
1
PDMACTL
EADC_PDMACTL
EADC PDMA Control Register
0x130
-1
read-write
n
0x0
0x0
INTPDMATEN
PDMA Transfer Enable Bit for Internal Channel
When EADC conversion is completed, the converted data is loaded into EADC_DATn (n:17, 16) register, user can enable this bit to generate a PDMA data transfer request.
16
2
read-write
0
PDMA data transfer Disabled
0
1
PDMA data transfer Enabled
1
PDMATEN
PDMA Transfer Enable Bit for External Channel
When EADC conversion is completed, the converted data is loaded into EADC_DATn (n:0 ~ 3) register, user can enable this bit to generate a PDMA data transfer request.
0
4
read-write
0
PDMA data transfer Disabled
0
1
PDMA data transfer Enabled
1
PENDSTS
EADC_PENDSTS
ADC Sample Module Start of Conversion Pending Flag Register
0x58
-1
read-write
n
0x0
0x0
INTSTPF
ADC Sample Module 17, 16 Start of Conversion Pending Flag
Read Operation:
16
2
read-write
0
There is no pending conversion for sample module
0
1
Sample module EADC start of conversion is pending.
Clear pending flag and stop conversion for corresponding sample module
1
STPF
ADC Sample Module 0~3 Start of Conversion Pending Flag
Read Operation:
0
4
read-write
0
There is no pending conversion for sample module
0
1
Sample module EADC start of conversion is pending.
Clear pending flag and stop conversion for corresponding sample module
1
PWRCTL
EADC_PWRCTL
EADC Power Management Control Register
0x110
-1
read-write
n
0x0
0x0
AUTOFF
Auto Off Mode
5
1
read-write
0
Auto off function Disabled
#0
1
Auto off function Enabled. When AUTOFF is set to 1, EADC will be powered off automatically to save power
#1
AUTOPDTHT
Auto Power Down Threshold Time
20
4
read-write
7
8 EADC clock for power down threshold time
#0111
8
16 EADC clock for power down threshold time
#1000
9
32 EADC clock for power down threshold time
#1001
10
64 EADC clock for power down threshold time
#1010
11
128 EADC clock for power down threshold time
#1011
12
256 EADC clock for power down threshold time
#1100
READY
EADC Start-up Completely and Ready for Conversion (Read Only)
0
1
read-only
0
Power-on sequence is still in progress
#0
1
EADC is ready for conversion
#1
STUPT
EADC Start-up Time
Set this bit fields to adjust start-up time. The minimum start-up time of EADC is 10us.
8
12
read-write
SCTL0
EADC_SCTL0
ADC Sample Module 0 Control Register
0x80
-1
read-write
n
0x0
0x0
CHSEL
ADC Sample Module Channel Selection
.
0
4
read-write
EXTFEN
ADC External Trigger Falling Edge Enable Bit
5
1
read-write
0
Falling edge Disabled when ADC selects EADC0_ST as trigger source
#0
1
Falling edge Enabled when ADC selects EADC0_ST as trigger source
#1
EXTREN
ADC External Trigger Rising Edge Enable Bit
4
1
read-write
0
Rising edge Disabled when ADC selects EADC0_ST as trigger source
#0
1
Rising edge Enabled when ADC selects EADC0_ST as trigger source
#1
EXTSMPT
EADC Sampling Time Extend
When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time. EXTSMPT can be set from 0~8'd251.
24
8
read-write
INTPOS
Interrupt Flag Position Select
22
1
read-write
0
Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion
#0
1
Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion
#1
TRGDLYCNT
ADC Sample Module Start of Conversion Trigger Delay Time
Note: If TRGDLYCNT is set to 1, trigger delay time is actually the same as TRGDLYCNT is set to 2 for hardware operation.
8
8
read-write
TRGDLYDIV
ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection
Trigger delay clock frequency:
6
2
read-write
0
EADC_CLK/1
#00
1
EADC_CLK/2
#01
2
EADC_CLK/4
#10
3
EADC_CLK/16
#11
TRGSEL
ADC Sample Module Start of Conversion Trigger Source Selection
16
5
read-write
SCTL1
EADC_SCTL1
ADC Sample Module 1 Control Register
0x84
-1
read-write
n
0x0
0x0
SCTL16
EADC_SCTL16
ADC Sample Module 16 Control Register
0xC0
-1
read-write
n
0x0
0x0
EXTSMPT
EADC Sampling Time Extend
When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend ADC sampling time after trigger source is coming to get enough sampling time. EXTSMPT can be set from 0~8'd255.
The range of start delay time is from 0~255 EADC clock.
24
8
read-write
SCTL17
EADC_SCTL17
ADC Sample Module 17 Control Register
0xC4
-1
read-write
n
0x0
0x0
SCTL2
EADC_SCTL2
ADC Sample Module 2 Control Register
0x88
-1
read-write
n
0x0
0x0
SCTL3
EADC_SCTL3
ADC Sample Module 3 Control Register
0x8C
-1
read-write
n
0x0
0x0
STATUS0
EADC_STATUS0
ADC Status Register 0
0xF0
-1
read-only
n
0x0
0x0
OV
EADC_DAT0~3 Overrun Flag
16
4
read-only
VALID
EADC_DAT0~3 Data Valid Flag
0
4
read-only
STATUS1
EADC_STATUS1
ADC Status Register 1
0xF4
-1
read-only
n
0x0
0x0
OV
EADC_DAT16~18 Overrun Flag
16
2
read-only
VALID
EADC_DAT16~17 Data Valid Flag
0
3
read-only
STATUS2
EADC_STATUS2
ADC Status Register 2
0xF8
-1
read-write
n
0x0
0x0
ADIF0
ADC ADINT0 Interrupt Flag
Note 1: This bit is cleared by writing 1 to it.
Note 2:This bit indicates whether an ADC conversion of specific sample module has been completed
0
1
read-write
0
No ADINT0 interrupt pulse received
#0
1
ADINT0 interrupt pulse has been received
#1
ADIF1
ADC ADINT1 Interrupt Flag
Note 1: This bit is cleared by writing 1 to it.
Note 2:This bit indicates whether an ADC conversion of specific sample module has been completed
1
1
read-write
0
No ADINT1 interrupt pulse received
#0
1
ADINT1 interrupt pulse has been received
#1
ADIF2
ADC ADINT2 Interrupt Flag
Note 1: This bit is cleared by writing 1 to it.
Note 2:This bit indicates whether an ADC conversion of specific sample module has been completed
2
1
read-write
0
No ADINT2 interrupt pulse received
#0
1
ADINT2 interrupt pulse has been received
#1
ADIF3
ADC ADINT3 Interrupt Flag
Note 1: This bit is cleared by writing 1 to it.
Note 2:This bit indicates whether an ADC conversion of specific sample module has been completed
3
1
read-write
0
No ADINT3 interrupt pulse received
#0
1
ADINT3 interrupt pulse has been received
#1
ADOVIF
All ADC Interrupt Flag Overrun Bits Check
Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
24
1
read-write
0
None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1
#0
1
Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1
#1
ADOVIF0
ADC ADINT0 Interrupt Flag Overrun
Note: This bit is cleared by writing 1 to it.
8
1
read-write
0
ADINT0 interrupt flag is not overwritten to 1
#0
1
ADINT0 interrupt flag is overwritten to 1
#1
ADOVIF1
ADC ADINT1 Interrupt Flag Overrun
Note: This bit is cleared by writing 1 to it.
9
1
read-write
0
ADINT1 interrupt flag is not overwritten to 1
#0
1
ADINT1 interrupt flag is overwritten to 1
#1
ADOVIF2
ADC ADINT2 Interrupt Flag Overrun
Note: This bit is cleared by writing 1 to it.
10
1
read-write
0
ADINT2 interrupt flag is not overwritten to 1
#0
1
ADINT2 interrupt flag is overwritten to 1
#1
ADOVIF3
ADC ADINT3 Interrupt Flag Overrun
Note: This bit is cleared by writing 1 to it.
11
1
read-write
0
ADINT3 interrupt flag is not overwritten to 1
#0
1
ADINT3 interrupt flag is overwritten to 1
#1
AOV
All Sample Module ADC Result Data Register Overrun Flags Check
Note: This bit will keep 1 when any OVn Flag is equal to 1.
27
1
read-write
0
None of sample module data register overrun flag OV (EADC_DATn[16]) is set to 1
#0
1
Any one of sample module data register overrun flag OV (EADC_DATn[16]) is set to 1
#1
AVALID
All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check
Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
26
1
read-write
0
None of sample module data register valid flag VALID (EADC_DATn[17]) is set to 1
#0
1
Any one of sample module data register valid flag VALID (EADC_DATn[17]) is set to 1
#1
BUSY
ADC Converter Busy/Idle Status (Read Only)
Note: Once a trigger source is coming, this bit must wait 2 EADC_CLK synchronization then the BUSY status will be high. The status will be high to low when the current conversion is finished.
23
1
read-only
0
EADC is in idle state
#0
1
EADC is busy for sample or conversion
#1
CHANNEL
Current Conversion Channel (Read Only)
16
5
read-only
EADCMPF0
EADC Compare 0 Flag
When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
Note: This bit is cleared by writing 1 to it.
4
1
read-write
0
Conversion result in EADC_DAT does not meet EADC_CMP0 register setting
#0
1
Conversion result in EADC_DAT meets EADC_CMP0 register setting
#1
EADCMPF1
EADC Compare 1 Flag
When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
Note: This bit is cleared by writing 1 to it.
5
1
read-write
0
Conversion result in EADC_DAT does not meet EADC_CMP1 register setting
#0
1
Conversion result in EADC_DAT meets EADC_CMP1 register setting
#1
EADCMPF2
EADC Compare 2 Flag
When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.
Note: This bit is cleared by writing 1 to it.
6
1
read-write
0
Conversion result in EADC_DAT does not meet EADC_CMP2 register setting
#0
1
Conversion result in EADC_DAT meets EADC_CMP2 register setting
#1
EADCMPF3
EADC Compare 3 Flag
When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.
Note: This bit is cleared by writing 1 to it.
7
1
read-write
0
Conversion result in EADC_DAT does not meet EADC_CMP3 register setting
#0
1
Conversion result in EADC_DAT meets EADC_CMP3 register setting
#1
EADCMPO0
EADC Compare 0 Output Status
The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
12
1
read-write
0
Conversion result in EADC_DAT is less than CMPDAT0 setting
#0
1
Conversion result in EADC_DAT is greater than or equal to CMPDAT0 setting
#1
EADCMPO1
EADC Compare 1 Output Status
The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
13
1
read-write
0
Conversion result in EADC_DAT is less than CMPDAT1 setting
#0
1
Conversion result in EADC_DAT is greater than or equal to CMPDAT1 setting
#1
EADCMPO2
EADC Compare 2 Output Status
The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
14
1
read-write
0
Conversion result in EADC_DAT is less than CMPDAT2 setting
#0
1
Conversion result in EADC_DAT is greater than or equal to CMPDAT2 setting
#1
EADCMPO3
EADC Compare 3 Output Status
The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
15
1
read-write
0
Conversion result in EADC_DAT is less than CMPDAT3 setting
#0
1
Conversion result in EADC_DAT is greater than or equal to CMPDAT3 setting
#1
STOVF
All ADC Sample Module Start of Conversion Overrun Flags Check
Note: This bit will keep 1 when any SPOVFn or INTSPOVFn Flag is equal to 1.
25
1
read-write
0
None of sample module event overrun flag SPOVF (EADC_OVSTS[n], n=0~3), INTSPOVF (EADC_OVSTS[n], n=16,17) is set to 1
#0
1
Any one of sample module event overrun flag SPOVF (EADC_OVSTS[n]) is set to 1
#1
STATUS3
EADC_STATUS3
ADC Status Register 3
0xFC
-1
read-only
n
0x0
0x0
CURSPL
EADC Current Sample Module (Read Only)
This register shows the current EADC is controlled by which sample module control logic modules.
If the EADC is Idle, the bit filed will be set to 0x1F.
0
5
read-only
SWTRG
EADC_SWTRG
ADC Sample Module Software Start Register
0x54
-1
write-only
n
0x0
0x0
INTSWTRG
ADC Sample Module 16,17 Software Force to Start EADC Conversion
Note: INTSWTRG is only for internal channels. After writing this register to start EADC conversion, the EADC_PENDSTS register will show which sample module will conversion. If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
16
2
write-only
0
No effect
0
1
Cause an EADC conversion when the priority is given to sample module
1
SWTRG
ADC Sample Module 0~3, Sample Module 16,17 Software Force to Start EADC Conversion
Note: After writing this register to start EADC conversion, the EADC_PENDSTS register will show which sample module will conversion. If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
0
4
write-only
0
No effect
0
1
Cause an EADC conversion when the priority is given to sample module
1
FMC
FMC Register Map
FMC
0x0
0x0
0x14
registers
n
0x18
0x4
registers
n
0x40
0x4
registers
n
0x4C
0x4
registers
n
0x80
0x10
registers
n
0xC0
0x8
registers
n
0xD0
0x8
registers
n
0xE0
0x4
registers
n
CYCCTL
FMC_CYCCTL
Flash Access Cycle Control Register
0x4C
-1
read-write
n
0x0
0x0
CYCLE
Flash Access Cycle Control (Write Protect)
The optimized HCLK working frequency range is 33~50 MHz
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
4
read-write
1
CPU access with zero wait cycle if cache hit or cache is disabled Flash access cycle is 1
#0001
2
CPU access with one wait cycles if cache miss Flash access cycle is 2
#0010
3
CPU access with two wait cycles if cahce miss Flash access cycle is 3
#0011
FTCTL
FMC_FTCTL
Flash Access Time Control Register
0x18
-1
read-write
n
0x0
0x0
CACHEINV
Flash Cache Invalidation (Write Protect)
Note 1: Write 1 to start cache invalidation. The value will be changed to 0 once the process finishes.
Note 2: This bit is write-protected. Refer to the SYS_REGLCTL register.
9
1
read-write
0
Flash Cache Invalidation finished (default)
#0
1
Flash Cache Invalidation
#1
ISPADDR
FMC_ISPADDR
ISP Address Register
0x4
-1
read-write
n
0x0
0x0
ISPADDR
ISP Address
The NuMicro M23 series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
For Checksum Calculation command, this field is the Flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation.
0
32
read-write
ISPCMD
FMC_ISPCMD
ISP Command Register
0xC
-1
read-write
n
0x0
0x0
CMD
ISP Command
ISP command table is shown below:
The other commands are invalid.
0
7
read-write
0
FLASH Read
0x00
4
Read Unique ID
0x04
11
Read Company ID
0x0b
12
Read Device ID
0x0c
13
Read Checksum
0x0d
33
FLASH 32-bit Program
0x21
34
FLASH Page Erase
0x22
39
FLASH Multi-Word Program
0x27
40
Run Flash All-One Verification
0x28
45
Run Checksum Calculation
0x2d
46
Vector Remap
0x2e
ISPCTL
FMC_ISPCTL
ISP Control Register
0x0
-1
read-write
n
0x0
0x0
APUEN
APROM Update Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
3
1
read-write
0
APROM cannot be updated when the chip runs in APROM
#0
1
APROM can be updated when the chip runs in APROM
#1
BS
Boot Select (Write Protect)
/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset or system reset is happened
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
Booting from APROM
#0
1
Booting from LDROM
#1
CFGUEN
CONFIG Update Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
CONFIG cannot be updated
#0
1
CONFIG can be updated
#1
ISPEN
ISP Enable Bit (Write Protect)
ISP function enable bit. Set this bit to enable ISP function.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
ISP function Disabled
#0
1
ISP function Enabled
#1
ISPFF
ISP Fail Flag (Write Protect)
This bit is set by hardware when a triggered ISP meets any of the following conditions:
This bit needs to be cleared by writing 1 to it.
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) Page Erase command at LOCK mode with ICE connection
(5) Erase or Program command at brown-out detected
(6) Destination address is illegal, such as over an available range.
(7) Invalid ISP commands
(8) ISP CMD in XOM region, except mass erase, page erase and chksum command
(9) The wrong setting of page erase ISP CMD in XOM
(10) Violate XOM setting one time protection
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
LDUEN
LDROM Update Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated
#1
ISPDAT
FMC_ISPDAT
ISP Data Register
0x8
-1
read-write
n
0x0
0x0
ISPDAT
ISP Data
Write data to this register before ISP program operation.
Read data from this register after ISP read operation.
0
32
read-write
ISPSTS
FMC_ISPSTS
ISP Status Register
0x40
-1
read-write
n
0x0
0x0
ALLONE
Flash All-one Verification Flag
This bit is set by hardware if all of Flash bits are 1, and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete this bit also can be clear by writing 1
7
1
read-write
0
Flash bits are not all 1 after 'Run Flash All-One Verification' complete
#0
1
All of Flash bits are 1 after 'Run Flash All-One Verification' complete
#1
CBS
Boot Selection of CONFIG (Read Only)
This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset or system reset is happened.
1
2
read-only
0
LDROM with IAP mode
#00
1
LDROM without IAP mode
#01
2
APROM with IAP mode
#10
3
APROM without IAP mode
#11
ISPBUSY
ISP Busy Flag (Read Only)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
0
1
read-only
0
ISP operation is finished
#0
1
ISP is progressed
#1
ISPFF
ISP Fail Flag (Write Protect)
This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) Page Erase command at LOCK mode with ICE connection
(5) Erase or Program command at brown-out detected
(6) Destination address is illegal, such as over an available range.
(7) Invalid ISP commands
(8) ISP CMD in XOM region, except mass erase, page erase and chksum command
(9) The wrong setting of page erase ISP CMD in XOM
(10) Violate XOM setting one time protection
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
6
1
read-write
PGFF
Flash Program with Fast Verification Flag (Read Only)
This bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP Flash erase or ISP read CID operation
5
1
read-only
0
Flash Program is success
#0
1
Flash Program is fail. Program data is different with data in the Flash memory
#1
VECMAP
Vector Page Mapping Address (Read Only)
All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}.
VECMAP [18:12] should be 0.
9
21
read-only
ISPTRG
FMC_ISPTRG
ISP Trigger Control Register
0x10
-1
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger (Write Protect)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
ISP operation is finished
#0
1
ISP is progressed
#1
MPADDR
FMC_MPADDR
ISP Multi-program Address Register
0xC4
-1
read-only
n
0x0
0x0
MPADDR
ISP Multi-word Program Address
MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
MPADDR will keep the final ISP address when ISP multi-word program is complete.
0
32
read-only
MPDAT0
FMC_MPDAT0
ISP Data0 Register
0x80
-1
read-write
n
0x0
0x0
ISPDAT0
ISP Data 0
This register is the first 32-bit data for 32-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data.
0
32
read-write
MPDAT1
FMC_MPDAT1
ISP Data1 Register
0x84
-1
read-write
n
0x0
0x0
ISPDAT1
ISP Data 1
This register is the second 32-bit data for multi-word programming.
0
32
read-write
MPDAT2
FMC_MPDAT2
ISP Data2 Register
0x88
-1
read-write
n
0x0
0x0
ISPDAT2
ISP Data 2
This register is the third 32-bit data for multi-word programming.
0
32
read-write
MPDAT3
FMC_MPDAT3
ISP Data3 Register
0x8C
-1
read-write
n
0x0
0x0
ISPDAT3
ISP Data 3
This register is the fourth 32-bit data for multi-word programming.
0
32
read-write
MPSTS
FMC_MPSTS
ISP Multi-program Status Register
0xC0
-1
read-only
n
0x0
0x0
D0
ISP DATA 0 Flag (Read Only)
This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete.
4
1
read-only
0
FMC_MPDAT0 register is empty, or program to Flash complete
#0
1
FMC_MPDAT0 register has been written, and not program to Flash complete
#1
D1
ISP DATA 1 Flag (Read Only)
This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete.
5
1
read-only
0
FMC_MPDAT1 register is empty, or program to Flash complete
#0
1
FMC_MPDAT1 register has been written, and not program to Flash complete
#1
D2
ISP DATA 2 Flag (Read Only)
This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete.
6
1
read-only
0
FMC_MPDAT2 register is empty, or program to Flash complete
#0
1
FMC_MPDAT2 register has been written, and not program to Flash complete
#1
D3
ISP DATA 3 Flag (Read Only)
This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete.
7
1
read-only
0
FMC_MPDAT3 register is empty, or program to Flash complete
#0
1
FMC_MPDAT3 register has been written, and not program to Flash complete
#1
ISPFF
ISP Fail Flag (Read Only)
This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) Page Erase command at LOCK mode with ICE connection
(5) Erase or Program command at brown-out detected
(6) Destination address is illegal, such as over an available range.
(7) Invalid ISP commands.
2
1
read-only
MPBUSY
ISP Multi-word Program Busy Flag (Read Only)
Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
0
1
read-only
0
ISP Multi-Word program operation is finished
#0
1
ISP Multi-Word program operation is progressed
#1
PPGO
ISP Multi-program Status (Read Only)
1
1
read-only
0
ISP multi-word program operation is not active
#0
1
ISP multi-word program operation is in progress
#1
XOMR0STS0
FMC_XOMR0STS0
XOM Region 0 Status Register 0
0xD0
-1
read-only
n
0x0
0x0
BASE
XOM Region 0 Base Address (Page-aligned)
BASE is the base address of XOM Region 0.
0
24
read-only
XOMR0STS1
FMC_XOMR0STS1
XOM Region 0 Status Register 1
0xD4
-1
read-only
n
0x0
0x0
SIZE
XOM Region 0 Size Page-aligned)
SIZE is the page number of XOM Region 0.
0
9
read-only
XOMSTS
FMC_XOMSTS
XOM Status Register
0xE0
-1
read-only
n
0x0
0x0
XOMPEF
XOM Page Erase Function Fail
XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.
4
1
read-only
0
Success
#0
1
Fail
#1
XOMR0ON
XOM Region 0 On
XOM Region 0 active status.
0
1
read-only
0
No active
#0
1
XOM region 0 is active
#1
GPIO
GPIO Register Map
GPIO
0x0
0x0
0x2C
registers
n
0x140
0x2C
registers
n
0x170
0x4
registers
n
0x30
0x4
registers
n
0x40
0x2C
registers
n
0x440
0x4
registers
n
0x70
0x4
registers
n
0x80
0x2C
registers
n
0x800
0x30
registers
n
0x840
0x20
registers
n
0x870
0x28
registers
n
0x8B8
0x4
registers
n
0x940
0x18
registers
n
0x97C
0x4
registers
n
0xB0
0x4
registers
n
DBCTL
GPIO_DBCTL
Interrupt De-bounce Control Register
0x440
-1
read-write
n
0x0
0x0
DBCLKSEL
De-bounce Sampling Cycle Selection
0
4
read-write
0
Sample interrupt input once per 1 clocks
#0000
1
Sample interrupt input once per 2 clocks
#0001
2
Sample interrupt input once per 4 clocks
#0010
3
Sample interrupt input once per 8 clocks
#0011
4
Sample interrupt input once per 16 clocks
#0100
5
Sample interrupt input once per 32 clocks
#0101
6
Sample interrupt input once per 64 clocks
#0110
7
Sample interrupt input once per 128 clocks
#0111
8
Sample interrupt input once per 256 clocks
#1000
9
Sample interrupt input once per 2*256 clocks
#1001
10
Sample interrupt input once per 4*256 clocks
#1010
11
Sample interrupt input once per 8*256 clocks
#1011
12
Sample interrupt input once per 16*256 clocks
#1100
13
Sample interrupt input once per 32*256 clocks
#1101
14
Sample interrupt input once per 64*256 clocks
#1110
15
Sample interrupt input once per 128*256 clocks
#1111
DBCLKSRC
De-bounce Counter Clock Source Selection
4
1
read-write
0
De-bounce counter clock source is the HCLK
#0
1
De-bounce counter clock source is the 38.4 kHz internal low speed RC oscillator (LIRC)
#1
ICLKONx
Interrupt Clock on Mode
Note: It is recommended to disable this bit to save system power if no special application concern. Each bit controls each GPIO group.
16
6
read-write
0
Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1
0
1
All I/O pins edge detection circuit is always active after reset
1
PA0_PDIO
PA0_PDIO
GPIO PA.n Pin Data Input/Output Register
0x800
-1
read-write
n
0x0
0x0
PDIO
GPIO Px.n Pin Data Input/Output
Writing this bit can control one GPIO pin output value.
Read this register to get GPIO pin status.
For example, writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return the value of PIN (PA_PIN[0]).
Note 1: The writing operation will not be affected by register DATMSK (Px_DATMSK[n]).
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
0
1
read-write
0
Corresponding GPIO pin set to low
#0
1
Corresponding GPIO pin set to high
#1
PA10_PDIO
PA10_PDIO
GPIO PA.n Pin Data Input/Output Register
0x828
-1
read-write
n
0x0
0x0
PA11_PDIO
PA11_PDIO
GPIO PA.n Pin Data Input/Output Register
0x82C
-1
read-write
n
0x0
0x0
PA1_PDIO
PA1_PDIO
GPIO PA.n Pin Data Input/Output Register
0x804
-1
read-write
n
0x0
0x0
PA2_PDIO
PA2_PDIO
GPIO PA.n Pin Data Input/Output Register
0x808
-1
read-write
n
0x0
0x0
PA3_PDIO
PA3_PDIO
GPIO PA.n Pin Data Input/Output Register
0x80C
-1
read-write
n
0x0
0x0
PA4_PDIO
PA4_PDIO
GPIO PA.n Pin Data Input/Output Register
0x810
-1
read-write
n
0x0
0x0
PA5_PDIO
PA5_PDIO
GPIO PA.n Pin Data Input/Output Register
0x814
-1
read-write
n
0x0
0x0
PA6_PDIO
PA6_PDIO
GPIO PA.n Pin Data Input/Output Register
0x818
-1
read-write
n
0x0
0x0
PA7_PDIO
PA7_PDIO
GPIO PA.n Pin Data Input/Output Register
0x81C
-1
read-write
n
0x0
0x0
PA8_PDIO
PA8_PDIO
GPIO PA.n Pin Data Input/Output Register
0x820
-1
read-write
n
0x0
0x0
PA9_PDIO
PA9_PDIO
GPIO PA.n Pin Data Input/Output Register
0x824
-1
read-write
n
0x0
0x0
PA_DATMSK
PA_DATMSK
PA Data Output Write Mask
0xC
-1
read-write
n
0x0
0x0
DATMSK0
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
0
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK1
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
1
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK10
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
10
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK11
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
11
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK12
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
12
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK13
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
13
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK14
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
14
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK15
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
15
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK2
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
2
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK3
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
3
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK4
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
4
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK5
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
5
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK6
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
6
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK7
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
7
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK8
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
8
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK9
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
9
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
PA_DBEN
PA_DBEN
PA De-bounce Enable Control Register
0x14
-1
read-write
n
0x0
0x0
DBEN0
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
0
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN1
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
1
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN10
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
10
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN11
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
11
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN12
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
12
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN13
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
13
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN14
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
14
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN15
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
15
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN2
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
2
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN3
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
3
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN4
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
4
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN5
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
5
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN6
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
6
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN7
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
7
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN8
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
8
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN9
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
9
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
PA_DINOFF
PA_DINOFF
PA Digital Input Path Disable Control
0x4
-1
read-write
n
0x0
0x0
DINOFF0
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
16
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF1
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
17
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF10
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
26
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF11
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
27
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF12
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
28
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF13
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
29
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF14
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
30
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF15
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
31
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF2
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
18
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF3
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
19
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF4
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
20
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF5
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
21
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF6
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
22
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF7
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
23
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF8
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
24
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF9
Port A-F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
25
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
PA_DOUT
PA_DOUT
PA Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
0
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
1
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT10
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
10
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT11
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
11
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT12
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
12
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT13
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
13
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT14
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
14
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT15
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
15
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
2
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
3
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
4
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
5
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
6
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
7
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT8
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
8
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT9
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
9
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
PA_INTEN
PA_INTEN
PA Interrupt Enable Control Register
0x1C
-1
read-write
n
0x0
0x0
FLIEN0
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
0
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN1
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
1
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN10
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
10
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN11
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
11
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN12
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
12
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN13
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
13
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN14
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
14
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN15
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
15
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN2
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
2
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN3
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
3
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN4
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
4
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN5
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
5
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN6
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
6
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN7
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
7
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN8
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
8
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN9
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
9
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
RHIEN0
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
16
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN1
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
17
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN10
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
26
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN11
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
27
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN12
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
28
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN13
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
29
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN14
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
30
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN15
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
31
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN2
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
18
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN3
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
19
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN4
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
20
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN5
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
21
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN6
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
22
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN7
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
23
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN8
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
24
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN9
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
25
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
PA_INTSRC
PA_INTSRC
PA Interrupt Source Flag
0x20
-1
read-write
n
0x0
0x0
INTSRC0
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
0
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC1
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
1
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC10
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
10
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC11
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
11
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC12
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
12
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC13
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
13
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC14
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
14
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC15
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
15
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC2
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
2
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC3
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
3
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC4
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
4
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC5
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
5
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC6
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
6
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC7
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
7
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC8
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
8
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC9
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
9
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
PA_INTTYPE
PA_INTTYPE
PA Interrupt Trigger Type Control
0x18
-1
read-write
n
0x0
0x0
TYPE0
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
0
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE1
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
1
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE10
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
10
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE11
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
11
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE12
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
12
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE13
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
13
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE14
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
14
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE15
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
15
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE2
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
2
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE3
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
3
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE4
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
4
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE5
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
5
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE6
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
6
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE7
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
7
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE8
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
8
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE9
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
9
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
PA_MODE
PA_MODE
PA I/O Mode Control
0x0
-1
read-write
n
0x0
0x0
MODE0
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
0
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE1
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
2
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE10
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
20
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE11
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
22
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE12
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
24
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE13
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
26
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE14
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
28
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE15
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
30
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE2
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
4
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE3
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
6
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE4
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
8
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE5
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
10
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE6
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
12
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE7
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
14
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE8
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
16
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE9
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
18
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
PA_PIN
PA_PIN
PA Pin Value
0x10
-1
read-only
n
0x0
0x0
PIN0
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
0
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN1
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
1
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN10
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
10
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN11
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
11
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN12
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
12
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN13
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
13
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN14
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
14
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN15
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
15
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN2
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
2
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN3
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
3
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN4
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
4
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN5
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
5
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN6
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
6
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN7
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
7
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN8
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
8
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN9
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
9
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PA_PUSEL
PA_PUSEL
PA Pull-up and Pull-down Selection Register
0x30
-1
read-write
n
0x0
0x0
PUSEL0
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
0
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL1
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
2
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL10
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
20
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL11
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
22
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL12
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
24
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL13
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
26
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL14
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
28
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL15
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
30
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL2
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
4
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL3
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
6
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL4
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
8
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL5
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
10
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL6
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
12
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL7
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
14
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL8
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
16
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL9
Port A-F Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up and pull-down control has following behavior limitation.
The independent pull-up control register is only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g. UARTx_RXD. The independent pull-down control register is only valid when MODEn is set as tri-state mode.
When both pull-up andpull-down are set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
18
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PA_SLEWCTL
PA_SLEWCTL
PA High Slew Rate Control Register
0x28
-1
read-write
n
0x0
0x0
HSREN0
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
0
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN1
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
2
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN10
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
20
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN11
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
22
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN12
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
24
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN13
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
26
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN14
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
28
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN15
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
30
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN2
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
4
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN3
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
6
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN4
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
8
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN5
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
10
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN6
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
12
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN7
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
14
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN8
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
16
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN9
Port A-F Pin[n] High Slew Rate Control
Note 1: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
Note 2: Please refer to the M253 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
18
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
PA_SMTEN
PA_SMTEN
PA Input Schmitt Trigger Enable Register
0x24
-1
read-write
n
0x0
0x0
SMTEN0
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
0
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN1
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
1
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN10
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
10
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN11
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
11
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN12
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
12
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN13
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
13
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN14
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
14
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN15
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
15
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN2
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
2
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN3
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
3
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN4
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
4
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN5
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
5
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN6
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
6
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN7
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
7
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN8
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
8
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN9
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective.
9
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
PB0_PDIO
PB0_PDIO
GPIO PB.n Pin Data Input/Output Register
0x840
-1
read-write
n
0x0
0x0
PB12_PDIO
PB12_PDIO
GPIO PB.n Pin Data Input/Output Register
0x870
-1
read-write
n
0x0
0x0
PB13_PDIO
PB13_PDIO
GPIO PB.n Pin Data Input/Output Register
0x874
-1
read-write
n
0x0
0x0
PB14_PDIO
PB14_PDIO
GPIO PB.n Pin Data Input/Output Register
0x878
-1
read-write
n
0x0
0x0
PB15_PDIO
PB15_PDIO
GPIO PB.n Pin Data Input/Output Register
0x87C
-1
read-write
n
0x0
0x0
PB1_PDIO
PB1_PDIO
GPIO PB.n Pin Data Input/Output Register
0x844
-1
read-write
n
0x0
0x0
PB2_PDIO
PB2_PDIO
GPIO PB.n Pin Data Input/Output Register
0x848
-1
read-write
n
0x0
0x0
PB3_PDIO
PB3_PDIO
GPIO PB.n Pin Data Input/Output Register
0x84C
-1
read-write
n
0x0
0x0
PB4_PDIO
PB4_PDIO
GPIO PB.n Pin Data Input/Output Register
0x850
-1
read-write
n
0x0
0x0
PB5_PDIO
PB5_PDIO
GPIO PB.n Pin Data Input/Output Register
0x854
-1
read-write
n
0x0
0x0
PB6_PDIO
PB6_PDIO
GPIO PB.n Pin Data Input/Output Register
0x858
-1
read-write
n
0x0
0x0
PB7_PDIO
PB7_PDIO
GPIO PB.n Pin Data Input/Output Register
0x85C
-1
read-write
n
0x0
0x0
PB_DATMSK
PB_DATMSK
PB Data Output Write Mask
0x4C
-1
read-write
n
0x0
0x0
PB_DBEN
PB_DBEN
PB De-bounce Enable Control Register
0x54
-1
read-write
n
0x0
0x0
PB_DINOFF
PB_DINOFF
PB Digital Input Path Disable Control
0x44
-1
read-write
n
0x0
0x0
PB_DOUT
PB_DOUT
PB Data Output Value
0x48
-1
read-write
n
0x0
0x0
PB_INTEN
PB_INTEN
PB Interrupt Enable Control Register
0x5C
-1
read-write
n
0x0
0x0
PB_INTSRC
PB_INTSRC
PB Interrupt Source Flag
0x60
-1
read-write
n
0x0
0x0
PB_INTTYPE
PB_INTTYPE
PB Interrupt Trigger Type Control
0x58
-1
read-write
n
0x0
0x0
PB_MODE
PB_MODE
PB I/O Mode Control
0x40
-1
read-write
n
0x0
0x0
PB_PIN
PB_PIN
PB Pin Value
0x50
-1
read-write
n
0x0
0x0
PB_PUSEL
PB_PUSEL
PB Pull-up and Pull-down Selection Register
0x70
-1
read-write
n
0x0
0x0
PB_SLEWCTL
PB_SLEWCTL
PB High Slew Rate Control Register
0x68
-1
read-write
n
0x0
0x0
PB_SMTEN
PB_SMTEN
PB Input Schmitt Trigger Enable Register
0x64
-1
read-write
n
0x0
0x0
PC0_PDIO
PC0_PDIO
GPIO PC.n Pin Data Input/Output Register
0x880
-1
read-write
n
0x0
0x0
PC14_PDIO
PC14_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8B8
-1
read-write
n
0x0
0x0
PC1_PDIO
PC1_PDIO
GPIO PC.n Pin Data Input/Output Register
0x884
-1
read-write
n
0x0
0x0
PC2_PDIO
PC2_PDIO
GPIO PC.n Pin Data Input/Output Register
0x888
-1
read-write
n
0x0
0x0
PC3_PDIO
PC3_PDIO
GPIO PC.n Pin Data Input/Output Register
0x88C
-1
read-write
n
0x0
0x0
PC4_PDIO
PC4_PDIO
GPIO PC.n Pin Data Input/Output Register
0x890
-1
read-write
n
0x0
0x0
PC5_PDIO
PC5_PDIO
GPIO PC.n Pin Data Input/Output Register
0x894
-1
read-write
n
0x0
0x0
PC_DATMSK
PC_DATMSK
PC Data Output Write Mask
0x8C
-1
read-write
n
0x0
0x0
PC_DBEN
PC_DBEN
PC De-bounce Enable Control Register
0x94
-1
read-write
n
0x0
0x0
PC_DINOFF
PC_DINOFF
PC Digital Input Path Disable Control
0x84
-1
read-write
n
0x0
0x0
PC_DOUT
PC_DOUT
PC Data Output Value
0x88
-1
read-write
n
0x0
0x0
PC_INTEN
PC_INTEN
PC Interrupt Enable Control Register
0x9C
-1
read-write
n
0x0
0x0
PC_INTSRC
PC_INTSRC
PC Interrupt Source Flag
0xA0
-1
read-write
n
0x0
0x0
PC_INTTYPE
PC_INTTYPE
PC Interrupt Trigger Type Control
0x98
-1
read-write
n
0x0
0x0
PC_MODE
PC_MODE
PC I/O Mode Control
0x80
-1
read-write
n
0x0
0x0
PC_PIN
PC_PIN
PC Pin Value
0x90
-1
read-write
n
0x0
0x0
PC_PUSEL
PC_PUSEL
PC Pull-up and Pull-down Selection Register
0xB0
-1
read-write
n
0x0
0x0
PC_SLEWCTL
PC_SLEWCTL
PC High Slew Rate Control Register
0xA8
-1
read-write
n
0x0
0x0
PC_SMTEN
PC_SMTEN
PC Input Schmitt Trigger Enable Register
0xA4
-1
read-write
n
0x0
0x0
PF0_PDIO
PF0_PDIO
GPIO PF.n Pin Data Input/Output Register
0x940
-1
read-write
n
0x0
0x0
PF15_PDIO
PF15_PDIO
GPIO PF.n Pin Data Input/Output Register
0x97C
-1
read-write
n
0x0
0x0
PF1_PDIO
PF1_PDIO
GPIO PF.n Pin Data Input/Output Register
0x944
-1
read-write
n
0x0
0x0
PF2_PDIO
PF2_PDIO
GPIO PF.n Pin Data Input/Output Register
0x948
-1
read-write
n
0x0
0x0
PF3_PDIO
PF3_PDIO
GPIO PF.n Pin Data Input/Output Register
0x94C
-1
read-write
n
0x0
0x0
PF4_PDIO
PF4_PDIO
GPIO PF.n Pin Data Input/Output Register
0x950
-1
read-write
n
0x0
0x0
PF5_PDIO
PF5_PDIO
GPIO PF.n Pin Data Input/Output Register
0x954
-1
read-write
n
0x0
0x0
PF_DATMSK
PF_DATMSK
PF Data Output Write Mask
0x14C
-1
read-write
n
0x0
0x0
PF_DBEN
PF_DBEN
PF De-bounce Enable Control Register
0x154
-1
read-write
n
0x0
0x0
PF_DINOFF
PF_DINOFF
PF Digital Input Path Disable Control
0x144
-1
read-write
n
0x0
0x0
PF_DOUT
PF_DOUT
PF Data Output Value
0x148
-1
read-write
n
0x0
0x0
PF_INTEN
PF_INTEN
PF Interrupt Enable Control Register
0x15C
-1
read-write
n
0x0
0x0
PF_INTSRC
PF_INTSRC
PF Interrupt Source Flag
0x160
-1
read-write
n
0x0
0x0
PF_INTTYPE
PF_INTTYPE
PF Interrupt Trigger Type Control
0x158
-1
read-write
n
0x0
0x0
PF_MODE
PF_MODE
PF I/O Mode Control
0x140
-1
read-write
n
0x0
0x0
PF_PIN
PF_PIN
PF Pin Value
0x150
-1
read-write
n
0x0
0x0
PF_PUSEL
PF_PUSEL
PF Pull-up and Pull-down Selection Register
0x170
-1
read-write
n
0x0
0x0
PF_SLEWCTL
PF_SLEWCTL
PF High Slew Rate Control Register
0x168
-1
read-write
n
0x0
0x0
PF_SMTEN
PF_SMTEN
PF Input Schmitt Trigger Enable Register
0x164
-1
read-write
n
0x0
0x0
I2C0
I2C Register Map
I2C
0x0
0x0
0x34
registers
n
0x3C
0x14
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
-1
read-write
n
0x0
0x0
ADDR
I2C Address
The content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
Note: When software sets 10'h000, the address can not be used.
1
10
read-write
GC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
-1
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
-1
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
-1
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
-1
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask
I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
Note: The wake-up function cannot use address mask.
1
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
-1
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
-1
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
-1
read-write
n
0x0
0x0
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
-1
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided
Note: The minimum value of I2C_CLKDIV is 4.
0
10
read-write
I2C_CTL0
I2C_CTL0
I2C Control Register 0
0x0
-1
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
2
1
read-write
I2CEN
I2C Controller Enable Bit
6
1
read-write
0
I2C controller Disabled
#0
1
I2C controller Enabled
#1
INTEN
Enable Interrupt
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag
When a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
3
1
read-write
STA
I2C START Control
Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or Repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
4
1
read-write
I2C_CTL1
I2C_CTL1
I2C Control Register 1
0x44
-1
read-write
n
0x0
0x0
ADDR10EN
Address 10-bit Function Enable Bit
9
1
read-write
0
Address match 10-bit function Disabled
#0
1
Address match 10-bit function Enabled
#1
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the I2C request to PDMA
#1
PDMASTR
PDMA Stretch Bit
8
1
read-write
0
I2C send STOP automatically after PDMA transfer done. (only master TX)
#0
1
I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX)
#1
RXPDMAEN
PDMA Receive Channel Available
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
I2C_DAT
I2C_DAT
I2C Data Register
0x8
-1
read-write
n
0x0
0x0
DAT
I2C Data
Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
0
8
read-write
I2C_STATUS0
I2C_STATUS0
I2C Status Register 0
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status
0
8
read-only
I2C_STATUS1
I2C_STATUS1
I2C Status Register 1
0x48
-1
read-write
n
0x0
0x0
ADMAT0
I2C Address 0 Match Status
When address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
I2C Address 1 Match Status
When address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
ADMAT2
I2C Address 2 Match Status
When address 2 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
2
1
read-write
ADMAT3
I2C Address 3 Match Status
When address 3 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
3
1
read-write
ONBUSY
On Bus Busy (Read Only)
Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.
8
1
read-only
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
I2C_TMCTL
I2C_TMCTL
I2C Timing Configure Control Register
0x4C
-1
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control
This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
16
9
read-write
STCTL
Setup Time Configure Control
This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
Note: Setup time setting should not make SCL output less than three PCLKs.
0
9
read-write
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
-1
read-write
n
0x0
0x0
TOCDIV4
Time-out Counter Input Clock Divided by 4
When enabled, the time-out period is extended 4 times.
1
1
read-write
0
Time-out period is extend 4 times Disabled
#0
1
Time-out period is extend 4 times Enabled
#1
TOCEN
Time-out Counter Enable Bit
When enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOIF
Time-out Flag
This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
Note: Software can write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
-1
read-write
n
0x0
0x0
NHDBUSEN
I2C No Hold BUS Enable Bit
Note: The I2C controller could respond when WKIF event is not cleared. It may cause error data transmitted or received. If data transmitted or received when WKIF event is not cleared, user must reset I2C controller and execute the original operation again.
7
1
read-write
0
I2C holds bus after wake-up
#0
1
I2C does not hold bus after wake-up
#1
WKEN
I2C Wake-up Enable Bit
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
-1
read-write
n
0x0
0x0
WKAKDONE
Wakeup Address Frame Acknowledge Bit Done
Note: This bit cannot release WKIF. Software can write 1 to clear this bit.
1
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WKIF
I2C Wake-up Flag
When chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WRSTSWK
Read/Write Status Bit in Address Wakeup Frame (Read Only)
Note: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit.
2
1
read-only
0
Write command be record on the address match wakeup frame
#0
1
Read command be record on the address match wakeup frame
#1
I2C1
I2C Register Map
I2C
0x0
0x0
0x34
registers
n
0x3C
0x14
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
-1
read-write
n
0x0
0x0
ADDR
I2C Address
The content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
Note: When software sets 10'h000, the address can not be used.
1
10
read-write
GC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
-1
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
-1
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
-1
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
-1
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask
I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
Note: The wake-up function cannot use address mask.
1
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
-1
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
-1
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
-1
read-write
n
0x0
0x0
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
-1
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided
Note: The minimum value of I2C_CLKDIV is 4.
0
10
read-write
I2C_CTL0
I2C_CTL0
I2C Control Register 0
0x0
-1
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
2
1
read-write
I2CEN
I2C Controller Enable Bit
6
1
read-write
0
I2C controller Disabled
#0
1
I2C controller Enabled
#1
INTEN
Enable Interrupt
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag
When a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
3
1
read-write
STA
I2C START Control
Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or Repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
4
1
read-write
I2C_CTL1
I2C_CTL1
I2C Control Register 1
0x44
-1
read-write
n
0x0
0x0
ADDR10EN
Address 10-bit Function Enable Bit
9
1
read-write
0
Address match 10-bit function Disabled
#0
1
Address match 10-bit function Enabled
#1
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the I2C request to PDMA
#1
PDMASTR
PDMA Stretch Bit
8
1
read-write
0
I2C send STOP automatically after PDMA transfer done. (only master TX)
#0
1
I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX)
#1
RXPDMAEN
PDMA Receive Channel Available
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
I2C_DAT
I2C_DAT
I2C Data Register
0x8
-1
read-write
n
0x0
0x0
DAT
I2C Data
Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
0
8
read-write
I2C_STATUS0
I2C_STATUS0
I2C Status Register 0
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status
0
8
read-only
I2C_STATUS1
I2C_STATUS1
I2C Status Register 1
0x48
-1
read-write
n
0x0
0x0
ADMAT0
I2C Address 0 Match Status
When address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
I2C Address 1 Match Status
When address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
ADMAT2
I2C Address 2 Match Status
When address 2 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
2
1
read-write
ADMAT3
I2C Address 3 Match Status
When address 3 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
3
1
read-write
ONBUSY
On Bus Busy (Read Only)
Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.
8
1
read-only
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
I2C_TMCTL
I2C_TMCTL
I2C Timing Configure Control Register
0x4C
-1
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control
This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
16
9
read-write
STCTL
Setup Time Configure Control
This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
Note: Setup time setting should not make SCL output less than three PCLKs.
0
9
read-write
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
-1
read-write
n
0x0
0x0
TOCDIV4
Time-out Counter Input Clock Divided by 4
When enabled, the time-out period is extended 4 times.
1
1
read-write
0
Time-out period is extend 4 times Disabled
#0
1
Time-out period is extend 4 times Enabled
#1
TOCEN
Time-out Counter Enable Bit
When enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOIF
Time-out Flag
This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
Note: Software can write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
-1
read-write
n
0x0
0x0
NHDBUSEN
I2C No Hold BUS Enable Bit
Note: The I2C controller could respond when WKIF event is not cleared. It may cause error data transmitted or received. If data transmitted or received when WKIF event is not cleared, user must reset I2C controller and execute the original operation again.
7
1
read-write
0
I2C holds bus after wake-up
#0
1
I2C does not hold bus after wake-up
#1
WKEN
I2C Wake-up Enable Bit
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
-1
read-write
n
0x0
0x0
WKAKDONE
Wakeup Address Frame Acknowledge Bit Done
Note: This bit cannot release WKIF. Software can write 1 to clear this bit.
1
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WKIF
I2C Wake-up Flag
When chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WRSTSWK
Read/Write Status Bit in Address Wakeup Frame (Read Only)
Note: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit.
2
1
read-only
0
Write command be record on the address match wakeup frame
#0
1
Read command be record on the address match wakeup frame
#1
NMI
NMI Register Map
NMI
0x0
0x0
0x8
registers
n
NMIEN
NMIEN
NMI Source Interrupt Enable Register
0x0
-1
read-write
n
0x0
0x0
BODOUT
BOD NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
BOD NMI source Disabled
#0
1
BOD NMI source Enabled
#1
CLKFAIL
Clock Fail Detected NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
Clock fail detected interrupt NMI source Disabled
#0
1
Clock fail detected interrupt NMI source Enabled
#1
EINT0
External Interrupt From PA.0, PD.2 or PE.4 Pin NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
8
1
read-write
0
External interrupt from PA.0, PD.2 or PE.4 pin NMI source Disabled
#0
1
External interrupt from PA.0, PD.2 or PE.4 pin NMI source Enabled
#1
EINT1
External Interrupt From PB.0, PD.3 or PE.5 Pin NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
9
1
read-write
0
External interrupt from PB.0, PD.3 or PE.5 pin NMI source Disabled
#0
1
External interrupt from PB.0, PD.3 or PE.5 pin NMI source Enabled
#1
EINT2
External Interrupt From PC.0 Pin NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
10
1
read-write
0
External interrupt from PC.0 pin NMI source Disabled
#0
1
External interrupt from PC.0 pin NMI source Enabled
#1
EINT3
External Interrupt From PD.0 Pin NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
11
1
read-write
0
External interrupt from PD.0 pin NMI source Disabled
#0
1
External interrupt from PD.0 pin NMI source Enabled
#1
EINT4
External Interrupt From PE.0 Pin NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
12
1
read-write
0
External interrupt from PE.0 pin NMI source Disabled
#0
1
External interrupt from PE.0 pin NMI source Enabled
#1
EINT5
External Interrupt From PF.0 Pin NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
13
1
read-write
0
External interrupt from PF.0 pin NMI source Disabled
#0
1
External interrupt from PF.0 pin NMI source Enabled
#1
IRC_INT
IRC TRIM NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
IRC TRIM NMI source Disabled
#0
1
IRC TRIM NMI source Enabled
#1
PWRWU_INT
Power-down Mode Wake-up NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
Power-down mode wake-up NMI source Disabled
#0
1
Power-down mode wake-up NMI source Enabled
#1
RTC_INT
RTC NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
RTC NMI source Disabled
#0
1
RTC NMI source Enabled
#1
UART0_INT
UART0 NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
14
1
read-write
0
UART0 NMI source Disabled
#0
1
UART0 NMI source Enabled
#1
UART1_INT
UART1 NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
15
1
read-write
0
UART1 NMI source Disabled
#0
1
UART1 NMI source Enabled
#1
NMISTS
NMISTS
NMI Source Interrupt Status Register
0x4
-1
read-only
n
0x0
0x0
BODOUT
BOD Interrupt Flag (Read Only)
0
1
read-only
0
BOD interrupt is deasserted
#0
1
BOD interrupt is asserted
#1
CLKFAIL
Clock Fail Detected Interrupt Flag (Read Only)
4
1
read-only
0
Clock fail detected interrupt is deasserted
#0
1
Clock fail detected interrupt is asserted
#1
EINT0
External Interrupt From PA.0, PD.2 or PE.4 Pin Interrupt Flag (Read Only)
8
1
read-only
0
External Interrupt from PA.0, PD.2 or PE.4 interrupt is deasserted
#0
1
External Interrupt from PA.0, PD.2 or PE.4 interrupt is asserted
#1
EINT1
External Interrupt From PB.0, PD.3 or PE.5 Pin Interrupt Flag (Read Only)
9
1
read-only
0
External Interrupt from PB.0, PD.3 or PE.5 interrupt is deasserted
#0
1
External Interrupt from PB.0, PD.3 or PE.5 interrupt is asserted
#1
EINT2
External Interrupt From PC.0 Pin Interrupt Flag (Read Only)
10
1
read-only
0
External Interrupt from PC.0 interrupt is deasserted
#0
1
External Interrupt from PC.0 interrupt is asserted
#1
EINT3
External Interrupt From PD.0 Pin Interrupt Flag (Read Only)
11
1
read-only
0
External Interrupt from PD.0 interrupt is deasserted
#0
1
External Interrupt from PD.0 interrupt is asserted
#1
EINT4
External Interrupt From PE.0 Pin Interrupt Flag (Read Only)
12
1
read-only
0
External Interrupt from PE.0 interrupt is deasserted
#0
1
External Interrupt from PE.0 interrupt is asserted
#1
EINT5
External Interrupt From PF.0 Pin Interrupt Flag (Read Only)
13
1
read-only
0
External Interrupt from PF.0 interrupt is deasserted
#0
1
External Interrupt from PF.0 interrupt is asserted
#1
IRC_INT
IRC TRIM Interrupt Flag (Read Only)
1
1
read-only
0
HIRC TRIM interrupt is deasserted
#0
1
HIRC TRIM interrupt is asserted
#1
PWRWU_INT
Power-down Mode Wake-up Interrupt Flag (Read Only)
2
1
read-only
0
Power-down mode wake-up interrupt is deasserted
#0
1
Power-down mode wake-up interrupt is asserted
#1
RTC_INT
RTC Interrupt Flag (Read Only)
6
1
read-only
0
RTC interrupt is deasserted
#0
1
RTC interrupt is asserted
#1
UART0_INT
UART0 Interrupt Flag (Read Only)
14
1
read-only
0
UART1 interrupt is deasserted
#0
1
UART1 interrupt is asserted
#1
UART1_INT
UART1 Interrupt Flag (Read Only)
15
1
read-only
0
UART1 interrupt is deasserted
#0
1
UART1 interrupt is asserted
#1
NVIC
NVIC Register Map
NVIC
0x0
0x0
0x8
registers
n
0x100
0x8
registers
n
0x180
0x8
registers
n
0x200
0x8
registers
n
0x80
0x8
registers
n
IABR0
NVIC_IABR0
IRQ0 ~ IRQ31 Active Bit Register
0x200
-1
read-write
n
0x0
0x0
ACTIVE
Interrupt Active Flags
The NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active.
0
32
read-write
0
interrupt not active
0
1
interrupt active
1
IABR1
NVIC_IABR1
IRQ32 ~ IRQ63 Active Bit Register
0x204
-1
read-write
n
0x0
0x0
ACTIVE
Interrupt Active Flags
The NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active.
0
32
read-write
0
interrupt not active
0
1
interrupt active
1
ICER0
NVIC_ICER0
IRQ0 ~ IRQ31 Clear-enable Control Register
0x80
-1
read-write
n
0x0
0x0
CALENA
Interrupt Clear Enable Bit
The NVIC_ICER0-NVIC_ICER1 registers disable interrupts, and show which interrupts are enabled.
Write Operation:
0
32
read-write
0
No effect.
Interrupt Disabled
0
1
Interrupt Disabled.
Interrupt Enabled
1
ICER1
NVIC_ICER1
IRQ32 ~ IRQ63 Clear-enable Control Register
0x84
-1
read-write
n
0x0
0x0
CALENA
Interrupt Clear Enable Bit
The NVIC_ICER0-NVIC_ICER2 registers disable interrupts, and show which interrupts are enabled.
Write Operation:
0
32
read-write
0
No effect.
Interrupt Disabled
0
1
Interrupt Disabled.
Interrupt Enabled
1
ICPR0
NVIC_ICPR0
IRQ0 ~ IRQ31 Clear-pending Control Register
0x180
-1
read-write
n
0x0
0x0
CALPEND
Interrupt Clear-pending
The NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts, and show which interrupts are pending
Write Operation:
0
32
read-write
0
No effect.
Interrupt is not pending
0
1
Removes pending state an interrupt.
Interrupt is pending
1
ICPR1
NVIC_ICPR1
IRQ32 ~ IRQ63 Clear-pending Control Register
0x184
-1
read-write
n
0x0
0x0
CALPEND
Interrupt Clear-pending
The NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts, and show which interrupts are pending
Write Operation:
0
32
read-write
0
No effect.
Interrupt is not pending
0
1
Removes pending state an interrupt.
Interrupt is pending
1
ISER0
NVIC_ISER0
IRQ0 ~ IRQ31 Set-enable Control Register
0x0
-1
read-write
n
0x0
0x0
SETENA
Interrupt Set Enable Bit
The NVIC_ISER0-NVIC_ISER1 registers enable interrupts, and show which interrupts are enabled
Write Operation:
0
32
read-write
0
No effect.
Interrupt Disabled
0
1
Interrupt Enabled
1
ISER1
NVIC_ISER1
IRQ32 ~ IRQ63 Set-enable Control Register
0x4
-1
read-write
n
0x0
0x0
SETENA
Interrupt Set Enable Bit
The NVIC_ISER0-NVIC_ISER2 registers enable interrupts, and show which interrupts are enabled
Write Operation:
0
32
read-write
0
No effect.
Interrupt Disabled
0
1
Interrupt Enabled
1
ISPR0
NVIC_ISPR0
IRQ0 ~ IRQ31 Set-pending Control Register
0x100
-1
read-write
n
0x0
0x0
SETPEND
Interrupt Set-pending
The NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state, and show which interrupts are pending
Write Operation:
0
32
read-write
0
No effect.
Interrupt is not pending
0
1
Changes interrupt state to pending.
Interrupt is pending
1
ISPR1
NVIC_ISPR1
IRQ32 ~ IRQ63 Set-pending Control Register
0x104
-1
read-write
n
0x0
0x0
SETPEND
Interrupt Set-pending
The NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state, and show which interrupts are pending
Write Operation:
0
32
read-write
0
No effect.
Interrupt is not pending
0
1
Changes interrupt state to pending.
Interrupt is pending
1
PDMA
PDMA Register Map
PDMA
0x0
0x0
0x50
registers
n
0x100
0x14
registers
n
0x400
0x44
registers
n
0x460
0x4
registers
n
0x480
0x8
registers
n
ABTSTS
PDMA_ABTSTS
PDMA Channel Read/Write Target Abort Flag Register
0x420
-1
read-write
n
0x0
0x0
ABTIF0
PDMA Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
0
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF1
PDMA Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
1
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF2
PDMA Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
2
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF3
PDMA Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
3
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF4
PDMA Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
4
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ALIGN
PDMA_ALIGN
PDMA Transfer Alignment Status Register
0x428
-1
read-write
n
0x0
0x0
ALIGN0
Transfer Alignment Flag
0
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN1
Transfer Alignment Flag
1
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN2
Transfer Alignment Flag
2
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN3
Transfer Alignment Flag
3
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN4
Transfer Alignment Flag
4
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
CHCTL
PDMA_CHCTL
PDMA Channel Control Register
0x400
-1
read-write
n
0x0
0x0
CHEN0
PDMA Channel Enable Bits
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
0
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN1
PDMA Channel Enable Bits
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
1
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN2
PDMA Channel Enable Bits
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
2
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN3
PDMA Channel Enable Bits
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
3
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN4
PDMA Channel Enable Bits
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
4
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHRST
PDMA_CHRST
PDMA Channel Reset Register
0x460
-1
read-write
n
0x0
0x0
CHnRST
Channel n Reset
0
5
read-write
0
corresponding channel n is not reset
0
1
corresponding channel n is reset
1
CURSCAT0
PDMA_CURSCAT0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x100
-1
read-only
n
0x0
0x0
CURADDR
PDMA Current Description Address (Read Only)
This field indicates a 32-bit current external description address of PDMA controller.
Note: This field is read only and used for Scatter-gather mode only to indicate the current external description address.
0
32
read-only
CURSCAT1
PDMA_CURSCAT1
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x104
-1
read-write
n
0x0
0x0
CURSCAT2
PDMA_CURSCAT2
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x108
-1
read-write
n
0x0
0x0
CURSCAT3
PDMA_CURSCAT3
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x10C
-1
read-write
n
0x0
0x0
CURSCAT4
PDMA_CURSCAT4
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x110
-1
read-write
n
0x0
0x0
DSCT0_CTL
PDMA_DSCT0_CTL
Descriptor Table Control Register of PDMA Channel n
0x0
-1
read-write
n
0x0
0x0
BURSIZE
Burst Size
This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
Note: This field is only useful in burst transfer type.
4
3
read-write
0
128 Transfers
#000
1
64 Transfers
#001
2
32 Transfers
#010
3
16 Transfers
#011
4
8 Transfers
#100
5
4 Transfers
#101
6
2 Transfers
#110
7
1 Transfers
#111
DAINC
Destination Address Increment
This field is used to set the destination address increment size.
Note: The fixed address function do not support in memory to memory transfer type.
10
2
read-write
3
No increment (fixed address)
#11
OPMODE
PDMA Operation Mode Selection
Note: Before filling new transfer task in the Descriptor Table, user must check the PDMA_INTSTS[1] to make sure the current task is complete.
0
2
read-write
0
Idle state: Channel is stopped or this table is complete. When PDMA finishes channel table task, OPMODE will be cleared to idle state automatically
#00
1
Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[1] will be asserted
#01
2
Scatter-gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register PDMA controller will ignore this task, then load the next task to execute
#10
3
Reserved.
#11
SAINC
Source Address Increment
This field is used to set the source address increment size.
Note: The fixed address function do not support in memory to memory transfer type.
8
2
read-write
3
No increment (fixed address)
#11
TBINTDIS
Table Interrupt Disable Bit
This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[4:0]) when PDMA controller finishes transfer task.
Note: This function is only for Scatter-gather mode.
7
1
read-write
0
Table interrupt Enabled
#0
1
Table interrupt Disabled
#1
TXCNT
Transfer Count
The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 65536, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
Note: When PDMA finishes each transfer data, this field will be decreased immediately.
16
16
read-write
TXTYPE
Transfer Type
2
1
read-write
0
Burst transfer type
#0
1
Single transfer type
#1
TXWIDTH
Transfer Width Selection
This field is used for transfer width.
Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
12
2
read-write
0
One byte (8 bit) is transferred for every operation
#00
1
One half-word (16 bit) is transferred for every operation
#01
2
One word (32-bit) is transferred for every operation
#10
3
Reserved.
#11
DSCT0_DA
PDMA_DSCT0_DA
Destination Address Register of PDMA Channel n
0x8
-1
read-write
n
0x0
0x0
DA
PDMA Transfer Destination Address
This field indicates a 32-bit destination address of PDMA controller.
0
32
read-write
DSCT0_NEXT
PDMA_DSCT0_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0xC
-1
read-write
n
0x0
0x0
EXENEXT
PDMA Execution Next Descriptor Table Offset
This field indicates the offset of next descriptor table address of current execution descriptor table in system memory.
Note: Write operation is useless in this field.
16
16
read-write
NEXT
PDMA Next Descriptor Table Offset
This field indicates the offset of the next descriptor table address in system memory.
Write Operation:
If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.
Read Operation:
When operating in Scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory.
Note 1: The descriptor table address must be word boundary.
Note 2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
0
16
read-write
DSCT0_SA
PDMA_DSCT0_SA
Source Address Register of PDMA Channel n
0x4
-1
read-write
n
0x0
0x0
SA
PDMA Transfer Source Address
This field indicates a 32-bit source address of PDMA controller.
0
32
read-write
DSCT1_CTL
PDMA_DSCT1_CTL
Descriptor Table Control Register of PDMA Channel n
0x10
-1
read-write
n
0x0
0x0
DSCT1_DA
PDMA_DSCT1_DA
Destination Address Register of PDMA Channel n
0x18
-1
read-write
n
0x0
0x0
DSCT1_NEXT
PDMA_DSCT1_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x1C
-1
read-write
n
0x0
0x0
DSCT1_SA
PDMA_DSCT1_SA
Source Address Register of PDMA Channel n
0x14
-1
read-write
n
0x0
0x0
DSCT2_CTL
PDMA_DSCT2_CTL
Descriptor Table Control Register of PDMA Channel n
0x20
-1
read-write
n
0x0
0x0
DSCT2_DA
PDMA_DSCT2_DA
Destination Address Register of PDMA Channel n
0x28
-1
read-write
n
0x0
0x0
DSCT2_NEXT
PDMA_DSCT2_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x2C
-1
read-write
n
0x0
0x0
DSCT2_SA
PDMA_DSCT2_SA
Source Address Register of PDMA Channel n
0x24
-1
read-write
n
0x0
0x0
DSCT3_CTL
PDMA_DSCT3_CTL
Descriptor Table Control Register of PDMA Channel n
0x30
-1
read-write
n
0x0
0x0
DSCT3_DA
PDMA_DSCT3_DA
Destination Address Register of PDMA Channel n
0x38
-1
read-write
n
0x0
0x0
DSCT3_NEXT
PDMA_DSCT3_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x3C
-1
read-write
n
0x0
0x0
DSCT3_SA
PDMA_DSCT3_SA
Source Address Register of PDMA Channel n
0x34
-1
read-write
n
0x0
0x0
DSCT4_CTL
PDMA_DSCT4_CTL
Descriptor Table Control Register of PDMA Channel n
0x40
-1
read-write
n
0x0
0x0
DSCT4_DA
PDMA_DSCT4_DA
Destination Address Register of PDMA Channel n
0x48
-1
read-write
n
0x0
0x0
DSCT4_NEXT
PDMA_DSCT4_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x4C
-1
read-write
n
0x0
0x0
DSCT4_SA
PDMA_DSCT4_SA
Source Address Register of PDMA Channel n
0x44
-1
read-write
n
0x0
0x0
INTEN
PDMA_INTEN
PDMA Interrupt Enable Register
0x418
-1
read-write
n
0x0
0x0
INTEN0
PDMA Interrupt Enable Bits
This field is used to enable PDMA channel[n] interrupt.
Note: The interrupt flag is time-out, abort, transfer done and align.
0
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN1
PDMA Interrupt Enable Bits
This field is used to enable PDMA channel[n] interrupt.
Note: The interrupt flag is time-out, abort, transfer done and align.
1
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN2
PDMA Interrupt Enable Bits
This field is used to enable PDMA channel[n] interrupt.
Note: The interrupt flag is time-out, abort, transfer done and align.
2
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN3
PDMA Interrupt Enable Bits
This field is used to enable PDMA channel[n] interrupt.
Note: The interrupt flag is time-out, abort, transfer done and align.
3
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN4
PDMA Interrupt Enable Bits
This field is used to enable PDMA channel[n] interrupt.
Note: The interrupt flag is time-out, abort, transfer done and align.
4
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTSTS
PDMA_INTSTS
PDMA Interrupt Status Register
0x41C
-1
read-write
n
0x0
0x0
ABTIF
PDMA Read/Write Target Abort Interrupt Flag (Read Only)
This bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error.
0
1
read-only
0
No AHB bus ERROR response received
#0
1
AHB bus ERROR response received
#1
ALIGNF
Transfer Alignment Interrupt Flag (Read Only)
2
1
read-only
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
REQTOF0
Request Time-out Flag for Channel 0
This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear this bit.
Note: Please disable time-out function before clear this bit.
8
1
read-write
0
No request time-out
#0
1
Peripheral request time-out
#1
REQTOF1
Request Time-out Flag for Channel 1
This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear this bit.
Note: Please disable time-out function before clear this bit.
9
1
read-write
0
No request time-out
#0
1
Peripheral request time-out
#1
TDIF
Transfer Done Interrupt Flag (Read Only)
This bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer.
1
1
read-only
0
Not finished yet
#0
1
PDMA channel has finished transmission
#1
PAUSE
PDMA_PAUSE
PDMA Transfer Pause Control Register
0x404
-1
write-only
n
0x0
0x0
PAUSE0
PDMA Channel n Transfer Pause Control (Write Only)
0
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE1
PDMA Channel n Transfer Pause Control (Write Only)
1
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE2
PDMA Channel n Transfer Pause Control (Write Only)
2
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE3
PDMA Channel n Transfer Pause Control (Write Only)
3
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE4
PDMA Channel n Transfer Pause Control (Write Only)
4
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PRICLR
PDMA_PRICLR
PDMA Fixed Priority Clear Register
0x414
-1
write-only
n
0x0
0x0
FPRICLR0
PDMA Fixed Priority Clear Bits (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
0
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR1
PDMA Fixed Priority Clear Bits (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
1
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR2
PDMA Fixed Priority Clear Bits (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
2
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR3
PDMA Fixed Priority Clear Bits (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
3
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR4
PDMA Fixed Priority Clear Bits (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
4
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
PRISET
PDMA_PRISET
PDMA Fixed Priority Setting Register
0x410
-1
read-write
n
0x0
0x0
FPRISET0
PDMA Fixed Priority Setting
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
0
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET1
PDMA Fixed Priority Setting
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
1
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET2
PDMA Fixed Priority Setting
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
2
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET3
PDMA Fixed Priority Setting
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
3
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET4
PDMA Fixed Priority Setting
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
4
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
REQSEL0_3
PDMA_REQSEL0_3
PDMA Request Source Select Register 0
0x480
-1
read-write
n
0x0
0x0
REQSRC0
Channel 0 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.
Note 1: A peripheral cannot be assigned to two channels at the same time.
Note 2: This field is useless when transfer between memory and memory.
0
7
read-write
0
Disable PDMA peripheral request
0
1
Reserved.
1
10
Channel connects to UART3_TX
10
11
Channel connects to UART3_RX
11
12
Channel connects to UART4_TX
12
13
Channel connects to UART4_RX
13
14
Reserved.
14
15
Reserved.
15
16
Channel connects to USCI0_TX
16
17
Channel connects to USCI0_RX
17
18
Reserved.
18
19
Reserved.
19
2
Reserved.
2
20
Reserved.
20
21
Reserved.
21
22
Channel connects to SPI0_TX
22
23
Channel connects to SPI0_RX
23
24
Reserved.
24
25
Reserved.
25
26
Reserved.
26
27
Reserved.
27
28
Reserved.
28
29
Reserved.
29
3
Reserved.
3
30
Reserved.
30
31
Reserved.
31
32
Reserved.
32
33
Reserved.
33
34
Reserved.
34
35
Reserved.
35
36
Reserved.
36
37
Reserved.
37
38
Channel connects to I2C0_TX
38
39
Channel connects to I2C0_RX
39
4
Channel connects to UART0_TX
4
40
Channel connects to I2C1_TX
40
41
Channel connects to I2C1_RX
41
42
Reserved.
42
43
Reserved.
43
44
Reserved.
44
45
Reserved.
45
46
Channel connects to TMR0
46
47
Channel connects to TMR1
47
48
Channel connects to TMR2
48
49
Channel connects to TMR3
49
5
Channel connects to UART0_RX
5
50
Channel connects to ADC_RX
50
52
Reserved.
52
53
Reserved.
53
54
Reserved.
54
55
Reserved.
55
56
Reserved.
56
57
Reserved.
57
58
Reserved.
58
59
Reserved.
59
6
Channel connects to UART1_TX
6
60
Reserved.
60
61
Reserved.
61
62
Reserved.
62
63
Reserved.
63
64
Reserved.
64
65
Reserved.
65
7
Channel connects to UART1_RX
7
8
Channel connects to UART2_TX
8
9
Channel connects to UART2_RX
9
REQSRC1
Channel 1 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
7
read-write
REQSRC2
Channel 2 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
7
read-write
REQSRC3
Channel 3 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
7
read-write
REQSEL4
PDMA_REQSEL4
PDMA Request Source Select Register 1
0x484
-1
read-write
n
0x0
0x0
REQSRC4
Channel 4 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
0
7
read-write
SCATBA
PDMA_SCATBA
PDMA Scatter-gather Descriptor Table Base Address Register
0x43C
-1
read-write
n
0x0
0x0
SCATBA
PDMA Scatter-gather Descriptor Table Address
In Scatter-gather mode, this is the base address for calculating the next link - list address. The next link address equation is
Note: Only useful in Scatter-gather mode.
16
16
read-write
SWREQ
PDMA_SWREQ
PDMA Software Request Register
0x408
-1
write-only
n
0x0
0x0
SWREQ0
PDMA Software Request (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
0
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ1
PDMA Software Request (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
1
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ2
PDMA Software Request (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
2
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ3
PDMA Software Request (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
3
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ4
PDMA Software Request (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
4
1
write-only
0
No effect
#0
1
Generate a software request
#1
TACTSTS
PDMA_TACTSTS
PDMA Transfer Active Flag Register
0x42C
-1
read-only
n
0x0
0x0
TXACTF0
Transfer on Active Flag (Read Only)
This bit indicates which PDMA channel is in active.
0
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF1
Transfer on Active Flag (Read Only)
This bit indicates which PDMA channel is in active.
1
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF2
Transfer on Active Flag (Read Only)
This bit indicates which PDMA channel is in active.
2
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF3
Transfer on Active Flag (Read Only)
This bit indicates which PDMA channel is in active.
3
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF4
Transfer on Active Flag (Read Only)
This bit indicates which PDMA channel is in active.
4
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TDSTS
PDMA_TDSTS
PDMA Channel Transfer Done Flag Register
0x424
-1
read-write
n
0x0
0x0
TDIF0
Transfer Done Flag
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
0
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF1
Transfer Done Flag
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
1
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF2
Transfer Done Flag
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
2
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF3
Transfer Done Flag
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
3
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF4
Transfer Done Flag
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
4
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TOC0_1
PDMA_TOC0_1
PDMA Time-out Counter Ch1 and Ch0 Register
0x440
-1
read-write
n
0x0
0x0
TOC0
Time-out Counter for Channel 0
This controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC0[2:0]) clock.
0
16
read-write
TOC1
Time-out Counter for Channel 1
This controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC0[6:4]) clock. For the example of time-out period, refer to TOC0 bit description.
16
16
read-write
TOUTEN
PDMA_TOUTEN
PDMA Time-out Enable Register
0x434
-1
read-write
n
0x0
0x0
TOUTEN0
PDMA Time-out Enable Bits
0
1
read-write
0
PDMA Channel n time-out function Disabled
#0
1
PDMA Channel n time-out function Enabled
#1
TOUTEN1
PDMA Time-out Enable Bits
1
1
read-write
0
PDMA Channel n time-out function Disabled
#0
1
PDMA Channel n time-out function Enabled
#1
TOUTIEN
PDMA_TOUTIEN
PDMA Time-out Interrupt Enable Register
0x438
-1
read-write
n
0x0
0x0
TOUTIEN0
PDMA Time-out Interrupt Enable Bits
0
1
read-write
0
PDMA Channel n time-out interrupt Disabled
#0
1
PDMA Channel n time-out interrupt Enabled
#1
TOUTIEN1
PDMA Time-out Interrupt Enable Bits
1
1
read-write
0
PDMA Channel n time-out interrupt Disabled
#0
1
PDMA Channel n time-out interrupt Enabled
#1
TOUTPSC
PDMA_TOUTPSC
PDMA Time-out Prescaler Register
0x430
-1
read-write
n
0x0
0x0
TOUTPSC0
PDMA Channel 0 Time-out Clock Source Prescaler Bits
0
3
read-write
0
PDMA channel 0 time-out clock source is HCLK/28
#000
1
PDMA channel 0 time-out clock source is HCLK/29
#001
2
PDMA channel 0 time-out clock source is HCLK/210
#010
3
PDMA channel 0 time-out clock source is HCLK/211
#011
4
PDMA channel 0 time-out clock source is HCLK/212
#100
5
PDMA channel 0 time-out clock source is HCLK/213
#101
6
PDMA channel 0 time-out clock source is HCLK/214
#110
7
PDMA channel 0 time-out clock source is HCLK/215
#111
TOUTPSC1
PDMA Channel 1 Time-out Clock Source Prescaler Bits
4
3
read-write
0
PDMA channel 1 time-out clock source is HCLK/28
#000
1
PDMA channel 1 time-out clock source is HCLK/29
#001
2
PDMA channel 1 time-out clock source is HCLK/210
#010
3
PDMA channel 1 time-out clock source is HCLK/211
#011
4
PDMA channel 1 time-out clock source is HCLK/212
#100
5
PDMA channel 1 time-out clock source is HCLK/213
#101
6
PDMA channel 1 time-out clock source is HCLK/214
#110
7
PDMA channel 1 time-out clock source is HCLK/215
#111
TRGSTS
PDMA_TRGSTS
PDMA Channel Request Status Register
0x40C
-1
read-only
n
0x0
0x0
REQSTS0
PDMA Channel Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
0
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS1
PDMA Channel Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
1
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS2
PDMA Channel Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
2
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS3
PDMA Channel Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
3
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS4
PDMA Channel Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
4
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
RTC
RTC Register Map
RTC
0x0
0x0
0x4
registers
n
0x100
0x4
registers
n
0x110
0x4
registers
n
0x8
0x34
registers
n
CAL
RTC_CAL
RTC Calendar Loading Register
0x10
-1
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit (0~9)
0
4
read-write
MON
1-Month Calendar Digit (0~9)
8
4
read-write
TENDAY
10-Day Calendar Digit (0~3)
4
2
read-write
TENMON
10-Month Calendar Digit (0~1)
12
1
read-write
TENYEAR
10-Year Calendar Digit (0~9)
20
4
read-write
YEAR
1-Year Calendar Digit (0~9)
16
4
read-write
CALM
RTC_CALM
RTC Calendar Alarm Register
0x20
-1
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit of Alarm Setting (0~9)
0
4
read-write
MON
1-Month Calendar Digit of Alarm Setting (0~9)
8
4
read-write
TENDAY
10-Day Calendar Digit of Alarm Setting (0~3)
4
2
read-write
TENMON
10-Month Calendar Digit of Alarm Setting (0~1)
12
1
read-write
TENYEAR
10-Year Calendar Digit of Alarm Setting (0~9)
20
4
read-write
YEAR
1-Year Calendar Digit of Alarm Setting (0~9)
16
4
read-write
CAMSK
RTC_CAMSK
RTC Calendar Alarm Mask Register
0x38
-1
read-write
n
0x0
0x0
MDAY
Mask 1-Day Calendar Digit of Alarm Setting (0~9)
0
1
read-write
MMON
Mask 1-Month Calendar Digit of Alarm Setting (0~9)
2
1
read-write
MTENDAY
Mask 10-Day Calendar Digit of Alarm Setting (0~3)
1
1
read-write
MTENMON
Mask 10-Month Calendar Digit of Alarm Setting (0~1)
3
1
read-write
MTENYEAR
Mask 10-Year Calendar Digit of Alarm Setting (0~9)
5
1
read-write
MYEAR
Mask 1-Year Calendar Digit of Alarm Setting (0~9)
4
1
read-write
CLKFMT
RTC_CLKFMT
RTC Time Scale Selection Register
0x14
-1
read-write
n
0x0
0x0
DCOMPEN
Dynamic Compensation Enable Bit
16
1
read-write
0
Dynamic Compensation Disabled
#0
1
Dynamic Compensation Enabled
#1
_24HEN
24-hour / 12-hour Time Scale Selection
Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
0
1
read-write
0
12-hour time scale with AM and PM indication selected
#0
1
24-hour time scale selected
#1
DSTCTL
RTC_DSTCTL
RTC Daylight Saving Time Control Register
0x110
-1
read-write
n
0x0
0x0
ADDHR
Add 1 Hour
0
1
read-write
0
No effect
#0
1
Indicates RTC hour digit has been added one hour for summer time change
#1
DSBAK
Daylight Saving Back
2
1
read-write
0
Daylight Saving Change is not performed
#0
1
Daylight Saving Change is performed
#1
SUBHR
Subtract 1 Hour
1
1
read-write
0
No effect
#0
1
Indicates RTC hour digit has been subtracted one hour for winter time change
#1
FREQADJ
RTC_FREQADJ
RTC Frequency Compensation Register
0x8
-1
read-write
n
0x0
0x0
FCRBUSY
Frequency Compensation Register Write Operation Busy (Read Only)
Note: This bit is only used when DCOMPEN(RTC_CLKFMT[16]) enabled.
31
1
read-only
0
The new register write operation is acceptable
#0
1
The last write operation is in progress and new register write operation prohibited
#1
FRACTION
Fraction Part
Note: Digit in FCR must be expressed as hexadecimal number.
0
6
read-write
INTEGER
Integer Part
8
5
read-write
0
Integer part of detected value is 32752
#00000
1
Integer part of detected value is 32753
#00001
2
Integer part of detected value is 32754
#00010
3
Integer part of detected value is 32755
#00011
4
Integer part of detected value is 32756
#00100
5
Integer part of detected value is 32757
#00101
6
Integer part of detected value is 32758
#00110
7
Integer part of detected value is 32759
#00111
8
Integer part of detected value is 32760
#01000
9
Integer part of detected value is 32761
#01001
10
Integer part of detected value is 32762
#01010
11
Integer part of detected value is 32763
#01011
12
Integer part of detected value is 32764
#01100
13
Integer part of detected value is 32765
#01101
14
Integer part of detected value is 32766
#01110
15
Integer part of detected value is 32767
#01111
16
Integer part of detected value is 32768
#10000
17
Integer part of detected value is 32769
#10001
18
Integer part of detected value is 32770
#10010
19
Integer part of detected value is 32771
#10011
20
Integer part of detected value is 32772
#10100
21
Integer part of detected value is 32773
#10101
22
Integer part of detected value is 32774
#10110
23
Integer part of detected value is 32775
#10111
24
Integer part of detected value is 32776
#11000
25
Integer part of detected value is 32777
#11001
26
Integer part of detected value is 32778
#11010
27
Integer part of detected value is 32779
#11011
28
Integer part of detected value is 32780
#11100
29
Integer part of detected value is 32781
#11101
30
Integer part of detected value is 32782
#11110
31
Integer part of detected value is 32783
#11111
INIT
RTC_INIT
RTC Initiation Register
0x0
-1
read-write
n
0x0
0x0
ACTIVE
RTC Active Status (Read Only)
0
1
read-only
0
RTC is at reset state
#0
1
RTC is at normal active state
#1
INIT
RTC Initiation (Write Only)
When RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leave reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
The INIT is a write-only field and read value will be always 0.
1
31
write-only
INTEN
RTC_INTEN
RTC Interrupt Enable Register
0x28
-1
read-write
n
0x0
0x0
ALMIEN
Alarm Interrupt Enable Bit
Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
0
1
read-write
0
RTC Alarm interrupt Disabled
#0
1
RTC Alarm interrupt Enabled
#1
TICKIEN
Time Tick Interrupt Enable Bit
Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
1
1
read-write
0
RTC Time Tick interrupt Disabled
#0
1
RTC Time Tick interrupt Enabled
#1
INTSTS
RTC_INTSTS
RTC Interrupt Status Register
0x2C
-1
read-write
n
0x0
0x0
ALMIF
RTC Alarm Interrupt Flag
Note: Write 1 to clear this bit.
0
1
read-write
0
Alarm condition is not matched
#0
1
Alarm condition is matched
#1
TICKIF
RTC Time Tick Interrupt Flag
Note: Write 1 to clear this bit.
1
1
read-write
0
Tick condition did not occur
#0
1
Tick condition occurred
#1
LEAPYEAR
RTC_LEAPYEAR
RTC Leap Year Indicator Register
0x24
-1
read-only
n
0x0
0x0
LEAPYEAR
Leap Year Indication (Read Only)
0
1
read-only
0
This year is not a leap year
#0
1
This year is leap year
#1
LXTCTL
RTC_LXTCTL
RTC 32.768 kHz Oscillator Control Register
0x100
-1
read-write
n
0x0
0x0
C32KS
Clock 32K Source Selection:
7
1
read-write
0
Internal 32K clock is from 32K crystal
#0
1
Internal 32K clock is from LIRC32K
#1
GAIN
Oscillator Gain Option
User can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption.
Note: Please refer to the M253 Datasheet for detailed information about LXT electrical characteristics.
1
2
read-write
0
L0 mode
000
1
L1 mode
001
10
L2 mode
010
11
L3 mode
011
TALM
RTC_TALM
RTC Time Alarm Register
0x1C
-1
read-write
n
0x0
0x0
HR
1-Hour Time Digit of Alarm Setting (0~9)
16
4
read-write
MIN
1-Min Time Digit of Alarm Setting (0~9)
8
4
read-write
SEC
1-Sec Time Digit of Alarm Setting (0~9)
0
4
read-write
TENHR
10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
20
2
read-write
TENMIN
10-Min Time Digit of Alarm Setting (0~5)
12
3
read-write
TENSEC
10-Sec Time Digit of Alarm Setting (0~5)
4
3
read-write
TAMSK
RTC_TAMSK
RTC Time Alarm Mask Register
0x34
-1
read-write
n
0x0
0x0
MHR
Mask 1-Hour Time Digit of Alarm Setting (0~9)
4
1
read-write
MMIN
Mask 1-Min Time Digit of Alarm Setting (0~9)
2
1
read-write
MSEC
Mask 1-Sec Time Digit of Alarm Setting (0~9)
0
1
read-write
MTENHR
Mask 10-Hour Time Digit of Alarm Setting (0~2)
5
1
read-write
MTENMIN
Mask 10-Min Time Digit of Alarm Setting (0~5)
3
1
read-write
MTENSEC
Mask 10-Sec Time Digit of Alarm Setting (0~5)
1
1
read-write
TICK
RTC_TICK
RTC Time Tick Register
0x30
-1
read-write
n
0x0
0x0
TICK
Time Tick Register
These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
Note: If C32KS(RTC_LXTCTL[7]) is 1, the tick period will become 1, 1/3, 1/5, 1/10, 1/19, 1/38, 1/75, 1/150 second. But the 1/3, 1/5, 1/10, 1/19, 1/38 are not uniform output.
0
3
read-write
0
Time tick is 1 second
#000
1
Time tick is 1/2 second
#001
2
Time tick is 1/4 second
#010
3
Time tick is 1/8 second
#011
4
Time tick is 1/16 second
#100
5
Time tick is 1/32 second
#101
6
Time tick is 1/64 second
#110
7
Time tick is 1/128 second
#111
TIME
RTC_TIME
RTC Time Loading Register
0xC
-1
read-write
n
0x0
0x0
HR
1-Hour Time Digit (0~9)
16
4
read-write
MIN
1-Min Time Digit (0~9)
8
4
read-write
SEC
1-Sec Time Digit (0~9)
0
4
read-write
TENHR
10-Hour Time Digit (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
20
2
read-write
TENMIN
10-Min Time Digit (0~5)
12
3
read-write
TENSEC
10-Sec Time Digit (0~5)
4
3
read-write
WEEKDAY
RTC_WEEKDAY
RTC Day of the Week Register
0x18
-1
read-write
n
0x0
0x0
WEEKDAY
Day of the Week Register
0
3
read-write
0
Sunday
#000
1
Monday
#001
2
Tuesday
#010
3
Wednesday
#011
4
Thursday
#100
5
Friday
#101
6
Saturday
#110
7
Reserved.
#111
SCS
SYST_SCR Register Map
SYST_SCR
0x0
0x10
0xC
registers
n
0xD04
0x14
registers
n
0xD1C
0xC
registers
n
AIRCR
AIRCR
Application Interrupt and Reset Control Register
0xD0C
-1
read-write
n
0x0
0x0
ENDIANNESS
Data Endianness (Read Only)
15
1
read-only
0
Little-endian
#0
1
Big-endian
#1
PRIS
Priority Secure Exceptions Bit
14
1
read-write
0
Priority ranges of Secure and Non-secure exceptions are identical.1 = Non-secure exceptions are de-prioritized
#0
SYSRESETREQ
System Reset Request Bit
Writing This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested
This bit is write only and self-cleared as part of the reset sequence.
2
1
read-write
SYSRESETREQS
System Reset Request Secure Only Bit
3
1
read-write
0
SYSRESETREQ functionality is available to both security states.1 = SYSRESETREQ functionality is available to secure state only
#0
VECTCLRACTIVE
Exception Active Status Clear Bit
Setting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions
This bit is write only and can only be written when the core is halted.
Note: It is the debugger's responsibility to re-initialize the stack.
Note: This bit reads as zero.
1
1
read-write
VECTORKEY
Register Access Key
When writing this register, this field should be 0x05FA, otherwise the write action will be ignored.
The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.
16
16
read-write
CCR
CCR
Configuration and Control Register
0xD14
-1
read-write
n
0x0
0x0
ICSR
ICSR
Interrupt Control and State Register
0xD04
-1
read-write
n
0x0
0x0
ISRPENDING
Interrupt Pending Flag, Excluding NMI and Faults (Read Only)
22
1
read-only
0
Interrupt not pending
#0
1
Interrupt pending
#1
ISRPREEMPT
Interrupt Preempt Bit (Read Only)
If set, a pending exception will be serviced on exit from the debug halt state.
23
1
read-only
NMIPENDCLR
NMI Bit-pending Bit
Note: If AIRCR.BFHFNMINS is 0, this bit is RAZ/WI from Non-secure state.
30
1
read-write
0
No effect
#0
1
Clear pending status
#1
NMIPENDSET
NMI Set-pending Bit
Write Operation:
Note: If AIRCR.BFHFNMINS is 0, this bit is RAZ/WI from Non-secure state.
31
1
read-write
0
No effect.
NMI exception is not pending
#0
1
Changes NMI exception state to pending.
NMI exception is pending
#1
PENDSTCLR
SysTick Exception Clear-pending Bit
Write Operation:
Note: This is a write only bit. To clear the PENDST bit, you must 'write 0 to PENDSTSET and write 1 to PENDSTCLR' at the same time.
25
1
read-write
0
No effect
#0
1
Removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick Exception Set-pending Bit
Write Operation:
26
1
read-write
0
No effect.
SysTick exception is not pending
#0
1
Changes SysTick exception state to pending.
SysTick exception is pending
#1
PENDSVCLR
PendSV Clear-pending Bit
Write Operation:
Note: This is a write only bit. To clear the PENDSV bit, you must 'write 0 to PENDSVSET and write 1 to PENDSVCLR' at the same time.
27
1
read-write
0
No effect
#0
1
Removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV Set-pending Bit
Write Operation:
Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
No effect.
PendSV exception is not pending
#0
1
Changes PendSV exception state to pending.
PendSV exception is pending
#1
VECTACTIVE
Number of the Current Active Exception (Read Only)
0
8
read-only
0
Thread mode
0
VECTPENDING
Number of the Highest Pended Exception (Read Only)
12
8
read-only
0
no pending exceptions
0
SCR
SCR
System Control Register
0xD10
-1
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending
When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded
#0
1
Enabled events and all interrupts, including disabled interrupts, can wake up the processor
#1
SLEEPDEEP
Processor Deep Sleep and Sleep Mode Selection
Control Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode.
2
1
read-write
0
Sleep
#0
1
Deep sleep
#1
SLEEPONEXIT
Sleep-on-exit Enable Control
This bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.
Note: Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
0
Do not sleep when returning to Thread mode
#0
1
Enter sleep, or deep sleep, on return from an ISR to Thread mode
#1
SHCSR
SHCSR
System Handler Control and State Register
0xD24
-1
read-write
n
0x0
0x0
HARDFAULTPENDED
HardFault Exception Pended State
This bit indicates and allows modification of the pending state of
the HardFault exception corresponding to the selected Security state.
This bit is banked between Security states.
The possible values of this bit are:
21
1
read-write
0
HardFault exception not pending for the selected Security state
#0
1
HardFault exception pending for the selected Security state
#1
SHPR2
SHPR2
System Handler Priority Register 2
0xD1C
-1
read-write
n
0x0
0x0
PRI_11
Priority of System Handler 11 - SVCall
'0' denotes the highest priority and '3' denotes the lowest priority.
30
2
read-write
SHPR3
SHPR3
System Handler Priority Register 3
0xD20
-1
read-write
n
0x0
0x0
PRI_14
Priority of System Handler 14 - PendSV
'0' denotes the highest priority and '3' denotes the lowest priority.
22
2
read-write
PRI_15
Priority of System Handler 15 - SysTick
'0' denotes the highest priority and '3' denotes the lowest priority.
30
2
read-write
SYST_CTRL
SYST_CTRL
SysTick Control and Status Register
0x10
-1
read-write
n
0x0
0x0
CLKSRC
System Tick Clock Source Selection
2
1
read-write
0
Clock source is the (optional) external reference clock
#0
1
Core clock used for SysTick
#1
COUNTFLAG
System Tick Counter Flag
Returns 1 if timer counted to 0 since last time this register was read.
COUNTFLAG is set by a count transition from 1 to 0.
COUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-write
ENABLE
System Tick Counter Enabled
0
1
read-write
0
Counter Disabled
#0
1
Counter will operate in a multi-shot manner
#1
TICKINT
System Tick Interrupt Enabled
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended
#1
SYST_LOAD
SYST_LOAD
SysTick Reload Value Register
0x14
-1
read-write
n
0x0
0x0
RELOAD
System Tick Reload Value
The value to load into the Current Value register when the counter reaches 0.
0
24
read-write
SYST_VAL
SYST_VAL
SysTick Current Value Register
0x18
-1
read-write
n
0x0
0x0
CURRENT
System Tick Current Value
Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
0
24
read-write
VTOR
VTOR
Vector Table Offset Register
0xD08
-1
read-write
n
0x0
0x0
TBLOFF
Table Offset Bits
The vector table address for the selected Security state.
9
23
read-write
SPI0
SPI Register Map
SPI
0x0
0x0
0x18
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
0x60
0xC
registers
n
SPIx_CLKDIV
SPIx_CLKDIV
SPI Clock Divider Register
0x4
-1
read-write
n
0x0
0x0
DIVIDER
Clock Divider
The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.
where
is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
Note1: Not supported in I2S mode.
Note2: The time interval must be larger than or equal 8 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register.
0
9
read-write
SPIx_CTL
SPIx_CTL
SPI Control Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity
3
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
DATDIR
Data Port Direction Control
This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
20
1
read-write
0
SPI data is input direction
#0
1
SPI data is output direction
#1
DWIDTH
Data Width
This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.
Note: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically.
8
5
read-write
HALFDPX
SPI Half-duplex Transfer Enable Bit
This bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
14
1
read-write
0
SPI operates in full-duplex transfer
#0
1
SPI operates in half-duplex transfer
#1
LSB
Send LSB First
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
#1
REORDER
Byte Reorder Function Enable Bit
Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXNEG
Receive on Negative Edge
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
RXONLY
Receive-only Mode Enable Bit (Master Only)
This bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
15
1
read-write
0
Receive-only mode Disabled
#0
1
Receive-only mode Enabled
#1
SLAVE
Slave Mode Control
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Control Enable Bit
In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.
Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
0
1
read-write
0
Transfer control Disabled
#0
1
Transfer control Enabled
#1
SUSPITV
Suspend Interval (Master Only)
The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.
(SUSPITV + 0.5) * period of SPICLK clock cycle
Example:
4
4
read-write
TXNEG
Transmit on Negative Edge
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SPI bus clock
#1
UNITIEN
Unit Transfer Interrupt Enable Bit
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
SPIx_FIFOCTL
SPIx_FIFOCTL
SPI FIFO Control Register
0x10
-1
read-write
n
0x0
0x0
RXFBCLR
Receive FIFO Buffer Clear
Note: The RX shift register will not be cleared.
8
1
read-write
0
No effect
#0
1
Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
RXOVIEN
Receive FIFO Overrun Interrupt Enable Bit
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Receive Reset
0
1
read-write
0
No effect
#0
1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not
#1
RXTH
Receive FIFO Threshold
If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
24
3
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Bit
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-out Interrupt Enable Bit
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXFBCLR
Transmit FIFO Buffer Clear
Note: The TX shift register will not be cleared.
9
1
read-write
0
No effect
#0
1
Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
TXRST
Transmit Reset
Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
1
1
read-write
0
No effect
#0
1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
28
3
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
TX Underflow Interrupt Enable Bit
When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt.
7
1
read-write
0
Slave TX underflow interrupt Disabled
#0
1
Slave TX underflow interrupt Enabled
#1
TXUFPOL
TX Underflow Data Polarity
Note 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
Note 2: This bit should be set as 0 in I2S mode.
Note 3: When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
6
1
read-write
0
The SPI data out is keep 0 if there is TX underflow event in Slave mode
#0
1
The SPI data out is keep 1 if there is TX underflow event in Slave mode
#1
SPIx_I2SCLK
SPIx_I2SCLK
I2S Clock Divider Control Register
0x64
-1
read-write
n
0x0
0x0
BCLKDIV
Bit Clock Divider
The I2S controller will generate bit clock in Master mode. The clock frequency of bit clock , fBCLK, is determined by the following expression:
where
is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by .
The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.
Note: The time interval must be larger than or equal 8 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register.
8
10
read-write
I2SMODE
I2S Clock Divider Number Selection for I2S Mode and SPI Mode
User sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set.
User needs to set I2SMODE before I2SEN (SPIx_I2SCTL[0]) or SPIEN (SPIx_CTL[0]) is enabled.
24
1
read-write
0
The frequency of peripheral clock is set to SPI mode
#0
1
The frequency of peripheral clock is set to I2S mode
#1
I2SSLAVE
I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode
User sets I2SSLAVE to set frequency of peripheral clock of I2S master mode and I2S slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set.
I2SSLAVE needs to set before I2SEN (SPIx_I2SCTL[0]) is enabled.
25
1
read-write
0
The frequency of peripheral clock is set to I2S master mode
#0
1
The frequency of peripheral clock is set to I2S slave mode
#1
MCLKDIV
Master Clock Divider
If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions:
where
is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate.
0
7
read-write
SPIx_I2SCTL
SPIx_I2SCTL
I2S Control Register
0x60
-1
read-write
n
0x0
0x0
FORMAT
Data Format Selection
28
2
read-write
0
I2S data format
#00
1
MSB justified data format
#01
2
PCM mode A
#10
3
PCM mode B
#11
I2SEN
I2S Controller Enable Bit
Note 1: If enabling this bit, I2Sx_BCLK will start to output in Master mode.
Note 2: Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.
0
1
read-write
0
I2S mode Disabled
#0
1
I2S mode Enabled
#1
LZCEN
Left Channel Zero Cross Detection Enable Bit
If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation.
17
1
read-write
0
Left channel zero cross detection Disabled
#0
1
Left channel zero cross detection Enabled
#1
LZCIEN
Left Channel Zero Cross Interrupt Enable Bit
Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs.
25
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
MCLKEN
Master Clock Enable Bit
If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
15
1
read-write
0
Master clock Disabled
#0
1
Master clock Enabled
#1
MONO
Monaural Data
6
1
read-write
0
Data is stereo format
#0
1
Data is monaural format
#1
MUTE
Transmit Mute Enable Bit
3
1
read-write
0
Transmit data is shifted from buffer
#0
1
Transmit channel zero
#1
ORDER
Stereo Data Order in FIFO
7
1
read-write
0
Left channel data at high byte
#0
1
Left channel data at low byte
#1
RXEN
Receive Enable Bit
2
1
read-write
0
Data receive Disabled
#0
1
Data receive Enabled
#1
RXLCH
Receive Left Channel Enable Bit
23
1
read-write
0
Receive right channel data in Mono mode
#0
1
Receive left channel data in Mono mode
#1
RZCEN
Right Channel Zero Cross Detection Enable Bit
If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation.
16
1
read-write
0
Right channel zero cross detection Disabled
#0
1
Right channel zero cross detection Enabled
#1
RZCIEN
Right Channel Zero Cross Interrupt Enable Bit
Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs.
24
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
SLAVE
Slave Mode
I2S can operate as master or slave. For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.
8
1
read-write
0
Master mode
#0
1
Slave mode
#1
SLVERRIEN
Bit Number Error Interrupt Enable Bit for Slave Mode
Interrupt occurs if this bit is set to 1 and bit number error event occurs.
31
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXEN
Transmit Enable Bit
1
1
read-write
0
Data transmit Disabled
#0
1
Data transmit Enabled
#1
WDWIDTH
Word Width
4
2
read-write
0
data size is 8-bit
#00
1
data size is 16-bit
#01
2
data size is 24-bit
#10
3
data size is 32-bit
#11
SPIx_I2SSTS
SPIx_I2SSTS
I2S Status Register
0x68
-1
read-write
n
0x0
0x0
I2SENSTS
I2S Enable Status (Read Only)
Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.
15
1
read-only
0
The SPI/I2S control logic is disabled
#0
1
The SPI/I2S control logic is enabled
#1
LZCIF
Left Channel Zero Cross Interrupt Flag
21
1
read-write
0
No zero cross event occurred on left channel
#0
1
Zero cross event occurred on left channel
#1
RIGHT
Right Channel (Read Only)
This bit indicates the current transmit data is belong to which channel.
4
1
read-only
0
Left channel
#0
1
Right channel
#1
RXCNT
Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
24
3
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
11
1
read-write
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
RZCIF
Right Channel Zero Cross Interrupt Flag
20
1
read-write
0
No zero cross event occurred on right channel
#0
1
Zero cross event occurred on right channel
#1
SLVERRIF
Bit Number Error Interrupt Flag for Slave Mode
Note: This bit will be cleared by writing 1 to it.
22
1
read-write
0
No bit number error event occurred
#0
1
Bit number error event occurred
#1
TXCNT
Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
28
3
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)
Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
Transmit FIFO Underflow Interrupt Flag
When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
19
1
read-write
SPIx_PDMACTL
SPIx_PDMACTL
SPI PDMA Control Register
0xC
-1
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0
#1
RXPDMAEN
Receive PDMA Enable Bit
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
Transmit PDMA Enable Bit
Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
SPIx_RX
SPIx_RX
SPI Data Receive Register
0x30
-1
read-only
n
0x0
0x0
RX
Data Receive Register (Read Only)
There are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
0
32
read-only
SPIx_SSCTL
SPIx_SSCTL
SPI Slave Select Control Register
0x8
-1
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit (Master Only)
3
1
read-write
0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0])
#0
1
Automatic slave selection function Enabled
#1
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit
8
1
read-write
0
Slave mode bit count error interrupt Disabled
#0
1
Slave mode bit count error interrupt Enabled
#1
SLVURIEN
Slave Mode TX Under Run Interrupt Enable Bit
9
1
read-write
0
Slave mode TX under run interrupt Disabled
#0
1
Slave mode TX under run interrupt Enabled
#1
SS
Slave Selection Control (Master Only)
If AUTOSS bit is cleared to 0,
0
1
read-write
0
set the SPIx_SS line to inactive state.
Keep the SPIx_SS line at inactive state
#0
1
set the SPIx_SS line to active state.
SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit
12
1
read-write
0
Slave select active interrupt Disabled
#0
1
Slave select active interrupt Enabled
#1
SSACTPOL
Slave Selection Active Polarity
This bit defines the active polarity of slave selection signal (SPIx_SS).
2
1
read-write
0
The slave selection signal SPIx_SS is active low
#0
1
The slave selection signal SPIx_SS is active high
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit
13
1
read-write
0
Slave select inactive interrupt Disabled
#0
1
Slave select inactive interrupt Enabled
#1
SPIx_STATUS
SPIx_STATUS
SPI Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
0
1
read-only
0
SPI controller is in idle state
#0
1
SPI controller is in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
11
1
read-write
0
No FIFO is overrun
#0
1
Receive FIFO is overrun
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Bit Count Error Interrupt Flag
In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatched with DWIDTH, this interrupt flag will be set to 1.
Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
6
1
read-write
0
No Slave mode bit count error event
#0
1
Slave mode bit count error event occurred
#1
SLVURIF
Slave Mode TX Under Run Interrupt Flag
In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
Note: This bit will be cleared by writing 1 to it.
7
1
read-write
0
No Slave TX under run event
#0
1
Slave TX under run event occurred
#1
SPIENSTS
SPI Enable Status (Read Only)
Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
15
1
read-only
0
SPI controller Disabled
#0
1
SPI controller Enabled
#1
SSACTIF
Slave Select Active Interrupt Flag
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
2
1
read-write
0
Slave select active interrupt was cleared or not occurred
#0
1
Slave select active interrupt event occurred
#1
SSINAIF
Slave Select Inactive Interrupt Flag
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
3
1
read-write
0
Slave select inactive interrupt was cleared or not occurred
#0
1
Slave select inactive interrupt event occurred
#1
SSLINE
Slave Select Line Bus Status (Read Only)
Note: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)
Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
TX Underflow Interrupt Flag
When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
Note 1: This bit will be cleared by writing 1 to it.
Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
SPIx_TX
SPIx_TX
SPI Data Transmit Register
0x20
-1
write-only
n
0x0
0x0
TX
Data Transmit Register
The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.
In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section
Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
0
32
write-only
SYS
SYS Register Map
SYS
0x0
0x0
0x20
registers
n
0x100
0x10
registers
n
0x1EC
0x4
registers
n
0x1F8
0x8
registers
n
0x24
0x4
registers
n
0x30
0x18
registers
n
0x58
0x8
registers
n
0x80
0xC
registers
n
0x94
0x4
registers
n
0xC0
0x4
registers
n
0xD0
0x8
registers
n
0xF0
0xC
registers
n
ALTCTL
SYS_ALTCTL
Miscellaneous Control Register
0x14
-1
read-write
n
0x0
0x0
CANFD0CKSTP
CANFD0 Clock Stop Acknowledgement (Read Only)
7
1
read-only
0
CANFD0 clock didn't stop
#0
1
CANFD0 clock stop
#1
CANFD0_PDEN
CANFD0 Power Down Enable Bit
6
1
read-write
0
CANFD0 Power-down mode Disabled
#0
1
CANFD0 Power-down mode Enabled
#1
BODCTL
SYS_BODCTL
Brown-out Detector Control Register
0x18
-1
read-write
n
0x0
0x0
BODDGSEL
Brown-out Detector Output De-glitch Time Select (Write Protect)
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
8
3
read-write
0
BOD output is sampled by LIRC
#000
1
4 system clock (HCLK)
#001
2
8 system clock (HCLK)
#010
3
16 system clock (HCLK)
#011
4
32 system clock (HCLK)
#100
5
64 system clock (HCLK)
#101
6
128 system clock (HCLK)
#110
7
256 system clock (HCLK)
#111
BODEN
Brown-out Detector Enable Bit (Write Protect)
The default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]).
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by power on reset.
0
1
read-write
0
Brown-out Detector function Disabled
#0
1
Brown-out Detector function Enabled
#1
BODIF
Brown-out Detector Interrupt Flag
Note: Write 1 to clear this bit to 0.
4
1
read-write
0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting
#0
1
When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled
#1
BODLPM
Brown-out Detector Low Power Mode (Write Protect)
Note 1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
Note 2: For BOD low power mode to be active, LVREN must be set to 1
Note 3: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
BOD operate in normal mode (default)
#0
1
BOD Low Power mode Enabled
#1
BODOUT
Brown-out Detector Output Status
It means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function is disabled. This bit always responds 0000.
6
1
read-write
0
Brown-out Detector output status is 0
#0
1
Brown-out Detector output status is 1
#1
BODRSTEN
Brown-out Reset Enable Bit (Write Protect)
The default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit.
Note 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 3: Reset by power on reset.
3
1
read-write
0
Brown-out 'INTERRUPT' function Enabled
#0
1
Brown-out 'RESET' function Enabled
#1
BODVL
Brown-out Detector Threshold Voltage Selection (Write Protect)
The default value is set by Flash controller user configuration register CBOV (CONFIG0 [23:21]).
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by power on reset.
16
3
read-write
0
Reserved.
#000
1
Brown-Out Detector threshold voltage is 1.8V
#001
2
Brown-Out Detector threshold voltage is 2.0V
#010
3
Brown-Out Detector threshold voltage is 2.4V
#011
4
Brown-Out Detector threshold voltage is 2.7V
#100
5
Brown-Out Detector threshold voltage is 3.0V
#101
6
Brown-Out Detector threshold voltage is 3.7V
#110
7
Brown-Out Detector threshold voltage is 4.4V
#111
LVRDGSEL
LVR Output De-glitch Time Select (Write Protect)
Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
Note 2: The MIRC is enabled automatically when LVRDGSEL is not 000 and LVREN is 1.
12
3
read-write
0
Without de-glitch function
#000
1
4 MIRC clock (4 MHz), 1 us
#001
2
8 MIRC clock (4 MHz), 2 us
#010
3
16 MIRC clock (4 MHz), 4 us
#011
4
32 MIRC clock (4 MHz), 8 us
#100
5
64 MIRC clock (4 MHz), 16 us
#101
6
128 MIRC clock (4 MHz), 32 us
#110
7
256 MIRC clock (4 MHz), 64 us
#111
LVREN
Low Voltage Reset Enable Bit (Write Protect)
The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.
Note 1: After enabling the bit, the LVR function will be active with 3ms delay for LVR output stable (default).
Note 2: For BOD low power mode to be active, this bit must be set to 1.
Note 3: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
Low Voltage Reset function Disabled
#0
1
Low Voltage Reset function Enabled
#1
GPA_MFOS
SYS_GPA_MFOS
GPIOA Multiple Function Output Select Register
0x80
-1
read-write
n
0x0
0x0
MFOS0
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
0
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
MFOS1
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
1
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
MFOS10
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
10
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
MFOS11
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
11
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
MFOS12
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
12
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
MFOS13
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
13
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
MFOS14
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
14
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
MFOS15
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
15
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
MFOS2
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
2
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
MFOS3
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
3
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
MFOS4
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
4
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
MFOS5
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
5
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
MFOS6
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
6
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
MFOS7
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
7
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
MFOS8
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
8
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
MFOS9
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select
This bit used to select multiple function pin output mode type for Px.n pin
9
1
read-write
0
Multiple function pin output mode type is Push-pull mode
#0
1
Multiple function pin output mode type is Open-drain mode
#1
GPA_MFPH
SYS_GPA_MFPH
GPIOA High Byte Multiple Function Control Register
0x34
-1
read-write
n
0x0
0x0
PA10MFP
PA.10 Multi-function Pin Selection
8
4
read-write
PA11MFP
PA.11 Multi-function Pin Selection
12
4
read-write
PA12MFP
PA.12 Multi-function Pin Selection
16
4
read-write
PA13MFP
PA.13 Multi-function Pin Selection
20
4
read-write
PA14MFP
PA.14 Multi-function Pin Selection
24
4
read-write
PA15MFP
PA.15 Multi-function Pin Selection
28
4
read-write
PA8MFP
PA.8 Multi-function Pin Selection
0
4
read-write
PA9MFP
PA.9 Multi-function Pin Selection
4
4
read-write
GPA_MFPL
SYS_GPA_MFPL
GPIOA Low Byte Multiple Function Control Register
0x30
-1
read-write
n
0x0
0x0
PA0MFP
PA.0 Multi-function Pin Selection
0
4
read-write
PA1MFP
PA.1 Multi-function Pin Selection
4
4
read-write
PA2MFP
PA.2 Multi-function Pin Selection
8
4
read-write
PA3MFP
PA.3 Multi-function Pin Selection
12
4
read-write
PA4MFP
PA.4 Multi-function Pin Selection
16
4
read-write
PA5MFP
PA.5 Multi-function Pin Selection
20
4
read-write
PA6MFP
PA.6 Multi-function Pin Selection
24
4
read-write
PA7MFP
PA.7 Multi-function Pin Selection
28
4
read-write
GPB_MFOS
SYS_GPB_MFOS
GPIOB Multiple Function Output Select Register
0x84
-1
read-write
n
0x0
0x0
GPB_MFPH
SYS_GPB_MFPH
GPIOB High Byte Multiple Function Control Register
0x3C
-1
read-write
n
0x0
0x0
PB10MFP
PB.10 Multi-function Pin Selection
8
4
read-write
PB11MFP
PB.11 Multi-function Pin Selection
12
4
read-write
PB12MFP
PB.12 Multi-function Pin Selection
16
4
read-write
PB13MFP
PB.13 Multi-function Pin Selection
20
4
read-write
PB14MFP
PB.14 Multi-function Pin Selection
24
4
read-write
PB15MFP
PB.15 Multi-function Pin Selection
28
4
read-write
PB8MFP
PB.8 Multi-function Pin Selection
0
4
read-write
PB9MFP
PB.9 Multi-function Pin Selection
4
4
read-write
GPB_MFPL
SYS_GPB_MFPL
GPIOB Low Byte Multiple Function Control Register
0x38
-1
read-write
n
0x0
0x0
PB0MFP
PB.0 Multi-function Pin Selection
0
4
read-write
PB1MFP
PB.1 Multi-function Pin Selection
4
4
read-write
PB2MFP
PB.2 Multi-function Pin Selection
8
4
read-write
PB3MFP
PB.3 Multi-function Pin Selection
12
4
read-write
PB4MFP
PB.4 Multi-function Pin Selection
16
4
read-write
PB5MFP
PB.5 Multi-function Pin Selection
20
4
read-write
PB6MFP
PB.6 Multi-function Pin Selection
24
4
read-write
PB7MFP
PB.7 Multi-function Pin Selection
28
4
read-write
GPC_MFOS
SYS_GPC_MFOS
GPIOC Multiple Function Output Select Register
0x88
-1
read-write
n
0x0
0x0
GPC_MFPH
SYS_GPC_MFPH
GPIOC High Byte Multiple Function Control Register
0x44
-1
read-write
n
0x0
0x0
PC10MFP
PC.10 Multi-function Pin Selection
8
4
read-write
PC11MFP
PC.11 Multi-function Pin Selection
12
4
read-write
PC12MFP
PC.12 Multi-function Pin Selection
16
4
read-write
PC13MFP
PC.13 Multi-function Pin Selection
20
4
read-write
PC14MFP
PC.14 Multi-function Pin Selection
24
4
read-write
PC15MFP
PC.15 Multi-function Pin Selection
28
4
read-write
PC8MFP
PC.8 Multi-function Pin Selection
0
4
read-write
PC9MFP
PC.9 Multi-function Pin Selection
4
4
read-write
GPC_MFPL
SYS_GPC_MFPL
GPIOC Low Byte Multiple Function Control Register
0x40
-1
read-write
n
0x0
0x0
PC0MFP
PC.0 Multi-function Pin Selection
0
4
read-write
PC1MFP
PC.1 Multi-function Pin Selection
4
4
read-write
PC2MFP
PC.2 Multi-function Pin Selection
8
4
read-write
PC3MFP
PC.3 Multi-function Pin Selection
12
4
read-write
PC4MFP
PC.4 Multi-function Pin Selection
16
4
read-write
PC5MFP
PC.5 Multi-function Pin Selection
20
4
read-write
PC6MFP
PC.6 Multi-function Pin Selection
24
4
read-write
PC7MFP
PC.7 Multi-function Pin Selection
28
4
read-write
GPF_MFOS
SYS_GPF_MFOS
GPIOF Multiple Function Output Select Register
0x94
-1
read-write
n
0x0
0x0
GPF_MFPH
SYS_GPF_MFPH
GPIOF High Byte Multiple Function Control Register
0x5C
-1
read-write
n
0x0
0x0
PF10MFP
PF.10 Multi-function Pin Selection
8
4
read-write
PF11MFP
PF.11 Multi-function Pin Selection
12
4
read-write
PF12MFP
PF.12 Multi-function Pin Selection
16
4
read-write
PF13MFP
PF.13 Multi-function Pin Selection
20
4
read-write
PF14MFP
PF.14 Multi-function Pin Selection
24
4
read-write
PF15MFP
PF.15 Multi-function Pin Selection
28
4
read-write
PF8MFP
PF.8 Multi-function Pin Selection
0
4
read-write
PF9MFP
PF.9 Multi-function Pin Selection
4
4
read-write
GPF_MFPL
SYS_GPF_MFPL
GPIOF Low Byte Multiple Function Control Register
0x58
-1
read-write
n
0x0
0x0
PF0MFP
PF.0 Multi-function Pin Selection
0
4
read-write
PF1MFP
PF.1 Multi-function Pin Selection
4
4
read-write
PF2MFP
PF.2 Multi-function Pin Selection
8
4
read-write
PF3MFP
PF.3 Multi-function Pin Selection
12
4
read-write
PF4MFP
PF.4 Multi-function Pin Selection
16
4
read-write
PF5MFP
PF.5 Multi-function Pin Selection
20
4
read-write
PF6MFP
PF.6 Multi-function Pin Selection
24
4
read-write
PF7MFP
PF.7 Multi-function Pin Selection
28
4
read-write
HIRCTRIMCTL
SYS_HIRCTRIMCTL
HIRC Trim Control Register
0xF0
-1
read-write
n
0x0
0x0
BOUNDARY
Boundary Selection
Fill the boundary range from 0x1 to 0x1F. 0x0 is reserved.
Note: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enabled.
16
5
read-write
BOUNDEN
Boundary Enable Bit
9
1
read-write
0
Boundary function Disabled
#0
1
Boundary function Enabled
#1
CESTOPEN
Clock Error Stop Enable Bit
8
1
read-write
0
The trim operation keeps going if clock is inaccurate
#0
1
The trim operation stops if clock is inaccurate
#1
FREQSEL
Trim Frequency Selection
This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.
During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
0
2
read-write
0
Disable HIRC auto trim function
#00
1
Enable HIRC auto trim function and trim HIRC to 48 MHz
#01
2
Reserved.
#10
3
Reserved.
#11
LOOPSEL
Trim Calculation Loop Selection
This field defines that trim value calculation is based on how many reference clocks.
Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
4
2
read-write
0
Trim value calculation is based on average difference in 4 clocks of reference clock
#00
1
Trim value calculation is based on average difference in 8 clocks of reference clock
#01
2
Trim value calculation is based on average difference in 16 clocks of reference clock
#10
3
Trim value calculation is based on average difference in 32 clocks of reference clock
#11
REFCKSEL
Reference Clock Selection
10
1
read-write
0
HIRC trim reference clock is from LXT (32.768 kHz)
#0
1
HIRC trim reference clock is from internal USB synchronous mode
#1
RETRYCNT
Trim Value Update Limitation Count
This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
Once the HIRC locked, the internal trim value update counter will be reset.
If the trim value update counter reached this limitation value and frequency of HIRC is still not locked, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
6
2
read-write
0
Trim retry count limitation is 64 loops
#00
1
Trim retry count limitation is 128 loops
#01
2
Trim retry count limitation is 256 loops
#10
3
Trim retry count limitation is 512 loops
#11
HIRCTRIMIEN
SYS_HIRCTRIMIEN
HIRC Trim Interrupt Enable Register
0xF4
-1
read-write
n
0x0
0x0
CLKEIEN
Clock Error Interrupt Enable Bit
This bit controls if CPU would get an interrupt while clock is inaccurate during auto trim operation.
If this bit is set to1, and CLKERRIF(SYS_HIRCTRIMSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccurate.
2
1
read-write
0
Disable CLKERRIF(SYS_HIRCTRIMSTS[2]) status to trigger an interrupt to CPU
#0
1
Enable CLKERRIF(SYS_HIRCTRIMSTS[2]) status to trigger an interrupt to CPU
#1
TFALIEN
Trim Failure Interrupt Enable Bit
This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency is still not locked on target frequency set by FREQSEL(SYS_HIRCTRIMCTL[1:0]).
If this bit is high and TFAILIF(SYS_HIRCTRIMSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count reached.
1
1
read-write
0
Disable TFAILIF(SYS_HIRCTRIMSTS[1]) status to trigger an interrupt to CPU
#0
1
Enable TFAILIF(SYS_HIRCTRIMSTS[1]) status to trigger an interrupt to CPU
#1
HIRCTRIMSTS
SYS_HIRCTRIMSTS
HIRC Trim Interrupt Status Register
0xF8
-1
read-write
n
0x0
0x0
CLKERIF
Clock Error Interrupt Status
When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccurate.
Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_HIRCTRIMCTL[8]) is set to 1.
If this bit is set and CLKEIEN(SYS_HIRCTRIMIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
Note: Reset by power on reset.
2
1
read-write
0
Clock frequency is accurate
#0
1
Clock frequency is inaccurate
#1
FREQLOCK
HIRC Frequency Lock Status
This bit indicates the HIRC frequency is locked.
This is a status bit and doesn't trigger any interrupt
Write 1 to clear this to 0. This bit will be set automatically if the frequency is locked and the RC_TRIM is enabled.
Note: Reset by power on reset.
0
1
read-write
0
The internal high-speed oscillator frequency is not locked at 48 MHz
#0
1
The internal high-speed oscillator frequency locked at 48 MHz
#1
OVBDIF
Over Boundary Status
When the over boundary function is set, if there occurs the over boundary condition, this flag will be set.
Note: Write 1 to clear this flag.
3
1
read-write
0
Over boundary condition did not occur
#0
1
Over boundary condition occurred
#1
TFAILIF
Trim Failure Interrupt Status
This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency is still not locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically.
If this bit is set and TFAILIEN(SYS_HIRCTRIMIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count reached. Write 1 to clear this to 0.
Note: Reset by power on reset.
1
1
read-write
0
Trim value update limitation count not reached
#0
1
Trim value update limitation count reached and HIRC frequency still not locked
#1
IPRST0
SYS_IPRST0
Peripheral Reset Control Register 0
0x8
-1
read-write
n
0x0
0x0
CHIPRST
Chip One-shot Reset (Write Protect)
Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload.
For the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2.
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by power on reset
0
1
read-write
0
Chip normal operation
#0
1
Chip one-shot reset
#1
CPURST
Processor Core One-shot Reset (Write Protect)
Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
Processor core normal operation
#0
1
Processor core one-shot reset
#1
CRCRST
CRC Calculation Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
CRC calculation controller normal operation
#0
1
CRC calculation controller reset
#1
PDMARST
PDMA Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
PDMA controller normal operation
#0
1
PDMA controller reset
#1
IPRST1
SYS_IPRST1
Peripheral Reset Control Register 1
0xC
-1
read-write
n
0x0
0x0
CANFD0RST
CANFD0 Controller Reset
24
1
read-write
0
CANFD0 controller normal operation
#0
1
CANFD0 controller reset
#1
EADCRST
EADC Controller Reset
28
1
read-write
0
EADC controller normal operation
#0
1
EADC controller reset
#1
GPIORST
GPIO Controller Reset
1
1
read-write
0
GPIO controller normal operation
#0
1
GPIO controller reset
#1
I2C0RST
I2C0 Controller Reset
8
1
read-write
0
I2C0 controller normal operation
#0
1
I2C0 controller reset
#1
I2C1RST
I2C1 Controller Reset
9
1
read-write
0
I2C1 controller normal operation
#0
1
I2C1 controller reset
#1
SPI0RST
SPI0 Controller Reset
13
1
read-write
0
SPI0 controller normal operation
#0
1
SPI0 controller reset
#1
TMR0RST
Timer0 Controller Reset
2
1
read-write
0
Timer0 controller normal operation
#0
1
Timer0 controller reset
#1
TMR1RST
Timer1 Controller Reset
3
1
read-write
0
Timer1 controller normal operation
#0
1
Timer1 controller reset
#1
TMR2RST
Timer2 Controller Reset
4
1
read-write
0
Timer2 controller normal operation
#0
1
Timer2 controller reset
#1
TMR3RST
Timer3 Controller Reset
5
1
read-write
0
Timer3 controller normal operation
#0
1
Timer3 controller reset
#1
UART0RST
UART0 Controller Reset
16
1
read-write
0
UART0 controller normal operation
#0
1
UART0 controller reset
#1
UART1RST
UART1 Controller Reset
17
1
read-write
0
UART1 controller normal operation
#0
1
UART1 controller reset
#1
UART2RST
UART2 Controller Reset
18
1
read-write
0
UART2 controller normal operation
#0
1
UART2 controller reset
#1
UART3RST
UART3 Controller Reset
19
1
read-write
0
UART3 controller normal operation
#0
1
UART3 controller reset
#1
UART4RST
UART4 Controller Reset
20
1
read-write
0
UART4 controller normal operation
#0
1
UART4 controller reset
#1
USBDRST
USBD Controller Reset
27
1
read-write
0
USBD controller normal operation
#0
1
USBD controller reset
#1
IPRST2
SYS_IPRST2
Peripheral Reset Control Register 2
0x10
-1
read-write
n
0x0
0x0
BPWM0RST
BPWM0 Controller Reset
18
1
read-write
0
BPWM0 controller normal operation
#0
1
BPWM0 controller reset
#1
USCI0RST
USCI0 Controller Reset
8
1
read-write
0
USCI0 controller normal operation
#0
1
USCI0 controller reset
#1
IVSCTL
SYS_IVSCTL
Internal Voltage Source Control Register
0x1C
-1
read-write
n
0x0
0x0
VTEMPEN
Temperature Sensor Enable Bit
This bit is used to enable/disable temperature sensor function.
.
0
1
read-write
0
Temperature sensor function Disabled (default)
#0
1
Temperature sensor function Enabled
#1
MIRCTRIMCTL
SYS_MIRCTRIMCTL
MIRC Trim Control Register
0x104
-1
read-write
n
0x0
0x0
BOUNDARY
Boundary Selection
Fill the boundary range from 0x1 to 0x1F. 0x0 is reserved.
Note: This field is effective only when the BOUNDEN(SYS_MIRCTRIMCTL[9]) is enabled.
16
5
read-write
BOUNDEN
Boundary Enable Bit
9
1
read-write
0
Boundary function Disabled
#0
1
Boundary function Enabled
#1
CESTOPEN
Clock Error Stop Enable Bit
8
1
read-write
0
The trim operation keeps going if clock is inaccurate
#0
1
The trim operation stops if clock is inaccurate
#1
FREQSEL
Trim Frequency Selection
This field indicates the target frequency of medium speed RC oscillator (MIRC) auto trim.
During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
0
2
read-write
0
Disable HIRC auto trim function
#00
1
Reserved.
#01
2
Enable HIRC auto trim function and trim MIRC to 4.032 MHz
#10
LOOPSEL
Trim Calculation Loop Selection
This field defines that trim value calculation is based on how many reference clocks.
Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
4
2
read-write
0
Reserved.
#00
1
Trim value calculation is based on average difference in 8 clocks of reference clock
#01
2
Trim value calculation is based on average difference in 16 clocks of reference clock
#10
3
Trim value calculation is based on average difference in 32 clocks of reference clock
#11
REFCKSEL
Reference Clock Selection
10
1
read-write
0
MIRC trim reference clock is from LXT (32.768 kHz)
#0
1
MIRC trim reference clock is from internal USB synchronous mode
#1
RETRYCNT
Trim Value Update Limitation Count
This field defines that how many times the auto trim circuit will try to update the MIRC trim value before the frequency of MIRC locked.
Once the MIRC locked, the internal trim value update counter will be reset.
If the trim value update counter reached this limitation value and frequency of MIRC is still not locked, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
6
2
read-write
0
Trim retry count limitation is 64 loops
#00
1
Trim retry count limitation is 128 loops
#01
2
Trim retry count limitation is 256 loops
#10
3
Trim retry count limitation is 512 loops
#11
MIRCTRIMIEN
SYS_MIRCTRIMIEN
MIRC Trim Interrupt Enable Register
0x108
-1
read-write
n
0x0
0x0
CLKEIEN
Clock Error Interrupt Enable Bit
This bit controls if CPU would get an interrupt while clock is inaccurate during auto trim operation.
If this bit is set to1, and CLKERRIF(SYS_MIRCTRIMSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccurate.
2
1
read-write
0
Disable CLKERRIF(SYS_MIRCTRIMSTS[2]) status to trigger an interrupt to CPU
#0
1
Enable CLKERRIF(SYS_MIRCTRIMSTS[2]) status to trigger an interrupt to CPU
#1
TFALIEN
Trim Failure Interrupt Enable Bit
This bit controls if an interrupt will be triggered while MIRC trim value update limitation count reached and MIRC frequency still not locked on target frequency set by FREQSEL(SYS_ MIRTRIMCTL[1:0]).
If this bit is high and TFAILIF(SYS_ MIRCTRIMSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that MIRC trim value update limitation count reached.
1
1
read-write
0
Disable TFAILIF(SYS_MIRCTRIMSTS[1]) status to trigger an interrupt to CPU
#0
1
Enable TFAILIF(SYS_MIRCTRIMSTS[1]) status to trigger an interrupt to CPU
#1
MIRCTRIMSTS
SYS_MIRCTRIMSTS
MIRC Trim Interrupt Status Register
0x10C
-1
read-write
n
0x0
0x0
CLKERIF
Clock Error Interrupt Status
When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal medium speed RC oscillator (MIRC) is shift larger to unreasonable value, this bit will be set and be an indicate that clock frequency is inaccurate.
Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_MIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_MIRCTRIMCTL[8]) is set to 1.
If this bit is set and CLKEIEN(SYS_MIRCTRIMIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccurate. Write 1 to clear this to 0.
Note: Reset by power on reset.
2
1
read-write
0
Clock frequency is accurate
#0
1
Clock frequency is inaccurate
#1
FREQLOCK
MIRC Frequency Lock Status
This bit indicates the MIRC frequency is locked.
This is a status bit and doesn't trigger any interrupt.
Write 1 to clear this to 0. This bit will be set automatically if the frequency is locked and the RC_TRIM is enabled.
Note: Reset by power on reset.
0
1
read-write
0
The internal medium-speed oscillator frequency not locked
#0
1
The internal medium-speed oscillator frequency locked
#1
OVBDIF
Over Boundary Status
When the over boundary function is set, if there occurs the over boundary condition, this flag will be set.
Note: Write 1 to clear this flag.
3
1
read-write
0
Over boundary condition did not occur
#0
1
Over boundary condition occurred
#1
TFAILIF
Trim Failure Interrupt Status
This bit indicates that MIRC trim value update limitation count reached and the MIRC clock frequency is still not locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_MIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically.
If this bit is set and TFAILIEN(SYS_MIRCTRIMIEN[1]) is high, an interrupt will be triggered to notify that MIRC trim value update limitation count reached. Write 1 to clear this to 0.
Note: Reset by power on reset.
1
1
read-write
0
Trim value update limitation count not reached
#0
1
Trim value update limitation count reached and MIRC frequency still not locked
#1
MODCTL
SYS_MODCTL
Modulation Control Register
0xC0
-1
read-write
n
0x0
0x0
PDID
SYS_PDID
Part Device Identification Number Register
0x0
-1
read-only
n
0x0
0x0
PDID
Part Device Identification Number (Read Only)
This register reflects device part number code. Software can read this register to identify which device is used.
0
32
read-only
PLCTL
SYS_PLCTL
Power Level Control Register
0x1F8
-1
read-write
n
0x0
0x0
PLSEL
Power Level Select(Write Protect)
Note : When system is at PL3, HCLK clock has to come from LXT or LIRC.
0
2
read-write
0
Set to power level 0 (PL0)
#00
3
Set to power level 3 (PL3)
#11
PLSTS
SYS_PLSTS
Power Level Status Register
0x1FC
-1
read-write
n
0x0
0x0
CURPL
Current Power Level (Read Only)
This bit field reflect the current power level.
Note : When system is at PL3, HCLK clock has to come from LXT or LIRC.
8
2
read-only
0
Current power level is PL0
#00
3
Current power level is PL3
#11
PLCBUSY
Power Level Change Busy Bit (Read Only)
This bit is set by hardware when power level is changing. After power level change is completed, this bit will be cleared automatically by hardware.
0
1
read-only
0
Power level change is completed
#0
1
Power level change is ongoing
#1
PORCTL0
SYS_PORCTL0
Power-On-reset Controller Register 0
0x24
-1
read-write
n
0x0
0x0
PORMASK
Power-on Reset Mask Enable Bit (Write Protect)
When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can mask internal POR signal to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
0
16
read-write
PORCTL1
SYS_PORCTL1
Power-On-reset Controller Register 1
0x1EC
-1
read-write
n
0x0
0x0
POROFF
Power-on Reset Enable Bit (Write Protect)
After powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field.
The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including:
nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
16
read-write
REGLCTL
SYS_REGLCTL
Register Lock Control Register
0x100
-1
read-write
n
0x0
0x0
REGLCTL
Register Lock Control Code
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
Register Lock Control Disable Index
The Protected registers are:
NMIEN address 0x4000_0300
FMC_ISPCTL address 0x4000_C000 (Flash ISP Control register)
FMC_ISPTRG address 0x4000_C010 (ISP Trigger Control register)
FMC_ISPSTS address 0x4000_C040
WDT_CTL address 0x4004_0000
FMC_FTCTL address 0x4000_5018
FMC_ICPCMD address 0x4000_501C
EADC_TEST address 0x4004_3200
AHBMCTL address 0x4000_0400
SYS_IPRST0 address 0x4000_0008
SYS_BODCTL address 0x4000_0018
SYS_PORCTL0 address 0x4000_0024
SYS_SRAM_BISTCTL address 0x4000_00D0
SYS_PORCTL1 address 0x4000_1EC
CLK_PWRCTL address 0x4000_0200
CLK_APBCLK0[0] address 0x4000_0208
CLK_CLKSEL0 address 0x4000_0110
CLK_CLKSEL1[3:0] address 0x4000_0214
CLK_PLLCTL address 0x4000_0240
CLK_PMUCTL address 0x4000_0290
CLK_HXTFSEL address 0x4000_02B4
0
8
read-write
0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
0
1
Write-protection Disabled for writing protected registers
1
RSTSTS
SYS_RSTSTS
System Reset Status Register
0x4
-1
read-write
n
0x0
0x0
BODRF
BOD Reset Flag
The BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
4
1
read-write
0
No reset from BOD
#0
1
BOD had issued the reset signal to reset the system
#1
CPULKRF
CPU Lockup Reset Flag
Note 1: Write 1 to clear this bit to 0.
Note 2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset.
8
1
read-write
0
No reset from CPU lockup happened
#0
1
The Cortex-M23 lockup happened and chip is reset
#1
CPURF
CPU Reset Flag
The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex- M23 core and Flash Memory Controller (FMC).
Note: Write 1 to clear this bit to 0.
7
1
read-write
0
No reset from CPU
#0
1
The Cortex-M23 Core and FMC are reset by software setting CPURST to 1
#1
LVRF
LVR Reset Flag
The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
3
1
read-write
0
No reset from LVR
#0
1
LVR controller had issued the reset signal to reset the system
#1
PINRF
NRESET Pin Reset Flag
The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
1
1
read-write
0
No reset from nRESET pin
#0
1
Pin nRESET had issued the reset signal to reset the system
#1
PMURF
PMU Reset Flag,
The PMU reset flag is set by any reset signal when MCU is in power down state.
Note: Write 1 to clear this bit to 0.
6
1
read-write
0
No reset in power down state
#0
1
Any reset signal happens in power down state
#1
PORF
POR Reset Flag
The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
0
1
read-write
0
No reset from POR or CHIPRST
#0
1
Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system
#1
SYSRF
System Reset Flag
The system reset flag is set by the 'Reset Signal' from the CortexM23Core to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
5
1
read-write
0
No reset from Cortex-M23
#0
1
The Cortex- M23 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M23 core
#1
WDTRF
WDT Reset Flag
The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
Note 1: Write 1 to clear this bit to 0.
Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
2
1
read-write
0
No reset from watchdog timer or window watchdog timer
#0
1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
#1
SRAM_BISTCTL
SYS_SRAM_BISTCTL
System SRAM BIST Test Control Register
0xD0
-1
read-write
n
0x0
0x0
CANFD0BIST
CANFD0 BIST Enable Bit (Write Protect)
This bit enables BIST test for CANFD0 RAM.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
System CANFD0 BIST Disabled
#0
1
System CANFD0 BIST Enabled
#1
FMCBIST
FMC CACHE BIST Enable Bit (Write Protect)
This bit enables BIST test for CACHE RAM.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
System CACHE BIST Disabled
#0
1
System CACHE BIST Enabled
#1
PDMABIST
PDMA BIST Enable Bit (Write Protect)
This bit enables BIST test for PDMA RAM.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
System PDMA BIST Disabled
#0
1
System PDMA BIST Enabled
#1
SRBIST
SRAM BIST Enable Bit (Write Protect)
This bit enables BIST test for SRAM.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
System SRAM BIST Disabled
#0
1
System SRAM BIST Enabled
#1
USBBIST
USB BIST Enable Bit (Write Protect)
This bit enables BIST test for USB RAM
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
System USB BIST Disabled
#0
1
System USB BIST Enabled
#1
SRAM_BISTSTS
SYS_SRAM_BISTSTS
System SRAM BIST Test Status Register
0xD4
-1
read-only
n
0x0
0x0
CANFD0BISTF
CANFD0 SRAM BIST Failed Flag
6
1
read-only
0
CANFD0 SRAM BIST passed
#0
1
CANFD0 SRAM BIST failed
#1
CANFD0END
CANFD0 SRAM BIST Test Finish
22
1
read-only
0
CANFD0 SRAM BIST is active
#0
1
CANFD0 SRAM BIST test finished
#1
CR0BEND
CACHE 0 SRAM BIST Test Finish
17
1
read-only
0
System CACHE RAM BIST is active
#0
1
System CACHE RAM BIST test finished
#1
CR0BISTEF
CACHE0 SRAM BIST Fail Flag
1
1
read-only
0
System CACHE RAM BIST test passed
#0
1
System CACHE RAM BIST test failed
#1
CR1BEND
CACHE 1 SRAM BIST Test Finish
18
1
read-only
0
System CACHE RAM BIST is active
#0
1
System CACHE RAM BIST test finished
#1
CR1BISTEF
CACHE1 SRAM BIST Fail Flag
2
1
read-only
0
System CACHE RAM BIST test passed
#0
1
System CACHE RAM BIST test failed
#1
PDMABISTF
PDMA SRAM BIST Failed Flag
7
1
read-only
0
PDMA SRAM BIST passed
#0
1
PDMA SRAM BIST failed
#1
PDMAEND
PDMA SRAM BIST Test Finish
23
1
read-only
0
PDMA SRAM BIST is active
#0
1
PDMA SRAM BIST test finished
#1
SRBEND
SRAM BIST Test Finish
16
1
read-only
0
System SRAM BIST active
#0
1
system SRAM BIST finished
#1
SRBISTEF
System SRAM BIST Fail Flag
0
1
read-only
0
System SRAM BIST test passed
#0
1
System SRAM BIST test failed
#1
USBBEF
USB SRAM BIST Fail Flag
4
1
read-only
0
USB SRAM BIST test passed
#0
1
USB SRAM BIST test failed
#1
USBBEND
USB SRAM BIST Test Finish
20
1
read-only
0
USB SRAM BIST is active
#0
1
USB SRAM BIST test finished
#1
TMR01
TIMER Register Map
TIMER
0x0
0x0
0x20
registers
n
0x100
0x20
registers
n
TIMER0_CAP
TIMER0_CAP
Timer0 Capture Data Register
0x10
-1
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register
When CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
Note: User must consider the Timer will keep register TIMERx_CAP unchanged and drop the new capture value if the CPU does not clear the CAPIF status.
0
24
read-only
TIMER0_CMP
TIMER0_CMP
Timer0 Comparator Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
Timer Comparator Value
CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
0
24
read-write
TIMER0_CNT
TIMER0_CNT
Timer0 Data Register
0xC
-1
read-write
n
0x0
0x0
CNT
Timer Data Register
Read operation.
Read this register to get CNT value. For example:
If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.
If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.
Write operation.
Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
0
24
read-write
RSTACT
Timer Data Register Reset Active (Read Only)
This bit indicates if the counter reset operation active.
When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically.
31
1
read-only
0
Reset operation is done
#0
1
Reset operation triggered by writing TIMERx_CNT is in progress
#1
TIMER0_CTL
TIMER0_CTL
Timer0 Control Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)
This bit indicates the 24-bit up counter status.
Note: This bit may active when CNT 0 transition to CNT 1.
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CAPSRC
Capture Pin Source Selection
22
1
read-write
0
Capture Function source is from TMx_EXT (x= 0~3) pin
#0
1
Capture Function source is from internal ACMP output signal, internal clock (LIRC, HIRC), or external clock (HXT, LXT)
#1
CNTEN
Timer Counting Enable Bit
Note 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Event Counter Mode Enable Bit
This bit is for external counting pin function enabled.
Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
24
1
read-write
0
Event counter mode Disabled
#0
1
Event counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
TIMER counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Timer Interrupt Enable Bit
Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer time-out interrupt Disabled
#0
1
Timer time-out interrupt Enabled
#1
INTRGEN
Inter-timer Trigger Mode Enable Bit
Setting this bit will enable the inter-timer trigger capture function.
The Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.
Note: For Timer1/3, this bit is ineffective and the read back value is always 0.
19
1
read-write
0
Inter-Timer Trigger Capture mode Disabled
#0
1
Inter-Timer Trigger Capture mode Enabled
#1
OPMODE
Timer Counting Mode Select
27
2
read-write
0
The timer controller is operated in One-shot mode
#00
1
The timer controller is operated in Periodic mode
#01
2
The timer controller is operated in Toggle-output mode
#10
3
The timer controller is operated in Continuous Counting mode
#11
PERIOSEL
Periodic Mode Behavior Selection Enable Bit
If updated CMPDAT value CNT, CNT will be reset to default value.
20
1
read-write
0
The behavior selection in periodic mode is Disabled
#0
1
The behavior selection in periodic mode is Enabled
#1
PSC
Prescale Counter
Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
0
8
read-write
TGLPINSEL
Toggle-output Pin Select
21
1
read-write
0
Toggle mode output to TMx (Timer Event Counter Pin)
#0
1
Toggle mode output to TMx_EXT (Timer External Capture Pin)
#1
WKEN
Wake-up Function Enable Bit
If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
23
1
read-write
0
Wake-up function Disabled if timer interrupt signal generated
#0
1
Wake-up function Enabled if timer interrupt signal generated
#1
TIMER0_EINTSTS
TIMER0_EINTSTS
Timer0 External Interrupt Status Register
0x18
-1
read-write
n
0x0
0x0
CAPIF
Timer External Capture Interrupt Flag
This bit indicates the timer external capture interrupt flag status.
Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
0
1
read-write
0
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt did not occur
#0
1
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt occurred
#1
TIMER0_EXTCTL
TIMER0_EXTCTL
Timer0 External Control Register
0x14
-1
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled
#0
1
TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled
#1
CAPDIVSCL
Timer Capture Source Divider Scale
This bits indicate the divide scale for capture source divider
Note: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source.
28
4
read-write
0
Capture source/1
#0000
1
Capture source/2
#0001
2
Capture source/4
#0010
3
Capture source/8
#0011
4
Capture source/16
#0100
5
Capture source/32
#0101
6
Capture source/64
#0110
7
Capture source/128
#0111
8
Capture source/256
#1000
CAPEDGE
Timer External Capture Pin Edge Detect
When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.
Note: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL (TIMERx_EXTCTL[10:8]) to select capture source.
12
3
read-write
0
Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin
#000
1
Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin
#001
2
Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer
#010
3
Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer
#011
6
First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin
#110
7
First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin
#111
CAPEN
Timer Capture Enable Bit
This bit enables the capture input function.
Note: When CAPEN is 1, user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source.
3
1
read-write
0
Capture source Disabled
#0
1
Capture source Enabled
#1
CAPFUNCS
Capture Function Selection
4
1
read-write
0
External Capture Mode Enabled
#0
1
External Reset Mode Enabled
#1
CAPIEN
Timer External Capture Interrupt Enable Bit
5
1
read-write
0
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~3) pin de-bounce Disabled
#0
1
TMx (x= 0~3) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
INTERCAPSEL
Internal Capture Source Select
Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1.
8
3
read-write
0
Capture Function source is from internal ACMP0 output signal
#000
1
Capture Function source is from internal ACMP1 output signal
#001
2
Capture Function source is from HXT
#010
3
Capture Function source is from LXT
#011
4
Capture Function source is from HIRC
#100
5
Capture Function source is from LIRC
#101
6
Capture Function source is from MIRC
#110
7
Reserved.
#111
TIMER0_INTSTS
TIMER0_INTSTS
Timer0 Interrupt Status Register
0x8
-1
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-up Flag
This bit indicates the interrupt wake-up flag status of timer.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
#1
TIMER0_TRGCTL
TIMER0_TRGCTL
Timer0 Trigger Control Register
0x1C
-1
read-write
n
0x0
0x0
TRGDAC
Trigger DAC Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
3
1
read-write
0
Timer interrupt trigger DAC Disabled
#0
1
Timer interrupt trigger DAC Enabled
#1
TRGEADC
Trigger EADC Enable Bit
If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion.
2
1
read-write
0
Timer interrupt trigger EADC Disabled
#0
1
Timer interrupt trigger EADC Enabled
#1
TRGPDMA
Trigger PDMA Enable Bit
If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
4
1
read-write
0
Timer interrupt trigger PDMA Disabled
#0
1
Timer interrupt trigger PDMA Enabled
#1
TRGPWM
Trigger BPWM Enable Bit
If this bit is set to 1, each timer time-out event or capture event can be as BPWM counter clock source.
1
1
read-write
0
Timer interrupt trigger BPWM Disabled
#0
1
Timer interrupt trigger BPWM Enabled
#1
TRGSSEL
Trigger Source Select Bit
This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal.
0
1
read-write
0
Time-out interrupt signal is used to internal trigger BPWM, PDMA, DAC, and EADC
#0
1
Capture interrupt signal is used to internal trigger BPWM, PDMA, DAC, and EADC
#1
TIMER1_CAP
TIMER1_CAP
Timer1 Capture Data Register
0x110
-1
read-write
n
0x0
0x0
TIMER1_CMP
TIMER1_CMP
Timer1 Comparator Register
0x104
-1
read-write
n
0x0
0x0
TIMER1_CNT
TIMER1_CNT
Timer1 Data Register
0x10C
-1
read-write
n
0x0
0x0
TIMER1_CTL
TIMER1_CTL
Timer1 Control Register
0x100
-1
read-write
n
0x0
0x0
TIMER1_EINTSTS
TIMER1_EINTSTS
Timer1 External Interrupt Status Register
0x118
-1
read-write
n
0x0
0x0
TIMER1_EXTCTL
TIMER1_EXTCTL
Timer1 External Control Register
0x114
-1
read-write
n
0x0
0x0
TIMER1_INTSTS
TIMER1_INTSTS
Timer1 Interrupt Status Register
0x108
-1
read-write
n
0x0
0x0
TIMER1_TRGCTL
TIMER1_TRGCTL
Timer1 Trigger Control Register
0x11C
-1
read-write
n
0x0
0x0
TMR23
TIMER Register Map
TIMER
0x0
0x0
0x20
registers
n
0x100
0x20
registers
n
TIMER2_CAP
TIMER2_CAP
Timer2 Capture Data Register
0x10
-1
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register
When CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
Note: User must consider the Timer will keep register TIMERx_CAP unchanged and drop the new capture value if the CPU does not clear the CAPIF status.
0
24
read-only
TIMER2_CMP
TIMER2_CMP
Timer2 Comparator Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
Timer Comparator Value
CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
0
24
read-write
TIMER2_CNT
TIMER2_CNT
Timer2 Data Register
0xC
-1
read-write
n
0x0
0x0
CNT
Timer Data Register
Read operation.
Read this register to get CNT value. For example:
If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.
If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.
Write operation.
Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
0
24
read-write
RSTACT
Timer Data Register Reset Active (Read Only)
This bit indicates if the counter reset operation active.
When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically.
31
1
read-only
0
Reset operation is done
#0
1
Reset operation triggered by writing TIMERx_CNT is in progress
#1
TIMER2_CTL
TIMER2_CTL
Timer2 Control Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)
This bit indicates the 24-bit up counter status.
Note: This bit may active when CNT 0 transition to CNT 1.
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CAPSRC
Capture Pin Source Selection
22
1
read-write
0
Capture Function source is from TMx_EXT (x= 0~3) pin
#0
1
Capture Function source is from internal ACMP output signal, internal clock (LIRC, HIRC), or external clock (HXT, LXT)
#1
CNTEN
Timer Counting Enable Bit
Note 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Event Counter Mode Enable Bit
This bit is for external counting pin function enabled.
Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
24
1
read-write
0
Event counter mode Disabled
#0
1
Event counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
TIMER counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Timer Interrupt Enable Bit
Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer time-out interrupt Disabled
#0
1
Timer time-out interrupt Enabled
#1
INTRGEN
Inter-timer Trigger Mode Enable Bit
Setting this bit will enable the inter-timer trigger capture function.
The Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.
Note: For Timer1/3, this bit is ineffective and the read back value is always 0.
19
1
read-write
0
Inter-Timer Trigger Capture mode Disabled
#0
1
Inter-Timer Trigger Capture mode Enabled
#1
OPMODE
Timer Counting Mode Select
27
2
read-write
0
The timer controller is operated in One-shot mode
#00
1
The timer controller is operated in Periodic mode
#01
2
The timer controller is operated in Toggle-output mode
#10
3
The timer controller is operated in Continuous Counting mode
#11
PERIOSEL
Periodic Mode Behavior Selection Enable Bit
If updated CMPDAT value CNT, CNT will be reset to default value.
20
1
read-write
0
The behavior selection in periodic mode is Disabled
#0
1
The behavior selection in periodic mode is Enabled
#1
PSC
Prescale Counter
Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
0
8
read-write
TGLPINSEL
Toggle-output Pin Select
21
1
read-write
0
Toggle mode output to TMx (Timer Event Counter Pin)
#0
1
Toggle mode output to TMx_EXT (Timer External Capture Pin)
#1
WKEN
Wake-up Function Enable Bit
If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
23
1
read-write
0
Wake-up function Disabled if timer interrupt signal generated
#0
1
Wake-up function Enabled if timer interrupt signal generated
#1
TIMER2_EINTSTS
TIMER2_EINTSTS
Timer2 External Interrupt Status Register
0x18
-1
read-write
n
0x0
0x0
CAPIF
Timer External Capture Interrupt Flag
This bit indicates the timer external capture interrupt flag status.
Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
0
1
read-write
0
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt did not occur
#0
1
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt occurred
#1
TIMER2_EXTCTL
TIMER2_EXTCTL
Timer2 External Control Register
0x14
-1
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled
#0
1
TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled
#1
CAPDIVSCL
Timer Capture Source Divider Scale
This bits indicate the divide scale for capture source divider
Note: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source.
28
4
read-write
0
Capture source/1
#0000
1
Capture source/2
#0001
2
Capture source/4
#0010
3
Capture source/8
#0011
4
Capture source/16
#0100
5
Capture source/32
#0101
6
Capture source/64
#0110
7
Capture source/128
#0111
8
Capture source/256
#1000
CAPEDGE
Timer External Capture Pin Edge Detect
When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.
Note: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL (TIMERx_EXTCTL[10:8]) to select capture source.
12
3
read-write
0
Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin
#000
1
Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin
#001
2
Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer
#010
3
Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer
#011
6
First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin
#110
7
First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin
#111
CAPEN
Timer Capture Enable Bit
This bit enables the capture input function.
Note: When CAPEN is 1, user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source.
3
1
read-write
0
Capture source Disabled
#0
1
Capture source Enabled
#1
CAPFUNCS
Capture Function Selection
4
1
read-write
0
External Capture Mode Enabled
#0
1
External Reset Mode Enabled
#1
CAPIEN
Timer External Capture Interrupt Enable Bit
5
1
read-write
0
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~3) pin de-bounce Disabled
#0
1
TMx (x= 0~3) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
INTERCAPSEL
Internal Capture Source Select
Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1.
8
3
read-write
0
Capture Function source is from internal ACMP0 output signal
#000
1
Capture Function source is from internal ACMP1 output signal
#001
2
Capture Function source is from HXT
#010
3
Capture Function source is from LXT
#011
4
Capture Function source is from HIRC
#100
5
Capture Function source is from LIRC
#101
6
Capture Function source is from MIRC
#110
7
Reserved.
#111
TIMER2_INTSTS
TIMER2_INTSTS
Timer2 Interrupt Status Register
0x8
-1
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-up Flag
This bit indicates the interrupt wake-up flag status of timer.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
#1
TIMER2_TRGCTL
TIMER2_TRGCTL
Timer2 Trigger Control Register
0x1C
-1
read-write
n
0x0
0x0
TRGDAC
Trigger DAC Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
3
1
read-write
0
Timer interrupt trigger DAC Disabled
#0
1
Timer interrupt trigger DAC Enabled
#1
TRGEADC
Trigger EADC Enable Bit
If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion.
2
1
read-write
0
Timer interrupt trigger EADC Disabled
#0
1
Timer interrupt trigger EADC Enabled
#1
TRGPDMA
Trigger PDMA Enable Bit
If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
4
1
read-write
0
Timer interrupt trigger PDMA Disabled
#0
1
Timer interrupt trigger PDMA Enabled
#1
TRGPWM
Trigger BPWM Enable Bit
If this bit is set to 1, each timer time-out event or capture event can be as BPWM counter clock source.
1
1
read-write
0
Timer interrupt trigger BPWM Disabled
#0
1
Timer interrupt trigger BPWM Enabled
#1
TRGSSEL
Trigger Source Select Bit
This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal.
0
1
read-write
0
Time-out interrupt signal is used to internal trigger BPWM, PDMA, DAC, and EADC
#0
1
Capture interrupt signal is used to internal trigger BPWM, PDMA, DAC, and EADC
#1
TIMER3_CAP
TIMER3_CAP
Timer3 Capture Data Register
0x110
-1
read-write
n
0x0
0x0
TIMER3_CMP
TIMER3_CMP
Timer3 Comparator Register
0x104
-1
read-write
n
0x0
0x0
TIMER3_CNT
TIMER3_CNT
Timer3 Data Register
0x10C
-1
read-write
n
0x0
0x0
TIMER3_CTL
TIMER3_CTL
Timer3 Control Register
0x100
-1
read-write
n
0x0
0x0
TIMER3_EINTSTS
TIMER3_EINTSTS
Timer3 External Interrupt Status Register
0x118
-1
read-write
n
0x0
0x0
TIMER3_EXTCTL
TIMER3_EXTCTL
Timer3 External Control Register
0x114
-1
read-write
n
0x0
0x0
TIMER3_INTSTS
TIMER3_INTSTS
Timer3 Interrupt Status Register
0x108
-1
read-write
n
0x0
0x0
TIMER3_TRGCTL
TIMER3_TRGCTL
Timer3 Trigger Control Register
0x11C
-1
read-write
n
0x0
0x0
UART0
UART Register Map
UART
0x0
0x0
0x34
registers
n
0x3C
0x10
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length
Note : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from START bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from START bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from START bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from START bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit
Note : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit
This bit is used to enable RS-485 Address Detection mode.
Note: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value
This field contains the RS-485 address match values.
Note: This field is used for RS-485 auto address detection mode.
24
8
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode
Note: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function
Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode
Note: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0
This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.124.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1
This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.124.
Note: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider
The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.124.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1
This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.124.
24
4
read-write
UART_BRCOMP
UART_BRCOMP
UART Baud Rate Compensation Register
0x3C
-1
read-write
n
0x0
0x0
BRCOMP
Baud Rate Compensation Patten
These 9-bits are used to define the relative bit is compensated or not.
BRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8]).
0
9
read-write
BRCOMPDEC
Baud Rate Compensation Decrease
31
1
read-write
0
Positive (increase one module clock) compensation for each compensated bit
#0
1
Negative (decrease one module clock) compensation for each compensated bit
#1
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
-1
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer
Write Operation:
By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
Read Operation:
By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
PARITY Bit Receive/Transmit Buffer
Write Operation:
By writing to this bit, the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.
Read Operation:
If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the PARITY bit can be read by this bit.
Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
-1
read-write
n
0x0
0x0
STCOMP
START Bit Compensation Value
These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode.
Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level
When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control
Note: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit
The receiver is disabled or not (set 1 to disable receiver).
Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset
When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset
When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag
This bit is set to logic '1' when auto-baud rate detect function is finished.
Note: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag
This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.
Note: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag
Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.
Note 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag
This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits).
Note: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0).
Note: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.
Note: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)
This bit initiate RX FIFO empty or not.
Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)
This bit initiates RX FIFO full or not.
Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)
This bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)
This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer is equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)
This bit indicates TX FIFO empty or not.
Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)
This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)
This bit indicates TX FIFO full or not.
Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
Note: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)
This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer is equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)
This bit indicates TX and RX are active or inactive.
Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller cannot transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
-1
read-write
n
0x0
0x0
DGE
Deglitch Enable Bit
Note 1: When this bit is set to logic 1, any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic.
Note 2: It is recommended to set this bit only when operating at baud rate under 2.5 Mbps.
6
1
read-write
0
Deglitch Disabled
#0
1
Deglitch Enabled
#1
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit
Setting this bit can disable TX and RX.
Note: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
-1
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit
Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit
Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit
This bit can enable or disable RX PDMA service.
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit
Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.
Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Interrupt Disabled
#0
1
Single-wire Bit Error Detect Interrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit
If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)
This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated.
#1
RDAIF
Receive Data Available Interrupt Flag
When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)
This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag
This bit is set when the single wire bus state is not equal to UART controller TX state in Single-wire mode.
Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
Note 2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)
This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag
This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)
This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag
This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only)
This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)
This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.
Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)
This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
-1
read-write
n
0x0
0x0
BCB
Break Control Bit
Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit
Note: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
PARITY Bit Enable Bit
Note: PARITY bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
PARITY bit generated Disabled
#0
1
PARITY bit generated Enabled
#1
PSS
PARITY Bit Source Selection
The PARITY bit can be selected to be generated and checked automatically or by software.
Note 1: This bit has effect only when PBE (UART_LINE[3]) is set.
Note 2: If PSS is 0, the PARITY bit is transmitted and checked automatically. If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (UART_DAT[8]) and the PARITY bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
PARITY bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
PARITY bit generated and checked by software
#1
RXDINV
RX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit
Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection
This field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS Signal Control
This bit is direct control internal nRTS (Request-to-send) signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
Note 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
Note 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
Note 3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level
This bit defines the active level state of nRTS pin output.
Note 1: Refer to Figure 6.1213 and Figure 6.1214 for UART function mode.
Note 2: Refer to Figure 6.1217 and Figure 6.1218 for RS-485 function mode.
Note 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)
This bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level
This bit defines the active level state of nCTS pin input.
Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)
This bit mirror from nCTS pin input of voltage logic status.
Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
-1
read-write
n
0x0
0x0
DLY
TX Delay Time Value
This field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
-1
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit
Note: When the system is in Power-down mode, an external nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit
Note: When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit
Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match Wake-up Enable Bit
Note 1: When the system is in Power-down mode, RS-485 Address Match will wake up system from Power-down mode.
Note 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit
Note 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.
Note 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
-1
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag
This bit is set if chip wake-up from power-down state by nCTS wake-up.
Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag
This bit is set if chip wake-up from power-down state by data wake-up.
Note 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold
wake-up .
Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match Wake-up Flag
This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).
Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.
Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UART1
UART Register Map
UART
0x0
0x0
0x34
registers
n
0x3C
0x10
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length
Note : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from START bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from START bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from START bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from START bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit
Note : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit
This bit is used to enable RS-485 Address Detection mode.
Note: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value
This field contains the RS-485 address match values.
Note: This field is used for RS-485 auto address detection mode.
24
8
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode
Note: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function
Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode
Note: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0
This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.124.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1
This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.124.
Note: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider
The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.124.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1
This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.124.
24
4
read-write
UART_BRCOMP
UART_BRCOMP
UART Baud Rate Compensation Register
0x3C
-1
read-write
n
0x0
0x0
BRCOMP
Baud Rate Compensation Patten
These 9-bits are used to define the relative bit is compensated or not.
BRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8]).
0
9
read-write
BRCOMPDEC
Baud Rate Compensation Decrease
31
1
read-write
0
Positive (increase one module clock) compensation for each compensated bit
#0
1
Negative (decrease one module clock) compensation for each compensated bit
#1
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
-1
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer
Write Operation:
By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
Read Operation:
By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
PARITY Bit Receive/Transmit Buffer
Write Operation:
By writing to this bit, the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.
Read Operation:
If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the PARITY bit can be read by this bit.
Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
-1
read-write
n
0x0
0x0
STCOMP
START Bit Compensation Value
These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode.
Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level
When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control
Note: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit
The receiver is disabled or not (set 1 to disable receiver).
Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset
When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset
When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag
This bit is set to logic '1' when auto-baud rate detect function is finished.
Note: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag
This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.
Note: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag
Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.
Note 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag
This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits).
Note: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0).
Note: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.
Note: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)
This bit initiate RX FIFO empty or not.
Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)
This bit initiates RX FIFO full or not.
Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)
This bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)
This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer is equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)
This bit indicates TX FIFO empty or not.
Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)
This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)
This bit indicates TX FIFO full or not.
Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
Note: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)
This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer is equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)
This bit indicates TX and RX are active or inactive.
Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller cannot transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
-1
read-write
n
0x0
0x0
DGE
Deglitch Enable Bit
Note 1: When this bit is set to logic 1, any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic.
Note 2: It is recommended to set this bit only when operating at baud rate under 2.5 Mbps.
6
1
read-write
0
Deglitch Disabled
#0
1
Deglitch Enabled
#1
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit
Setting this bit can disable TX and RX.
Note: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
-1
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit
Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit
Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit
This bit can enable or disable RX PDMA service.
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit
Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.
Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Interrupt Disabled
#0
1
Single-wire Bit Error Detect Interrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit
If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)
This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag
When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)
This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag
This bit is set when the single wire bus state is not equal to UART controller TX state in Single-wire mode.
Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
Note 2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)
This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag
This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)
This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag
This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only)
This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)
This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.
Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)
This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
-1
read-write
n
0x0
0x0
BCB
Break Control Bit
Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit
Note: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
PARITY Bit Enable Bit
Note: PARITY bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
PARITY bit generated Disabled
#0
1
PARITY bit generated Enabled
#1
PSS
PARITY Bit Source Selection
The PARITY bit can be selected to be generated and checked automatically or by software.
Note 1: This bit has effect only when PBE (UART_LINE[3]) is set.
Note 2: If PSS is 0, the PARITY bit is transmitted and checked automatically. If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (UART_DAT[8]) and the PARITY bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
PARITY bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
PARITY bit generated and checked by software
#1
RXDINV
RX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit
Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection
This field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS Signal Control
This bit is direct control internal nRTS (Request-to-send) signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
Note 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
Note 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
Note 3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level
This bit defines the active level state of nRTS pin output.
Note 1: Refer to Figure 6.1213 and Figure 6.1214 for UART function mode.
Note 2: Refer to Figure 6.1217 and Figure 6.1218 for RS-485 function mode.
Note 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)
This bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level
This bit defines the active level state of nCTS pin input.
Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)
This bit mirror from nCTS pin input of voltage logic status.
Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
-1
read-write
n
0x0
0x0
DLY
TX Delay Time Value
This field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
-1
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit
Note: When the system is in Power-down mode, an external nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit
Note: When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit
Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match Wake-up Enable Bit
Note 1: When the system is in Power-down mode, RS-485 Address Match will wake up system from Power-down mode.
Note 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit
Note 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.
Note 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
-1
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag
This bit is set if chip wake-up from power-down state by nCTS wake-up.
Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag
This bit is set if chip wake-up from power-down state by data wake-up.
Note 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold
wake-up .
Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match Wake-up Flag
This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).
Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.
Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UART2
UART Register Map
UART
0x0
0x0
0x34
registers
n
0x3C
0x10
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length
Note : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from START bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from START bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from START bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from START bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit
Note : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit
This bit is used to enable RS-485 Address Detection mode.
Note: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value
This field contains the RS-485 address match values.
Note: This field is used for RS-485 auto address detection mode.
24
8
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode
Note: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function
Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode
Note: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0
This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.124.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1
This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.124.
Note: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider
The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.124.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1
This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.124.
24
4
read-write
UART_BRCOMP
UART_BRCOMP
UART Baud Rate Compensation Register
0x3C
-1
read-write
n
0x0
0x0
BRCOMP
Baud Rate Compensation Patten
These 9-bits are used to define the relative bit is compensated or not.
BRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8]).
0
9
read-write
BRCOMPDEC
Baud Rate Compensation Decrease
31
1
read-write
0
Positive (increase one module clock) compensation for each compensated bit
#0
1
Negative (decrease one module clock) compensation for each compensated bit
#1
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
-1
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer
Write Operation:
By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
Read Operation:
By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
PARITY Bit Receive/Transmit Buffer
Write Operation:
By writing to this bit, the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.
Read Operation:
If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the PARITY bit can be read by this bit.
Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
-1
read-write
n
0x0
0x0
STCOMP
START Bit Compensation Value
These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode.
Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level
When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control
Note: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit
The receiver is disabled or not (set 1 to disable receiver).
Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset
When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset
When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag
This bit is set to logic '1' when auto-baud rate detect function is finished.
Note: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag
This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.
Note: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag
Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.
Note 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag
This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits).
Note: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0).
Note: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.
Note: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)
This bit initiate RX FIFO empty or not.
Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)
This bit initiates RX FIFO full or not.
Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)
This bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)
This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer is equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)
This bit indicates TX FIFO empty or not.
Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)
This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)
This bit indicates TX FIFO full or not.
Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
Note: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)
This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer is equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)
This bit indicates TX and RX are active or inactive.
Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller cannot transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
-1
read-write
n
0x0
0x0
DGE
Deglitch Enable Bit
Note 1: When this bit is set to logic 1, any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic.
Note 2: It is recommended to set this bit only when operating at baud rate under 2.5 Mbps.
6
1
read-write
0
Deglitch Disabled
#0
1
Deglitch Enabled
#1
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit
Setting this bit can disable TX and RX.
Note: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
-1
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit
Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit
Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit
This bit can enable or disable RX PDMA service.
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit
Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.
Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Interrupt Disabled
#0
1
Single-wire Bit Error Detect Interrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit
If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)
This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag
When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)
This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag
This bit is set when the single wire bus state is not equal to UART controller TX state in Single-wire mode.
Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
Note 2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)
This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag
This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)
This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag
This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only)
This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)
This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.
Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)
This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
-1
read-write
n
0x0
0x0
BCB
Break Control Bit
Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit
Note: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
PARITY Bit Enable Bit
Note: PARITY bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
PARITY bit generated Disabled
#0
1
PARITY bit generated Enabled
#1
PSS
PARITY Bit Source Selection
The PARITY bit can be selected to be generated and checked automatically or by software.
Note 1: This bit has effect only when PBE (UART_LINE[3]) is set.
Note 2: If PSS is 0, the PARITY bit is transmitted and checked automatically. If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (UART_DAT[8]) and the PARITY bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
PARITY bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
PARITY bit generated and checked by software
#1
RXDINV
RX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit
Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection
This field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS Signal Control
This bit is direct control internal nRTS (Request-to-send) signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
Note 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
Note 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
Note 3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level
This bit defines the active level state of nRTS pin output.
Note 1: Refer to Figure 6.1213 and Figure 6.1214 for UART function mode.
Note 2: Refer to Figure 6.1217 and Figure 6.1218 for RS-485 function mode.
Note 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)
This bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level
This bit defines the active level state of nCTS pin input.
Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)
This bit mirror from nCTS pin input of voltage logic status.
Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
-1
read-write
n
0x0
0x0
DLY
TX Delay Time Value
This field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
-1
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit
Note: When the system is in Power-down mode, an external nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit
Note: When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit
Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match Wake-up Enable Bit
Note 1: When the system is in Power-down mode, RS-485 Address Match will wake up system from Power-down mode.
Note 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit
Note 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.
Note 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
-1
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag
This bit is set if chip wake-up from power-down state by nCTS wake-up.
Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag
This bit is set if chip wake-up from power-down state by data wake-up.
Note 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold
wake-up .
Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match Wake-up Flag
This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).
Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.
Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UART3
UART Register Map
UART
0x0
0x0
0x34
registers
n
0x3C
0x10
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length
Note : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from START bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from START bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from START bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from START bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit
Note : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit
This bit is used to enable RS-485 Address Detection mode.
Note: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value
This field contains the RS-485 address match values.
Note: This field is used for RS-485 auto address detection mode.
24
8
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode
Note: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function
Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode
Note: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0
This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.124.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1
This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.124.
Note: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider
The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.124.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1
This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.124.
24
4
read-write
UART_BRCOMP
UART_BRCOMP
UART Baud Rate Compensation Register
0x3C
-1
read-write
n
0x0
0x0
BRCOMP
Baud Rate Compensation Patten
These 9-bits are used to define the relative bit is compensated or not.
BRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8]).
0
9
read-write
BRCOMPDEC
Baud Rate Compensation Decrease
31
1
read-write
0
Positive (increase one module clock) compensation for each compensated bit
#0
1
Negative (decrease one module clock) compensation for each compensated bit
#1
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
-1
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer
Write Operation:
By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
Read Operation:
By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
PARITY Bit Receive/Transmit Buffer
Write Operation:
By writing to this bit, the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.
Read Operation:
If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the PARITY bit can be read by this bit.
Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
-1
read-write
n
0x0
0x0
STCOMP
START Bit Compensation Value
These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode.
Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level
When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control
Note: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit
The receiver is disabled or not (set 1 to disable receiver).
Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset
When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset
When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag
This bit is set to logic '1' when auto-baud rate detect function is finished.
Note: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag
This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.
Note: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag
Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.
Note 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag
This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits).
Note: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0).
Note: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.
Note: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)
This bit initiate RX FIFO empty or not.
Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)
This bit initiates RX FIFO full or not.
Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)
This bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)
This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer is equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)
This bit indicates TX FIFO empty or not.
Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)
This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)
This bit indicates TX FIFO full or not.
Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
Note: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)
This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer is equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)
This bit indicates TX and RX are active or inactive.
Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller cannot transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
-1
read-write
n
0x0
0x0
DGE
Deglitch Enable Bit
Note 1: When this bit is set to logic 1, any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic.
Note 2: It is recommended to set this bit only when operating at baud rate under 2.5 Mbps.
6
1
read-write
0
Deglitch Disabled
#0
1
Deglitch Enabled
#1
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit
Setting this bit can disable TX and RX.
Note: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
-1
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit
Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit
Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit
This bit can enable or disable RX PDMA service.
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit
Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.
Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Interrupt Disabled
#0
1
Single-wire Bit Error Detect Interrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit
If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)
This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag
When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)
This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag
This bit is set when the single wire bus state is not equal to UART controller TX state in Single-wire mode.
Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
Note 2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)
This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag
This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)
This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag
This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only)
This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)
This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.
Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)
This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
-1
read-write
n
0x0
0x0
BCB
Break Control Bit
Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit
Note: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
PARITY Bit Enable Bit
Note: PARITY bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
PARITY bit generated Disabled
#0
1
PARITY bit generated Enabled
#1
PSS
PARITY Bit Source Selection
The PARITY bit can be selected to be generated and checked automatically or by software.
Note 1: This bit has effect only when PBE (UART_LINE[3]) is set.
Note 2: If PSS is 0, the PARITY bit is transmitted and checked automatically. If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (UART_DAT[8]) and the PARITY bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
PARITY bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
PARITY bit generated and checked by software
#1
RXDINV
RX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit
Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection
This field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS Signal Control
This bit is direct control internal nRTS (Request-to-send) signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
Note 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
Note 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
Note 3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level
This bit defines the active level state of nRTS pin output.
Note 1: Refer to Figure 6.1213 and Figure 6.1214 for UART function mode.
Note 2: Refer to Figure 6.1217 and Figure 6.1218 for RS-485 function mode.
Note 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)
This bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level
This bit defines the active level state of nCTS pin input.
Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)
This bit mirror from nCTS pin input of voltage logic status.
Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
-1
read-write
n
0x0
0x0
DLY
TX Delay Time Value
This field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
-1
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit
Note: When the system is in Power-down mode, an external nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit
Note: When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit
Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match Wake-up Enable Bit
Note 1: When the system is in Power-down mode, RS-485 Address Match will wake up system from Power-down mode.
Note 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit
Note 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.
Note 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
-1
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag
This bit is set if chip wake-up from power-down state by nCTS wake-up.
Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag
This bit is set if chip wake-up from power-down state by data wake-up.
Note 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold
wake-up .
Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match Wake-up Flag
This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).
Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.
Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UART4
UART Register Map
UART
0x0
0x0
0x34
registers
n
0x40
0xC
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length
Note : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from START bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from START bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from START bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from START bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit
Note : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit
This bit is used to enable RS-485 Address Detection mode.
Note: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value
This field contains the RS-485 address match values.
Note: This field is used for RS-485 auto address detection mode.
24
8
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode
Note: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function
Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode
Note: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0
This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.124.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1
This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.124.
Note: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider
The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.124.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1
This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.124.
24
4
read-write
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
-1
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer
Write Operation:
By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
Read Operation:
By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
PARITY Bit Receive/Transmit Buffer
Write Operation:
By writing to this bit, the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.
Read Operation:
If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the PARITY bit can be read by this bit.
Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
-1
read-write
n
0x0
0x0
STCOMP
START Bit Compensation Value
These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode.
Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level
When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control
Note: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit
The receiver is disabled or not (set 1 to disable receiver).
Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset
When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset
When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag
This bit is set to logic '1' when auto-baud rate detect function is finished.
Note: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag
This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.
Note: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag
Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.
Note 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag
This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits).
Note: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0).
Note: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.
Note: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)
This bit initiate RX FIFO empty or not.
Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)
This bit initiates RX FIFO full or not.
Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)
This bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)
This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer is equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)
This bit indicates TX FIFO empty or not.
Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)
This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)
This bit indicates TX FIFO full or not.
Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
Note: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)
This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer is equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)
This bit indicates TX and RX are active or inactive.
Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller cannot transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
-1
read-write
n
0x0
0x0
DGE
Deglitch Enable Bit
Note 1: When this bit is set to logic 1, any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic.
Note 2: It is recommended to set this bit only when operating at baud rate under 2.5 Mbps.
6
1
read-write
0
Deglitch Disabled
#0
1
Deglitch Enabled
#1
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit
Setting this bit can disable TX and RX.
Note: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
-1
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit
Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit
Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit
This bit can enable or disable RX PDMA service.
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit
Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.
Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Interrupt Disabled
#0
1
Single-wire Bit Error Detect Interrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit
If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)
This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag
When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)
This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag
This bit is set when the single wire bus state is not equal to UART controller TX state in Single-wire mode.
Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
Note 2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)
This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag
This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)
This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag
This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only)
This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)
This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.
Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)
This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
-1
read-write
n
0x0
0x0
BCB
Break Control Bit
Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit
Note: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
PARITY Bit Enable Bit
Note: PARITY bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
PARITY bit generated Disabled
#0
1
PARITY bit generated Enabled
#1
PSS
PARITY Bit Source Selection
The PARITY bit can be selected to be generated and checked automatically or by software.
Note 1: This bit has effect only when PBE (UART_LINE[3]) is set.
Note 2: If PSS is 0, the PARITY bit is transmitted and checked automatically. If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (UART_DAT[8]) and the PARITY bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
PARITY bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
PARITY bit generated and checked by software
#1
RXDINV
RX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit
Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection
This field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS Signal Control
This bit is direct control internal nRTS (Request-to-send) signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
Note 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
Note 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
Note 3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level
This bit defines the active level state of nRTS pin output.
Note 1: Refer to Figure 6.1213 and Figure 6.1214 for UART function mode.
Note 2: Refer to Figure 6.1217 and Figure 6.1218 for RS-485 function mode.
Note 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)
This bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level
This bit defines the active level state of nCTS pin input.
Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)
This bit mirror from nCTS pin input of voltage logic status.
Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
-1
read-write
n
0x0
0x0
DLY
TX Delay Time Value
This field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
-1
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit
Note: When the system is in Power-down mode, an external nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit
Note: When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit
Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match Wake-up Enable Bit
Note 1: When the system is in Power-down mode, RS-485 Address Match will wake up system from Power-down mode.
Note 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit
Note 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.
Note 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
-1
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag
This bit is set if chip wake-up from power-down state by nCTS wake-up.
Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag
This bit is set if chip wake-up from power-down state by data wake-up.
Note 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold
wake-up .
Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match Wake-up Flag
This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).
Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.
Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UI2C0
USCII2C Register Map
USCII2C
0x0
0x0
0x4
registers
n
0x2C
0xC
registers
n
0x44
0x24
registers
n
0x8
0x4
registers
n
0x88
0x8
registers
n
UI2C_ADDRMSK0
UI2C_ADDRMSK0
USCI Device Address Mask Register 0
0x4C
-1
read-write
n
0x0
0x0
ADDRMSK
USCI Device Address Mask
USCI supports multiple address recognition with two address mask register. When the bit in the address mask register is set to 1, it means the received corresponding address bit is don't-care. If the bit is set to 0, that means the received corresponding register bit should be exact the same as address register.
Note: The wake-up function cannot use address mask.
0
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
UI2C_ADDRMSK1
UI2C_ADDRMSK1
USCI Device Address Mask Register 1
0x50
-1
read-write
n
0x0
0x0
UI2C_ADMAT
UI2C_ADMAT
I2C Slave Match Address Register
0x88
-1
read-write
n
0x0
0x0
ADMAT0
USCI Address 0 Match Status Register
When address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
USCI Address 1 Match Status Register
When address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
UI2C_BRGEN
UI2C_BRGEN
USCI Baud Rate Generator Register
0x8
-1
read-write
n
0x0
0x0
CLKDIV
Clock Divider
16
10
read-write
DSCNT
Denominator for Sample Counter
This bit field defines the divide ratio of the sample clock fSAMP_CLK.
Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection
This bit selects the source signal of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection
This bit selects the source signal of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection
This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fSAMP_CLK = fDIV_CLK
#00
1
fSAMP_CLK = fPROT_CLK
#01
2
fSAMP_CLK = fSCLK
#10
3
fSAMP_CLK = fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit
This bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Time measurement counter Disabled
#0
1
Time measurement counter Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
UI2C_CTL
UI2C_CTL
USCI Control Register
0x0
-1
read-write
n
0x0
0x0
FUNMODE
Function Mode
This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
Note: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
UI2C_DEVADDR0
UI2C_DEVADDR0
USCI Device Address Register 0
0x44
-1
read-write
n
0x0
0x0
DEVADDR
Device Address
In I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].
Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
Note 2: When software sets 10'h000, the address cannot be used.
0
10
read-write
UI2C_DEVADDR1
UI2C_DEVADDR1
USCI Device Address Register 1
0x48
-1
read-write
n
0x0
0x0
UI2C_LINECTL
UI2C_LINECTL
USCI Line Control Register
0x2C
-1
read-write
n
0x0
0x0
DWIDTH
Word Length of Transmission
This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.
0x0: The data word contains 16 bits located at bit positions [15:0].
0x1: Reserved.
0x2: Reserved.
0x3: Reserved.
0x4: The data word contains 4 bits located at bit positions [3:0].
0x5: The data word contains 5 bits located at bit positions [4:0].
...
0xF: The data word contains 15 bits located at bit positions [14:0].
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
UI2C_PROTCTL
UI2C_PROTCTL
USCI Protocol Control Register
0x5C
-1
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
1
1
read-write
ADDR10EN
Address 10-bit Function Enable Bit
4
1
read-write
0
Address match 10 bit function Disabled
#0
1
Address match 10 bit function Enabled
#1
GCFUNC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
MONEN
Monitor Mode Enable Bit
This bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.
Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
9
1
read-write
0
The monitor mode Disabled
#0
1
The monitor mode Enabled
#1
PROTEN
I2C Protocol Enable Bit
31
1
read-write
0
I2C Protocol Disabled
#0
1
I2C Protocol Enabled
#1
PTRG
I2C Protocol Trigger (Write Only)
When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
5
1
write-only
0
I2C's stretch disabled and the I2C protocol function will go ahead
#0
1
I2C's stretch active
#1
SCLOUTEN
SCL Output Enable Bit
This bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
8
1
read-write
0
SCL output will be forced high due to open drain mechanism
#0
1
I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt
#1
STA
I2C START Control
Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
3
1
read-write
STO
I2C STOP Control
2
1
read-write
TOCNT
Time-out Clock Cycle
This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0.
Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set as 0 on I2C mode.
16
10
read-write
UI2C_PROTIEN
UI2C_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
-1
read-write
n
0x0
0x0
ACKIEN
Acknowledge Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
6
1
read-write
0
The acknowledge interrupt Disabled
#0
1
The acknowledge interrupt Enabled
#1
ARBLOIEN
Arbitration Lost Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
4
1
read-write
0
The arbitration lost interrupt Disabled
#0
1
The arbitration lost interrupt Enabled
#1
ERRIEN
Error Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).
5
1
read-write
0
The error interrupt Disabled
#0
1
The error interrupt Enabled
#1
NACKIEN
Non - Acknowledge Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master.
3
1
read-write
0
The non - acknowledge interrupt Disabled
#0
1
The non - acknowledge interrupt Enabled
#1
STARIEN
START Condition Received Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if a START condition is detected.
1
1
read-write
0
The start condition interrupt Disabled
#0
1
The start condition interrupt Enabled
#1
STORIEN
STOP Condition Received Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if a STOP condition is detected.
2
1
read-write
0
The stop condition interrupt Disabled
#0
1
The stop condition interrupt Enabled
#1
TOIEN
Time-out Interrupt Enable Bit
In I2C protocol, this bit enables the interrupt generation in case of a time-out event.
0
1
read-write
0
The time-out interrupt Disabled
#0
1
The time-out interrupt Enabled
#1
UI2C_PROTSTS
UI2C_PROTSTS
USCI Protocol Status Register
0x64
-1
read-write
n
0x0
0x0
ACKIF
Acknowledge Received Interrupt Flag
Note: It is cleared by software writing 1 into this bit.
13
1
read-write
0
An acknowledge has not been received
#0
1
An acknowledge has been received
#1
ARBLOIF
Arbitration Lost Interrupt Flag
Note: It is cleared by software writing 1 into this bit.
11
1
read-write
0
An arbitration has not been lost
#0
1
An arbitration has been lost
#1
BUSHANG
Bus Hang-up
This bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal.
Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
18
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is hang-up status for transmission
#1
ERRARBLO
Error Arbitration Lost
This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.
Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
19
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is error arbitration lost status for transmission
#1
ERRIF
Error Interrupt Flag
Note 1: It is cleared by software writing 1 into this bit
Note 2: This bit is set for slave mode, and user must write 1 into STO register to the defined 'not addressed' slave mode.
12
1
read-write
0
An I2C error has not been detected
#0
1
An I2C error has been detected
#1
NACKIF
Non - Acknowledge Received Interrupt Flag
Note: It is cleared by software writing 1 into this bit.
10
1
read-write
0
A non - acknowledge has not been received
#0
1
A non - acknowledge has been received
#1
ONBUSY
On Bus Busy
Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
6
1
read-write
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
SLAREAD
Slave Read Request Status
This bit indicates that a slave read request has been detected.
Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
15
1
read-write
0
A slave R/W bit is 1 has not been detected
#0
1
A slave R/W bit is 1 has been detected
#1
SLASEL
Slave Select Status
This bit indicates that this device has been selected as slave.
Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
14
1
read-write
0
The device is not selected as slave
#0
1
The device is selected as slave
#1
STARIF
Start Condition Received Interrupt Flag
This bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.
Note: It is cleared by software writing 1 into this bit.
8
1
read-write
0
A start condition has not yet been detected
#0
1
A start condition has been detected
#1
STORIF
Stop Condition Received Interrupt Flag
Note 1: It is cleared by software writing 1 into this bit.
9
1
read-write
0
A stop condition has not yet been detected
#0
1
A stop condition has been detected
#1
TOIF
Time-out Interrupt Flag
Note: It is cleared by software writing 1 into this bit
5
1
read-write
0
A time-out interrupt status has not occurred
#0
1
A time-out interrupt status has occurred
#1
WKAKDONE
Wake-up Address Frame Acknowledge Bit Done
Note: This bit can't release when WKUPIF is set.
16
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WRSTSWK
Read/Write Status Bit in Address Wake-up Frame
17
1
read-write
0
Write command is recorded on the address match wake-up frame
#0
1
Read command is recorded on the address match wake-up frame
#1
UI2C_RXDAT
UI2C_RXDAT
USCI Receive Data Register
0x34
-1
read-only
n
0x0
0x0
RXDAT
Received Data
This bit field monitors the received data which stored in receive data buffer.
Note: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions defined in I2C.
0
16
read-only
UI2C_TMCTL
UI2C_TMCTL
I2C Timing Configure Control Register
0x8C
-1
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control
This field is used to generate the delay timing between SCL falling edge SDA edge in
transmission mode.
16
9
read-write
STCTL
Setup Time Configure Control
This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.
0
9
read-write
UI2C_TXDAT
UI2C_TXDAT
USCI Transmit Data Register
0x30
-1
write-only
n
0x0
0x0
TXDAT
Transmit Data
Software can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
UI2C_WKCTL
UI2C_WKCTL
USCI Wake-up Control Register
0x54
-1
read-write
n
0x0
0x0
WKADDREN
Wake-up Address Match Enable Bit
1
1
read-write
0
The chip is woken up according to data toggle
#0
1
The chip is woken up according to address match
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
UI2C_WKSTS
UI2C_WKSTS
USCI Wake-up Status Register
0x58
-1
read-write
n
0x0
0x0
WKF
Wake-up Flag
When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
UI2C1
USCII2C Register Map
USCII2C
0x0
0x0
0x4
registers
n
0x2C
0xC
registers
n
0x44
0x24
registers
n
0x8
0x4
registers
n
0x88
0x8
registers
n
UI2C_ADDRMSK0
UI2C_ADDRMSK0
USCI Device Address Mask Register 0
0x4C
-1
read-write
n
0x0
0x0
ADDRMSK
USCI Device Address Mask
USCI supports multiple address recognition with two address mask register. When the bit in the address mask register is set to 1, it means the received corresponding address bit is don't-care. If the bit is set to 0, that means the received corresponding register bit should be exact the same as address register.
Note: The wake-up function cannot use address mask.
0
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
UI2C_ADDRMSK1
UI2C_ADDRMSK1
USCI Device Address Mask Register 1
0x50
-1
read-write
n
0x0
0x0
UI2C_ADMAT
UI2C_ADMAT
I2C Slave Match Address Register
0x88
-1
read-write
n
0x0
0x0
ADMAT0
USCI Address 0 Match Status Register
When address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
USCI Address 1 Match Status Register
When address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
UI2C_BRGEN
UI2C_BRGEN
USCI Baud Rate Generator Register
0x8
-1
read-write
n
0x0
0x0
CLKDIV
Clock Divider
16
10
read-write
DSCNT
Denominator for Sample Counter
This bit field defines the divide ratio of the sample clock fSAMP_CLK.
Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection
This bit selects the source signal of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection
This bit selects the source signal of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection
This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fSAMP_CLK = fDIV_CLK
#00
1
fSAMP_CLK = fPROT_CLK
#01
2
fSAMP_CLK = fSCLK
#10
3
fSAMP_CLK = fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit
This bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Time measurement counter Disabled
#0
1
Time measurement counter Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
UI2C_CTL
UI2C_CTL
USCI Control Register
0x0
-1
read-write
n
0x0
0x0
FUNMODE
Function Mode
This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
Note: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
UI2C_DEVADDR0
UI2C_DEVADDR0
USCI Device Address Register 0
0x44
-1
read-write
n
0x0
0x0
DEVADDR
Device Address
In I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].
Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
Note 2: When software sets 10'h000, the address cannot be used.
0
10
read-write
UI2C_DEVADDR1
UI2C_DEVADDR1
USCI Device Address Register 1
0x48
-1
read-write
n
0x0
0x0
UI2C_LINECTL
UI2C_LINECTL
USCI Line Control Register
0x2C
-1
read-write
n
0x0
0x0
DWIDTH
Word Length of Transmission
This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.
0x0: The data word contains 16 bits located at bit positions [15:0].
0x1: Reserved.
0x2: Reserved.
0x3: Reserved.
0x4: The data word contains 4 bits located at bit positions [3:0].
0x5: The data word contains 5 bits located at bit positions [4:0].
...
0xF: The data word contains 15 bits located at bit positions [14:0].
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
UI2C_PROTCTL
UI2C_PROTCTL
USCI Protocol Control Register
0x5C
-1
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
1
1
read-write
ADDR10EN
Address 10-bit Function Enable Bit
4
1
read-write
0
Address match 10 bit function Disabled
#0
1
Address match 10 bit function Enabled
#1
GCFUNC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
MONEN
Monitor Mode Enable Bit
This bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.
Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
9
1
read-write
0
The monitor mode Disabled
#0
1
The monitor mode Enabled
#1
PROTEN
I2C Protocol Enable Bit
31
1
read-write
0
I2C Protocol Disabled
#0
1
I2C Protocol Enabled
#1
PTRG
I2C Protocol Trigger (Write Only)
When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
5
1
write-only
0
I2C's stretch disabled and the I2C protocol function will go ahead
#0
1
I2C's stretch active
#1
SCLOUTEN
SCL Output Enable Bit
This bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
8
1
read-write
0
SCL output will be forced high due to open drain mechanism
#0
1
I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt
#1
STA
I2C START Control
Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
3
1
read-write
STO
I2C STOP Control
2
1
read-write
TOCNT
Time-out Clock Cycle
This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0.
Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set as 0 on I2C mode.
16
10
read-write
UI2C_PROTIEN
UI2C_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
-1
read-write
n
0x0
0x0
ACKIEN
Acknowledge Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
6
1
read-write
0
The acknowledge interrupt Disabled
#0
1
The acknowledge interrupt Enabled
#1
ARBLOIEN
Arbitration Lost Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
4
1
read-write
0
The arbitration lost interrupt Disabled
#0
1
The arbitration lost interrupt Enabled
#1
ERRIEN
Error Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).
5
1
read-write
0
The error interrupt Disabled
#0
1
The error interrupt Enabled
#1
NACKIEN
Non - Acknowledge Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master.
3
1
read-write
0
The non - acknowledge interrupt Disabled
#0
1
The non - acknowledge interrupt Enabled
#1
STARIEN
START Condition Received Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if a START condition is detected.
1
1
read-write
0
The start condition interrupt Disabled
#0
1
The start condition interrupt Enabled
#1
STORIEN
STOP Condition Received Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if a STOP condition is detected.
2
1
read-write
0
The stop condition interrupt Disabled
#0
1
The stop condition interrupt Enabled
#1
TOIEN
Time-out Interrupt Enable Bit
In I2C protocol, this bit enables the interrupt generation in case of a time-out event.
0
1
read-write
0
The time-out interrupt Disabled
#0
1
The time-out interrupt Enabled
#1
UI2C_PROTSTS
UI2C_PROTSTS
USCI Protocol Status Register
0x64
-1
read-write
n
0x0
0x0
ACKIF
Acknowledge Received Interrupt Flag
Note: It is cleared by software writing 1 into this bit.
13
1
read-write
0
An acknowledge has not been received
#0
1
An acknowledge has been received
#1
ARBLOIF
Arbitration Lost Interrupt Flag
Note: It is cleared by software writing 1 into this bit.
11
1
read-write
0
An arbitration has not been lost
#0
1
An arbitration has been lost
#1
BUSHANG
Bus Hang-up
This bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal.
Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
18
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is hang-up status for transmission
#1
ERRARBLO
Error Arbitration Lost
This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.
Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
19
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is error arbitration lost status for transmission
#1
ERRIF
Error Interrupt Flag
Note 1: It is cleared by software writing 1 into this bit
Note 2: This bit is set for slave mode, and user must write 1 into STO register to the defined 'not addressed' slave mode.
12
1
read-write
0
An I2C error has not been detected
#0
1
An I2C error has been detected
#1
NACKIF
Non - Acknowledge Received Interrupt Flag
Note: It is cleared by software writing 1 into this bit.
10
1
read-write
0
A non - acknowledge has not been received
#0
1
A non - acknowledge has been received
#1
ONBUSY
On Bus Busy
Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
6
1
read-write
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
SLAREAD
Slave Read Request Status
This bit indicates that a slave read request has been detected.
Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
15
1
read-write
0
A slave R/W bit is 1 has not been detected
#0
1
A slave R/W bit is 1 has been detected
#1
SLASEL
Slave Select Status
This bit indicates that this device has been selected as slave.
Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
14
1
read-write
0
The device is not selected as slave
#0
1
The device is selected as slave
#1
STARIF
Start Condition Received Interrupt Flag
This bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.
Note: It is cleared by software writing 1 into this bit.
8
1
read-write
0
A start condition has not yet been detected
#0
1
A start condition has been detected
#1
STORIF
Stop Condition Received Interrupt Flag
Note 1: It is cleared by software writing 1 into this bit.
9
1
read-write
0
A stop condition has not yet been detected
#0
1
A stop condition has been detected
#1
TOIF
Time-out Interrupt Flag
Note: It is cleared by software writing 1 into this bit
5
1
read-write
0
A time-out interrupt status has not occurred
#0
1
A time-out interrupt status has occurred
#1
WKAKDONE
Wake-up Address Frame Acknowledge Bit Done
Note: This bit can't release when WKUPIF is set.
16
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WRSTSWK
Read/Write Status Bit in Address Wake-up Frame
17
1
read-write
0
Write command is recorded on the address match wake-up frame
#0
1
Read command is recorded on the address match wake-up frame
#1
UI2C_RXDAT
UI2C_RXDAT
USCI Receive Data Register
0x34
-1
read-only
n
0x0
0x0
RXDAT
Received Data
This bit field monitors the received data which stored in receive data buffer.
Note: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions defined in I2C.
0
16
read-only
UI2C_TMCTL
UI2C_TMCTL
I2C Timing Configure Control Register
0x8C
-1
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control
This field is used to generate the delay timing between SCL falling edge SDA edge in
transmission mode.
16
9
read-write
STCTL
Setup Time Configure Control
This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.
0
9
read-write
UI2C_TXDAT
UI2C_TXDAT
USCI Transmit Data Register
0x30
-1
write-only
n
0x0
0x0
TXDAT
Transmit Data
Software can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
UI2C_WKCTL
UI2C_WKCTL
USCI Wake-up Control Register
0x54
-1
read-write
n
0x0
0x0
WKADDREN
Wake-up Address Match Enable Bit
1
1
read-write
0
The chip is woken up according to data toggle
#0
1
The chip is woken up according to address match
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
UI2C_WKSTS
UI2C_WKSTS
USCI Wake-up Status Register
0x58
-1
read-write
n
0x0
0x0
WKF
Wake-up Flag
When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
UI2C2
USCII2C Register Map
USCII2C
0x0
0x0
0x4
registers
n
0x2C
0xC
registers
n
0x44
0x24
registers
n
0x8
0x4
registers
n
0x88
0x8
registers
n
UI2C_ADDRMSK0
UI2C_ADDRMSK0
USCI Device Address Mask Register 0
0x4C
-1
read-write
n
0x0
0x0
ADDRMSK
USCI Device Address Mask
USCI supports multiple address recognition with two address mask register. When the bit in the address mask register is set to 1, it means the received corresponding address bit is don't-care. If the bit is set to 0, that means the received corresponding register bit should be exact the same as address register.
Note: The wake-up function cannot use address mask.
0
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
UI2C_ADDRMSK1
UI2C_ADDRMSK1
USCI Device Address Mask Register 1
0x50
-1
read-write
n
0x0
0x0
UI2C_ADMAT
UI2C_ADMAT
I2C Slave Match Address Register
0x88
-1
read-write
n
0x0
0x0
ADMAT0
USCI Address 0 Match Status Register
When address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
USCI Address 1 Match Status Register
When address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
UI2C_BRGEN
UI2C_BRGEN
USCI Baud Rate Generator Register
0x8
-1
read-write
n
0x0
0x0
CLKDIV
Clock Divider
16
10
read-write
DSCNT
Denominator for Sample Counter
This bit field defines the divide ratio of the sample clock fSAMP_CLK.
Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection
This bit selects the source signal of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection
This bit selects the source signal of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection
This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fSAMP_CLK = fDIV_CLK
#00
1
fSAMP_CLK = fPROT_CLK
#01
2
fSAMP_CLK = fSCLK
#10
3
fSAMP_CLK = fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit
This bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Time measurement counter Disabled
#0
1
Time measurement counter Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
UI2C_CTL
UI2C_CTL
USCI Control Register
0x0
-1
read-write
n
0x0
0x0
FUNMODE
Function Mode
This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
Note: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
UI2C_DEVADDR0
UI2C_DEVADDR0
USCI Device Address Register 0
0x44
-1
read-write
n
0x0
0x0
DEVADDR
Device Address
In I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].
Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
Note 2: When software sets 10'h000, the address cannot be used.
0
10
read-write
UI2C_DEVADDR1
UI2C_DEVADDR1
USCI Device Address Register 1
0x48
-1
read-write
n
0x0
0x0
UI2C_LINECTL
UI2C_LINECTL
USCI Line Control Register
0x2C
-1
read-write
n
0x0
0x0
DWIDTH
Word Length of Transmission
This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.
0x0: The data word contains 16 bits located at bit positions [15:0].
0x1: Reserved.
0x2: Reserved.
0x3: Reserved.
0x4: The data word contains 4 bits located at bit positions [3:0].
0x5: The data word contains 5 bits located at bit positions [4:0].
...
0xF: The data word contains 15 bits located at bit positions [14:0].
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
UI2C_PROTCTL
UI2C_PROTCTL
USCI Protocol Control Register
0x5C
-1
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
1
1
read-write
ADDR10EN
Address 10-bit Function Enable Bit
4
1
read-write
0
Address match 10 bit function Disabled
#0
1
Address match 10 bit function Enabled
#1
GCFUNC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
MONEN
Monitor Mode Enable Bit
This bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.
Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
9
1
read-write
0
The monitor mode Disabled
#0
1
The monitor mode Enabled
#1
PROTEN
I2C Protocol Enable Bit
31
1
read-write
0
I2C Protocol Disabled
#0
1
I2C Protocol Enabled
#1
PTRG
I2C Protocol Trigger (Write Only)
When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
5
1
write-only
0
I2C's stretch disabled and the I2C protocol function will go ahead
#0
1
I2C's stretch active
#1
SCLOUTEN
SCL Output Enable Bit
This bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
8
1
read-write
0
SCL output will be forced high due to open drain mechanism
#0
1
I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt
#1
STA
I2C START Control
Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
3
1
read-write
STO
I2C STOP Control
2
1
read-write
TOCNT
Time-out Clock Cycle
This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0.
Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set as 0 on I2C mode.
16
10
read-write
UI2C_PROTIEN
UI2C_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
-1
read-write
n
0x0
0x0
ACKIEN
Acknowledge Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
6
1
read-write
0
The acknowledge interrupt Disabled
#0
1
The acknowledge interrupt Enabled
#1
ARBLOIEN
Arbitration Lost Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
4
1
read-write
0
The arbitration lost interrupt Disabled
#0
1
The arbitration lost interrupt Enabled
#1
ERRIEN
Error Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).
5
1
read-write
0
The error interrupt Disabled
#0
1
The error interrupt Enabled
#1
NACKIEN
Non - Acknowledge Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master.
3
1
read-write
0
The non - acknowledge interrupt Disabled
#0
1
The non - acknowledge interrupt Enabled
#1
STARIEN
START Condition Received Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if a START condition is detected.
1
1
read-write
0
The start condition interrupt Disabled
#0
1
The start condition interrupt Enabled
#1
STORIEN
STOP Condition Received Interrupt Enable Bit
This bit enables the generation of a protocol interrupt if a STOP condition is detected.
2
1
read-write
0
The stop condition interrupt Disabled
#0
1
The stop condition interrupt Enabled
#1
TOIEN
Time-out Interrupt Enable Bit
In I2C protocol, this bit enables the interrupt generation in case of a time-out event.
0
1
read-write
0
The time-out interrupt Disabled
#0
1
The time-out interrupt Enabled
#1
UI2C_PROTSTS
UI2C_PROTSTS
USCI Protocol Status Register
0x64
-1
read-write
n
0x0
0x0
ACKIF
Acknowledge Received Interrupt Flag
Note: It is cleared by software writing 1 into this bit.
13
1
read-write
0
An acknowledge has not been received
#0
1
An acknowledge has been received
#1
ARBLOIF
Arbitration Lost Interrupt Flag
Note: It is cleared by software writing 1 into this bit.
11
1
read-write
0
An arbitration has not been lost
#0
1
An arbitration has been lost
#1
BUSHANG
Bus Hang-up
This bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal.
Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
18
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is hang-up status for transmission
#1
ERRARBLO
Error Arbitration Lost
This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.
Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
19
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is error arbitration lost status for transmission
#1
ERRIF
Error Interrupt Flag
Note 1: It is cleared by software writing 1 into this bit
Note 2: This bit is set for slave mode, and user must write 1 into STO register to the defined 'not addressed' slave mode.
12
1
read-write
0
An I2C error has not been detected
#0
1
An I2C error has been detected
#1
NACKIF
Non - Acknowledge Received Interrupt Flag
Note: It is cleared by software writing 1 into this bit.
10
1
read-write
0
A non - acknowledge has not been received
#0
1
A non - acknowledge has been received
#1
ONBUSY
On Bus Busy
Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
6
1
read-write
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
SLAREAD
Slave Read Request Status
This bit indicates that a slave read request has been detected.
Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
15
1
read-write
0
A slave R/W bit is 1 has not been detected
#0
1
A slave R/W bit is 1 has been detected
#1
SLASEL
Slave Select Status
This bit indicates that this device has been selected as slave.
Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
14
1
read-write
0
The device is not selected as slave
#0
1
The device is selected as slave
#1
STARIF
Start Condition Received Interrupt Flag
This bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.
Note: It is cleared by software writing 1 into this bit.
8
1
read-write
0
A start condition has not yet been detected
#0
1
A start condition has been detected
#1
STORIF
Stop Condition Received Interrupt Flag
Note 1: It is cleared by software writing 1 into this bit.
9
1
read-write
0
A stop condition has not yet been detected
#0
1
A stop condition has been detected
#1
TOIF
Time-out Interrupt Flag
Note: It is cleared by software writing 1 into this bit
5
1
read-write
0
A time-out interrupt status has not occurred
#0
1
A time-out interrupt status has occurred
#1
WKAKDONE
Wake-up Address Frame Acknowledge Bit Done
Note: This bit can't release when WKUPIF is set.
16
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WRSTSWK
Read/Write Status Bit in Address Wake-up Frame
17
1
read-write
0
Write command is recorded on the address match wake-up frame
#0
1
Read command is recorded on the address match wake-up frame
#1
UI2C_RXDAT
UI2C_RXDAT
USCI Receive Data Register
0x34
-1
read-only
n
0x0
0x0
RXDAT
Received Data
This bit field monitors the received data which stored in receive data buffer.
Note: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions defined in I2C.
0
16
read-only
UI2C_TMCTL
UI2C_TMCTL
I2C Timing Configure Control Register
0x8C
-1
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control
This field is used to generate the delay timing between SCL falling edge SDA edge in
transmission mode.
16
9
read-write
STCTL
Setup Time Configure Control
This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.
0
9
read-write
UI2C_TXDAT
UI2C_TXDAT
USCI Transmit Data Register
0x30
-1
write-only
n
0x0
0x0
TXDAT
Transmit Data
Software can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
UI2C_WKCTL
UI2C_WKCTL
USCI Wake-up Control Register
0x54
-1
read-write
n
0x0
0x0
WKADDREN
Wake-up Address Match Enable Bit
1
1
read-write
0
The chip is woken up according to data toggle
#0
1
The chip is woken up according to address match
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
UI2C_WKSTS
UI2C_WKSTS
USCI Wake-up Status Register
0x58
-1
read-write
n
0x0
0x0
WKF
Wake-up Flag
When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
USBD
USBD Register Map
USBD
0x0
0x0
0x1C
registers
n
0x20
0xC
registers
n
0x500
0x110
registers
n
0x88
0xC
registers
n
ATTR
USBD_ATTR
USB Device Bus Status and Attribution Register
0x10
-1
read-write
n
0x0
0x0
BYTEM
CPU Access USB SRAM Size Mode Selection
10
1
read-write
0
Word mode: The size of the transfer from CPU to USB SRAM can be Word only
#0
1
Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only
#1
DPPUEN
Pull-up Resistor on USB_DP Enable Bit
8
1
read-write
0
Pull-up resistor in USB_D+ bus Disabled
#0
1
Pull-up resistor in USB_D+ bus Active
#1
L1RESUME
LPM L1 Resume (Read Only)
13
1
read-only
0
Bus has no LPM L1 state resume
#0
1
LPM L1 state resume from LPM L1 state suspend
#1
L1SUSPEND
LPM L1 Suspend (Read Only)
12
1
read-only
0
Bus has no L1 state suspend
#0
1
This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged
#1
LPMACK
LPM Token Acknowledge Enable Bit
11
1
read-write
0
The valid LPM Token will be NYET
#0
1
The valid LPM Token will be ACK
#1
PHYEN
PHY Transceiver Function Enable Bit
4
1
read-write
0
PHY transceiver function Disabled
#0
1
PHY transceiver function Enabled
#1
PWRDN
Power-down PHY Transceiver, Low Active
9
1
read-write
0
Power-down related circuit of PHY transceiver
#0
1
Turn-on related circuit of PHY transceiver
#1
RESUME
Resume Status (Read Only)
2
1
read-only
0
No bus resume
#0
1
Resume from suspend
#1
RWAKEUP
Remote Wake-up
5
1
read-write
0
Release the USB bus from K state
#0
1
Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up
#1
SUSPEND
Suspend Status (Read Only)
1
1
read-only
0
Bus no suspend
#0
1
Bus idle more than 3ms, either cable is plugged out or host is sleeping
#1
TOUT
Time-out Status (Read Only)
3
1
read-only
0
No time-out
#0
1
No Bus response more than 18 bits time (
#1
USBEN
USB Controller Enable Bit
7
1
read-write
0
USB Controller Disabled
#0
1
USB Controller Enabled
#1
USBRST
USB Reset Status (Read Only)
0
1
read-only
0
Bus no reset
#0
1
Bus reset when SE0 (single-ended 0) more than 2.5us
#1
BUFSEG0
USBD_BUFSEG0
Endpoint 0 Buffer Segmentation Register
0x500
-1
read-write
n
0x0
0x0
BUFSEG
Endpoint Buffer Segmentation
It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:
USBD_SRAM address + { BUFSE.G. 3'b000}
Refer to the endpoint SRAM structure and its description.
3
6
read-write
BUFSEG1
USBD_BUFSEG1
Endpoint 1 Buffer Segmentation Register
0x510
-1
read-write
n
0x0
0x0
BUFSEG10
USBD_BUFSEG10
Endpoint 10 Buffer Segmentation Register
0x5A0
-1
read-write
n
0x0
0x0
BUFSEG11
USBD_BUFSEG11
Endpoint 11 Buffer Segmentation Register
0x5B0
-1
read-write
n
0x0
0x0
BUFSEG12
USBD_BUFSEG12
Endpoint 12 Buffer Segmentation Register
0x5C0
-1
read-write
n
0x0
0x0
BUFSEG13
USBD_BUFSEG13
Endpoint 13 Buffer Segmentation Register
0x5D0
-1
read-write
n
0x0
0x0
BUFSEG14
USBD_BUFSEG14
Endpoint 14 Buffer Segmentation Register
0x5E0
-1
read-write
n
0x0
0x0
BUFSEG15
USBD_BUFSEG15
Endpoint 15 Buffer Segmentation Register
0x5F0
-1
read-write
n
0x0
0x0
BUFSEG16
USBD_BUFSEG16
Endpoint 16 Buffer Segmentation Register
0x600
-1
read-write
n
0x0
0x0
BUFSEG2
USBD_BUFSEG2
Endpoint 2 Buffer Segmentation Register
0x520
-1
read-write
n
0x0
0x0
BUFSEG3
USBD_BUFSEG3
Endpoint 3 Buffer Segmentation Register
0x530
-1
read-write
n
0x0
0x0
BUFSEG4
USBD_BUFSEG4
Endpoint 4 Buffer Segmentation Register
0x540
-1
read-write
n
0x0
0x0
BUFSEG5
USBD_BUFSEG5
Endpoint 5 Buffer Segmentation Register
0x550
-1
read-write
n
0x0
0x0
BUFSEG6
USBD_BUFSEG6
Endpoint 6 Buffer Segmentation Register
0x560
-1
read-write
n
0x0
0x0
BUFSEG7
USBD_BUFSEG7
Endpoint 7 Buffer Segmentation Register
0x570
-1
read-write
n
0x0
0x0
BUFSEG8
USBD_BUFSEG8
Endpoint 8 Buffer Segmentation Register
0x580
-1
read-write
n
0x0
0x0
BUFSEG9
USBD_BUFSEG9
Endpoint 9 Buffer Segmentation Register
0x590
-1
read-write
n
0x0
0x0
CFG0
USBD_CFG0
Endpoint 0 Configuration Register
0x508
-1
read-write
n
0x0
0x0
CSTALL
Clear STALL Response
9
1
read-write
0
Disable the device to clear the STALL handshake in setup stage
#0
1
Clear the device to response STALL handshake in setup stage
#1
DSQSYNC
Data Sequence Synchronization
Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on this bit.
7
1
read-write
0
DATA0 PID
#0
1
DATA1 PID
#1
EPNUM
Endpoint Number
These bits are used to define the endpoint number of the current endpoint.
0
4
read-write
ISOCH
Isochronous Endpoint
This bit is used to set the endpoint as Isochronous endpoint, no handshake.
4
1
read-write
0
No Isochronous endpoint
#0
1
Isochronous endpoint
#1
STATE
Endpoint State
5
2
read-write
0
Endpoint is Disabled
#00
1
Out endpoint
#01
2
IN endpoint
#10
3
Undefined
#11
CFG1
USBD_CFG1
Endpoint 1 Configuration Register
0x518
-1
read-write
n
0x0
0x0
CFG10
USBD_CFG10
Endpoint 10 Configuration Register
0x5A8
-1
read-write
n
0x0
0x0
CFG11
USBD_CFG11
Endpoint 11 Configuration Register
0x5B8
-1
read-write
n
0x0
0x0
CFG12
USBD_CFG12
Endpoint 12 Configuration Register
0x5C8
-1
read-write
n
0x0
0x0
CFG13
USBD_CFG13
Endpoint 13 Configuration Register
0x5D8
-1
read-write
n
0x0
0x0
CFG14
USBD_CFG14
Endpoint 14 Configuration Register
0x5E8
-1
read-write
n
0x0
0x0
CFG15
USBD_CFG15
Endpoint 15 Configuration Register
0x5F8
-1
read-write
n
0x0
0x0
CFG16
USBD_CFG16
Endpoint 16 Configuration Register
0x608
-1
read-write
n
0x0
0x0
CFG2
USBD_CFG2
Endpoint 2 Configuration Register
0x528
-1
read-write
n
0x0
0x0
CFG3
USBD_CFG3
Endpoint 3 Configuration Register
0x538
-1
read-write
n
0x0
0x0
CFG4
USBD_CFG4
Endpoint 4 Configuration Register
0x548
-1
read-write
n
0x0
0x0
CFG5
USBD_CFG5
Endpoint 5 Configuration Register
0x558
-1
read-write
n
0x0
0x0
CFG6
USBD_CFG6
Endpoint 6 Configuration Register
0x568
-1
read-write
n
0x0
0x0
CFG7
USBD_CFG7
Endpoint 7 Configuration Register
0x578
-1
read-write
n
0x0
0x0
CFG8
USBD_CFG8
Endpoint 8 Configuration Register
0x588
-1
read-write
n
0x0
0x0
CFG9
USBD_CFG9
Endpoint 9 Configuration Register
0x598
-1
read-write
n
0x0
0x0
CFGP0
USBD_CFGP0
Endpoint 0 Set Stall and Clear In/Out Ready Control Register
0x50C
-1
read-write
n
0x0
0x0
CLRRDY
Clear Ready
When the USBD_MXPLD0~16 register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.
For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
This bit is write 1 only and is always 0 when it is read back.
0
1
read-write
SSTALL
Set STALL
1
1
read-write
0
Disable the device to response STALL
#0
1
Set the device to respond STALL automatically
#1
CFGP1
USBD_CFGP1
Endpoint 1 Set Stall and Clear In/Out Ready Control Register
0x51C
-1
read-write
n
0x0
0x0
CFGP10
USBD_CFGP10
Endpoint 10 Set Stall and Clear In/Out Ready Control Register
0x5AC
-1
read-write
n
0x0
0x0
CFGP11
USBD_CFGP11
Endpoint 11 Set Stall and Clear In/Out Ready Control Register
0x5BC
-1
read-write
n
0x0
0x0
CFGP12
USBD_CFGP12
Endpoint 12 Set Stall and Clear In/Out Ready Control Register
0x5CC
-1
read-write
n
0x0
0x0
CFGP13
USBD_CFGP13
Endpoint 13 Set Stall and Clear In/Out Ready Control Register
0x5DC
-1
read-write
n
0x0
0x0
CFGP14
USBD_CFGP14
Endpoint 14 Set Stall and Clear In/Out Ready Control Register
0x5EC
-1
read-write
n
0x0
0x0
CFGP15
USBD_CFGP15
Endpoint 15 Set Stall and Clear In/Out Ready Control Register
0x5FC
-1
read-write
n
0x0
0x0
CFGP16
USBD_CFGP16
Endpoint 16 Set Stall and Clear In/Out Ready Control Register
0x60C
-1
read-write
n
0x0
0x0
CFGP2
USBD_CFGP2
Endpoint 2 Set Stall and Clear In/Out Ready Control Register
0x52C
-1
read-write
n
0x0
0x0
CFGP3
USBD_CFGP3
Endpoint 3 Set Stall and Clear In/Out Ready Control Register
0x53C
-1
read-write
n
0x0
0x0
CFGP4
USBD_CFGP4
Endpoint 4 Set Stall and Clear In/Out Ready Control Register
0x54C
-1
read-write
n
0x0
0x0
CFGP5
USBD_CFGP5
Endpoint 5 Set Stall and Clear In/Out Ready Control Register
0x55C
-1
read-write
n
0x0
0x0
CFGP6
USBD_CFGP6
Endpoint 6 Set Stall and Clear In/Out Ready Control Register
0x56C
-1
read-write
n
0x0
0x0
CFGP7
USBD_CFGP7
Endpoint 7 Set Stall and Clear In/Out Ready Control Register
0x57C
-1
read-write
n
0x0
0x0
CFGP8
USBD_CFGP8
Endpoint 8 Set Stall and Clear In/Out Ready Control Register
0x58C
-1
read-write
n
0x0
0x0
CFGP9
USBD_CFGP9
Endpoint 9 Set Stall and Clear In/Out Ready Control Register
0x59C
-1
read-write
n
0x0
0x0
EPSTS
USBD_EPSTS
USB Device Endpoint Status Register
0xC
-1
read-only
n
0x0
0x0
OV
Overrun
It indicates that the received data is more than the maximum payload number or not.
7
1
read-only
0
No overrun
#0
1
Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes
#1
EPSTS0
USBD_EPSTS0
USB Device Endpoint Status Register 0
0x20
-1
read-only
n
0x0
0x0
EPSTS5
Endpoint 5 Status
These bits are used to indicate the current status of this endpoint
20
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS6
Endpoint 6 Status
These bits are used to indicate the current status of this endpoint
24
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS7
Endpoint 7 Status
These bits are used to indicate the current status of this endpoint
28
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS1
USBD_EPSTS1
USB Device Endpoint Status Register 1
0x24
-1
read-only
n
0x0
0x0
EPSTS10
Endpoint 10 Status
These bits are used to indicate the current status of this endpoint
8
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS11
Endpoint 11 Status
These bits are used to indicate the current status of this endpoint
12
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS12
Endpoint 12 Status
These bits are used to indicate the current status of this endpoint
16
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS13
Endpoint 13 Status
These bits are used to indicate the current status of this endpoint
20
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS14
Endpoint 14 Status
These bits are used to indicate the current status of this endpoint
24
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS15
Endpoint 15 Status
These bits are used to indicate the current status of this endpoint
28
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS8
Endpoint 8 Status
These bits are used to indicate the current status of this endpoint
0
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS9
Endpoint 9 Status
These bits are used to indicate the current status of this endpoint
4
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS2
USBD_EPSTS2
USB Device Endpoint Status Register 2
0x28
-1
read-only
n
0x0
0x0
EPSTS16
Endpoint 16 Status
These bits are used to indicate the current status of this endpoint
0
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
FADDR
USBD_FADDR
USB Device Function Address Register
0x8
-1
read-write
n
0x0
0x0
FADDR
USB Device Function Address
0
7
read-write
FN
USBD_FN
USB Frame Number Register
0x8C
-1
read-only
n
0x0
0x0
FN
Frame Number
These bits contain the 11-bits frame number in the last received SOF packet.
Note: Suggest to read USBD_FN after USBD_INTSTS[4] SOFIF interrupt is triggered and cleared.
0
11
read-only
INTEN
USBD_INTEN
USB Device Interrupt Enable Register
0x0
-1
read-write
n
0x0
0x0
BUSIEN
Bus Event Interrupt Enable Bit
0
1
read-write
0
BUS event interrupt Disabled
#0
1
BUS event interrupt Enabled
#1
INNAKEN
Active NAK Function and Its Status in IN Token
15
1
read-write
0
When the device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1 register, so that the USB interrupt event will not be asserted
#0
1
IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted when the device responds NAK after receiving IN token
#1
NEVWKIEN
USB No-event-wake-up Interrupt Enable Bit
3
1
read-write
0
No-event-wake-up Interrupt Disabled
#0
1
No-event-wake-up Interrupt Enabled
#1
SOFIEN
Start of Frame Interrupt Enable Bit
4
1
read-write
0
SOF Interrupt Disabled
#0
1
SOF Interrupt Enabled
#1
USBIEN
USB Event Interrupt Enable Bit
1
1
read-write
0
USB event interrupt Disabled
#0
1
USB event interrupt Enabled
#1
VBDETIEN
VBUS Detection Interrupt Enable Bit
2
1
read-write
0
VBUS detection Interrupt Disabled
#0
1
VBUS detection Interrupt Enabled
#1
WKEN
Wake-up Function Enable Bit
Note: If woken up by any change by VBUS state, VBDETIEN must be enabled. If woken up by receiving resume signal, BUSIEN must be enabled.
8
1
read-write
0
USB wake-up function Disabled
#0
1
USB wake-up function Enabled
#1
INTSTS
USBD_INTSTS
USB Device Interrupt Event Status Register
0x4
-1
read-write
n
0x0
0x0
BUSIF
BUS Interrupt Status
The BUS event means that there is one of the suspense or the resume function in the bus.
0
1
read-write
0
No BUS event occurred
#0
1
Bus event occurred check USBD_ATTR[3:0] to know which kind of bus event occurred, and it is cleared by writing 1 to USBD_INTSTS[0]
#1
EPEVT0
Endpoint 0's USB Event Status
16
1
read-write
0
No event occurred in endpoint 0
#0
1
USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[16] or USBD_INTSTS[1]
#1
EPEVT1
Endpoint 1's USB Event Status
17
1
read-write
0
No event occurred in endpoint 1
#0
1
USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[17] or USBD_INTSTS[1]
#1
EPEVT10
Endpoint 10's USB Event Status
26
1
read-write
0
No event occurred in endpoint 10
#0
1
USB event occurred on Endpoint 10, check USBD_EPSTS1[11 :8] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[26] or USBD_INTSTS[1]
#1
EPEVT11
Endpoint 11's USB Event Status
27
1
read-write
0
No event occurred in endpoint 11
#0
1
USB event occurred on Endpoint 11 check USBD_EPSTS1[ 15:12] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[27] or USBD_INTSTS[1]
#1
EPEVT12
Endpoint 12's USB Event Status
28
1
read-write
0
No event occurred in endpoint 12
#0
1
USB event occurred on Endpoint 12 check USBD_EPSTS1[ 19:16] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[28] or USBD_INTSTS[1]
#1
EPEVT13
Endpoint 13's USB Event Status
29
1
read-write
0
No event occurred in endpoint 13
#0
1
USB event occurred on Endpoint 13 check USBD_EPSTS1[ 23:20] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[29] or USBD_INTSTS[1]
#1
EPEVT14
Endpoint 14's USB Event Status
30
1
read-write
0
No event occurred in endpoint 14
#0
1
USB event occurred on Endpoint 14 check USBD_EPSTS1[ 27:24] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[30] or USBD_INTSTS[1]
#1
EPEVT15
Endpoint 15's USB Event Status
8
1
read-write
0
No event occurred in endpoint 15
#0
1
USB event occurred on Endpoint 15 check USBD_EPSTS1[ 31:28] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[8] or USBD_INTSTS[1]
#1
EPEVT16
Endpoint 16's USB Event Status
9
1
read-write
0
No event occurred in endpoint 16
#0
1
USB event occurred on Endpoint 16 check USBD_EPSTS2[ 3:0] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[30] or USBD_INTSTS[1]
#1
EPEVT2
Endpoint 2's USB Event Status
18
1
read-write
0
No event occurred in endpoint 2
#0
1
USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[18] or USBD_INTSTS[1]
#1
EPEVT3
Endpoint 3's USB Event Status
19
1
read-write
0
No event occurred in endpoint 3
#0
1
USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[19] or USBD_INTSTS[1]
#1
EPEVT4
Endpoint 4's USB Event Status
20
1
read-write
0
No event occurred in endpoint 4
#0
1
USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[20] or USBD_INTSTS[1]
#1
EPEVT5
Endpoint 5's USB Event Status
21
1
read-write
0
No event occurred in endpoint 5
#0
1
USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[21] or USBD_INTSTS[1]
#1
EPEVT6
Endpoint 6's USB Event Status
22
1
read-write
0
No event occurred in endpoint 6
#0
1
USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[22] or USBD_INTSTS[1]
#1
EPEVT7
Endpoint 7's USB Event Status
23
1
read-write
0
No event occurred in endpoint 7
#0
1
USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[23] or USBD_INTSTS[1]
#1
EPEVT8
Endpoint 8's USB Event Status
24
1
read-write
0
No event occurred in endpoint 8
#0
1
USB event occurred on Endpoint 8 check USBD_EPSTS1[3 :0] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[24] or USBD_INTSTS[1]
#1
EPEVT9
Endpoint 9's USB Event Status
25
1
read-write
0
No event occurred in endpoint 9
#0
1
USB event occurred on Endpoint 9, check USBD_EPSTS1[7 :4] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[25] or USBD_INTSTS[1]
#1
NEVWKIF
No-event-wake-up Interrupt Status
3
1
read-write
0
NEVWK event did not occur
#0
1
No-event-wake-up event occurred, and it is cleared by writing 1 to USBD_INTSTS[3]
#1
SETUP
Setup Event Status
31
1
read-write
0
No Setup event
#0
1
Setup event occurred, and it is cleared by writing 1 to USBD_INTSTS[31]
#1
SOFIF
Start of Frame Interrupt Status
4
1
read-write
0
SOF event did not occur
#0
1
SOF event occurred, and it is cleared by writing 1 to USBD_INTSTS[4]
#1
USBIF
USB Event Interrupt Status
The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
1
1
read-write
0
No USB event occurred
#0
1
USB event occurred check EPSTS0~11[3:0] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31])
#1
VBDETIF
VBUS Detection Interrupt Status
2
1
read-write
0
There is not attached/detached event in the USB
#0
1
There is attached/detached event in the USB bus and it is cleared by writing 1 to USBD_INTSTS[2]
#1
LPMATTR
USBD_LPMATTR
USB LPM Attribution Register
0x88
-1
read-only
n
0x0
0x0
LPMBESL
LPM Best Effort Service Latency
These bits contain the BESL value received with last ACK LPM Token
4
4
read-only
LPMLINKSTS
LPM Link State
These bits contain the bLinkState received with last ACK LPM Token
0
4
read-only
LPMRWAKUP
LPM Remote Wake-up
This bit contains the bRemoteWake value received with last ACK LPM Token
8
1
read-only
MXPLD0
USBD_MXPLD0
Endpoint 0 Maximal Payload Register
0x504
-1
read-write
n
0x0
0x0
MXPLD
Maximal Payload
Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
(1) When the register is written by CPU,
For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
(2) When the register is read by CPU,
For IN token, the value of MXPLD is indicated by the data length be transmitted to host
For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
0
9
read-write
MXPLD1
USBD_MXPLD1
Endpoint 1 Maximal Payload Register
0x514
-1
read-write
n
0x0
0x0
MXPLD10
USBD_MXPLD10
Endpoint 10 Maximal Payload Register
0x5A4
-1
read-write
n
0x0
0x0
MXPLD11
USBD_MXPLD11
Endpoint 11 Maximal Payload Register
0x5B4
-1
read-write
n
0x0
0x0
MXPLD12
USBD_MXPLD12
Endpoint 12 Maximal Payload Register
0x5C4
-1
read-write
n
0x0
0x0
MXPLD13
USBD_MXPLD13
Endpoint 13 Maximal Payload Register
0x5D4
-1
read-write
n
0x0
0x0
MXPLD14
USBD_MXPLD14
Endpoint 14 Maximal Payload Register
0x5E4
-1
read-write
n
0x0
0x0
MXPLD15
USBD_MXPLD15
Endpoint 15 Maximal Payload Register
0x5F4
-1
read-write
n
0x0
0x0
MXPLD16
USBD_MXPLD16
Endpoint 16 Maximal Payload Register
0x604
-1
read-write
n
0x0
0x0
MXPLD2
USBD_MXPLD2
Endpoint 2 Maximal Payload Register
0x524
-1
read-write
n
0x0
0x0
MXPLD3
USBD_MXPLD3
Endpoint 3 Maximal Payload Register
0x534
-1
read-write
n
0x0
0x0
MXPLD4
USBD_MXPLD4
Endpoint 4 Maximal Payload Register
0x544
-1
read-write
n
0x0
0x0
MXPLD5
USBD_MXPLD5
Endpoint 5 Maximal Payload Register
0x554
-1
read-write
n
0x0
0x0
MXPLD6
USBD_MXPLD6
Endpoint 6 Maximal Payload Register
0x564
-1
read-write
n
0x0
0x0
MXPLD7
USBD_MXPLD7
Endpoint 7 Maximal Payload Register
0x574
-1
read-write
n
0x0
0x0
MXPLD8
USBD_MXPLD8
Endpoint 8 Maximal Payload Register
0x584
-1
read-write
n
0x0
0x0
MXPLD9
USBD_MXPLD9
Endpoint 9 Maximal Payload Register
0x594
-1
read-write
n
0x0
0x0
SE0
USBD_SE0
USB Device Drive SE0 Control Register
0x90
-1
read-write
n
0x0
0x0
SE0
Drive Single Ended Zero in USB Bus
The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
0
1
read-write
0
Normal operation
#0
1
Force USB PHY transceiver to drive SE0
#1
STBUFSEG
USBD_STBUFSEG
SETUP Token Buffer Segmentation Register
0x18
-1
read-write
n
0x0
0x0
STBUFSEG
SETUP Token Buffer Segmentation
It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address. The effective starting address is
USBD_SRAM address + {STBUFSE.G. 3'b000}
Note: It is used for SETUP token only.
3
6
read-write
VBUSDET
USBD_VBUSDET
USB Device VBUS Detection Register
0x14
-1
read-only
n
0x0
0x0
VBUSDET
Device VBUS Detection
0
1
read-only
0
Controller is not attached to the USB host
#0
1
Controller is attached to the USB host
#1
USPI0
USCISPI Register Map
USCISPI
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x28
0x1C
registers
n
0x54
0x14
registers
n
USPI_BRGEN
USPI_BRGEN
USCI Baud Rate Generator Register
0x8
-1
read-write
n
0x0
0x0
CLKDIV
Clock Divider
16
10
read-write
PTCLKSEL
Protocol Clock Source Selection
This bit selects the source of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection
This bit selects the source of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection
This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fDIV_CLK
#00
1
fPROT_CLK
#01
2
fSCLK
#10
3
fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit
This bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Time measurement counter Disabled
#0
1
Time measurement counter Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
USPI_BUFCTL
USPI_BUFCTL
USCI Transmit/Receive Buffer Control Register
0x38
-1
read-write
n
0x0
0x0
RXCLR
Clear Receive Buffer
Note: It is cleared automatically after one PCLK cycle.
15
1
read-write
0
No effect
#0
1
The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic
#1
RXOVIEN
Receive Buffer Overrun Interrupt Enable Bit
14
1
read-write
0
Receive overrun interrupt Disabled
#0
1
Receive overrun interrupt Enabled
#1
RXRST
Receive Reset
Note: It is cleared automatically after one PCLK cycle.
17
1
read-write
0
No effect
#0
1
Reset the receive-related counters, state machine, and the content of receive shift register and data buffer
#1
TXCLR
Clear Transmit Buffer
Note: It is cleared automatically after one PCLK cycle.
7
1
read-write
0
No effect
#0
1
The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic
#1
TXRST
Transmit Reset
16
1
read-write
0
No effect
#0
1
Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer
#1
TXUDRIEN
Slave Transmit Under-run Interrupt Enable Bit
6
1
read-write
0
Transmit under-run interrupt Disabled
#0
1
Transmit under-run interrupt Enabled
#1
USPI_BUFSTS
USPI_BUFSTS
USCI Transmit/Receive Buffer Status Register
0x3C
-1
read-only
n
0x0
0x0
RXEMPTY
Receive Buffer Empty Indicator
0
1
read-only
0
Receive buffer is not empty
#0
1
Receive buffer is empty
#1
RXFULL
Receive Buffer Full Indicator
1
1
read-only
0
Receive buffer is not full
#0
1
Receive buffer is full
#1
RXOVIF
Receive Buffer Over-run Interrupt Status
This bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit.
3
1
read-only
0
A receive buffer overrun event has not been detected
#0
1
A receive buffer overrun event has been detected
#1
TXEMPTY
Transmit Buffer Empty Indicator
8
1
read-only
0
Transmit buffer is not empty
#0
1
Transmit buffer is empty and available for the next transmission datum
#1
TXFULL
Transmit Buffer Full Indicator
9
1
read-only
0
Transmit buffer is not full
#0
1
Transmit buffer is full
#1
TXUDRIF
Transmit Buffer Under-run Interrupt Status
This bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit
11
1
read-only
0
A transmit buffer under-run event has not been detected
#0
1
A transmit buffer under-run event has been detected
#1
USPI_CLKIN
USPI_CLKIN
USCI Input Clock Signal Configuration Register
0x28
-1
read-write
n
0x0
0x0
SYNCSEL
Input Synchronization Signal Selection
This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.
Note: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_CTL
USPI_CTL
USCI Control Register
0x0
-1
read-write
n
0x0
0x0
FUNMODE
Function Mode
This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
Note: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
USPI_CTLIN0
USPI_CTLIN0
USCI Input Control Signal Configuration Register 0
0x20
-1
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection
This bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Synchronization Signal Selection
This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.
Note: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_DATIN0
USPI_DATIN0
USCI Input Data Signal Configuration Register 0
0x10
-1
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection
This bit defines the inverter enable of the input asynchronous signal.
Note: In SPI protocol, it is suggested this bit should be set as 0.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Signal Synchronization Selection
This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.
Note: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_INTEN
USPI_INTEN
USCI Interrupt Enable Register
0x4
-1
read-write
n
0x0
0x0
RXENDIEN
Receive End Interrupt Enable Bit
This bit enables the interrupt generation in case of a receive finish event.
Note: The receive finish event happens when hardware receives the last bit of RX data into shift data unit.
4
1
read-write
0
The receive end interrupt Disabled
#0
1
The receive end interrupt Enabled
#1
RXSTIEN
Receive Start Interrupt Enable Bit
This bit enables the interrupt generation in case of a receive start event.
Note: For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
3
1
read-write
0
The receive start interrupt Disabled
#0
1
The receive start interrupt Enabled
#1
TXENDIEN
Transmit End Interrupt Enable Bit
This bit enables the interrupt generation in case of a transmit finish event.
Note: The transmit finish event happens when hardware sends the last bit of TX data from shift data unit.
2
1
read-write
0
The transmit finish interrupt Disabled
#0
1
The transmit finish interrupt Enabled
#1
TXSTIEN
Transmit Start Interrupt Enable Bit
This bit enables the interrupt generation in case of a transmit start event.
Note: The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
1
1
read-write
0
The transmit start interrupt Disabled
#0
1
The transmit start interrupt Enabled
#1
USPI_LINECTL
USPI_LINECTL
USCI Line Control Register
0x2C
-1
read-write
n
0x0
0x0
CTLOINV
Control Signal Output Inverse Selection
This bit defines the relation between the internal control signal and the output control signal.
Note: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal.
7
1
read-write
0
No effect
#0
1
The control signal will be inverted before its output
#1
DATOINV
Data Output Inverse Selection
This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.
5
1
read-write
0
Data output values of USCIx_DAT0/1 pins are not inverted
#0
1
Data output values of USCIx_DAT0/1 pins are inverted
#1
DWIDTH
Word Length of Transmission
This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.
0x0: The data word contains 16 bits located at bit positions [15:0].
0x1: Reserved.
0x2: Reserved.
0x3: Reserved.
0x4: The data word contains 4 bits located at bit positions [3:0].
0x5: The data word contains 5 bits located at bit positions [4:0].
...
0xF: The data word contains 15 bits located at bit positions [14:0].
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
USPI_PDMACTL
USPI_PDMACTL
USCI PDMA Control Register
0x40
-1
read-write
n
0x0
0x0
PDMAEN
PDMA Mode Enable Bit
3
1
read-write
0
PDMA function Disabled
#0
1
PDMA function Enabled
#1
PDMARST
PDMA Reset
0
1
read-write
0
No effect
#0
1
Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically
#1
RXPDMAEN
PDMA Receive Channel Available
2
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
1
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
USPI_PROTCTL
USPI_PROTCTL
USCI Protocol Control Register
0x5C
-1
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)
3
1
read-write
0
Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit
#0
1
Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
PROTEN
SPI Protocol Enable Bit
31
1
read-write
0
SPI Protocol Disabled
#0
1
SPI Protocol Enabled
#1
SCLKMODE
Serial Bus Clock Mode
This bit field defines the SCLK idle status, data transmit, and data receive edge.
6
2
read-write
0
MODE0. The idle state of SPI clock is low level. Data is transmitted with falling edge and received with rising edge
#00
1
MODE1. The idle state of SPI clock is low level. Data is transmitted with rising edge and received with falling edge
#01
2
MODE2. The idle state of SPI clock is high level. Data is transmitted with rising edge and received with falling edge
#10
3
MODE3. The idle state of SPI clock is high level. Data is transmitted with falling edge and received with rising edge
#11
SLAVE
Slave Mode Selection
0
1
read-write
0
Master mode
#0
1
Slave mode
#1
SLV3WIRE
Slave 3-wire Mode Selection (Slave Only)
The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
1
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLVTOCNT
Slave Mode Time-out Period (Slave Only)
In Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function.
Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
16
10
read-write
SS
Slave Select Control (Master Only)
If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.
Note: In SPI protocol, the internal slave select signal is active high.
2
1
read-write
SUSPITV
Suspend Interval (Master Only)
This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.
(SUSPITV + 0.5) * period of SPI_CLK clock cycle
Example:
8
4
read-write
TSMSEL
Transmit Data Mode Selection
This bit field describes how receive and transmit data is shifted in and out.
Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
12
3
read-write
0
TSMSEL: Full-duplex SPI
#000
4
TSMSEL: Half-duplex SPI
#100
TXUDRPOL
Transmit Under-run Data Polarity (for Slave)
This bit defines the transmitting data level of USCIx_DAT1 when no data is available for transferring.
28
1
read-write
0
The output data level is 0 if TX under run event occurs
#0
1
The output data level is 1 if TX under run event occurs
#1
USPI_PROTIEN
USPI_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
-1
read-write
n
0x0
0x0
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit
If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]). Bit count error event occurs.
3
1
read-write
0
The Slave mode bit count error interrupt Disabled
#0
1
The Slave mode bit count error interrupt Enabled
#1
SLVTOIEN
Slave Time-out Interrupt Enable Bit
In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
2
1
read-write
0
The Slave time-out interrupt Disabled
#0
1
The Slave time-out interrupt Enabled
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit
This bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
1
1
read-write
0
Slave select active interrupt generation Disabled
#0
1
Slave select active interrupt generation Enabled
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit
This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
0
1
read-write
0
Slave select inactive interrupt generation Disabled
#0
1
Slave select inactive interrupt generation Enabled
#1
USPI_PROTSTS
USPI_PROTSTS
USCI Protocol Status Register
0x64
-1
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
17
1
read-only
0
SPI is in idle state
#0
1
SPI is in busy state
#1
RXENDIF
Receive End Interrupt Flag
Note: It is cleared by software write 1 to this bit. The receive end event happens when hardware receives the last bit of RX data into shift data unit.
4
1
read-write
0
Receive end event did not occur
#0
1
Receive end event occurred
#1
RXSTIF
Receive Start Interrupt Flag
Note: It is cleared by software write 1 to this bit. For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
3
1
read-write
0
Receive start event did not occur
#0
1
Receive start event occurred
#1
SLVBEIF
Slave Bit Count Error Interrupt Flag (for Slave Only)
Note1: It is cleared by software write 1 to this bit. If the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]), bit count error event occurs.
Note2: SLVBEIF fix to 0 when slave 3-wire mode enable.
6
1
read-write
0
Slave bit count error event did not occur
#0
1
Slave bit count error event occurred
#1
SLVTOIF
Slave Time-out Interrupt Flag (for Slave Only)
Note: It is cleared by software write 1 to this bit
5
1
read-write
0
Slave time-out event did not occur
#0
1
Slave time-out event occurred
#1
SLVUDR
Slave Mode Transmit Under-run Status (Read Only)
In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
18
1
read-only
0
Slave transmit under-run event does not occur
#0
1
Slave transmit under-run event occurs
#1
SSACTIF
Slave Select Active Interrupt Flag (for Slave Only)
This bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit.
Note1: The internal slave select signal is active high.
Note2: SSACTIF fix to 0 when slave 3-wire mode enable.
9
1
read-write
0
The slave select signal has not changed to active
#0
1
The slave select signal has changed to active
#1
SSINAIF
Slave Select Inactive Interrupt Flag (for Slave Only)
This bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit
Note1: The internal slave select signal is active high.
Note2: SSINAIF fix to 0 when slave 3-wire mode enable.
8
1
read-write
0
The slave select signal has not changed to inactive
#0
1
The slave select signal has changed to inactive
#1
SSLINE
Slave Select Line Bus Status (Read Only)
This bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus.
16
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXENDIF
Transmit End Interrupt Flag
Note: It is cleared by software write 1 to this bit. The transmit end event happens when hardware sends the last bit of TX data from shift data unit.
2
1
read-write
0
Transmit end event did not occur
#0
1
Transmit end event occurred
#1
TXSTIF
Transmit Start Interrupt Flag
Note: It is cleared by software write 1 to this bit. The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
1
1
read-write
0
Transmit start event did not occur
#0
1
Transmit start event occurred
#1
USPI_RXDAT
USPI_RXDAT
USCI Receive Data Register
0x34
-1
read-only
n
0x0
0x0
RXDAT
Received Data
This bit field monitors the received data which stored in receive data buffer.
0
16
read-only
USPI_TXDAT
USPI_TXDAT
USCI Transmit Data Register
0x30
-1
write-only
n
0x0
0x0
PORTDIR
Port Direction Control
16
1
write-only
0
The data pin is configured as output mode
#0
1
The data pin is configured as input mode
#1
TXDAT
Transmit Data
Software can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
0
16
write-only
USPI_WKCTL
USPI_WKCTL
USCI Wake-up Control Register
0x54
-1
read-write
n
0x0
0x0
PDBOPT
Power Down Blocking Option
2
1
read-write
0
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately
#0
1
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
USPI_WKSTS
USPI_WKSTS
USCI Wake-up Status Register
0x58
-1
read-write
n
0x0
0x0
WKF
Wake-up Flag
When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
Note: The wake-up flag also is set to 1 when PDBOPT (USCI_WKCTL[2]) is enabled.
0
1
read-write
UUART0
USCIUART Register Map
USCIUART
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x28
0x1C
registers
n
0x54
0x14
registers
n
UUART_BRGEN
UUART_BRGEN
USCI Baud Rate Generator Register
0x8
-1
read-write
n
0x0
0x0
CLKDIV
Clock Divider
Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate.
16
10
read-write
DSCNT
Denominator for Sample Counter
This bit field defines the divide ratio of the sample clock fSAMP_CLK.
Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection
This bit selects the source signal of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection
This bit selects the source signal of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection
This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fSAMP_CLK is selected to fDIV_CLK
#00
1
fSAMP_CLK is selected to fPROT_CLK
#01
2
fSAMP_CLK is selected to fSCLK
#10
3
fSAMP_CLK is selected to fREF_CLK
#11
TMCNTEN
Timing Measurement Counter Enable Bit
This bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Timing measurement counter is Disabled
#0
1
Timing measurement counter is Enabled
#1
TMCNTSRC
Timing Measurement Counter Clock Source Selection
5
1
read-write
0
Timing measurement counter with fPROT_CLK
#0
1
Timing measurement counter with fDIV_CLK
#1
UUART_BUFCTL
UUART_BUFCTL
USCI Transmit/Receive Buffer Control Register
0x38
-1
read-write
n
0x0
0x0
RXCLR
Clear Receive Buffer
Note: It is cleared automatically after one PCLK cycle.
15
1
read-write
0
No effect
#0
1
The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic
#1
RXOVIEN
Receive Buffer Overrun Error Interrupt Enable Bit
14
1
read-write
0
Receive overrun interrupt Disabled
#0
1
Receive overrun interrupt Enabled
#1
RXRST
Receive Reset
Note 1: It is cleared automatically after one PCLK cycle.
Note 2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1.
17
1
read-write
0
No effect
#0
1
Reset the receive-related counters, state machine, and the content of receive shift register and data buffer
#1
TXCLR
Clear Transmit Buffer
Note: It is cleared automatically after one PCLK cycle.
7
1
read-write
0
No effect
#0
1
The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic
#1
TXRST
Transmit Reset
Note: It is cleared automatically after one PCLK cycle.
16
1
read-write
0
No effect
#0
1
Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer
#1
UUART_BUFSTS
UUART_BUFSTS
USCI Transmit/Receive Buffer Status Register
0x3C
-1
read-write
n
0x0
0x0
RXEMPTY
Receive Buffer Empty Indicator (Read Only)
0
1
read-only
0
Receive buffer is not empty
#0
1
Receive buffer is empty
#1
RXFULL
Receive Buffer Full Indicator (Read Only)
1
1
read-only
0
Receive buffer is not full
#0
1
Receive buffer is full
#1
RXOVIF
Receive Buffer Over-run Error Interrupt Status
This bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated.
Note: It is cleared by software writing 1 into this bit.
3
1
read-write
0
A receive buffer overrun error event has not been detected
#0
1
A receive buffer overrun error event has been detected
#1
TXEMPTY
Transmit Buffer Empty Indicator (Read Only)
8
1
read-only
0
Transmit buffer is not empty
#0
1
Transmit buffer is empty
#1
TXFULL
Transmit Buffer Full Indicator (Read Only)
9
1
read-only
0
Transmit buffer is not full
#0
1
Transmit buffer is full
#1
UUART_CLKIN
UUART_CLKIN
USCI Input Clock Signal Configuration Register
0x28
-1
read-write
n
0x0
0x0
SYNCSEL
Input Synchronization Signal Selection
This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_CTL
UUART_CTL
USCI Control Register
0x0
-1
read-write
n
0x0
0x0
FUNMODE
Function Mode
This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
UUART_CTLIN0
UUART_CTLIN0
USCI Input Control Signal Configuration Register 0
0x20
-1
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection
This bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Synchronization Signal Selection
This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_DATIN0
UUART_DATIN0
USCI Input Data Signal Configuration Register 0
0x10
-1
read-write
n
0x0
0x0
EDGEDET
Input Signal Edge Detection Mode
This bit field selects which edge actives the trigger event of input data signal.
Note: In UART function mode, it is suggested to set this bit field as 0x2.
3
2
read-write
0
The trigger event activation is disabled
#00
1
A rising edge activates the trigger event of input data signal
#01
2
A falling edge activates the trigger event of input data signal
#10
3
Both edges activate the trigger event of input data signal
#11
ININV
Input Signal Inverse Selection
This bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Signal Synchronization Selection
This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_INTEN
UUART_INTEN
USCI Interrupt Enable Register
0x4
-1
read-write
n
0x0
0x0
RXENDIEN
Receive End Interrupt Enable Bit
This bit enables the interrupt generation in case of a receive finish event.
4
1
read-write
0
The receive end interrupt Disabled
#0
1
The receive end interrupt Enabled
#1
RXSTIEN
Receive Start Interrupt Enable Bit
This bit enables the interrupt generation in case of a receive start event.
3
1
read-write
0
The receive start interrupt Disabled
#0
1
The receive start interrupt Enabled
#1
TXENDIEN
Transmit End Interrupt Enable Bit
This bit enables the interrupt generation in case of a transmit finish event.
2
1
read-write
0
The transmit finish interrupt Disabled
#0
1
The transmit finish interrupt Enabled
#1
TXSTIEN
Transmit Start Interrupt Enable Bit
This bit enables the interrupt generation in case of a transmit start event.
1
1
read-write
0
The transmit start interrupt Disabled
#0
1
The transmit start interrupt Enabled
#1
UUART_LINECTL
UUART_LINECTL
USCI Line Control Register
0x2C
-1
read-write
n
0x0
0x0
CTLOINV
Control Signal Output Inverse Selection
This bit defines the relation between the internal control signal and the output control signal.
Note: In UART protocol, the control signal means nRTS signal.
7
1
read-write
0
No effect
#0
1
The control signal will be inverted before its output
#1
DATOINV
Data Output Inverse Selection
This bit defines the relation between the internal shift data value and the output data signal of USCI0_DAT1 pin.
5
1
read-write
0
The value of USCI0_DAT1 is equal to the data shift register
#0
1
The value of USCI0_DAT1 is the inversion of data shift register
#1
DWIDTH
Word Length of Transmission
This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.
Note: In UART protocol, the length can be configured as 6~13 bits.
8
4
read-write
0
The data word contains 16 bits located at bit positions [15:0]
#0000
1
Reserved.
#0001
2
Reserved.
#0010
3
Reserved.
#0011
4
The data word contains 4 bits located at bit positions [3:0]
#0100
5
The data word contains 5 bits located at bit positions [4:0]
#0101
6
The data word contains 6 bits located at bit positions [5:0]
#0110
7
The data word contains 7 bits located at bit positions [6:0]
#0111
8
The data word contains 8 bits located at bit positions [7:0]
#1000
9
The data word contains 9 bits located at bit positions [8:0]
#1001
10
The data word contains 10 bits located at bit positions [9:0]
#1010
11
The data word contains 11 bits located at bit positions [10:0]
#1011
12
The data word contains 12 bits located at bit positions [11:0]
#1100
13
The data word contains 13 bits located at bit positions [12:0]
#1101
14
The data word contains 14 bits located at bit positions [13:0]
#1110
15
The data word contains 15 bits located at bit positions [14:0]
#1111
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
UUART_PDMACTL
UUART_PDMACTL
USCI PDMA Control Register
0x40
-1
read-write
n
0x0
0x0
PDMAEN
PDMA Mode Enable Bit
3
1
read-write
0
PDMA function Disabled
#0
1
PDMA function Enabled
#1
PDMARST
PDMA Reset
0
1
read-write
0
No effect
#0
1
Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically
#1
RXPDMAEN
PDMA Receive Channel Available
2
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
1
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
UUART_PROTCTL
UUART_PROTCTL
USCI Protocol Control Register
0x5C
-1
read-write
n
0x0
0x0
ABREN
Auto-baud Rate Detect Enable Bit
Note: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTSTS[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).
6
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
BCEN
Transmit Break Control Enable Bit
Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the receiver logic.
29
1
read-write
0
Transmit Break Control Disabled
#0
1
Transmit Break Control Enabled
#1
BRDETITV
Baud Rate Detection Interval
This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.
Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV.
16
9
read-write
CTSAUTOEN
nCTS Auto-flow Control Enable Bit
When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).
4
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
CTSWKEN
nCTS Wake-up Mode Enable Bit
10
1
read-write
0
nCTS wake-up mode Disabled
#0
1
nCTS wake-up mode Enabled
#1
DATWKEN
Data Wake-up Mode Enable Bit
9
1
read-write
0
Data wake-up mode Disabled
#0
1
Data wake-up mode Enabled
#1
DGE
Deglitch Enable Bit
Note 1: When this bit is set to logic 1, any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic.
Note 2: It is recommended to set this bit only when operating at baud rate under 2.5 Mbps.
30
1
read-write
0
Deglitch Disabled
#0
1
Deglitch Enabled
#1
EVENPARITY
Even Parity Enable Bit
Note: This bit has effect only when PARITYEN is set.
2
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
PARITYEN
Parity Enable Bit
This bit defines the parity bit is enabled in an UART frame.
1
1
read-write
0
The parity bit Disabled
#0
1
The parity bit Enabled
#1
PROTEN
UART Protocol Enable Bit
31
1
read-write
0
UART Protocol Disabled
#0
1
UART Protocol Enabled
#1
RTSAUDIREN
nRTS Auto Direction Enable Bit
When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the nRTS signal is inactive automatically.
Note 1: This bit is used for nRTS auto direction control for RS485.
Note 2: This bit has effect only when the RTSAUTOEN is not set.
5
1
read-write
0
nRTS auto direction control Disabled
#0
1
nRTS auto direction control Enabled
#1
RTSAUTOEN
nRTS Auto-flow Control Enable Bit
Note: This bit has effect only when the RTSAUDIREN is not set.
3
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
STICKEN
Stick Parity Enable Bit
Note: Refer to RS-485 Support section for detailed information.
26
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
STOPB
Stop Bits
This bit defines the number of stop bits in an UART frame.
0
1
read-write
0
The number of stop bits is 1
#0
1
The number of stop bits is 2
#1
WAKECNT
Wake-up Counter
These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is woken up from Power-down mode.
11
4
read-write
UUART_PROTIEN
UUART_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
-1
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
1
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
2
1
read-write
0
Receive line status interrupt Disabled
#0
1
Receive line status interrupt Enabled
#1
UUART_PROTSTS
UUART_PROTSTS
USCI Protocol Status Register
0x64
-1
read-write
n
0x0
0x0
ABERRSTS
Auto-baud Rate Error Status
This bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.
Note 1: This bit is set at the same time of ABRDETIF.
Note 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS.
11
1
read-write
0
Auto-baud rate detect counter is not overrun
#0
1
Auto-baud rate detect counter is overrun
#1
ABRDETIF
Auto-baud Rate Interrupt Flag
This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.
Note: This bit can be cleared by writing '1' to it.
9
1
read-write
0
Auto-baud rate detect function is not done
#0
1
One Bit auto-baud rate detect function is done
#1
BREAK
Break Flag
This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).
Note: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
7
1
read-write
0
No Break is generated
#0
1
Break is generated in the receiver bus
#1
CTSLV
nCTS Pin Status (Read Only)
This bit used to monitor the current status of nCTS pin input.
17
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
CTSSYNCLV
nCTS Synchronized Level Status (Read Only)
This bit used to indicate the current status of the internal synchronized nCTS signal.
16
1
read-only
0
The internal synchronized nCTS is low
#0
1
The internal synchronized nCTS is high
#1
FRMERR
Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
Note: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
6
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PARITYERR
Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.
Note: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
5
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXBUSY
RX Bus Status Flag (Read Only)
This bit indicates the busy status of the receiver.
10
1
read-only
0
The receiver is Idle
#0
1
The receiver is BUSY
#1
RXENDIF
Receive End Interrupt Flag
Note: It is cleared by software writing 1 into this bit.
4
1
read-write
0
A receive finish interrupt status has not occurred
#0
1
A receive finish interrupt status has occurred
#1
RXSTIF
Receive Start Interrupt Flag
Note: It is cleared by software writing 1 into this bit.
3
1
read-write
0
A receive start interrupt status has not occurred
#0
1
A receive start interrupt status has occurred
#1
TXENDIF
Transmit End Interrupt Flag
Note: It is cleared by software writing 1 into this bit.
2
1
read-write
0
A transmit end interrupt status has not occurred
#0
1
A transmit end interrupt status has occurred
#1
TXSTIF
Transmit Start Interrupt Flag
Note 1: It is cleared by software writing one into this bit.
Note 2: Used for user to load next transmit data when there is no data in transmit buffer.
1
1
read-write
0
A transmit start interrupt status has not occurred
#0
1
A transmit start interrupt status has occurred
#1
UUART_RXDAT
UUART_RXDAT
USCI Receive Data Register
0x34
-1
read-only
n
0x0
0x0
RXDAT
Received Data
This bit field monitors the received data which stored in receive data buffer.
Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]).
0
16
read-only
UUART_TXDAT
UUART_TXDAT
USCI Transmit Data Register
0x30
-1
write-only
n
0x0
0x0
TXDAT
Transmit Data
Software can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
UUART_WKCTL
UUART_WKCTL
USCI Wake-up Control Register
0x54
-1
read-write
n
0x0
0x0
PDBOPT
Power Down Blocking Option
2
1
read-write
0
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately
#0
1
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
UUART_WKSTS
UUART_WKSTS
USCI Wake-up Status Register
0x58
-1
read-write
n
0x0
0x0
WKF
Wake-up Flag
When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WDT
WDT Register Map
WDT
0x0
0x0
0xC
registers
n
ALTCTL
WDT_ALTCTL
WDT Alternative Control Register
0x4
-1
read-write
n
0x0
0x0
RSTDSEL
WDT Reset Delay Selection (Write Protect)
When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT (WDT_RSTCNT[31:0]) to prevent WDT time-out reset happened.
User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: This register will be reset to 0 if WDT time-out reset happened.
0
2
read-write
0
WDT Reset Delay Period is 1026 * WDT_CLK
#00
1
WDT Reset Delay Period is 130 * WDT_CLK
#01
2
WDT Reset Delay Period is 18 * WDT_CLK
#10
3
WDT Reset Delay Period is 3 * WDT_CLK
#11
CTL
WDT_CTL
WDT Control Register
0x0
-1
read-write
n
0x0
0x0
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
WDT up counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement affects WDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
IF
WDT Time-out Interrupt Flag
This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
Note: This bit is cleared by writing 1 to it.
3
1
read-write
0
WDT time-out interrupt did not occur
#0
1
WDT time-out interrupt occurred
#1
INTEN
WDT Time-out Interrupt Enable Bit (Write Protect)
If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
WDT time-out interrupt Disabled
#0
1
WDT time-out interrupt Enabled
#1
RSTEN
WDT Time-out Reset Enable Bit (Write Protect)
Setting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
WDT time-out reset function Disabled
#0
1
WDT time-out reset function Enabled
#1
RSTF
WDT Time-out Reset Flag
This bit indicates the system has been reset by WDT time-out reset or not.
Note: This bit is cleared by writing 1 to it.
2
1
read-write
0
WDT time-out reset did not occur
#0
1
WDT time-out reset occurred
#1
SYNC
WDT Enable Control SYNC Flag Indicator (Read Only)
If user executes enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.
Note: Performing enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
30
1
read-only
0
Set WDTEN bit is completed
#0
1
Set WDTEN bit is synchronizing and not become active yet
#1
TOUTSEL
WDT Time-out Interval Selection (Write Protect)
These four bits select the time-out interval period for the WDT.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
8
4
read-write
0
24 * WDT_CLK
#0000
1
26 * WDT_CLK
#0001
2
28 * WDT_CLK
#0010
3
210 * WDT_CLK
#0011
4
212 * WDT_CLK
#0100
5
214 * WDT_CLK
#0101
6
216 * WDT_CLK
#0110
7
218 * WDT_CLK
#0111
8
220 * WDT_CLK
#1000
WDTEN
WDT Enable Bit (Write Protect)
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111, this bit is forced as 1 and user cannot change this bit to 0.
7
1
read-write
0
WDT Disabled (This action will reset the internal up counter value)
#0
1
WDT Enabled
#1
WKEN
WDT Time-out Wake-up Function Control (Write Protect)
If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: Chip can be woken up by WDT time-out interrupt signal generated only if WDT clock source is selected to 38.4 kHz internal low speed RC oscillator (LIRC) or LXT.
4
1
read-write
0
Wake-up trigger event Disabled if WDT time-out interrupt signal generated
#0
1
Wake-up trigger event Enabled if WDT time-out interrupt signal generated
#1
WKF
WDT Time-out Wake-up Flag (Write Protect)
This bit indicates the interrupt wake-up flag status of WDT
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: This bit is cleared by writing 1 to it.
5
1
read-write
0
WDT does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated
#1
RSTCNT
WDT_RSTCNT
WDT Reset Counter Register
0x8
-1
write-only
n
0x0
0x0
RSTCNT
WDT Reset Counter Register
Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.
Note1: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
0
32
write-only
WWDT
WWDT Register Map
WWDT
0x0
0x0
0x10
registers
n
CNT
WWDT_CNT
WWDT Counter Value Register
0xC
-1
read-only
n
0x0
0x0
CNTDAT
WWDT Counter Value
CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
0
6
read-only
CTL
WWDT_CTL
WWDT Control Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
WWDT Window Compare Register
Set this register to adjust the valid reload window.
Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
16
6
read-write
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit
Note: WWDT down counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects WWDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
WWDT Interrupt Enable Bit
If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
1
1
read-write
0
WWDT counter compare match interrupt Disabled
#0
1
WWDT counter compare match interrupt Enabled
#1
PSCSEL
WWDT Counter Prescale Period Selection
8
4
read-write
0
Pre-scale is 1 Max time-out period is 1 * 64 * WWDT_CLK
#0000
1
Pre-scale is 2 Max time-out period is 2 * 64 * WWDT_CLK
#0001
2
Pre-scale is 4 Max time-out period is 4 * 64 * WWDT_CLK
#0010
3
Pre-scale is 8 Max time-out period is 8 * 64 * WWDT_CLK
#0011
4
Pre-scale is 16 Max time-out period is 16 * 64 * WWDT_CLK
#0100
5
Pre-scale is 32 Max time-out period is 32 * 64 * WWDT_CLK
#0101
6
Pre-scale is 64 Max time-out period is 64 * 64 * WWDT_CLK
#0110
7
Pre-scale is 128 Max time-out period is 128 * 64 * WWDT_CLK
#0111
8
Pre-scale is 192 Max time-out period is 192 * 64 * WWDT_CLK
#1000
9
Pre-scale is 256 Max time-out period is 256 * 64 * WWDT_CLK
#1001
10
Pre-scale is 384 Max time-out period is 384 * 64 * WWDT_CLK
#1010
11
Pre-scale is 512 Max time-out period is 512 * 64 * WWDT_CLK
#1011
12
Pre-scale is 768 Max time-out period is 768 * 64 * WWDT_CLK
#1100
13
Pre-scale is 1024 Max time-out period is 1024 * 64 * WWDT_CLK
#1101
14
Pre-scale is 1536 Max time-out period is 1536 * 64 * WWDT_CLK
#1110
15
Pre-scale is 2048 Max time-out period is 2048 * 64 * WWDT_CLK
#1111
WWDTEN
WWDT Enable Bit
0
1
read-write
0
WWDT counter is stopped
#0
1
WWDT counter starts counting
#1
RLDCNT
WWDT_RLDCNT
WWDT Reload Counter Register
0x0
-1
write-only
n
0x0
0x0
RLDCNT
WWDT Reload Counter Register
Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]). If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated immediately.
0
32
write-only
STATUS
WWDT_STATUS
WWDT Status Register
0x8
-1
read-write
n
0x0
0x0
WWDTIF
WWDT Compare Match Interrupt Flag
This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
WWDT counter value matches CMPDAT
#1
WWDTRF
WWDT Timer-out Reset Flag
This bit indicates the system has been reset by WWDT time-out reset or not.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
WWDT time-out reset did not occur
#0
1
WWDT time-out reset occurred
#1