nuvoTon M261_v1 2024.04.29 M261_v1 SVD file 8 32 ACMP01 ACMP Register Map ACMP 0x0 0x0 0x10 registers n ACMP_CTL0 ACMP_CTL0 Analog Comparator 0 Control Register 0x0 read-write n 0x0 0x0 ACMPEN Comparator Enable Bit 0 1 read-write 0 Comparator 0 Disabled #0 1 Comparator 0 Enabled #1 ACMPIE Comparator Interrupt Enable Bit 1 1 read-write 0 Comparator 0 interrupt Disabled #0 1 Comparator 0 interrupt Enabled. If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well #1 ACMPOINV Comparator Output Inverse 3 1 read-write 0 Comparator 0 output inverse Disabled #0 1 Comparator 0 output inverse Enabled #1 FILTSEL Comparator Output Filter Count Selection 13 3 read-write 0 Filter function is Disabled #000 1 ACMP0 output is sampled 1 consecutive PCLK #001 2 ACMP0 output is sampled 2 consecutive PCLKs #010 3 ACMP0 output is sampled 4 consecutive PCLKs #011 4 ACMP0 output is sampled 8 consecutive PCLKs #100 5 ACMP0 output is sampled 16 consecutive PCLKs #101 6 ACMP0 output is sampled 32 consecutive PCLKs #110 7 ACMP0 output is sampled 64 consecutive PCLKs #111 HYSSEL Hysteresis Mode Selection 24 2 read-write 0 Hysteresis is 0mV #00 1 Hysteresis is 10mV #01 2 Hysteresis is 20mV #10 3 Hysteresis is 30mV #11 INTPOL Interrupt Condition Polarity Selection\nACMPIF0 will be set to 1 when comparator output edge condition is detected. 8 2 read-write 0 Rising edge or falling edge #00 1 Rising edge #01 2 Falling edge #10 3 Reserved #11 MODESEL Propagation Delay Mode Selection 28 2 read-write 0 Max propagation delay is 4.5uS, operation current is 1.2uA #00 1 Max propagation delay is 2uS, operation current is 3uA #01 2 Max propagation delay is 600nS, operation current is 10uA #10 3 Max propagation delay is 200nS, operation current is 75uA #11 NEGSEL Comparator Negative Input Selection 4 2 read-write 0 ACMP0_N pin #00 1 Internal comparator reference voltage (CRV) #01 2 Band-gap voltage #10 3 DAC output #11 OUTSEL Comparator Output Select 12 1 read-write 0 Comparator 0 output to ACMP0_O pin is unfiltered comparator output #0 1 Comparator 0 output to ACMP0_O pin is from filter output #1 POSSEL Comparator Positive Input Selection 6 2 read-write 0 Input from ACMP0_P0 #00 1 Input from ACMP0_P1 #01 2 Input from ACMP0_P2 #10 3 Input from ACMP0_P3 #11 WCMPSEL Window Compare Mode Selection 18 1 read-write 0 Window Compare Mode Disabled #0 1 Window Compare Mode is Selected #1 WKEN Power-down Wake-up Enable Bit 16 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 WLATEN Window Latch Mode Enable Bit 17 1 read-write 0 Window Latch Mode Disabled #0 1 Window Latch Mode Enabled #1 ACMP_CTL1 ACMP_CTL1 Analog Comparator 1 Control Register 0x4 read-write n 0x0 0x0 ACMPEN Comparator Enable Bit 0 1 read-write 0 Comparator 1 Disabled #0 1 Comparator 1 Enabled #1 ACMPIE Comparator Interrupt Enable Bit 1 1 read-write 0 Comparator 1 interrupt Disabled #0 1 Comparator 1 interrupt Enabled. If WKEN (ACMP_CTL1[16]) is set to 1, the wake-up interrupt function will be enabled as well #1 ACMPOINV Comparator Output Inverse Control 3 1 read-write 0 Comparator 1 output inverse Disabled #0 1 Comparator 1 output inverse Enabled #1 FILTSEL Comparator Output Filter Count Selection 13 3 read-write 0 Filter function is Disabled #000 1 ACMP1 output is sampled 1 consecutive PCLK #001 2 ACMP1 output is sampled 2 consecutive PCLKs #010 3 ACMP1 output is sampled 4 consecutive PCLKs #011 4 ACMP1 output is sampled 8 consecutive PCLKs #100 5 ACMP1 output is sampled 16 consecutive PCLKs #101 6 ACMP1 output is sampled 32 consecutive PCLKs #110 7 ACMP1 output is sampled 64 consecutive PCLKs #111 HYSSEL Hysteresis Mode Selection 24 2 read-write 0 Hysteresis is 0mV #00 1 Hysteresis is 10mV #01 2 Hysteresis is 20mV #10 3 Hysteresis is 30mV #11 INTPOL Interrupt Condition Polarity Selection\nACMPIF1 will be set to 1 when comparator output edge condition is detected. 8 2 read-write 0 Rising edge or falling edge #00 1 Rising edge #01 2 Falling edge #10 3 Reserved #11 MODESEL Propagation Delay Mode Selection 28 2 read-write 0 Max propagation delay is 4.5uS, operation current is 1.2uA #00 1 Max propagation delay is 2uS, operation current is 3uA #01 2 Max propagation delay is 600nS, operation current is 10uA #10 3 Max propagation delay is 200nS, operation current is 75uA #11 NEGSEL Comparator Negative Input Selection 4 2 read-write 0 ACMP1_N pin #00 1 Internal comparator reference voltage (CRV) #01 2 Band-gap voltage #10 3 DAC output #11 OUTSEL Comparator Output Select 12 1 read-write 0 Comparator 1 output to ACMP1_O pin is unfiltered comparator output #0 1 Comparator 1 output to ACMP1_O pin is from filter output #1 POSSEL Comparator Positive Input Selection 6 2 read-write 0 Input from ACMP1_P0 #00 1 Input from ACMP1_P1 #01 2 Input from ACMP1_P2 #10 3 Input from ACMP1_P3 #11 WCMPSEL Window Compare Mode Selection 18 1 read-write 0 Window Compare Mode Disabled #0 1 Window Compare Mode is Selected #1 WKEN Power-down Wakeup Enable Bit 16 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 WLATEN Window Latch Mode Enable Bit 17 1 read-write 0 Window Latch Mode Disabled #0 1 Window Latch Mode Enabled #1 ACMP_STATUS ACMP_STATUS Analog Comparator Status Register 0x8 read-write n 0x0 0x0 ACMPIF0 Comparator 0 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.\nNote: Write 1 to clear this bit to 0. 0 1 read-write ACMPIF1 Comparator 1 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output. This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.\nNote: Write 1 to clear this bit to 0. 1 1 read-write ACMPO0 Comparator 0 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0. 4 1 read-write ACMPO1 Comparator 1 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0. 5 1 read-write ACMPS0 Comparator 0 Status \nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0. 12 1 read-write ACMPS1 Comparator 1 Status\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0. 13 1 read-write ACMPWO Comparator Window Output\nThis bit shows the output status of window compare mode 16 1 read-write 0 The positive input voltage is outside the window #0 1 The positive input voltage is in the window #1 WKIF0 Comparator 0 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP0 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0. 8 1 read-write 0 No power-down wake-up occurred #0 1 Power-down wake-up occurred #1 WKIF1 Comparator 1 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP1 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0. 9 1 read-write 0 No power-down wake-up occurred #0 1 Power-down wake-up occurred #1 ACMP_VREF ACMP_VREF Analog Comparator Reference Voltage Control Register 0xC read-write n 0x0 0x0 CRVCTL Comparator Reference Voltage Setting 0 4 read-write CRVSSEL CRV Source Voltage Selection 6 1 read-write 0 AVDD is selected as CRV source voltage #0 1 The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage #1 BPWM0 BPWM Register Map BPWM 0x0 0x0 0x8 registers n 0x10 0x8 registers n 0x110 0x8 registers n 0x120 0x4 registers n 0x20 0x8 registers n 0x200 0x3C registers n 0x250 0x8 registers n 0x30 0x4 registers n 0x304 0x4 registers n 0x31C 0x18 registers n 0x50 0x18 registers n 0x90 0x4 registers n 0xB0 0x10 registers n 0xD4 0x8 registers n 0xE0 0x4 registers n 0xE8 0x4 registers n 0xF8 0x8 registers n BPWM_CAPCTL BPWM_CAPCTL BPWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPEN0 Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n. 0 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN1 Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n. 1 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN2 Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n. 2 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN3 Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n. 3 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN4 Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n. 4 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN5 Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n. 5 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPINV0 Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n. 8 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV1 Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n. 9 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV2 Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n. 10 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV3 Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n. 11 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV4 Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n. 12 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV5 Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n. 13 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 FCRLDEN0 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 24 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN1 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 25 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN2 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 26 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN3 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 27 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN4 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 28 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN5 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 29 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 RCRLDEN0 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 16 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN1 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 17 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN2 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 18 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN3 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 19 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN4 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 20 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN5 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 21 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 BPWM_CAPIEN BPWM_CAPIEN BPWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIENn BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 8 6 read-write 0 Capture falling edge latch interrupt Disabled 0 1 Capture falling edge latch interrupt Enabled 1 CAPRIENn BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 0 6 read-write 0 Capture rising edge latch interrupt Disabled 0 1 Capture rising edge latch interrupt Enabled 1 BPWM_CAPIF BPWM_CAPIF BPWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CAPFIF0 BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 8 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF1 BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 9 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF2 BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 10 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF3 BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 11 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF4 BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 12 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF5 BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 13 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPRIF0 BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF1 BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF2 BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 2 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF3 BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 3 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF4 BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 4 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF5 BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 5 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 BPWM_CAPINEN BPWM_CAPINEN BPWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINEN0 Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n. 0 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN1 Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n. 1 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN2 Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n. 2 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN3 Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n. 3 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN4 Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n. 4 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN5 Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n. 5 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 BPWM_CAPSTS BPWM_CAPSTS BPWM Capture Status Register 0x208 read-only n 0x0 0x0 CFIFOV0 Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared. 8 1 read-only CFIFOV1 Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared. 9 1 read-only CFIFOV2 Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared. 10 1 read-only CFIFOV3 Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared. 11 1 read-only CFIFOV4 Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared. 12 1 read-only CFIFOV5 Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared. 13 1 read-only CRIFOV0 Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared. 0 1 read-only CRIFOV1 Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared. 1 1 read-only CRIFOV2 Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared. 2 1 read-only CRIFOV3 Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared. 3 1 read-only CRIFOV4 Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared. 4 1 read-only CRIFOV5 Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared. 5 1 read-only BPWM_CLKPSC BPWM_CLKPSC BPWM Clock Prescale Register 0x14 read-write n 0x0 0x0 CLKPSC BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1). 0 12 read-write BPWM_CLKSRC BPWM_CLKSRC BPWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 BPWM_CH01 External Clock Source Select 0 3 read-write 0 BPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 BPWM_CMPBUF0 BPWM_CMPBUF0 BPWM CMPDAT 0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF BPWM Comparator Buffer (Read Only)\nUsed as CMP active register. 0 16 read-only BPWM_CMPBUF1 BPWM_CMPBUF1 BPWM CMPDAT 1 Buffer 0x320 read-write n 0x0 0x0 BPWM_CMPBUF2 BPWM_CMPBUF2 BPWM CMPDAT 2 Buffer 0x324 read-write n 0x0 0x0 BPWM_CMPBUF3 BPWM_CMPBUF3 BPWM CMPDAT 3 Buffer 0x328 read-write n 0x0 0x0 BPWM_CMPBUF4 BPWM_CMPBUF4 BPWM CMPDAT 4 Buffer 0x32C read-write n 0x0 0x0 BPWM_CMPBUF5 BPWM_CMPBUF5 BPWM CMPDAT 5 Buffer 0x330 read-write n 0x0 0x0 BPWM_CMPDAT0 BPWM_CMPDAT0 BPWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMPDAT BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC.\nIn independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. 0 16 read-write BPWM_CMPDAT1 BPWM_CMPDAT1 BPWM Comparator Register 1 0x54 read-write n 0x0 0x0 BPWM_CMPDAT2 BPWM_CMPDAT2 BPWM Comparator Register 2 0x58 read-write n 0x0 0x0 BPWM_CMPDAT3 BPWM_CMPDAT3 BPWM Comparator Register 3 0x5C read-write n 0x0 0x0 BPWM_CMPDAT4 BPWM_CMPDAT4 BPWM Comparator Register 4 0x60 read-write n 0x0 0x0 BPWM_CMPDAT5 BPWM_CMPDAT5 BPWM Comparator Register 5 0x64 read-write n 0x0 0x0 BPWM_CNT BPWM_CNT BPWM Counter Register 0x90 read-only n 0x0 0x0 CNT BPWM Data Register (Read Only)\nMonitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF BPWM Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 BPWM_CNTCLR BPWM_CNTCLR BPWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLR0 Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Clear 16-bit BPWM counter to 0000H #1 BPWM_CNTEN BPWM_CNTEN BPWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTEN0 BPWM Counter 0 Enable Bit 0 1 read-write 0 BPWM Counter and clock prescaler stop running #0 1 BPWM Counter and clock prescaler start running #1 BPWM_CTL0 BPWM_CTL0 BPWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLD0 Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 1 read-write CTRLD1 Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 1 1 read-write CTRLD2 Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 2 1 read-write CTRLD3 Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 3 1 read-write CTRLD4 Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 4 1 read-write CTRLD5 Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 5 1 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects BPWM output #0 1 ICE debug mode acknowledgement Disabled #1 IMMLDEN0 Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 16 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN1 Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 17 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN2 Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 18 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN3 Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 19 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN4 Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 20 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN5 Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 21 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 BPWM_CTL1 BPWM_CTL1 BPWM Control Register 1 0x4 read-write n 0x0 0x0 CNTTYPE0 BPWM Counter Behavior Type 0 0 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 BPWM_EADCTS0 BPWM_EADCTS0 BPWM Trigger EADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 BPWM_CH0 Trigger EADC Enable Bit 7 1 read-write TRGEN1 BPWM_CH1 Trigger EADC Enable Bit 15 1 read-write TRGEN2 BPWM_CH2 Trigger EADC Enable Bit 23 1 read-write TRGEN3 BPWM_CH3 Trigger EADC Enable Bit 31 1 read-write TRGSEL0 BPWM_CH0 Trigger EADC Source Select\nOthers reserved 0 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count compared point #0011 4 BPWM_CH0 down-count compared point #0100 8 BPWM_CH1 up-count compared point #1000 9 BPWM_CH1 down-count compared point #1001 TRGSEL1 BPWM_CH1 Trigger EADC Source Select\nOthers reserved 8 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count compared point #0011 4 BPWM_CH0 down-count compared point #0100 8 BPWM_CH1 up-count compared point #1000 9 BPWM_CH1 down-count compared point #1001 TRGSEL2 BPWM_CH2 Trigger EADC Source Select\nOthers reserved 16 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count compared point #0011 4 BPWM_CH2 down-count compared point #0100 8 BPWM_CH3 up-count compared point #1000 9 BPWM_CH3 down-count compared point #1001 TRGSEL3 BPWM_CH3 Trigger EADC Source Select\nOthers reserved. 24 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count compared point #0011 4 BPWM_CH2 down-count compared point #0100 8 BPWM_CH3 up-count compared point #1000 9 BPWM_CH3 down-count compared point #1001 BPWM_EADCTS1 BPWM_EADCTS1 BPWM Trigger EADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 BPWM_CH4 Trigger EADC Enable Bit 7 1 read-write TRGEN5 BPWM_CH5 Trigger EADC Enable Bit 15 1 read-write TRGSEL4 BPWM_CH4 Trigger EADC Source Select\nOthers reserved 0 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count compared point #0011 4 BPWM_CH4 down-count compared point #0100 8 BPWM_CH5 up-count compared point #1000 9 BPWM_CH5 down-count compared point #1001 TRGSEL5 BPWM_CH5 Trigger EADC Source Select\nOthers reserved 8 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count compared point #0011 4 BPWM_CH4 down-count compared point #0100 8 BPWM_CH5 up-count compared point #1000 9 BPWM_CH5 down-count compared point #1001 BPWM_FCAPDAT0 BPWM_FCAPDAT0 BPWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_FCAPDAT1 BPWM_FCAPDAT1 BPWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 BPWM_FCAPDAT2 BPWM_FCAPDAT2 BPWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 BPWM_FCAPDAT3 BPWM_FCAPDAT3 BPWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 BPWM_FCAPDAT4 BPWM_FCAPDAT4 BPWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 BPWM_FCAPDAT5 BPWM_FCAPDAT5 BPWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 BPWM_INTEN BPWM_INTEN BPWM Interrupt Enable Register 0xE0 read-write n 0x0 0x0 CMPDIEN0 BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 24 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN1 BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 25 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN2 BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 26 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN3 BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 27 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN4 BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 28 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN5 BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 29 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPUIEN0 BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 16 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN1 BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 17 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN2 BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 18 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN3 BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 19 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN4 BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 20 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN5 BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 21 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 PIEN0 BPWM Period Point Interrupt 0 Enable Bit\nNote: When up-down counter type period point means center point. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 BPWM Zero Point Interrupt 0 Enable Bit 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 BPWM_INTSTS BPWM_INTSTS BPWM Interrupt Flag Register 0xE8 read-write n 0x0 0x0 CMPDIF0 BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 24 1 read-write CMPDIF1 BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 25 1 read-write CMPDIF2 BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 26 1 read-write CMPDIF3 BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 27 1 read-write CMPDIF4 BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 28 1 read-write CMPDIF5 BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 29 1 read-write CMPUIF0 BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 16 1 read-write CMPUIF1 BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 17 1 read-write CMPUIF2 BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 18 1 read-write CMPUIF3 BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 19 1 read-write CMPUIF4 BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 20 1 read-write CMPUIF5 BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 21 1 read-write PIF0 BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to 0. 8 1 read-write ZIF0 BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0, software can write 1 to clear this bit to 0. 0 1 read-write BPWM_MSK BPWM_MSK BPWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDAT0 BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 0 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT1 BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 1 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT2 BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 2 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT3 BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 3 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT4 BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 4 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT5 BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 5 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 BPWM_MSKEN BPWM_MSKEN BPWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKEN0 BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 0 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN1 BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 1 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN2 BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 2 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN3 BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 3 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN4 BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 4 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN5 BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 5 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 BPWM_PBUF BPWM_PBUF BPWM PERIOD Buffer 0x304 read-only n 0x0 0x0 PBUF BPWM Period Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only BPWM_PERIOD BPWM_PERIOD BPWM Period Register 0x30 read-write n 0x0 0x0 PERIOD BPWM Period Register\nUp-Count mode: \nIn this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0. 0 16 read-write BPWM_POEN BPWM_POEN BPWM Output Enable Register 0xD8 read-write n 0x0 0x0 POEN0 BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n. 0 1 read-write 0 BPWMx_CHn pin at tri-state #0 1 BPWMx_CHn pin in output mode #1 POEN1 BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n. 1 1 read-write 0 BPWMx_CHn pin at tri-state #0 1 BPWMx_CHn pin in output mode #1 POEN2 BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n. 2 1 read-write 0 BPWMx_CHn pin at tri-state #0 1 BPWMx_CHn pin in output mode #1 POEN3 BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n. 3 1 read-write 0 BPWMx_CHn pin at tri-state #0 1 BPWMx_CHn pin in output mode #1 POEN4 BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n. 4 1 read-write 0 BPWMx_CHn pin at tri-state #0 1 BPWMx_CHn pin in output mode #1 POEN5 BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n. 5 1 read-write 0 BPWMx_CHn pin at tri-state #0 1 BPWMx_CHn pin in output mode #1 BPWM_POLCTL BPWM_POLCTL BPWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINV0 BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin. Each bit n controls the corresponding BPWM channel n. 0 1 read-write 0 BPWMx_CHn output pin polar inverse Disabled #0 1 BPWMx_CHn output pin polar inverse Enabled #1 PINV1 BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin. Each bit n controls the corresponding BPWM channel n. 1 1 read-write 0 BPWMx_CHn output pin polar inverse Disabled #0 1 BPWMx_CHn output pin polar inverse Enabled #1 PINV2 BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin. Each bit n controls the corresponding BPWM channel n. 2 1 read-write 0 BPWMx_CHn output pin polar inverse Disabled #0 1 BPWMx_CHn output pin polar inverse Enabled #1 PINV3 BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin. Each bit n controls the corresponding BPWM channel n. 3 1 read-write 0 BPWMx_CHn output pin polar inverse Disabled #0 1 BPWMx_CHn output pin polar inverse Enabled #1 PINV4 BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin. Each bit n controls the corresponding BPWM channel n. 4 1 read-write 0 BPWMx_CHn output pin polar inverse Disabled #0 1 BPWMx_CHn output pin polar inverse Enabled #1 PINV5 BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin. Each bit n controls the corresponding BPWM channel n. 5 1 read-write 0 BPWMx_CHn output pin polar inverse Disabled #0 1 BPWMx_CHn output pin polar inverse Enabled #1 BPWM_RCAPDAT0 BPWM_RCAPDAT0 BPWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_RCAPDAT1 BPWM_RCAPDAT1 BPWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 BPWM_RCAPDAT2 BPWM_RCAPDAT2 BPWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 BPWM_RCAPDAT3 BPWM_RCAPDAT3 BPWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 BPWM_RCAPDAT4 BPWM_RCAPDAT4 BPWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 BPWM_RCAPDAT5 BPWM_RCAPDAT5 BPWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 BPWM_SSCTL BPWM_SSCTL BPWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSEN0 BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). 0 1 read-write 0 BPWM synchronous start function Disabled #0 1 BPWM synchronous start function Enabled #1 SSRC BPWM Synchronous Start Source Select 8 2 read-write 0 Synchronous start source come from PWM0 #00 1 Synchronous start source come from PWM1 #01 2 Synchronous start source come from BPWM0 #10 3 Synchronous start source come from BPWM1 #11 BPWM_SSTRG BPWM_SSTRG BPWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN BPWM Counter Synchronous Start Enable Bit(Write Only)\nBPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled. 0 1 write-only BPWM_STATUS BPWM_STATUS BPWM Status Register 0x120 read-write n 0x0 0x0 CNTMAX0 Time-base Counter 0 Equal to 0xFFFF Latched Status\nNote: This bit can be cleared by software write 1. 0 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 EADCTRG0 EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1. 16 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRG1 EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1. 17 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRG2 EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1. 18 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRG3 EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1. 19 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRG4 EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1. 20 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRG5 EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1. 21 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 BPWM_WGCTL0 BPWM_WGCTL0 BPWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTL0 BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 16 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL1 BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 18 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL2 BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 20 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL3 BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 22 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL4 BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 24 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL5 BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 26 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 ZPCTL0 BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n. 0 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL1 BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n. 2 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL2 BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n. 4 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL3 BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n. 6 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL4 BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n. 8 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL5 BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n. 10 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 BPWM_WGCTL1 BPWM_WGCTL1 BPWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTL0 BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 16 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL1 BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 18 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL2 BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 20 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL3 BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 22 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL4 BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 24 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL5 BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 26 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPUCTL0 BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 0 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL1 BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 2 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL2 BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 4 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL3 BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 6 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL4 BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 8 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL5 BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 10 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 BPWM1 BPWM Register Map BPWM 0x0 0x0 0x8 registers n 0x10 0x8 registers n 0x110 0x8 registers n 0x120 0x4 registers n 0x20 0x8 registers n 0x200 0x3C registers n 0x250 0x8 registers n 0x30 0x4 registers n 0x304 0x4 registers n 0x31C 0x18 registers n 0x50 0x18 registers n 0x90 0x4 registers n 0xB0 0x10 registers n 0xD4 0x8 registers n 0xE0 0x4 registers n 0xE8 0x4 registers n 0xF8 0x8 registers n BPWM_CAPCTL BPWM_CAPCTL BPWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPEN0 Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n. 0 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN1 Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n. 1 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN2 Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n. 2 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN3 Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n. 3 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN4 Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n. 4 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN5 Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n. 5 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPINV0 Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n. 8 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV1 Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n. 9 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV2 Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n. 10 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV3 Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n. 11 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV4 Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n. 12 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV5 Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n. 13 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 FCRLDEN0 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 24 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN1 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 25 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN2 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 26 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN3 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 27 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN4 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 28 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN5 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 29 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 RCRLDEN0 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 16 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN1 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 17 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN2 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 18 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN3 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 19 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN4 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 20 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN5 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n. 21 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 BPWM_CAPIEN BPWM_CAPIEN BPWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIENn BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 8 6 read-write 0 Capture falling edge latch interrupt Disabled 0 1 Capture falling edge latch interrupt Enabled 1 CAPRIENn BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 0 6 read-write 0 Capture rising edge latch interrupt Disabled 0 1 Capture rising edge latch interrupt Enabled 1 BPWM_CAPIF BPWM_CAPIF BPWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CAPFIF0 BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 8 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF1 BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 9 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF2 BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 10 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF3 BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 11 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF4 BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 12 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF5 BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 13 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPRIF0 BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF1 BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF2 BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 2 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF3 BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 3 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF4 BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 4 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF5 BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it. 5 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 BPWM_CAPINEN BPWM_CAPINEN BPWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINEN0 Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n. 0 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN1 Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n. 1 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN2 Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n. 2 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN3 Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n. 3 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN4 Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n. 4 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN5 Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n. 5 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 BPWM_CAPSTS BPWM_CAPSTS BPWM Capture Status Register 0x208 read-only n 0x0 0x0 CFIFOV0 Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared. 8 1 read-only CFIFOV1 Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared. 9 1 read-only CFIFOV2 Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared. 10 1 read-only CFIFOV3 Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared. 11 1 read-only CFIFOV4 Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared. 12 1 read-only CFIFOV5 Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared. 13 1 read-only CRIFOV0 Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared. 0 1 read-only CRIFOV1 Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared. 1 1 read-only CRIFOV2 Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared. 2 1 read-only CRIFOV3 Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared. 3 1 read-only CRIFOV4 Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared. 4 1 read-only CRIFOV5 Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared. 5 1 read-only BPWM_CLKPSC BPWM_CLKPSC BPWM Clock Prescale Register 0x14 read-write n 0x0 0x0 CLKPSC BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1). 0 12 read-write BPWM_CLKSRC BPWM_CLKSRC BPWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 BPWM_CH01 External Clock Source Select 0 3 read-write 0 BPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 BPWM_CMPBUF0 BPWM_CMPBUF0 BPWM CMPDAT 0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF BPWM Comparator Buffer (Read Only)\nUsed as CMP active register. 0 16 read-only BPWM_CMPBUF1 BPWM_CMPBUF1 BPWM CMPDAT 1 Buffer 0x320 read-write n 0x0 0x0 BPWM_CMPBUF2 BPWM_CMPBUF2 BPWM CMPDAT 2 Buffer 0x324 read-write n 0x0 0x0 BPWM_CMPBUF3 BPWM_CMPBUF3 BPWM CMPDAT 3 Buffer 0x328 read-write n 0x0 0x0 BPWM_CMPBUF4 BPWM_CMPBUF4 BPWM CMPDAT 4 Buffer 0x32C read-write n 0x0 0x0 BPWM_CMPBUF5 BPWM_CMPBUF5 BPWM CMPDAT 5 Buffer 0x330 read-write n 0x0 0x0 BPWM_CMPDAT0 BPWM_CMPDAT0 BPWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMPDAT BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC.\nIn independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. 0 16 read-write BPWM_CMPDAT1 BPWM_CMPDAT1 BPWM Comparator Register 1 0x54 read-write n 0x0 0x0 BPWM_CMPDAT2 BPWM_CMPDAT2 BPWM Comparator Register 2 0x58 read-write n 0x0 0x0 BPWM_CMPDAT3 BPWM_CMPDAT3 BPWM Comparator Register 3 0x5C read-write n 0x0 0x0 BPWM_CMPDAT4 BPWM_CMPDAT4 BPWM Comparator Register 4 0x60 read-write n 0x0 0x0 BPWM_CMPDAT5 BPWM_CMPDAT5 BPWM Comparator Register 5 0x64 read-write n 0x0 0x0 BPWM_CNT BPWM_CNT BPWM Counter Register 0x90 read-only n 0x0 0x0 CNT BPWM Data Register (Read Only)\nMonitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF BPWM Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 BPWM_CNTCLR BPWM_CNTCLR BPWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLR0 Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Clear 16-bit BPWM counter to 0000H #1 BPWM_CNTEN BPWM_CNTEN BPWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTEN0 BPWM Counter 0 Enable Bit 0 1 read-write 0 BPWM Counter and clock prescaler stop running #0 1 BPWM Counter and clock prescaler start running #1 BPWM_CTL0 BPWM_CTL0 BPWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLD0 Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 1 read-write CTRLD1 Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 1 1 read-write CTRLD2 Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 2 1 read-write CTRLD3 Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 3 1 read-write CTRLD4 Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 4 1 read-write CTRLD5 Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 5 1 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects BPWM output #0 1 ICE debug mode acknowledgement Disabled #1 IMMLDEN0 Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 16 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN1 Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 17 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN2 Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 18 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN3 Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 19 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN4 Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 20 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN5 Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 21 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 BPWM_CTL1 BPWM_CTL1 BPWM Control Register 1 0x4 read-write n 0x0 0x0 CNTTYPE0 BPWM Counter Behavior Type 0 0 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 BPWM_EADCTS0 BPWM_EADCTS0 BPWM Trigger EADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 BPWM_CH0 Trigger EADC Enable Bit 7 1 read-write TRGEN1 BPWM_CH1 Trigger EADC Enable Bit 15 1 read-write TRGEN2 BPWM_CH2 Trigger EADC Enable Bit 23 1 read-write TRGEN3 BPWM_CH3 Trigger EADC Enable Bit 31 1 read-write TRGSEL0 BPWM_CH0 Trigger EADC Source Select\nOthers reserved 0 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count compared point #0011 4 BPWM_CH0 down-count compared point #0100 8 BPWM_CH1 up-count compared point #1000 9 BPWM_CH1 down-count compared point #1001 TRGSEL1 BPWM_CH1 Trigger EADC Source Select\nOthers reserved 8 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count compared point #0011 4 BPWM_CH0 down-count compared point #0100 8 BPWM_CH1 up-count compared point #1000 9 BPWM_CH1 down-count compared point #1001 TRGSEL2 BPWM_CH2 Trigger EADC Source Select\nOthers reserved 16 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count compared point #0011 4 BPWM_CH2 down-count compared point #0100 8 BPWM_CH3 up-count compared point #1000 9 BPWM_CH3 down-count compared point #1001 TRGSEL3 BPWM_CH3 Trigger EADC Source Select\nOthers reserved. 24 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count compared point #0011 4 BPWM_CH2 down-count compared point #0100 8 BPWM_CH3 up-count compared point #1000 9 BPWM_CH3 down-count compared point #1001 BPWM_EADCTS1 BPWM_EADCTS1 BPWM Trigger EADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 BPWM_CH4 Trigger EADC Enable Bit 7 1 read-write TRGEN5 BPWM_CH5 Trigger EADC Enable Bit 15 1 read-write TRGSEL4 BPWM_CH4 Trigger EADC Source Select\nOthers reserved 0 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count compared point #0011 4 BPWM_CH4 down-count compared point #0100 8 BPWM_CH5 up-count compared point #1000 9 BPWM_CH5 down-count compared point #1001 TRGSEL5 BPWM_CH5 Trigger EADC Source Select\nOthers reserved 8 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count compared point #0011 4 BPWM_CH4 down-count compared point #0100 8 BPWM_CH5 up-count compared point #1000 9 BPWM_CH5 down-count compared point #1001 BPWM_FCAPDAT0 BPWM_FCAPDAT0 BPWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_FCAPDAT1 BPWM_FCAPDAT1 BPWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 BPWM_FCAPDAT2 BPWM_FCAPDAT2 BPWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 BPWM_FCAPDAT3 BPWM_FCAPDAT3 BPWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 BPWM_FCAPDAT4 BPWM_FCAPDAT4 BPWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 BPWM_FCAPDAT5 BPWM_FCAPDAT5 BPWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 BPWM_INTEN BPWM_INTEN BPWM Interrupt Enable Register 0xE0 read-write n 0x0 0x0 CMPDIEN0 BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 24 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN1 BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 25 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN2 BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 26 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN3 BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 27 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN4 BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 28 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN5 BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 29 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPUIEN0 BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 16 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN1 BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 17 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN2 BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 18 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN3 BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 19 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN4 BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 20 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN5 BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n. 21 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 PIEN0 BPWM Period Point Interrupt 0 Enable Bit\nNote: When up-down counter type period point means center point. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 BPWM Zero Point Interrupt 0 Enable Bit 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 BPWM_INTSTS BPWM_INTSTS BPWM Interrupt Flag Register 0xE8 read-write n 0x0 0x0 CMPDIF0 BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 24 1 read-write CMPDIF1 BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 25 1 read-write CMPDIF2 BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 26 1 read-write CMPDIF3 BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 27 1 read-write CMPDIF4 BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 28 1 read-write CMPDIF5 BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 29 1 read-write CMPUIF0 BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 16 1 read-write CMPUIF1 BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 17 1 read-write CMPUIF2 BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 18 1 read-write CMPUIF3 BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 19 1 read-write CMPUIF4 BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 20 1 read-write CMPUIF5 BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 21 1 read-write PIF0 BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to 0. 8 1 read-write ZIF0 BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0, software can write 1 to clear this bit to 0. 0 1 read-write BPWM_MSK BPWM_MSK BPWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDAT0 BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 0 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT1 BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 1 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT2 BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 2 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT3 BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 3 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT4 BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 4 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT5 BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 5 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 BPWM_MSKEN BPWM_MSKEN BPWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKEN0 BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 0 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN1 BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 1 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN2 BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 2 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN3 BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 3 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN4 BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 4 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN5 BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 5 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 BPWM_PBUF BPWM_PBUF BPWM PERIOD Buffer 0x304 read-only n 0x0 0x0 PBUF BPWM Period Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only BPWM_PERIOD BPWM_PERIOD BPWM Period Register 0x30 read-write n 0x0 0x0 PERIOD BPWM Period Register\nUp-Count mode: \nIn this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0. 0 16 read-write BPWM_POEN BPWM_POEN BPWM Output Enable Register 0xD8 read-write n 0x0 0x0 POEN0 BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n. 0 1 read-write 0 BPWMx_CHn pin at tri-state #0 1 BPWMx_CHn pin in output mode #1 POEN1 BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n. 1 1 read-write 0 BPWMx_CHn pin at tri-state #0 1 BPWMx_CHn pin in output mode #1 POEN2 BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n. 2 1 read-write 0 BPWMx_CHn pin at tri-state #0 1 BPWMx_CHn pin in output mode #1 POEN3 BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n. 3 1 read-write 0 BPWMx_CHn pin at tri-state #0 1 BPWMx_CHn pin in output mode #1 POEN4 BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n. 4 1 read-write 0 BPWMx_CHn pin at tri-state #0 1 BPWMx_CHn pin in output mode #1 POEN5 BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n. 5 1 read-write 0 BPWMx_CHn pin at tri-state #0 1 BPWMx_CHn pin in output mode #1 BPWM_POLCTL BPWM_POLCTL BPWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINV0 BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin. Each bit n controls the corresponding BPWM channel n. 0 1 read-write 0 BPWMx_CHn output pin polar inverse Disabled #0 1 BPWMx_CHn output pin polar inverse Enabled #1 PINV1 BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin. Each bit n controls the corresponding BPWM channel n. 1 1 read-write 0 BPWMx_CHn output pin polar inverse Disabled #0 1 BPWMx_CHn output pin polar inverse Enabled #1 PINV2 BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin. Each bit n controls the corresponding BPWM channel n. 2 1 read-write 0 BPWMx_CHn output pin polar inverse Disabled #0 1 BPWMx_CHn output pin polar inverse Enabled #1 PINV3 BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin. Each bit n controls the corresponding BPWM channel n. 3 1 read-write 0 BPWMx_CHn output pin polar inverse Disabled #0 1 BPWMx_CHn output pin polar inverse Enabled #1 PINV4 BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin. Each bit n controls the corresponding BPWM channel n. 4 1 read-write 0 BPWMx_CHn output pin polar inverse Disabled #0 1 BPWMx_CHn output pin polar inverse Enabled #1 PINV5 BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin. Each bit n controls the corresponding BPWM channel n. 5 1 read-write 0 BPWMx_CHn output pin polar inverse Disabled #0 1 BPWMx_CHn output pin polar inverse Enabled #1 BPWM_RCAPDAT0 BPWM_RCAPDAT0 BPWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_RCAPDAT1 BPWM_RCAPDAT1 BPWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 BPWM_RCAPDAT2 BPWM_RCAPDAT2 BPWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 BPWM_RCAPDAT3 BPWM_RCAPDAT3 BPWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 BPWM_RCAPDAT4 BPWM_RCAPDAT4 BPWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 BPWM_RCAPDAT5 BPWM_RCAPDAT5 BPWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 BPWM_SSCTL BPWM_SSCTL BPWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSEN0 BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). 0 1 read-write 0 BPWM synchronous start function Disabled #0 1 BPWM synchronous start function Enabled #1 SSRC BPWM Synchronous Start Source Select 8 2 read-write 0 Synchronous start source come from PWM0 #00 1 Synchronous start source come from PWM1 #01 2 Synchronous start source come from BPWM0 #10 3 Synchronous start source come from BPWM1 #11 BPWM_SSTRG BPWM_SSTRG BPWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN BPWM Counter Synchronous Start Enable Bit(Write Only)\nBPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled. 0 1 write-only BPWM_STATUS BPWM_STATUS BPWM Status Register 0x120 read-write n 0x0 0x0 CNTMAX0 Time-base Counter 0 Equal to 0xFFFF Latched Status\nNote: This bit can be cleared by software write 1. 0 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 EADCTRG0 EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1. 16 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRG1 EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1. 17 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRG2 EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1. 18 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRG3 EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1. 19 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRG4 EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1. 20 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRG5 EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1. 21 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 BPWM_WGCTL0 BPWM_WGCTL0 BPWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTL0 BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 16 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL1 BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 18 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL2 BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 20 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL3 BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 22 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL4 BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 24 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL5 BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 26 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 ZPCTL0 BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n. 0 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL1 BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n. 2 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL2 BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n. 4 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL3 BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n. 6 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL4 BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n. 8 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL5 BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n. 10 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 BPWM_WGCTL1 BPWM_WGCTL1 BPWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTL0 BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 16 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL1 BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 18 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL2 BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 20 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL3 BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 22 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL4 BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 24 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL5 BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 26 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPUCTL0 BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 0 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL1 BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 2 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL2 BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 4 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL3 BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 6 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL4 BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 8 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL5 BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n. 10 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CAN CAN Register Map CAN 0x0 0x0 0x1C registers n 0x100 0x8 registers n 0x120 0x8 registers n 0x140 0x8 registers n 0x160 0x10 registers n 0x20 0x2C registers n 0x80 0x2C registers n BRPE CAN_BRPE Baud Rate Prescaler Extension Register 0x18 read-write n 0x0 0x0 BRPE BRPE: Baud Rate Prescaler Extension\n0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023. The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used. 0 4 read-write BTIME CAN_BTIME Bit Timing Register 0xC -1 read-write n 0x0 0x0 BRP Baud Rate Prescaler \n0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are [0...63]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 0 6 read-write SJW (Re)Synchronization Jump Width\n0x0-0x3: Valid programmed values are [0...3]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 6 2 read-write TSeg1 Time Segment Before the Sample Point Minus Sync_Seg\n0x01-0x0F: valid values for TSeg1 are [1...15]. The actual interpretation by the hardware of this value is such that one more than the value programmed is used. 8 4 read-write TSeg2 Time Segment After Sample Point \n0x0-0x7: Valid values for TSeg2 are [0...7]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 12 3 read-write CON CAN_CON Control Register 0x0 -1 read-write n 0x0 0x0 CCE Configuration Change Enable Bit 6 1 read-write 0 No write access to the Bit Timing Register #0 1 Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1) #1 DAR Automatic Re-transmission Disable Bit 5 1 read-write 0 Automatic Retransmission of disturbed messages Enabled #0 1 Automatic Retransmission Disabled #1 EIE Error Interrupt Enable Bit 3 1 read-write 0 Disabled - No Error Status Interrupt will be generated #0 1 Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt #1 IE Module Interrupt Enable Bit 1 1 read-write 0 Funcrion interrupt Disabled #0 1 Funcrion interrupt Enabled #1 Init Init Initialization 0 1 read-write 0 Normal Operation #0 1 Initialization is started #1 SIE Status Change Interrupt Enable Bit 2 1 read-write 0 Disabled - No Status Change Interrupt will be generated #0 1 Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected #1 Test Test Mode Enable Bit 7 1 read-write 0 Normal Operation #0 1 Test Mode #1 ERR CAN_ERR Error Counter Register 0x8 read-only n 0x0 0x0 REC Receive Error Counter\nActual state of the Receive Error Counter. Values between 0 and 127. 8 7 read-only RP Receive Error Passive 15 1 read-only 0 The Receive Error Counter is below the error passive level #0 1 The Receive Error Counter has reached the error passive level as defined in the CAN Specification #1 TEC Transmit Error Counter\nActual state of the Transmit Error Counter. Values between 0 and 255. 0 8 read-only IF1_ARB1 CAN_IF1_ARB1 IFn Arbitration 1 Registers 0x30 read-write n 0x0 0x0 ID Message Identifier 15-0\nID28 - ID0, 29-bit Identifier ('Extended Frame').\nID28 - ID18, 11-bit Identifier ('Standard Frame') 0 16 read-write IF1_ARB2 CAN_IF1_ARB2 IFn Arbitration 2 Registers 0x34 read-write n 0x0 0x0 Dir Message Direction 13 1 read-write 0 Direction is receive #0 1 Direction is transmit #1 ID Message Identifier 28-16\nID28 - ID0, 29-bit Identifier ('Extended Frame').\nID28 - ID18, 11-bit Identifier ('Standard Frame') 0 13 read-write MsgVal Message Valid Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]). This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_ARB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required. 15 1 read-write 0 The Message Object is ignored by the Message Handler #0 1 The Message Object is configured and should be considered by the Message Handler #1 Xtd Extended Identifier 14 1 read-write 0 The 11-bit ('standard') Identifier will be used for this Message Object #0 1 The 29-bit ('extended') Identifier will be used for this Message Object #1 IF1_CMASK CAN_IF1_CMASK IFn Command Mask Registers 0x24 read-write n 0x0 0x0 Arb Access Arbitration Bits\nWrite Operation: 5 1 read-write 0 Arbitration bits unchanged #0 1 Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_ARB2[15]) to Message Object.\nTransfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register #1 ClrIntPnd Clear Interrupt Pending Bit\nWrite Operation:\nWhen writing to a Message Object, this bit is ignored.\nRead Operation: 3 1 read-write 0 IntPnd bit (CAN_IFn_MCON[13]) remains unchanged #0 1 Clear IntPnd bit in the Message Object #1 Control Control Access Control Bits\nWrite Operation: 4 1 read-write 0 Control Bits unchanged #0 1 Transfer Control Bits to Message Object.\nTransfer Control Bits to IFn Message Buffer Register #1 DAT_A Access Data Bytes [3:0]\nWrite Operation: 1 1 read-write 0 Data Bytes [3:0] unchanged #0 1 Transfer Data Bytes [3:0] to Message Object.\nTransfer Data Bytes [3:0] to IFn Message Buffer Register #1 DAT_B Access Data Bytes [7:4]\nWrite Operation: 0 1 read-write 0 Data Bytes [7:4] unchanged #0 1 Transfer Data Bytes [7:4] to Message Object.\nTransfer Data Bytes [7:4] to IFn Message Buffer Register #1 Mask Access Mask Bits\nWrite Operation: 6 1 read-write 0 Mask bits unchanged #0 1 Transfer Identifier Mask + MDir + MXtd to Message Object.\nTransfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register #1 TxRqst_NewDat Access Transmission Request Bit When Write Operation\nNote: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits. 2 1 read-write 0 TxRqst bit unchanged.\nNewDat bit remains unchanged #0 1 Set TxRqst bit.\nClear NewDat bit in the Message Object #1 WR_RD Write / Read Mode 7 1 read-write 0 Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers #0 1 Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register #1 IF1_CREQ CAN_IF1_CREQ IFn (Register Map Note 2) Command Request Registers 0x20 -1 read-write n 0x0 0x0 Busy Busy Flag 15 1 read-write 0 Read/write action has finished #0 1 Writing to the IFn Command Request Register is in progress. This bit can only be read by the software #1 MessageNumber Message Number\n0x01-0x20: Valid Message Number, the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number, interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F. 0 6 read-write IF1_DAT_A1 CAN_IF1_DAT_A1 IFn Data A1 Registers (Register Map Note 3) 0x3C read-write n 0x0 0x0 Data_0 Data Byte 0\n1st data byte of a CAN Data Frame 0 8 read-write Data_1 Data Byte 1\n2nd data byte of a CAN Data Frame 8 8 read-write IF1_DAT_A2 CAN_IF1_DAT_A2 IFn Data A2 Registers (Register Map Note 3) 0x40 read-write n 0x0 0x0 Data_2 Data Byte 2\n3rd data byte of CAN Data Frame 0 8 read-write Data_3 Data Byte 3\n4th data byte of CAN Data Frame 8 8 read-write IF1_DAT_B1 CAN_IF1_DAT_B1 IFn Data B1 Registers (Register Map Note 3) 0x44 read-write n 0x0 0x0 Data_4 Data Byte 4\n5th data byte of CAN Data Frame 0 8 read-write Data_5 Data Byte 5\n6th data byte of CAN Data Frame 8 8 read-write IF1_DAT_B2 CAN_IF1_DAT_B2 IFn Data B2 Registers (Register Map Note 3) 0x48 read-write n 0x0 0x0 Data_6 Data Byte 6\n7th data byte of CAN Data Frame. 0 8 read-write Data_7 Data Byte 7\n8th data byte of CAN Data Frame. 8 8 read-write IF1_MASK1 CAN_IF1_MASK1 IFn Mask 1 Registers 0x28 -1 read-write n 0x0 0x0 Msk Identifier Mask 15-0 0 16 read-write 0 The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering 0 1 The corresponding identifier bit is used for acceptance filtering 1 IF1_MASK2 CAN_IF1_MASK2 IFn Mask 2 Registers 0x2C -1 read-write n 0x0 0x0 MDir Mask Message Direction 14 1 read-write 0 The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering #0 1 The message direction bit (Dir) is used for acceptance filtering #1 Msk Identifier Mask 28-16 0 13 read-write 0 The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering 0 1 The corresponding identifier bit is used for acceptance filtering 1 MXtd Mask Extended Identifier Note: When 11-bit ('standard') Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]). For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered. 15 1 read-write 0 The extended identifier bit (IDE) has no effect on the acceptance filtering #0 1 The extended identifier bit (IDE) is used for acceptance filtering #1 IF1_MCON CAN_IF1_MCON IFn Message Control Registers 0x38 read-write n 0x0 0x0 DLC Data Length Code\n0-8: Data Frame has 0-8 data bytes.\n9-15: Data Frame has 8 data bytes\nNote: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.\nData(0): 1st data byte of a CAN Data Frame\nData(1): 2nd data byte of a CAN Data Frame\nData(2): 3rd data byte of a CAN Data Frame\nData(3): 4th data byte of a CAN Data Frame\nData(4): 5th data byte of a CAN Data Frame\nData(5): 6th data byte of a CAN Data Frame\nData(6): 7th data byte of a CAN Data Frame\nData(7): 8th data byte of a CAN Data Frame\nNote: The Data(0) byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data(7) byte is the last. When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object. If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values. 0 4 read-write EoB End of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one. 7 1 read-write 0 Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer #0 1 Single Message Object or last Message Object of a FIFO Buffer #1 IntPnd Interrupt Pending 13 1 read-write 0 This message object is not the source of an interrupt #0 1 This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority #1 MsgLst Message Lost 14 1 read-write 0 No message lost since last time this bit was reset by the CPU #0 1 The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message #1 NewDat New Data 15 1 read-write 0 No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software #0 1 The Message Handler or the application software has written new data into the data portion of this Message Object #1 RmtEn Remote Enable Bit 9 1 read-write 0 At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged #0 1 At the reception of a Remote Frame, TxRqst is set #1 RxIE Receive Interrupt Enable Bit 10 1 read-write 0 IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame #0 1 IntPnd will be set after a successful reception of a frame #1 TxIE Transmit Interrupt Enable Bit 11 1 read-write 0 IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame #0 1 IntPnd will be set after a successful transmission of a frame #1 TxRqst Transmit Request 8 1 read-write 0 This Message Object is not waiting for transmission #0 1 The transmission of this Message Object is requested and is not yet done #1 UMask Use Acceptance Mask Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one. 12 1 read-write 0 Mask ignored #0 1 Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering #1 IF2_ARB1 CAN_IF2_ARB1 IFn Arbitration 1 Registers 0x90 read-write n 0x0 0x0 IF2_ARB2 CAN_IF2_ARB2 IFn Arbitration 2 Registers 0x94 read-write n 0x0 0x0 IF2_CMASK CAN_IF2_CMASK IFn Command Mask Registers 0x84 read-write n 0x0 0x0 IF2_CREQ CAN_IF2_CREQ IFn (Register Map Note 2) Command Request Registers 0x80 read-write n 0x0 0x0 IF2_DAT_A1 CAN_IF2_DAT_A1 IFn Data A1 Registers (Register Map Note 3) 0x9C read-write n 0x0 0x0 IF2_DAT_A2 CAN_IF2_DAT_A2 IFn Data A2 Registers (Register Map Note 3) 0xA0 read-write n 0x0 0x0 IF2_DAT_B1 CAN_IF2_DAT_B1 IFn Data B1 Registers (Register Map Note 3) 0xA4 read-write n 0x0 0x0 IF2_DAT_B2 CAN_IF2_DAT_B2 IFn Data B2 Registers (Register Map Note 3) 0xA8 read-write n 0x0 0x0 IF2_MASK1 CAN_IF2_MASK1 IFn Mask 1 Registers 0x88 read-write n 0x0 0x0 IF2_MASK2 CAN_IF2_MASK2 IFn Mask 2 Registers 0x8C read-write n 0x0 0x0 IF2_MCON CAN_IF2_MCON IFn Message Control Registers 0x98 read-write n 0x0 0x0 IIDR CAN_IIDR Interrupt Identifier Register 0x10 read-only n 0x0 0x0 IntId Interrupt Identifier (Indicates the Source of the Interrupt)\nIf several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the application software has cleared it. If IntId is different from 0x0000 and IE (CAN_CON[1]) is set, the IRQ interrupt signal to the EIC is active. The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.\nThe Status Interrupt has the highest priority. Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.\nA message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]). The Status Interrupt is cleared by reading the Status Register. 0 16 read-only IPND1 CAN_IPND1 Interrupt Pending Register 1 0x140 read-only n 0x0 0x0 IntPnd16_1 Interrupt Pending Bits 16-1 (of All Message Objects) 0 16 read-only 0 This message object is not the source of an interrupt 0 1 This message object is the source of an interrupt 1 IPND2 CAN_IPND2 Interrupt Pending Register 2 0x144 read-only n 0x0 0x0 IntPnd32_17 Interrupt Pending Bits 32-17 (of All Message Objects) 0 16 read-only 0 This message object is not the source of an interrupt 0 1 This message object is the source of an interrupt 1 MVLD1 CAN_MVLD1 Message Valid Register 1 0x160 read-only n 0x0 0x0 MsgVal16_1 Message Valid Bits 16-1 (of All Message Objects) (Read Only)\nNote: CAN_MVLD1[0] means Message object No.1 is valid or not. If CAN_MVLD1[0] is set, message object No.1 is configured. 0 16 read-only 0 This Message Object is ignored by the Message Handler 0 1 This Message Object is configured and should be considered by the Message Handler 1 MVLD2 CAN_MVLD2 Message Valid Register 2 0x164 read-only n 0x0 0x0 MsgVal32_17 Message Valid Bits 32-17 (of All Message Objects) (Read Only)\nNote: CAN_MVLD2[15] means Message object No.32 is valid or not. If CAN_MVLD2[15] is set, message object No.32 is configured. 0 16 read-only 0 This Message Object is ignored by the Message Handler 0 1 This Message Object is configured and should be considered by the Message Handler 1 NDAT1 CAN_NDAT1 New Data Register 1 0x120 read-only n 0x0 0x0 NewData16_1 New Data Bits 16-1 (of All Message Objects) 0 16 read-only 0 No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software 0 1 The Message Handler or the application software has written new data into the data portion of this Message Object 1 NDAT2 CAN_NDAT2 New Data Register 2 0x124 read-only n 0x0 0x0 NewData32_17 New Data Bits 32-17 (of All Message Objects) 0 16 read-only 0 No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software 0 1 The Message Handler or the application software has written new data into the data portion of this Message Object 1 STATUS CAN_STATUS Status Register 0x4 read-write n 0x0 0x0 BOff Bus-off Status (Read Only) 7 1 read-only 0 The CAN module is not in bus-off state #0 1 The CAN module is in bus-off state #1 EPass Error Passive (Read Only) 5 1 read-only 0 The CAN Core is error active #0 1 The CAN Core is in the error passive state as defined in the CAN Specification #1 EWarn Error Warning Status (Read Only) 6 1 read-only 0 Both error counters are below the error warning limit of 96 #0 1 At least one of the error counters in the EML has reached the error warning limit of 96 #1 LEC Last Error Code (Type of the Last Error to Occur on the CAN Bus)\nThe LEC field holds a code, which indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. The unused code '7' may be written by the CPU to check for updates. Table 6.265 Last Error Codedescribes the error code. 0 3 read-write RxOK Received a Message Successfully 4 1 read-write 0 No message has been successfully received since this bit was last reset by the CPU. This bit is never reset by the CAN Core #0 1 A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering) #1 TxOK Transmitted a Message Successfully 3 1 read-write 0 Since this bit was reset by the CPU, no message has been successfully transmitted. This bit is never reset by the CAN Core #0 1 Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted #1 TEST CAN_TEST Test Register (Register Map Note 1) 0x14 -1 read-write n 0x0 0x0 Basic Basic Mode 2 1 read-write 0 Basic Mode Disabled #0 1 IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer #1 LBack Loop Back Mode Enable Bit 4 1 read-write 0 Loop Back Mode Disabled #0 1 Loop Back Mode Enabled #1 Rx Monitors the Actual Value of CAN_RX Pin (Read Only) *(1) 7 1 read-only 0 The CAN bus is dominant (CAN_RX = '0') #0 1 The CAN bus is recessive (CAN_RX = '1') #1 Silent Silent Mode 3 1 read-write 0 Normal operation #0 1 The module is in Silent Mode #1 Tx Tx[1:0]: Control of CAN_TX Pin 5 2 read-write 0 Reset value, CAN_TX pin is controlled by the CAN Core #00 1 Sample Point can be monitored at CAN_TX pin #01 2 CAN_TX pin drives a dominant ('0') value #10 3 CAN_TX pin drives a recessive ('1') value #11 TXREQ1 CAN_TXREQ1 Transmission Request Register 1 0x100 read-only n 0x0 0x0 TxRqst16_1 Transmission Request Bits 16-1 (of All Message Objects) (Read Only) 0 16 read-only 0 This Message Object is not waiting for transmission 0 1 The transmission of this Message Object is requested and is not yet done 1 TXREQ2 CAN_TXREQ2 Transmission Request Register 2 0x104 read-only n 0x0 0x0 TxRqst32_17 Transmission Request Bits 32-17 (of All Message Objects) (Read Only) 0 16 read-only 0 This Message Object is not waiting for transmission 0 1 The transmission of this Message Object is requested and is not yet done 1 WU_EN CAN_WU_EN Wake-up Enable Control Register 0x168 read-write n 0x0 0x0 WAKUP_EN Wake-up Enable Bit\nNote: User can wake up system when there is a falling edge in the CAN_Rx pin. 0 1 read-write 0 The wake-up function Disabled #0 1 The wake-up function Enabled #1 WU_STATUS CAN_WU_STATUS Wake-up Status Register 0x16C read-write n 0x0 0x0 WAKUP_STS Wake-up Status \nNote: This bit can be cleared by writing '0' to it. 0 1 read-write 0 No wake-up event occurred #0 1 Wake-up event occurred #1 CLK CLK Register Map CLK 0x0 0x0 0x28 registers n 0x30 0x8 registers n 0x40 0x4 registers n 0x50 0x4 registers n 0x60 0x4 registers n 0x70 0x10 registers n 0x90 0x8 registers n 0x9C 0x1C registers n AHBCLK CLK_AHBCLK AHB Devices Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 CRCCKEN CRC Generator Controller Clock Enable Bit 7 1 read-write 0 CRC peripheral clock Disabled #0 1 CRC peripheral clock Enabled #1 CRPTCKEN Cryptographic Accelerator Clock Enable Bit 12 1 read-write 0 Cryptographic Accelerator clock Disabled #0 1 Cryptographic Accelerator clock Enabled #1 EBICKEN EBI Controller Clock Enable Bit 3 1 read-write 0 EBI peripheral clock Disabled #0 1 EBI peripheral clock Enabled #1 FMCIDLE Flash Memory Controller Clock Enable Bit in IDLE Mode 15 1 read-write 0 FMC clock Disabled when chip is under IDLE mode #0 1 FMC clock Enabled when chip is under IDLE mode #1 ISPCKEN Flash ISP Controller Clock Enable Bit 2 1 read-write 0 Flash ISP peripheral clock Disabled #0 1 Flash ISP peripheral clock Enabled #1 PDMA0CKEN PDMA0 Controller Clock Enable Bit 0 1 read-write 0 PDMA0 peripheral clock Disabled #0 1 PDMA0 peripheral clock Enabled #1 PDMA1CKEN PDMA1 Controller Clock Enable Bit 1 1 read-write 0 PDMA1 peripheral clock Disabled #0 1 PDMA1 peripheral clock Enabled #1 SDH0CKEN SDHOST0 Controller Clock Enable Bit 6 1 read-write 0 SDHOST0 peripheral clock Disabled #0 1 SDHOST0 peripheral clock Enabled #1 USBHCKEN USB HOST 1.1 Controller Clock Enable Bit 16 1 read-write 0 USB HOST 1.1 peripheral clock Disabled #0 1 USB HOST 1.1 peripheral clock Enabled #1 APBCLK0 CLK_APBCLK0 APB Devices Clock Enable Control Register 0 0x8 -1 read-write n 0x0 0x0 ACMP01CKEN Analog Comparator 0/1 Clock Enable Bit 7 1 read-write 0 Analog comparator 0/1 clock Disabled #0 1 Analog comparator 0/1 clock Enabled #1 CAN0CKEN CAN0 Clock Enable Bit 24 1 read-write 0 CAN0 clock Disabled #0 1 CAN0 clock Enabled #1 CLKOCKEN CLKO Clock Enable Bit 6 1 read-write 0 CLKO clock Disabled #0 1 CLKO clock Enabled #1 EADCCKEN Enhanced Analog-digital-converter (EADC) Clock Enable Bit 28 1 read-write 0 EADC clock Disabled #0 1 EADC clock Enabled #1 I2C0CKEN I2C0 Clock Enable Bit 8 1 read-write 0 I2C0 clock Disabled #0 1 I2C0 clock Enabled #1 I2C1CKEN I2C1 Clock Enable Bit 9 1 read-write 0 I2C1 clock Disabled #0 1 I2C1 clock Enabled #1 I2C2CKEN I2C2 Clock Enable Bit 10 1 read-write 0 I2C2 clock Disabled #0 1 I2C2 clock Enabled #1 I2S0CKEN I2S0 Clock Enable Bit 29 1 read-write 0 I2S0 Clock Disabled #0 1 I2S0 Clock Enabled #1 OTGCKEN USB OTG Clock Enable Bit 26 1 read-write 0 USB OTG clock Disabled #0 1 USB OTG clock Enabled #1 QSPI0CKEN QSPI0 Clock Enable Bit 12 1 read-write 0 QSPI0 clock Disabled #0 1 QSPI0 clock Enabled #1 RTCCKEN Real-time-clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only. The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]). It can be selected to 32.768 kHz external low speed crystal (LXT) or 10 kHz internal low speed RC oscillator (LIRC). 1 1 read-write 0 RTC clock Disabled #0 1 RTC clock Enabled #1 SPI0CKEN SPI0 Clock Enable Bit 13 1 read-write 0 SPI0 clock Disabled #0 1 SPI0 clock Enabled #1 SPI1CKEN SPI1 Clock Enable Bit 14 1 read-write 0 SPI1 clock Disabled #0 1 SPI1 clock Enabled #1 SPI2CKEN SPI2 Clock Enable Bit 15 1 read-write 0 SPI2 clock Disabled #0 1 SPI2 clock Enabled #1 TMR0CKEN Timer0 Clock Enable Bit 2 1 read-write 0 Timer0 clock Disabled #0 1 Timer0 clock Enabled #1 TMR1CKEN Timer1 Clock Enable Bit 3 1 read-write 0 Timer1 clock Disabled #0 1 Timer1 clock Enabled #1 TMR2CKEN Timer2 Clock Enable Bit 4 1 read-write 0 Timer2 clock Disabled #0 1 Timer2 clock Enabled #1 TMR3CKEN Timer3 Clock Enable Bit 5 1 read-write 0 Timer3 clock Disabled #0 1 Timer3 clock Enabled #1 UART0CKEN UART0 Clock Enable Bit 16 1 read-write 0 UART0 clock Disabled #0 1 UART0 clock Enabled #1 UART1CKEN UART1 Clock Enable Bit 17 1 read-write 0 UART1 clock Disabled #0 1 UART1 clock Enabled #1 UART2CKEN UART2 Clock Enable Bit 18 1 read-write 0 UART2 clock Disabled #0 1 UART2 clock Enabled #1 UART3CKEN UART3 Clock Enable Bit 19 1 read-write 0 UART3 clock Disabled #0 1 UART3 clock Enabled #1 UART4CKEN UART4 Clock Enable Bit 20 1 read-write 0 UART4 clock Disabled #0 1 UART4 clock Enabled #1 UART5CKEN UART5 Clock Enable Bit 21 1 read-write 0 UART5 clock Disabled #0 1 UART5 clock Enabled #1 USBDCKEN USB Device Clock Enable Bit 27 1 read-write 0 USB Device clock Disabled #0 1 USB Device clock Enabled #1 WDTCKEN Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Watchdog timer clock Disabled #0 1 Watchdog timer clock Enabled #1 APBCLK1 CLK_APBCLK1 APB Devices Clock Enable Control Register 1 0xC read-write n 0x0 0x0 BPWM0CKEN BPWM0 Clock Enable Bit 18 1 read-write 0 BPWM0 clock Disabled #0 1 BPWM0 clock Enabled #1 BPWM1CKEN BPWM1 Clock Enable Bit 19 1 read-write 0 BPWM1 clock Disabled #0 1 BPWM1 clock Enabled #1 DACCKEN DAC Clock Enable Bit 12 1 read-write 0 DAC clock Disabled #0 1 DAC clock Enabled #1 ECAP0CKEN ECAP0 Clock Enable Bit 26 1 read-write 0 ECAP0 clock Disabled #0 1 ECAP0 clock Enabled #1 ECAP1CKEN ECAP1 Clock Enable Bit 27 1 read-write 0 ECAP1 clock Disabled #0 1 ECAP1 clock Enabled #1 EPWM0CKEN EPWM0 Clock Enable Bit 16 1 read-write 0 EPWM0 clock Disabled #0 1 EPWM0 clock Enabled #1 EPWM1CKEN EPWM1 Clock Enable Bit 17 1 read-write 0 EPWM1 clock Disabled #0 1 EPWM1 clock Enabled #1 QEI0CKEN QEI0 Clock Enable Bit 22 1 read-write 0 QEI0 clock Disabled #0 1 QEI0 clock Enabled #1 QEI1CKEN QEI1 Clock Enable Bit 23 1 read-write 0 QEI1 clock Disabled #0 1 QEI1 clock Enabled #1 SC0CKEN Smart Card 0 (SC0) Clock Enable Bit 0 1 read-write 0 SC0 clock Disabled #0 1 SC0 clock Enabled #1 SC1CKEN Smart Card 1 (SC1) Clock Enable Bit 1 1 read-write 0 SC1 clock Disabled #0 1 SC1 clock Enabled #1 SC2CKEN Smart Card 2 (SC2) Clock Enable Bit 2 1 read-write 0 SC2 clock Disabled #0 1 SC2 clock Enabled #1 SPI3CKEN SPI3 Clock Enable Bit 6 1 read-write 0 SPI3 clock Disabled #0 1 SPI3 clock Enabled #1 TRNGCKEN TRNG Clock Enable Bit 25 1 read-write 0 TRNG clock Disabled #0 1 TRNG clock Enabled #1 USCI0CKEN USCI0 Clock Enable Bit 8 1 read-write 0 USCI0 clock Disabled #0 1 USCI0 clock Enabled #1 USCI1CKEN USCI1 Clock Enable Bit 9 1 read-write 0 USCI1 clock Disabled #0 1 USCI1 clock Enabled #1 CDLOWB CLK_CDLOWB Clock Frequency Detector Lower Boundary Register 0x7C read-write n 0x0 0x0 LOWERBD HXT Clock Frequency Detector Lower Boundary\nThe bits define the low value of frequency monitor window.\nWhen HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1. 0 10 read-write CDUPB CLK_CDUPB Clock Frequency Detector Upper Boundary Register 0x78 read-write n 0x0 0x0 UPERBD HXT Clock Frequency Detector Upper Boundary\nThe bits define the high value of frequency monitor window.\nWhen HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1. 0 10 read-write CLKDCTL CLK_CLKDCTL Clock Fail Detector Control Register 0x70 read-write n 0x0 0x0 HXTFDEN HXT Clock Fail Detector Enable Bit\n 4 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled #1 HXTFIEN HXT Clock Fail Interrupt Enable Bit 5 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled #1 HXTFQDEN HXT Clock Frequency Monitor Enable Bit 16 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled #1 HXTFQIEN HXT Clock Frequency Monitor Interrupt Enable Bit 17 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled #1 LXTFDEN LXT Clock Fail Detector Enable Bit 12 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled #1 LXTFIEN LXT Clock Fail Interrupt Enable Bit 13 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled #1 CLKDIV0 CLK_CLKDIV0 Clock Divider Number Register 0 0x20 read-write n 0x0 0x0 EADCDIV EADC Clock Divide Number From EADC Clock Source 16 8 read-write HCLKDIV HCLK Clock Divide Number From HCLK Clock Source 0 4 read-write SDH0DIV SDHOST0 Clock Divide Number From SDHOST0 Clock Source 24 8 read-write UART0DIV UART0 Clock Divide Number From UART0 Clock Source 8 4 read-write UART1DIV UART1 Clock Divide Number From UART1 Clock Source 12 4 read-write USBDIV USB Clock Divide Number From PLL Clock 4 4 read-write CLKDIV1 CLK_CLKDIV1 Clock Divider Number Register 1 0x24 read-write n 0x0 0x0 SC0DIV Smart Card 0 (SC0) Clock Divide Number From SC0 Clock Source 0 8 read-write SC1DIV Smart Card 1 (SC1) Clock Divide Number From SC1 Clock Source 8 8 read-write SC2DIV Smart Card 2 (SC2) Clock Divide Number From SC2 Clock Source 16 8 read-write CLKDIV4 CLK_CLKDIV4 Clock Divider Number Register 4 0x30 read-write n 0x0 0x0 UART2DIV UART2 Clock Divide Number From UART2 Clock Source 0 4 read-write UART3DIV UART3 Clock Divide Number From UART3 Clock Source 4 4 read-write UART4DIV UART4 Clock Divide Number From UART4 Clock Source 8 4 read-write UART5DIV UART5 Clock Divide Number From UART5 Clock Source 12 4 read-write CLKDSTS CLK_CLKDSTS Clock Fail Detector Status Register 0x74 read-write n 0x0 0x0 HXTFIF HXT Clock Fail Interrupt Flag (Write Protect)\nNote1: Write 1 to clear the bit to 0.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock is normal #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock stops #1 HXTFQIF HXT Clock Frequency Monitor Interrupt Flag (Write Protect)\nNote1: Write 1 to clear the bit to 0.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 8 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock is normal #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal #1 LXTFIF LXT Clock Fail Interrupt Flag (Write Protect)\nNote1: Write 1 to clear the bit to 0. \nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock is normal #0 1 32.768 kHz external low speed crystal oscillator (LXT) stops #1 CLKOCTL CLK_CLKOCTL Clock Output Control Register 0x60 read-write n 0x0 0x0 CLK1HZEN Clock Output 1Hz Enable Bit 6 1 read-write 0 1 Hz clock output for 32.768 kHz frequency compensation Disabled #0 1 1 Hz clock output for 32.768 kHz frequency compensation Enabled #1 CLKOEN Clock Output Enable Bit 4 1 read-write 0 Clock Output function Disabled #0 1 Clock Output function Enabled #1 DIV1EN Clock Output Divide One Enable Bit 5 1 read-write 0 Clock Output will output clock with source frequency divided by FREQSEL #0 1 Clock Output will output clock with source frequency #1 FREQSEL Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]. 0 4 read-write CLKSEL0 CLK_CLKSEL0 Clock Source Select Control Register 0 0x10 -1 read-write n 0x0 0x0 HCLKSEL HCLK Clock Source Selection (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turned on.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 0 3 read-write 0 Clock source from HXT #000 1 Clock source from LXT #001 2 Clock source from PLL #010 3 Clock source from LIRC #011 4 Reserved #100 5 Clock source from HIRC48 #101 7 Clock source from HIRC #111 SDH0SEL SDHOST0 Peripheral Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 20 2 read-write 0 Clock source from HXT clock #00 1 Clock source from PLL clock #01 2 Clock source from HCLK #10 3 Clock source from HIRC clock #11 STCLKSEL SysTick Clock Source Selection (Write Protect)\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register. 3 3 read-write 0 Clock source from HXT #000 1 Clock source from LXT #001 2 Clock source from HXT/2 #010 3 Clock source from HCLK/2 #011 7 Clock source from HIRC/2 #111 USBSEL USB Clock Source Selection (Write Protect) 8 1 read-write 0 Clock source from HIRC48 #0 1 Clock source from PLL #1 CLKSEL1 CLK_CLKSEL1 Clock Source Select Control Register 1 0x14 -1 read-write n 0x0 0x0 CLKOSEL Clock Output Clock Source Selection 28 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #01 2 Clock source from HCLK #10 3 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #11 TMR0SEL TIMER0 Clock Source Selection 8 3 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK0 #010 3 Clock source from external clock TM0 pin #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #101 7 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #111 TMR1SEL TIMER1 Clock Source Selection 12 3 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK0 #010 3 Clock source from external clock TM1 pin #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #101 7 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #111 TMR2SEL TIMER2 Clock Source Selection 16 3 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK1 #010 3 Clock source from external clock TM2 pin #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #101 7 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #111 TMR3SEL TIMER3 Clock Source Selection 20 3 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK1 #010 3 Clock source from external clock TM3 pin #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #101 7 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #111 UART0SEL UART0 Clock Source Selection 24 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #10 3 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #11 UART1SEL UART1 Clock Source Selection 26 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #10 3 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #11 WDTSEL Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 0 2 read-write 0 Reserved #00 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #01 2 Clock source from HCLK/2048 #10 3 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #11 WWDTSEL Window Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 30 2 read-write 2 Clock source from HCLK/2048 #10 3 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #11 CLKSEL2 CLK_CLKSEL2 Clock Source Select Control Register 2 0x18 -1 read-write n 0x0 0x0 BPWM0SEL BPWM0 Clock Source Selection (Read Only)\nThe peripheral clock source of BPWM0 is defined by BPWM0SEL. 8 1 read-only 1 Clock source from PCLK0 #1 BPWM1SEL BPWM1 Clock Source Selection (Read Only)\nThe peripheral clock source of BPWM1 is defined by BPWM1SEL. 9 1 read-only 1 Clock source from PCLK1 #1 EPWM0SEL EPWM0 Clock Source Selection (Read Only)\nThe peripheral clock source of EPWM0 is defined by EPWM0SEL. 0 1 read-only 1 Clock source from PCLK0 #1 EPWM1SEL EPWM1 Clock Source Selection (Read Only)\nThe peripheral clock source of EPWM1 is defined by EPWM1SEL. 1 1 read-only 1 Clock source from PCLK1 #1 QSPI0SEL QSPI0 Clock Source Selection 2 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from PCLK0 #10 3 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #11 SPI0SEL SPI0 Clock Source Selection 4 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from PCLK1 #10 3 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #11 SPI1SEL SPI1 Clock Source Selection 6 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from PCLK0 #10 3 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #11 SPI2SEL SPI2 Clock Source Selection 10 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from PCLK1 #10 3 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #11 SPI3SEL SPI3 Clock Source Selection 12 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from PCLK0 #10 3 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #11 CLKSEL3 CLK_CLKSEL3 Clock Source Select Control Register 3 0x1C -1 read-write n 0x0 0x0 I2S0SEL I2S0 Clock Source Selection 16 2 read-write 0 Clock source from HXT clock #00 1 Clock source from PLL clock #01 2 Clock source from PCLK0 #10 3 Clock source from HIRC clock #11 RTCSEL RTC Clock Source Selection 8 1 read-write 0 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #0 1 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #1 SC0SEL Smart Card 0 (SC0) Clock Source Selection 0 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from PCLK0 #10 3 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #11 SC1SEL Smart Card 1 (SC1) Clock Source Selection 2 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from PCLK1 #10 3 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #11 SC2SEL Smart Card 2 (SC2) Clock Source Selection 4 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from PCLK0 #10 3 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #11 UART2SEL UART2 Clock Source Selection 24 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #10 3 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #11 UART3SEL UART3 Clock Source Selection 26 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #10 3 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #11 UART4SEL UART4 Clock Source Selection 28 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #10 3 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #11 UART5SEL UART5 Clock Source Selection 30 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #10 3 Clock source from 12 MHz internal high speed RC oscillator (HIRC) #11 HXTFSEL CLK_HXTFSEL HXT Filter Select Control Register 0xB4 read-write n 0x0 0x0 HXTFSEL HXT Filter Select 0 1 read-write 0 HXT frequency is larger than 12 MHz #0 1 HXT frequency is less than or equal to 12 MHz #1 IOPDCTL CLK_IOPDCTL GPIO Standby Power-down Control Register 0xB0 read-write n 0x0 0x0 IOHR GPIO Hold Release\nWhen GPIO enters standby power-down mode, all I/O status are hold to keep normal operating status. After chip was waked up from standby power-down mode, the I/O still keeps hold status until user sets this bit to release I/O hold status.\nNote: This bit is auto cleared by hardware. 0 1 read-write PASWKCTL CLK_PASWKCTL GPA Standby Power-down Wake-up Control Register 0xA0 read-write n 0x0 0x0 DBEN GPA Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC).\nThe de-bounce function is valid only for edge triggered. 8 1 read-write 0 Standby power-down wake-up pin De-bounce function Disabled #0 1 Standby power-down wake-up pin De-bounce function Enabled #1 PFWKEN Pin Falling Edge Wake-up Enable Bit 2 1 read-write 0 GPA group pin falling edge wake-up function Disabled #0 1 GPA group pin falling edge wake-up function Enabled #1 PRWKEN Pin Rising Edge Wake-up Enable Bit 1 1 read-write 0 GPA group pin rising edge wake-up function Disabled #0 1 GPA group pin rising edge wake-up function Enabled #1 WKEN Standby Power-down Pin Wake-up Enable Bit 0 1 read-write 0 GPA group pin wake-up function Disabled #0 1 GPA group pin wake-up function Enabled #1 WKPSEL GPA Standby Power-down Wake-up Pin Select 4 4 read-write 0 GPA.0 wake-up function enabled #0000 1 GPA.1 wake-up function enabled #0001 2 GPA.2 wake-up function enabled #0010 3 GPA.3 wake-up function enabled #0011 4 GPA.4 wake-up function enabled #0100 5 GPA.5 wake-up function enabled #0101 6 GPA.6 wake-up function enabled #0110 7 GPA.7 wake-up function enabled #0111 8 GPA.8 wake-up function enabled #1000 9 GPA.9 wake-up function enabled #1001 10 GPA.10 wake-up function enabled #1010 11 GPA.11 wake-up function enabled #1011 12 GPA.12 wake-up function enabled #1100 13 GPA.13 wake-up function enabled #1101 14 GPA.14 wake-up function enabled #1110 15 GPA.15 wake-up function enabled #1111 PBSWKCTL CLK_PBSWKCTL GPB Standby Power-down Wake-up Control Register 0xA4 read-write n 0x0 0x0 DBEN GPB Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC).\nThe de-bounce function is valid only for edge triggered. 8 1 read-write 0 Standby power-down wake-up pin De-bounce function Disabled #0 1 Standby power-down wake-up pin De-bounce function Enabled #1 PFWKEN Pin Falling Edge Wake-up Enable Bit 2 1 read-write 0 GPB group pin falling edge wake-up function Disabled #0 1 GPB group pin falling edge wake-up function Enabled #1 PRWKEN Pin Rising Edge Wake-up Enable Bit 1 1 read-write 0 GPB group pin rising edge wake-up function Disabled #0 1 GPB group pin rising edge wake-up function Enabled #1 WKEN Standby Power-down Pin Wake-up Enable Bit 0 1 read-write 0 GPB group pin wake-up function Disabled #0 1 GPB group pin wake-up function Enabled #1 WKPSEL GPB Standby Power-down Wake-up Pin Select 4 4 read-write 0 GPB.0 wake-up function enabled #0000 1 GPB.1 wake-up function enabled #0001 2 GPB.2 wake-up function enabled #0010 3 GPB.3 wake-up function enabled #0011 4 GPB.4 wake-up function enabled #0100 5 GPB.5 wake-up function enabled #0101 6 GPB.6 wake-up function enabled #0110 7 GPB.7 wake-up function enabled #0111 8 GPB.8 wake-up function enabled #1000 9 GPB.9 wake-up function enabled #1001 10 GPB.10 wake-up function enabled #1010 11 GPB.11 wake-up function enabled #1011 12 GPB.12 wake-up function enabled #1100 13 GPB.13 wake-up function enabled #1101 14 GPB.14 wake-up function enabled #1110 15 GPB.15 wake-up function enabled #1111 PCLKDIV CLK_PCLKDIV APB Clock Divider Register 0x34 read-write n 0x0 0x0 APB0DIV APB0 Clock Divider\nAPB0 clock can be divided from HCLK 0 3 read-write 0 PCLK0 frequency is HCLK #000 1 PCLK0 frequency is 1/2 HCLK #001 2 PCLK0 frequency is 1/4 HCLK #010 3 PCLK0 frequency is 1/8 HCLK #011 4 PCLK0 frequency is 1/16 HCLK #100 5 PCLK0 frequency is 1/32 HCLK #101 APB1DIV APB1 Clock Divider\nAPB1 clock can be divided from HCLK 4 3 read-write 0 PCLK1 frequency is HCLK #000 1 PCLK1 frequency is 1/2 HCLK #001 2 PCLK1 frequency is 1/4 HCLK #010 3 PCLK1 frequency is 1/8 HCLK #011 4 PCLK1 frequency is 1/16 HCLK #100 5 PCLK1 frequency is 1/32 HCLK #101 PCSWKCTL CLK_PCSWKCTL GPC Standby Power-down Wake-up Control Register 0xA8 read-write n 0x0 0x0 DBEN GPC Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. The de-bounce clock source is the 10 kHz internal low speed RC oscillator.\nThe de-bounce function is valid only for edge triggered. 8 1 read-write 0 Standby power-down wake-up pin De-bounce function Disabled #0 1 Standby power-down wake-up pin De-bounce function Enabled #1 PFWKEN Pin Falling Edge Wake-up Enable Bit 2 1 read-write 0 GPC group pin falling edge wake-up function Disabled #0 1 GPC group pin falling edge wake-up function Enabled #1 PRWKEN Pin Rising Edge Wake-up Enable Bit 1 1 read-write 0 GPC group pin rising edge wake-up function Disabled #0 1 GPC group pin rising edge wake-up function Enabled #1 WKEN Standby Power-down Pin Wake-up Enable Bit 0 1 read-write 0 GPC group pin wake-up function Disabled #0 1 GPC group pin wake-up function Enabled #1 WKPSEL GPC Standby Power-down Wake-up Pin Select 4 4 read-write 0 GPC.0 wake-up function enabled #0000 1 GPC.1 wake-up function enabled #0001 2 GPC.2 wake-up function enabled #0010 3 GPC.3 wake-up function enabled #0011 4 GPC.4 wake-up function enabled #0100 5 GPC.5 wake-up function enabled #0101 6 GPC.6 wake-up function enabled #0110 7 GPC.7 wake-up function enabled #0111 8 GPC.8 wake-up function enabled #1000 9 GPC.9 wake-up function enabled #1001 10 GPC.10 wake-up function enabled #1010 11 GPC.11 wake-up function enabled #1011 12 GPC.12 wake-up function enabled #1100 13 GPC.13 wake-up function enabled #1101 14 Reserved #1110 15 Reserved #1111 PDSWKCTL CLK_PDSWKCTL GPD Standby Power-down Wake-up Control Register 0xAC read-write n 0x0 0x0 DBEN GPD Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. The de-bounce clock source is the 10 kHz internal low speed RC oscillator.\nThe de-bounce function is valid only for edge triggered. 8 1 read-write 0 Standby power-down wake-up pin De-bounce function Disabled #0 1 Standby power-down wake-up pin De-bounce function Enabled #1 PFWKEN Pin Falling Edge Wake-up Enable Bit 2 1 read-write 0 GPD group pin falling edge wake-up function Disabled #0 1 GPD group pin falling edge wake-up function Enabled #1 PRWKEN Pin Rising Edge Wake-up Enable Bit 1 1 read-write 0 GPD group pin rising edge wake-up function Disabled #0 1 GPD group pin rising edge wake-up function Enabled #1 WKEN Standby Power-down Pin Wake-up Enable Bit 0 1 read-write 0 GPD group pin wake-up function Disabled #0 1 GPD group pin wake-up function Enabled #1 WKPSEL GPD Standby Power-down Wake-up Pin Select 4 4 read-write 0 GPD.0 wake-up function enabled #0000 1 GPD.1 wake-up function enabled #0001 2 GPD.2 wake-up function enabled #0010 3 GPD.3 wake-up function enabled #0011 4 GPD.4 wake-up function enabled #0100 5 GPD.5 wake-up function enabled #0101 6 GPD.6 wake-up function enabled #0110 7 GPD.7 wake-up function enabled #0111 8 GPD.8 wake-up function enabled #1000 9 GPD.9 wake-up function enabled #1001 10 GPD.10 wake-up function enabled #1010 11 GPD.11 wake-up function enabled #1011 12 GPD.12 wake-up function enabled #1100 13 GPD.13 wake-up function enabled #1101 14 GPD.14 wake-up function enabled #1110 15 Reserved #1111 PLLCTL CLK_PLLCTL PLL Control Register 0x40 -1 read-write n 0x0 0x0 BP PLL Bypass Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 17 1 read-write 0 PLL is in normal mode (default) #0 1 PLL clock output is same as PLL input clock FIN #1 FBDIV PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 0 9 read-write INDIV PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 9 5 read-write OE PLL OE (FOUT Enable) Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 18 1 read-write 0 PLL FOUT Enabled #0 1 PLL FOUT is fixed low #1 OUTDIV PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 14 2 read-write PD Power-down Mode (Write Protect)\nNote1: If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register 16 1 read-write 0 PLL is enable (in normal mode) #0 1 PLL is disable (in Power-down mode) (default) #1 PLLSRC PLL Source Clock Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 19 1 read-write 0 PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT) #0 1 PLL source clock from 12 MHz internal high-speed oscillator (HIRC) #1 STBSEL PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 23 1 read-write 0 PLL stable time is 1200 PLL source clock (suitable for source clock is equal to or less than 12 MHz) #0 1 PLL stable time is 2400 PLL source clock (suitable for source clock is larger than 12 MHz) #1 PMUCTL CLK_PMUCTL Power Manager Control Register 0x90 read-write n 0x0 0x0 ACMPSPWK ACMP Standby Power-down Mode Wake-up Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 18 1 read-write 0 ACMP wake-up Disabled in Standby Power-down mode #0 1 ACMP wake-up Enabled in Standby Power-down mode #1 PDMSEL Power-down Mode Selection (Write Protect)\nThese bits control chip Power-down mode grade selection when CPU executes WFI/WFE instruction.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 0 3 read-write 0 Power-down mode is selected (PD) #000 1 Low leakage Power-down mode is selected (LLPD) #001 2 Fast wake-up Power-down (FWPD) #010 3 Ultra low leakage Power-down mode is selected (ULLPD) #011 4 Standby Power-down mode is selected (SPD) #100 5 Reserved #101 6 Deep Power-down mode is selected (DPD) #110 7 Reserved #111 RTCWKEN RTC Wake-up Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 23 1 read-write 0 RTC wake-up Disabled in Deep Power-down mode or Standby Power-down mode #0 1 RTC wake-up Enabled at Deep Power-down mode or Standby Power-down mode #1 WKPINEN Wake-up Pin Enable (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 16 2 read-write 0 Wake-up pin Disabled in Deep Power-down mode #00 1 Wake-up pin rising edge Enabled in Deep Power-down mode #01 2 Wake-up pin falling edge Enabled in Deep Power-down mode #10 3 Wake-up pin both edge Enabled in Deep Power-down mode #11 WKTMREN Wake-up Timer Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 8 1 read-write 0 Wake-up timer disabled at Deep Power-down mode or Standby Power-down mode #0 1 Wake-up timer enabled at Deep Power-down mode or Standby Power-down mode #1 WKTMRIS Wake-up Timer Time-out Interval Select (Write Protect)\nThese bits control wake-up timer time-out interval when chip is under Deep Power-down mode or Standby Power-down mode.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 9 3 read-write 0 Time-out interval is 128 OSC10K clocks (12.8ms) #000 1 Time-out interval is 256 OSC10K clocks (25.6ms) #001 2 Time-out interval is 512 OSC10K clocks (51.2ms) #010 3 Time-out interval is 1024 OSC10K clocks (102.4ms) #011 4 Time-out interval is 4096 OSC10K clocks (409.6ms) #100 5 Time-out interval is 8192 OSC10K clocks (819.2ms) #101 6 Time-out interval is 16384 OSC10K clocks (1638.4ms) #110 7 Time-out interval is 65536 OSC10K clocks (6553.6ms) #111 PMUSTS CLK_PMUSTS Power Manager Status Register 0x94 read-write n 0x0 0x0 ACMPWK ACMP Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition. This flag is cleared when SPD mode is entered. 14 1 read-only BODWK BOD Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened. This flag is cleared when SPD mode is entered. 13 1 read-only CLRWK Clear Wake-up Flage\nNote: This bit is auto cleared by hardware. 31 1 read-write 0 No clear #0 1 Clear all of wake-up flag #1 GPAWK GPA Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPA group pins. This flag is cleared when SPD mode is entered. 8 1 read-only GPBWK GPB Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPB group pins. This flag is cleared when SPD mode is entered. 9 1 read-only GPCWK GPC Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPC group pins. This flag is cleared when SPD mode is entered. 10 1 read-only GPDWK GPD Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPD group pins. This flag is cleared when SPD mode is entered. 11 1 read-only LVRWK LVR Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a LVR happened. This flag is cleared when SPD mode is entered. 12 1 read-only PINWK Pin Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPC.0). This flag is cleared when DPD mode is entered. 0 1 read-only RTCWK RTC Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened. This flag is cleared when DPD or SPD mode is entered. 2 1 read-only TMRWK Timer Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out. This flag is cleared when DPD or SPD mode is entered. 1 1 read-only PWRCTL CLK_PWRCTL System Power-down Control Register 0x0 read-write n 0x0 0x0 HIRC48EN HIRC48 Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 18 1 read-write 0 48 MHz internal high speed RC oscillator (HIRC48) Disabled #0 1 48 MHz internal high speed RC oscillator (HIRC48) Enabled #1 HIRCEN HIRC Enable Bit (Write Protect)\nThe HCLK default clock source is from HIRC and this bit default value is 1.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: HIRC cannot be disabled and HIRCEN will always read as 1 if Flash access cycle auto-tuning function is enabled or HCLK clock source is selected from HIRC or PLL (clock source from HIRC). Flash access cycle auto-tuning function can be disabled by setting FADIS (FMC_CYCCTL[8]). 2 1 read-write 0 12 MHz internal high speed RC oscillator (HIRC) Disabled #0 1 12 MHz internal high speed RC oscillator (HIRC) Enabled #1 HXTEN HXT Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: HXT cannot be disabled and HXTEN will always read as 1 if HCLK clock source is selected from HXT or PLL (clock source from HXT). 0 1 read-write 0 4~24 MHz external high speed crystal (HXT) Disabled #0 1 4~24 MHz external high speed crystal (HXT) Enabled #1 HXTGAIN HXT Gain Control Bit (Write Protect)\nGain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. \nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 10 2 read-write 0 HXT frequency is lower than from 8 MHz #00 1 HXT frequency is from 8 MHz to 12 MHz #01 2 HXT frequency is from 12 MHz to 16 MHz #10 3 HXT frequency is higher than 16 MHz #11 HXTSELTYP HXT Crystal Type Select Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 12 1 read-write 0 Select INV type #0 1 Select GM type #1 HXTTBEN HXT Crystal TURBO Mode (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 13 1 read-write 0 HXT Crystal TURBO mode disabled #0 1 HXT Crystal TURBO mode enabled #1 LIRCEN LIRC Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: LIRC cannot be disabled and LIRCEN will always read as 1 if HCLK clock source is selected from LIRC.\nNote3: If CWDTEN(CONFIG[31,4:3]) is set to 111, LIRC clock can be enabled or disabled by setting LIRCEN(CLK_PWRCTL[3]).\nIf CWDTEN([31,4:3]) is not set to 111, LIRC cannot be disabled in normal mode. In Power-down mode, LIRC clock is controlled by LIRCEN(CLK_PWRCTL[3]) and CWDTPDEN(CONFIG[30]) setting. 3 1 read-write 0 10 kHz internal low speed RC oscillator (LIRC) Disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) Enabled #1 LXTEN LXT Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: LXT cannot be disabled and LXTEN will always read as 1 if HCLK clock source is selected from LXT when the LXT clock source is selected as extLXT by setting C32KS(RTC_LXTCTL[7]) to 1. 1 1 read-write 0 32.768 kHz external low speed crystal (extLXT) Disabled #0 1 32.768 kHz external low speed crystal (extLXT) Enabled #1 PDEN System Power-down Enable (Write Protect)\nWhen this bit is set to 1, Power-down mode is enabled and the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.\nWhen chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.\nIn Power-down mode, HXT, HIRC, HIRC48, PLL and system clock will be disabled and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Chip operating normally or chip in idle mode because of WFI command #0 1 Chip waits CPU sleep command WFI and then enters Power-down mode #1 PDWKIEN Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PDWKIF and PDWKIEN are high, after resume from Power-down mode.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 Power-down mode wake-up interrupt Disabled #0 1 Power-down mode wake-up interrupt Enabled #1 PDWKIF Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event', it indicates that resume from Power-down mode' \nThe flag is set if the EINT7~0, GPIO, UART0~5, USBH, USBD, OTG, CAN0, BOD, ACMP, WDT, SDH0, TMR0~3, I2C0~2, USCI0~1, SPI4, , RTC wake-up occurred.\nNote1: Write 1 to clear the bit to 0.\nNote2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. 6 1 read-write STATUS CLK_STATUS Clock Status Monitor Register 0x50 read-only n 0x0 0x0 CLKSFAIL Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote: This bit is read only. After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware. 7 1 read-only 0 Clock switching success #0 1 Clock switching failure #1 EXTLXTSTB EXTLXT Clock Source Stable Flag (Read Only) 8 1 read-only 0 32.768 kHz external low speed crystal oscillator (extLXT) clock is not stable or disabled #0 1 32.768 kHz external low speed crystal oscillator (extLXT) clock is stable and enabled #1 HIRC48STB HIRC48 Clock Source Stable Flag (Read Only) 6 1 read-only 0 48 MHz internal high speed RC oscillator (HIRC48) clock is not stable or disabled #0 1 48 MHz internal high speed RC oscillator (HIRC48) clock is stable and enabled #1 HIRCSTB HIRC Clock Source Stable Flag (Read Only) 4 1 read-only 0 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled #0 1 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled #1 HXTSTB HXT Clock Source Stable Flag (Read Only) 0 1 read-only 0 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled #1 LIRC32STB LIRC32 Clock Source Stable Flag (Read Only) 9 1 read-only 0 32 kHz internal low speed RC oscillator (LIRC32) clock is not stable or disabled #0 1 32 kHz internal low speed RC oscillator (LIRC32) clock is stable and enabled #1 LIRCSTB LIRC Clock Source Stable Flag (Read Only) 3 1 read-only 0 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled #1 LXTSTB LXT Clock Source Stable Flag (Read Only)\nLXT clock source can be selected as extLXT or LIRC32 by setting C32KS(RTC_LXTCTL[7]). If C32KS is set to 0, the LXT stable flag is set when extLXT clock source is stable. If C32KS is set to 1, the LXT stable flag is set when LIRC32 clock source is stable. 1 1 read-only 0 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled #1 PLLSTB Internal PLL Clock Source Stable Flag (Read Only) 2 1 read-only 0 Internal PLL clock is not stable or disabled #0 1 Internal PLL clock is stable and enabled #1 SWKDBCTL CLK_SWKDBCTL Standby Power-down Wake-up De-bounce Control Register 0x9C read-write n 0x0 0x0 SWKDBCLKSEL Standby Power-down Wake-up De-bounce Sampling Cycle Selection\nNote: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). 0 4 read-write 0 Sample wake-up input once per 1 clocks #0000 1 Sample wake-up input once per 2 clocks #0001 2 Sample wake-up input once per 4 clocks #0010 3 Sample wake-up input once per 8 clocks #0011 4 Sample wake-up input once per 16 clocks #0100 5 Sample wake-up input once per 32 clocks #0101 6 Sample wake-up input once per 64 clocks #0110 7 Sample wake-up input once per 128 clocks #0111 8 Sample wake-up input once per 256 clocks #1000 9 Sample wake-up input once per 2*256 clocks #1001 10 Sample wake-up input once per 4*256 clocks #1010 11 Sample wake-up input once per 8*256 clocks #1011 12 Sample wake-up input once per 16*256 clocks #1100 13 Sample wake-up input once per 32*256 clocks #1101 14 Sample wake-up input once per 64*256 clocks #1110 15 Sample wake-up input once per 128*256 clocks #1111 CRC CRC Register Map CRC 0x0 0x0 0x10 registers n CHECKSUM CRC_CHECKSUM CRC Checksum Register 0xC -1 read-only n 0x0 0x0 CHECKSUM CRC Checksum Results\nThis field indicates the CRC checksum result. 0 32 read-only CTL CRC_CTL CRC Control Register 0x0 -1 read-write n 0x0 0x0 CHKSFMT Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. 27 1 read-write 0 1's complement for CRC checksum Disabled #0 1 1's complement for CRC checksum Enabled #1 CHKSINIT Checksum Initialization\nNote: This bit will be cleared automatically. 1 1 read-write 0 No effect #0 1 Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value #1 CHKSREV Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB. 25 1 read-write 0 Bit order reverse for CRC checksum Disabled #0 1 Bit order reverse for CRC checksum Enabled #1 CRCEN CRC Channel Enable Bit 0 1 read-write 0 No effect #0 1 CRC operation Enabled #1 CRCMODE CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode. 30 2 read-write 0 CRC-CCITT Polynomial mode #00 1 CRC-8 Polynomial mode #01 2 CRC-16 Polynomial mode #10 3 CRC-32 Polynomial mode #11 DATFMT Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DAT register. 26 1 read-write 0 1's complement for CRC writes data in Disabled #0 1 1's complement for CRC writes data in Enabled #1 DATLEN CPU Write Data Length This field indicates the write data length. Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. 28 2 read-write 0 Data length is 8-bit mode #00 1 Data length is 16-bit mode.\nData length is 32-bit mode #01 DATREV Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB. 24 1 read-write 0 Bit order reversed for CRC write data in Disabled #0 1 Bit order reversed for CRC write data in Enabled (per byte) #1 DAT CRC_DAT CRC Write Data Register 0x4 read-write n 0x0 0x0 DATA CRC Write Data Bits User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. 0 32 read-write SEED CRC_SEED CRC Seed Register 0x8 -1 read-write n 0x0 0x0 SEED CRC Seed Value\nThis field indicates the CRC seed value.\nNote: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]). 0 32 read-write CRYPTO CRYPTO Register Map CRYPTO 0x0 0x0 0x30 registers n 0x100 0x13C registers n 0x248 0x2C registers n 0x288 0x2C registers n 0x2C8 0x2C registers n 0x300 0x38 registers n 0x348 0x10 registers n 0x50 0x18 registers n 0x800 0x258 registers n AES0_CNT CRYPTO_AES0_CNT AES Byte Count Register for Channel 0 0x148 read-write n 0x0 0x0 CNT AES Byte Count\nThe CRYPTO_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode. The CRYPTO_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\nCRYPTO_AESn_CNT can be read and written. Writing to CRYPTO_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation. But the value of CRYPTO_AESn_CNT will be updated later on. Consequently, software can prepare the byte count of data for the next AES operation.\nAccording to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes. Operations that are qual or less than one block will output unexpected result.\nIn Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRYPTO_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRYPTO_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. 0 32 read-write AES0_DADDR CRYPTO_AES0_DADDR AES DMA Destination Address Register for Channel 0 0x144 read-write n 0x0 0x0 DADDR AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO. The DADDR keeps the destination address of the data buffer where the engine output's text will be stored. Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished. The start of destination address should be located at word boundary. In other words, bit 1 and 0 of DADDR are ignored.\nDADDR can be read and written. Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of DADDR will be updated later on. Consequently, software can prepare the destination address for the next AES operation.\nIn DMA mode, software can update the next CRYPTO_AESn_DADDR before triggering START. \nThe value of CRYPTO_AESn_SADDR and CRYPTO_AESn_DADDR can be the same. 0 32 read-write AES0_IV0 CRYPTO_AES0_IV0 AES Initial Vector Word 0 Register for Channel 0 0x130 read-write n 0x0 0x0 IV AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0, CRYPTO_AESn_IV1, CRYPTO_AESn_IV2, and CRYPTO_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode. Four registers (CRYPTO_AESn_IV0, CRYPTO_AESn_IV1, CRYPTO_AESn_IV2, and CRYPTO_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. 0 32 read-write AES0_IV1 CRYPTO_AES0_IV1 AES Initial Vector Word 1 Register for Channel 0 0x134 read-write n 0x0 0x0 AES0_IV2 CRYPTO_AES0_IV2 AES Initial Vector Word 2 Register for Channel 0 0x138 read-write n 0x0 0x0 AES0_IV3 CRYPTO_AES0_IV3 AES Initial Vector Word 3 Register for Channel 0 0x13C read-write n 0x0 0x0 AES0_KEY0 CRYPTO_AES0_KEY0 AES Key Word 0 Register for Channel 0 0x110 read-write n 0x0 0x0 KEY CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. {CRYPTO_AESn_KEY3, CRYPTO_AESn_KEY2, CRYPTO_AESn_KEY1, CRYPTO_AESn_KEY0} stores the 128-bit security key for AES operation. {CRYPTO_AESn_KEY5, CRYPTO_AESn_KEY4, CRYPTO_AESn_KEY3, CRYPTO_AESn_KEY2, CRYPTO_AESn_KEY1, CRYPTO_AESn_KEY0} stores the 192-bit security key for AES operation. {CRYPTO_AESn_KEY7, CRYPTO_AESn_KEY6, CRYPTO_AESn_KEY5, CRYPTO_AESn_KEY4, CRYPTO_AESn_KEY3, CRYPTO_AESn_KEY2, CRYPTO_AESn_KEY1, CRYPTO_AESn_KEY0} stores the 256-bit security key for AES operation. 0 32 read-write AES0_KEY1 CRYPTO_AES0_KEY1 AES Key Word 1 Register for Channel 0 0x114 read-write n 0x0 0x0 AES0_KEY2 CRYPTO_AES0_KEY2 AES Key Word 2 Register for Channel 0 0x118 read-write n 0x0 0x0 AES0_KEY3 CRYPTO_AES0_KEY3 AES Key Word 3 Register for Channel 0 0x11C read-write n 0x0 0x0 AES0_KEY4 CRYPTO_AES0_KEY4 AES Key Word 4 Register for Channel 0 0x120 read-write n 0x0 0x0 AES0_KEY5 CRYPTO_AES0_KEY5 AES Key Word 5 Register for Channel 0 0x124 read-write n 0x0 0x0 AES0_KEY6 CRYPTO_AES0_KEY6 AES Key Word 6 Register for Channel 0 0x128 read-write n 0x0 0x0 AES0_KEY7 CRYPTO_AES0_KEY7 AES Key Word 7 Register for Channel 0 0x12C read-write n 0x0 0x0 AES0_SADDR CRYPTO_AES0_SADDR AES DMA Source Address Register for Channel 0 0x140 read-write n 0x0 0x0 SADDR AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (descryption) from SRAM memory space and do AES operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of SADDR are ignored.\nSADDR can be read and written. Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next AES operation.\nIn DMA mode, software can update the next CRYPTO_AESn_SADDR before triggering START.\nThe value of CRYPTO_AESn_SADDR and CRYPTO_AESn_DADDR can be the same. 0 32 read-write AES1_CNT CRYPTO_AES1_CNT AES Byte Count Register for Channel 1 0x184 read-write n 0x0 0x0 AES1_DADDR CRYPTO_AES1_DADDR AES DMA Destination Address Register for Channel 1 0x180 read-write n 0x0 0x0 AES1_IV0 CRYPTO_AES1_IV0 AES Initial Vector Word 0 Register for Channel 1 0x16C read-write n 0x0 0x0 AES1_IV1 CRYPTO_AES1_IV1 AES Initial Vector Word 1 Register for Channel 1 0x170 read-write n 0x0 0x0 AES1_IV2 CRYPTO_AES1_IV2 AES Initial Vector Word 2 Register for Channel 1 0x174 read-write n 0x0 0x0 AES1_IV3 CRYPTO_AES1_IV3 AES Initial Vector Word 3 Register for Channel 1 0x178 read-write n 0x0 0x0 AES1_KEY0 CRYPTO_AES1_KEY0 AES Key Word 0 Register for Channel 1 0x14C read-write n 0x0 0x0 AES1_KEY1 CRYPTO_AES1_KEY1 AES Key Word 1 Register for Channel 1 0x150 read-write n 0x0 0x0 AES1_KEY2 CRYPTO_AES1_KEY2 AES Key Word 2 Register for Channel 1 0x154 read-write n 0x0 0x0 AES1_KEY3 CRYPTO_AES1_KEY3 AES Key Word 3 Register for Channel 1 0x158 read-write n 0x0 0x0 AES1_KEY4 CRYPTO_AES1_KEY4 AES Key Word 4 Register for Channel 1 0x15C read-write n 0x0 0x0 AES1_KEY5 CRYPTO_AES1_KEY5 AES Key Word 5 Register for Channel 1 0x160 read-write n 0x0 0x0 AES1_KEY6 CRYPTO_AES1_KEY6 AES Key Word 6 Register for Channel 1 0x164 read-write n 0x0 0x0 AES1_KEY7 CRYPTO_AES1_KEY7 AES Key Word 7 Register for Channel 1 0x168 read-write n 0x0 0x0 AES1_SADDR CRYPTO_AES1_SADDR AES DMA Source Address Register for Channel 1 0x17C read-write n 0x0 0x0 AES2_CNT CRYPTO_AES2_CNT AES Byte Count Register for Channel 2 0x1C0 read-write n 0x0 0x0 AES2_DADDR CRYPTO_AES2_DADDR AES DMA Destination Address Register for Channel 2 0x1BC read-write n 0x0 0x0 AES2_IV0 CRYPTO_AES2_IV0 AES Initial Vector Word 0 Register for Channel 2 0x1A8 read-write n 0x0 0x0 AES2_IV1 CRYPTO_AES2_IV1 AES Initial Vector Word 1 Register for Channel 2 0x1AC read-write n 0x0 0x0 AES2_IV2 CRYPTO_AES2_IV2 AES Initial Vector Word 2 Register for Channel 2 0x1B0 read-write n 0x0 0x0 AES2_IV3 CRYPTO_AES2_IV3 AES Initial Vector Word 3 Register for Channel 2 0x1B4 read-write n 0x0 0x0 AES2_KEY0 CRYPTO_AES2_KEY0 AES Key Word 0 Register for Channel 2 0x188 read-write n 0x0 0x0 AES2_KEY1 CRYPTO_AES2_KEY1 AES Key Word 1 Register for Channel 2 0x18C read-write n 0x0 0x0 AES2_KEY2 CRYPTO_AES2_KEY2 AES Key Word 2 Register for Channel 2 0x190 read-write n 0x0 0x0 AES2_KEY3 CRYPTO_AES2_KEY3 AES Key Word 3 Register for Channel 2 0x194 read-write n 0x0 0x0 AES2_KEY4 CRYPTO_AES2_KEY4 AES Key Word 4 Register for Channel 2 0x198 read-write n 0x0 0x0 AES2_KEY5 CRYPTO_AES2_KEY5 AES Key Word 5 Register for Channel 2 0x19C read-write n 0x0 0x0 AES2_KEY6 CRYPTO_AES2_KEY6 AES Key Word 6 Register for Channel 2 0x1A0 read-write n 0x0 0x0 AES2_KEY7 CRYPTO_AES2_KEY7 AES Key Word 7 Register for Channel 2 0x1A4 read-write n 0x0 0x0 AES2_SADDR CRYPTO_AES2_SADDR AES DMA Source Address Register for Channel 2 0x1B8 read-write n 0x0 0x0 AES3_CNT CRYPTO_AES3_CNT AES Byte Count Register for Channel 3 0x1FC read-write n 0x0 0x0 AES3_DADDR CRYPTO_AES3_DADDR AES DMA Destination Address Register for Channel 3 0x1F8 read-write n 0x0 0x0 AES3_IV0 CRYPTO_AES3_IV0 AES Initial Vector Word 0 Register for Channel 3 0x1E4 read-write n 0x0 0x0 AES3_IV1 CRYPTO_AES3_IV1 AES Initial Vector Word 1 Register for Channel 3 0x1E8 read-write n 0x0 0x0 AES3_IV2 CRYPTO_AES3_IV2 AES Initial Vector Word 2 Register for Channel 3 0x1EC read-write n 0x0 0x0 AES3_IV3 CRYPTO_AES3_IV3 AES Initial Vector Word 3 Register for Channel 3 0x1F0 read-write n 0x0 0x0 AES3_KEY0 CRYPTO_AES3_KEY0 AES Key Word 0 Register for Channel 3 0x1C4 read-write n 0x0 0x0 AES3_KEY1 CRYPTO_AES3_KEY1 AES Key Word 1 Register for Channel 3 0x1C8 read-write n 0x0 0x0 AES3_KEY2 CRYPTO_AES3_KEY2 AES Key Word 2 Register for Channel 3 0x1CC read-write n 0x0 0x0 AES3_KEY3 CRYPTO_AES3_KEY3 AES Key Word 3 Register for Channel 3 0x1D0 read-write n 0x0 0x0 AES3_KEY4 CRYPTO_AES3_KEY4 AES Key Word 4 Register for Channel 3 0x1D4 read-write n 0x0 0x0 AES3_KEY5 CRYPTO_AES3_KEY5 AES Key Word 5 Register for Channel 3 0x1D8 read-write n 0x0 0x0 AES3_KEY6 CRYPTO_AES3_KEY6 AES Key Word 6 Register for Channel 3 0x1DC read-write n 0x0 0x0 AES3_KEY7 CRYPTO_AES3_KEY7 AES Key Word 7 Register for Channel 3 0x1E0 read-write n 0x0 0x0 AES3_SADDR CRYPTO_AES3_SADDR AES DMA Source Address Register for Channel 3 0x1F4 read-write n 0x0 0x0 AES_CTL CRYPTO_AES_CTL AES Control Register 0x100 read-write n 0x0 0x0 CHANNEL AES Engine Working Channel 24 2 read-write 0 Current control register setting is for channel 0 #00 1 Current control register setting is for channel 1 #01 2 Current control register setting is for channel 2 #10 3 Current control register setting is for channel 3 #11 DMACSCAD AES Engine DMA with Cascade Mode 6 1 read-write 0 DMA cascade function Disabled #0 1 In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation #1 DMAEN AES Engine DMA Enable Bit\nThe AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. 7 1 read-write 0 AES DMA engine Disabled #0 1 AES_DMA engine Enabled #1 DMALAST AES Last Block\nIn DMA mode, this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.\nThis bit is always 0 when it's read back. Must be written again once START is triggered. 5 1 read-write ENCRYPTO AES Encryption/Decryption 16 1 read-write 0 AES engine executes decryption operation #0 1 AES engine executes encryption operation #1 INSWAP AES Engine Input Data Swap 23 1 read-write 0 Keep the original order #0 1 The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3} #1 KEYPRT Protect Key\nRead as a flag to reflect KEYPRT. 31 1 read-write 0 No effect #0 1 Protect the content of the AES key from reading. The return value for reading CRYPTO_AESn_KEYx is not the content of the registers CRYPTO_AESn_KEYx. Once it is set, it can be cleared by asserting KEYUNPRT. And the key content would be cleared as well #1 KEYSZ AES Key Size\nThis bit defines three different key size for AES operation.\nIf the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect. 2 2 read-write KEYUNPRT Unprotect Key\nWriting 0 to CRYPTO_AES_CTL[31] and '10110' to CRYPTO_AES_CTL[30:26] is to unprotect the AES key.\nThe KEYUNPRT can be read and written. When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. 26 5 read-write OPMODE AES Engine Operation Modes 8 8 read-write 0 ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode) 0x00 2 CFB (Cipher Feedback Mode) 0x02 3 OFB (Output Feedback Mode) 0x03 4 CTR (Counter Mode) 0x04 16 CBC-CS1 (CBC Ciphertext-Stealing 1 Mode) 0x10 17 CBC-CS2 (CBC Ciphertext-Stealing 2 Mode) 0x11 18 CBC-CS3 (CBC Ciphertext-Stealing 3 Mode) 0x12 OUTSWAP AES Engine Output Data Swap 22 1 read-write 0 Keep the original order #0 1 The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3} #1 START AES Engine Start\nNote: This bit is always 0 when it's read back. 0 1 read-write 0 No effect #0 1 Start AES engine. BUSY flag will be set #1 STOP AES Engine Stop\nNote: This bit is always 0 when it's read back. 1 1 read-write 0 No effect #0 1 Stop AES engine #1 AES_DATIN CRYPTO_AES_DATIN AES Engine Data Input Port Register 0x108 read-write n 0x0 0x0 DATIN AES Engine Input Port\nCPU feeds data to AES engine through this port by checking CRYPTO_AES_STS. Feed data as INBUFFULL is 0. 0 32 read-write AES_DATOUT CRYPTO_AES_DATOUT AES Engine Data Output Port Register 0x10C read-only n 0x0 0x0 DATOUT AES Engine Output Port\nCPU gets results from the AES engine through this port by checking CRYPTO_AES_STS. Get data as OUTBUFEMPTY is 0. 0 32 read-only AES_FDBCK0 CRYPTO_AES_FDBCK0 AES Engine Output Feedback Data after Cryptographic Operation 0x50 read-only n 0x0 0x0 FDBCK AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for IV in the next block's operation. Software can use this feedback information to implement more than four DMA channels. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to CRYPTO_AESn_IVx in the same channel operation, and then continue the operation with the original setting. 0 32 read-only AES_FDBCK1 CRYPTO_AES_FDBCK1 AES Engine Output Feedback Data after Cryptographic Operation 0x54 read-write n 0x0 0x0 AES_FDBCK2 CRYPTO_AES_FDBCK2 AES Engine Output Feedback Data after Cryptographic Operation 0x58 read-write n 0x0 0x0 AES_FDBCK3 CRYPTO_AES_FDBCK3 AES Engine Output Feedback Data after Cryptographic Operation 0x5C read-write n 0x0 0x0 AES_STS CRYPTO_AES_STS AES Engine Flag 0x104 -1 read-only n 0x0 0x0 BUSERR AES DMA Access Bus Error Flag 20 1 read-only 0 No error #0 1 Bus error will stop DMA operation and AES engine #1 BUSY AES Engine Busy 0 1 read-only 0 The AES engine is idle or finished #0 1 The AES engine is under processing #1 CNTERR CRYPTO_AESn_CNT Setting Error 12 1 read-only 0 No error in CRYPTO_AESn_CNT setting #0 1 CRYPTO_AESn_CNT is 0 or not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode if DMAEN (CRYPTO_AES_CTL[7]) is enabled #1 INBUFEMPTY AES Input Buffer Empty 8 1 read-only 0 There are some data in input buffer waiting for the AES engine to process #0 1 AES input buffer is empty. Software needs to feed data to the AES engine. Otherwise, the AES engine will be pending to wait for input data #1 INBUFERR AES Input Buffer Error Flag 10 1 read-only 0 No error #0 1 Error happens during feeding data to the AES engine #1 INBUFFULL AES Input Buffer Full Flag 9 1 read-only 0 AES input buffer is not full. Software can feed the data into the AES engine #0 1 AES input buffer is full. Software cannot feed data to the AES engine. Otherwise, the flag INBUFERR will be set to 1 #1 OUTBUFEMPTY AES Out Buffer Empty 16 1 read-only 0 AES output buffer is not empty. There are some valid data kept in output buffer #0 1 AES output buffer is empty. Software cannot get data from CRYPTO_AES_DATOUT. Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty #1 OUTBUFERR AES Out Buffer Error Flag 18 1 read-only 0 No error #0 1 Error happens during getting the result from AES engine #1 OUTBUFFULL AES Out Buffer Full Flag 17 1 read-only 0 AES output buffer is not full #0 1 AES output buffer is full, and software needs to get data from CRYPTO_AES_DATOUT. Otherwise, the AES engine will be pending since the output buffer is full #1 ECC_A_00 CRYPTO_ECC_A_00 ECC The parameter CURVEA word0 of elliptic curve 0x928 read-write n 0x0 0x0 CURVEA ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08\nFor B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12\nFor B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17\nFor P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06\nFor P-256, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11\nFor P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 0 32 read-write ECC_A_01 CRYPTO_ECC_A_01 ECC The parameter CURVEA word1 of elliptic curve 0x92C read-write n 0x0 0x0 ECC_A_02 CRYPTO_ECC_A_02 ECC The parameter CURVEA word2 of elliptic curve 0x930 read-write n 0x0 0x0 ECC_A_03 CRYPTO_ECC_A_03 ECC The parameter CURVEA word3 of elliptic curve 0x934 read-write n 0x0 0x0 ECC_A_04 CRYPTO_ECC_A_04 ECC The parameter CURVEA word4 of elliptic curve 0x938 read-write n 0x0 0x0 ECC_A_05 CRYPTO_ECC_A_05 ECC The parameter CURVEA word5 of elliptic curve 0x93C read-write n 0x0 0x0 ECC_A_06 CRYPTO_ECC_A_06 ECC The parameter CURVEA word6 of elliptic curve 0x940 read-write n 0x0 0x0 ECC_A_07 CRYPTO_ECC_A_07 ECC The parameter CURVEA word7 of elliptic curve 0x944 read-write n 0x0 0x0 ECC_A_08 CRYPTO_ECC_A_08 ECC The parameter CURVEA word8 of elliptic curve 0x948 read-write n 0x0 0x0 ECC_A_09 CRYPTO_ECC_A_09 ECC The parameter CURVEA word9 of elliptic curve 0x94C read-write n 0x0 0x0 ECC_A_10 CRYPTO_ECC_A_10 ECC The parameter CURVEA word10 of elliptic curve 0x950 read-write n 0x0 0x0 ECC_A_11 CRYPTO_ECC_A_11 ECC The parameter CURVEA word11 of elliptic curve 0x954 read-write n 0x0 0x0 ECC_A_12 CRYPTO_ECC_A_12 ECC The parameter CURVEA word12 of elliptic curve 0x958 read-write n 0x0 0x0 ECC_A_13 CRYPTO_ECC_A_13 ECC The parameter CURVEA word13 of elliptic curve 0x95C read-write n 0x0 0x0 ECC_A_14 CRYPTO_ECC_A_14 ECC The parameter CURVEA word14 of elliptic curve 0x960 read-write n 0x0 0x0 ECC_A_15 CRYPTO_ECC_A_15 ECC The parameter CURVEA word15 of elliptic curve 0x964 read-write n 0x0 0x0 ECC_A_16 CRYPTO_ECC_A_16 ECC The parameter CURVEA word16 of elliptic curve 0x968 read-write n 0x0 0x0 ECC_A_17 CRYPTO_ECC_A_17 ECC The parameter CURVEA word17 of elliptic curve 0x96C read-write n 0x0 0x0 ECC_B_00 CRYPTO_ECC_B_00 ECC The parameter CURVEB word0 of elliptic curve 0x970 read-write n 0x0 0x0 CURVEB ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08\nFor B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12\nFor B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17\nFor P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06\nFor P-256, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11\nFor P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 0 32 read-write ECC_B_01 CRYPTO_ECC_B_01 ECC The parameter CURVEB word1 of elliptic curve 0x974 read-write n 0x0 0x0 ECC_B_02 CRYPTO_ECC_B_02 ECC The parameter CURVEB word2 of elliptic curve 0x978 read-write n 0x0 0x0 ECC_B_03 CRYPTO_ECC_B_03 ECC The parameter CURVEB word3 of elliptic curve 0x97C read-write n 0x0 0x0 ECC_B_04 CRYPTO_ECC_B_04 ECC The parameter CURVEB word4 of elliptic curve 0x980 read-write n 0x0 0x0 ECC_B_05 CRYPTO_ECC_B_05 ECC The parameter CURVEB word5 of elliptic curve 0x984 read-write n 0x0 0x0 ECC_B_06 CRYPTO_ECC_B_06 ECC The parameter CURVEB word6 of elliptic curve 0x988 read-write n 0x0 0x0 ECC_B_07 CRYPTO_ECC_B_07 ECC The parameter CURVEB word7 of elliptic curve 0x98C read-write n 0x0 0x0 ECC_B_08 CRYPTO_ECC_B_08 ECC The parameter CURVEB word8 of elliptic curve 0x990 read-write n 0x0 0x0 ECC_B_09 CRYPTO_ECC_B_09 ECC The parameter CURVEB word9 of elliptic curve 0x994 read-write n 0x0 0x0 ECC_B_10 CRYPTO_ECC_B_10 ECC The parameter CURVEB word10 of elliptic curve 0x998 read-write n 0x0 0x0 ECC_B_11 CRYPTO_ECC_B_11 ECC The parameter CURVEB word11 of elliptic curve 0x99C read-write n 0x0 0x0 ECC_B_12 CRYPTO_ECC_B_12 ECC The parameter CURVEB word12 of elliptic curve 0x9A0 read-write n 0x0 0x0 ECC_B_13 CRYPTO_ECC_B_13 ECC The parameter CURVEB word13 of elliptic curve 0x9A4 read-write n 0x0 0x0 ECC_B_14 CRYPTO_ECC_B_14 ECC The parameter CURVEB word14 of elliptic curve 0x9A8 read-write n 0x0 0x0 ECC_B_15 CRYPTO_ECC_B_15 ECC The parameter CURVEB word15 of elliptic curve 0x9AC read-write n 0x0 0x0 ECC_B_16 CRYPTO_ECC_B_16 ECC The parameter CURVEB word16 of elliptic curve 0x9B0 read-write n 0x0 0x0 ECC_B_17 CRYPTO_ECC_B_17 ECC The parameter CURVEB word17 of elliptic curve 0x9B4 read-write n 0x0 0x0 ECC_CTL CRYPTO_ECC_CTL ECC Control Register 0x800 read-write n 0x0 0x0 CURVEM The key length of elliptic curve. 22 10 read-write DMAEN ECC Accelerator DMA Enable Bit\nOnly when START and DMAEN are 1, ECC DMA engine will be active 7 1 read-write 0 ECC DMA engine Disabled #0 1 ECC DMA engine Enabled #1 ECCOP Point Operation for BF and PF\nBesides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11. 9 2 read-write 0 Point multiplication : #00 1 Modulus operation : choose by MODOP (CRYPTO_ECC_CTL[12:11]) #01 2 Point addition : #10 3 Point doubling : #11 FSEL Field Selection 8 1 read-write 0 Binary Field (GF(2m )) #0 1 Prime Field (GF(p)) #1 LDA The Control Signal of Register for the Parameter CURVEA of Elliptic Curve 18 1 read-write 0 The register for CURVEA is not modified by DMA or user #0 1 The register for CURVEA is modified by DMA or user #1 LDB The Control Signal of Register for the Parameter CURVEB of Elliptic Curve 19 1 read-write 0 The register for CURVEB is not modified by DMA or user #0 1 The register for CURVEB is modified by DMA or user #1 LDK The Control Signal of Register for SCALARK 21 1 read-write 0 The register for SCALARK is not modified by DMA or user #0 1 The register for SCALARK is modified by DMA or user #1 LDN The Control Signal of Register for the Parameter CURVEN of Elliptic Curve 20 1 read-write 0 The register for CURVEN is not modified by DMA or user #0 1 The register for CURVEN is modified by DMA or user #1 LDP1 The Control Signal of Register for the X and Y Coordinate of the First Point (POINTX1, POINTY1) 16 1 read-write 0 The register for POINTX1 and POINTY1 is not modified by DMA or user #0 1 The register for POINTX1 and POINTY1 is modified by DMA or user #1 LDP2 The Control Signal of Register for the X and Y Coordinate of the Second Point (POINTX2, POINTY2) 17 1 read-write 0 The register for POINTX2 and POINTY2 is not modified by DMA or user #0 1 The register for POINTX2 and POINTY2 is modified by DMA or user #1 MODOP Modulus Operation for PF 11 2 read-write 0 Division : #00 1 Multiplication : #01 2 Addition : #10 3 Subtraction : #11 START ECC Accelerator Start\nThis bit is always 0 when it's read back.\nECC accelerator will ignore this START signal when BUSY flag is 1. 0 1 read-write 0 No effect #0 1 Start ECC accelerator. BUSY flag will be set #1 STOP ECC Accelerator Stop\nThis bit is always 0 when it's read back.\nRemember to clear ECC interrupt flag after stopping ECC accelerator. 1 1 read-write 0 No effect #0 1 Abort ECC accelerator and make it into idle state #1 ECC_DADDR CRYPTO_ECC_DADDR ECC DMA Destination Address Register 0xA4C read-write n 0x0 0x0 DADDR ECC DMA Destination Address \nThe ECC accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory and ECC accelerator. The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored. Based on the destination address, the ECC accelerator can write the result data back to SRAM memory space after the ECC operation is finished. The start of destination address should be located at word boundary. That is, bit 1 and 0 of DADDR are ignored. DADDR can be read and written. In DMA mode, software must update the CRYPTO_ECC_DADDR before triggering START. 0 32 read-write ECC_K_00 CRYPTO_ECC_K_00 ECC The scalar SCALARK word0 of point multiplication 0xA00 write-only n 0x0 0x0 SCALARK ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07\nFor B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08\nFor B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12\nFor B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17\nFor P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06\nFor P-256, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07\nFor P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11\nFor P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 0 32 write-only ECC_K_01 CRYPTO_ECC_K_01 ECC The scalar SCALARK word1 of point multiplication 0xA04 read-write n 0x0 0x0 ECC_K_02 CRYPTO_ECC_K_02 ECC The scalar SCALARK word2 of point multiplication 0xA08 read-write n 0x0 0x0 ECC_K_03 CRYPTO_ECC_K_03 ECC The scalar SCALARK word3 of point multiplication 0xA0C read-write n 0x0 0x0 ECC_K_04 CRYPTO_ECC_K_04 ECC The scalar SCALARK word4 of point multiplication 0xA10 read-write n 0x0 0x0 ECC_K_05 CRYPTO_ECC_K_05 ECC The scalar SCALARK word5 of point multiplication 0xA14 read-write n 0x0 0x0 ECC_K_06 CRYPTO_ECC_K_06 ECC The scalar SCALARK word6 of point multiplication 0xA18 read-write n 0x0 0x0 ECC_K_07 CRYPTO_ECC_K_07 ECC The scalar SCALARK word7 of point multiplication 0xA1C read-write n 0x0 0x0 ECC_K_08 CRYPTO_ECC_K_08 ECC The scalar SCALARK word8 of point multiplication 0xA20 read-write n 0x0 0x0 ECC_K_09 CRYPTO_ECC_K_09 ECC The scalar SCALARK word9 of point multiplication 0xA24 read-write n 0x0 0x0 ECC_K_10 CRYPTO_ECC_K_10 ECC The scalar SCALARK word10 of point multiplication 0xA28 read-write n 0x0 0x0 ECC_K_11 CRYPTO_ECC_K_11 ECC The scalar SCALARK word11 of point multiplication 0xA2C read-write n 0x0 0x0 ECC_K_12 CRYPTO_ECC_K_12 ECC The scalar SCALARK word12 of point multiplication 0xA30 read-write n 0x0 0x0 ECC_K_13 CRYPTO_ECC_K_13 ECC The scalar SCALARK word13 of point multiplication 0xA34 read-write n 0x0 0x0 ECC_K_14 CRYPTO_ECC_K_14 ECC The scalar SCALARK word14 of point multiplication 0xA38 read-write n 0x0 0x0 ECC_K_15 CRYPTO_ECC_K_15 ECC The scalar SCALARK word15 of point multiplication 0xA3C read-write n 0x0 0x0 ECC_K_16 CRYPTO_ECC_K_16 ECC The scalar SCALARK word16 of point multiplication 0xA40 read-write n 0x0 0x0 ECC_K_17 CRYPTO_ECC_K_17 ECC The scalar SCALARK word17 of point multiplication 0xA44 read-write n 0x0 0x0 ECC_N_00 CRYPTO_ECC_N_00 ECC The parameter CURVEN word0 of elliptic curve 0x9B8 read-write n 0x0 0x0 CURVEN ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN) In GF(p), CURVEN is the prime p. In GF(2m), CURVEN is the irreducible polynomial. For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 For P-256, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 0 32 read-write ECC_N_01 CRYPTO_ECC_N_01 ECC The parameter CURVEN word1 of elliptic curve 0x9BC read-write n 0x0 0x0 ECC_N_02 CRYPTO_ECC_N_02 ECC The parameter CURVEN word2 of elliptic curve 0x9C0 read-write n 0x0 0x0 ECC_N_03 CRYPTO_ECC_N_03 ECC The parameter CURVEN word3 of elliptic curve 0x9C4 read-write n 0x0 0x0 ECC_N_04 CRYPTO_ECC_N_04 ECC The parameter CURVEN word4 of elliptic curve 0x9C8 read-write n 0x0 0x0 ECC_N_05 CRYPTO_ECC_N_05 ECC The parameter CURVEN word5 of elliptic curve 0x9CC read-write n 0x0 0x0 ECC_N_06 CRYPTO_ECC_N_06 ECC The parameter CURVEN word6 of elliptic curve 0x9D0 read-write n 0x0 0x0 ECC_N_07 CRYPTO_ECC_N_07 ECC The parameter CURVEN word7 of elliptic curve 0x9D4 read-write n 0x0 0x0 ECC_N_08 CRYPTO_ECC_N_08 ECC The parameter CURVEN word8 of elliptic curve 0x9D8 read-write n 0x0 0x0 ECC_N_09 CRYPTO_ECC_N_09 ECC The parameter CURVEN word9 of elliptic curve 0x9DC read-write n 0x0 0x0 ECC_N_10 CRYPTO_ECC_N_10 ECC The parameter CURVEN word10 of elliptic curve 0x9E0 read-write n 0x0 0x0 ECC_N_11 CRYPTO_ECC_N_11 ECC The parameter CURVEN word11 of elliptic curve 0x9E4 read-write n 0x0 0x0 ECC_N_12 CRYPTO_ECC_N_12 ECC The parameter CURVEN word12 of elliptic curve 0x9E8 read-write n 0x0 0x0 ECC_N_13 CRYPTO_ECC_N_13 ECC The parameter CURVEN word13 of elliptic curve 0x9EC read-write n 0x0 0x0 ECC_N_14 CRYPTO_ECC_N_14 ECC The parameter CURVEN word14 of elliptic curve 0x9F0 read-write n 0x0 0x0 ECC_N_15 CRYPTO_ECC_N_15 ECC The parameter CURVEN word15 of elliptic curve 0x9F4 read-write n 0x0 0x0 ECC_N_16 CRYPTO_ECC_N_16 ECC The parameter CURVEN word16 of elliptic curve 0x9F8 read-write n 0x0 0x0 ECC_N_17 CRYPTO_ECC_N_17 ECC The parameter CURVEN word17 of elliptic curve 0x9FC read-write n 0x0 0x0 ECC_SADDR CRYPTO_ECC_SADDR ECC DMA Source Address Register 0xA48 read-write n 0x0 0x0 ECC_STARTREG CRYPTO_ECC_STARTREG ECC Starting Address of Updated Registers 0xA50 read-write n 0x0 0x0 STARTREG ECC Starting Address of Updated Registers The address of the updated registers that DMA feeds the first data or parameter to ECC engine. When ECC engine is active, ECC accelerator does not allow users to modify STARTREG, for example, to update input data from register CRYPTO_ECC POINTX1. Thus, the value of STARTREG is 0x808. 0 32 read-write ECC_STS CRYPTO_ECC_STS ECC Status Register 0x804 read-only n 0x0 0x0 BUSERR ECC DMA Access Bus Error Flag 16 1 read-only 0 No error #0 1 Bus error will stop DMA operation and ECC accelerator #1 BUSY ECC Accelerator Busy Flag\nRemember to clear ECC interrupt flag after ECC accelerator finished 0 1 read-only 0 The ECC accelerator is idle or finished #0 1 The ECC accelerator is under processing and protects all registers #1 DMABUSY ECC DMA Busy Flag 1 1 read-only 0 ECC DMA is idle or finished #0 1 ECC DMA is busy #1 ECC_WORDCNT CRYPTO_ECC_WORDCNT ECC DMA Word Count 0xA54 read-write n 0x0 0x0 WORDCNT ECC DMA Word Count \nThe CRYPTO_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode. Although CRYPTO_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144 words. CRYPTO_ECC_WORDCNT can be read and written. 0 32 read-write ECC_X1_00 CRYPTO_ECC_X1_00 ECC The X-coordinate word0 of the first point 0x808 read-write n 0x0 0x0 POINTX1 ECC the x-coordinate Value of the First Point (POINTX1) For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 For P-256, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 0 32 read-write ECC_X1_01 CRYPTO_ECC_X1_01 ECC The X-coordinate word1 of the first point 0x80C read-write n 0x0 0x0 ECC_X1_02 CRYPTO_ECC_X1_02 ECC The X-coordinate word2 of the first point 0x810 read-write n 0x0 0x0 ECC_X1_03 CRYPTO_ECC_X1_03 ECC The X-coordinate word3 of the first point 0x814 read-write n 0x0 0x0 ECC_X1_04 CRYPTO_ECC_X1_04 ECC The X-coordinate word4 of the first point 0x818 read-write n 0x0 0x0 ECC_X1_05 CRYPTO_ECC_X1_05 ECC The X-coordinate word5 of the first point 0x81C read-write n 0x0 0x0 ECC_X1_06 CRYPTO_ECC_X1_06 ECC The X-coordinate word6 of the first point 0x820 read-write n 0x0 0x0 ECC_X1_07 CRYPTO_ECC_X1_07 ECC The X-coordinate word7 of the first point 0x824 read-write n 0x0 0x0 ECC_X1_08 CRYPTO_ECC_X1_08 ECC The X-coordinate word8 of the first point 0x828 read-write n 0x0 0x0 ECC_X1_09 CRYPTO_ECC_X1_09 ECC The X-coordinate word9 of the first point 0x82C read-write n 0x0 0x0 ECC_X1_10 CRYPTO_ECC_X1_10 ECC The X-coordinate word10 of the first point 0x830 read-write n 0x0 0x0 ECC_X1_11 CRYPTO_ECC_X1_11 ECC The X-coordinate word11 of the first point 0x834 read-write n 0x0 0x0 ECC_X1_12 CRYPTO_ECC_X1_12 ECC The X-coordinate word12 of the first point 0x838 read-write n 0x0 0x0 ECC_X1_13 CRYPTO_ECC_X1_13 ECC The X-coordinate word13 of the first point 0x83C read-write n 0x0 0x0 ECC_X1_14 CRYPTO_ECC_X1_14 ECC The X-coordinate word14 of the first point 0x840 read-write n 0x0 0x0 ECC_X1_15 CRYPTO_ECC_X1_15 ECC The X-coordinate word15 of the first point 0x844 read-write n 0x0 0x0 ECC_X1_16 CRYPTO_ECC_X1_16 ECC The X-coordinate word16 of the first point 0x848 read-write n 0x0 0x0 ECC_X1_17 CRYPTO_ECC_X1_17 ECC The X-coordinate word17 of the first point 0x84C read-write n 0x0 0x0 ECC_X2_00 CRYPTO_ECC_X2_00 ECC The X-coordinate word0 of the second point 0x898 read-write n 0x0 0x0 POINTX2 ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08\nFor B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12\nFor B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17\nFor P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06\nFor P-256, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11\nFor P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 0 32 read-write ECC_X2_01 CRYPTO_ECC_X2_01 ECC The X-coordinate word1 of the second point 0x89C read-write n 0x0 0x0 ECC_X2_02 CRYPTO_ECC_X2_02 ECC The X-coordinate word2 of the second point 0x8A0 read-write n 0x0 0x0 ECC_X2_03 CRYPTO_ECC_X2_03 ECC The X-coordinate word3 of the second point 0x8A4 read-write n 0x0 0x0 ECC_X2_04 CRYPTO_ECC_X2_04 ECC The X-coordinate word4 of the second point 0x8A8 read-write n 0x0 0x0 ECC_X2_05 CRYPTO_ECC_X2_05 ECC The X-coordinate word5 of the second point 0x8AC read-write n 0x0 0x0 ECC_X2_06 CRYPTO_ECC_X2_06 ECC The X-coordinate word6 of the second point 0x8B0 read-write n 0x0 0x0 ECC_X2_07 CRYPTO_ECC_X2_07 ECC The X-coordinate word7 of the second point 0x8B4 read-write n 0x0 0x0 ECC_X2_08 CRYPTO_ECC_X2_08 ECC The X-coordinate word8 of the second point 0x8B8 read-write n 0x0 0x0 ECC_X2_09 CRYPTO_ECC_X2_09 ECC The X-coordinate word9 of the second point 0x8BC read-write n 0x0 0x0 ECC_X2_10 CRYPTO_ECC_X2_10 ECC The X-coordinate word10 of the second point 0x8C0 read-write n 0x0 0x0 ECC_X2_11 CRYPTO_ECC_X2_11 ECC The X-coordinate word11 of the second point 0x8C4 read-write n 0x0 0x0 ECC_X2_12 CRYPTO_ECC_X2_12 ECC The X-coordinate word12 of the second point 0x8C8 read-write n 0x0 0x0 ECC_X2_13 CRYPTO_ECC_X2_13 ECC The X-coordinate word13 of the second point 0x8CC read-write n 0x0 0x0 ECC_X2_14 CRYPTO_ECC_X2_14 ECC The X-coordinate word14 of the second point 0x8D0 read-write n 0x0 0x0 ECC_X2_15 CRYPTO_ECC_X2_15 ECC The X-coordinate word15 of the second point 0x8D4 read-write n 0x0 0x0 ECC_X2_16 CRYPTO_ECC_X2_16 ECC The X-coordinate word16 of the second point 0x8D8 read-write n 0x0 0x0 ECC_X2_17 CRYPTO_ECC_X2_17 ECC The X-coordinate word17 of the second point 0x8DC read-write n 0x0 0x0 ECC_Y1_00 CRYPTO_ECC_Y1_00 ECC The Y-coordinate word0 of the first point 0x850 read-write n 0x0 0x0 POINTY1 ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08\nFor B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12\nFor B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17\nFor P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06\nFor P-256, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11\nFor P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 0 32 read-write ECC_Y1_01 CRYPTO_ECC_Y1_01 ECC The Y-coordinate word1 of the first point 0x854 read-write n 0x0 0x0 ECC_Y1_02 CRYPTO_ECC_Y1_02 ECC The Y-coordinate word2 of the first point 0x858 read-write n 0x0 0x0 ECC_Y1_03 CRYPTO_ECC_Y1_03 ECC The Y-coordinate word3 of the first point 0x85C read-write n 0x0 0x0 ECC_Y1_04 CRYPTO_ECC_Y1_04 ECC The Y-coordinate word4 of the first point 0x860 read-write n 0x0 0x0 ECC_Y1_05 CRYPTO_ECC_Y1_05 ECC The Y-coordinate word5 of the first point 0x864 read-write n 0x0 0x0 ECC_Y1_06 CRYPTO_ECC_Y1_06 ECC The Y-coordinate word6 of the first point 0x868 read-write n 0x0 0x0 ECC_Y1_07 CRYPTO_ECC_Y1_07 ECC The Y-coordinate word7 of the first point 0x86C read-write n 0x0 0x0 ECC_Y1_08 CRYPTO_ECC_Y1_08 ECC The Y-coordinate word8 of the first point 0x870 read-write n 0x0 0x0 ECC_Y1_09 CRYPTO_ECC_Y1_09 ECC The Y-coordinate word9 of the first point 0x874 read-write n 0x0 0x0 ECC_Y1_10 CRYPTO_ECC_Y1_10 ECC The Y-coordinate word10 of the first point 0x878 read-write n 0x0 0x0 ECC_Y1_11 CRYPTO_ECC_Y1_11 ECC The Y-coordinate word11 of the first point 0x87C read-write n 0x0 0x0 ECC_Y1_12 CRYPTO_ECC_Y1_12 ECC The Y-coordinate word12 of the first point 0x880 read-write n 0x0 0x0 ECC_Y1_13 CRYPTO_ECC_Y1_13 ECC The Y-coordinate word13 of the first point 0x884 read-write n 0x0 0x0 ECC_Y1_14 CRYPTO_ECC_Y1_14 ECC The Y-coordinate word14 of the first point 0x888 read-write n 0x0 0x0 ECC_Y1_15 CRYPTO_ECC_Y1_15 ECC The Y-coordinate word15 of the first point 0x88C read-write n 0x0 0x0 ECC_Y1_16 CRYPTO_ECC_Y1_16 ECC The Y-coordinate word16 of the first point 0x890 read-write n 0x0 0x0 ECC_Y1_17 CRYPTO_ECC_Y1_17 ECC The Y-coordinate word17 of the first point 0x894 read-write n 0x0 0x0 ECC_Y2_00 CRYPTO_ECC_Y2_00 ECC The Y-coordinate word0 of the second point 0x8E0 read-write n 0x0 0x0 POINTY2 ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08\nFor B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12\nFor B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17\nFor P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06\nFor P-256, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11\nFor P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 0 32 read-write ECC_Y2_01 CRYPTO_ECC_Y2_01 ECC The Y-coordinate word1 of the second point 0x8E4 read-write n 0x0 0x0 ECC_Y2_02 CRYPTO_ECC_Y2_02 ECC The Y-coordinate word2 of the second point 0x8E8 read-write n 0x0 0x0 ECC_Y2_03 CRYPTO_ECC_Y2_03 ECC The Y-coordinate word3 of the second point 0x8EC read-write n 0x0 0x0 ECC_Y2_04 CRYPTO_ECC_Y2_04 ECC The Y-coordinate word4 of the second point 0x8F0 read-write n 0x0 0x0 ECC_Y2_05 CRYPTO_ECC_Y2_05 ECC The Y-coordinate word5 of the second point 0x8F4 read-write n 0x0 0x0 ECC_Y2_06 CRYPTO_ECC_Y2_06 ECC The Y-coordinate word6 of the second point 0x8F8 read-write n 0x0 0x0 ECC_Y2_07 CRYPTO_ECC_Y2_07 ECC The Y-coordinate word7 of the second point 0x8FC read-write n 0x0 0x0 ECC_Y2_08 CRYPTO_ECC_Y2_08 ECC The Y-coordinate word8 of the second point 0x900 read-write n 0x0 0x0 ECC_Y2_09 CRYPTO_ECC_Y2_09 ECC The Y-coordinate word9 of the second point 0x904 read-write n 0x0 0x0 ECC_Y2_10 CRYPTO_ECC_Y2_10 ECC The Y-coordinate word10 of the second point 0x908 read-write n 0x0 0x0 ECC_Y2_11 CRYPTO_ECC_Y2_11 ECC The Y-coordinate word11 of the second point 0x90C read-write n 0x0 0x0 ECC_Y2_12 CRYPTO_ECC_Y2_12 ECC The Y-coordinate word12 of the second point 0x910 read-write n 0x0 0x0 ECC_Y2_13 CRYPTO_ECC_Y2_13 ECC The Y-coordinate word13 of the second point 0x914 read-write n 0x0 0x0 ECC_Y2_14 CRYPTO_ECC_Y2_14 ECC The Y-coordinate word14 of the second point 0x918 read-write n 0x0 0x0 ECC_Y2_15 CRYPTO_ECC_Y2_15 ECC The Y-coordinate word15 of the second point 0x91C read-write n 0x0 0x0 ECC_Y2_16 CRYPTO_ECC_Y2_16 ECC The Y-coordinate word16 of the second point 0x920 read-write n 0x0 0x0 ECC_Y2_17 CRYPTO_ECC_Y2_17 ECC The Y-coordinate word17 of the second point 0x924 read-write n 0x0 0x0 INTEN CRYPTO_INTEN Crypto Interrupt Enable Control Register 0x0 read-write n 0x0 0x0 AESEIEN AES Error Flag Enable Bit 1 1 read-write 0 AES error interrupt flag Disabled #0 1 AES error interrupt flag Enabled #1 AESIEN AES Interrupt Enable Bit\nNote: In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine. In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation. 0 1 read-write 0 AES interrupt Disabled #0 1 AES interrupt Enabled #1 ECCEIEN ECC Error Interrupt Enable Bit 23 1 read-write 0 ECC error interrupt flag Disabled #0 1 ECC error interrupt flag Enabled #1 ECCIEN ECC Interrupt Enable Bit\nNote: In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine. In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation. 22 1 read-write 0 ECC interrupt Disabled #0 1 ECC interrupt Enabled #1 PRNGIEN PRNG Interrupt Enable Bit 16 1 read-write 0 PRNG interrupt Disabled #0 1 PRNG interrupt Enabled #1 SHAEIEN SHA Error Interrupt Enable Bit 25 1 read-write 0 SHA error interrupt flag Disabled #0 1 SHA error interrupt flag Enabled #1 SHAIEN SHA Interrupt Enable Bit\nNote: In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA engine. In Non-DMA mode, an interrupt will be triggered when the SHA engine finishes the operation. 24 1 read-write 0 SHA interrupt Disabled #0 1 SHA interrupt Enabled #1 TDESEIEN TDES/DES Error Flag Enable Bit 9 1 read-write 0 TDES/DES error interrupt flag Disabled #0 1 TDES/DES error interrupt flag Enabled #1 TDESIEN TDES/DES Interrupt Enable Bit\nNote: In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine. In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation. 8 1 read-write 0 TDES/DES interrupt Disabled #0 1 TDES/DES interrupt Enabled #1 INTSTS CRYPTO_INTSTS Crypto Interrupt Flag 0x4 read-write n 0x0 0x0 AESEIF AES Error Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0. 1 1 read-write 0 No AES error #0 1 AES encryption/decryption error interrupt #1 AESIF AES Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0. 0 1 read-write 0 No AES interrupt #0 1 AES encryption/decryption done interrupt #1 ECCEIF ECC Error Flag\nThis register includes operating and setting error. The detail flag is shown in CRYPTO_ECC_STS register.\nThis bit is cleared by writing 1, and it has no effect by writing 0. 23 1 read-write 0 No ECC error #0 1 ECC error interrupt #1 ECCIF ECC Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0. 22 1 read-write 0 No ECC interrupt #0 1 ECC operation done interrupt #1 PRNGIF PRNG Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0. 16 1 read-write 0 No PRNG interrupt #0 1 PRNG key generation done interrupt #1 SHAEIF SHA Error Flag\nThis register includes operating and setting error. The detail flag is shown in CRYPTO_SHA_STS register.\nThis bit is cleared by writing 1, and it has no effect by writing 0. 25 1 read-write 0 No SHA error #0 1 SHA error interrupt #1 SHAIF SHA Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0. 24 1 read-write 0 No SHA interrupt #0 1 SHA operation done interrupt #1 TDESEIF TDES/DES Error Flag\nThis bit includes the operating and setting error. The detailed flag is shown in the CRYPTO_TDES_STS register. This includes operating and setting error.\nThis bit is cleared by writing 1, and it has no effect by writing 0. 9 1 read-write 0 No TDES/DES error #0 1 TDES/DES encryption/decryption error interrupt #1 TDESIF TDES/DES Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0. 8 1 read-write 0 No TDES/DES interrupt #0 1 TDES/DES encryption/decryption done interrupt #1 PRNG_CTL CRYPTO_PRNG_CTL PRNG Control Register 0x8 read-write n 0x0 0x0 BUSY PRNG Busy (Read Only) 8 1 read-only 0 PRNG engine is idle #0 1 Indicate that the PRNG engine is generating CRYPTO_PRNG_KEYx #1 KEYSZ PRNG Generate Key Size 2 2 read-write 0 64 bits #00 1 128 bits #01 2 192 bits #10 3 256 bits #11 SEEDRLD Reload New Seed for PRNG Engine 1 1 read-write 0 Generating key based on the current seed #0 1 Reload new seed #1 START Start PRNG Engine 0 1 read-write 0 Stop PRNG engine #0 1 Generate new key and store the new key to register CRYPTO_PRNG_KEYx, which will be cleared when the new key is generated #1 PRNG_KEY0 CRYPTO_PRNG_KEY0 PRNG Generated Key0 0x10 read-only n 0x0 0x0 KEY Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG. 0 32 read-only PRNG_KEY1 CRYPTO_PRNG_KEY1 PRNG Generated Key1 0x14 read-write n 0x0 0x0 PRNG_KEY2 CRYPTO_PRNG_KEY2 PRNG Generated Key2 0x18 read-write n 0x0 0x0 PRNG_KEY3 CRYPTO_PRNG_KEY3 PRNG Generated Key3 0x1C read-write n 0x0 0x0 PRNG_KEY4 CRYPTO_PRNG_KEY4 PRNG Generated Key4 0x20 read-write n 0x0 0x0 PRNG_KEY5 CRYPTO_PRNG_KEY5 PRNG Generated Key5 0x24 read-write n 0x0 0x0 PRNG_KEY6 CRYPTO_PRNG_KEY6 PRNG Generated Key6 0x28 read-write n 0x0 0x0 PRNG_KEY7 CRYPTO_PRNG_KEY7 PRNG Generated Key7 0x2C read-write n 0x0 0x0 PRNG_SEED CRYPTO_PRNG_SEED Seed for PRNG 0xC write-only n 0x0 0x0 SEED Seed for PRNG (Write Only)\nThe bits store the seed for PRNG engine. 0 32 write-only SHA_CTL CRYPTO_SHA_CTL SHA Control Register 0x300 read-write n 0x0 0x0 DMAEN SHA Engine DMA Enable Bit\nSHA engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. 7 1 read-write 0 SHA DMA engine Disabled #0 1 SHA DMA engine Enabled #1 DMALAST SHA Last Block\nThis bit must be set as feeding in last byte of data. 5 1 read-write INSWAP SHA Engine Input Data Swap 23 1 read-write 0 Keep the original order #0 1 The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3} #1 OPMODE SHA Engine Operation Modes\n0x0xx: SHA160\n0x100: SHA256\n0x101: SHA224\n0x110: reservedReserved.\n0x111: SHA384 8 3 read-write OUTSWAP SHA Engine Output Data Swap 22 1 read-write 0 Keep the original order #0 1 The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3} #1 START SHA Engine Start\nNote: This bit is always 0 when it's read back. 0 1 read-write 0 No effect #0 1 Start SHA/SHA engine. BUSY flag will be set #1 STOP SHA Engine Stop\nNote: This bit is always 0 when it's read back. 1 1 read-write 0 No effect #0 1 Stop SHA/SHA engine #1 SHA_DATIN CRYPTO_SHA_DATIN SHA Engine Non-DMA Mode Data Input Port Register 0x354 read-write n 0x0 0x0 DATIN SHA Engine Input Port\nCPU feeds data to SHA engine through this port by checking CRYPTO_SHA_STS. Feed data as DATINREQ is 1. 0 32 read-write SHA_DGST0 CRYPTO_SHA_DGST0 SHA Digest Message 0 0x308 read-only n 0x0 0x0 DGST SHA Digest Message Output Register\nFor SHA-160, the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224, the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256, the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST7.\nFor SHA-384, the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST11. 0 32 read-only SHA_DGST1 CRYPTO_SHA_DGST1 SHA Digest Message 1 0x30C read-write n 0x0 0x0 SHA_DGST10 CRYPTO_SHA_DGST10 SHA Digest Message 10 0x330 read-write n 0x0 0x0 SHA_DGST11 CRYPTO_SHA_DGST11 SHA Digest Message 11 0x334 read-write n 0x0 0x0 SHA_DGST2 CRYPTO_SHA_DGST2 SHA Digest Message 2 0x310 read-write n 0x0 0x0 SHA_DGST3 CRYPTO_SHA_DGST3 SHA Digest Message 3 0x314 read-write n 0x0 0x0 SHA_DGST4 CRYPTO_SHA_DGST4 SHA Digest Message 4 0x318 read-write n 0x0 0x0 SHA_DGST5 CRYPTO_SHA_DGST5 SHA Digest Message 5 0x31C read-write n 0x0 0x0 SHA_DGST6 CRYPTO_SHA_DGST6 SHA Digest Message 6 0x320 read-write n 0x0 0x0 SHA_DGST7 CRYPTO_SHA_DGST7 SHA Digest Message 7 0x324 read-write n 0x0 0x0 SHA_DGST8 CRYPTO_SHA_DGST8 SHA Digest Message 8 0x328 read-write n 0x0 0x0 SHA_DGST9 CRYPTO_SHA_DGST9 SHA Digest Message 9 0x32C read-write n 0x0 0x0 SHA_DMACNT CRYPTO_SHA_DMACNT SHA Byte Count Register 0x350 read-write n 0x0 0x0 DMACNT SHA Operation Byte Count\nThe CRYPTO_SHA_DMACNT keeps the byte count of source text that is for the SHA engine operating in DMA mode. The CRYPTO_SHA_DMACNT is 32-bit and the maximum of byte count is 4G bytes.\nCRYPTO_SHA_DMACNT can be read and written. Writing to CRYPTO_SHA_DMACNT while the SHA accelerator is operating doesn't affect the current SHA operation. But the value of CRYPTO_SHA_DMACNT will be updated later on. Consequently, software can prepare the byte count of data for the next SHA operation.\nIn Non-DMA mode, CRYPTO_SHA_DMACNT must be set as the byte count of the last block before feeding in the last block of data. 0 32 read-write SHA_KEYCNT CRYPTO_SHA_KEYCNT SHA Key Byte Count Register 0x348 read-write n 0x0 0x0 KEYCNT SHA Key Byte Count\nThe CRYPTO_SHA_KEYCNT keeps the byte count of key that SHA/SHA engine operates. The register is 32-bit and the maximum byte count is 4G bytes. It can be read and written. \nWriting to the register CRYPTO_SHA_KEYCNT as the SHA/SHA accelerator operating doesn't affect the current SHA/SHA operation. But the value of CRYPTO_SHA _KEYCNT will be updated later on. Consequently, software can prepare the key count for the next SHA/SHA operation. 0 32 read-write SHA_SADDR CRYPTO_SHA_SADDR SHA DMA Source Address Register 0x34C read-write n 0x0 0x0 SADDR SHA DMA Source Address\nThe SHA accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The CRYPTO_SHA_SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the SHA accelerator can read the plain text from SRAM memory space and do SHA operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of CRYPTO_SHA_SADDR are ignored.\nCRYPTO_SHA_SADDR can be read and written. Writing to CRYPTO_SHA_SADDR while the SHA accelerator is operating doesn't affect the current SHA operation. But the value of CRYPTO_SHA_SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next SHA operation.\nIn DMA mode, software can update the next CRYPTO_SHA_SADDR before triggering START.\nCRYPTO_SHA_SADDR and CRYPTO_SHA_DADDR can be the same in the value. 0 32 read-write SHA_STS CRYPTO_SHA_STS SHA Status Flag 0x304 read-only n 0x0 0x0 BUSY SHA Engine Busy 0 1 read-only 0 SHA/SHA engine is idle or finished #0 1 SHA/SHA engine is busy #1 DATINREQ SHA Non-dMA Mode Data Input Request 16 1 read-only 0 No effect #0 1 Request SHA/SHA Non-DMA mode data input #1 DMABUSY SHA Engine DMA Busy Flag 1 1 read-only 0 SHA/SHA DMA engine is idle or finished #0 1 SHA/SHA DMA engine is busy #1 DMAERR SHA Engine DMA Error Flag 8 1 read-only 0 Show the SHA/SHA engine access normal #0 1 Show the SHA/SHA engine access error #1 TDES0_CNT CRYPTO_TDES0_CNT TDES/DES Byte Count Register for Channel 0 0x230 read-write n 0x0 0x0 CNT TDES/DES Byte Count \nThe CRYPTO_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode. The CRYPTO_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\nCRYPTO_TDESn_CNT can be read and written. Writing to CRYPTO_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. But the value of CRYPTO_TDESn_CNT will be updated later on. Consequently, software can prepare the byte count of data for the next TDES /DES operation.\nIn Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRYPTO_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. 0 32 read-write TDES0_DADDR CRYPTO_TDES0_DADDR TDES/DES DMA Destination Address Register for Channel 0 0x22C read-write n 0x0 0x0 DADDR TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO. The CRYPTO_TDESn_DADDR keeps the destination address of the data buffer where the engine output's text will be stored. Based on the destination address, the TDES/DES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the TDES/DES operation is finished. The start of destination address should be located at word boundary. In other words, bit 1 and 0 of CRYPTO_TDESn_DADDR are ignored.\nCRYPTO_TDESn_DADDR can be read and written. Writing to CRYPTO_TDESn_DADDR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. But the value of CRYPTO_TDESn_DADDR will be updated later on. Consequently, software can prepare the destination address for the next TDES/DES operation.\nIn DMA mode, software can update the next CRYPTO_TDESn_DADDR before triggering START. \nCRYPTO_TDESn_SADDR and CRYPTO_TDESn_DADDR can be the same in the value. 0 32 read-write TDES0_IVH CRYPTO_TDES0_IVH TDES/DES Initial Vector High Word Register for Channel 0 0x220 read-write n 0x0 0x0 IV TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode. IV is Nonce counter for TDES/DES engine in CTR mode. 0 32 read-write TDES0_IVL CRYPTO_TDES0_IVL TDES/DES Initial Vector Low Word Register for Channel 0 0x224 read-write n 0x0 0x0 TDES0_KEY1H CRYPTO_TDES0_KEY1H TDES/DES Key 1 High Word Register for Channel 0 0x208 read-write n 0x0 0x0 KEY TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits. Thus, it needs two 32-bit registers to store a security key. The register CRYPTO_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRYPTO_TDESn_KEYxL is used to keep the bit [31:0]. 0 32 read-write TDES0_KEY1L CRYPTO_TDES0_KEY1L TDES/DES Key 1 Low Word Register for Channel 0 0x20C read-write n 0x0 0x0 TDES0_KEY2H CRYPTO_TDES0_KEY2H TDES Key 2 High Word Register for Channel 0 0x210 read-write n 0x0 0x0 TDES0_KEY2L CRYPTO_TDES0_KEY2L TDES Key 2 Low Word Register for Channel 0 0x214 read-write n 0x0 0x0 TDES0_KEY3H CRYPTO_TDES0_KEY3H TDES Key 3 High Word Register for Channel 0 0x218 read-write n 0x0 0x0 TDES0_KEY3L CRYPTO_TDES0_KEY3L TDES Key 3 Low Word Register for Channel 0 0x21C read-write n 0x0 0x0 TDES0_SADDR CRYPTO_TDES0_SADDR TDES/DES DMA Source Address Register for Channel 0 0x228 read-write n 0x0 0x0 SADDR TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The CRYPTO_TDESn_SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the TDES/DES accelerator can read the plain text (encryption) / cipher text (decryption) from SRAM memory space and do TDES/DES operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of CRYPTO_TDESn_SADDR are ignored.\nCRYPTO_TDESn_SADDR can be read and written. Writing to CRYPTO_TDESn_SADDR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. But the value of CRYPTO_TDESn_SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next TDES/DES operation.\nIn DMA mode, software can update the next CRYPTO_TDESn_SADDR before triggering START.\nCRYPTO_TDESn_SADDR and CRYPTO_TDESn_DADDR can be the same in the value. 0 32 read-write TDES1_CNT CRYPTO_TDES1_CNT TDES/DES Byte Count Register for Channel 1 0x270 read-write n 0x0 0x0 TDES1_DADDR CRYPTO_TDES1_DADDR TDES/DES DMA Destination Address Register for Channel 1 0x26C read-write n 0x0 0x0 TDES1_IVH CRYPTO_TDES1_IVH TDES/DES Initial Vector High Word Register for Channel 1 0x260 read-write n 0x0 0x0 TDES1_IVL CRYPTO_TDES1_IVL TDES/DES Initial Vector Low Word Register for Channel 1 0x264 read-write n 0x0 0x0 TDES1_KEY1H CRYPTO_TDES1_KEY1H TDES/DES Key 1 High Word Register for Channel 1 0x248 read-write n 0x0 0x0 TDES1_KEY1L CRYPTO_TDES1_KEY1L TDES/DES Key 1 Low Word Register for Channel 1 0x24C read-write n 0x0 0x0 TDES1_KEY2H CRYPTO_TDES1_KEY2H TDES Key 2 High Word Register for Channel 1 0x250 read-write n 0x0 0x0 TDES1_KEY2L CRYPTO_TDES1_KEY2L TDES Key 2 Low Word Register for Channel 1 0x254 read-write n 0x0 0x0 TDES1_KEY3H CRYPTO_TDES1_KEY3H TDES Key 3 High Word Register for Channel 1 0x258 read-write n 0x0 0x0 TDES1_KEY3L CRYPTO_TDES1_KEY3L TDES Key 3 Low Word Register for Channel 1 0x25C read-write n 0x0 0x0 TDES1_SADDR CRYPTO_TDES1_SADDR TDES/DES DMA Source Address Register for Channel 1 0x268 read-write n 0x0 0x0 TDES2_CNT CRYPTO_TDES2_CNT TDES/DES Byte Count Register for Channel 2 0x2B0 read-write n 0x0 0x0 TDES2_DADDR CRYPTO_TDES2_DADDR TDES/DES DMA Destination Address Register for Channel 2 0x2AC read-write n 0x0 0x0 TDES2_IVH CRYPTO_TDES2_IVH TDES/DES Initial Vector High Word Register for Channel 2 0x2A0 read-write n 0x0 0x0 TDES2_IVL CRYPTO_TDES2_IVL TDES/DES Initial Vector Low Word Register for Channel 2 0x2A4 read-write n 0x0 0x0 TDES2_KEY1H CRYPTO_TDES2_KEY1H TDES/DES Key 1 High Word Register for Channel 2 0x288 read-write n 0x0 0x0 TDES2_KEY1L CRYPTO_TDES2_KEY1L TDES/DES Key 1 Low Word Register for Channel 2 0x28C read-write n 0x0 0x0 TDES2_KEY2H CRYPTO_TDES2_KEY2H TDES Key 2 High Word Register for Channel 2 0x290 read-write n 0x0 0x0 TDES2_KEY2L CRYPTO_TDES2_KEY2L TDES Key 2 Low Word Register for Channel 2 0x294 read-write n 0x0 0x0 TDES2_KEY3H CRYPTO_TDES2_KEY3H TDES Key 3 High Word Register for Channel 2 0x298 read-write n 0x0 0x0 TDES2_KEY3L CRYPTO_TDES2_KEY3L TDES Key 3 Low Word Register for Channel 2 0x29C read-write n 0x0 0x0 TDES2_SADDR CRYPTO_TDES2_SADDR TDES/DES DMA Source Address Register for Channel 2 0x2A8 read-write n 0x0 0x0 TDES3_CNT CRYPTO_TDES3_CNT TDES/DES Byte Count Register for Channel 3 0x2F0 read-write n 0x0 0x0 TDES3_DADDR CRYPTO_TDES3_DADDR TDES/DES DMA Destination Address Register for Channel 3 0x2EC read-write n 0x0 0x0 TDES3_IVH CRYPTO_TDES3_IVH TDES/DES Initial Vector High Word Register for Channel 3 0x2E0 read-write n 0x0 0x0 TDES3_IVL CRYPTO_TDES3_IVL TDES/DES Initial Vector Low Word Register for Channel 3 0x2E4 read-write n 0x0 0x0 TDES3_KEY1H CRYPTO_TDES3_KEY1H TDES/DES Key 1 High Word Register for Channel 3 0x2C8 read-write n 0x0 0x0 TDES3_KEY1L CRYPTO_TDES3_KEY1L TDES/DES Key 1 Low Word Register for Channel 3 0x2CC read-write n 0x0 0x0 TDES3_KEY2H CRYPTO_TDES3_KEY2H TDES Key 2 High Word Register for Channel 3 0x2D0 read-write n 0x0 0x0 TDES3_KEY2L CRYPTO_TDES3_KEY2L TDES Key 2 Low Word Register for Channel 3 0x2D4 read-write n 0x0 0x0 TDES3_KEY3H CRYPTO_TDES3_KEY3H TDES Key 3 High Word Register for Channel 3 0x2D8 read-write n 0x0 0x0 TDES3_KEY3L CRYPTO_TDES3_KEY3L TDES Key 3 Low Word Register for Channel 3 0x2DC read-write n 0x0 0x0 TDES3_SADDR CRYPTO_TDES3_SADDR TDES/DES DMA Source Address Register for Channel 3 0x2E8 read-write n 0x0 0x0 TDES_CTL CRYPTO_TDES_CTL TDES/DES Control Register 0x200 read-write n 0x0 0x0 BLKSWAP TDES/DES Engine Block Double Word Endian Swap 21 1 read-write 0 Keep the original order, e.g. {WORD_H, WORD_L} #0 1 When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H} #1 CHANNEL TDES/DES Engine Working Channel 24 2 read-write 0 Current control register setting is for channel 0 #00 1 Current control register setting is for channel 1 #01 2 Current control register setting is for channel 2 #10 3 Current control register setting is for channel 3 #11 DMACSCAD TDES/DES Engine DMA with Cascade Mode 6 1 read-write 0 DMA cascade function Disabled #0 1 In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation #1 DMAEN TDES/DES Engine DMA Enable Bit\nTDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. 7 1 read-write 0 TDES_DMA engine Disabled #0 1 TDES_DMA engine Enabled #1 DMALAST TDES/DES Engine Start for the Last Block \nIn DMA mode, this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode, this bit must be set as feeding in last block of data. 5 1 read-write ENCRYPTO TDES/DES Encryption/Decryption 16 1 read-write 0 TDES engine executes decryption operation #0 1 TDES engine executes encryption operation #1 INSWAP TDES/DES Engine Input Data Swap 23 1 read-write 0 Keep the original order #0 1 The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3} #1 KEYPRT Protect Key\nRead as a flag to reflect KEYPRT. 31 1 read-write 0 No effect #0 1 This bit is to protect the content of TDES key from reading. The return value for reading CRYPTO_ TDESn_KEYxH/L is not the content in the registers CRYPTO_ TDESn_KEYxH/L. Once it is set, it can be cleared by asserting KEYUNPRT. The key content would be cleared as well #1 KEYUNPRT Unprotect Key\nWriting 0 to CRYPTO_TDES_CTL [31] and '10110' to CRYPTO_TDES_CTL [30:26] is to unprotect TDES key.\nThe KEYUNPRT can be read and written. When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. 26 5 read-write OPMODE TDES/DES Engine Operation Mode 8 3 read-write 0 ECB (Electronic Codebook Mode) 0x00 1 CBC (Cipher Block Chaining Mode) 0x01 2 CFB (Cipher Feedback Mode) 0x02 3 OFB (Output Feedback Mode) 0x03 4 CTR (Counter Mode) 0x04 OUTSWAP TDES/DES Engine Output Data Swap 22 1 read-write 0 Keep the original order #0 1 The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3} #1 START TDES/DES Engine Start\nNote: The bit is always 0 when it's read back. 0 1 read-write 0 No effect #0 1 Start TDES/DES engine. The flag BUSY would be set #1 STOP TDES/DES Engine Stop\nNote: The bit is always 0 when it's read back. 1 1 read-write 0 No effect #0 1 Stop TDES/DES engine #1 TMODE TDES/DES Engine Operating Mode 2 1 read-write 0 Set DES mode for TDES/DES engine #0 1 Set Triple DES mode for TDES/DES engine #1 _3KEYS TDES/DES Key Number 3 1 read-write 0 Select KEY1 and KEY2 in TDES/DES engine #0 1 Triple keys in TDES/DES engine Enabled #1 TDES_DATIN CRYPTO_TDES_DATIN TDES/DES Engine Input data Word Register 0x234 read-write n 0x0 0x0 DATIN TDES/DES Engine Input Port\nCPU feeds data to TDES/DES engine through this port by checking CRYPTO_TDES_STS. Feed data as INBUFFULL is 0. 0 32 read-write TDES_DATOUT CRYPTO_TDES_DATOUT TDES/DES Engine Output data Word Register 0x238 read-only n 0x0 0x0 DATOUT TDES/DES Engine Output Port\nCPU gets result from the TDES/DES engine through this port by checking CRYPTO_TDES_STS. Get data as OUTBUFEMPTY is 0. 0 32 read-only TDES_FDBCKH CRYPTO_TDES_FDBCKH TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation 0x60 read-only n 0x0 0x0 FDBCK TDES/DES Feedback\nThe feedback value is 64 bits in size.\nThe TDES/DES engine uses the data from {CRYPTO_TDES_FDBCKH, CRYPTO_TDES_FDBCKL} as the data inputted to {CRYPTO_TDESn_IVH, CRYPTO_TDESn_IVL} for the next block in DMA cascade mode. The feedback register is for CBC, CFB, and OFB mode.\nTDES/DES engine outputs feedback information for IV in the next block's operation. Software can use this feedback information to implement more than four DMA channels. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to CRYPTO_TDESn_IVH/L in the same channel operation. Then can continue the operation with the original setting. 0 32 read-only TDES_FDBCKL CRYPTO_TDES_FDBCKL TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation 0x64 read-write n 0x0 0x0 TDES_STS CRYPTO_TDES_STS TDES/DES Engine Flag 0x204 -1 read-only n 0x0 0x0 BUSERR TDES/DES DMA Access Bus Error Flag 20 1 read-only 0 No error #0 1 Bus error will stop DMA operation and TDES/DES engine #1 BUSY TDES/DES Engine Busy 0 1 read-only 0 TDES/DES engine is idle or finished #0 1 TDES/DES engine is under processing #1 INBUFEMPTY TDES/DES in Buffer Empty 8 1 read-only 0 There are some data in input buffer waiting for the TDES/DES engine to process #0 1 TDES/DES input buffer is empty. Software needs to feed data to the TDES/DES engine. Otherwise, the TDES/DES engine will be pending to wait for input data #1 INBUFERR TDES/DES in Buffer Error Flag 10 1 read-only 0 No error #0 1 Error happens during feeding data to the TDES/DES engine #1 INBUFFULL TDES/DES in Buffer Full Flag 9 1 read-only 0 TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine #0 1 TDES input buffer is full. Software cannot feed data to the TDES/DES engine. Otherwise, the flag INBUFERR will be set to 1 #1 OUTBUFEMPTY TDES/DES Output Buffer Empty Flag 16 1 read-only 0 TDES/DES output buffer is not empty. There are some valid data kept in output buffer #0 1 TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT. Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty #1 OUTBUFERR TDES/DES Out Buffer Error Flag 18 1 read-only 0 No error #0 1 Error happens during getting test result from TDES/DES engine #1 OUTBUFFULL TDES/DES Output Buffer Full Flag 17 1 read-only 0 TDES/DES output buffer is not full #0 1 TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT. Otherwise, the TDES/DES engine will be pending since output buffer is full #1 DAC DAC Register Map DAC 0x0 0x0 0x18 registers n 0x40 0x18 registers n DAC0_CTL DAC0_CTL DAC0 Control Register 0x0 read-write n 0x0 0x0 BWSEL DAC Data Bit-width Selection 14 2 read-write 0 data is 12 bits #00 1 data is 8 bits #01 BYPASS Bypass Buffer Mode 8 1 read-write 0 Output voltage buffer Enabled #0 1 Output voltage buffer Disabled #1 DACEN DAC Enable Bit 0 1 read-write 0 DAC Disabled #0 1 DAC Enabled #1 DACIEN DAC Interrupt Enable Bit 1 1 read-write 0 DAC interrupt Disabled #0 1 DAC interrupt Enabled #1 DMAEN DMA Mode Enable Bit 2 1 read-write 0 DMA mode Disabled #0 1 DMA mode Enabled #1 DMAURIEN DMA Under-run Interrupt Enable Bit 3 1 read-write 0 DMA under-run interrupt Disabled #0 1 DMA under-run interrupt Enabled #1 ETRGSEL External Pin Trigger Selection 12 2 read-write 0 Low level trigger #00 1 High level trigger #01 2 Falling edge trigger #10 3 Rising edge trigger #11 GRPEN DAC Group Mode Enable Bit 16 1 read-write 0 DAC0 and DAC1 are not grouped #0 1 DAC0 and DAC1 are grouped #1 LALIGN DAC Data Left-aligned Enabled Control 10 1 read-write 0 Right alignment #0 1 Left alignment #1 TRGEN Trigger Mode Enable Bit 4 1 read-write 0 DAC event trigger mode Disabled #0 1 DAC event trigger mode Enabled #1 TRGSEL Trigger Source Selection 5 3 read-write 0 Software trigger #000 1 External pin DAC0_ST trigger #001 2 Timer 0 trigger #010 3 Timer 1 trigger #011 4 Timer 2 trigger #100 5 Timer 3 trigger #101 6 EPWM0 trigger #110 7 EPWM1 trigger #111 DAC0_DAT DAC0_DAT DAC0 Data Holding Register 0x8 read-write n 0x0 0x0 DACDAT DAC 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.\n12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.\n12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. 0 16 read-write DAC0_DATOUT DAC0_DATOUT DAC0 Data Output Register 0xC read-only n 0x0 0x0 DATOUT DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC_DAT register and user cannot write it directly. 0 12 read-only DAC0_STATUS DAC0_STATUS DAC0 Status Register 0x10 read-write n 0x0 0x0 BUSY DAC Busy Flag (Read Only) 8 1 read-only 0 DAC is ready for next conversion #0 1 DAC is busy in conversion #1 DMAUDR DMA Under-run Interrupt Flag\nNote: User writes 1 to clear this bit. 1 1 read-write 0 No DMA under-run error condition occurred #0 1 DMA under-run error condition occurred #1 FINISH DAC Conversion Complete Finish Flag\nNote: This bit is set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. User writes 1 to clear this bit to 0. 0 1 read-write 0 DAC is in conversion state #0 1 DAC conversion finish #1 DAC0_SWTRG DAC0_SWTRG DAC0 Software Trigger Control Register 0x4 read-write n 0x0 0x0 SWTRG Software Trigger Note: User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically reading this bit will always get 0. 0 1 read-write 0 Software trigger Disabled #0 1 Software trigger Enabled #1 DAC0_TCTL DAC0_TCTL DAC0 Timing Control Register 0x14 read-write n 0x0 0x0 SETTLET DAC Output Settling Time\nUser software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\nFor example, DAC controller clock speed is 80 MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x50. 0 10 read-write DAC1_CTL DAC1_CTL DAC1 Control Register 0x40 read-write n 0x0 0x0 BWSEL DAC Data Bit-width Selection 14 2 read-write 0 Data is 12 bits #00 1 Data is 8 bits #01 BYPASS Bypass Buffer Mode 8 1 read-write 0 Output voltage buffer Enabled #0 1 Output voltage buffer Disabled #1 DACEN DAC Enable Bit 0 1 read-write 0 DAC Disabled #0 1 DAC Enabled #1 DACIEN DAC Interrupt Enable Bit 1 1 read-write 0 DAC interrupt Disabled #0 1 DAC interrupt Enabled #1 DMAEN DMA Mode Enable Bit 2 1 read-write 0 DMA mode Disabled #0 1 DMA mode Enabled #1 DMAURIEN DMA Under-run Interrupt Enable Bit 3 1 read-write 0 DMA under-run interrupt Disabled #0 1 DMA under-run interrupt Enabled #1 ETRGSEL External Pin Trigger Selection 12 2 read-write 0 Low level trigger #00 1 High level trigger #01 2 Falling edge trigger #10 3 Rising edge trigger #11 LALIGN DAC Data Left-aligned Enabled Control 10 1 read-write 0 Right alignment #0 1 Left alignment #1 TRGEN Trigger Mode Enable Bit 4 1 read-write 0 DAC event trigger mode Disabled #0 1 DAC event trigger mode Enabled #1 TRGSEL Trigger Source Selection 5 3 read-write 0 Software trigger #000 1 External pin DAC1_ST trigger #001 2 Timer 0 trigger #010 3 Timer 1 trigger #011 4 Timer 2 trigger #100 5 Timer 3 trigger #101 6 EPWM0 trigger #110 7 EPWM1 trigger #111 DAC1_DAT DAC1_DAT DAC1 Data Holding Register 0x48 read-write n 0x0 0x0 DACDAT DAC 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.\n12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.\n12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. 0 16 read-write DAC1_DATOUT DAC1_DATOUT DAC1 Data Output Register 0x4C read-only n 0x0 0x0 DATOUT DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC_DAT register and user cannot write it directly. 0 12 read-only DAC1_STATUS DAC1_STATUS DAC1 Status Register 0x50 read-write n 0x0 0x0 BUSY DAC Busy Flag (Read Only) 8 1 read-only 0 DAC is ready for next conversion #0 1 DAC is busy in conversion #1 DMAUDR DMA Under-run Interrupt Flag\nNote: User writes 1 to clear this bit. 1 1 read-write 0 No DMA under-run error condition occurred #0 1 DMA under-run error condition occurred #1 FINISH DAC Conversion Complete Finish Flag\nNote: This bit set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. User writes 1 to clear this bit to 0. 0 1 read-write 0 DAC is in conversion state #0 1 DAC conversion finish #1 DAC1_SWTRG DAC1_SWTRG DAC1 Software Trigger Control Register 0x44 read-write n 0x0 0x0 SWTRG Software Trigger Note: User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically Reading this bit will always get 0. 0 1 read-write 0 Software trigger Disabled #0 1 Software trigger Enabled #1 DAC1_TCTL DAC1_TCTL DAC1 Timing Control Register 0x54 read-write n 0x0 0x0 SETTLET DAC Output Settling Time\nUser software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\nFor example, DAC controller clock speed is 80 MHz and DAC conversion settling time is 1 us, SETTLET value must be greater than 0x50. 0 10 read-write EADC EADC Register Map EADC 0x0 0x0 0x60 registers n 0x80 0x4C registers n 0xD0 0x4C registers n CALCTL EADC_CALCTL ADC Calibration Control Register 0x114 -1 read-write n 0x0 0x0 CALDONE Calibration Functional Block Complete (Read Only) 2 1 read-only 0 During a calibration #0 1 Calibration is completed #1 CALSEL Select Calibration Functional Block 3 1 read-write 0 Load calibration word when calibration functional block is active #0 1 Execute calibration when calibration functional block is active #1 CALSTART Calibration Functional Block Start\nNote: This bit is set by SW and clear by HW after re-calibration finish 1 1 read-write 0 Stop calibration functional block #0 1 Start calibration functional block #1 CALDWRD EADC_CALDWRD ADC Calibration Load Word Register 0x118 read-write n 0x0 0x0 CALWORD Calibration Word Bits Write to this register with the previous calibration word before load calibration action. Read this register after calibration done. Note: The calibration block contains two parts 'CALIBRATION' and 'LOAD CALIBRATION' if the calibration block configure as 'CALIBRATION' then this register represent the result of calibration when calibration is completed if configure as 'LOAD CALIBRATION' configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done. 0 7 read-write CMP0 EADC_CMP0 ADC Result Compare Register 0 0xE0 read-write n 0x0 0x0 ADCMPEN ADC Result Compare Enable Bit 0 1 read-write 0 Compare Disabled #0 1 Compare Enabled #1 ADCMPIE ADC Result Compare Interrupt Enable Bit 1 1 read-write 0 Compare function interrupt Disabled #0 1 Compare function interrupt Enabled #1 CMPCOND Compare Condition 2 1 read-write 0 Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one #0 1 Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one #1 CMPDAT Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software. 16 12 read-write CMPMCNT Compare Match Count 8 4 read-write CMPSPL Compare Sample Module Selection 3 5 read-write 0 Sample Module 0 conversion result EADC_DAT0 is selected to be compared #00000 1 Sample Module 1 conversion result EADC_DAT1 is selected to be compared #00001 2 Sample Module 2 conversion result EADC_DAT2 is selected to be compared #00010 3 Sample Module 3 conversion result EADC_DAT3 is selected to be compared #00011 4 Sample Module 4 conversion result EADC_DAT4 is selected to be compared #00100 5 Sample Module 5 conversion result EADC_DAT5 is selected to be compared #00101 6 Sample Module 6 conversion result EADC_DAT6 is selected to be compared #00110 7 Sample Module 7 conversion result EADC_DAT7 is selected to be compared #00111 8 Sample Module 8 conversion result EADC_DAT8 is selected to be compared #01000 9 Sample Module 9 conversion result EADC_DAT9 is selected to be compared #01001 10 Sample Module 10 conversion result EADC_DAT10 is selected to be compared #01010 11 Sample Module 11 conversion result EADC_DAT11 is selected to be compared #01011 12 Sample Module 12 conversion result EADC_DAT12 is selected to be compared #01100 13 Sample Module 13 conversion result EADC_DAT13 is selected to be compared #01101 14 Sample Module 14 conversion result EADC_DAT14 is selected to be compared #01110 15 Sample Module 15 conversion result EADC_DAT15 is selected to be compared #01111 16 Sample Module 16 conversion result EADC_DAT16 is selected to be compared #10000 17 Sample Module 17 conversion result EADC_DAT17 is selected to be compared #10001 18 Sample Module 18 conversion result EADC_DAT18 is selected to be compared #10010 CMPWEN Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register. 15 1 read-write 0 ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched. ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched #0 1 ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched #1 CMP1 EADC_CMP1 ADC Result Compare Register 1 0xE4 read-write n 0x0 0x0 CMP2 EADC_CMP2 ADC Result Compare Register 2 0xE8 read-write n 0x0 0x0 CMP3 EADC_CMP3 ADC Result Compare Register 3 0xEC read-write n 0x0 0x0 CTL EADC_CTL ADC Control Register 0x50 -1 read-write n 0x0 0x0 ADCEN ADC Converter Enable Bit\nNote: Before starting ADC conversion function, this bit should be set to 1. Clear it to 0 to disable ADC converter analog circuit power consumption. 0 1 read-write 0 Disabled EADC #0 1 Enabled EADC #1 ADCIEN0 Specific Sample Module ADC ADINT0 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion. If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. 2 1 read-write 0 Specific sample module ADC ADINT0 interrupt function Disabled #0 1 Specific sample module ADC ADINT0 interrupt function Enabled #1 ADCIEN1 Specific Sample Module ADC ADINT1 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion. If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. 3 1 read-write 0 Specific sample module ADC ADINT1 interrupt function Disabled #0 1 Specific sample module ADC ADINT1 interrupt function Enabled #1 ADCIEN2 Specific Sample Module ADC ADINT2 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion. If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. 4 1 read-write 0 Specific sample module ADC ADINT2 interrupt function Disabled #0 1 Specific sample module ADC ADINT2 interrupt function Enabled #1 ADCIEN3 Specific Sample Module ADC ADINT3 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion. If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. 5 1 read-write 0 Specific sample module ADC ADINT3 interrupt function Disabled #0 1 Specific sample module ADC ADINT3 interrupt function Enabled #1 ADCRST ADC Converter Control Circuits Reset\nNote: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0. 1 1 read-write 0 No effect #0 1 Cause ADC control circuits reset to initial state, but not change the ADC registers value #1 DIFFEN Differential Analog Input Mode Enable Bit 8 1 read-write 0 Single-end analog input mode #0 1 Differential analog input mode #1 DMOF ADC Differential Input Mode Output Format 9 1 read-write 0 ADC conversion result will be filled in RESULT (EADC_DATn[15:0], where n= 0 ~18) with unsigned format #0 1 ADC conversion result will be filled in RESULT (EADC_DATn[15:0], where n= 0 ~18) with 2'complement format #1 PDMAEN PDMA Transfer Enable Bit\nWhen ADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request. 11 1 read-write 0 PDMA data transfer Disabled #0 1 PDMA data transfer Enabled #1 RESSEL Resolution Selection 6 2 read-write 0 6-bit ADC result will be put at RESULT (EADC_DATn[5:0]) #00 1 8-bit ADC result will be put at RESULT (EADC_DATn[7:0]) #01 2 10-bit ADC result will be put at RESULT (EADC_DATn[9:0]) #10 3 12-bit ADC result will be put at RESULT (EADC_DATn[11:0]) #11 CURDAT EADC_CURDAT ADC PDMA Current Transfer Data Register 0x4C read-only n 0x0 0x0 CURDAT ADC PDMA Current Transfer Data (Read Only) 0 18 read-only DAT0 EADC_DAT0 ADC Data Register 0 for Sample Module 0 0x0 read-only n 0x0 0x0 OV Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read. 16 1 read-only 0 Data in RESULT[11:0] is recent conversion result #0 1 Data in RESULT[11:0] is overwrite #1 RESULT ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. 0 16 read-only VALID Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. 17 1 read-only 0 Data in RESULT[11:0] bits is not valid #0 1 Data in RESULT[11:0] bits is valid #1 DAT1 EADC_DAT1 ADC Data Register 1 for Sample Module 1 0x4 read-write n 0x0 0x0 DAT10 EADC_DAT10 ADC Data Register 10 for Sample Module 10 0x28 read-write n 0x0 0x0 DAT11 EADC_DAT11 ADC Data Register 11 for Sample Module 11 0x2C read-write n 0x0 0x0 DAT12 EADC_DAT12 ADC Data Register 12 for Sample Module 12 0x30 read-write n 0x0 0x0 DAT13 EADC_DAT13 ADC Data Register 13 for Sample Module 13 0x34 read-write n 0x0 0x0 DAT14 EADC_DAT14 ADC Data Register 14 for Sample Module 14 0x38 read-write n 0x0 0x0 DAT15 EADC_DAT15 ADC Data Register 15 for Sample Module 15 0x3C read-write n 0x0 0x0 DAT16 EADC_DAT16 ADC Data Register 16 for Sample Module 16 0x40 read-write n 0x0 0x0 DAT17 EADC_DAT17 ADC Data Register 17 for Sample Module 17 0x44 read-write n 0x0 0x0 DAT18 EADC_DAT18 ADC Data Register 18 for Sample Module 18 0x48 read-write n 0x0 0x0 DAT2 EADC_DAT2 ADC Data Register 2 for Sample Module 2 0x8 read-write n 0x0 0x0 DAT3 EADC_DAT3 ADC Data Register 3 for Sample Module 3 0xC read-write n 0x0 0x0 DAT4 EADC_DAT4 ADC Data Register 4 for Sample Module 4 0x10 read-write n 0x0 0x0 DAT5 EADC_DAT5 ADC Data Register 5 for Sample Module 5 0x14 read-write n 0x0 0x0 DAT6 EADC_DAT6 ADC Data Register 6 for Sample Module 6 0x18 read-write n 0x0 0x0 DAT7 EADC_DAT7 ADC Data Register 7 for Sample Module 7 0x1C read-write n 0x0 0x0 DAT8 EADC_DAT8 ADC Data Register 8 for Sample Module 8 0x20 read-write n 0x0 0x0 DAT9 EADC_DAT9 ADC Data Register 9 for Sample Module 9 0x24 read-write n 0x0 0x0 DDAT0 EADC_DDAT0 ADC Double Data Register 0 for Sample Module 0 0x100 read-only n 0x0 0x0 OV Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after EADC_DDAT register is read. 16 1 read-only 0 Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result #0 1 Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite #1 RESULT ADC Conversion Results\nThis field contains 12 bits conversion results.\nWhen the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].\nWhen DMOF (EADC_CTL[9]) is set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12]. 0 16 read-only VALID Valid Flag 17 1 read-only 0 Double data in RESULT (EADC_DDATn[15:0]) is not valid #0 1 Double data in RESULT (EADC_DDATn[15:0]) is valid #1 DDAT1 EADC_DDAT1 ADC Double Data Register 1 for Sample Module 1 0x104 read-write n 0x0 0x0 DDAT2 EADC_DDAT2 ADC Double Data Register 2 for Sample Module 2 0x108 read-write n 0x0 0x0 DDAT3 EADC_DDAT3 ADC Double Data Register 3 for Sample Module 3 0x10C read-write n 0x0 0x0 INTSRC0 EADC_INTSRC0 ADC interrupt 0 Source Enable Control Register. 0xD0 read-write n 0x0 0x0 SPLIE0 Sample Module 0 Interrupt Enable Bit 0 1 read-write 0 Sample Module 0 interrupt Disabled #0 1 Sample Module 0 interrupt Enabled #1 SPLIE1 Sample Module 1 Interrupt Enable Bit 1 1 read-write 0 Sample Module 1 interrupt Disabled #0 1 Sample Module 1 interrupt Enabled #1 SPLIE10 Sample Module 10 Interrupt Enable Bit 10 1 read-write 0 Sample Module 10 interrupt Disabled #0 1 Sample Module 10 interrupt Enabled #1 SPLIE11 Sample Module 11 Interrupt Enable Bit 11 1 read-write 0 Sample Module 11 interrupt Disabled #0 1 Sample Module 11 interrupt Enabled #1 SPLIE12 Sample Module 12 Interrupt Enable Bit 12 1 read-write 0 Sample Module 12 interrupt Disabled #0 1 Sample Module 12 interrupt Enabled #1 SPLIE13 Sample Module 13 Interrupt Enable Bit 13 1 read-write 0 Sample Module 13 interrupt Disabled #0 1 Sample Module 13 interrupt Enabled #1 SPLIE14 Sample Module 14 Interrupt Enable Bit 14 1 read-write 0 Sample Module 14 interrupt Disabled #0 1 Sample Module 14 interrupt Enabled #1 SPLIE15 Sample Module 15 Interrupt Enable Bit 15 1 read-write 0 Sample Module 15 interrupt Disabled #0 1 Sample Module 15 interrupt Enabled #1 SPLIE16 Sample Module 16 Interrupt Enable Bit 16 1 read-write 0 Sample Module 16 interrupt Disabled #0 1 Sample Module 16 interrupt Enabled #1 SPLIE17 Sample Module 17 Interrupt Enable Bit 17 1 read-write 0 Sample Module 17 interrupt Disabled #0 1 Sample Module 17 interrupt Enabled #1 SPLIE18 Sample Module 18 Interrupt Enable Bit 18 1 read-write 0 Sample Module 18 interrupt Disabled #0 1 Sample Module 18 interrupt Enabled #1 SPLIE2 Sample Module 2 Interrupt Enable Bit 2 1 read-write 0 Sample Module 2 interrupt Disabled #0 1 Sample Module 2 interrupt Enabled #1 SPLIE3 Sample Module 3 Interrupt Enable Bit 3 1 read-write 0 Sample Module 3 interrupt Disabled #0 1 Sample Module 3 interrupt Enabled #1 SPLIE4 Sample Module 4 Interrupt Enable Bit 4 1 read-write 0 Sample Module 4 interrupt Disabled #0 1 Sample Module 4 interrupt Enabled #1 SPLIE5 Sample Module 5 Interrupt Enable Bit 5 1 read-write 0 Sample Module 5 interrupt Disabled #0 1 Sample Module 5 interrupt Enabled #1 SPLIE6 Sample Module 6 Interrupt Enable Bit 6 1 read-write 0 Sample Module 6 interrupt Disabled #0 1 Sample Module 6 interrupt Enabled #1 SPLIE7 Sample Module 7 Interrupt Enable Bit 7 1 read-write 0 Sample Module 7 interrupt Disabled #0 1 Sample Module 7 interrupt Enabled #1 SPLIE8 Sample Module 8 Interrupt Enable Bit 8 1 read-write 0 Sample Module 8 interrupt Disabled #0 1 Sample Module 8 interrupt Enabled #1 SPLIE9 Sample Module 9 Interrupt Enable Bit 9 1 read-write 0 Sample Module 9 interrupt Disabled #0 1 Sample Module 9 interrupt Enabled #1 INTSRC1 EADC_INTSRC1 ADC interrupt 1 Source Enable Control Register. 0xD4 read-write n 0x0 0x0 INTSRC2 EADC_INTSRC2 ADC interrupt 2 Source Enable Control Register. 0xD8 read-write n 0x0 0x0 INTSRC3 EADC_INTSRC3 ADC interrupt 3 Source Enable Control Register. 0xDC read-write n 0x0 0x0 OVSTS EADC_OVSTS ADC Sample Module Start of Conversion Overrun Flag Register 0x5C read-write n 0x0 0x0 SPOVF ADC SAMPLE0~18 Overrun Flag\nNote: This bit is cleared by writing 1 to it. 0 19 read-write 0 No sample module event overrun 0 1 Indicates a new sample module event is generated while an old one event is pending 1 PENDSTS EADC_PENDSTS ADC Start of Conversion Pending Flag Register 0x58 read-write n 0x0 0x0 STPF ADC Sample Module 0~18 Start of Conversion Pending Flag\nRead Operation: 0 19 read-write 0 There is no pending conversion for sample module 0 1 Sample module ADC start of conversion is pending. Cear pending flag cancel the conversion for sample module 1 PWRM EADC_PWRM ADC Power Management Register 0x110 -1 read-write n 0x0 0x0 LDOSUT ADC Internal LDO Start-up Time 8 12 read-write PWDMOD ADC Power-down Mode Set this bit field to select ADC Power-down mode when system power-down. Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence user must keep PWMOD consistent each time in power down and start up. 2 2 read-write 0 ADC Deep Power-down mode #00 1 ADC Power down #01 2 ADC Standby mode #10 3 ADC Deep Power-down mode #11 PWUCALEN Power Up Calibration Function Enable Bit\nNote: This bit work together with CALSEL (EADC_CALCTL [3]), see the following\n{PWUCALEN, CALSEL } Description:\nPWUCALEN is 0 and CALSEL is 0: No need to calibrate. \nPWUCALEN is 0 and CALSEL is 1: No need to calibrate.\nPWUCALEN is 1 and CALSEL is 0: Load calibration word when power up.\nPWUCALEN is 1 and CALSEL is 1: Calibrate when power up. 1 1 read-write 0 Calibration function Disabled at power up #0 1 Calibration function Enabled at power up #1 PWUPRDY ADC Power-up Sequence Completed and Ready for Conversion (Read Only) 0 1 read-only 0 ADC is not ready for conversion may be in power down state or in the progress of start up #0 1 ADC is ready for conversion #1 SCTL0 EADC_SCTL0 ADC Sample Module 0 Control Register 0x80 read-write n 0x0 0x0 CHSEL ADC Sample Module Channel Selection 0 4 read-write DBMEN Double Buffer Mode Enable Bit 23 1 read-write 0 Sample has one sample result register (default) #0 1 Sample has two sample result registers #1 EXTFEN ADC External Trigger Falling Edge Enable Bit 5 1 read-write 0 Falling edge Disabled when ADC selects EADC0_ST as trigger source #0 1 Falling edge Enabled when ADC selects EADC0_ST as trigger source #1 EXTREN ADC External Trigger Rising Edge Enable Bit 4 1 read-write 0 Rising edge Disabled when ADC selects EADC0_ST as trigger source #0 1 Rising edge Enabled when ADC selects EADC0_ST as trigger source #1 EXTSMPT ADC Sampling Time Extend\nWhen ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time.\nThe range of start delay time is from 0~255 ADC clock. 24 8 read-write INTPOS Interrupt Flag Position Select 22 1 read-write 0 Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion #0 1 Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion #1 TRGDLYCNT ADC Sample Module Start of Conversion Trigger Delay Time 8 8 read-write TRGDLYDIV ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency: 6 2 read-write 0 ADC_CLK/1 #00 1 ADC_CLK/2 #01 2 ADC_CLK/4 #10 3 ADC_CLK/16 #11 TRGSEL ADC Sample Module Start of Conversion Trigger Source Selection 16 5 read-write SCTL1 EADC_SCTL1 ADC Sample Module 1 Control Register 0x84 read-write n 0x0 0x0 SCTL10 EADC_SCTL10 ADC Sample Module 10 Control Register 0xA8 read-write n 0x0 0x0 SCTL11 EADC_SCTL11 ADC Sample Module 11 Control Register 0xAC read-write n 0x0 0x0 SCTL12 EADC_SCTL12 ADC Sample Module 12 Control Register 0xB0 read-write n 0x0 0x0 SCTL13 EADC_SCTL13 ADC Sample Module 13 Control Register 0xB4 read-write n 0x0 0x0 SCTL14 EADC_SCTL14 ADC Sample Module 14 Control Register 0xB8 read-write n 0x0 0x0 SCTL15 EADC_SCTL15 ADC Sample Module 15 Control Register 0xBC read-write n 0x0 0x0 SCTL16 EADC_SCTL16 ADC Sample Module 16 Control Register 0xC0 read-write n 0x0 0x0 EXTSMPT ADC Sampling Time Extend\nWhen ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend ADC sampling time after trigger source is coming to get enough sampling time.\nThe range of start delay time is from 0~255 ADC clock. 24 8 read-write SCTL17 EADC_SCTL17 ADC Sample Module 17 Control Register 0xC4 read-write n 0x0 0x0 SCTL18 EADC_SCTL18 ADC Sample Module 18 Control Register 0xC8 read-write n 0x0 0x0 SCTL2 EADC_SCTL2 ADC Sample Module 2 Control Register 0x88 read-write n 0x0 0x0 SCTL3 EADC_SCTL3 ADC Sample Module 3 Control Register 0x8C read-write n 0x0 0x0 SCTL4 EADC_SCTL4 ADC Sample Module 4 Control Register 0x90 read-write n 0x0 0x0 CHSEL ADC Sample Module Channel Selection 0 4 read-write EXTFEN ADC External Trigger Falling Edge Enable Bit 5 1 read-write 0 Falling edge Disabled when ADC selects EADC0_ST as trigger source #0 1 Falling edge Enabled when ADC selects EADC0_ST as trigger source #1 EXTREN ADC External Trigger Rising Edge Enable Bit 4 1 read-write 0 Rising edge Disabled when ADC selects EADC0_ST as trigger source #0 1 Rising edge Enabled when ADC selects EADC0_ST as trigger source #1 EXTSMPT ADC Sampling Time Extend\nWhen ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend ADC sampling time after trigger source is coming to get enough sampling time.\nThe range of start delay time is from 0~255 ADC clock. 24 8 read-write INTPOS Interrupt Flag Position Select 22 1 read-write 0 Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion #0 1 Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion #1 TRGDLYCNT ADC Sample Module Start of Conversion Trigger Delay Time 8 8 read-write TRGDLYDIV ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency: 6 2 read-write 0 ADC_CLK/1 #00 1 ADC_CLK/2 #01 2 ADC_CLK/4 #10 3 ADC_CLK/16 #11 TRGSEL ADC Sample Module Start of Conversion Trigger Source Selection 16 5 read-write SCTL5 EADC_SCTL5 ADC Sample Module 5 Control Register 0x94 read-write n 0x0 0x0 SCTL6 EADC_SCTL6 ADC Sample Module 6 Control Register 0x98 read-write n 0x0 0x0 SCTL7 EADC_SCTL7 ADC Sample Module 7 Control Register 0x9C read-write n 0x0 0x0 SCTL8 EADC_SCTL8 ADC Sample Module 8 Control Register 0xA0 read-write n 0x0 0x0 SCTL9 EADC_SCTL9 ADC Sample Module 9 Control Register 0xA4 read-write n 0x0 0x0 STATUS0 EADC_STATUS0 ADC Status Register 0 0xF0 read-only n 0x0 0x0 OV EADC_DAT0~15 Overrun Flag 16 16 read-only VALID EADC_DAT0~15 Data Valid Flag 0 16 read-only STATUS1 EADC_STATUS1 ADC Status Register 1 0xF4 read-only n 0x0 0x0 OV EADC_DAT16~18 Overrun Flag 16 3 read-only VALID EADC_DAT16~18 Data Valid Flag 0 3 read-only STATUS2 EADC_STATUS2 ADC Status Register 2 0xF8 read-write n 0x0 0x0 ADCMPF0 ADC Compare 0 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it. 4 1 read-write 0 Conversion result in EADC_DAT does not meet EADC_CMP0 register setting #0 1 Conversion result in EADC_DAT meets EADC_CMP0 register setting #1 ADCMPF1 ADC Compare 1 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it. 5 1 read-write 0 Conversion result in EADC_DAT does not meet EADC_CMP1 register setting #0 1 Conversion result in EADC_DAT meets EADC_CMP1 register setting #1 ADCMPF2 ADC Compare 2 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it. 6 1 read-write 0 Conversion result in EADC_DAT does not meet EADC_CMP2 register setting #0 1 Conversion result in EADC_DAT meets EADC_CMP2 register setting #1 ADCMPF3 ADC Compare 3 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it. 7 1 read-write 0 Conversion result in EADC_DAT does not meet EADC_CMP3 register setting #0 1 Conversion result in EADC_DAT meets EADC_CMP3 register setting #1 ADCMPO0 ADC Compare 0 Output Status (Read Only)\nThe 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status. 12 1 read-only 0 Conversion result in EADC_DAT less than CMPDAT0 setting #0 1 Conversion result in EADC_DAT great than or equal CMPDAT0 setting #1 ADCMPO1 ADC Compare 1 Output Status (Read Only)\nThe 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status. 13 1 read-only 0 Conversion result in EADC_DAT less than CMPDAT1 setting #0 1 Conversion result in EADC_DAT great than or equal CMPDAT1 setting #1 ADCMPO2 ADC Compare 2 Output Status (Read Only)\nThe 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status. 14 1 read-only 0 Conversion result in EADC_DAT less than CMPDAT2 setting #0 1 Conversion result in EADC_DAT great than or equal CMPDAT2 setting #1 ADCMPO3 ADC Compare 3 Output Status (Read Only)\nThe 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status. 15 1 read-only 0 Conversion result in EADC_DAT less than CMPDAT3 setting #0 1 Conversion result in EADC_DAT great than or equal CMPDAT3 setting #1 ADIF0 ADC ADINT0 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an ADC conversion of specific sample module has been completed 0 1 read-write 0 No ADINT0 interrupt pulse received #0 1 ADINT0 interrupt pulse has been received #1 ADIF1 ADC ADINT1 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an ADC conversion of specific sample module has been completed 1 1 read-write 0 No ADINT1 interrupt pulse received #0 1 ADINT1 interrupt pulse has been received #1 ADIF2 ADC ADINT2 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it. \nNote2:This bit indicates whether an ADC conversion of specific sample module has been completed 2 1 read-write 0 No ADINT2 interrupt pulse received #0 1 ADINT2 interrupt pulse has been received #1 ADIF3 ADC ADINT3 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an ADC conversion of specific sample module has been completed 3 1 read-write 0 No ADINT3 interrupt pulse received #0 1 ADINT3 interrupt pulse has been received #1 ADOVIF All ADC Interrupt Flag Overrun Bits Check (Read Only)\nNote: This bit will keep 1 when any ADOVIFn Flag is equal to 1. 24 1 read-only 0 None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1 #0 1 Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1 #1 ADOVIF0 ADC ADINT0 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it. 8 1 read-write 0 ADINT0 interrupt flag is not overwritten to 1 #0 1 ADINT0 interrupt flag is overwritten to 1 #1 ADOVIF1 ADC ADINT1 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it. 9 1 read-write 0 ADINT1 interrupt flag is not overwritten to 1 #0 1 ADINT1 interrupt flag is overwritten to 1 #1 ADOVIF2 ADC ADINT2 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it. 10 1 read-write 0 ADINT2 interrupt flag is not overwritten to 1 #0 1 ADINT2 interrupt flag is s overwritten to 1 #1 ADOVIF3 ADC ADINT3 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it. 11 1 read-write 0 ADINT3 interrupt flag is not overwritten to 1 #0 1 ADINT3 interrupt flag is overwritten to 1 #1 AOV for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any OVn Flag is equal to 1. 27 1 read-only 0 None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1 #0 1 Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1 #1 AVALID for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only)\nNote: This bit will keep 1 when any VALIDn Flag is equal to 1. 26 1 read-only 0 None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1 #0 1 Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1 #1 BUSY Busy/Idle (Read Only) 23 1 read-only 0 EADC is in idle state #0 1 EADC is busy at conversion #1 CHANNEL Current Conversion Channel (Read Only) 16 5 read-only STOVF for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any SPOVFn Flag is equal to 1. 25 1 read-only 0 None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1 #0 1 Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1 #1 STATUS3 EADC_STATUS3 ADC Status Register 3 0xFC -1 read-only n 0x0 0x0 CURSPL ADC Current Sample Module (Read Only)\nThis register shows the current ADC is controlled by which sample module control logic modules.\nIf the ADC is Idle, the bit filed will set to 0x1F. 0 5 read-only SWTRG EADC_SWTRG ADC Sample Module Software Start Register 0x54 write-only n 0x0 0x0 SWTRG ADC Sample Module 0~18 Software Force to Start ADC Conversion\nNote: After writing this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion. If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. 0 19 write-only 0 No effect 0 1 Cause an ADC conversion when the priority is given to sample module 1 EBI EBI Register Map EBI 0x0 0x0 0x8 registers n 0x10 0x8 registers n 0x20 0x8 registers n CTL0 EBI_CTL0 External Bus Interface Bank0 Control Register 0x0 read-write n 0x0 0x0 ADSEPEN EBI Address/Data Bus Separating Mode Enable Bit 3 1 read-write 0 Address/Data Bus Separating Mode Disabled #0 1 Address/Data Bus Separating Mode Enabled #1 CACCESS Continuous Data Access Mode\nWhen con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. 4 1 read-write 0 Continuous data access mode Disabled #0 1 Continuous data access mode Enabled #1 CSPOLINV Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS). 2 1 read-write 0 Chip select pin (EBI_nCS) is active low #0 1 Chip select pin (EBI_nCS) is active high #1 DW16 EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit. 1 1 read-write 0 EBI data width is 8-bit #0 1 EBI data width is 16-bit #1 EN EBI Enable Bit\nThis bit is the functional enable bit for EBI. 0 1 read-write 0 EBI function Disabled #0 1 EBI function Enabled #1 MCLKDIV External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: 8 3 read-write 0 HCLK/1 #000 1 HCLK/2 #001 2 HCLK/4 #010 3 HCLK/8 #011 4 HCLK/16 #100 5 HCLK/32 #101 6 HCLK/64 #110 7 HCLK/128 #111 TALE Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field only available in EBI_CTL0 register 16 3 read-write WBUFEN EBI Write Buffer Enable Bit\nNote: This bit only available in EBI_CTL0 register 24 1 read-write 0 EBI write buffer Disabled #0 1 EBI write buffer Enabled #1 CTL1 EBI_CTL1 External Bus Interface Bank1 Control Register 0x10 read-write n 0x0 0x0 CTL2 EBI_CTL2 External Bus Interface Bank2 Control Register 0x20 read-write n 0x0 0x0 TCTL0 EBI_TCTL0 External Bus Interface Bank0 Timing Control Register 0x4 read-write n 0x0 0x0 R2R Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nWhen read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. 24 4 read-write RAHDOFF Access Hold Time Disable Control When Read 22 1 read-write 0 Data Access Hold Time (tAHD) during EBI reading Enabled #0 1 Data Access Hold Time (tAHD) during EBI reading Disabled #1 TACC EBI Data Access Time\nTACC defines data access time (tACC). 3 5 read-write TAHD EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD). 8 3 read-write W2X Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nWhen write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state. 12 4 read-write WAHDOFF Access Hold Time Disable Control When Write 23 1 read-write 0 Data Access Hold Time (tAHD) during EBI writing Enabled #0 1 Data Access Hold Time (tAHD) during EBI writing Disabled #1 TCTL1 EBI_TCTL1 External Bus Interface Bank1 Timing Control Register 0x14 read-write n 0x0 0x0 TCTL2 EBI_TCTL2 External Bus Interface Bank2 Timing Control Register 0x24 read-write n 0x0 0x0 ECAP0 ECAP Register Map ECAP 0x0 0x0 0x20 registers n ECAP_CNT ECAP_CNT Input Capture Counter (24-bit up counter) 0x0 read-write n 0x0 0x0 CNT Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from thme clock divider. 0 24 read-write ECAP_CNTCMP ECAP_CNTCMP Input Capture Compare Register 0x10 read-write n 0x0 0x0 CNTCMP Input Capture Counter Compare Register 0 24 read-write ECAP_CTL0 ECAP_CTL0 Input Capture Control Register 0 0x14 read-write n 0x0 0x0 CAPEN Input Capture Timer/Counter Enable Control 29 1 read-write 0 Input Capture function Disabled #0 1 Input Capture function Enabled #1 CAPIEN0 Input Capture Channel 0 Interrupt Enable Control 16 1 read-write 0 The flag CAPTF0 can trigger Input Capture interrupt Disabled #0 1 The flag CAPTF0 can trigger Input Capture interrupt Enabled #1 CAPIEN1 Input Capture Channel 1 Interrupt Enable Control 17 1 read-write 0 The flag CAPTF1 can trigger Input Capture interrupt Disabled #0 1 The flag CAPTF1 can trigger Input Capture interrupt Enabled #1 CAPIEN2 Input Capture Channel 2 Interrupt Enable Control 18 1 read-write 0 The flag CAPTF2 can trigger Input Capture interrupt Disabled #0 1 The flag CAPTF2 can trigger Input Capture interrupt Enabled #1 CAPNFDIS Input Capture Noise Filter Disable Control 3 1 read-write 0 Noise filter of Input Capture Enabled #0 1 Noise filter of Input Capture Disabled (Bypass) #1 CAPSEL0 CAP0 Input Source Selection 8 2 read-write 0 CAP0 input is from port pin ICAP0 #00 1 Reserved #01 2 CAP0 input is from signal CHA of QEI controller unit n #10 3 Reserved #11 CAPSEL1 CAP1 Input Source Selection 10 2 read-write 0 CAP1 input is from port pin ICAP1 #00 1 Reserved #01 2 CAP1 input is from signal CHB of QEI controller unit n #10 3 Reserved #11 CAPSEL2 CAP2 Input Source Selection 12 2 read-write 0 CAP2 input is from port pin ICAP2 #00 1 Reserved #01 2 CAP2 input is from signal CHX of QEI controller unit n #10 3 Reserved #11 CMPCLREN Input Capture Counter Cleared by Compare-match Control 25 1 read-write 0 Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled #0 1 Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled #1 CMPEN Compare Function Enable Control\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set. 28 1 read-write 0 The compare function Disabled #0 1 The compare function Enabled #1 CMPIEN CAPCMPF Trigger Input Capture Interrupt Enable Control 21 1 read-write 0 The flag CAPCMPF can trigger Input Capture interrupt Disabled #0 1 The flag CAPCMPF can trigger Input Capture interrupt Enabled #1 CNTEN Input Capture Counter Start Counting Control\nSetting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the . 24 1 read-write 0 ECAP_CNT stop counting #0 1 ECAP_CNT starts up-counting #1 IC0EN Port Pin IC0 Input to Input Capture Unit Enable Control 4 1 read-write 0 IC0 input to Input Capture Unit Disabled #0 1 IC0 input to Input Capture Unit Enabled #1 IC1EN Port Pin IC1 Input to Input Capture Unit Enable Control 5 1 read-write 0 IC1 input to Input Capture Unit Disabled #0 1 IC1 input to Input Capture Unit Enabled #1 IC2EN Port Pin IC2 Input to Input Capture Unit Enable Control 6 1 read-write 0 IC2 input to Input Capture Unit Disabled #0 1 IC2 input to Input Capture Unit Enabled #1 NFCLKSEL Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock 0 3 read-write 0 CAP_CLK #000 1 CAP_CLK/2 #001 2 CAP_CLK/4 #010 3 CAP_CLK/16 #011 4 CAP_CLK/32 #100 5 CAP_CLK/64 #101 OVIEN CAPOVF Trigger Input Capture Interrupt Enable Control 20 1 read-write 0 The flag CAPOVF can trigger Input Capture interrupt Disabled #0 1 The flag CAPOVF can trigger Input Capture interrupt Enabled #1 ECAP_CTL1 ECAP_CTL1 Input Capture Control Register 1 0x18 read-write n 0x0 0x0 CAP0CLREN Capture Counter Cleared by Capture Event0 Control 20 1 read-write 0 Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled #0 1 Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled #1 CAP0RLDEN Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit 8 1 read-write 0 The reload triggered by Event CAPTE0 Disabled #0 1 The reload triggered by Event CAPTE0 Enabled #1 CAP1CLREN Capture Counter Cleared by Capture Event1 Control 21 1 read-write 0 Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled #0 1 Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled #1 CAP1RLDEN Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit 9 1 read-write 0 The reload triggered by Event CAPTE1 Disabled #0 1 The reload triggered by Event CAPTE1 Enabled #1 CAP2CLREN Capture Counter Cleared by Capture Event2 Control 22 1 read-write 0 Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled #0 1 Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled #1 CAP2RLDEN Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit 10 1 read-write 0 The reload triggered by Event CAPTE2 Disabled #0 1 The reload triggered by Event CAPTE2 Enabled #1 CLKSEL Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]. 12 3 read-write 0 CAP_CLK/1 #000 1 CAP_CLK/4 #001 2 CAP_CLK/16 #010 3 CAP_CLK/32 #011 4 CAP_CLK/64 #100 5 CAP_CLK/96 #101 6 CAP_CLK/112 #110 7 CAP_CLK/128 #111 CNTSRCSEL Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source. 16 2 read-write 0 CAP_CLK (default) #00 1 CAP0 #01 2 CAP1 #10 3 CAP2 #11 EDGESEL0 Channel 0 Captured Edge Selection\nInput capture0 can detect falling edge change only, rising edge change only or both edge change 0 2 read-write 0 Detect rising edge only #00 1 Detect falling edge only.\nDetect both rising and falling edge #01 EDGESEL1 Channel 1 Captured Edge Selection\nInput capture1 can detect falling edge change only, rising edge change only or both edge change 2 2 read-write 0 Detect rising edge only #00 1 Detect falling edge only.\nDetect both rising and falling edge #01 EDGESEL2 Channel 2 Captured Edge Selection\nInput capture2 can detect falling edge change only, rising edge change only or both edge changes 4 2 read-write 0 Detect rising edge only #00 1 Detect falling edge only.\nDetect both rising and falling edge #01 OVRLDEN Capture Counter's Reload Function Triggered by Overflow Enable Bit 11 1 read-write 0 The reload triggered by CAPOV Disabled #0 1 The reload triggered by CAPOV Enabled #1 ECAP_HLD0 ECAP_HLD0 Input Capture Hold Register 0 0x4 read-write n 0x0 0x0 HOLD Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. 0 24 read-write ECAP_HLD1 ECAP_HLD1 Input Capture Hold Register 1 0x8 read-write n 0x0 0x0 ECAP_HLD2 ECAP_HLD2 Input Capture Hold Register 2 0xC read-write n 0x0 0x0 ECAP_STATUS ECAP_STATUS Input Capture Status Register 0x1C read-write n 0x0 0x0 CAP0 Value of Input Channel 0, CAP0 (Read Only)\nReflecting the value of input channel 0, CAP0\nNote: The bit is read only and write is ignored. 8 1 read-only CAP1 Value of Input Channel 1, CAP1 (Read Only)\nReflecting the value of input channel 1, CAP1\nNote: The bit is read only and write is ignored. 9 1 read-only CAP2 Value of Input Channel 2, CAP2 (Read Only)\nReflecting the value of input channel 2, CAP2.\nNote: The bit is read only and write is ignored. 10 1 read-only CAPCMPF Input Capture Compare-match Flag\nIf the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it. 4 1 read-write 0 ECAP_CNT has not matched ECAP_CNTCMP value since last clear #0 1 ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear #1 CAPOVF Input Capture Counter Overflow Flag\nFlag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\nNote: This bit is only cleared by writing 1 to it. 5 1 read-write 0 No overflow event has occurred since last clear #0 1 Overflow event(s) has/have occurred since last clear #1 CAPTF0 Input Capture Channel 0 Triggered Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. \nNote: This bit is only cleared by writing 1 to it. 0 1 read-write 0 No valid edge change has been detected at CAP0 input since last clear #0 1 At least a valid edge change has been detected at CAP0 input since last clear #1 CAPTF1 Input Capture Channel 1 Triggered Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. \nNote: This bit is only cleared by writing 1 to it. 1 1 read-write 0 No valid edge change has been detected at CAP1 input since last clear #0 1 At least a valid edge change has been detected at CAP1 input since last clear #1 CAPTF2 Input Capture Channel 2 Triggered Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. \nNote: This bit is only cleared by writing 1 to it. 2 1 read-write 0 No valid edge change has been detected at CAP2 input since last clear #0 1 At least a valid edge change has been detected at CAP2 input since last clear #1 ECAP1 ECAP Register Map ECAP 0x0 0x0 0x20 registers n ECAP_CNT ECAP_CNT Input Capture Counter (24-bit up counter) 0x0 read-write n 0x0 0x0 CNT Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from thme clock divider. 0 24 read-write ECAP_CNTCMP ECAP_CNTCMP Input Capture Compare Register 0x10 read-write n 0x0 0x0 CNTCMP Input Capture Counter Compare Register 0 24 read-write ECAP_CTL0 ECAP_CTL0 Input Capture Control Register 0 0x14 read-write n 0x0 0x0 CAPEN Input Capture Timer/Counter Enable Control 29 1 read-write 0 Input Capture function Disabled #0 1 Input Capture function Enabled #1 CAPIEN0 Input Capture Channel 0 Interrupt Enable Control 16 1 read-write 0 The flag CAPTF0 can trigger Input Capture interrupt Disabled #0 1 The flag CAPTF0 can trigger Input Capture interrupt Enabled #1 CAPIEN1 Input Capture Channel 1 Interrupt Enable Control 17 1 read-write 0 The flag CAPTF1 can trigger Input Capture interrupt Disabled #0 1 The flag CAPTF1 can trigger Input Capture interrupt Enabled #1 CAPIEN2 Input Capture Channel 2 Interrupt Enable Control 18 1 read-write 0 The flag CAPTF2 can trigger Input Capture interrupt Disabled #0 1 The flag CAPTF2 can trigger Input Capture interrupt Enabled #1 CAPNFDIS Input Capture Noise Filter Disable Control 3 1 read-write 0 Noise filter of Input Capture Enabled #0 1 Noise filter of Input Capture Disabled (Bypass) #1 CAPSEL0 CAP0 Input Source Selection 8 2 read-write 0 CAP0 input is from port pin ICAP0 #00 1 Reserved #01 2 CAP0 input is from signal CHA of QEI controller unit n #10 3 Reserved #11 CAPSEL1 CAP1 Input Source Selection 10 2 read-write 0 CAP1 input is from port pin ICAP1 #00 1 Reserved #01 2 CAP1 input is from signal CHB of QEI controller unit n #10 3 Reserved #11 CAPSEL2 CAP2 Input Source Selection 12 2 read-write 0 CAP2 input is from port pin ICAP2 #00 1 Reserved #01 2 CAP2 input is from signal CHX of QEI controller unit n #10 3 Reserved #11 CMPCLREN Input Capture Counter Cleared by Compare-match Control 25 1 read-write 0 Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled #0 1 Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled #1 CMPEN Compare Function Enable Control\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set. 28 1 read-write 0 The compare function Disabled #0 1 The compare function Enabled #1 CMPIEN CAPCMPF Trigger Input Capture Interrupt Enable Control 21 1 read-write 0 The flag CAPCMPF can trigger Input Capture interrupt Disabled #0 1 The flag CAPCMPF can trigger Input Capture interrupt Enabled #1 CNTEN Input Capture Counter Start Counting Control\nSetting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the . 24 1 read-write 0 ECAP_CNT stop counting #0 1 ECAP_CNT starts up-counting #1 IC0EN Port Pin IC0 Input to Input Capture Unit Enable Control 4 1 read-write 0 IC0 input to Input Capture Unit Disabled #0 1 IC0 input to Input Capture Unit Enabled #1 IC1EN Port Pin IC1 Input to Input Capture Unit Enable Control 5 1 read-write 0 IC1 input to Input Capture Unit Disabled #0 1 IC1 input to Input Capture Unit Enabled #1 IC2EN Port Pin IC2 Input to Input Capture Unit Enable Control 6 1 read-write 0 IC2 input to Input Capture Unit Disabled #0 1 IC2 input to Input Capture Unit Enabled #1 NFCLKSEL Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock 0 3 read-write 0 CAP_CLK #000 1 CAP_CLK/2 #001 2 CAP_CLK/4 #010 3 CAP_CLK/16 #011 4 CAP_CLK/32 #100 5 CAP_CLK/64 #101 OVIEN CAPOVF Trigger Input Capture Interrupt Enable Control 20 1 read-write 0 The flag CAPOVF can trigger Input Capture interrupt Disabled #0 1 The flag CAPOVF can trigger Input Capture interrupt Enabled #1 ECAP_CTL1 ECAP_CTL1 Input Capture Control Register 1 0x18 read-write n 0x0 0x0 CAP0CLREN Capture Counter Cleared by Capture Event0 Control 20 1 read-write 0 Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled #0 1 Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled #1 CAP0RLDEN Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit 8 1 read-write 0 The reload triggered by Event CAPTE0 Disabled #0 1 The reload triggered by Event CAPTE0 Enabled #1 CAP1CLREN Capture Counter Cleared by Capture Event1 Control 21 1 read-write 0 Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled #0 1 Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled #1 CAP1RLDEN Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit 9 1 read-write 0 The reload triggered by Event CAPTE1 Disabled #0 1 The reload triggered by Event CAPTE1 Enabled #1 CAP2CLREN Capture Counter Cleared by Capture Event2 Control 22 1 read-write 0 Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled #0 1 Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled #1 CAP2RLDEN Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit 10 1 read-write 0 The reload triggered by Event CAPTE2 Disabled #0 1 The reload triggered by Event CAPTE2 Enabled #1 CLKSEL Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]. 12 3 read-write 0 CAP_CLK/1 #000 1 CAP_CLK/4 #001 2 CAP_CLK/16 #010 3 CAP_CLK/32 #011 4 CAP_CLK/64 #100 5 CAP_CLK/96 #101 6 CAP_CLK/112 #110 7 CAP_CLK/128 #111 CNTSRCSEL Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source. 16 2 read-write 0 CAP_CLK (default) #00 1 CAP0 #01 2 CAP1 #10 3 CAP2 #11 EDGESEL0 Channel 0 Captured Edge Selection\nInput capture0 can detect falling edge change only, rising edge change only or both edge change 0 2 read-write 0 Detect rising edge only #00 1 Detect falling edge only.\nDetect both rising and falling edge #01 EDGESEL1 Channel 1 Captured Edge Selection\nInput capture1 can detect falling edge change only, rising edge change only or both edge change 2 2 read-write 0 Detect rising edge only #00 1 Detect falling edge only.\nDetect both rising and falling edge #01 EDGESEL2 Channel 2 Captured Edge Selection\nInput capture2 can detect falling edge change only, rising edge change only or both edge changes 4 2 read-write 0 Detect rising edge only #00 1 Detect falling edge only.\nDetect both rising and falling edge #01 OVRLDEN Capture Counter's Reload Function Triggered by Overflow Enable Bit 11 1 read-write 0 The reload triggered by CAPOV Disabled #0 1 The reload triggered by CAPOV Enabled #1 ECAP_HLD0 ECAP_HLD0 Input Capture Hold Register 0 0x4 read-write n 0x0 0x0 HOLD Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. 0 24 read-write ECAP_HLD1 ECAP_HLD1 Input Capture Hold Register 1 0x8 read-write n 0x0 0x0 ECAP_HLD2 ECAP_HLD2 Input Capture Hold Register 2 0xC read-write n 0x0 0x0 ECAP_STATUS ECAP_STATUS Input Capture Status Register 0x1C read-write n 0x0 0x0 CAP0 Value of Input Channel 0, CAP0 (Read Only)\nReflecting the value of input channel 0, CAP0\nNote: The bit is read only and write is ignored. 8 1 read-only CAP1 Value of Input Channel 1, CAP1 (Read Only)\nReflecting the value of input channel 1, CAP1\nNote: The bit is read only and write is ignored. 9 1 read-only CAP2 Value of Input Channel 2, CAP2 (Read Only)\nReflecting the value of input channel 2, CAP2.\nNote: The bit is read only and write is ignored. 10 1 read-only CAPCMPF Input Capture Compare-match Flag\nIf the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it. 4 1 read-write 0 ECAP_CNT has not matched ECAP_CNTCMP value since last clear #0 1 ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear #1 CAPOVF Input Capture Counter Overflow Flag\nFlag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\nNote: This bit is only cleared by writing 1 to it. 5 1 read-write 0 No overflow event has occurred since last clear #0 1 Overflow event(s) has/have occurred since last clear #1 CAPTF0 Input Capture Channel 0 Triggered Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. \nNote: This bit is only cleared by writing 1 to it. 0 1 read-write 0 No valid edge change has been detected at CAP0 input since last clear #0 1 At least a valid edge change has been detected at CAP0 input since last clear #1 CAPTF1 Input Capture Channel 1 Triggered Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. \nNote: This bit is only cleared by writing 1 to it. 1 1 read-write 0 No valid edge change has been detected at CAP1 input since last clear #0 1 At least a valid edge change has been detected at CAP1 input since last clear #1 CAPTF2 Input Capture Channel 2 Triggered Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. \nNote: This bit is only cleared by writing 1 to it. 2 1 read-write 0 No valid edge change has been detected at CAP2 input since last clear #0 1 At least a valid edge change has been detected at CAP2 input since last clear #1 EPWM0 EPWM Register Map EPWM 0x0 0x0 0x2C registers n 0x110 0x14 registers n 0x130 0x18 registers n 0x150 0xC registers n 0x200 0x4C registers n 0x250 0x8 registers n 0x30 0x18 registers n 0x304 0x4C registers n 0x50 0x18 registers n 0x70 0xC registers n 0x80 0xC registers n 0x90 0x18 registers n 0xB0 0x40 registers n 0xF4 0x18 registers n EPWM_AINTEN EPWM_AINTEN EPWM Accumulator Interrupt Enable Register 0x154 read-write n 0x0 0x0 IFAIEN0 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 0 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN1 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN2 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 2 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN3 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 3 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN4 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 4 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN5 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 5 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 EPWM_AINTSTS EPWM_AINTSTS EPWM Accumulator Interrupt Flag Register 0x150 read-write n 0x0 0x0 IFAIF0 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 0 1 read-write IFAIF1 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1 1 read-write IFAIF2 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 2 1 read-write IFAIF3 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 3 1 read-write IFAIF4 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 4 1 read-write IFAIF5 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 5 1 read-write EPWM_APDMACTL EPWM_APDMACTL EPWM Accumulator PDMA Control Register 0x158 read-write n 0x0 0x0 APDMAEN0 Channel N Accumulator PDMA Enable Bits 0 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN1 Channel N Accumulator PDMA Enable Bits 1 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN2 Channel N Accumulator PDMA Enable Bits 2 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN3 Channel N Accumulator PDMA Enable Bits 3 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN4 Channel N Accumulator PDMA Enable Bits 4 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN5 Channel N Accumulator PDMA Enable Bits 5 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 EPWM_BNF EPWM_BNF EPWM Brake Noise Filter Register 0xC0 read-write n 0x0 0x0 BK0SRC Brake 0 Pin Source Select\nFor EPWM0 setting: 16 1 read-write 0 Brake 0 pin source come from EPWM0_BRAKE0.\nBrake 0 pin source come from EPWM1_BRAKE0 #0 1 Brake 0 pin source come from EPWM1_BRAKE0.\nBrake 0 pin source come from EPWM0_BRAKE0 #1 BK1SRC Brake 1 Pin Source Select\nFor EPWM0 setting: 24 1 read-write 0 Brake 1 pin source come from EPWM0_BRAKE1.\nBrake 1 pin source come from EPWM1_BRAKE1 #0 1 Brake 1 pin source come from EPWM1_BRAKE1.\nBrake 1 pin source come from EPWM0_BRAKE1 #1 BRK0FCNT Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. 4 3 read-write BRK0NFEN EPWM Brake 0 Noise Filter Enable Bit 0 1 read-write 0 Noise filter of EPWM Brake 0 Disabled #0 1 Noise filter of EPWM Brake 0 Enabled #1 BRK0NFSEL Brake 0 Edge Detector Filter Clock Selection 1 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK0PINV Brake 0 Pin Inverse 7 1 read-write 0 brake pin event will be detected if EPWMx BRAKE0 pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 brake pin event will be detected if EPWMx BRAKE0 pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 BRK1FCNT Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 12 3 read-write BRK1NFEN EPWM Brake 1 Noise Filter Enable Bit 8 1 read-write 0 Noise filter of EPWM Brake 1 Disabled #0 1 Noise filter of EPWM Brake 1 Enabled #1 BRK1NFSEL Brake 1 Edge Detector Filter Clock Selection 9 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK1PINV Brake 1 Pin Inverse 15 1 read-write 0 brake pin event will be detected if EPWMx BRAKE1 pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 brake pin event will be detected if EPWMx BRAKE1 pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 EPWM_BRKCTL0_1 EPWM_BRKCTL0_1 EPWM Brake Edge Detect Control Register 0/1 0xC8 read-write n 0x0 0x0 BRKAEVEN EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 16 2 read-write 0 EPWMx brake event will not affect even channels output #00 1 EPWM even channel output tri-state when EPWMx brake event happened #01 2 EPWM even channel output low level when EPWMx brake event happened #10 3 EPWM even channel output high level when EPWMx brake event happened #11 BRKAODD EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 18 2 read-write 0 EPWMx brake event will not affect odd channels output #00 1 EPWM odd channel output tri-state when EPWMx brake event happened #01 2 EPWM odd channel output low level when EPWMx brake event happened #10 3 EPWM odd channel output high level when EPWMx brake event happened #11 BRKP0EEN Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 EPWMx_BRAKE0 pin as edge-detect brake source Disabled #0 1 EPWMx_BRAKE0 pin as edge-detect brake source Enabled #1 BRKP0LEN Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 EPWMx_BRAKE0 pin as level-detect brake source Disabled #0 1 EPWMx_BRAKE0 pin as level-detect brake source Enabled #1 BRKP1EEN Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 EPWMx_BRAKE1 pin as edge-detect brake source Disabled #0 1 EPWMx_BRAKE1 pin as edge-detect brake source Enabled #1 BRKP1LEN Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 EPWMx_BRAKE1 pin as level-detect brake source Disabled #0 1 EPWMx_BRAKE1 pin as level-detect brake source Enabled #1 CPO0EBEN Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 ACMP0_O as edge-detect brake source Disabled #0 1 ACMP0_O as edge-detect brake source Enabled #1 CPO0LBEN Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 ACMP0_O as level-detect brake source Disabled #0 1 ACMP0_O as level-detect brake source Enabled #1 CPO1EBEN Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 ACMP1_O as edge-detect brake source Disabled #0 1 ACMP1_O as edge-detect brake source Enabled #1 CPO1LBEN Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 ACMP1_O as level-detect brake source Disabled #0 1 ACMP1_O as level-detect brake source Enabled #1 EADCEBEN Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 20 1 read-write 0 EADCRM as edge-detect brake source Disabled #0 1 EADCRM as edge-detect brake source Enabled #1 EADCLBEN Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 28 1 read-write 0 EADCRM as level-detect brake source Disabled #0 1 EADCRM as level-detect brake source Enabled #1 SYSEBEN Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 7 1 read-write 0 System Fail condition as edge-detect brake source Disabled #0 1 System Fail condition as edge-detect brake source Enabled #1 SYSLBEN Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 15 1 read-write 0 System Fail condition as level-detect brake source Disabled #0 1 System Fail condition as level-detect brake source Enabled #1 EPWM_BRKCTL2_3 EPWM_BRKCTL2_3 EPWM Brake Edge Detect Control Register 2/3 0xCC read-write n 0x0 0x0 EPWM_BRKCTL4_5 EPWM_BRKCTL4_5 EPWM Brake Edge Detect Control Register 4/5 0xD0 read-write n 0x0 0x0 EPWM_CAPCTL EPWM_CAPCTL EPWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPEN0 Capture Function Enable Bits 0 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN1 Capture Function Enable Bits 1 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN2 Capture Function Enable Bits 2 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN3 Capture Function Enable Bits 3 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN4 Capture Function Enable Bits 4 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN5 Capture Function Enable Bits 5 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPINV0 Capture Inverter Enable Bits 8 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV1 Capture Inverter Enable Bits 9 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV2 Capture Inverter Enable Bits 10 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV3 Capture Inverter Enable Bits 11 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV4 Capture Inverter Enable Bits 12 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV5 Capture Inverter Enable Bits 13 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 FCRLDEN0 Falling Capture Reload Enable Bits 24 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN1 Falling Capture Reload Enable Bits 25 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN2 Falling Capture Reload Enable Bits 26 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN3 Falling Capture Reload Enable Bits 27 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN4 Falling Capture Reload Enable Bits 28 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN5 Falling Capture Reload Enable Bits 29 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 RCRLDEN0 Rising Capture Reload Enable Bits 16 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN1 Rising Capture Reload Enable Bits 17 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN2 Rising Capture Reload Enable Bits 18 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN3 Rising Capture Reload Enable Bits 19 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN4 Rising Capture Reload Enable Bits 20 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN5 Rising Capture Reload Enable Bits 21 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 EPWM_CAPIEN EPWM_CAPIEN EPWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIEN0 EPWM Capture Falling Latch Interrupt Enable Bits 8 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN1 EPWM Capture Falling Latch Interrupt Enable Bits 9 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN2 EPWM Capture Falling Latch Interrupt Enable Bits 10 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN3 EPWM Capture Falling Latch Interrupt Enable Bits 11 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN4 EPWM Capture Falling Latch Interrupt Enable Bits 12 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN5 EPWM Capture Falling Latch Interrupt Enable Bits 13 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPRIEN0 EPWM Capture Rising Latch Interrupt Enable Bits 0 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN1 EPWM Capture Rising Latch Interrupt Enable Bits 1 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN2 EPWM Capture Rising Latch Interrupt Enable Bits 2 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN3 EPWM Capture Rising Latch Interrupt Enable Bits 3 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN4 EPWM Capture Rising Latch Interrupt Enable Bits 4 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN5 EPWM Capture Rising Latch Interrupt Enable Bits 5 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 EPWM_CAPIF EPWM_CAPIF EPWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CFLIF0 EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 8 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF1 EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 9 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF2 EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 10 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF3 EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 11 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF4 EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 12 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF5 EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 13 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CRLIF0 EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 0 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF1 EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 1 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF2 EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 2 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF3 EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 3 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF4 EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 4 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF5 EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 5 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 EPWM_CAPINEN EPWM_CAPINEN EPWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINEN0 Capture Input Enable Bits 0 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN1 Capture Input Enable Bits 1 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN2 Capture Input Enable Bits 2 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN3 Capture Input Enable Bits 3 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN4 Capture Input Enable Bits 4 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN5 Capture Input Enable Bits 5 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 EPWM_CAPSTS EPWM_CAPSTS EPWM Capture Status Register 0x208 read-only n 0x0 0x0 CFLIFOV0 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 8 1 read-only CFLIFOV1 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 9 1 read-only CFLIFOV2 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 10 1 read-only CFLIFOV3 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 11 1 read-only CFLIFOV4 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 12 1 read-only CFLIFOV5 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 13 1 read-only CRLIFOV0 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 0 1 read-only CRLIFOV1 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 1 1 read-only CRLIFOV2 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 2 1 read-only CRLIFOV3 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 3 1 read-only CRLIFOV4 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 4 1 read-only CRLIFOV5 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 5 1 read-only EPWM_CLKPSC0_1 EPWM_CLKPSC0_1 EPWM Clock Prescale Register 0/1 0x14 read-write n 0x0 0x0 CLKPSC EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1). 0 12 read-write EPWM_CLKPSC2_3 EPWM_CLKPSC2_3 EPWM Clock Prescale Register 2/3 0x18 read-write n 0x0 0x0 EPWM_CLKPSC4_5 EPWM_CLKPSC4_5 EPWM Clock Prescale Register 4/5 0x1C read-write n 0x0 0x0 EPWM_CLKSRC EPWM_CLKSRC EPWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 EPWM_CH01 External Clock Source Select 0 3 read-write 0 EPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC2 EPWM_CH23 External Clock Source Select 8 3 read-write 0 EPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC4 EPWM_CH45 External Clock Source Select 16 3 read-write 0 EPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 EPWM_CMPBUF0 EPWM_CMPBUF0 EPWM CMPDAT0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register. 0 16 read-only EPWM_CMPBUF1 EPWM_CMPBUF1 EPWM CMPDAT1 Buffer 0x320 read-write n 0x0 0x0 EPWM_CMPBUF2 EPWM_CMPBUF2 EPWM CMPDAT2 Buffer 0x324 read-write n 0x0 0x0 EPWM_CMPBUF3 EPWM_CMPBUF3 EPWM CMPDAT3 Buffer 0x328 read-write n 0x0 0x0 EPWM_CMPBUF4 EPWM_CMPBUF4 EPWM CMPDAT4 Buffer 0x32C read-write n 0x0 0x0 EPWM_CMPBUF5 EPWM_CMPBUF5 EPWM CMPDAT5 Buffer 0x330 read-write n 0x0 0x0 EPWM_CMPDAT0 EPWM_CMPDAT0 EPWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMP EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform, interrupt and trigger EADC/DAC.\nIn independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. 0 16 read-write EPWM_CMPDAT1 EPWM_CMPDAT1 EPWM Comparator Register 1 0x54 read-write n 0x0 0x0 EPWM_CMPDAT2 EPWM_CMPDAT2 EPWM Comparator Register 2 0x58 read-write n 0x0 0x0 EPWM_CMPDAT3 EPWM_CMPDAT3 EPWM Comparator Register 3 0x5C read-write n 0x0 0x0 EPWM_CMPDAT4 EPWM_CMPDAT4 EPWM Comparator Register 4 0x60 read-write n 0x0 0x0 EPWM_CMPDAT5 EPWM_CMPDAT5 EPWM Comparator Register 5 0x64 read-write n 0x0 0x0 EPWM_CNT0 EPWM_CNT0 EPWM Counter Register 0 0x90 read-only n 0x0 0x0 CNT EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF EPWM Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is counting down #0 1 Counter is counting up #1 EPWM_CNT1 EPWM_CNT1 EPWM Counter Register 1 0x94 read-write n 0x0 0x0 EPWM_CNT2 EPWM_CNT2 EPWM Counter Register 2 0x98 read-write n 0x0 0x0 EPWM_CNT3 EPWM_CNT3 EPWM Counter Register 3 0x9C read-write n 0x0 0x0 EPWM_CNT4 EPWM_CNT4 EPWM Counter Register 4 0xA0 read-write n 0x0 0x0 EPWM_CNT5 EPWM_CNT5 EPWM Counter Register 5 0xA4 read-write n 0x0 0x0 EPWM_CNTCLR EPWM_CNTCLR EPWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLR0 Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 0 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR1 Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 1 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR2 Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 2 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR3 Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 3 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR4 Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 4 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR5 Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 5 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 EPWM_CNTEN EPWM_CNTEN EPWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTEN0 EPWM Counter Enable Bits 0 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN1 EPWM Counter Enable Bits 1 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN2 EPWM Counter Enable Bits 2 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN3 EPWM Counter Enable Bits 3 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN4 EPWM Counter Enable Bits 4 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN5 EPWM Counter Enable Bits 5 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 EPWM_CPSCBUF0_1 EPWM_CPSCBUF0_1 EPWM CLKPSC0_1 Buffer 0x334 read-only n 0x0 0x0 CPSCBUF EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register. 0 12 read-only EPWM_CPSCBUF2_3 EPWM_CPSCBUF2_3 EPWM CLKPSC2_3 Buffer 0x338 read-write n 0x0 0x0 EPWM_CPSCBUF4_5 EPWM_CPSCBUF4_5 EPWM CLKPSC4_5 Buffer 0x33C read-write n 0x0 0x0 EPWM_CTL0 EPWM_CTL0 EPWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLD0 Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 1 read-write CTRLD1 Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 1 1 read-write CTRLD2 Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 2 1 read-write CTRLD3 Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 3 1 read-write CTRLD4 Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 4 1 read-write CTRLD5 Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 5 1 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nEPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects EPWM output #0 1 ICE debug mode acknowledgement disabled #1 GROUPEN Group Function Enable Bit 24 1 read-write 0 The output waveform of each EPWM channel are independent #0 1 Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1 #1 IMMLDEN0 Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 16 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN1 Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 17 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN2 Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 18 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN3 Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 19 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN4 Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 20 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN5 Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 21 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 WINLDEN0 Window Load Enable Bits 8 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN1 Window Load Enable Bits 9 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN2 Window Load Enable Bits 10 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN3 Window Load Enable Bits 11 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN4 Window Load Enable Bits 12 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN5 Window Load Enable Bits 13 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 EPWM_CTL1 EPWM_CTL1 EPWM Control Register 1 0x4 read-write n 0x0 0x0 CNTMODE0 EPWM Counter Mode 16 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE1 EPWM Counter Mode 17 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE2 EPWM Counter Mode 18 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE3 EPWM Counter Mode 19 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE4 EPWM Counter Mode 20 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE5 EPWM Counter Mode 21 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTTYPE0 EPWM Counter Behavior Type 0 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE1 EPWM Counter Behavior Type 2 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE2 EPWM Counter Behavior Type 4 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE3 EPWM Counter Behavior Type 6 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE4 EPWM Counter Behavior Type 8 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE5 EPWM Counter Behavior Type 10 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 OUTMODE0 EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 24 1 read-write 0 EPWM independent mode #0 1 EPWM complementary mode #1 OUTMODE2 EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 25 1 read-write 0 EPWM independent mode #0 1 EPWM complementary mode #1 OUTMODE4 EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 26 1 read-write 0 EPWM independent mode #0 1 EPWM complementary mode #1 EPWM_DACTRGEN EPWM_DACTRGEN EPWM Trigger DAC Enable Register 0xF4 read-write n 0x0 0x0 CDTRGE0 EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGE1, 3, 5 is used as another CDTRGE for channel 0, 2, 4. 24 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE1 EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGE1, 3, 5 is used as another CDTRGE for channel 0, 2, 4. 25 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE2 EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGE1, 3, 5 is used as another CDTRGE for channel 0, 2, 4. 26 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE3 EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGE1, 3, 5 is used as another CDTRGE for channel 0, 2, 4. 27 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE4 EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGE1, 3, 5 is used as another CDTRGE for channel 0, 2, 4. 28 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE5 EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGE1, 3, 5 is used as another CDTRGE for channel 0, 2, 4. 29 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CUTRGE0 EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGE1, 3, 5 is used as another CUTRGE for channel 0, 2, 4. 16 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE1 EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGE1, 3, 5 is used as another CUTRGE for channel 0, 2, 4. 17 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE2 EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGE1, 3, 5 is used as another CUTRGE for channel 0, 2, 4. 18 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE3 EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGE1, 3, 5 is used as another CUTRGE for channel 0, 2, 4. 19 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE4 EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGE1, 3, 5 is used as another CUTRGE for channel 0, 2, 4. 20 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE5 EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGE1, 3, 5 is used as another CUTRGE for channel 0, 2, 4. 21 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 PTE0 EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 8 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE1 EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 9 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE2 EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 10 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE3 EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 11 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE4 EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 12 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE5 EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 13 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE0 EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 0 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE1 EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE2 EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 2 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE3 EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 3 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE4 EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 4 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE5 EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 5 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 EPWM_DTCTL0_1 EPWM_DTCTL0_1 EPWM Dead-time Control Register 0/1 0x70 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to REGWRPROT register. 24 1 read-write 0 Dead-time clock source from EPWM_CLK #0 1 Dead-time clock source from prescaler output #1 DTCNT Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 12 read-write DTEN Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 EPWM_DTCTL2_3 EPWM_DTCTL2_3 EPWM Dead-time Control Register 2/3 0x74 read-write n 0x0 0x0 EPWM_DTCTL4_5 EPWM_DTCTL4_5 EPWM Dead-time Control Register 4/5 0x78 read-write n 0x0 0x0 EPWM_EADCTS0 EPWM_EADCTS0 EPWM Trigger EADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 EPWM_CH0 Trigger EADC Enable Bit 7 1 read-write 0 EPWM_CH0 Trigger EADC function Disabled #0 1 EPWM_CH0 Trigger EADC function Enabled #1 TRGEN1 EPWM_CH1 Trigger EADC Enable Bit 15 1 read-write 0 EPWM_CH1 Trigger EADC function Disabled #0 1 EPWM_CH1 Trigger EADC function Enabled #1 TRGEN2 EPWM_CH2 Trigger EADC Enable Bit 23 1 read-write 0 EPWM_CH2 Trigger EADC function Disabled #0 1 EPWM_CH2 Trigger EADC function Enabled #1 TRGEN3 EPWM_CH3 Trigger EADC Enable Bit 31 1 read-write 0 EPWM_CH3 Trigger EADC function Disabled #0 1 EPWM_CH3 Trigger EADC function Enabled #1 TRGSEL0 EPWM_CH0 Trigger EADC Source Select 0 4 read-write 0 EPWM_CH0 zero point #0000 1 EPWM_CH0 period point #0001 2 EPWM_CH0 zero or period point #0010 3 EPWM_CH0 up-count compared point #0011 4 EPWM_CH0 down-count compared point #0100 5 EPWM_CH1 zero point #0101 6 EPWM_CH1 period point #0110 7 EPWM_CH1 zero or period point #0111 8 EPWM_CH1 up-count compared point #1000 9 EPWM_CH1 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL1 EPWM_CH1 Trigger EADC Source Select 8 4 read-write 0 EPWM_CH0 zero point #0000 1 EPWM_CH0 period point #0001 2 EPWM_CH0 zero or period point #0010 3 EPWM_CH0 up-count compared point #0011 4 EPWM_CH0 down-count compared point #0100 5 EPWM_CH1 zero point #0101 6 EPWM_CH1 period point #0110 7 EPWM_CH1 zero or period point #0111 8 EPWM_CH1 up-count compared point #1000 9 EPWM_CH1 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL2 EPWM_CH2 Trigger EADC Source Select 16 4 read-write 0 EPWM_CH2 zero point #0000 1 EPWM_CH2 period point #0001 2 EPWM_CH2 zero or period point #0010 3 EPWM_CH2 up-count compared point #0011 4 EPWM_CH2 down-count compared point #0100 5 EPWM_CH3 zero point #0101 6 EPWM_CH3 period point #0110 7 EPWM_CH3 zero or period point #0111 8 EPWM_CH3 up-count compared point #1000 9 EPWM_CH3 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL3 EPWM_CH3 Trigger EADC Source Select 24 4 read-write 0 EPWM_CH2 zero point #0000 1 EPWM_CH2 period point #0001 2 EPWM_CH2 zero or period point #0010 3 EPWM_CH2 up-count compared point #0011 4 EPWM_CH2 down-count compared point #0100 5 EPWM_CH3 zero point #0101 6 EPWM_CH3 period point #0110 7 EPWM_CH3 zero or period point #0111 8 EPWM_CH3 up-count compared point #1000 9 EPWM_CH3 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 EPWM_EADCTS1 EPWM_EADCTS1 EPWM Trigger EADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 EPWM_CH4 Trigger EADC Enable Bit 7 1 read-write 0 EPWM_CH4 Trigger EADC function Disabled #0 1 EPWM_CH4 Trigger EADC function Enabled #1 TRGEN5 EPWM_CH5 Trigger EADC Enable Bit 15 1 read-write 0 EPWM_CH5 Trigger EADC function Disabled #0 1 EPWM_CH5 Trigger EADC function Enabled #1 TRGSEL4 EPWM_CH4 Trigger EADC Source Select 0 4 read-write 0 EPWM_CH4 zero point #0000 1 EPWM_CH4 period point #0001 2 EPWM_CH4 zero or period point #0010 3 EPWM_CH4 up-count compared point #0011 4 EPWM_CH4 down-count compared point #0100 5 EPWM_CH5 zero point #0101 6 EPWM_CH5 period point #0110 7 EPWM_CH5 zero or period point #0111 8 EPWM_CH5 up-count compared point #1000 9 EPWM_CH5 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL5 EPWM_CH5 Trigger EADC Source Select 8 4 read-write 0 EPWM_CH4 zero point #0000 1 EPWM_CH4 period point #0001 2 EPWM_CH4 zero or period point #0010 3 EPWM_CH4 up-count compared point #0011 4 EPWM_CH4 down-count compared point #0100 5 EPWM_CH5 zero point #0101 6 EPWM_CH5 period point #0110 7 EPWM_CH5 zero or period point #0111 8 EPWM_CH5 up-count compared point #1000 9 EPWM_CH5 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 EPWM_FAILBRK EPWM_FAILBRK EPWM System Fail Brake Control Register 0xC4 read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit 1 1 read-write 0 Brake Function triggered by BOD Disabled #0 1 Brake Function triggered by BOD Enabled #1 CORBRKEN Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit 3 1 read-write 0 Brake Function triggered by Core lockup detection Disabled #0 1 Brake Function triggered by Core lockup detection Enabled #1 CSSBRKEN Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit 0 1 read-write 0 Brake Function triggered by CSS detection Disabled #0 1 Brake Function triggered by CSS detection Enabled #1 RAMBRKEN SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit 2 1 read-write 0 Brake Function triggered by SRAM parity error detection Disabled #0 1 Brake Function triggered by SRAM parity error detection Enabled #1 EPWM_FCAPDAT0 EPWM_FCAPDAT0 EPWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the EPWM counter value will be saved in this register. 0 16 read-only EPWM_FCAPDAT1 EPWM_FCAPDAT1 EPWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 EPWM_FCAPDAT2 EPWM_FCAPDAT2 EPWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 EPWM_FCAPDAT3 EPWM_FCAPDAT3 EPWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 EPWM_FCAPDAT4 EPWM_FCAPDAT4 EPWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 EPWM_FCAPDAT5 EPWM_FCAPDAT5 EPWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 EPWM_FTCBUF0_1 EPWM_FTCBUF0_1 EPWM FTCMPDAT0_1 Buffer 0x340 read-only n 0x0 0x0 FTCMPBUF EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register. 0 16 read-only EPWM_FTCBUF2_3 EPWM_FTCBUF2_3 EPWM FTCMPDAT2_3 Buffer 0x344 read-write n 0x0 0x0 EPWM_FTCBUF4_5 EPWM_FTCBUF4_5 EPWM FTCMPDAT4_5 Buffer 0x348 read-write n 0x0 0x0 EPWM_FTCI EPWM_FTCI EPWM FTCMPDAT Indicator Register 0x34C read-write n 0x0 0x0 FTCMD0 EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 8 1 read-write FTCMD2 EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 9 1 read-write FTCMD4 EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 10 1 read-write FTCMU0 EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 0 1 read-write FTCMU2 EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 1 1 read-write FTCMU4 EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 2 1 read-write EPWM_FTCMPDAT0_1 EPWM_FTCMPDAT0_1 EPWM Free Trigger Compare Register 0/1 0x100 read-write n 0x0 0x0 FTCMP EPWM Free Trigger Compare Register 0 16 read-write EPWM_FTCMPDAT2_3 EPWM_FTCMPDAT2_3 EPWM Free Trigger Compare Register 2/3 0x104 read-write n 0x0 0x0 EPWM_FTCMPDAT4_5 EPWM_FTCMPDAT4_5 EPWM Free Trigger Compare Register 4/5 0x108 read-write n 0x0 0x0 EPWM_IFA0 EPWM_IFA0 EPWM Interrupt Flag Accumulator Register 0 0x130 read-write n 0x0 0x0 IFACNT EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period. 0 16 read-write IFAEN EPWM_CHn Interrupt Flag Accumulator Enable Bits 31 1 read-write 0 EPWM_CHn interrupt flag accumulator Disabled #0 1 EPWM_CHn interrupt flag accumulator Enabled #1 IFASEL None 28 2 read-write 1 EPWM_CHn period in channel n #01 2 EPWM_CHn up-count compared point #10 3 EPWM_CHn down-count compared point #11 EPWM_IFA1 EPWM_IFA1 EPWM Interrupt Flag Accumulator Register 1 0x134 read-write n 0x0 0x0 EPWM_IFA2 EPWM_IFA2 EPWM Interrupt Flag Accumulator Register 2 0x138 read-write n 0x0 0x0 EPWM_IFA3 EPWM_IFA3 EPWM Interrupt Flag Accumulator Register 3 0x13C read-write n 0x0 0x0 EPWM_IFA4 EPWM_IFA4 EPWM Interrupt Flag Accumulator Register 4 0x140 read-write n 0x0 0x0 EPWM_IFA5 EPWM_IFA5 EPWM Interrupt Flag Accumulator Register 5 0x144 read-write n 0x0 0x0 EPWM_INTEN0 EPWM_INTEN0 EPWM Interrupt Enable Register 0 0xE0 read-write n 0x0 0x0 CMPDIEN0 EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 24 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN1 EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 25 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN2 EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 26 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN3 EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 27 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN4 EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 28 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN5 EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 29 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPUIEN0 EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 16 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN1 EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 17 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN2 EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 18 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN3 EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 19 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN4 EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 20 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN5 EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 21 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 PIEN0 EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN1 EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 9 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN2 EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 10 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN3 EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 11 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN4 EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 12 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN5 EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 13 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode. 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN1 EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode. 1 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN2 EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode. 2 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN3 EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode. 3 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN4 EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode. 4 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN5 EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode. 5 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 EPWM_INTEN1 EPWM_INTEN1 EPWM Interrupt Enable Register 1 0xE4 read-write n 0x0 0x0 BRKEIEN0_1 EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 Edge-detect Brake interrupt for channel0/1 Disabled #0 1 Edge-detect Brake interrupt for channel0/1 Enabled #1 BRKEIEN2_3 EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 Edge-detect Brake interrupt for channel2/3 Disabled #0 1 Edge-detect Brake interrupt for channel2/3 Enabled #1 BRKEIEN4_5 EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 Edge-detect Brake interrupt for channel4/5 Disabled #0 1 Edge-detect Brake interrupt for channel4/5 Enabled #1 BRKLIEN0_1 EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 Level-detect Brake interrupt for channel0/1 Disabled #0 1 Level-detect Brake interrupt for channel0/1 Enabled #1 BRKLIEN2_3 EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 Level-detect Brake interrupt for channel2/3 Disabled #0 1 Level-detect Brake interrupt for channel2/3 Enabled #1 BRKLIEN4_5 EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 Level-detect Brake interrupt for channel4/5 Disabled #0 1 Level-detect Brake interrupt for channel4/5 Enabled #1 EPWM_INTSTS0 EPWM_INTSTS0 EPWM Interrupt Flag Register 0 0xE8 read-write n 0x0 0x0 CMPDIF0 EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 24 1 read-write CMPDIF1 EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 25 1 read-write CMPDIF2 EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 26 1 read-write CMPDIF3 EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 27 1 read-write CMPDIF4 EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 28 1 read-write CMPDIF5 EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 29 1 read-write CMPUIF0 EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 16 1 read-write CMPUIF1 EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 17 1 read-write CMPUIF2 EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 18 1 read-write CMPUIF3 EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 19 1 read-write CMPUIF4 EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 20 1 read-write CMPUIF5 EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 21 1 read-write PIF0 EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1. 8 1 read-write PIF1 EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1. 9 1 read-write PIF2 EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1. 10 1 read-write PIF3 EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1. 11 1 read-write PIF4 EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1. 12 1 read-write PIF5 EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1. 13 1 read-write ZIF0 EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1 0 1 read-write ZIF1 EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1 1 1 read-write ZIF2 EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1 2 1 read-write ZIF3 EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1 3 1 read-write ZIF4 EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1 4 1 read-write ZIF5 EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1 5 1 read-write EPWM_INTSTS1 EPWM_INTSTS1 EPWM Interrupt Flag Register 1 0xEC read-write n 0x0 0x0 BRKEIF0 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF1 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF2 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF3 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 3 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF4 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF5 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKESTS0 EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 16 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS1 EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 17 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS2 EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 18 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS3 EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 19 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS4 EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 20 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS5 EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 21 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLIF0 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF1 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF2 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF3 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 11 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF4 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF5 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLSTS0 EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 24 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS1 EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 25 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS2 EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 26 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS3 EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 27 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS4 EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 28 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS5 EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 29 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 EPWM_LEBCNT EPWM_LEBCNT EPWM Leading Edge Blanking Counter Register 0x11C read-write n 0x0 0x0 LEBCNT EPWM Leading Edge Blanking Counter 0 9 read-write EPWM_LEBCTL EPWM_LEBCTL EPWM Leading Edge Blanking Control Register 0x118 read-write n 0x0 0x0 LEBEN EPWM Leading Edge Blanking Enable Bit 0 1 read-write 0 EPWM Leading Edge Blanking Disabled #0 1 EPWM Leading Edge Blanking Enabled #1 SRCEN0 EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit 8 1 read-write 0 EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled #0 1 EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled #1 SRCEN2 EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit 9 1 read-write 0 EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled #0 1 EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled #1 SRCEN4 EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit 10 1 read-write 0 EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled #0 1 EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled #1 TRGTYPE EPWM Leading Edge Blanking Trigger Type 16 2 read-write 0 When detect leading edge blanking source rising edge, blanking counter start counting 0 1 When detect leading edge blanking source falling edge, blanking counter start counting 1 2 When detect leading edge blanking source rising or falling edge, blanking counter start counting 2 3 Reserved 3 EPWM_LOAD EPWM_LOAD EPWM Load Register 0x28 read-write n 0x0 0x0 LOAD0 Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation: 0 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD1 Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation: 1 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD2 Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation: 2 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD3 Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation: 3 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD4 Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation: 4 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD5 Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation: 5 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 EPWM_MSK EPWM_MSK EPWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDAT0 EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 0 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT1 EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 1 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT2 EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 2 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT3 EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 3 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT4 EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 4 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT5 EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 5 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 EPWM_MSKEN EPWM_MSKEN EPWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKEN0 EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 0 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN1 EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 1 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN2 EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 2 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN3 EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 3 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN4 EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 4 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN5 EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 5 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 EPWM_PBUF0 EPWM_PBUF0 EPWM PERIOD0 Buffer 0x304 read-only n 0x0 0x0 PBUF EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only EPWM_PBUF1 EPWM_PBUF1 EPWM PERIOD1 Buffer 0x308 read-write n 0x0 0x0 EPWM_PBUF2 EPWM_PBUF2 EPWM PERIOD2 Buffer 0x30C read-write n 0x0 0x0 EPWM_PBUF3 EPWM_PBUF3 EPWM PERIOD3 Buffer 0x310 read-write n 0x0 0x0 EPWM_PBUF4 EPWM_PBUF4 EPWM PERIOD4 Buffer 0x314 read-write n 0x0 0x0 EPWM_PBUF5 EPWM_PBUF5 EPWM PERIOD5 Buffer 0x318 read-write n 0x0 0x0 EPWM_PDMACAP0_1 EPWM_PDMACAP0_1 EPWM Capture Channel 01 PDMA Register 0x240 read-only n 0x0 0x0 CAPBUF EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. 0 16 read-only EPWM_PDMACAP2_3 EPWM_PDMACAP2_3 EPWM Capture Channel 23 PDMA Register 0x244 read-write n 0x0 0x0 EPWM_PDMACAP4_5 EPWM_PDMACAP4_5 EPWM Capture Channel 45 PDMA Register 0x248 read-write n 0x0 0x0 EPWM_PDMACTL EPWM_PDMACTL EPWM PDMA Control Register 0x23C read-write n 0x0 0x0 CAPMOD0_1 Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer 1 2 read-write 0 Reserved #00 1 EPWM_RCAPDAT0/1 #01 2 EPWM_FCAPDAT0/1 #10 3 Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1 #11 CAPMOD2_3 Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer 9 2 read-write 0 Reserved #00 1 EPWM_RCAPDAT2/3 #01 2 EPWM_FCAPDAT2/3 #10 3 Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3 #11 CAPMOD4_5 Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer 17 2 read-write 0 Reserved #00 1 EPWM_RCAPDAT4/5 #01 2 EPWM_FCAPDAT4/5 #10 3 Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5 #11 CAPORD0_1 Capture Channel 0/1 Rising/Falling Order 3 1 read-write 0 EPWM_FCAPDAT0/1 is the first captured data to memory #0 1 EPWM_RCAPDAT0/1 is the first captured data to memory #1 CAPORD2_3 Capture Channel 2/3 Rising/Falling Order 11 1 read-write 0 EPWM_FCAPDAT2/3 is the first captured data to memory #0 1 EPWM_RCAPDAT2/3 is the first captured data to memory #1 CAPORD4_5 Capture Channel 4/5 Rising/Falling Order 19 1 read-write 0 EPWM_FCAPDAT4/5 is the first captured data to memory #0 1 EPWM_RCAPDAT4/5 is the first captured data to memory #1 CHEN0_1 Channel 0/1 PDMA Enable Bit 0 1 read-write 0 Channel 0/1 PDMA function Disabled #0 1 Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory #1 CHEN2_3 Channel 2/3 PDMA Enable Bit 8 1 read-write 0 Channel 2/3 PDMA function Disabled #0 1 Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory #1 CHEN4_5 Channel 4/5 PDMA Enable Bit 16 1 read-write 0 Channel 4/5 PDMA function Disabled #0 1 Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory #1 CHSEL0_1 Select Channel 0/1 to Do PDMA Transfer 4 1 read-write 0 Channel0 #0 1 Channel1 #1 CHSEL2_3 Select Channel 2/3 to Do PDMA Transfer 12 1 read-write 0 Channel2 #0 1 Channel3 #1 CHSEL4_5 Select Channel 4/5 to Do PDMA Transfer 20 1 read-write 0 Channel4 #0 1 Channel5 #1 EPWM_PERIOD0 EPWM_PERIOD0 EPWM Period Register 0 0x30 read-write n 0x0 0x0 PERIOD EPWM Period Register\nUp-Count mode: \nIn this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. 0 16 read-write EPWM_PERIOD1 EPWM_PERIOD1 EPWM Period Register 1 0x34 read-write n 0x0 0x0 EPWM_PERIOD2 EPWM_PERIOD2 EPWM Period Register 2 0x38 read-write n 0x0 0x0 EPWM_PERIOD3 EPWM_PERIOD3 EPWM Period Register 3 0x3C read-write n 0x0 0x0 EPWM_PERIOD4 EPWM_PERIOD4 EPWM Period Register 4 0x40 read-write n 0x0 0x0 EPWM_PERIOD5 EPWM_PERIOD5 EPWM Period Register 5 0x44 read-write n 0x0 0x0 EPWM_PHS0_1 EPWM_PHS0_1 EPWM Counter Phase Register 0/1 0x80 read-write n 0x0 0x0 PHS EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value. These bits only use in synchronous function. 0 16 read-write EPWM_PHS2_3 EPWM_PHS2_3 EPWM Counter Phase Register 2/3 0x84 read-write n 0x0 0x0 EPWM_PHS4_5 EPWM_PHS4_5 EPWM Counter Phase Register 4/5 0x88 read-write n 0x0 0x0 EPWM_POEN EPWM_POEN EPWM Output Enable Register 0xD8 read-write n 0x0 0x0 POEN0 EPWM Pin Output Enable Bits 0 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN1 EPWM Pin Output Enable Bits 1 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN2 EPWM Pin Output Enable Bits 2 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN3 EPWM Pin Output Enable Bits 3 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN4 EPWM Pin Output Enable Bits 4 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN5 EPWM Pin Output Enable Bits 5 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 EPWM_POLCTL EPWM_POLCTL EPWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINV0 EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output. 0 1 read-write 0 EPWMx_CHn output polar inverse Disabled #0 1 EPWMx_CHn output polar inverse Enabled #1 PINV1 EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output. 1 1 read-write 0 EPWMx_CHn output polar inverse Disabled #0 1 EPWMx_CHn output polar inverse Enabled #1 PINV2 EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output. 2 1 read-write 0 EPWMx_CHn output polar inverse Disabled #0 1 EPWMx_CHn output polar inverse Enabled #1 PINV3 EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output. 3 1 read-write 0 EPWMx_CHn output polar inverse Disabled #0 1 EPWMx_CHn output polar inverse Enabled #1 PINV4 EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output. 4 1 read-write 0 EPWMx_CHn output polar inverse Disabled #0 1 EPWMx_CHn output polar inverse Enabled #1 PINV5 EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output. 5 1 read-write 0 EPWMx_CHn output polar inverse Disabled #0 1 EPWMx_CHn output polar inverse Enabled #1 EPWM_RCAPDAT0 EPWM_RCAPDAT0 EPWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the EPWM counter value will be saved in this register. 0 16 read-only EPWM_RCAPDAT1 EPWM_RCAPDAT1 EPWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 EPWM_RCAPDAT2 EPWM_RCAPDAT2 EPWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 EPWM_RCAPDAT3 EPWM_RCAPDAT3 EPWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 EPWM_RCAPDAT4 EPWM_RCAPDAT4 EPWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 EPWM_RCAPDAT5 EPWM_RCAPDAT5 EPWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 EPWM_SSCTL EPWM_SSCTL EPWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSEN0 EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 0 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN1 EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN2 EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 2 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN3 EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 3 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN4 EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 4 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN5 EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 5 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSRC EPWM Synchronous Start Source Select Bits 8 2 read-write 0 Synchronous start source come from EPWM0 #00 1 Synchronous start source come from EPWM1 #01 2 Synchronous start source come from BPWM0 #10 3 Synchronous start source come from BPWM1 #11 EPWM_SSTRG EPWM_SSTRG EPWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN EPWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled. 0 1 write-only EPWM_STATUS EPWM_STATUS EPWM Status Register 0x120 read-write n 0x0 0x0 CNTMAXF0 Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1. 0 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF1 Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1. 1 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF2 Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1. 2 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF3 Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1. 3 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF4 Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1. 4 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF5 Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1. 5 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 DACTRGF DAC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1. 24 1 read-write 0 No DAC start of conversion trigger event has occurred #0 1 A DAC start of conversion trigger event has occurred #1 EADCTRGF0 EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1. 16 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF1 EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1. 17 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF2 EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1. 18 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF3 EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1. 19 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF4 EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1. 20 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF5 EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1. 21 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 SYNCINF0 Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1. 8 1 read-write 0 No SYNC_IN event has occurred #0 1 A SYNC_IN event has occurred #1 SYNCINF2 Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1. 9 1 read-write 0 No SYNC_IN event has occurred #0 1 A SYNC_IN event has occurred #1 SYNCINF4 Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1. 10 1 read-write 0 No SYNC_IN event has occurred #0 1 A SYNC_IN event has occurred #1 EPWM_SWBRK EPWM_SWBRK EPWM Software Brake Control Register 0xDC write-only n 0x0 0x0 BRKETRG0 EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 write-only BRKETRG2 EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 write-only BRKETRG4 EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 write-only BRKLTRG0 EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 write-only BRKLTRG2 EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 write-only BRKLTRG4 EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 write-only EPWM_SWSYNC EPWM_SWSYNC EPWM Software Control Synchronization Register 0xC read-write n 0x0 0x0 SWSYNC0 Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. 0 1 read-write SWSYNC2 Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. 1 1 read-write SWSYNC4 Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. 2 1 read-write EPWM_SYNC EPWM_SYNC EPWM Synchronization Register 0x8 read-write n 0x0 0x0 PHSDIR0 EPWM Phase Direction Control 24 1 read-write 0 Control EPWM counter count decrement after synchronizing #0 1 Control EPWM counter count increment after synchronizing #1 PHSDIR2 EPWM Phase Direction Control 25 1 read-write 0 Control EPWM counter count decrement after synchronizing #0 1 Control EPWM counter count increment after synchronizing #1 PHSDIR4 EPWM Phase Direction Control 26 1 read-write 0 Control EPWM counter count decrement after synchronizing #0 1 Control EPWM counter count increment after synchronizing #1 PHSEN0 SYNC Phase Enable Bits 0 1 read-write 0 EPWM counter disable to load PHS value #0 1 EPWM counter enable to load PHS value #1 PHSEN2 SYNC Phase Enable Bits 1 1 read-write 0 EPWM counter disable to load PHS value #0 1 EPWM counter enable to load PHS value #1 PHSEN4 SYNC Phase Enable Bits 2 1 read-write 0 EPWM counter disable to load PHS value #0 1 EPWM counter enable to load PHS value #1 SFLTCNT SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector. 20 3 read-write SFLTCSEL SYNC Edge Detector Filter Clock Selection 17 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 SINPINV SYNC Input Pin Inverse 23 1 read-write 0 The state of pin SYNC is passed to the negative edge detector #0 1 The inversed state of pin SYNC is passed to the negative edge detector #1 SINSRC0 EPWM0_SYNC_IN Source Selection 8 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT will not be generated #11 SINSRC2 EPWM0_SYNC_IN Source Selection 10 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT will not be generated #11 SINSRC4 EPWM0_SYNC_IN Source Selection 12 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT will not be generated #11 SNFLTEN EPWM0_SYNC_IN Noise Filter Enable Bits 16 1 read-write 0 Noise filter of input pin EPWM0_SYNC_IN Disabled #0 1 Noise filter of input pin EPWM0_SYNC_IN Enabled #1 EPWM_WGCTL0 EPWM_WGCTL0 EPWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTL0 EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type. 16 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL1 EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type. 18 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL2 EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type. 20 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL3 EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type. 22 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL4 EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type. 24 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL5 EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type. 26 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 ZPCTL0 EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0. 0 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL1 EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0. 2 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL2 EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0. 4 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL3 EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0. 6 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL4 EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0. 8 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL5 EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0. 10 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 EPWM_WGCTL1 EPWM_WGCTL1 EPWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTL0 EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 16 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL1 EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 18 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL2 EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 20 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL3 EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 22 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL4 EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 24 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL5 EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 26 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPUCTL0 EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 0 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL1 EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 2 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL2 EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 4 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL3 EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 6 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL4 EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 8 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL5 EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 10 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 EPWM1 EPWM Register Map EPWM 0x0 0x0 0x2C registers n 0x110 0x14 registers n 0x130 0x18 registers n 0x150 0xC registers n 0x200 0x4C registers n 0x250 0x8 registers n 0x30 0x18 registers n 0x304 0x4C registers n 0x50 0x18 registers n 0x70 0xC registers n 0x80 0xC registers n 0x90 0x18 registers n 0xB0 0x40 registers n 0xF4 0x18 registers n EPWM_AINTEN EPWM_AINTEN EPWM Accumulator Interrupt Enable Register 0x154 read-write n 0x0 0x0 IFAIEN0 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 0 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN1 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN2 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 2 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN3 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 3 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN4 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 4 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN5 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 5 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 EPWM_AINTSTS EPWM_AINTSTS EPWM Accumulator Interrupt Flag Register 0x150 read-write n 0x0 0x0 IFAIF0 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 0 1 read-write IFAIF1 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1 1 read-write IFAIF2 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 2 1 read-write IFAIF3 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 3 1 read-write IFAIF4 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 4 1 read-write IFAIF5 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 5 1 read-write EPWM_APDMACTL EPWM_APDMACTL EPWM Accumulator PDMA Control Register 0x158 read-write n 0x0 0x0 APDMAEN0 Channel N Accumulator PDMA Enable Bits 0 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN1 Channel N Accumulator PDMA Enable Bits 1 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN2 Channel N Accumulator PDMA Enable Bits 2 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN3 Channel N Accumulator PDMA Enable Bits 3 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN4 Channel N Accumulator PDMA Enable Bits 4 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN5 Channel N Accumulator PDMA Enable Bits 5 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 EPWM_BNF EPWM_BNF EPWM Brake Noise Filter Register 0xC0 read-write n 0x0 0x0 BK0SRC Brake 0 Pin Source Select\nFor EPWM0 setting: 16 1 read-write 0 Brake 0 pin source come from EPWM0_BRAKE0.\nBrake 0 pin source come from EPWM1_BRAKE0 #0 1 Brake 0 pin source come from EPWM1_BRAKE0.\nBrake 0 pin source come from EPWM0_BRAKE0 #1 BK1SRC Brake 1 Pin Source Select\nFor EPWM0 setting: 24 1 read-write 0 Brake 1 pin source come from EPWM0_BRAKE1.\nBrake 1 pin source come from EPWM1_BRAKE1 #0 1 Brake 1 pin source come from EPWM1_BRAKE1.\nBrake 1 pin source come from EPWM0_BRAKE1 #1 BRK0FCNT Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. 4 3 read-write BRK0NFEN EPWM Brake 0 Noise Filter Enable Bit 0 1 read-write 0 Noise filter of EPWM Brake 0 Disabled #0 1 Noise filter of EPWM Brake 0 Enabled #1 BRK0NFSEL Brake 0 Edge Detector Filter Clock Selection 1 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK0PINV Brake 0 Pin Inverse 7 1 read-write 0 brake pin event will be detected if EPWMx BRAKE0 pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 brake pin event will be detected if EPWMx BRAKE0 pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 BRK1FCNT Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 12 3 read-write BRK1NFEN EPWM Brake 1 Noise Filter Enable Bit 8 1 read-write 0 Noise filter of EPWM Brake 1 Disabled #0 1 Noise filter of EPWM Brake 1 Enabled #1 BRK1NFSEL Brake 1 Edge Detector Filter Clock Selection 9 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK1PINV Brake 1 Pin Inverse 15 1 read-write 0 brake pin event will be detected if EPWMx BRAKE1 pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 brake pin event will be detected if EPWMx BRAKE1 pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 EPWM_BRKCTL0_1 EPWM_BRKCTL0_1 EPWM Brake Edge Detect Control Register 0/1 0xC8 read-write n 0x0 0x0 BRKAEVEN EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 16 2 read-write 0 EPWMx brake event will not affect even channels output #00 1 EPWM even channel output tri-state when EPWMx brake event happened #01 2 EPWM even channel output low level when EPWMx brake event happened #10 3 EPWM even channel output high level when EPWMx brake event happened #11 BRKAODD EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 18 2 read-write 0 EPWMx brake event will not affect odd channels output #00 1 EPWM odd channel output tri-state when EPWMx brake event happened #01 2 EPWM odd channel output low level when EPWMx brake event happened #10 3 EPWM odd channel output high level when EPWMx brake event happened #11 BRKP0EEN Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 EPWMx_BRAKE0 pin as edge-detect brake source Disabled #0 1 EPWMx_BRAKE0 pin as edge-detect brake source Enabled #1 BRKP0LEN Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 EPWMx_BRAKE0 pin as level-detect brake source Disabled #0 1 EPWMx_BRAKE0 pin as level-detect brake source Enabled #1 BRKP1EEN Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 EPWMx_BRAKE1 pin as edge-detect brake source Disabled #0 1 EPWMx_BRAKE1 pin as edge-detect brake source Enabled #1 BRKP1LEN Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 EPWMx_BRAKE1 pin as level-detect brake source Disabled #0 1 EPWMx_BRAKE1 pin as level-detect brake source Enabled #1 CPO0EBEN Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 ACMP0_O as edge-detect brake source Disabled #0 1 ACMP0_O as edge-detect brake source Enabled #1 CPO0LBEN Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 ACMP0_O as level-detect brake source Disabled #0 1 ACMP0_O as level-detect brake source Enabled #1 CPO1EBEN Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 ACMP1_O as edge-detect brake source Disabled #0 1 ACMP1_O as edge-detect brake source Enabled #1 CPO1LBEN Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 ACMP1_O as level-detect brake source Disabled #0 1 ACMP1_O as level-detect brake source Enabled #1 EADCEBEN Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 20 1 read-write 0 EADCRM as edge-detect brake source Disabled #0 1 EADCRM as edge-detect brake source Enabled #1 EADCLBEN Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 28 1 read-write 0 EADCRM as level-detect brake source Disabled #0 1 EADCRM as level-detect brake source Enabled #1 SYSEBEN Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 7 1 read-write 0 System Fail condition as edge-detect brake source Disabled #0 1 System Fail condition as edge-detect brake source Enabled #1 SYSLBEN Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 15 1 read-write 0 System Fail condition as level-detect brake source Disabled #0 1 System Fail condition as level-detect brake source Enabled #1 EPWM_BRKCTL2_3 EPWM_BRKCTL2_3 EPWM Brake Edge Detect Control Register 2/3 0xCC read-write n 0x0 0x0 EPWM_BRKCTL4_5 EPWM_BRKCTL4_5 EPWM Brake Edge Detect Control Register 4/5 0xD0 read-write n 0x0 0x0 EPWM_CAPCTL EPWM_CAPCTL EPWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPEN0 Capture Function Enable Bits 0 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN1 Capture Function Enable Bits 1 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN2 Capture Function Enable Bits 2 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN3 Capture Function Enable Bits 3 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN4 Capture Function Enable Bits 4 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN5 Capture Function Enable Bits 5 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPINV0 Capture Inverter Enable Bits 8 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV1 Capture Inverter Enable Bits 9 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV2 Capture Inverter Enable Bits 10 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV3 Capture Inverter Enable Bits 11 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV4 Capture Inverter Enable Bits 12 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV5 Capture Inverter Enable Bits 13 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 FCRLDEN0 Falling Capture Reload Enable Bits 24 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN1 Falling Capture Reload Enable Bits 25 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN2 Falling Capture Reload Enable Bits 26 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN3 Falling Capture Reload Enable Bits 27 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN4 Falling Capture Reload Enable Bits 28 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN5 Falling Capture Reload Enable Bits 29 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 RCRLDEN0 Rising Capture Reload Enable Bits 16 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN1 Rising Capture Reload Enable Bits 17 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN2 Rising Capture Reload Enable Bits 18 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN3 Rising Capture Reload Enable Bits 19 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN4 Rising Capture Reload Enable Bits 20 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN5 Rising Capture Reload Enable Bits 21 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 EPWM_CAPIEN EPWM_CAPIEN EPWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIEN0 EPWM Capture Falling Latch Interrupt Enable Bits 8 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN1 EPWM Capture Falling Latch Interrupt Enable Bits 9 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN2 EPWM Capture Falling Latch Interrupt Enable Bits 10 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN3 EPWM Capture Falling Latch Interrupt Enable Bits 11 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN4 EPWM Capture Falling Latch Interrupt Enable Bits 12 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN5 EPWM Capture Falling Latch Interrupt Enable Bits 13 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPRIEN0 EPWM Capture Rising Latch Interrupt Enable Bits 0 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN1 EPWM Capture Rising Latch Interrupt Enable Bits 1 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN2 EPWM Capture Rising Latch Interrupt Enable Bits 2 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN3 EPWM Capture Rising Latch Interrupt Enable Bits 3 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN4 EPWM Capture Rising Latch Interrupt Enable Bits 4 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN5 EPWM Capture Rising Latch Interrupt Enable Bits 5 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 EPWM_CAPIF EPWM_CAPIF EPWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CFLIF0 EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 8 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF1 EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 9 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF2 EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 10 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF3 EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 11 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF4 EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 12 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF5 EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 13 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CRLIF0 EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 0 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF1 EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 1 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF2 EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 2 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF3 EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 3 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF4 EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 4 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF5 EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it. 5 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 EPWM_CAPINEN EPWM_CAPINEN EPWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINEN0 Capture Input Enable Bits 0 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN1 Capture Input Enable Bits 1 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN2 Capture Input Enable Bits 2 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN3 Capture Input Enable Bits 3 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN4 Capture Input Enable Bits 4 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN5 Capture Input Enable Bits 5 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 EPWM_CAPSTS EPWM_CAPSTS EPWM Capture Status Register 0x208 read-only n 0x0 0x0 CFLIFOV0 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 8 1 read-only CFLIFOV1 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 9 1 read-only CFLIFOV2 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 10 1 read-only CFLIFOV3 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 11 1 read-only CFLIFOV4 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 12 1 read-only CFLIFOV5 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 13 1 read-only CRLIFOV0 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 0 1 read-only CRLIFOV1 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 1 1 read-only CRLIFOV2 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 2 1 read-only CRLIFOV3 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 3 1 read-only CRLIFOV4 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 4 1 read-only CRLIFOV5 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 5 1 read-only EPWM_CLKPSC0_1 EPWM_CLKPSC0_1 EPWM Clock Prescale Register 0/1 0x14 read-write n 0x0 0x0 CLKPSC EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1). 0 12 read-write EPWM_CLKPSC2_3 EPWM_CLKPSC2_3 EPWM Clock Prescale Register 2/3 0x18 read-write n 0x0 0x0 EPWM_CLKPSC4_5 EPWM_CLKPSC4_5 EPWM Clock Prescale Register 4/5 0x1C read-write n 0x0 0x0 EPWM_CLKSRC EPWM_CLKSRC EPWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 EPWM_CH01 External Clock Source Select 0 3 read-write 0 EPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC2 EPWM_CH23 External Clock Source Select 8 3 read-write 0 EPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC4 EPWM_CH45 External Clock Source Select 16 3 read-write 0 EPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 EPWM_CMPBUF0 EPWM_CMPBUF0 EPWM CMPDAT0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register. 0 16 read-only EPWM_CMPBUF1 EPWM_CMPBUF1 EPWM CMPDAT1 Buffer 0x320 read-write n 0x0 0x0 EPWM_CMPBUF2 EPWM_CMPBUF2 EPWM CMPDAT2 Buffer 0x324 read-write n 0x0 0x0 EPWM_CMPBUF3 EPWM_CMPBUF3 EPWM CMPDAT3 Buffer 0x328 read-write n 0x0 0x0 EPWM_CMPBUF4 EPWM_CMPBUF4 EPWM CMPDAT4 Buffer 0x32C read-write n 0x0 0x0 EPWM_CMPBUF5 EPWM_CMPBUF5 EPWM CMPDAT5 Buffer 0x330 read-write n 0x0 0x0 EPWM_CMPDAT0 EPWM_CMPDAT0 EPWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMP EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform, interrupt and trigger EADC/DAC.\nIn independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. 0 16 read-write EPWM_CMPDAT1 EPWM_CMPDAT1 EPWM Comparator Register 1 0x54 read-write n 0x0 0x0 EPWM_CMPDAT2 EPWM_CMPDAT2 EPWM Comparator Register 2 0x58 read-write n 0x0 0x0 EPWM_CMPDAT3 EPWM_CMPDAT3 EPWM Comparator Register 3 0x5C read-write n 0x0 0x0 EPWM_CMPDAT4 EPWM_CMPDAT4 EPWM Comparator Register 4 0x60 read-write n 0x0 0x0 EPWM_CMPDAT5 EPWM_CMPDAT5 EPWM Comparator Register 5 0x64 read-write n 0x0 0x0 EPWM_CNT0 EPWM_CNT0 EPWM Counter Register 0 0x90 read-only n 0x0 0x0 CNT EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF EPWM Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is counting down #0 1 Counter is counting up #1 EPWM_CNT1 EPWM_CNT1 EPWM Counter Register 1 0x94 read-write n 0x0 0x0 EPWM_CNT2 EPWM_CNT2 EPWM Counter Register 2 0x98 read-write n 0x0 0x0 EPWM_CNT3 EPWM_CNT3 EPWM Counter Register 3 0x9C read-write n 0x0 0x0 EPWM_CNT4 EPWM_CNT4 EPWM Counter Register 4 0xA0 read-write n 0x0 0x0 EPWM_CNT5 EPWM_CNT5 EPWM Counter Register 5 0xA4 read-write n 0x0 0x0 EPWM_CNTCLR EPWM_CNTCLR EPWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLR0 Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 0 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR1 Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 1 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR2 Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 2 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR3 Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 3 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR4 Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 4 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR5 Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 5 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 EPWM_CNTEN EPWM_CNTEN EPWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTEN0 EPWM Counter Enable Bits 0 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN1 EPWM Counter Enable Bits 1 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN2 EPWM Counter Enable Bits 2 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN3 EPWM Counter Enable Bits 3 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN4 EPWM Counter Enable Bits 4 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN5 EPWM Counter Enable Bits 5 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 EPWM_CPSCBUF0_1 EPWM_CPSCBUF0_1 EPWM CLKPSC0_1 Buffer 0x334 read-only n 0x0 0x0 CPSCBUF EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register. 0 12 read-only EPWM_CPSCBUF2_3 EPWM_CPSCBUF2_3 EPWM CLKPSC2_3 Buffer 0x338 read-write n 0x0 0x0 EPWM_CPSCBUF4_5 EPWM_CPSCBUF4_5 EPWM CLKPSC4_5 Buffer 0x33C read-write n 0x0 0x0 EPWM_CTL0 EPWM_CTL0 EPWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLD0 Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 1 read-write CTRLD1 Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 1 1 read-write CTRLD2 Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 2 1 read-write CTRLD3 Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 3 1 read-write CTRLD4 Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 4 1 read-write CTRLD5 Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 5 1 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nEPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects EPWM output #0 1 ICE debug mode acknowledgement disabled #1 GROUPEN Group Function Enable Bit 24 1 read-write 0 The output waveform of each EPWM channel are independent #0 1 Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1 #1 IMMLDEN0 Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 16 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN1 Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 17 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN2 Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 18 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN3 Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 19 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN4 Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 20 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN5 Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 21 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 WINLDEN0 Window Load Enable Bits 8 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN1 Window Load Enable Bits 9 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN2 Window Load Enable Bits 10 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN3 Window Load Enable Bits 11 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN4 Window Load Enable Bits 12 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN5 Window Load Enable Bits 13 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 EPWM_CTL1 EPWM_CTL1 EPWM Control Register 1 0x4 read-write n 0x0 0x0 CNTMODE0 EPWM Counter Mode 16 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE1 EPWM Counter Mode 17 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE2 EPWM Counter Mode 18 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE3 EPWM Counter Mode 19 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE4 EPWM Counter Mode 20 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE5 EPWM Counter Mode 21 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTTYPE0 EPWM Counter Behavior Type 0 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE1 EPWM Counter Behavior Type 2 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE2 EPWM Counter Behavior Type 4 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE3 EPWM Counter Behavior Type 6 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE4 EPWM Counter Behavior Type 8 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE5 EPWM Counter Behavior Type 10 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 OUTMODE0 EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 24 1 read-write 0 EPWM independent mode #0 1 EPWM complementary mode #1 OUTMODE2 EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 25 1 read-write 0 EPWM independent mode #0 1 EPWM complementary mode #1 OUTMODE4 EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 26 1 read-write 0 EPWM independent mode #0 1 EPWM complementary mode #1 EPWM_DACTRGEN EPWM_DACTRGEN EPWM Trigger DAC Enable Register 0xF4 read-write n 0x0 0x0 CDTRGE0 EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGE1, 3, 5 is used as another CDTRGE for channel 0, 2, 4. 24 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE1 EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGE1, 3, 5 is used as another CDTRGE for channel 0, 2, 4. 25 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE2 EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGE1, 3, 5 is used as another CDTRGE for channel 0, 2, 4. 26 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE3 EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGE1, 3, 5 is used as another CDTRGE for channel 0, 2, 4. 27 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE4 EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGE1, 3, 5 is used as another CDTRGE for channel 0, 2, 4. 28 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE5 EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGE1, 3, 5 is used as another CDTRGE for channel 0, 2, 4. 29 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CUTRGE0 EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGE1, 3, 5 is used as another CUTRGE for channel 0, 2, 4. 16 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE1 EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGE1, 3, 5 is used as another CUTRGE for channel 0, 2, 4. 17 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE2 EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGE1, 3, 5 is used as another CUTRGE for channel 0, 2, 4. 18 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE3 EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGE1, 3, 5 is used as another CUTRGE for channel 0, 2, 4. 19 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE4 EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGE1, 3, 5 is used as another CUTRGE for channel 0, 2, 4. 20 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE5 EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGE1, 3, 5 is used as another CUTRGE for channel 0, 2, 4. 21 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 PTE0 EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 8 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE1 EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 9 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE2 EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 10 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE3 EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 11 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE4 EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 12 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE5 EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 13 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE0 EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 0 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE1 EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE2 EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 2 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE3 EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 3 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE4 EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 4 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE5 EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 5 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 EPWM_DTCTL0_1 EPWM_DTCTL0_1 EPWM Dead-time Control Register 0/1 0x70 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to REGWRPROT register. 24 1 read-write 0 Dead-time clock source from EPWM_CLK #0 1 Dead-time clock source from prescaler output #1 DTCNT Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 12 read-write DTEN Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 EPWM_DTCTL2_3 EPWM_DTCTL2_3 EPWM Dead-time Control Register 2/3 0x74 read-write n 0x0 0x0 EPWM_DTCTL4_5 EPWM_DTCTL4_5 EPWM Dead-time Control Register 4/5 0x78 read-write n 0x0 0x0 EPWM_EADCTS0 EPWM_EADCTS0 EPWM Trigger EADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 EPWM_CH0 Trigger EADC Enable Bit 7 1 read-write 0 EPWM_CH0 Trigger EADC function Disabled #0 1 EPWM_CH0 Trigger EADC function Enabled #1 TRGEN1 EPWM_CH1 Trigger EADC Enable Bit 15 1 read-write 0 EPWM_CH1 Trigger EADC function Disabled #0 1 EPWM_CH1 Trigger EADC function Enabled #1 TRGEN2 EPWM_CH2 Trigger EADC Enable Bit 23 1 read-write 0 EPWM_CH2 Trigger EADC function Disabled #0 1 EPWM_CH2 Trigger EADC function Enabled #1 TRGEN3 EPWM_CH3 Trigger EADC Enable Bit 31 1 read-write 0 EPWM_CH3 Trigger EADC function Disabled #0 1 EPWM_CH3 Trigger EADC function Enabled #1 TRGSEL0 EPWM_CH0 Trigger EADC Source Select 0 4 read-write 0 EPWM_CH0 zero point #0000 1 EPWM_CH0 period point #0001 2 EPWM_CH0 zero or period point #0010 3 EPWM_CH0 up-count compared point #0011 4 EPWM_CH0 down-count compared point #0100 5 EPWM_CH1 zero point #0101 6 EPWM_CH1 period point #0110 7 EPWM_CH1 zero or period point #0111 8 EPWM_CH1 up-count compared point #1000 9 EPWM_CH1 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL1 EPWM_CH1 Trigger EADC Source Select 8 4 read-write 0 EPWM_CH0 zero point #0000 1 EPWM_CH0 period point #0001 2 EPWM_CH0 zero or period point #0010 3 EPWM_CH0 up-count compared point #0011 4 EPWM_CH0 down-count compared point #0100 5 EPWM_CH1 zero point #0101 6 EPWM_CH1 period point #0110 7 EPWM_CH1 zero or period point #0111 8 EPWM_CH1 up-count compared point #1000 9 EPWM_CH1 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL2 EPWM_CH2 Trigger EADC Source Select 16 4 read-write 0 EPWM_CH2 zero point #0000 1 EPWM_CH2 period point #0001 2 EPWM_CH2 zero or period point #0010 3 EPWM_CH2 up-count compared point #0011 4 EPWM_CH2 down-count compared point #0100 5 EPWM_CH3 zero point #0101 6 EPWM_CH3 period point #0110 7 EPWM_CH3 zero or period point #0111 8 EPWM_CH3 up-count compared point #1000 9 EPWM_CH3 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL3 EPWM_CH3 Trigger EADC Source Select 24 4 read-write 0 EPWM_CH2 zero point #0000 1 EPWM_CH2 period point #0001 2 EPWM_CH2 zero or period point #0010 3 EPWM_CH2 up-count compared point #0011 4 EPWM_CH2 down-count compared point #0100 5 EPWM_CH3 zero point #0101 6 EPWM_CH3 period point #0110 7 EPWM_CH3 zero or period point #0111 8 EPWM_CH3 up-count compared point #1000 9 EPWM_CH3 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 EPWM_EADCTS1 EPWM_EADCTS1 EPWM Trigger EADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 EPWM_CH4 Trigger EADC Enable Bit 7 1 read-write 0 EPWM_CH4 Trigger EADC function Disabled #0 1 EPWM_CH4 Trigger EADC function Enabled #1 TRGEN5 EPWM_CH5 Trigger EADC Enable Bit 15 1 read-write 0 EPWM_CH5 Trigger EADC function Disabled #0 1 EPWM_CH5 Trigger EADC function Enabled #1 TRGSEL4 EPWM_CH4 Trigger EADC Source Select 0 4 read-write 0 EPWM_CH4 zero point #0000 1 EPWM_CH4 period point #0001 2 EPWM_CH4 zero or period point #0010 3 EPWM_CH4 up-count compared point #0011 4 EPWM_CH4 down-count compared point #0100 5 EPWM_CH5 zero point #0101 6 EPWM_CH5 period point #0110 7 EPWM_CH5 zero or period point #0111 8 EPWM_CH5 up-count compared point #1000 9 EPWM_CH5 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL5 EPWM_CH5 Trigger EADC Source Select 8 4 read-write 0 EPWM_CH4 zero point #0000 1 EPWM_CH4 period point #0001 2 EPWM_CH4 zero or period point #0010 3 EPWM_CH4 up-count compared point #0011 4 EPWM_CH4 down-count compared point #0100 5 EPWM_CH5 zero point #0101 6 EPWM_CH5 period point #0110 7 EPWM_CH5 zero or period point #0111 8 EPWM_CH5 up-count compared point #1000 9 EPWM_CH5 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 EPWM_FAILBRK EPWM_FAILBRK EPWM System Fail Brake Control Register 0xC4 read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit 1 1 read-write 0 Brake Function triggered by BOD Disabled #0 1 Brake Function triggered by BOD Enabled #1 CORBRKEN Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit 3 1 read-write 0 Brake Function triggered by Core lockup detection Disabled #0 1 Brake Function triggered by Core lockup detection Enabled #1 CSSBRKEN Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit 0 1 read-write 0 Brake Function triggered by CSS detection Disabled #0 1 Brake Function triggered by CSS detection Enabled #1 RAMBRKEN SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit 2 1 read-write 0 Brake Function triggered by SRAM parity error detection Disabled #0 1 Brake Function triggered by SRAM parity error detection Enabled #1 EPWM_FCAPDAT0 EPWM_FCAPDAT0 EPWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the EPWM counter value will be saved in this register. 0 16 read-only EPWM_FCAPDAT1 EPWM_FCAPDAT1 EPWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 EPWM_FCAPDAT2 EPWM_FCAPDAT2 EPWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 EPWM_FCAPDAT3 EPWM_FCAPDAT3 EPWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 EPWM_FCAPDAT4 EPWM_FCAPDAT4 EPWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 EPWM_FCAPDAT5 EPWM_FCAPDAT5 EPWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 EPWM_FTCBUF0_1 EPWM_FTCBUF0_1 EPWM FTCMPDAT0_1 Buffer 0x340 read-only n 0x0 0x0 FTCMPBUF EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register. 0 16 read-only EPWM_FTCBUF2_3 EPWM_FTCBUF2_3 EPWM FTCMPDAT2_3 Buffer 0x344 read-write n 0x0 0x0 EPWM_FTCBUF4_5 EPWM_FTCBUF4_5 EPWM FTCMPDAT4_5 Buffer 0x348 read-write n 0x0 0x0 EPWM_FTCI EPWM_FTCI EPWM FTCMPDAT Indicator Register 0x34C read-write n 0x0 0x0 FTCMD0 EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 8 1 read-write FTCMD2 EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 9 1 read-write FTCMD4 EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 10 1 read-write FTCMU0 EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 0 1 read-write FTCMU2 EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 1 1 read-write FTCMU4 EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 2 1 read-write EPWM_FTCMPDAT0_1 EPWM_FTCMPDAT0_1 EPWM Free Trigger Compare Register 0/1 0x100 read-write n 0x0 0x0 FTCMP EPWM Free Trigger Compare Register 0 16 read-write EPWM_FTCMPDAT2_3 EPWM_FTCMPDAT2_3 EPWM Free Trigger Compare Register 2/3 0x104 read-write n 0x0 0x0 EPWM_FTCMPDAT4_5 EPWM_FTCMPDAT4_5 EPWM Free Trigger Compare Register 4/5 0x108 read-write n 0x0 0x0 EPWM_IFA0 EPWM_IFA0 EPWM Interrupt Flag Accumulator Register 0 0x130 read-write n 0x0 0x0 IFACNT EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period. 0 16 read-write IFAEN EPWM_CHn Interrupt Flag Accumulator Enable Bits 31 1 read-write 0 EPWM_CHn interrupt flag accumulator Disabled #0 1 EPWM_CHn interrupt flag accumulator Enabled #1 IFASEL None 28 2 read-write 1 EPWM_CHn period in channel n #01 2 EPWM_CHn up-count compared point #10 3 EPWM_CHn down-count compared point #11 EPWM_IFA1 EPWM_IFA1 EPWM Interrupt Flag Accumulator Register 1 0x134 read-write n 0x0 0x0 EPWM_IFA2 EPWM_IFA2 EPWM Interrupt Flag Accumulator Register 2 0x138 read-write n 0x0 0x0 EPWM_IFA3 EPWM_IFA3 EPWM Interrupt Flag Accumulator Register 3 0x13C read-write n 0x0 0x0 EPWM_IFA4 EPWM_IFA4 EPWM Interrupt Flag Accumulator Register 4 0x140 read-write n 0x0 0x0 EPWM_IFA5 EPWM_IFA5 EPWM Interrupt Flag Accumulator Register 5 0x144 read-write n 0x0 0x0 EPWM_INTEN0 EPWM_INTEN0 EPWM Interrupt Enable Register 0 0xE0 read-write n 0x0 0x0 CMPDIEN0 EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 24 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN1 EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 25 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN2 EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 26 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN3 EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 27 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN4 EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 28 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN5 EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 29 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPUIEN0 EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 16 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN1 EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 17 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN2 EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 18 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN3 EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 19 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN4 EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 20 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN5 EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 21 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 PIEN0 EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN1 EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 9 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN2 EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 10 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN3 EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 11 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN4 EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 12 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN5 EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 13 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode. 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN1 EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode. 1 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN2 EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode. 2 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN3 EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode. 3 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN4 EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode. 4 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN5 EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode. 5 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 EPWM_INTEN1 EPWM_INTEN1 EPWM Interrupt Enable Register 1 0xE4 read-write n 0x0 0x0 BRKEIEN0_1 EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 Edge-detect Brake interrupt for channel0/1 Disabled #0 1 Edge-detect Brake interrupt for channel0/1 Enabled #1 BRKEIEN2_3 EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 Edge-detect Brake interrupt for channel2/3 Disabled #0 1 Edge-detect Brake interrupt for channel2/3 Enabled #1 BRKEIEN4_5 EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 Edge-detect Brake interrupt for channel4/5 Disabled #0 1 Edge-detect Brake interrupt for channel4/5 Enabled #1 BRKLIEN0_1 EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 Level-detect Brake interrupt for channel0/1 Disabled #0 1 Level-detect Brake interrupt for channel0/1 Enabled #1 BRKLIEN2_3 EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 Level-detect Brake interrupt for channel2/3 Disabled #0 1 Level-detect Brake interrupt for channel2/3 Enabled #1 BRKLIEN4_5 EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 Level-detect Brake interrupt for channel4/5 Disabled #0 1 Level-detect Brake interrupt for channel4/5 Enabled #1 EPWM_INTSTS0 EPWM_INTSTS0 EPWM Interrupt Flag Register 0 0xE8 read-write n 0x0 0x0 CMPDIF0 EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 24 1 read-write CMPDIF1 EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 25 1 read-write CMPDIF2 EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 26 1 read-write CMPDIF3 EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 27 1 read-write CMPDIF4 EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 28 1 read-write CMPDIF5 EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 29 1 read-write CMPUIF0 EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 16 1 read-write CMPUIF1 EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 17 1 read-write CMPUIF2 EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 18 1 read-write CMPUIF3 EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 19 1 read-write CMPUIF4 EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 20 1 read-write CMPUIF5 EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 21 1 read-write PIF0 EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1. 8 1 read-write PIF1 EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1. 9 1 read-write PIF2 EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1. 10 1 read-write PIF3 EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1. 11 1 read-write PIF4 EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1. 12 1 read-write PIF5 EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1. 13 1 read-write ZIF0 EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1 0 1 read-write ZIF1 EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1 1 1 read-write ZIF2 EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1 2 1 read-write ZIF3 EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1 3 1 read-write ZIF4 EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1 4 1 read-write ZIF5 EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1 5 1 read-write EPWM_INTSTS1 EPWM_INTSTS1 EPWM Interrupt Flag Register 1 0xEC read-write n 0x0 0x0 BRKEIF0 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF1 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF2 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF3 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 3 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF4 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF5 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKESTS0 EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 16 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS1 EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 17 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS2 EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 18 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS3 EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 19 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS4 EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 20 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS5 EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 21 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLIF0 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF1 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF2 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF3 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 11 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF4 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF5 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLSTS0 EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 24 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS1 EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 25 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS2 EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 26 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS3 EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 27 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS4 EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 28 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS5 EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 29 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 EPWM_LEBCNT EPWM_LEBCNT EPWM Leading Edge Blanking Counter Register 0x11C read-write n 0x0 0x0 LEBCNT EPWM Leading Edge Blanking Counter 0 9 read-write EPWM_LEBCTL EPWM_LEBCTL EPWM Leading Edge Blanking Control Register 0x118 read-write n 0x0 0x0 LEBEN EPWM Leading Edge Blanking Enable Bit 0 1 read-write 0 EPWM Leading Edge Blanking Disabled #0 1 EPWM Leading Edge Blanking Enabled #1 SRCEN0 EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit 8 1 read-write 0 EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled #0 1 EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled #1 SRCEN2 EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit 9 1 read-write 0 EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled #0 1 EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled #1 SRCEN4 EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit 10 1 read-write 0 EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled #0 1 EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled #1 TRGTYPE EPWM Leading Edge Blanking Trigger Type 16 2 read-write 0 When detect leading edge blanking source rising edge, blanking counter start counting 0 1 When detect leading edge blanking source falling edge, blanking counter start counting 1 2 When detect leading edge blanking source rising or falling edge, blanking counter start counting 2 3 Reserved 3 EPWM_LOAD EPWM_LOAD EPWM Load Register 0x28 read-write n 0x0 0x0 LOAD0 Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation: 0 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD1 Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation: 1 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD2 Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation: 2 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD3 Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation: 3 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD4 Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation: 4 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD5 Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation: 5 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 EPWM_MSK EPWM_MSK EPWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDAT0 EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 0 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT1 EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 1 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT2 EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 2 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT3 EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 3 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT4 EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 4 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT5 EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 5 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 EPWM_MSKEN EPWM_MSKEN EPWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKEN0 EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 0 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN1 EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 1 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN2 EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 2 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN3 EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 3 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN4 EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 4 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN5 EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 5 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 EPWM_PBUF0 EPWM_PBUF0 EPWM PERIOD0 Buffer 0x304 read-only n 0x0 0x0 PBUF EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only EPWM_PBUF1 EPWM_PBUF1 EPWM PERIOD1 Buffer 0x308 read-write n 0x0 0x0 EPWM_PBUF2 EPWM_PBUF2 EPWM PERIOD2 Buffer 0x30C read-write n 0x0 0x0 EPWM_PBUF3 EPWM_PBUF3 EPWM PERIOD3 Buffer 0x310 read-write n 0x0 0x0 EPWM_PBUF4 EPWM_PBUF4 EPWM PERIOD4 Buffer 0x314 read-write n 0x0 0x0 EPWM_PBUF5 EPWM_PBUF5 EPWM PERIOD5 Buffer 0x318 read-write n 0x0 0x0 EPWM_PDMACAP0_1 EPWM_PDMACAP0_1 EPWM Capture Channel 01 PDMA Register 0x240 read-only n 0x0 0x0 CAPBUF EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. 0 16 read-only EPWM_PDMACAP2_3 EPWM_PDMACAP2_3 EPWM Capture Channel 23 PDMA Register 0x244 read-write n 0x0 0x0 EPWM_PDMACAP4_5 EPWM_PDMACAP4_5 EPWM Capture Channel 45 PDMA Register 0x248 read-write n 0x0 0x0 EPWM_PDMACTL EPWM_PDMACTL EPWM PDMA Control Register 0x23C read-write n 0x0 0x0 CAPMOD0_1 Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer 1 2 read-write 0 Reserved #00 1 EPWM_RCAPDAT0/1 #01 2 EPWM_FCAPDAT0/1 #10 3 Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1 #11 CAPMOD2_3 Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer 9 2 read-write 0 Reserved #00 1 EPWM_RCAPDAT2/3 #01 2 EPWM_FCAPDAT2/3 #10 3 Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3 #11 CAPMOD4_5 Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer 17 2 read-write 0 Reserved #00 1 EPWM_RCAPDAT4/5 #01 2 EPWM_FCAPDAT4/5 #10 3 Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5 #11 CAPORD0_1 Capture Channel 0/1 Rising/Falling Order 3 1 read-write 0 EPWM_FCAPDAT0/1 is the first captured data to memory #0 1 EPWM_RCAPDAT0/1 is the first captured data to memory #1 CAPORD2_3 Capture Channel 2/3 Rising/Falling Order 11 1 read-write 0 EPWM_FCAPDAT2/3 is the first captured data to memory #0 1 EPWM_RCAPDAT2/3 is the first captured data to memory #1 CAPORD4_5 Capture Channel 4/5 Rising/Falling Order 19 1 read-write 0 EPWM_FCAPDAT4/5 is the first captured data to memory #0 1 EPWM_RCAPDAT4/5 is the first captured data to memory #1 CHEN0_1 Channel 0/1 PDMA Enable Bit 0 1 read-write 0 Channel 0/1 PDMA function Disabled #0 1 Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory #1 CHEN2_3 Channel 2/3 PDMA Enable Bit 8 1 read-write 0 Channel 2/3 PDMA function Disabled #0 1 Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory #1 CHEN4_5 Channel 4/5 PDMA Enable Bit 16 1 read-write 0 Channel 4/5 PDMA function Disabled #0 1 Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory #1 CHSEL0_1 Select Channel 0/1 to Do PDMA Transfer 4 1 read-write 0 Channel0 #0 1 Channel1 #1 CHSEL2_3 Select Channel 2/3 to Do PDMA Transfer 12 1 read-write 0 Channel2 #0 1 Channel3 #1 CHSEL4_5 Select Channel 4/5 to Do PDMA Transfer 20 1 read-write 0 Channel4 #0 1 Channel5 #1 EPWM_PERIOD0 EPWM_PERIOD0 EPWM Period Register 0 0x30 read-write n 0x0 0x0 PERIOD EPWM Period Register\nUp-Count mode: \nIn this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. 0 16 read-write EPWM_PERIOD1 EPWM_PERIOD1 EPWM Period Register 1 0x34 read-write n 0x0 0x0 EPWM_PERIOD2 EPWM_PERIOD2 EPWM Period Register 2 0x38 read-write n 0x0 0x0 EPWM_PERIOD3 EPWM_PERIOD3 EPWM Period Register 3 0x3C read-write n 0x0 0x0 EPWM_PERIOD4 EPWM_PERIOD4 EPWM Period Register 4 0x40 read-write n 0x0 0x0 EPWM_PERIOD5 EPWM_PERIOD5 EPWM Period Register 5 0x44 read-write n 0x0 0x0 EPWM_PHS0_1 EPWM_PHS0_1 EPWM Counter Phase Register 0/1 0x80 read-write n 0x0 0x0 PHS EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value. These bits only use in synchronous function. 0 16 read-write EPWM_PHS2_3 EPWM_PHS2_3 EPWM Counter Phase Register 2/3 0x84 read-write n 0x0 0x0 EPWM_PHS4_5 EPWM_PHS4_5 EPWM Counter Phase Register 4/5 0x88 read-write n 0x0 0x0 EPWM_POEN EPWM_POEN EPWM Output Enable Register 0xD8 read-write n 0x0 0x0 POEN0 EPWM Pin Output Enable Bits 0 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN1 EPWM Pin Output Enable Bits 1 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN2 EPWM Pin Output Enable Bits 2 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN3 EPWM Pin Output Enable Bits 3 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN4 EPWM Pin Output Enable Bits 4 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN5 EPWM Pin Output Enable Bits 5 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 EPWM_POLCTL EPWM_POLCTL EPWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINV0 EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output. 0 1 read-write 0 EPWMx_CHn output polar inverse Disabled #0 1 EPWMx_CHn output polar inverse Enabled #1 PINV1 EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output. 1 1 read-write 0 EPWMx_CHn output polar inverse Disabled #0 1 EPWMx_CHn output polar inverse Enabled #1 PINV2 EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output. 2 1 read-write 0 EPWMx_CHn output polar inverse Disabled #0 1 EPWMx_CHn output polar inverse Enabled #1 PINV3 EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output. 3 1 read-write 0 EPWMx_CHn output polar inverse Disabled #0 1 EPWMx_CHn output polar inverse Enabled #1 PINV4 EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output. 4 1 read-write 0 EPWMx_CHn output polar inverse Disabled #0 1 EPWMx_CHn output polar inverse Enabled #1 PINV5 EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output. 5 1 read-write 0 EPWMx_CHn output polar inverse Disabled #0 1 EPWMx_CHn output polar inverse Enabled #1 EPWM_RCAPDAT0 EPWM_RCAPDAT0 EPWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the EPWM counter value will be saved in this register. 0 16 read-only EPWM_RCAPDAT1 EPWM_RCAPDAT1 EPWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 EPWM_RCAPDAT2 EPWM_RCAPDAT2 EPWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 EPWM_RCAPDAT3 EPWM_RCAPDAT3 EPWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 EPWM_RCAPDAT4 EPWM_RCAPDAT4 EPWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 EPWM_RCAPDAT5 EPWM_RCAPDAT5 EPWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 EPWM_SSCTL EPWM_SSCTL EPWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSEN0 EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 0 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN1 EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN2 EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 2 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN3 EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 3 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN4 EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 4 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN5 EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 5 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSRC EPWM Synchronous Start Source Select Bits 8 2 read-write 0 Synchronous start source come from EPWM0 #00 1 Synchronous start source come from EPWM1 #01 2 Synchronous start source come from BPWM0 #10 3 Synchronous start source come from BPWM1 #11 EPWM_SSTRG EPWM_SSTRG EPWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN EPWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled. 0 1 write-only EPWM_STATUS EPWM_STATUS EPWM Status Register 0x120 read-write n 0x0 0x0 CNTMAXF0 Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1. 0 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF1 Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1. 1 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF2 Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1. 2 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF3 Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1. 3 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF4 Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1. 4 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF5 Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1. 5 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 DACTRGF DAC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1. 24 1 read-write 0 No DAC start of conversion trigger event has occurred #0 1 A DAC start of conversion trigger event has occurred #1 EADCTRGF0 EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1. 16 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF1 EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1. 17 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF2 EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1. 18 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF3 EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1. 19 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF4 EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1. 20 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF5 EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1. 21 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 SYNCINF0 Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1. 8 1 read-write 0 No SYNC_IN event has occurred #0 1 A SYNC_IN event has occurred #1 SYNCINF2 Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1. 9 1 read-write 0 No SYNC_IN event has occurred #0 1 A SYNC_IN event has occurred #1 SYNCINF4 Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1. 10 1 read-write 0 No SYNC_IN event has occurred #0 1 A SYNC_IN event has occurred #1 EPWM_SWBRK EPWM_SWBRK EPWM Software Brake Control Register 0xDC write-only n 0x0 0x0 BRKETRG0 EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 write-only BRKETRG2 EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 write-only BRKETRG4 EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 write-only BRKLTRG0 EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 write-only BRKLTRG2 EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 write-only BRKLTRG4 EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 write-only EPWM_SWSYNC EPWM_SWSYNC EPWM Software Control Synchronization Register 0xC read-write n 0x0 0x0 SWSYNC0 Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. 0 1 read-write SWSYNC2 Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. 1 1 read-write SWSYNC4 Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. 2 1 read-write EPWM_SYNC EPWM_SYNC EPWM Synchronization Register 0x8 read-write n 0x0 0x0 PHSDIR0 EPWM Phase Direction Control 24 1 read-write 0 Control EPWM counter count decrement after synchronizing #0 1 Control EPWM counter count increment after synchronizing #1 PHSDIR2 EPWM Phase Direction Control 25 1 read-write 0 Control EPWM counter count decrement after synchronizing #0 1 Control EPWM counter count increment after synchronizing #1 PHSDIR4 EPWM Phase Direction Control 26 1 read-write 0 Control EPWM counter count decrement after synchronizing #0 1 Control EPWM counter count increment after synchronizing #1 PHSEN0 SYNC Phase Enable Bits 0 1 read-write 0 EPWM counter disable to load PHS value #0 1 EPWM counter enable to load PHS value #1 PHSEN2 SYNC Phase Enable Bits 1 1 read-write 0 EPWM counter disable to load PHS value #0 1 EPWM counter enable to load PHS value #1 PHSEN4 SYNC Phase Enable Bits 2 1 read-write 0 EPWM counter disable to load PHS value #0 1 EPWM counter enable to load PHS value #1 SFLTCNT SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector. 20 3 read-write SFLTCSEL SYNC Edge Detector Filter Clock Selection 17 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 SINPINV SYNC Input Pin Inverse 23 1 read-write 0 The state of pin SYNC is passed to the negative edge detector #0 1 The inversed state of pin SYNC is passed to the negative edge detector #1 SINSRC0 EPWM0_SYNC_IN Source Selection 8 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT will not be generated #11 SINSRC2 EPWM0_SYNC_IN Source Selection 10 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT will not be generated #11 SINSRC4 EPWM0_SYNC_IN Source Selection 12 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT will not be generated #11 SNFLTEN EPWM0_SYNC_IN Noise Filter Enable Bits 16 1 read-write 0 Noise filter of input pin EPWM0_SYNC_IN Disabled #0 1 Noise filter of input pin EPWM0_SYNC_IN Enabled #1 EPWM_WGCTL0 EPWM_WGCTL0 EPWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTL0 EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type. 16 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL1 EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type. 18 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL2 EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type. 20 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL3 EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type. 22 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL4 EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type. 24 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL5 EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type. 26 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 ZPCTL0 EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0. 0 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL1 EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0. 2 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL2 EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0. 4 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL3 EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0. 6 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL4 EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0. 8 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL5 EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0. 10 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 EPWM_WGCTL1 EPWM_WGCTL1 EPWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTL0 EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 16 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL1 EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 18 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL2 EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 20 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL3 EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 22 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL4 EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 24 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL5 EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 26 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPUCTL0 EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 0 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL1 EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 2 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL2 EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 4 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL3 EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 6 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL4 EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 8 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL5 EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 10 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 FMC FMC Register Map FMC 0x0 0x0 0x14 registers n 0x40 0x4 registers n 0x4C 0x20 registers n 0x80 0x10 registers n 0xC0 0x8 registers n 0xD0 0x14 registers n CYCCTL FMC_CYCCTL Flash Access Cycle Control Register 0x4C -1 read-write n 0x0 0x0 CYCLE Flash Access Cycle Control (Write Protect) This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1).When auto-tuning function disabled, user needs to check the speed of HCLK and set the cycle 0. The optimized HCLK working frequency range is 49~79 MHz Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 4 read-write 0 CPU access with zero wait cycle Flash access cycle is 1 #0000 1 CPU access with one wait cycle if cache miss Flash access cycle is 1 #0001 2 CPU access with two wait cycles if cache miss Flash access cycle is 2 #0010 3 CPU access with three wait cycles if cache miss Flash access cycle is 3 #0011 FADIS Flash Access Cycle Auto-tuning Disable Bit (Write Protect)\nSet this bit to disable Flash access cycle auto-tuning function\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.When FMC is doing auto-tuning,we considered as a ISP operation need to monitor busy flag. 8 1 read-write 0 Flash access cycle auto-tuning Enabled #0 1 Flash access cycle auto-tuning Disabled #1 ISPADDR FMC_ISPADDR ISP Address Register 0x4 read-write n 0x0 0x0 ISPADDR ISP Address\nThe M261/M262/M263 series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.\nFor CRC32 Checksum Calculation command, this field is the Flash starting address for checksum calculation, 2 Kbytes alignment is necessary for CRC32 checksum calculation.\nFor Flash32-bit Program, ISP address needs word alignment (4-byte). For Flash 64-bit Program, ISP address needs double word alignment (8-byte). 0 32 read-write ISPCMD FMC_ISPCMD ISP Command Register 0xC read-write n 0x0 0x0 CMD ISP Command\nISP command table is shown below:\nThe other commands are invalid. 0 7 read-write 0 FLASH Read 0x00 4 Read Unique ID 0x04 8 Read Flash All-One Result 0x08 11 Read Company ID 0x0b 12 Read Device ID 0x0c 13 Read Checksum 0x0d 33 FLASH 32-bit Program 0x21 34 FLASH Page Erase. Erase any page in two banks, except for OTP 0x22 35 FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1 0x23 37 FLASH Block Erase. Erase four pages alignment of APROM in BANK0 or BANK1 0x25 39 FLASH Multi-Word Program 0x27 40 Run Flash All-One Verification 0x28 45 Run Checksum Calculation 0x2d 46 Vector Remap 0x2e 64 FLASH 64-bit Read 0x40 97 FLASH 64-bit Program 0x61 ISPCTL FMC_ISPCTL ISP Control Register 0x0 read-write n 0x0 0x0 APUEN APROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 APROM cannot be updated when the chip runs in APROM #0 1 APROM can be updated when the chip runs in APROM #1 BS Boot Select (Write Protect) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Boot from APROM #0 1 Boot from LDROM #1 CFGUEN CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 CONFIG cannot be updated #0 1 CONFIG can be updated #1 INTEN ISP INT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. Before using INT, user needs to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time. 24 1 read-write 0 ISP INT Disabled #0 1 ISP INT Enabled #1 ISPEN ISP Enable Bit (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 ISP function Disabled #0 1 ISP function Enabled #1 ISPFF ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\n(8) KPROM is erased/programmed if KEYLOCK is set to 1\n(9) APROM is erased/programmed if KEYLOCK is set to 1\n(10) LDROM is erased/programmed if KEYLOCK is set to 1\n(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0 \n(12) The address of block erase and bank erase is not in APROM\n(13) ISP CMD in XOM region, except mass erase, page erase and chksum command\n(14) The wrong setting of page erase ISP CMD in XOM\n(15) Violate XOM setting one time protection \n(16) Mass erase when MERASE (CFG0[13]) is disable\n(17) Page erase, mass erase , multi-word program or 64-bit word program in OTP\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write LDUEN LDROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 LDROM cannot be updated #0 1 LDROM can be updated #1 ISPDAT FMC_ISPDAT ISP Data Register 0x8 read-write n 0x0 0x0 ISPDAT ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation. 0 32 read-write ISPSTS FMC_ISPSTS ISP Status Register 0x40 read-write n 0x0 0x0 ALLONE Flash All-one Verification Flag This bit is set by hardware if all of Flash bits are 1, and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete this bit also can be clear by writing 1 7 1 read-write 0 Flash bits are not all 1 after 'Run Flash All-One Verification' complete #0 1 All of Flash bits are 1 after 'Run Flash All-One Verification' complete #1 CBS Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. 2 1 read-only 0 LDROM with IAP mode #0 1 APROM with IAP mode #1 FCYCDIS Flash Access Cycle Auto-tuning Disable Flag (Read Only)\nThis bit is set if Flash access cycle auto-tunning function is disabled. The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready. 4 1 read-only 0 Flash access cycle auto-tuning Enabled #0 1 Flash access cyle auto-tuning Disabled #1 INTFLAG None 24 1 read-write 0 ISP not finished #0 1 ISP done or ISPFF set #1 ISPBUSY ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]). 0 1 read-only 0 ISP operation is finished #0 1 ISP is progressed #1 ISPFF ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\n(8) KPROM is erased/programmed if KEYLOCK is set to 1\n(9) APROM is erased/programmed if KEYLOCK is set to 1\n(10) LDROM is erased/programmed if KEYLOCK is set to 1\n(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0.\n(12) The address of block erase and bank erase is not in APROM\n(13) ISP CMD in XOM region, except mass erase, page erase and chksum command\n(14) The wrong setting of page erase ISP CMD in XOM\n(15) Violate XOM setting one time protection \n(16) Mass erase when MERASE (CFG0[13]) is disable\n(17) Page erase, mass erase , multi-word program or 64-bit word program in OTP\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write PGFF Flash Program with Fast Verification Flag (Read Only)\nThis bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP Flash erase or ISP read CID operation 5 1 read-only 0 Flash Program is success #0 1 Flash Program is fail. Program data is different with data in the Flash memory #1 VECMAP Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF} 9 15 read-only ISPTRG FMC_ISPTRG ISP Trigger Control Register 0x10 read-write n 0x0 0x0 ISPGO ISP Start Trigger (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 ISP operation is finished #0 1 ISP is progressed #1 KPCNT FMC_KPCNT KPROM KEY-Unmatched Power-On Counting Register 0x68 read-only n 0x0 0x0 KPCNT Power-on Counter for Error Key Entry (Read Only)\nKPCNT is the power-on counting for error key entry in Security Key protection. KPCNT is cleared to 0 if key comparison is matched. 0 4 read-only KPMAX Power-on Maximum Number for Error Key Entry (Read Only)\nKPMAX is the power-on maximum number for error key entry. When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated. KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting. The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX 8 4 read-only KPKEY0 FMC_KPKEY0 KPROM KEY0 Data Register 0x50 write-only n 0x0 0x0 KPKEY0 KPROM KEY0 Data (Write Only)\nWrite KPKEY0 data to this register before KEY Comparison operation. 0 32 write-only KPKEY1 FMC_KPKEY1 KPROM KEY1 Data Register 0x54 write-only n 0x0 0x0 KPKEY1 KPROM KEY1 Data (Write Only)\nWrite KPKEY1 data to this register before KEY Comparison operation. 0 32 write-only KPKEY2 FMC_KPKEY2 KPROM KEY2 Data Register 0x58 write-only n 0x0 0x0 KPKEY2 KPROM KEY2 Data (Write Only)\nWrite KPKEY2 data to this register before KEY Comparison operation. 0 32 write-only KPKEYCNT FMC_KPKEYCNT KPROM KEY-Unmatched Counting Register 0x64 read-only n 0x0 0x0 KPKECNT Error Key Entry Counter at Each Power-on (Read Only)\nKPKECNT is increased when entry keys is wrong in Security Key protection. KPKECNT is cleared to 0 if key comparison is matched or system power-on. 0 6 read-only KPKEMAX Maximum Number for Error Key Entry at Each Power-on (Read Only)\nKPKEMAX is the maximum error key entry number at each power-on. When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated. KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting. The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX. 8 6 read-only KPKEYSTS FMC_KPKEYSTS KPROM KEY Comparison Status Register 0x60 -1 read-write n 0x0 0x0 CFGFLAG CONFIG Write-protection Enable Flag (Read Only)\nThis bit is set while the KEYENROM [0] is 0 at power-on or reset. This bit is cleared to 0 by hardware while KPROM is erased. This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0. 5 1 read-only 0 CONFIG write-protection Disabled #0 1 CONFIG write-protection Enabled #1 FORBID KEY Comparison Forbidden Flag (Read Only)\nThis bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]). 3 1 read-only 0 KEY comparison is not forbidden #0 1 KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger #1 KEYBUSY KEY Comparison Busy (Read Only) 0 1 read-only 0 KEY comparison is finished #0 1 KEY comparison is busy #1 KEYFLAG KEY Protection Enable Flag (Read Only)\nThis bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset. This bit is cleared to 0 by hardware while KPROM is erased. This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value. 4 1 read-only 0 Security Key protection Disabled #0 1 Security Key protection Enabled #1 KEYLOCK KEY LOCK Flag \nThis bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection. After Mass Erase operation, users must reset or power on /off to clear this bit to 0. This bit also can be set to 1 while:\nCPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or\nKEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or\nKEYENROM is programmed a non-0xFF value or\nTimeout event or\nFORBID(FMC_KPKEYSTS[3]) is 1\nCONFIG write protect is dependent on CFGFLAG. 1 1 read-write 0 KPROM, LDROM and APROM is not in write protection #0 1 KPROM, LDROM and APROM is in write protection #1 KEYMATCH KEY Match Flag (Read Only) This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM and cleared to 0 if KEYs are unmatched. This bit is also cleared to 0 while CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or Timeout event or KPROM is erased or KEYENROM is programmed to a non-0xFF value. Chip is in Power-down mode. 2 1 read-only 0 KEY0, KEY1, and KEY2 are unmatched with the KPROM setting #0 1 KEY0, KEY1, and KEY2 are matched with the KPROM setting #1 KPKEYTRG FMC_KPKEYTRG KPROM KEY Comparison Trigger Control Register 0x5C read-write n 0x0 0x0 KPKEYGO KPROM KEY Comparison Start Trigger (Write Protect)\nWrite 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished. This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0.\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 KEY comparison operation is finished #0 1 KEY comparison is progressed #1 TCEN Timeout Counting Enable Bit (Write Protect)\n10 minutes is at least for timeout, and average is about 20 minutes.\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Timeout counting Disabled #0 1 Timeout counting Enabled if input key is matched after key comparison finished #1 MPADDR FMC_MPADDR ISP Multi-Program Address Register 0xC4 read-only n 0x0 0x0 MPADDR ISP Multi-word Program Address\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete. 0 32 read-only MPDAT0 FMC_MPDAT0 ISP Data0 Register 0x80 read-write n 0x0 0x0 ISPDAT0 ISP Data 0\nThis register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data. 0 32 read-write MPDAT1 FMC_MPDAT1 ISP Data1 Register 0x84 read-write n 0x0 0x0 ISPDAT1 ISP Data 1\nThis register is the second 32-bit data for 64-bit/multi-word programming. 0 32 read-write MPDAT2 FMC_MPDAT2 ISP Data2 Register 0x88 read-write n 0x0 0x0 ISPDAT2 ISP Data 2\nThis register is the third 32-bit data for multi-word programming. 0 32 read-write MPDAT3 FMC_MPDAT3 ISP Data3 Register 0x8C read-write n 0x0 0x0 ISPDAT3 ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming. 0 32 read-write MPSTS FMC_MPSTS ISP Multi-Program Status Register 0xC0 read-only n 0x0 0x0 D0 ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete. 4 1 read-only 0 FMC_MPDAT0 register is empty, or program to Flash complete #0 1 FMC_MPDAT0 register has been written, and not program to Flash complete #1 D1 ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete. 5 1 read-only 0 FMC_MPDAT1 register is empty, or program to Flash complete #0 1 FMC_MPDAT1 register has been written, and not program to Flash complete #1 D2 ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete. 6 1 read-only 0 FMC_MPDAT2 register is empty, or program to Flash complete #0 1 FMC_MPDAT2 register has been written, and not program to Flash complete #1 D3 ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete. 7 1 read-only 0 FMC_MPDAT3 register is empty, or program to Flash complete #0 1 FMC_MPDAT3 register has been written, and not program to Flash complete #1 ISPFF ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands.\n(8) KPROM is erased/programmed if KEYLOCK is set to 1\n(9) APROM is erased/programmed if KEYLOCK is set to 1\n(10) LDROM is erased/programmed if KEYLOCK is set to 1\n(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0.\n(12) The address of block erase and bank erase is not in APROM\n(13) ISP CMD in XOM region, except mass erase, page erase and chksum command\n(14) The wrong setting of page erase ISP CMD in XOM\n(15) Violate XOM setting one time protection \n(16) Mass erase when MERASE (CFG0[13]) is disable\n(17) Page erase, mass erase , multi-word program or 64-bit word program in OTP 2 1 read-only MPBUSY ISP Multi-word Program Busy Flag (Read Only)\nWrite 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]). 0 1 read-only 0 ISP Multi-Word program operation is finished #0 1 ISP Multi-Word program operation is progressed #1 PPGO ISP Multi-program Status (Read Only) 1 1 read-only 0 ISP multi-word program operation is not active #0 1 ISP multi-word program operation is in progress #1 XOMR0STS FMC_XOMR0STS XOM Region 0 Status Register 0xD0 -1 read-only n 0x0 0x0 BASE XOM Region 0 Base Address (Page-aligned)\nBASE is the base address of XOM Region 0. 8 24 read-only SIZE XOM Region 0 Size (Page-aligned)\nSIZE is the page number of XOM Region 0. 0 8 read-only XOMR1STS FMC_XOMR1STS XOM Region 1 Status Register 0xD4 -1 read-only n 0x0 0x0 BASE XOM Region 1 Base Address (Page-aligned)\nBASE is the base address of XOM Region 1. 8 24 read-only SIZE XOM Region 1 Size (Page-aligned)\nSIZE is the page number of XOM Region 1. 0 8 read-only XOMR2STS FMC_XOMR2STS XOM Region 2 Status Register 0xD8 -1 read-only n 0x0 0x0 BASE XOM Region 2 Base Address (Page-aligned)\nBASE is the base address of XOM Region 2. 8 24 read-only SIZE XOM Region 2 Size (Page-aligned)\nSIZE is the page number of XOM Region 2. 0 8 read-only XOMR3STS FMC_XOMR3STS XOM Region 3 Status Register 0xDC -1 read-only n 0x0 0x0 BASE XOM Region 3 Base Address (Page-aligned)\nBASE is the base address of XOM Region 3. 8 24 read-only SIZE XOM Region 3 Size (Page-aligned)\nSIZE is the page number of XOM Region 3. 0 8 read-only XOMSTS FMC_XOMSTS XOM Status Register 0xE0 read-only n 0x0 0x0 XOMPEF XOM Page Erase Function Fail\nXOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again. 4 1 read-only 0 Sucess #0 1 Fail #1 XOMR0ON XOM Region 0 On\nXOM Region 0 active status. 0 1 read-only 0 No active #0 1 XOM region 0 is active #1 XOMR1ON XOM Region 1 On\nXOM Region 1 active status. 1 1 read-only 0 No active #0 1 XOM region 1 is active #1 XOMR2ON XOM Region 2 On\nXOM Region 2 active status. 2 1 read-only 0 No active #0 1 XOM region 2 is active #1 XOMR3ON XOM Region 3 On\nXOM Region 3 active status. 3 1 read-only 0 No active #0 1 XOM region 3 is active #1 GPIO GPIO Register Map GPIO 0x0 0x0 0x2C registers n 0x100 0x2C registers n 0x130 0x8 registers n 0x140 0x2C registers n 0x170 0x8 registers n 0x180 0x2C registers n 0x1B0 0x8 registers n 0x1C0 0x2C registers n 0x1F0 0x8 registers n 0x30 0x8 registers n 0x40 0x2C registers n 0x70 0x8 registers n 0x80 0x2C registers n 0x800 0x200 registers n 0xB0 0x8 registers n 0xC0 0x2C registers n 0xF0 0x8 registers n PA0_PDIO PA0_PDIO GPIO PA.n Pin Data Input/Output Register 0x800 read-write n 0x0 0x0 PDIO GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value. 0 1 read-write 0 Corresponding GPIO pin set to low #0 1 Corresponding GPIO pin set to high #1 PA10_PDIO PA10_PDIO GPIO PA.n Pin Data Input/Output Register 0x828 read-write n 0x0 0x0 PA11_PDIO PA11_PDIO GPIO PA.n Pin Data Input/Output Register 0x82C read-write n 0x0 0x0 PA12_PDIO PA12_PDIO GPIO PA.n Pin Data Input/Output Register 0x830 read-write n 0x0 0x0 PA13_PDIO PA13_PDIO GPIO PA.n Pin Data Input/Output Register 0x834 read-write n 0x0 0x0 PA14_PDIO PA14_PDIO GPIO PA.n Pin Data Input/Output Register 0x838 read-write n 0x0 0x0 PA15_PDIO PA15_PDIO GPIO PA.n Pin Data Input/Output Register 0x83C read-write n 0x0 0x0 PA1_PDIO PA1_PDIO GPIO PA.n Pin Data Input/Output Register 0x804 read-write n 0x0 0x0 PA2_PDIO PA2_PDIO GPIO PA.n Pin Data Input/Output Register 0x808 read-write n 0x0 0x0 PA3_PDIO PA3_PDIO GPIO PA.n Pin Data Input/Output Register 0x80C read-write n 0x0 0x0 PA4_PDIO PA4_PDIO GPIO PA.n Pin Data Input/Output Register 0x810 read-write n 0x0 0x0 PA5_PDIO PA5_PDIO GPIO PA.n Pin Data Input/Output Register 0x814 read-write n 0x0 0x0 PA6_PDIO PA6_PDIO GPIO PA.n Pin Data Input/Output Register 0x818 read-write n 0x0 0x0 PA7_PDIO PA7_PDIO GPIO PA.n Pin Data Input/Output Register 0x81C read-write n 0x0 0x0 PA8_PDIO PA8_PDIO GPIO PA.n Pin Data Input/Output Register 0x820 read-write n 0x0 0x0 PA9_PDIO PA9_PDIO GPIO PA.n Pin Data Input/Output Register 0x824 read-write n 0x0 0x0 PA_DATMSK PA_DATMSK PA Data Output Write Mask 0xC read-write n 0x0 0x0 DATMSK0 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 0 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK1 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 1 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK10 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 10 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK11 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 11 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK12 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 12 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK13 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 13 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK14 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 14 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK15 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 15 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK2 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 2 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK3 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 3 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK4 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 4 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK5 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 5 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK6 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 6 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK7 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 7 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK8 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 8 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK9 Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective. 9 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 PA_DBCTL PA_DBCTL PA Interrupt De-bounce Control Register 0x34 -1 read-write n 0x0 0x0 DBCLKSEL De-bounce Sampling Cycle Selection 0 4 read-write 0 Sample interrupt input once per 1 clocks #0000 1 Sample interrupt input once per 2 clocks #0001 2 Sample interrupt input once per 4 clocks #0010 3 Sample interrupt input once per 8 clocks #0011 4 Sample interrupt input once per 16 clocks #0100 5 Sample interrupt input once per 32 clocks #0101 6 Sample interrupt input once per 64 clocks #0110 7 Sample interrupt input once per 128 clocks #0111 8 Sample interrupt input once per 256 clocks #1000 9 Sample interrupt input once per 2*256 clocks #1001 10 Sample interrupt input once per 4*256 clocks #1010 11 Sample interrupt input once per 8*256 clocks #1011 12 Sample interrupt input once per 16*256 clocks #1100 13 Sample interrupt input once per 32*256 clocks #1101 14 Sample interrupt input once per 64*256 clocks #1110 15 Sample interrupt input once per 128*256 clocks #1111 DBCLKSRC De-bounce Counter Clock Source Selection 4 1 read-write 0 De-bounce counter clock source is the HCLK #0 1 De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC) #1 ICLKON Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern. 5 1 read-write 0 Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1 #0 1 All I/O pins edge detection circuit is always active after reset #1 PA_DBEN PA_DBEN PA De-Bounce Enable Control Register 0x14 read-write n 0x0 0x0 DBEN0 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 0 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN1 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 1 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN10 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 10 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN11 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 11 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN12 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 12 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN13 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 13 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN14 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 14 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN15 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 15 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN2 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 2 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN3 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 3 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN4 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 4 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN5 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 5 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN6 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 6 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN7 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 7 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN8 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 8 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN9 Port A-h Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 9 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 PA_DINOFF PA_DINOFF PA Digital Input Path Disable Control 0x4 read-write n 0x0 0x0 DINOFF0 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 16 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF1 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 17 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF10 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 26 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF11 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 27 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF12 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 28 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF13 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 29 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF14 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 30 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF15 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 31 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF2 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 18 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF3 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 19 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF4 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 20 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF5 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 21 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF6 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 22 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF7 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 23 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF8 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 24 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF9 Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 25 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 PA_DOUT PA_DOUT PA Data Output Value 0x8 -1 read-write n 0x0 0x0 DOUT0 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 0 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT1 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 1 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT10 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 10 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT11 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 11 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT12 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 12 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT13 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 13 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT14 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 14 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT15 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 15 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT2 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 2 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT3 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 3 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT4 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 4 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT5 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 5 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT6 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 6 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT7 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 7 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT8 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 8 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT9 Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 9 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 PA_INTEN PA_INTEN PA Interrupt Enable Control Register 0x1C read-write n 0x0 0x0 FLIEN0 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 0 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN1 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 1 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN10 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 10 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN11 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 11 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN12 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 12 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN13 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 13 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN14 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 14 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN15 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 15 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN2 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 2 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN3 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 3 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN4 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 4 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN5 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 5 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN6 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 6 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN7 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 7 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN8 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 8 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN9 Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 9 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 RHIEN0 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 16 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN1 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 17 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN10 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 26 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN11 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 27 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN12 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 28 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN13 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 29 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN14 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 30 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN15 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 31 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN2 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 18 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN3 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 19 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN4 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 20 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN5 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 21 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN6 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 22 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN7 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 23 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN8 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 24 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN9 Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 25 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 PA_INTSRC PA_INTSRC PA Interrupt Source Flag 0x20 read-write n 0x0 0x0 INTSRC0 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 0 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC1 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 1 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC10 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 10 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC11 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 11 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC12 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 12 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC13 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 13 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC14 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 14 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC15 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 15 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC2 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 2 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC3 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 3 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC4 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 4 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC5 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 5 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC6 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 6 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC7 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 7 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC8 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 8 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC9 Port A-h Pin[n] Interrupt Source Flag\nWrite Operation: 9 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 PA_INTTYPE PA_INTTYPE PA Interrupt Trigger Type Control 0x18 read-write n 0x0 0x0 TYPE0 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 0 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE1 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 1 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE10 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 10 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE11 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 11 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE12 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 12 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE13 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 13 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE14 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 14 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE15 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 15 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE2 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 2 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE3 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 3 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE4 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 4 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE5 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 5 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE6 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 6 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE7 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 7 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE8 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 8 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE9 Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 9 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 PA_MODE PA_MODE PA I/O Mode Control 0x0 read-write n 0x0 0x0 MODE0 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 0 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE1 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 2 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE10 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 20 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE11 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 22 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE12 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 24 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE13 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 26 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE14 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 28 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE15 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 30 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE2 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 4 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE3 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 6 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE4 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 8 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE5 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 10 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE6 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 12 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE7 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 14 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE8 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 16 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE9 Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins. 18 2 read-write 0 Px.n is in Input mode (tri-state) #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 PA_PIN PA_PIN PA Pin Value 0x10 read-only n 0x0 0x0 PIN0 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 0 1 read-only PIN1 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 1 1 read-only PIN10 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 10 1 read-only PIN11 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 11 1 read-only PIN12 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 12 1 read-only PIN13 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 13 1 read-only PIN14 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 14 1 read-only PIN15 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 15 1 read-only PIN2 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 2 1 read-only PIN3 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 3 1 read-only PIN4 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 4 1 read-only PIN5 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 5 1 read-only PIN6 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 6 1 read-only PIN7 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 7 1 read-only PIN8 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 8 1 read-only PIN9 Port A-h Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 9 1 read-only PA_PUSEL PA_PUSEL PA Pull-up and Pull-down Selection Register 0x30 read-write n 0x0 0x0 PUSEL0 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 0 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PUSEL1 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 2 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PUSEL10 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 20 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PUSEL11 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 22 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PUSEL12 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 24 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PUSEL13 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 26 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PUSEL14 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 28 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PUSEL15 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 30 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PUSEL2 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 4 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PUSEL3 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 6 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PUSEL4 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 8 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PUSEL5 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 10 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PUSEL6 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 12 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PUSEL7 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 14 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PUSEL8 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 16 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PUSEL9 Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins. 18 2 read-write 0 Px.n pull-up and pull-down disable #00 1 Px.n pull-up enable #01 2 Px.n pull-down enable #10 3 Px.n pull-up and pull-down disable #11 PA_SLEWCTL PA_SLEWCTL PA High Slew Rate Control Register 0x28 read-write n 0x0 0x0 HSREN0 Port A-h Pin[n] High Slew Rate Control 0 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 HSREN1 Port A-h Pin[n] High Slew Rate Control 2 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 HSREN10 Port A-h Pin[n] High Slew Rate Control 20 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 HSREN11 Port A-h Pin[n] High Slew Rate Control 22 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 HSREN12 Port A-h Pin[n] High Slew Rate Control 24 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 HSREN13 Port A-h Pin[n] High Slew Rate Control 26 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 HSREN14 Port A-h Pin[n] High Slew Rate Control 28 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 HSREN15 Port A-h Pin[n] High Slew Rate Control 30 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 HSREN2 Port A-h Pin[n] High Slew Rate Control 4 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 HSREN3 Port A-h Pin[n] High Slew Rate Control 6 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 HSREN4 Port A-h Pin[n] High Slew Rate Control 8 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 HSREN5 Port A-h Pin[n] High Slew Rate Control 10 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 HSREN6 Port A-h Pin[n] High Slew Rate Control 12 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 HSREN7 Port A-h Pin[n] High Slew Rate Control 14 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 HSREN8 Port A-h Pin[n] High Slew Rate Control 16 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 HSREN9 Port A-h Pin[n] High Slew Rate Control 18 2 read-write 0 Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V) #00 1 Px.n output with high slew rate mode (maximum 80 MHz at 2.7V) #01 2 Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V) #10 3 Reserved #11 PA_SMTEN PA_SMTEN PA Input Schmitt Trigger Enable Register 0x24 read-write n 0x0 0x0 SMTEN0 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 0 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN1 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 1 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN10 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 10 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN11 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 11 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN12 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 12 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN13 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 13 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN14 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 14 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN15 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 15 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN2 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 2 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN3 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 3 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN4 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 4 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN5 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 5 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN6 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 6 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN7 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 7 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN8 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 8 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN9 Port A-h Pin[n] Input Schmitt Trigger Enable Bit 9 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 PB0_PDIO PB0_PDIO GPIO PB.n Pin Data Input/Output Register 0x840 read-write n 0x0 0x0 PB10_PDIO PB10_PDIO GPIO PB.n Pin Data Input/Output Register 0x868 read-write n 0x0 0x0 PB11_PDIO PB11_PDIO GPIO PB.n Pin Data Input/Output Register 0x86C read-write n 0x0 0x0 PB12_PDIO PB12_PDIO GPIO PB.n Pin Data Input/Output Register 0x870 read-write n 0x0 0x0 PB13_PDIO PB13_PDIO GPIO PB.n Pin Data Input/Output Register 0x874 read-write n 0x0 0x0 PB14_PDIO PB14_PDIO GPIO PB.n Pin Data Input/Output Register 0x878 read-write n 0x0 0x0 PB15_PDIO PB15_PDIO GPIO PB.n Pin Data Input/Output Register 0x87C read-write n 0x0 0x0 PB1_PDIO PB1_PDIO GPIO PB.n Pin Data Input/Output Register 0x844 read-write n 0x0 0x0 PB2_PDIO PB2_PDIO GPIO PB.n Pin Data Input/Output Register 0x848 read-write n 0x0 0x0 PB3_PDIO PB3_PDIO GPIO PB.n Pin Data Input/Output Register 0x84C read-write n 0x0 0x0 PB4_PDIO PB4_PDIO GPIO PB.n Pin Data Input/Output Register 0x850 read-write n 0x0 0x0 PB5_PDIO PB5_PDIO GPIO PB.n Pin Data Input/Output Register 0x854 read-write n 0x0 0x0 PB6_PDIO PB6_PDIO GPIO PB.n Pin Data Input/Output Register 0x858 read-write n 0x0 0x0 PB7_PDIO PB7_PDIO GPIO PB.n Pin Data Input/Output Register 0x85C read-write n 0x0 0x0 PB8_PDIO PB8_PDIO GPIO PB.n Pin Data Input/Output Register 0x860 read-write n 0x0 0x0 PB9_PDIO PB9_PDIO GPIO PB.n Pin Data Input/Output Register 0x864 read-write n 0x0 0x0 PB_DATMSK PB_DATMSK PB Data Output Write Mask 0x4C read-write n 0x0 0x0 PB_DBCTL PB_DBCTL PB Interrupt De-bounce Control Register 0x74 read-write n 0x0 0x0 PB_DBEN PB_DBEN PB De-Bounce Enable Control Register 0x54 read-write n 0x0 0x0 PB_DINOFF PB_DINOFF PB Digital Input Path Disable Control 0x44 read-write n 0x0 0x0 PB_DOUT PB_DOUT PB Data Output Value 0x48 read-write n 0x0 0x0 PB_INTEN PB_INTEN PB Interrupt Enable Control Register 0x5C read-write n 0x0 0x0 PB_INTSRC PB_INTSRC PB Interrupt Source Flag 0x60 read-write n 0x0 0x0 PB_INTTYPE PB_INTTYPE PB Interrupt Trigger Type Control 0x58 read-write n 0x0 0x0 PB_MODE PB_MODE PB I/O Mode Control 0x40 read-write n 0x0 0x0 PB_PIN PB_PIN PB Pin Value 0x50 read-write n 0x0 0x0 PB_PUSEL PB_PUSEL PB Pull-up and Pull-down Selection Register 0x70 read-write n 0x0 0x0 PB_SLEWCTL PB_SLEWCTL PB High Slew Rate Control Register 0x68 read-write n 0x0 0x0 PB_SMTEN PB_SMTEN PB Input Schmitt Trigger Enable Register 0x64 read-write n 0x0 0x0 PC0_PDIO PC0_PDIO GPIO PC.n Pin Data Input/Output Register 0x880 read-write n 0x0 0x0 PC10_PDIO PC10_PDIO GPIO PC.n Pin Data Input/Output Register 0x8A8 read-write n 0x0 0x0 PC11_PDIO PC11_PDIO GPIO PC.n Pin Data Input/Output Register 0x8AC read-write n 0x0 0x0 PC12_PDIO PC12_PDIO GPIO PC.n Pin Data Input/Output Register 0x8B0 read-write n 0x0 0x0 PC13_PDIO PC13_PDIO GPIO PC.n Pin Data Input/Output Register 0x8B4 read-write n 0x0 0x0 PC14_PDIO PC14_PDIO GPIO PC.n Pin Data Input/Output Register 0x8B8 read-write n 0x0 0x0 PC15_PDIO PC15_PDIO GPIO PC.n Pin Data Input/Output Register 0x8BC read-write n 0x0 0x0 PC1_PDIO PC1_PDIO GPIO PC.n Pin Data Input/Output Register 0x884 read-write n 0x0 0x0 PC2_PDIO PC2_PDIO GPIO PC.n Pin Data Input/Output Register 0x888 read-write n 0x0 0x0 PC3_PDIO PC3_PDIO GPIO PC.n Pin Data Input/Output Register 0x88C read-write n 0x0 0x0 PC4_PDIO PC4_PDIO GPIO PC.n Pin Data Input/Output Register 0x890 read-write n 0x0 0x0 PC5_PDIO PC5_PDIO GPIO PC.n Pin Data Input/Output Register 0x894 read-write n 0x0 0x0 PC6_PDIO PC6_PDIO GPIO PC.n Pin Data Input/Output Register 0x898 read-write n 0x0 0x0 PC7_PDIO PC7_PDIO GPIO PC.n Pin Data Input/Output Register 0x89C read-write n 0x0 0x0 PC8_PDIO PC8_PDIO GPIO PC.n Pin Data Input/Output Register 0x8A0 read-write n 0x0 0x0 PC9_PDIO PC9_PDIO GPIO PC.n Pin Data Input/Output Register 0x8A4 read-write n 0x0 0x0 PC_DATMSK PC_DATMSK PC Data Output Write Mask 0x8C read-write n 0x0 0x0 PC_DBCTL PC_DBCTL PC Interrupt De-bounce Control Register 0xB4 read-write n 0x0 0x0 PC_DBEN PC_DBEN PC De-Bounce Enable Control Register 0x94 read-write n 0x0 0x0 PC_DINOFF PC_DINOFF PC Digital Input Path Disable Control 0x84 read-write n 0x0 0x0 PC_DOUT PC_DOUT PC Data Output Value 0x88 read-write n 0x0 0x0 PC_INTEN PC_INTEN PC Interrupt Enable Control Register 0x9C read-write n 0x0 0x0 PC_INTSRC PC_INTSRC PC Interrupt Source Flag 0xA0 read-write n 0x0 0x0 PC_INTTYPE PC_INTTYPE PC Interrupt Trigger Type Control 0x98 read-write n 0x0 0x0 PC_MODE PC_MODE PC I/O Mode Control 0x80 read-write n 0x0 0x0 PC_PIN PC_PIN PC Pin Value 0x90 read-write n 0x0 0x0 PC_PUSEL PC_PUSEL PC Pull-up and Pull-down Selection Register 0xB0 read-write n 0x0 0x0 PC_SLEWCTL PC_SLEWCTL PC High Slew Rate Control Register 0xA8 read-write n 0x0 0x0 PC_SMTEN PC_SMTEN PC Input Schmitt Trigger Enable Register 0xA4 read-write n 0x0 0x0 PD0_PDIO PD0_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C0 read-write n 0x0 0x0 PD10_PDIO PD10_PDIO GPIO PD.n Pin Data Input/Output Register 0x8E8 read-write n 0x0 0x0 PD11_PDIO PD11_PDIO GPIO PD.n Pin Data Input/Output Register 0x8EC read-write n 0x0 0x0 PD12_PDIO PD12_PDIO GPIO PD.n Pin Data Input/Output Register 0x8F0 read-write n 0x0 0x0 PD13_PDIO PD13_PDIO GPIO PD.n Pin Data Input/Output Register 0x8F4 read-write n 0x0 0x0 PD14_PDIO PD14_PDIO GPIO PD.n Pin Data Input/Output Register 0x8F8 read-write n 0x0 0x0 PD15_PDIO PD15_PDIO GPIO PD.n Pin Data Input/Output Register 0x8FC read-write n 0x0 0x0 PD1_PDIO PD1_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C4 read-write n 0x0 0x0 PD2_PDIO PD2_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C8 read-write n 0x0 0x0 PD3_PDIO PD3_PDIO GPIO PD.n Pin Data Input/Output Register 0x8CC read-write n 0x0 0x0 PD4_PDIO PD4_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D0 read-write n 0x0 0x0 PD5_PDIO PD5_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D4 read-write n 0x0 0x0 PD6_PDIO PD6_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D8 read-write n 0x0 0x0 PD7_PDIO PD7_PDIO GPIO PD.n Pin Data Input/Output Register 0x8DC read-write n 0x0 0x0 PD8_PDIO PD8_PDIO GPIO PD.n Pin Data Input/Output Register 0x8E0 read-write n 0x0 0x0 PD9_PDIO PD9_PDIO GPIO PD.n Pin Data Input/Output Register 0x8E4 read-write n 0x0 0x0 PD_DATMSK PD_DATMSK PD Data Output Write Mask 0xCC read-write n 0x0 0x0 PD_DBCTL PD_DBCTL PD Interrupt De-bounce Control Register 0xF4 read-write n 0x0 0x0 PD_DBEN PD_DBEN PD De-Bounce Enable Control Register 0xD4 read-write n 0x0 0x0 PD_DINOFF PD_DINOFF PD Digital Input Path Disable Control 0xC4 read-write n 0x0 0x0 PD_DOUT PD_DOUT PD Data Output Value 0xC8 read-write n 0x0 0x0 PD_INTEN PD_INTEN PD Interrupt Enable Control Register 0xDC read-write n 0x0 0x0 PD_INTSRC PD_INTSRC PD Interrupt Source Flag 0xE0 read-write n 0x0 0x0 PD_INTTYPE PD_INTTYPE PD Interrupt Trigger Type Control 0xD8 read-write n 0x0 0x0 PD_MODE PD_MODE PD I/O Mode Control 0xC0 read-write n 0x0 0x0 PD_PIN PD_PIN PD Pin Value 0xD0 read-write n 0x0 0x0 PD_PUSEL PD_PUSEL PD Pull-up and Pull-down Selection Register 0xF0 read-write n 0x0 0x0 PD_SLEWCTL PD_SLEWCTL PD High Slew Rate Control Register 0xE8 read-write n 0x0 0x0 PD_SMTEN PD_SMTEN PD Input Schmitt Trigger Enable Register 0xE4 read-write n 0x0 0x0 PE0_PDIO PE0_PDIO GPIO PE.n Pin Data Input/Output Register 0x900 read-write n 0x0 0x0 PE10_PDIO PE10_PDIO GPIO PE.n Pin Data Input/Output Register 0x928 read-write n 0x0 0x0 PE11_PDIO PE11_PDIO GPIO PE.n Pin Data Input/Output Register 0x92C read-write n 0x0 0x0 PE12_PDIO PE12_PDIO GPIO PE.n Pin Data Input/Output Register 0x930 read-write n 0x0 0x0 PE13_PDIO PE13_PDIO GPIO PE.n Pin Data Input/Output Register 0x934 read-write n 0x0 0x0 PE14_PDIO PE14_PDIO GPIO PE.n Pin Data Input/Output Register 0x938 read-write n 0x0 0x0 PE15_PDIO PE15_PDIO GPIO PE.n Pin Data Input/Output Register 0x93C read-write n 0x0 0x0 PE1_PDIO PE1_PDIO GPIO PE.n Pin Data Input/Output Register 0x904 read-write n 0x0 0x0 PE2_PDIO PE2_PDIO GPIO PE.n Pin Data Input/Output Register 0x908 read-write n 0x0 0x0 PE3_PDIO PE3_PDIO GPIO PE.n Pin Data Input/Output Register 0x90C read-write n 0x0 0x0 PE4_PDIO PE4_PDIO GPIO PE.n Pin Data Input/Output Register 0x910 read-write n 0x0 0x0 PE5_PDIO PE5_PDIO GPIO PE.n Pin Data Input/Output Register 0x914 read-write n 0x0 0x0 PE6_PDIO PE6_PDIO GPIO PE.n Pin Data Input/Output Register 0x918 read-write n 0x0 0x0 PE7_PDIO PE7_PDIO GPIO PE.n Pin Data Input/Output Register 0x91C read-write n 0x0 0x0 PE8_PDIO PE8_PDIO GPIO PE.n Pin Data Input/Output Register 0x920 read-write n 0x0 0x0 PE9_PDIO PE9_PDIO GPIO PE.n Pin Data Input/Output Register 0x924 read-write n 0x0 0x0 PE_DATMSK PE_DATMSK PE Data Output Write Mask 0x10C read-write n 0x0 0x0 PE_DBCTL PE_DBCTL PE Interrupt De-bounce Control Register 0x134 read-write n 0x0 0x0 PE_DBEN PE_DBEN PE De-Bounce Enable Control Register 0x114 read-write n 0x0 0x0 PE_DINOFF PE_DINOFF PE Digital Input Path Disable Control 0x104 read-write n 0x0 0x0 PE_DOUT PE_DOUT PE Data Output Value 0x108 read-write n 0x0 0x0 PE_INTEN PE_INTEN PE Interrupt Enable Control Register 0x11C read-write n 0x0 0x0 PE_INTSRC PE_INTSRC PE Interrupt Source Flag 0x120 read-write n 0x0 0x0 PE_INTTYPE PE_INTTYPE PE Interrupt Trigger Type Control 0x118 read-write n 0x0 0x0 PE_MODE PE_MODE PE I/O Mode Control 0x100 read-write n 0x0 0x0 PE_PIN PE_PIN PE Pin Value 0x110 read-write n 0x0 0x0 PE_PUSEL PE_PUSEL PE Pull-up and Pull-down Selection Register 0x130 read-write n 0x0 0x0 PE_SLEWCTL PE_SLEWCTL PE High Slew Rate Control Register 0x128 read-write n 0x0 0x0 PE_SMTEN PE_SMTEN PE Input Schmitt Trigger Enable Register 0x124 read-write n 0x0 0x0 PF0_PDIO PF0_PDIO GPIO PF.n Pin Data Input/Output Register 0x940 read-write n 0x0 0x0 PF10_PDIO PF10_PDIO GPIO PF.n Pin Data Input/Output Register 0x968 read-write n 0x0 0x0 PF11_PDIO PF11_PDIO GPIO PF.n Pin Data Input/Output Register 0x96C read-write n 0x0 0x0 PF12_PDIO PF12_PDIO GPIO PF.n Pin Data Input/Output Register 0x970 read-write n 0x0 0x0 PF13_PDIO PF13_PDIO GPIO PF.n Pin Data Input/Output Register 0x974 read-write n 0x0 0x0 PF14_PDIO PF14_PDIO GPIO PF.n Pin Data Input/Output Register 0x978 read-write n 0x0 0x0 PF15_PDIO PF15_PDIO GPIO PF.n Pin Data Input/Output Register 0x97C read-write n 0x0 0x0 PF1_PDIO PF1_PDIO GPIO PF.n Pin Data Input/Output Register 0x944 read-write n 0x0 0x0 PF2_PDIO PF2_PDIO GPIO PF.n Pin Data Input/Output Register 0x948 read-write n 0x0 0x0 PF3_PDIO PF3_PDIO GPIO PF.n Pin Data Input/Output Register 0x94C read-write n 0x0 0x0 PF4_PDIO PF4_PDIO GPIO PF.n Pin Data Input/Output Register 0x950 read-write n 0x0 0x0 PF5_PDIO PF5_PDIO GPIO PF.n Pin Data Input/Output Register 0x954 read-write n 0x0 0x0 PF6_PDIO PF6_PDIO GPIO PF.n Pin Data Input/Output Register 0x958 read-write n 0x0 0x0 PF7_PDIO PF7_PDIO GPIO PF.n Pin Data Input/Output Register 0x95C read-write n 0x0 0x0 PF8_PDIO PF8_PDIO GPIO PF.n Pin Data Input/Output Register 0x960 read-write n 0x0 0x0 PF9_PDIO PF9_PDIO GPIO PF.n Pin Data Input/Output Register 0x964 read-write n 0x0 0x0 PF_DATMSK PF_DATMSK PF Data Output Write Mask 0x14C read-write n 0x0 0x0 PF_DBCTL PF_DBCTL PF Interrupt De-bounce Control Register 0x174 read-write n 0x0 0x0 PF_DBEN PF_DBEN PF De-Bounce Enable Control Register 0x154 read-write n 0x0 0x0 PF_DINOFF PF_DINOFF PF Digital Input Path Disable Control 0x144 read-write n 0x0 0x0 PF_DOUT PF_DOUT PF Data Output Value 0x148 read-write n 0x0 0x0 PF_INTEN PF_INTEN PF Interrupt Enable Control Register 0x15C read-write n 0x0 0x0 PF_INTSRC PF_INTSRC PF Interrupt Source Flag 0x160 read-write n 0x0 0x0 PF_INTTYPE PF_INTTYPE PF Interrupt Trigger Type Control 0x158 read-write n 0x0 0x0 PF_MODE PF_MODE PF I/O Mode Control 0x140 read-write n 0x0 0x0 PF_PIN PF_PIN PF Pin Value 0x150 read-write n 0x0 0x0 PF_PUSEL PF_PUSEL PF Pull-up and Pull-down Selection Register 0x170 read-write n 0x0 0x0 PF_SLEWCTL PF_SLEWCTL PF High Slew Rate Control Register 0x168 read-write n 0x0 0x0 PF_SMTEN PF_SMTEN PF Input Schmitt Trigger Enable Register 0x164 read-write n 0x0 0x0 PG0_PDIO PG0_PDIO GPIO PG.n Pin Data Input/Output Register 0x980 read-write n 0x0 0x0 PG10_PDIO PG10_PDIO GPIO PG.n Pin Data Input/Output Register 0x9A8 read-write n 0x0 0x0 PG11_PDIO PG11_PDIO GPIO PG.n Pin Data Input/Output Register 0x9AC read-write n 0x0 0x0 PG12_PDIO PG12_PDIO GPIO PG.n Pin Data Input/Output Register 0x9B0 read-write n 0x0 0x0 PG13_PDIO PG13_PDIO GPIO PG.n Pin Data Input/Output Register 0x9B4 read-write n 0x0 0x0 PG14_PDIO PG14_PDIO GPIO PG.n Pin Data Input/Output Register 0x9B8 read-write n 0x0 0x0 PG15_PDIO PG15_PDIO GPIO PG.n Pin Data Input/Output Register 0x9BC read-write n 0x0 0x0 PG1_PDIO PG1_PDIO GPIO PG.n Pin Data Input/Output Register 0x984 read-write n 0x0 0x0 PG2_PDIO PG2_PDIO GPIO PG.n Pin Data Input/Output Register 0x988 read-write n 0x0 0x0 PG3_PDIO PG3_PDIO GPIO PG.n Pin Data Input/Output Register 0x98C read-write n 0x0 0x0 PG4_PDIO PG4_PDIO GPIO PG.n Pin Data Input/Output Register 0x990 read-write n 0x0 0x0 PG5_PDIO PG5_PDIO GPIO PG.n Pin Data Input/Output Register 0x994 read-write n 0x0 0x0 PG6_PDIO PG6_PDIO GPIO PG.n Pin Data Input/Output Register 0x998 read-write n 0x0 0x0 PG7_PDIO PG7_PDIO GPIO PG.n Pin Data Input/Output Register 0x99C read-write n 0x0 0x0 PG8_PDIO PG8_PDIO GPIO PG.n Pin Data Input/Output Register 0x9A0 read-write n 0x0 0x0 PG9_PDIO PG9_PDIO GPIO PG.n Pin Data Input/Output Register 0x9A4 read-write n 0x0 0x0 PG_DATMSK PG_DATMSK PG Data Output Write Mask 0x18C read-write n 0x0 0x0 PG_DBCTL PG_DBCTL PG Interrupt De-bounce Control Register 0x1B4 read-write n 0x0 0x0 PG_DBEN PG_DBEN PG De-Bounce Enable Control Register 0x194 read-write n 0x0 0x0 PG_DINOFF PG_DINOFF PG Digital Input Path Disable Control 0x184 read-write n 0x0 0x0 PG_DOUT PG_DOUT PG Data Output Value 0x188 read-write n 0x0 0x0 PG_INTEN PG_INTEN PG Interrupt Enable Control Register 0x19C read-write n 0x0 0x0 PG_INTSRC PG_INTSRC PG Interrupt Source Flag 0x1A0 read-write n 0x0 0x0 PG_INTTYPE PG_INTTYPE PG Interrupt Trigger Type Control 0x198 read-write n 0x0 0x0 PG_MODE PG_MODE PG I/O Mode Control 0x180 read-write n 0x0 0x0 PG_PIN PG_PIN PG Pin Value 0x190 read-write n 0x0 0x0 PG_PUSEL PG_PUSEL PG Pull-up and Pull-down Selection Register 0x1B0 read-write n 0x0 0x0 PG_SLEWCTL PG_SLEWCTL PG High Slew Rate Control Register 0x1A8 read-write n 0x0 0x0 PG_SMTEN PG_SMTEN PG Input Schmitt Trigger Enable Register 0x1A4 read-write n 0x0 0x0 PH0_PDIO PH0_PDIO GPIO PH.n Pin Data Input/Output Register 0x9C0 read-write n 0x0 0x0 PH10_PDIO PH10_PDIO GPIO PH.n Pin Data Input/Output Register 0x9E8 read-write n 0x0 0x0 PH11_PDIO PH11_PDIO GPIO PH.n Pin Data Input/Output Register 0x9EC read-write n 0x0 0x0 PH12_PDIO PH12_PDIO GPIO PH.n Pin Data Input/Output Register 0x9F0 read-write n 0x0 0x0 PH13_PDIO PH13_PDIO GPIO PH.n Pin Data Input/Output Register 0x9F4 read-write n 0x0 0x0 PH14_PDIO PH14_PDIO GPIO PH.n Pin Data Input/Output Register 0x9F8 read-write n 0x0 0x0 PH15_PDIO PH15_PDIO GPIO PH.n Pin Data Input/Output Register 0x9FC read-write n 0x0 0x0 PH1_PDIO PH1_PDIO GPIO PH.n Pin Data Input/Output Register 0x9C4 read-write n 0x0 0x0 PH2_PDIO PH2_PDIO GPIO PH.n Pin Data Input/Output Register 0x9C8 read-write n 0x0 0x0 PH3_PDIO PH3_PDIO GPIO PH.n Pin Data Input/Output Register 0x9CC read-write n 0x0 0x0 PH4_PDIO PH4_PDIO GPIO PH.n Pin Data Input/Output Register 0x9D0 read-write n 0x0 0x0 PH5_PDIO PH5_PDIO GPIO PH.n Pin Data Input/Output Register 0x9D4 read-write n 0x0 0x0 PH6_PDIO PH6_PDIO GPIO PH.n Pin Data Input/Output Register 0x9D8 read-write n 0x0 0x0 PH7_PDIO PH7_PDIO GPIO PH.n Pin Data Input/Output Register 0x9DC read-write n 0x0 0x0 PH8_PDIO PH8_PDIO GPIO PH.n Pin Data Input/Output Register 0x9E0 read-write n 0x0 0x0 PH9_PDIO PH9_PDIO GPIO PH.n Pin Data Input/Output Register 0x9E4 read-write n 0x0 0x0 PH_DATMSK PH_DATMSK PH Data Output Write Mask 0x1CC read-write n 0x0 0x0 PH_DBCTL PH_DBCTL PH Interrupt De-bounce Control Register 0x1F4 read-write n 0x0 0x0 PH_DBEN PH_DBEN PH De-Bounce Enable Control Register 0x1D4 read-write n 0x0 0x0 PH_DINOFF PH_DINOFF PH Digital Input Path Disable Control 0x1C4 read-write n 0x0 0x0 PH_DOUT PH_DOUT PH Data Output Value 0x1C8 read-write n 0x0 0x0 PH_INTEN PH_INTEN PH Interrupt Enable Control Register 0x1DC read-write n 0x0 0x0 PH_INTSRC PH_INTSRC PH Interrupt Source Flag 0x1E0 read-write n 0x0 0x0 PH_INTTYPE PH_INTTYPE PH Interrupt Trigger Type Control 0x1D8 read-write n 0x0 0x0 PH_MODE PH_MODE PH I/O Mode Control 0x1C0 read-write n 0x0 0x0 PH_PIN PH_PIN PH Pin Value 0x1D0 read-write n 0x0 0x0 PH_PUSEL PH_PUSEL PH Pull-up and Pull-down Selection Register 0x1F0 read-write n 0x0 0x0 PH_SLEWCTL PH_SLEWCTL PH High Slew Rate Control Register 0x1E8 read-write n 0x0 0x0 PH_SMTEN PH_SMTEN PH Input Schmitt Trigger Enable Register 0x1E4 read-write n 0x0 0x0 I2C0 I2C Register Map I2C 0x0 0x0 0x30 registers n 0x3C 0x30 registers n I2C_ADDR0 I2C_ADDR0 I2C Slave Address Register0 0x4 read-write n 0x0 0x0 ADDR I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.\nNote: When software set 10'h000, the address can not be used. 1 10 read-write GC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 I2C_ADDR1 I2C_ADDR1 I2C Slave Address Register1 0x18 read-write n 0x0 0x0 I2C_ADDR2 I2C_ADDR2 I2C Slave Address Register2 0x1C read-write n 0x0 0x0 I2C_ADDR3 I2C_ADDR3 I2C Slave Address Register3 0x20 read-write n 0x0 0x0 I2C_ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register0 0x24 read-write n 0x0 0x0 ADDRMSK I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\nNote: The wake-up function can not use address mask. 1 10 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 I2C_ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register1 0x28 read-write n 0x0 0x0 I2C_ADDRMSK2 I2C_ADDRMSK2 I2C Slave Address Mask Register2 0x2C read-write n 0x0 0x0 I2C_ADDRMSK3 I2C_ADDRMSK3 I2C Slave Address Mask Register3 0x30 read-write n 0x0 0x0 I2C_BUSCTL I2C_BUSCTL I2C Bus Management Control Register 0x50 read-write n 0x0 0x0 ACKM9SI Acknowledge Manual Enable Extra SI Interrupt 11 1 read-write 0 There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1 #0 1 There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1 #1 ACKMEN Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. 0 1 read-write 0 Slave byte control Disabled #0 1 Slave byte control Enabled. The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse #1 ALERTEN Bus Management Alert Enable Bit 4 1 read-write 0 Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin not supported #0 1 Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin supported #1 BCDIEN Packet Error Checking Byte Count Done Interrupt Enable Bit 12 1 read-write 0 Byte count done interrupt Disabled #0 1 Byte count done interrupt Enabled #1 BMDEN Bus Management Device Default Address Enable Bit 2 1 read-write 0 Device default address Disable. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed #0 1 Device default address Enabled. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed #1 BMHEN Bus Management Host Enable Bit 3 1 read-write 0 Host function Disabled #0 1 Host function Enabled #1 BUSEN BUS Enable Bit\nNote: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. 7 1 read-write 0 The system management function Disabled #0 1 The system management function Enabled #1 PECCLR PEC Clear at Repeat START\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of Repeat START can clear the PEC calculation. 10 1 read-write 0 PEC calculation is cleared by 'Repeat START' function Disabled #0 1 PEC calculation is cleared by 'Repeat START' function Enabled #1 PECDIEN Packet Error Checking Byte Transfer Done Interrupt Enable Bit 13 1 read-write 0 PEC transfer done interrupt Disabled #0 1 PEC transfer done interrupt Enabled #1 PECEN Packet Error Checking Calculation Enable Bit\nNote: When I2C enter powerdown mode, the bit should be enabled after wake-up if needed PEC calculation. 1 1 read-write 0 Packet Error Checking Calculation Disabled #0 1 Packet Error Checking Calculation Enabled #1 PECTXEN Packet Error Checking Byte Transmission/Reception 8 1 read-write 0 No PEC transfer #0 1 PEC transmission is requested #1 SCTLOEN Suspend or Control Pin Output Enable Bit 6 1 read-write 0 The SUSCON pin in input #0 1 The output enable is active on the SUSCON pin #1 SCTLOSTS Suspend/Control Data Output Status 5 1 read-write 0 The output of SUSCON pin is low #0 1 The output of SUSCON pin is high #1 TIDLE Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicate the current bus state. 9 1 read-write 0 BUSTOUT is used to calculate the clock low period in bus active #0 1 BUSTOUT is used to calculate the IDLE period in bus Idle #1 I2C_BUSSTS I2C_BUSSTS I2C Bus Management Status Register 0x58 read-write n 0x0 0x0 ALERT SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit. 3 1 read-write 0 SMBALERT pin state is low.\nNo SMBALERT event #0 1 SMBALERT pin state is high.\nThere is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1 #1 BCDONE Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit. 1 1 read-write 0 Byte count transmission/ receive is not finished when the PECEN is set #0 1 Byte count transmission/ receive is finished when the PECEN is set #1 BUSTO Bus Time-out Status In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. Note: Software can write 1 to clear this bit. 5 1 read-write 0 There is no any time-out or external clock time-out #0 1 A time-out or external clock time-out occurred #1 BUSY Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 0 1 read-write 0 Bus is IDLE (both SCLK and SDA High) #0 1 Bus is busy #1 CLKTO Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit. 6 1 read-write 0 Cumulative clock low is no any time-out #0 1 Cumulative clock low time-out occurred #1 PECDONE PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit. 7 1 read-write 0 PEC transmission/ receive is not finished when the PECEN is set #0 1 PEC transmission/ receive is finished when the PECEN is set #1 PECERR PEC Error in Reception \nNote: Software can write 1 to clear this bit. 2 1 read-write 0 PEC value equal the received PEC data packet #0 1 PEC value doesn't match the receive PEC data packet #1 SCTLDIN Bus Suspend or Control Signal Input Status 4 1 read-write 0 The input status of SUSCON pin is 0 #0 1 The input status of SUSCON pin is 1 #1 I2C_BUSTCTL I2C_BUSTCTL I2C Bus Management Timer Control Register 0x54 read-write n 0x0 0x0 BUSTOEN Bus Time Out Enable Bit 0 1 read-write 0 Bus clock low time-out detection Disabled #0 1 Bus clock low time-out detection Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1) #1 BUSTOIEN Time-out Interrupt Enable Bit 2 1 read-write 0 SCLK low time-out interrupt Disabled.\nBus IDLE time-out interrupt Disabled #0 1 SCLK low time-out interrupt Enabled.\nBus IDLE time-out interrupt Enabled #1 CLKTOEN Cumulative Clock Low Time Out Enable Bit\nFor Master, it calculates the period from START to ACK\nFor Slave, it calculates the period from START to STOP 1 1 read-write 0 Cumulative clock low time-out detection Disabled #0 1 Cumulative clock low time-out detection Enabled #1 CLKTOIEN Extended Clock Time Out Interrupt Enable Bit 3 1 read-write 0 Clock time out interrupt Disabled #0 1 Clock time out interrupt Enabled #1 TORSTEN Time Out Reset Enable Bit 4 1 read-write 0 I2C state machine reset Disabled #0 1 I2C state machine reset Enabled. (The clock and data bus will be released to high) #1 I2C_BUSTOUT I2C_BUSTOUT I2C Bus Management Timer Register 0x64 -1 read-write n 0x0 0x0 BUSTO Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set. 0 8 read-write I2C_CLKDIV I2C_CLKDIV I2C Clock Divided Register 0x10 read-write n 0x0 0x0 DIVIDER I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4. 0 10 read-write I2C_CLKTOUT I2C_CLKTOUT I2C Bus Management Clock Low Timer Register 0x68 -1 read-write n 0x0 0x0 CLKTO Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set. 0 8 read-write I2C_CTL0 I2C_CTL0 I2C Control Register 0 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control 2 1 read-write I2CEN I2C Controller Enable Bit 6 1 read-write 0 I2C controller Disabled #0 1 I2C controller Enabled #1 INTEN Enable Interrupt 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.\nFor ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. 3 1 read-write STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically. 4 1 read-write I2C_CTL1 I2C_CTL1 I2C Control Register 1 0x44 read-write n 0x0 0x0 ADDR10EN Address 10-bit Function Enable Bit 9 1 read-write 0 Address match 10-bit function Disabled #0 1 Address match 10-bit function Enabled #1 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the I2C request to PDMA #1 PDMASTR PDMA Stretch Bit 8 1 read-write 0 I2C send STOP automatically after PDMA transfer done. (only master TX) #0 1 I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX) #1 RXPDMAEN PDMA Receive Channel Available 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN PDMA Transmit Channel Available 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 I2C_DAT I2C_DAT I2C Data Register 0x8 read-write n 0x0 0x0 DAT I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port. 0 8 read-write I2C_PKTCRC I2C_PKTCRC I2C Packet Error Checking Byte Value Register 0x60 read-only n 0x0 0x0 PECCRC Packet Error Checking Byte Value 0 8 read-only I2C_PKTSIZE I2C_PKTSIZE I2C Packet Error Checking Byte Number Register 0x5C read-write n 0x0 0x0 PLDSIZE Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address, command code, and data frame. 0 9 read-write I2C_STATUS0 I2C_STATUS0 I2C Status Register 0 0xC -1 read-only n 0x0 0x0 STATUS I2C Status 0 8 read-only I2C_STATUS1 I2C_STATUS1 I2C Status Register 1 0x48 read-write n 0x0 0x0 ADMAT0 I2C Address 0 Match Status\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 0 1 read-write ADMAT1 I2C Address 1 Match Status\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 1 1 read-write ADMAT2 I2C Address 2 Match Status\nWhen address 2 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 2 1 read-write ADMAT3 I2C Address 3 Match Status\nWhen address 3 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 3 1 read-write ONBUSY On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected. 8 1 read-only 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 I2C_TMCTL I2C_TMCTL I2C Timing Configure Control Register 0x4C read-write n 0x0 0x0 HTCTL Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. 16 9 read-write STCTL Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs. 0 9 read-write I2C_TOCTL I2C_TOCTL I2C Time-out Control Register 0x14 read-write n 0x0 0x0 TOCDIV4 Time-out Counter Input Clock Divided by 4\nWhen enabled, the time-out period is extended 4 times. 1 1 read-write 0 Time-out period is extend 4 times Disabled #0 1 Time-out period is extend 4 times Enabled #1 TOCEN Time-out Counter Enable Bit\nWhen enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. 2 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOIF Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit. 0 1 read-write I2C_WKCTL I2C_WKCTL I2C Wake-up Control Register 0x3C read-write n 0x0 0x0 NHDBUSEN I2C No Hold BUS Enable Bit Note: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. 7 1 read-write 0 I2C hold bus after wake-up #0 1 I2C don't hold bus after wake-up #1 WKEN I2C Wake-up Enable Bit 0 1 read-write 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 I2C_WKSTS I2C_WKSTS I2C Wake-up Status Register 0x40 read-write n 0x0 0x0 WKAKDONE Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit. 1 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WKIF I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write WRSTSWK Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit. 2 1 read-write 0 Write command be record on the address match wakeup frame #0 1 Read command be record on the address match wakeup frame #1 I2C1 I2C Register Map I2C 0x0 0x0 0x30 registers n 0x3C 0x30 registers n I2C_ADDR0 I2C_ADDR0 I2C Slave Address Register0 0x4 read-write n 0x0 0x0 ADDR I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.\nNote: When software set 10'h000, the address can not be used. 1 10 read-write GC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 I2C_ADDR1 I2C_ADDR1 I2C Slave Address Register1 0x18 read-write n 0x0 0x0 I2C_ADDR2 I2C_ADDR2 I2C Slave Address Register2 0x1C read-write n 0x0 0x0 I2C_ADDR3 I2C_ADDR3 I2C Slave Address Register3 0x20 read-write n 0x0 0x0 I2C_ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register0 0x24 read-write n 0x0 0x0 ADDRMSK I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\nNote: The wake-up function can not use address mask. 1 10 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 I2C_ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register1 0x28 read-write n 0x0 0x0 I2C_ADDRMSK2 I2C_ADDRMSK2 I2C Slave Address Mask Register2 0x2C read-write n 0x0 0x0 I2C_ADDRMSK3 I2C_ADDRMSK3 I2C Slave Address Mask Register3 0x30 read-write n 0x0 0x0 I2C_BUSCTL I2C_BUSCTL I2C Bus Management Control Register 0x50 read-write n 0x0 0x0 ACKM9SI Acknowledge Manual Enable Extra SI Interrupt 11 1 read-write 0 There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1 #0 1 There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1 #1 ACKMEN Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. 0 1 read-write 0 Slave byte control Disabled #0 1 Slave byte control Enabled. The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse #1 ALERTEN Bus Management Alert Enable Bit 4 1 read-write 0 Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin not supported #0 1 Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin supported #1 BCDIEN Packet Error Checking Byte Count Done Interrupt Enable Bit 12 1 read-write 0 Byte count done interrupt Disabled #0 1 Byte count done interrupt Enabled #1 BMDEN Bus Management Device Default Address Enable Bit 2 1 read-write 0 Device default address Disable. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed #0 1 Device default address Enabled. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed #1 BMHEN Bus Management Host Enable Bit 3 1 read-write 0 Host function Disabled #0 1 Host function Enabled #1 BUSEN BUS Enable Bit\nNote: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. 7 1 read-write 0 The system management function Disabled #0 1 The system management function Enabled #1 PECCLR PEC Clear at Repeat START\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of Repeat START can clear the PEC calculation. 10 1 read-write 0 PEC calculation is cleared by 'Repeat START' function Disabled #0 1 PEC calculation is cleared by 'Repeat START' function Enabled #1 PECDIEN Packet Error Checking Byte Transfer Done Interrupt Enable Bit 13 1 read-write 0 PEC transfer done interrupt Disabled #0 1 PEC transfer done interrupt Enabled #1 PECEN Packet Error Checking Calculation Enable Bit\nNote: When I2C enter powerdown mode, the bit should be enabled after wake-up if needed PEC calculation. 1 1 read-write 0 Packet Error Checking Calculation Disabled #0 1 Packet Error Checking Calculation Enabled #1 PECTXEN Packet Error Checking Byte Transmission/Reception 8 1 read-write 0 No PEC transfer #0 1 PEC transmission is requested #1 SCTLOEN Suspend or Control Pin Output Enable Bit 6 1 read-write 0 The SUSCON pin in input #0 1 The output enable is active on the SUSCON pin #1 SCTLOSTS Suspend/Control Data Output Status 5 1 read-write 0 The output of SUSCON pin is low #0 1 The output of SUSCON pin is high #1 TIDLE Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicate the current bus state. 9 1 read-write 0 BUSTOUT is used to calculate the clock low period in bus active #0 1 BUSTOUT is used to calculate the IDLE period in bus Idle #1 I2C_BUSSTS I2C_BUSSTS I2C Bus Management Status Register 0x58 read-write n 0x0 0x0 ALERT SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit. 3 1 read-write 0 SMBALERT pin state is low.\nNo SMBALERT event #0 1 SMBALERT pin state is high.\nThere is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1 #1 BCDONE Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit. 1 1 read-write 0 Byte count transmission/ receive is not finished when the PECEN is set #0 1 Byte count transmission/ receive is finished when the PECEN is set #1 BUSTO Bus Time-out Status In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. Note: Software can write 1 to clear this bit. 5 1 read-write 0 There is no any time-out or external clock time-out #0 1 A time-out or external clock time-out occurred #1 BUSY Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 0 1 read-write 0 Bus is IDLE (both SCLK and SDA High) #0 1 Bus is busy #1 CLKTO Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit. 6 1 read-write 0 Cumulative clock low is no any time-out #0 1 Cumulative clock low time-out occurred #1 PECDONE PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit. 7 1 read-write 0 PEC transmission/ receive is not finished when the PECEN is set #0 1 PEC transmission/ receive is finished when the PECEN is set #1 PECERR PEC Error in Reception \nNote: Software can write 1 to clear this bit. 2 1 read-write 0 PEC value equal the received PEC data packet #0 1 PEC value doesn't match the receive PEC data packet #1 SCTLDIN Bus Suspend or Control Signal Input Status 4 1 read-write 0 The input status of SUSCON pin is 0 #0 1 The input status of SUSCON pin is 1 #1 I2C_BUSTCTL I2C_BUSTCTL I2C Bus Management Timer Control Register 0x54 read-write n 0x0 0x0 BUSTOEN Bus Time Out Enable Bit 0 1 read-write 0 Bus clock low time-out detection Disabled #0 1 Bus clock low time-out detection Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1) #1 BUSTOIEN Time-out Interrupt Enable Bit 2 1 read-write 0 SCLK low time-out interrupt Disabled.\nBus IDLE time-out interrupt Disabled #0 1 SCLK low time-out interrupt Enabled.\nBus IDLE time-out interrupt Enabled #1 CLKTOEN Cumulative Clock Low Time Out Enable Bit\nFor Master, it calculates the period from START to ACK\nFor Slave, it calculates the period from START to STOP 1 1 read-write 0 Cumulative clock low time-out detection Disabled #0 1 Cumulative clock low time-out detection Enabled #1 CLKTOIEN Extended Clock Time Out Interrupt Enable Bit 3 1 read-write 0 Clock time out interrupt Disabled #0 1 Clock time out interrupt Enabled #1 TORSTEN Time Out Reset Enable Bit 4 1 read-write 0 I2C state machine reset Disabled #0 1 I2C state machine reset Enabled. (The clock and data bus will be released to high) #1 I2C_BUSTOUT I2C_BUSTOUT I2C Bus Management Timer Register 0x64 -1 read-write n 0x0 0x0 BUSTO Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set. 0 8 read-write I2C_CLKDIV I2C_CLKDIV I2C Clock Divided Register 0x10 read-write n 0x0 0x0 DIVIDER I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4. 0 10 read-write I2C_CLKTOUT I2C_CLKTOUT I2C Bus Management Clock Low Timer Register 0x68 -1 read-write n 0x0 0x0 CLKTO Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set. 0 8 read-write I2C_CTL0 I2C_CTL0 I2C Control Register 0 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control 2 1 read-write I2CEN I2C Controller Enable Bit 6 1 read-write 0 I2C controller Disabled #0 1 I2C controller Enabled #1 INTEN Enable Interrupt 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.\nFor ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. 3 1 read-write STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically. 4 1 read-write I2C_CTL1 I2C_CTL1 I2C Control Register 1 0x44 read-write n 0x0 0x0 ADDR10EN Address 10-bit Function Enable Bit 9 1 read-write 0 Address match 10-bit function Disabled #0 1 Address match 10-bit function Enabled #1 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the I2C request to PDMA #1 PDMASTR PDMA Stretch Bit 8 1 read-write 0 I2C send STOP automatically after PDMA transfer done. (only master TX) #0 1 I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX) #1 RXPDMAEN PDMA Receive Channel Available 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN PDMA Transmit Channel Available 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 I2C_DAT I2C_DAT I2C Data Register 0x8 read-write n 0x0 0x0 DAT I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port. 0 8 read-write I2C_PKTCRC I2C_PKTCRC I2C Packet Error Checking Byte Value Register 0x60 read-only n 0x0 0x0 PECCRC Packet Error Checking Byte Value 0 8 read-only I2C_PKTSIZE I2C_PKTSIZE I2C Packet Error Checking Byte Number Register 0x5C read-write n 0x0 0x0 PLDSIZE Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address, command code, and data frame. 0 9 read-write I2C_STATUS0 I2C_STATUS0 I2C Status Register 0 0xC -1 read-only n 0x0 0x0 STATUS I2C Status 0 8 read-only I2C_STATUS1 I2C_STATUS1 I2C Status Register 1 0x48 read-write n 0x0 0x0 ADMAT0 I2C Address 0 Match Status\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 0 1 read-write ADMAT1 I2C Address 1 Match Status\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 1 1 read-write ADMAT2 I2C Address 2 Match Status\nWhen address 2 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 2 1 read-write ADMAT3 I2C Address 3 Match Status\nWhen address 3 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 3 1 read-write ONBUSY On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected. 8 1 read-only 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 I2C_TMCTL I2C_TMCTL I2C Timing Configure Control Register 0x4C read-write n 0x0 0x0 HTCTL Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. 16 9 read-write STCTL Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs. 0 9 read-write I2C_TOCTL I2C_TOCTL I2C Time-out Control Register 0x14 read-write n 0x0 0x0 TOCDIV4 Time-out Counter Input Clock Divided by 4\nWhen enabled, the time-out period is extended 4 times. 1 1 read-write 0 Time-out period is extend 4 times Disabled #0 1 Time-out period is extend 4 times Enabled #1 TOCEN Time-out Counter Enable Bit\nWhen enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. 2 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOIF Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit. 0 1 read-write I2C_WKCTL I2C_WKCTL I2C Wake-up Control Register 0x3C read-write n 0x0 0x0 NHDBUSEN I2C No Hold BUS Enable Bit Note: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. 7 1 read-write 0 I2C hold bus after wake-up #0 1 I2C don't hold bus after wake-up #1 WKEN I2C Wake-up Enable Bit 0 1 read-write 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 I2C_WKSTS I2C_WKSTS I2C Wake-up Status Register 0x40 read-write n 0x0 0x0 WKAKDONE Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit. 1 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WKIF I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write WRSTSWK Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit. 2 1 read-write 0 Write command be record on the address match wakeup frame #0 1 Read command be record on the address match wakeup frame #1 I2C2 I2C Register Map I2C 0x0 0x0 0x30 registers n 0x3C 0x30 registers n I2C_ADDR0 I2C_ADDR0 I2C Slave Address Register0 0x4 read-write n 0x0 0x0 ADDR I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.\nNote: When software set 10'h000, the address can not be used. 1 10 read-write GC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 I2C_ADDR1 I2C_ADDR1 I2C Slave Address Register1 0x18 read-write n 0x0 0x0 I2C_ADDR2 I2C_ADDR2 I2C Slave Address Register2 0x1C read-write n 0x0 0x0 I2C_ADDR3 I2C_ADDR3 I2C Slave Address Register3 0x20 read-write n 0x0 0x0 I2C_ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register0 0x24 read-write n 0x0 0x0 ADDRMSK I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\nNote: The wake-up function can not use address mask. 1 10 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 I2C_ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register1 0x28 read-write n 0x0 0x0 I2C_ADDRMSK2 I2C_ADDRMSK2 I2C Slave Address Mask Register2 0x2C read-write n 0x0 0x0 I2C_ADDRMSK3 I2C_ADDRMSK3 I2C Slave Address Mask Register3 0x30 read-write n 0x0 0x0 I2C_BUSCTL I2C_BUSCTL I2C Bus Management Control Register 0x50 read-write n 0x0 0x0 ACKM9SI Acknowledge Manual Enable Extra SI Interrupt 11 1 read-write 0 There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1 #0 1 There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1 #1 ACKMEN Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. 0 1 read-write 0 Slave byte control Disabled #0 1 Slave byte control Enabled. The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse #1 ALERTEN Bus Management Alert Enable Bit 4 1 read-write 0 Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin not supported #0 1 Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin supported #1 BCDIEN Packet Error Checking Byte Count Done Interrupt Enable Bit 12 1 read-write 0 Byte count done interrupt Disabled #0 1 Byte count done interrupt Enabled #1 BMDEN Bus Management Device Default Address Enable Bit 2 1 read-write 0 Device default address Disable. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed #0 1 Device default address Enabled. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed #1 BMHEN Bus Management Host Enable Bit 3 1 read-write 0 Host function Disabled #0 1 Host function Enabled #1 BUSEN BUS Enable Bit\nNote: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. 7 1 read-write 0 The system management function Disabled #0 1 The system management function Enabled #1 PECCLR PEC Clear at Repeat START\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of Repeat START can clear the PEC calculation. 10 1 read-write 0 PEC calculation is cleared by 'Repeat START' function Disabled #0 1 PEC calculation is cleared by 'Repeat START' function Enabled #1 PECDIEN Packet Error Checking Byte Transfer Done Interrupt Enable Bit 13 1 read-write 0 PEC transfer done interrupt Disabled #0 1 PEC transfer done interrupt Enabled #1 PECEN Packet Error Checking Calculation Enable Bit\nNote: When I2C enter powerdown mode, the bit should be enabled after wake-up if needed PEC calculation. 1 1 read-write 0 Packet Error Checking Calculation Disabled #0 1 Packet Error Checking Calculation Enabled #1 PECTXEN Packet Error Checking Byte Transmission/Reception 8 1 read-write 0 No PEC transfer #0 1 PEC transmission is requested #1 SCTLOEN Suspend or Control Pin Output Enable Bit 6 1 read-write 0 The SUSCON pin in input #0 1 The output enable is active on the SUSCON pin #1 SCTLOSTS Suspend/Control Data Output Status 5 1 read-write 0 The output of SUSCON pin is low #0 1 The output of SUSCON pin is high #1 TIDLE Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicate the current bus state. 9 1 read-write 0 BUSTOUT is used to calculate the clock low period in bus active #0 1 BUSTOUT is used to calculate the IDLE period in bus Idle #1 I2C_BUSSTS I2C_BUSSTS I2C Bus Management Status Register 0x58 read-write n 0x0 0x0 ALERT SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit. 3 1 read-write 0 SMBALERT pin state is low.\nNo SMBALERT event #0 1 SMBALERT pin state is high.\nThere is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1 #1 BCDONE Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit. 1 1 read-write 0 Byte count transmission/ receive is not finished when the PECEN is set #0 1 Byte count transmission/ receive is finished when the PECEN is set #1 BUSTO Bus Time-out Status In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. Note: Software can write 1 to clear this bit. 5 1 read-write 0 There is no any time-out or external clock time-out #0 1 A time-out or external clock time-out occurred #1 BUSY Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 0 1 read-write 0 Bus is IDLE (both SCLK and SDA High) #0 1 Bus is busy #1 CLKTO Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit. 6 1 read-write 0 Cumulative clock low is no any time-out #0 1 Cumulative clock low time-out occurred #1 PECDONE PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit. 7 1 read-write 0 PEC transmission/ receive is not finished when the PECEN is set #0 1 PEC transmission/ receive is finished when the PECEN is set #1 PECERR PEC Error in Reception \nNote: Software can write 1 to clear this bit. 2 1 read-write 0 PEC value equal the received PEC data packet #0 1 PEC value doesn't match the receive PEC data packet #1 SCTLDIN Bus Suspend or Control Signal Input Status 4 1 read-write 0 The input status of SUSCON pin is 0 #0 1 The input status of SUSCON pin is 1 #1 I2C_BUSTCTL I2C_BUSTCTL I2C Bus Management Timer Control Register 0x54 read-write n 0x0 0x0 BUSTOEN Bus Time Out Enable Bit 0 1 read-write 0 Bus clock low time-out detection Disabled #0 1 Bus clock low time-out detection Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1) #1 BUSTOIEN Time-out Interrupt Enable Bit 2 1 read-write 0 SCLK low time-out interrupt Disabled.\nBus IDLE time-out interrupt Disabled #0 1 SCLK low time-out interrupt Enabled.\nBus IDLE time-out interrupt Enabled #1 CLKTOEN Cumulative Clock Low Time Out Enable Bit\nFor Master, it calculates the period from START to ACK\nFor Slave, it calculates the period from START to STOP 1 1 read-write 0 Cumulative clock low time-out detection Disabled #0 1 Cumulative clock low time-out detection Enabled #1 CLKTOIEN Extended Clock Time Out Interrupt Enable Bit 3 1 read-write 0 Clock time out interrupt Disabled #0 1 Clock time out interrupt Enabled #1 TORSTEN Time Out Reset Enable Bit 4 1 read-write 0 I2C state machine reset Disabled #0 1 I2C state machine reset Enabled. (The clock and data bus will be released to high) #1 I2C_BUSTOUT I2C_BUSTOUT I2C Bus Management Timer Register 0x64 -1 read-write n 0x0 0x0 BUSTO Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set. 0 8 read-write I2C_CLKDIV I2C_CLKDIV I2C Clock Divided Register 0x10 read-write n 0x0 0x0 DIVIDER I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4. 0 10 read-write I2C_CLKTOUT I2C_CLKTOUT I2C Bus Management Clock Low Timer Register 0x68 -1 read-write n 0x0 0x0 CLKTO Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set. 0 8 read-write I2C_CTL0 I2C_CTL0 I2C Control Register 0 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control 2 1 read-write I2CEN I2C Controller Enable Bit 6 1 read-write 0 I2C controller Disabled #0 1 I2C controller Enabled #1 INTEN Enable Interrupt 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.\nFor ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. 3 1 read-write STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically. 4 1 read-write I2C_CTL1 I2C_CTL1 I2C Control Register 1 0x44 read-write n 0x0 0x0 ADDR10EN Address 10-bit Function Enable Bit 9 1 read-write 0 Address match 10-bit function Disabled #0 1 Address match 10-bit function Enabled #1 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the I2C request to PDMA #1 PDMASTR PDMA Stretch Bit 8 1 read-write 0 I2C send STOP automatically after PDMA transfer done. (only master TX) #0 1 I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX) #1 RXPDMAEN PDMA Receive Channel Available 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN PDMA Transmit Channel Available 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 I2C_DAT I2C_DAT I2C Data Register 0x8 read-write n 0x0 0x0 DAT I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port. 0 8 read-write I2C_PKTCRC I2C_PKTCRC I2C Packet Error Checking Byte Value Register 0x60 read-only n 0x0 0x0 PECCRC Packet Error Checking Byte Value 0 8 read-only I2C_PKTSIZE I2C_PKTSIZE I2C Packet Error Checking Byte Number Register 0x5C read-write n 0x0 0x0 PLDSIZE Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address, command code, and data frame. 0 9 read-write I2C_STATUS0 I2C_STATUS0 I2C Status Register 0 0xC -1 read-only n 0x0 0x0 STATUS I2C Status 0 8 read-only I2C_STATUS1 I2C_STATUS1 I2C Status Register 1 0x48 read-write n 0x0 0x0 ADMAT0 I2C Address 0 Match Status\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 0 1 read-write ADMAT1 I2C Address 1 Match Status\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 1 1 read-write ADMAT2 I2C Address 2 Match Status\nWhen address 2 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 2 1 read-write ADMAT3 I2C Address 3 Match Status\nWhen address 3 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 3 1 read-write ONBUSY On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected. 8 1 read-only 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 I2C_TMCTL I2C_TMCTL I2C Timing Configure Control Register 0x4C read-write n 0x0 0x0 HTCTL Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. 16 9 read-write STCTL Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs. 0 9 read-write I2C_TOCTL I2C_TOCTL I2C Time-out Control Register 0x14 read-write n 0x0 0x0 TOCDIV4 Time-out Counter Input Clock Divided by 4\nWhen enabled, the time-out period is extended 4 times. 1 1 read-write 0 Time-out period is extend 4 times Disabled #0 1 Time-out period is extend 4 times Enabled #1 TOCEN Time-out Counter Enable Bit\nWhen enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. 2 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOIF Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit. 0 1 read-write I2C_WKCTL I2C_WKCTL I2C Wake-up Control Register 0x3C read-write n 0x0 0x0 NHDBUSEN I2C No Hold BUS Enable Bit Note: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. 7 1 read-write 0 I2C hold bus after wake-up #0 1 I2C don't hold bus after wake-up #1 WKEN I2C Wake-up Enable Bit 0 1 read-write 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 I2C_WKSTS I2C_WKSTS I2C Wake-up Status Register 0x40 read-write n 0x0 0x0 WKAKDONE Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit. 1 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WKIF I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write WRSTSWK Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit. 2 1 read-write 0 Write command be record on the address match wakeup frame #0 1 Read command be record on the address match wakeup frame #1 I2S I2S Register Map I2S 0x0 0x0 0x18 registers n 0x20 0x8 registers n CLKDIV I2S_CLKDIV I2S Clock Divider Register 0x4 read-write n 0x0 0x0 BCLKDIV Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. Software can program these bit fields to generate sampling rate clock frequency.\nNote: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK 8 10 read-write MCLKDIV Master Clock Divider\nIf chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLKDIV is set to 0, MCLK is the same as external clock input.\nNote: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK 0 7 read-write CTL0 I2S_CTL0 I2S Control Register 0 0x0 read-write n 0x0 0x0 CHWIDTH Channel Width This bit fields are used to define the length of audio channel. If CHWIDTH DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH. 28 2 read-write 0 The bit-width of each audio channel is 8-bit #00 1 The bit-width of each audio channel is 16-bit #01 2 The bit-width of each audio channel is 24-bit #10 3 The bit-width of each audio channel is 32-bit #11 DATWIDTH Data Width\nThis bit field is used to define the bit-width of data word in each audio channel 4 2 read-write 0 The bit-width of data word is 8-bit #00 1 The bit-width of data word is 16-bit #01 2 The bit-width of data word is 24-bit #10 3 The bit-width of data word is 32-bit #11 FORMAT Data Format Selection 24 3 read-write 0 I2S standard data format #000 1 I2S with MSB justified #001 2 I2S with LSB justified #010 3 Reserved #011 4 PCM standard data format #100 5 PCM with MSB justified #101 6 PCM with LSB justified #110 7 Reserved #111 I2SEN I2S Controller Enable Bit 0 1 read-write 0 I2S controller Disabled #0 1 I2S controller Enabled #1 MCLKEN Master Clock Enable Bit\nIf MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices. 15 1 read-write 0 Master clock Disabled #0 1 Master clock Enabled #1 MONO Monaural Data Control\nNote: When chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected. 6 1 read-write 0 Data is stereo format #0 1 Data is monaural format #1 MUTE Transmit Mute Enable Bit 3 1 read-write 0 Transmit data is shifted from buffer #0 1 Send zero on transmit channel #1 ORDER Stereo Data Order in FIFO\nIn 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte. In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries.\nMSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries. 7 1 read-write 0 Even channel data at high byte in 8-bit/16-bit data width #0 1 Even channel data at low byte in 8-bit/16-bit data width #1 PCMSYNC PCM Synchronization Pulse Length Selection\nThis bit field is used to select the high pulse length of frame synchronization signal in PCM protocol\nNote: This bit is only available in master mode 27 1 read-write 0 One BCLK period #0 1 One channel period #1 RXEN Receive Enable Bit 2 1 read-write 0 Data receiving Disabled #0 1 Data receiving Enabled #1 RXFBCLR Receive FIFO Buffer Clear\nNote1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.\nNote2: This bit is cleared by hardware automatically, read it return 0. 19 1 read-write 0 No Effect #0 1 Clear RX FIFO #1 RXLCH Receive Left Channel Enable Bit 23 1 read-write 0 Receive channel1 data in MONO mode #0 1 Receive channel0 data in MONO mode #1 RXPDMAEN Receive PDMA Enable Bit 21 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 SLAVE Slave Mode Enable Bit\nNote: I2S can operate as master or slave. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip. 8 1 read-write 0 Master mode #0 1 Slave mode #1 TDMCHNUM TDM Channel Number 30 2 read-write 0 2 channels in audio frame #00 1 4 channels in audio frame #01 2 6 channels in audio frame #10 3 8 channels in audio frame #11 TXEN Transmit Enable Bit 1 1 read-write 0 Data transmission Disabled #0 1 Data transmission Enabled #1 TXFBCLR Transmit FIFO Buffer Clear\nNote1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nNote2: This bit is clear by hardware automatically, read it return 0. 18 1 read-write 0 No Effect #0 1 Clear TX FIFO #1 TXPDMAEN Transmit PDMA Enable Bit 20 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 CTL1 I2S_CTL1 I2S Control Register 1 0x20 read-write n 0x0 0x0 CH0ZCEN Channel0 Zero-cross Detection Enable Bit\nNote2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all 0 then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.\nNote3: If CH0ZCIF flag is set to 1, the channel0 will be mute. 0 1 read-write 0 channel0 zero-cross detect Disabled #0 1 channel0 zero-cross detect Enabled #1 CH1ZCEN Channel1 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all 0 then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.\nNote3: If CH1ZCIF flag is set to 1, the channel1 will be mute. 1 1 read-write 0 channel1 zero-cross detect Disabled #0 1 channel1 zero-cross detect Enabled #1 CH2ZCEN Channel2 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all 0 then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.\nNote3: If CH2ZCIF flag is set to 1, the channel2 will be mute. 2 1 read-write 0 channel2 zero-cross detect Disabled #0 1 channel2 zero-cross detect Enabled #1 CH3ZCEN Channel3 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all 0 then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.\nNote3: If CH3ZCIF flag is set to 1, the channel3 will be mute. 3 1 read-write 0 channel3 zero-cross detect Disabled #0 1 channel3 zero-cross detect Enabled #1 CH4ZCEN Channel4 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all 0 then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.\nNote3: If CH4ZCIF flag is set to 1, the channel4 will be mute. 4 1 read-write 0 channel4 zero-cross detect Disabled #0 1 channel4 zero-cross detect Enabled #1 CH5ZCEN Channel5 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all 0 then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.\nNote3: If CH5ZCIF flag is set to 1, the channel5 will be mute. 5 1 read-write 0 channel5 zero-cross detect Disabled #0 1 channel5 zero-cross detect Enabled #1 CH6ZCEN Channel6 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all 0 then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.\nNote3: If CH6ZCIF flag is set to 1, the channel6 will be mute. 6 1 read-write 0 channel6 zero-cross detect Disabled #0 1 channel6 zero-cross detect Enabled #1 CH7ZCEN Channel7 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all 0 then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.\nNote3: If CH7ZCIF flag is set to 1, the channel7 will be mute. 7 1 read-write 0 channel7 zero-cross detect Disabled #0 1 channel7 zero-cross detect Enabled #1 PB16ORD FIFO Read/Write Order in 16-bit Width of Peripheral Bus 25 1 read-write 0 Low 16-bit read/write access first #0 1 High 16-bit read/write access first #1 PBWIDTH Peripheral Bus Data Width Selection\nThis bit is used to choice the available data width of APB bus. It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode 24 1 read-write 0 32 bits data width #0 1 16 bits data width #1 RXTH Receive FIFO Threshold Level\nNote: When received data word number in receive buffer is larger than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set. 16 4 read-write 0 1 data word in receive FIFO #0000 1 2 data words in receive FIFO #0001 2 3 data words in receive FIFO #0010 14 15 data words in receive FIFO #1110 15 16 data words in receive FIFO #1111 TXTH Transmit FIFO Threshold Level\nNote: If remain data word number in transmit FIFO is less than or equal to threshold level then TXTHIF (I2S_STATUS0[18]) flag is set. 8 4 read-write 0 0 data word in transmit FIFO #0000 1 1 data word in transmit FIFO #0001 2 2 data words in transmit FIFO #0010 14 14 data words in transmit FIFO #1110 15 15 data words in transmit FIFO #1111 IEN I2S_IEN I2S Interrupt Enable Register 0x8 read-write n 0x0 0x0 CH0ZCIEN Channel0 Zero-cross Interrupt Enable Bit 16 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 CH1ZCIEN Channel1 Zero-cross Interrupt Enable Bit 17 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 CH2ZCIEN Channel2 Zero-cross Interrupt Enable Bit 18 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 CH3ZCIEN Channel3 Zero-cross Interrupt Enable Bit 19 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 CH4ZCIEN Channel4 Zero-cross Interrupt Enable Bit 20 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 CH5ZCIEN Channel5 Zero-cross Interrupt Enable Bit 21 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 CH6ZCIEN Channel6 Zero-cross Interrupt Enable Bit 22 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 CH7ZCIEN Channel7 Zero-cross Interrupt Enable Bit 23 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 RXOVFIEN Receive FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1 1 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 RXTHIEN Receive FIFO Threshold Level Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and data words in receive FIFO is larger than RXTH (I2S_CTL1[19:16]). 2 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 RXUDFIEN Receive FIFO Underflow Interrupt Enable Bit\nNote: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1. If RXUDFIEN bit is enabled, interrupt occurs. 0 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 TXOVFIEN Transmit FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1 9 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 TXTHIEN Transmit FIFO Threshold Level Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than or equal to TXTH (I2S_CTL1[11:8]). 10 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 TXUDFIEN Transmit FIFO Underflow Interrupt Enable Bit\nNote: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1. 8 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 RXFIFO I2S_RXFIFO I2S Receive FIFO Register 0x14 read-only n 0x0 0x0 RXFIFO Receive FIFO Bits\nI2S contains 16 words (16x32 bits) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]). 0 32 read-only STATUS0 I2S_STATUS0 I2S Status Register 0 0xC -1 read-write n 0x0 0x0 DATACH Transmission Data Channel (Read Only)\nThis bit fields are used to indicate which audio channel is current transmit data belong. 3 3 read-only 0 channel0 (means left channel while 2-channel I2S/PCM mode) #000 1 channel1 (means right channel while 2-channel I2S/PCM mode) #001 2 channel2 (available while 4-channel TDM PCM mode) #010 3 channel3 (available while 4-channel TDM PCM mode) #011 4 channel4 (available while 6-channel TDM PCM mode) #100 5 channel5 (available while 6-channel TDM PCM mode) #101 6 channel6 (available while 8-channel TDM PCM mode) #110 7 channel7 (available while 8-channel TDM PCM mode) #111 I2SINT I2S Interrupt Flag (Read Only)\nNote: It is wire-OR of I2STXINT and I2SRXINT bits. 0 1 read-only 0 No I2S interrupt #0 1 I2S interrupt #1 I2SRXINT I2S Receive Interrupt (Read Only) 1 1 read-only 0 No receive interrupt #0 1 Receive interrupt #1 I2STXINT I2S Transmit Interrupt (Read Only) 2 1 read-only 0 No transmit interrupt #0 1 Transmit interrupt #1 RXEMPTY Receive FIFO Empty (Read Only)\nNote: This bit reflects data words number in receive FIFO is 0. 12 1 read-only 0 Not empty #0 1 Empty #1 RXFULL Receive FIFO Full (Read Only)\nNote: This bit reflects data words number in receive FIFO is 16. 11 1 read-only 0 Not full #0 1 Full #1 RXOVIF Receive FIFO Overflow Interrupt Flag\nNote1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwritten.\nNote2: Write 1 to clear this bit to 0. 9 1 read-write 0 No overflow occur #0 1 Overflow occur #1 RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only)\nNote: When data word(s) in receive FIFO is larger than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1. It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is less than or equal to RXTH (I2S_CTL1[19:16]) after software read RXFIFO register. 10 1 read-only 0 Data word(s) in FIFO is less than or equal to threshold level #0 1 Data word(s) in FIFO is larger than threshold level #1 RXUDIF Receive FIFO Underflow Interrupt Flag\nNote1: When receive FIFO is empty, and software reads the receive FIFO again. This bit will be set to 1, and it indicates underflow situation occurs.\nNote2: Write 1 to clear this bit to 0 8 1 read-write 0 No underflow occur #0 1 Underflow occur #1 TXBUSY Transmit Busy (Read Only)\nNote: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer. 21 1 read-only 0 Transmit shift buffer is empty #0 1 Transmit shift buffer is busy #1 TXEMPTY Transmit FIFO Empty (Read Only)\nThis bit reflect data word number in transmit FIFO is 0 20 1 read-only 0 Not empty #0 1 Empty #1 TXFULL Transmit FIFO Full (Read Only)\nThis bit reflect data word number in transmit FIFO is 16 19 1 read-only 0 Not full #0 1 Full #1 TXOVIF Transmit FIFO Overflow Interrupt Flag\nNote1: Write data to transmit FIFO when it is full and this bit set to 1\nNote2: Write 1 to clear this bit to 0. 17 1 read-write 0 No overflow #0 1 Overflow #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only)\nNote: When data word(s) in transmit FIFO is less than or equal to threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1. It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is larger than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register. 18 1 read-only 0 Data word(s) in FIFO is larger than threshold level #0 1 Data word(s) in FIFO is less than or equal to threshold level #1 TXUDIF Transmit FIFO Underflow Interrupt Flag\nNote1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.\nNote2: Write 1 to clear this bit to 0. 16 1 read-write 0 No underflow #0 1 Underflow #1 STATUS1 I2S_STATUS1 I2S Status Register 1 0x24 read-write n 0x0 0x0 CH0ZCIF Channel0 Zero-cross Interrupt Flag\nIt indicates channel0 next sample data sign bit is changed or all data bits are 0. 0 1 read-write 0 No zero-cross in channel0 #0 1 Channel0 zero-cross is detected #1 CH1ZCIF Channel1 Zero-cross Interrupt Flag\nIt indicates channel1 next sample data sign bit is changed or all data bits are 0. 1 1 read-write 0 No zero-cross in channel1 #0 1 Channel1 zero-cross is detected #1 CH2ZCIF Channel2 Zero-cross Interrupt Flag\nIt indicates channel2 next sample data sign bit is changed or all data bits are 0. 2 1 read-write 0 No zero-cross in channel2 #0 1 Channel2 zero-cross is detected #1 CH3ZCIF Channel3 Zero-cross Interrupt Flag\nIt indicates channel3 next sample data sign bit is changed or all data bits are 0. 3 1 read-write 0 No zero-cross in channel3 #0 1 Channel3 zero-cross is detected #1 CH4ZCIF Channel4 Zero-cross Interrupt Flag\nIt indicates channel4 next sample data sign bit is changed or all data bits are 0. 4 1 read-write 0 No zero-cross in channel4 #0 1 Channel4 zero-cross is detected #1 CH5ZCIF Channel5 Zero-cross Interrupt Flag\nIt indicates channel5 next sample data sign bit is changed or all data bits are 0. 5 1 read-write 0 No zero-cross in channel5 #0 1 Channel5 zero-cross is detected #1 CH6ZCIF Channel6 Zero-cross Interrupt Flag\nIt indicates channel6 next sample data sign bit is changed or all data bits are 0. 6 1 read-write 0 No zero-cross in channel6 #0 1 Channel6 zero-cross is detected #1 CH7ZCIF Channel7 Zero-cross Interrupt Flag\nIt indicates channel7 next sample data sign bit is changed or all data bits are 0. 7 1 read-write 0 No zero-cross in channel7 #0 1 Channel7 zero-cross is detected #1 RXCNT Receive FIFO Level (Read Only)\nThese bits indicate the number of available entries in receive FIFO\nOthers are reserved. 16 5 read-only 0 No data #00000 1 1 word in receive FIFO #00001 2 2 words in receive FIFO #00010 14 14 words in receive FIFO #01110 15 15 words in receive FIFO #01111 16 16 words in receive FIFO #10000 TXCNT Transmit FIFO Level (Read Only)\nThese bits indicate the number of available entries in transmit FIFO\nOthers are reserved. 8 5 read-only 0 No data #00000 1 1 word in transmit FIFO #00001 2 2 words in transmit FIFO #00010 14 14 words in transmit FIFO #01110 15 15 words in transmit FIFO #01111 16 16 words in transmit FIFO #10000 TXFIFO I2S_TXFIFO I2S Transmit FIFO Register 0x10 write-only n 0x0 0x0 TXFIFO Transmit FIFO Bits\nThe I2S contains 16 words (16x32 bits) data buffer for data transmit. Write data to this register to prepare data for transmit. The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]). 0 32 write-only NMI NMI Register Map NMI 0x0 0x0 0x8 registers n NMIEN NMIEN NMI Source Interrupt Enable Register 0x0 read-write n 0x0 0x0 BODOUT BOD NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 BOD NMI source Disabled #0 1 BOD NMI source Enabled #1 CLKFAIL Clock Fail Detected NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 Clock fail detected interrupt NMI source Disabled #0 1 Clock fail detected interrupt NMI source Enabled #1 EINT0 External Interrupt From PA.6, or PB.5 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 8 1 read-write 0 External interrupt from PA.6, or PB.5 pin NMI source Disabled #0 1 External interrupt from PA.6, or PB.5 pin NMI source Enabled #1 EINT1 External Interrupt From PA.7 or PB.4 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 9 1 read-write 0 External interrupt from PA.7 or PB.4 pin NMI source Disabled #0 1 External interrupt from PA.7 or P4.4 pin NMI source Enabled #1 EINT2 External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 10 1 read-write 0 External interrupt from PB.3 or PC.6 pin NMI source Disabled #0 1 External interrupt from PB.3 or PC.6 pin NMI source Enabled #1 EINT3 External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 11 1 read-write 0 External interrupt from PB.2 or PC.7pin NMI source Disabled #0 1 External interrupt from PB.2 or PC.7 pin NMI source Enabled #1 EINT4 External Interrupt From PA.8 or PB.6 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 12 1 read-write 0 External interrupt from PA.8 or PB.6 pin NMI source Disabled #0 1 External interrupt from PA.8 or PB.6 pin NMI source Enabled #1 EINT5 External Interrupt From PB.7 or PD.12 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 13 1 read-write 0 External interrupt from PB.7 or PD.12 pin NMI source Disabled #0 1 External interrupt from PB.7 or PD.12 pin NMI source Enabled #1 EINT6 External Interrupt From PB.8 or PD.11 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 16 1 read-write 0 External interrupt from PB.8 or PD.11 pin NMI source Disabled #0 1 External interrupt from PB.8 or PD.11 pin NMI source Enabled #1 EINT7 External Interrupt From PB.9 or PD.10 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 17 1 read-write 0 External interrupt from PB.9 or PD.10 pin NMI source Disabled #0 1 External interrupt from PB.9 or PD.10 pin NMI source Enabled #1 IRCINT IRC TRIM NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 IRC TRIM NMI source Disabled #0 1 IRC TRIM NMI source Enabled #1 PWRWUINT Power-down Mode Wake-up NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 Power-down mode wake-up NMI source Disabled #0 1 Power-down mode wake-up NMI source Enabled #1 RTCINT RTC NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 RTC NMI source Disabled #0 1 RTC NMI source Enabled #1 SRAMPERR SRAM Parity Check Error NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 SRAM parity check error NMI source Disabled #0 1 SRAM parity check error NMI source Enabled #1 TAMPERINT Tamper Interrupt NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Backup register tamper detected interrupt NMI source Disabled #0 1 Backup register tamper detected interrupt NMI source Enabled #1 UART0INT UART0 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 14 1 read-write 0 UART0 NMI source Disabled #0 1 UART0 NMI source Enabled #1 UART1INT UART1 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 15 1 read-write 0 UART1 NMI source Disabled #0 1 UART1 NMI source Enabled #1 NMISTS NMISTS NMI source interrupt Status Register 0x4 read-only n 0x0 0x0 BODOUT BOD Interrupt Flag (Read Only) 0 1 read-only 0 BOD interrupt is deasserted #0 1 BOD interrupt is asserted #1 CLKFAIL Clock Fail Detected Interrupt Flag (Read Only) 4 1 read-only 0 Clock fail detected interrupt is deasserted #0 1 Clock fail detected interrupt is asserted #1 EINT0 External Interrupt From PA.6, or PB.5 Pin Interrupt Flag (Read Only) 8 1 read-only 0 External Interrupt from PA.6, or PB.5 interrupt is deasserted #0 1 External Interrupt from PA.6, or PB.5 interrupt is asserted #1 EINT1 External Interrupt From PA.7, or PB.4 Pin Interrupt Flag (Read Only) 9 1 read-only 0 External Interrupt from PA.7, or PB.4 interrupt is deasserted #0 1 External Interrupt from PA.7, or PB.4 interrupt is asserted #1 EINT2 External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only) 10 1 read-only 0 External Interrupt from PB.3 or PC.6 interrupt is deasserted #0 1 External Interrupt from PB.3 or PC.6 interrupt is asserted #1 EINT3 External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only) 11 1 read-only 0 External Interrupt from PB.2 or PC.7 interrupt is deasserted #0 1 External Interrupt from PB.2 or PC.7 interrupt is asserted #1 EINT4 External Interrupt From PA.8 or PB.6 Pin Interrupt Flag (Read Only) 12 1 read-only 0 External Interrupt from PA.8 or PB.6 interrupt is deasserted #0 1 External Interrupt from PA.8 or PB.6 interrupt is asserted #1 EINT5 External Interrupt From PB.7 or PD.12 Pin Interrupt Flag (Read Only) 13 1 read-only 0 External Interrupt from PB.7 or PD.12 interrupt is deasserted #0 1 External Interrupt from PB.7 or PD.12 interrupt is asserted #1 EINT6 External Interrupt From PB.8 or PD.11 Pin Interrupt Flag (Read Only) 16 1 read-only 0 External Interrupt from PB.8 or PD.11 interrupt is deasserted #0 1 External Interrupt from PB.8 or PD.11 interrupt is asserted #1 EINT7 External Interrupt From PB.9 or PD.10 Pin Interrupt Flag (Read Only) 17 1 read-only 0 External Interrupt from PB.9 or PD.10 interrupt is deasserted #0 1 External Interrupt from PB.9 or PD.10 interrupt is asserted #1 IRCINT IRC TRIM Interrupt Flag (Read Only) 1 1 read-only 0 HIRC TRIM interrupt is deasserted #0 1 HIRC TRIM interrupt is asserted #1 PWRWUINT Power-down Mode Wake-up Interrupt Flag (Read Only) 2 1 read-only 0 Power-down mode wake-up interrupt is deasserted #0 1 Power-down mode wake-up interrupt is asserted #1 RTCINT RTC Interrupt Flag (Read Only) 6 1 read-only 0 RTC interrupt is deasserted #0 1 RTC interrupt is asserted #1 SRAMPERR SRAM ParityCheck Error Interrupt Flag (Read Only) 3 1 read-only 0 SRAM parity check error interrupt is deasserted #0 1 SRAM parity check error interrupt is asserted #1 TAMPERINT Tamper Interrupt Flag (Read Only) 7 1 read-only 0 Backup register tamper detected interrupt is deasserted #0 1 Backup register tamper detected interrupt is asserted #1 UART0INT UART0 Interrupt Flag (Read Only) 14 1 read-only 0 UART1 interrupt is deasserted #0 1 UART1 interrupt is asserted #1 UART1INT UART1 Interrupt Flag (Read Only) 15 1 read-only 0 UART1 interrupt is deasserted #0 1 UART1 interrupt is asserted #1 NVIC NVIC Register Map NVIC 0x0 0x0 0x10 registers n 0x100 0x10 registers n 0x180 0x10 registers n 0x200 0x10 registers n 0x300 0x68 registers n 0x80 0x10 registers n IABR0 NVIC_IABR0 IRQ00 ~ IRQ31 Active Bit Register 0x200 read-write n 0x0 0x0 ACTIVE Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active. 0 32 read-write 0 interrupt not active 0 1 interrupt active 1 IABR1 NVIC_IABR1 IRQ32 ~ IRQ63 Active Bit Register 0x204 read-write n 0x0 0x0 ACTIVE Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active. 0 32 read-write 0 interrupt not active 0 1 interrupt active 1 IABR2 NVIC_IABR2 IRQ64 ~ IRQ95 Active Bit Register 0x208 read-write n 0x0 0x0 ACTIVE Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active. 0 32 read-write 0 interrupt not active 0 1 interrupt active 1 IABR3 NVIC_IABR3 IRQ96 ~ IRQ101 Active Bit Register 0x20C read-write n 0x0 0x0 ACTIVE Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active. 0 32 read-write 0 interrupt not active 0 1 interrupt active 1 ICER0 NVIC_ICER0 IRQ00 ~ IRQ31 Clear-Enable Control Register 0x80 read-write n 0x0 0x0 CALENA Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt Disabled 0 1 Interrupt Disabled.\nInterrupt Enabled 1 ICER1 NVIC_ICER1 IRQ32 ~ IRQ63 Clear-Enable Control Register 0x84 read-write n 0x0 0x0 CALENA Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt Disabled 0 1 Interrupt Disabled.\nInterrupt Enabled 1 ICER2 NVIC_ICER2 IRQ64 ~ IRQ95 Clear-Enable Control Register 0x88 read-write n 0x0 0x0 CALENA Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt Disabled 0 1 Interrupt Disabled.\nInterrupt Enabled 1 ICER3 NVIC_ICER3 IRQ96 ~ IRQ101 Clear-Enable Control Register 0x8C read-write n 0x0 0x0 CALENA Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt Disabled 0 1 Interrupt Disabled.\nInterrupt Enabled 1 ICPR0 NVIC_ICPR0 IRQ00 ~ IRQ31 Clear-Pending Control Register 0x180 read-write n 0x0 0x0 CALPEND Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt is not pending 0 1 Removes pending state an interrupt.\nInterrupt is pending 1 ICPR1 NVIC_ICPR1 IRQ32 ~ IRQ63 Clear-Pending Control Register 0x184 read-write n 0x0 0x0 CALPEND Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt is not pending 0 1 Removes pending state an interrupt.\nInterrupt is pending 1 ICPR2 NVIC_ICPR2 IRQ64 ~ IRQ95 Clear-Pending Control Register 0x188 read-write n 0x0 0x0 CALPEND Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt is not pending 0 1 Removes pending state an interrupt.\nInterrupt is pending 1 ICPR3 NVIC_ICPR3 IRQ96 ~ IRQ101 Clear-Pending Control Register 0x18C read-write n 0x0 0x0 CALPEND Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt is not pending 0 1 Removes pending state an interrupt.\nInterrupt is pending 1 IPR0 NVIC_IPR0 IRQ0 ~ IRQ101 Priority Control Register 0x300 read-write n 0x0 0x0 PRI_4n_0 Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority. 6 2 read-write PRI_4n_1 Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority. 14 2 read-write PRI_4n_2 Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority. 22 2 read-write PRI_4n_3 Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write IPR1 NVIC_IPR1 IRQ0 ~ IRQ101 Priority Control Register 0x304 read-write n 0x0 0x0 IPR10 NVIC_IPR10 IRQ0 ~ IRQ101 Priority Control Register 0x328 read-write n 0x0 0x0 IPR11 NVIC_IPR11 IRQ0 ~ IRQ101 Priority Control Register 0x32C read-write n 0x0 0x0 IPR12 NVIC_IPR12 IRQ0 ~ IRQ101 Priority Control Register 0x330 read-write n 0x0 0x0 IPR13 NVIC_IPR13 IRQ0 ~ IRQ101 Priority Control Register 0x334 read-write n 0x0 0x0 IPR14 NVIC_IPR14 IRQ0 ~ IRQ101 Priority Control Register 0x338 read-write n 0x0 0x0 IPR15 NVIC_IPR15 IRQ0 ~ IRQ101 Priority Control Register 0x33C read-write n 0x0 0x0 IPR16 NVIC_IPR16 IRQ0 ~ IRQ101 Priority Control Register 0x340 read-write n 0x0 0x0 IPR17 NVIC_IPR17 IRQ0 ~ IRQ101 Priority Control Register 0x344 read-write n 0x0 0x0 IPR18 NVIC_IPR18 IRQ0 ~ IRQ101 Priority Control Register 0x348 read-write n 0x0 0x0 IPR19 NVIC_IPR19 IRQ0 ~ IRQ101 Priority Control Register 0x34C read-write n 0x0 0x0 IPR2 NVIC_IPR2 IRQ0 ~ IRQ101 Priority Control Register 0x308 read-write n 0x0 0x0 IPR20 NVIC_IPR20 IRQ0 ~ IRQ101 Priority Control Register 0x350 read-write n 0x0 0x0 IPR21 NVIC_IPR21 IRQ0 ~ IRQ101 Priority Control Register 0x354 read-write n 0x0 0x0 IPR22 NVIC_IPR22 IRQ0 ~ IRQ101 Priority Control Register 0x358 read-write n 0x0 0x0 IPR23 NVIC_IPR23 IRQ0 ~ IRQ101 Priority Control Register 0x35C read-write n 0x0 0x0 IPR24 NVIC_IPR24 IRQ0 ~ IRQ101 Priority Control Register 0x360 read-write n 0x0 0x0 IPR25 NVIC_IPR25 IRQ0 ~ IRQ101 Priority Control Register 0x364 read-write n 0x0 0x0 IPR3 NVIC_IPR3 IRQ0 ~ IRQ101 Priority Control Register 0x30C read-write n 0x0 0x0 IPR4 NVIC_IPR4 IRQ0 ~ IRQ101 Priority Control Register 0x310 read-write n 0x0 0x0 IPR5 NVIC_IPR5 IRQ0 ~ IRQ101 Priority Control Register 0x314 read-write n 0x0 0x0 IPR6 NVIC_IPR6 IRQ0 ~ IRQ101 Priority Control Register 0x318 read-write n 0x0 0x0 IPR7 NVIC_IPR7 IRQ0 ~ IRQ101 Priority Control Register 0x31C read-write n 0x0 0x0 IPR8 NVIC_IPR8 IRQ0 ~ IRQ101 Priority Control Register 0x320 read-write n 0x0 0x0 IPR9 NVIC_IPR9 IRQ0 ~ IRQ101 Priority Control Register 0x324 read-write n 0x0 0x0 ISER0 NVIC_ISER0 IRQ00 ~ IRQ31 Set-Enable Control Register 0x0 read-write n 0x0 0x0 SETENA Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt Disabled 0 1 Interrupt Enabled 1 ISER1 NVIC_ISER1 IRQ32 ~ IRQ63 Set-Enable Control Register 0x4 read-write n 0x0 0x0 SETENA Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt Disabled 0 1 Interrupt Enabled 1 ISER2 NVIC_ISER2 IRQ64 ~ IRQ95 Set-Enable Control Register 0x8 read-write n 0x0 0x0 SETENA Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt Disabled 0 1 Interrupt Enabled 1 ISER3 NVIC_ISER3 IRQ96 ~ IRQ101 Set-Enable Control Register 0xC read-write n 0x0 0x0 SETENA Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt Disabled 0 1 Interrupt Enabled 1 ISPR0 NVIC_ISPR0 IRQ00 ~ IRQ31 Set-Pending Control Register 0x100 read-write n 0x0 0x0 SETPEND Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt is not pending 0 1 Changes interrupt state to pending.\nInterrupt is pending 1 ISPR1 NVIC_ISPR1 IRQ32 ~ IRQ63 Set-Pending Control Register 0x104 read-write n 0x0 0x0 SETPEND Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt is not pending 0 1 Changes interrupt state to pending.\nInterrupt is pending 1 ISPR2 NVIC_ISPR2 IRQ64 ~ IRQ95 Set-Pending Control Register 0x108 read-write n 0x0 0x0 SETPEND Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt is not pending 0 1 Changes interrupt state to pending.\nInterrupt is pending 1 ISPR3 NVIC_ISPR3 IRQ96 ~ IRQ101 Set-Pending Control Register 0x10C read-write n 0x0 0x0 SETPEND Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt is not pending 0 1 Changes interrupt state to pending.\nInterrupt is pending 1 OTG OTG Register Map OTG 0x0 0x0 0x14 registers n CTL OTG_CTL OTG Control Register 0x0 read-write n 0x0 0x0 BUSREQ OTG Bus Request\nIf OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection. If user won't use the bus any more, clearing this bit will drop VBUS to save power. This bit will be cleared when A-device goes to A_wait_vfall state. This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.\nIf user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol. This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues SRP in specified interval, defined in OTG specification). This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed. 1 1 read-write 0 Not launch VBUS in OTG A-device or not request SRP in OTG B-device #0 1 Launch VBUS in OTG A-device or request SRP in OTG B-device #1 HNPREQEN OTG HNP Request Enable Bit\nWhen USB frame as A-device, set this bit when A-device allows to process HNP protocol A-device changes role from Host to Peripheral. This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state. When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change B-device changes role from Peripheral to Host. This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.\nNote: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state. 2 1 read-write 0 HNP request Disabled #0 1 HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host) #1 OTGEN OTG Function Enable Bit\nUser needs to set this bit to enable OTG function while USB frame configured as OTG device. When USB frame not configured as OTG device, this bit is must be low. 4 1 read-write 0 OTG function Disabled #0 1 OTG function Enabled #1 VBUSDROP Drop VBUS Control\nIf user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS. BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device. 0 1 read-write 0 Not drop the VBUS #0 1 Drop the VBUS #1 WKEN OTG ID Pin Wake-up Enable Bit 5 1 read-write 0 OTG ID pin status change wake-up function Disabled #0 1 OTG ID pin status change wake-up function Enabled #1 INTEN OTG_INTEN OTG Interrupt Enable Register 0x8 read-write n 0x0 0x0 AVLDCHGIEN A-device Session Valid Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, an interrupt will be asserted. 9 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 BVLDCHGIEN B-device Session Valid Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, an interrupt will be asserted. 8 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 GOIDLEIEN OTG Device Goes to IDLE State Interrupt Enable Bit\nNote: Going to idle state means going to a_idle or b_idle state. Please refer to A-device state diagram and B-device state diagram in OTG specification. 4 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 HNPFIEN HNP Fail Interrupt Enable Bit 3 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 HOSTIEN Act As Host Interrupt Enable Bit\nIf this bit is set to 1 and the device is changed as a host, an interrupt will be asserted. 7 1 read-write 0 This device as a host interrupt Disabled #0 1 This device as a host interrupt Enabled #1 IDCHGIEN IDSTS Changed Interrupt Enable Bit\nIf this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, an interrupt will be asserted. 5 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 PDEVIEN Act As Peripheral Interrupt Enable Bit\nIf this bit is set to 1 and the device is changed as a peripheral, an interrupt will be asserted. 6 1 read-write 0 This device as a peripheral interrupt Disabled #0 1 This device as a peripheral interrupt Enabled #1 ROLECHGIEN Role (Host or Peripheral) Changed Interrupt Enable Bit 0 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 SECHGIEN SESSEND Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, an interrupt will be asserted. 11 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 SRPDETIEN SRP Detected Interrupt Enable Bit 13 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 SRPFIEN SRP Fail Interrupt Enable Bit 2 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 VBCHGIEN VBUSVLD Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, an interrupt will be asserted. 10 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 VBEIEN VBUS Error Interrupt Enable Bit\nNote: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG specification. 1 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 INTSTS OTG_INTSTS OTG Interrupt Status Register 0xC read-write n 0x0 0x0 AVLDCHGIF A-device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this status. 9 1 read-write 0 AVLD (OTG_STATUS[4]) not toggled #0 1 AVLD (OTG_STATUS[4]) from high to low or low to high #1 BVLDCHGIF B-device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this status. 8 1 read-write 0 BVLD (OTG_STATUS[3]) is not toggled #0 1 BVLD (OTG_STATUS[3]) from high to low or low to high #1 GOIDLEIF OTG Device Goes to IDLE Interrupt Status\nFlag is set if the OTG device transfers from non-idle state to idle state. The OTG device will be neither a host nor a peripheral.\nNote 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification.\nNote 2: Write 1 to clear this flag. 4 1 read-write 0 OTG device does not go back to idle state (a_idle or b_idle) #0 1 OTG device goes back to idle state(a_idle or b_idle) #1 HNPFIF HNP Fail Interrupt Status\nWhen A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires. \nNote: Write 1 to clear this flag. 3 1 read-write 0 A-device connects to B-device before specified interval expires #0 1 A-device does not connect to B-device before specified interval expires #1 HOSTIF Act As Host Interrupt Status\nNote: Write 1 to clear this flag. 7 1 read-write 0 This device does not act as a host #0 1 This device acts as a host #1 IDCHGIF ID State Change Interrupt Status\nNote: Write 1 to clear this flag. 5 1 read-write 0 IDSTS (OTG_STATUS[1]) not toggled #0 1 IDSTS (OTG_STATUS[1]) from high to low or from low to high #1 PDEVIF Act As Peripheral Interrupt Status\nNote: Write 1 to clear this flag. 6 1 read-write 0 This device does not act as a peripheral #0 1 This device acts as a peripheral #1 ROLECHGIF OTG Role Change Interrupt Status\nThis flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.\nNote: Write 1 to clear this flag. 0 1 read-write 0 OTG device role not changed #0 1 OTG device role changed #1 SECHGIF SESSEND State Change Interrupt Status\nNote: Write 1 to clear this flag. 11 1 read-write 0 SESSEND (OTG_STATUS[2]) not toggled #0 1 SESSEND (OTG_STATUS[2]) from high to low or from low to high #1 SRPDETIF SRP Detected Interrupt Status\nNote: Write 1 to clear this status. 13 1 read-write 0 SRP not detected #0 1 SRP detected #1 SRPFIF SRP Fail Interrupt Status\nAfter initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification. This flag is set when the OTG B-device does not get VBUS high after this interval.\nNote: Write 1 to clear this flag. 2 1 read-write 0 OTG B-device gets VBUS high before this interval #0 1 OTG B-device does not get VBUS high before this interval #1 VBCHGIF VBUSVLD State Change Interrupt Status\nNote: Write 1 to clear this status. 10 1 read-write 0 VBUSVLD (OTG_STATUS[5]) not toggled #0 1 VBUSVLD (OTG_STATUS[5]) from high to low or from low to high #1 VBEIF VBUS Error Interrupt Status\nThis bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. \nNote: Write 1 to clear this flag and recover from the VBUS error state. 1 1 read-write 0 OTG A-device drives VBUS over threshold voltage before this interval expires #0 1 OTG A-device cannot drive VBUS over threshold voltage before this interval expires #1 PHYCTL OTG_PHYCTL OTG PHY Control Register 0x4 read-write n 0x0 0x0 IDDETEN ID Detection Enable Bit 1 1 read-write 0 Detect ID pin status Disabled #0 1 Detect ID pin status Enabled #1 OTGPHYEN OTG PHY Enable Bit\nWhen USB frame is configured as either OTG-device or ID-dependent, user needs to set this bit before using OTG function. If device is configured as neither OTG-device nor ID-dependent, this bit is 'don't care'. 0 1 read-write 0 OTG PHY Disabled #0 1 OTG PHY Enabled #1 VBENPOL Off-chip USB VBUS Power Switch Enable Polarity\nThe OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need. A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.\nThe polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component. Set this bit as following according to the polarity of off-chip USB VBUS power switch. 4 1 read-write 0 The off-chip USB VBUS power switch enable is active high #0 1 The off-chip USB VBUS power switch enable is active low #1 VBSTSPOL Off-chip USB VBUS Power Switch Status Polarity\nThe polarity of off-chip USB VBUS power switch valid signal depends on the selected component. A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch. Set this bit as following according to the polarity of off-chip USB VBUS power switch. 5 1 read-write 0 The polarity of off-chip USB VBUS power switch valid status is high #0 1 The polarity of off-chip USB VBUS power switch valid status is low #1 STATUS OTG_STATUS OTG Status Register 0x10 -1 read-only n 0x0 0x0 ASHOST As Host Status\nWhen OTG acts as Host, this bit is set.\n0: OTG not as Host\n1: OTG as Host 7 1 read-only ASPERI As Peripheral Status\nWhen OTG acts as peripheral, this bit is set.\n0: OTG not as peripheral\n1: OTG as peripheral 6 1 read-only AVLD A-device Session Valid Status 4 1 read-only 0 A-device session is not valid #0 1 A-device session is valid #1 BVLD B-device Session Valid Status 3 1 read-only 0 B-device session is not valid #0 1 B-device session is valid #1 IDSTS USB_ID Pin State of Mini-/Micro-plug 1 1 read-only 0 Mini-A/Micro-A plug is attached #0 1 Mini-B/Micro-B plug is attached #1 OVERCUR Over Current Condition\nThe voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high. 0 1 read-only 0 OTG A-device drives VBUS successfully #0 1 OTG A-device cannot drives VBUS high in this interval #1 SESSEND Session End Status\nWhen VBUS voltage is lower than 0.4V, this bit will be set to 1. Session end means no meaningful power on VBUS. 2 1 read-only 0 Session is not end #0 1 Session is end #1 VBUSVLD VBUS Valid Status\nWhen VBUS is larger than 4.7V, this bit will be set to 1. 5 1 read-only 0 VBUS is not valid #0 1 VBUS is valid #1 PDMA0 PDMA Register Map PDMA 0x0 0x0 0xA0 registers n 0x400 0x44 registers n 0x460 0x4 registers n 0x480 0x8 registers n 0x500 0x30 registers n PDMAx_ABTSTS PDMAx_ABTSTS PDMA Channel Read/Write Target Abort Flag Register 0x420 read-write n 0x0 0x0 ABTIF0 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 0 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF1 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 1 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF2 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 2 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF3 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 3 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF4 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 4 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF5 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 5 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF6 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 6 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF7 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 7 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 PDMAx_ALIGN PDMAx_ALIGN PDMA Transfer Alignment Status Register 0x428 read-write n 0x0 0x0 ALIGN0 Transfer Alignment Flag 0 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN1 Transfer Alignment Flag 1 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN2 Transfer Alignment Flag 2 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN3 Transfer Alignment Flag 3 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN4 Transfer Alignment Flag 4 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN5 Transfer Alignment Flag 5 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN6 Transfer Alignment Flag 6 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN7 Transfer Alignment Flag 7 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 PDMAx_ASOCR0 PDMAx_ASOCR0 Address Stride Offset Register of PDMA Channel 0 0x504 read-write n 0x0 0x0 DASOL VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row. 16 16 read-write SASOL VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row. 0 16 read-write PDMAx_ASOCR1 PDMAx_ASOCR1 Address Stride Offset Register of PDMA Channel 1 0x50C read-write n 0x0 0x0 PDMAx_ASOCR2 PDMAx_ASOCR2 Address Stride Offset Register of PDMA Channel 2 0x514 read-write n 0x0 0x0 PDMAx_ASOCR3 PDMAx_ASOCR3 Address Stride Offset Register of PDMA Channel 3 0x51C read-write n 0x0 0x0 PDMAx_ASOCR4 PDMAx_ASOCR4 Address Stride Offset Register of PDMA Channel 4 0x524 read-write n 0x0 0x0 PDMAx_ASOCR5 PDMAx_ASOCR5 Address Stride Offset Register of PDMA Channel 5 0x52C read-write n 0x0 0x0 PDMAx_CHCTL PDMAx_CHCTL PDMA Channel Control Register 0x400 read-write n 0x0 0x0 CHEN0 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 0 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN1 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 1 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN2 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 2 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN3 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 3 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN4 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 4 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN5 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 5 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN6 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 6 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN7 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 7 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 PDMAx_CHRST PDMAx_CHRST PDMA Channel Reset Register 0x460 read-write n 0x0 0x0 CH0RST Channel N Reset 0 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 CH1RST Channel N Reset 1 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 CH2RST Channel N Reset 2 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 CH3RST Channel N Reset 3 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 CH4RST Channel N Reset 4 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 CH5RST Channel N Reset 5 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 CH6RST Channel N Reset 6 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 CH7RST Channel N Reset 7 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 PDMAx_CURSCAT0 PDMAx_CURSCAT0 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x80 read-only n 0x0 0x0 CURADDR PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external description address. 0 32 read-only PDMAx_CURSCAT1 PDMAx_CURSCAT1 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x84 read-write n 0x0 0x0 PDMAx_CURSCAT2 PDMAx_CURSCAT2 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x88 read-write n 0x0 0x0 PDMAx_CURSCAT3 PDMAx_CURSCAT3 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x8C read-write n 0x0 0x0 PDMAx_CURSCAT4 PDMAx_CURSCAT4 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x90 read-write n 0x0 0x0 PDMAx_CURSCAT5 PDMAx_CURSCAT5 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x94 read-write n 0x0 0x0 PDMAx_CURSCAT6 PDMAx_CURSCAT6 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x98 read-write n 0x0 0x0 PDMAx_CURSCAT7 PDMAx_CURSCAT7 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x9C read-write n 0x0 0x0 PDMAx_DSCT0_CTL PDMAx_DSCT0_CTL Descriptor Table Control Register of PDMA Channel n 0x0 read-write n 0x0 0x0 BURSIZE Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type. 4 3 read-write 0 128 Transfers #000 1 64 Transfers #001 2 32 Transfers #010 3 16 Transfers #011 4 8 Transfers #100 5 4 Transfers #101 6 2 Transfers #110 7 1 Transfers #111 DAINC Destination Address Increment\nThis field is used to set the destination address increment size. 10 2 read-write 3 No increment (fixed address) #11 OPMODE PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table, user must check the PDMA_INTSTS[1] to make sure the curren task is complete. 0 2 read-write 0 Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically #00 1 Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[1] will be asserted #01 2 Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register PDMA controller will ignore this task, then load the next task to execute #10 3 Reserved #11 SAINC Source Address Increment\nThis field is used to set the source address increment size. 8 2 read-write 3 No increment (fixed address) #11 STRIDEEN Stride Mode Enable Bit 15 1 read-write 0 Stride transfer mode Disabled #0 1 Stride transfer mode Enabled #1 TBINTDIS Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function only for scatter-gather mode. 7 1 read-write 0 Table interrupt Enabled #0 1 Table interrupt Disabled #1 TXCNT Transfer Count The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field. Note: When PDMA finish each transfer data, this field will be decrease immediately. 16 16 read-write TXTYPE Transfer Type 2 1 read-write 0 Burst transfer type #0 1 Single transfer type #1 TXWIDTH Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection 12 2 read-write 0 One byte (8 bit) is transferred for every operation #00 1 One half-word (16 bit) is transferred for every operation #01 2 One word (32-bit) is transferred for every operation #10 3 Reserved #11 PDMAx_DSCT0_DA PDMAx_DSCT0_DA Destination Address Register of PDMA Channel n 0x8 read-write n 0x0 0x0 DA PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller. 0 32 read-write PDMAx_DSCT0_NEXT PDMAx_DSCT0_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0xC read-write n 0x0 0x0 EXENEXT PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: write operation is useless in this field. 16 16 read-write NEXT PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.\nRead Operation:\nWhen operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory..\nNote1: The descriptor table address must be word boundary.\nNote2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. 0 16 read-write PDMAx_DSCT0_SA PDMAx_DSCT0_SA Source Address Register of PDMA Channel n 0x4 read-write n 0x0 0x0 SA PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller. 0 32 read-write PDMAx_DSCT1_CTL PDMAx_DSCT1_CTL Descriptor Table Control Register of PDMA Channel n 0x10 read-write n 0x0 0x0 PDMAx_DSCT1_DA PDMAx_DSCT1_DA Destination Address Register of PDMA Channel n 0x18 read-write n 0x0 0x0 PDMAx_DSCT1_NEXT PDMAx_DSCT1_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0x1C read-write n 0x0 0x0 PDMAx_DSCT1_SA PDMAx_DSCT1_SA Source Address Register of PDMA Channel n 0x14 read-write n 0x0 0x0 PDMAx_DSCT2_CTL PDMAx_DSCT2_CTL Descriptor Table Control Register of PDMA Channel n 0x20 read-write n 0x0 0x0 PDMAx_DSCT2_DA PDMAx_DSCT2_DA Destination Address Register of PDMA Channel n 0x28 read-write n 0x0 0x0 PDMAx_DSCT2_NEXT PDMAx_DSCT2_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0x2C read-write n 0x0 0x0 PDMAx_DSCT2_SA PDMAx_DSCT2_SA Source Address Register of PDMA Channel n 0x24 read-write n 0x0 0x0 PDMAx_DSCT3_CTL PDMAx_DSCT3_CTL Descriptor Table Control Register of PDMA Channel n 0x30 read-write n 0x0 0x0 PDMAx_DSCT3_DA PDMAx_DSCT3_DA Destination Address Register of PDMA Channel n 0x38 read-write n 0x0 0x0 PDMAx_DSCT3_NEXT PDMAx_DSCT3_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0x3C read-write n 0x0 0x0 PDMAx_DSCT3_SA PDMAx_DSCT3_SA Source Address Register of PDMA Channel n 0x34 read-write n 0x0 0x0 PDMAx_DSCT4_CTL PDMAx_DSCT4_CTL Descriptor Table Control Register of PDMA Channel n 0x40 read-write n 0x0 0x0 PDMAx_DSCT4_DA PDMAx_DSCT4_DA Destination Address Register of PDMA Channel n 0x48 read-write n 0x0 0x0 PDMAx_DSCT4_NEXT PDMAx_DSCT4_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0x4C read-write n 0x0 0x0 PDMAx_DSCT4_SA PDMAx_DSCT4_SA Source Address Register of PDMA Channel n 0x44 read-write n 0x0 0x0 PDMAx_DSCT5_CTL PDMAx_DSCT5_CTL Descriptor Table Control Register of PDMA Channel n 0x50 read-write n 0x0 0x0 PDMAx_DSCT5_DA PDMAx_DSCT5_DA Destination Address Register of PDMA Channel n 0x58 read-write n 0x0 0x0 PDMAx_DSCT5_NEXT PDMAx_DSCT5_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0x5C read-write n 0x0 0x0 PDMAx_DSCT5_SA PDMAx_DSCT5_SA Source Address Register of PDMA Channel n 0x54 read-write n 0x0 0x0 PDMAx_DSCT6_CTL PDMAx_DSCT6_CTL Descriptor Table Control Register of PDMA Channel n 0x60 read-write n 0x0 0x0 PDMAx_DSCT6_DA PDMAx_DSCT6_DA Destination Address Register of PDMA Channel n 0x68 read-write n 0x0 0x0 PDMAx_DSCT6_NEXT PDMAx_DSCT6_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0x6C read-write n 0x0 0x0 PDMAx_DSCT6_SA PDMAx_DSCT6_SA Source Address Register of PDMA Channel n 0x64 read-write n 0x0 0x0 PDMAx_DSCT7_CTL PDMAx_DSCT7_CTL Descriptor Table Control Register of PDMA Channel n 0x70 read-write n 0x0 0x0 PDMAx_DSCT7_DA PDMAx_DSCT7_DA Destination Address Register of PDMA Channel n 0x78 read-write n 0x0 0x0 PDMAx_DSCT7_NEXT PDMAx_DSCT7_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0x7C read-write n 0x0 0x0 PDMAx_DSCT7_SA PDMAx_DSCT7_SA Source Address Register of PDMA Channel n 0x74 read-write n 0x0 0x0 PDMAx_INTEN PDMAx_INTEN PDMA Interrupt Enable Register 0x418 read-write n 0x0 0x0 INTEN0 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 0 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN1 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 1 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN2 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 2 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN3 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 3 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN4 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 4 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN5 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 5 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN6 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 6 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN7 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 7 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 PDMAx_INTSTS PDMAx_INTSTS PDMA Interrupt Status Register 0x41C read-write n 0x0 0x0 ABTIF PDMA Read/Write Target Abort Interrupt Flag (Read Only) This bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error. 0 1 read-only 0 No AHB bus ERROR response received #0 1 AHB bus ERROR response received #1 ALIGNF Transfer Alignment Interrupt Flag (Read Only) 2 1 read-only 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 REQTOF0 Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear this bit. 8 1 read-write 0 No request time-out #0 1 Peripheral request time-out #1 REQTOF1 Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear this bit. 9 1 read-write 0 No request time-out #0 1 Peripheral request time-out #1 TDIF Transfer Done Interrupt Flag (Read Only) This bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer. 1 1 read-only 0 Not finished yet #0 1 PDMA channel has finished transmission #1 PDMAx_PAUSE PDMAx_PAUSE PDMA Transfer Pause Control Register 0x404 write-only n 0x0 0x0 PAUSE0 PDMA Channel N Transfer Pause Control (Write Only) 0 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE1 PDMA Channel N Transfer Pause Control (Write Only) 1 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE2 PDMA Channel N Transfer Pause Control (Write Only) 2 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE3 PDMA Channel N Transfer Pause Control (Write Only) 3 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE4 PDMA Channel N Transfer Pause Control (Write Only) 4 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE5 PDMA Channel N Transfer Pause Control (Write Only) 5 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE6 PDMA Channel N Transfer Pause Control (Write Only) 6 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE7 PDMA Channel N Transfer Pause Control (Write Only) 7 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PDMAx_PRICLR PDMAx_PRICLR PDMA Fixed Priority Clear Register 0x414 write-only n 0x0 0x0 FPRICLR0 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 0 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR1 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 1 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR2 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 2 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR3 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 3 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR4 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 4 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR5 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 5 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR6 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 6 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR7 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 7 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 PDMAx_PRISET PDMAx_PRISET PDMA Fixed Priority Setting Register 0x410 read-write n 0x0 0x0 FPRISET0 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 0 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET1 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 1 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET2 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 2 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET3 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 3 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET4 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 4 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET5 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 5 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET6 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 6 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET7 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 7 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 PDMAx_REQSEL0_3 PDMAx_REQSEL0_3 PDMA Request Source Select Register 0 0x480 read-write n 0x0 0x0 REQSRC0 Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote 1: A peripheral cannot be assigned to two channels at the same time.\nNote 2: This field is useless when transfer between memory and memory. 0 7 read-write 0 Disable PDMA peripheral request 0 1 Reserved 1 10 Channel connects to UART3_TX 10 11 Channel connects to UART3_RX 11 12 Channel connects to UART4_TX 12 13 Channel connects to UART4_RX 13 14 Channel connects to UART5_TX 14 15 Channel connects to UART5_RX 15 16 Channel connects to USCI0_TX 16 17 Channel connects to USCI0_RX 17 18 Channel connects to USCI1_TX 18 19 Channel connects to USCI1_RX 19 2 Channel connects to USB_TX 2 20 Channel connects to QSPI0_TX 20 21 Channel connects to QSPI0_RX 21 22 Channel connects to SPI0_TX 22 23 Channel connects to SPI0_RX 23 24 Channel connects to SPI1_TX 24 25 Channel connects to SPI1_RX 25 26 Channel connects to SPI2_TX 26 27 Channel connects to SPI2_RX 27 28 Channel connects to SPI3_TX 28 29 Channel connects to SPI3_RX 29 3 Channel connects to USB_RX 3 32 Channel connects to EPWM0_P1_RX 32 33 Channel connects to EPWM0_P2_RX 33 34 Channel connects to EPWM0_P3_RX 34 35 Channel connects to EPWM1_P1_RX 35 36 Channel connects to EPWM1_P2_RX 36 37 Channel connects to EPWM1_P3_RX 37 38 Channel connects to I2C0_TX 38 39 Channel connects to I2C0_RX 39 4 Channel connects to UART0_TX 4 40 Channel connects to I2C1_TX 40 41 Channel connects to I2C1_RX 41 42 Channel connects to I2C2_TX 42 43 Channel connects to I2C2_RX 43 44 Channel connects to I2S0_TX 44 45 Channel connects to I2S0_RX 45 46 Channel connects to TMR0 46 47 Channel connects to TMR1 47 48 Channel connects to TMR2 48 49 Channel connects to TMR3 49 5 Channel connects to UART0_RX 5 50 Channel connects to ADC_RX 50 51 Channel connects to DAC0_TX 51 52 Channel connects to DAC1_TX 52 53 Channel connects to EPWM0_CH0_TX 53 54 Channel connects to EPWM0_CH1_TX 54 55 Channel connects to EPWM0_CH2_TX 55 56 Channel connects to EPWM0_CH3_TX 56 57 Channel connects to EPWM0_CH4_TX 57 58 Channel connects to EPWM0_CH5_TX 58 59 Channel connects to EPWM1_CH0_TX 59 6 Channel connects to UART1_TX 6 60 Channel connects to EPWM1_CH1_TX 60 61 Channel connects to EPWM1_CH2_TX 61 62 Channel connects to EPWM1_CH3_TX 62 63 Channel connects to EPWM1_CH4_TX 63 64 Channel connects to EPWM1_CH5_TX 64 7 Channel connects to UART1_RX 7 8 Channel connects to UART2_TX 8 9 Channel connects to UART2_RX 9 REQSRC1 Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 8 7 read-write REQSRC2 Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 16 7 read-write REQSRC3 Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 24 7 read-write PDMAx_REQSEL4_7 PDMAx_REQSEL4_7 PDMA Request Source Select Register 1 0x484 read-write n 0x0 0x0 REQSRC4 Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 0 7 read-write REQSRC5 Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 8 7 read-write REQSRC6 Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 16 7 read-write REQSRC7 Channel 7 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 24 6 read-write PDMAx_SCATBA PDMAx_SCATBA PDMA Scatter-Gather Descriptor Table Base Address Register 0x43C -1 read-write n 0x0 0x0 SCATBA PDMA Scatter-gather Descriptor Table Address\nIn Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-Gather mode. 16 16 read-write PDMAx_STCR0 PDMAx_STCR0 Stride Transfer Count Register of PDMA Channel 0 0x500 read-write n 0x0 0x0 STC PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row. 0 16 read-write PDMAx_STCR1 PDMAx_STCR1 Stride Transfer Count Register of PDMA Channel 1 0x508 read-write n 0x0 0x0 PDMAx_STCR2 PDMAx_STCR2 Stride Transfer Count Register of PDMA Channel 2 0x510 read-write n 0x0 0x0 PDMAx_STCR3 PDMAx_STCR3 Stride Transfer Count Register of PDMA Channel 3 0x518 read-write n 0x0 0x0 PDMAx_STCR4 PDMAx_STCR4 Stride Transfer Count Register of PDMA Channel 4 0x520 read-write n 0x0 0x0 PDMAx_STCR5 PDMAx_STCR5 Stride Transfer Count Register of PDMA Channel 5 0x528 read-write n 0x0 0x0 PDMAx_SWREQ PDMAx_SWREQ PDMA Software Request Register 0x408 write-only n 0x0 0x0 SWREQ0 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 0 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ1 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 1 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ2 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 2 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ3 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 3 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ4 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 4 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ5 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 5 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ6 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 6 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ7 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 7 1 write-only 0 No effect #0 1 Generate a software request #1 PDMAx_TACTSTS PDMAx_TACTSTS PDMA Transfer Active Flag Register 0x42C read-only n 0x0 0x0 TXACTF0 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 0 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF1 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 1 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF2 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 2 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF3 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 3 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF4 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 4 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF5 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 5 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF6 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 6 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF7 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 7 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 PDMAx_TDSTS PDMAx_TDSTS PDMA Channel Transfer Done Flag Register 0x424 read-write n 0x0 0x0 TDIF0 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 0 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF1 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 1 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF2 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 2 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF3 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 3 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF4 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 4 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF5 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 5 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF6 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 6 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF7 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 7 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 PDMAx_TOC0_1 PDMAx_TOC0_1 PDMA Time-out Counter Ch1 and Ch0 Register 0x440 read-write n 0x0 0x0 TOC0 Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock. 0 16 read-write TOC1 Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock. The example of time-out period can refer TOC0 bit description. 16 16 read-write PDMAx_TOUTEN PDMAx_TOUTEN PDMA Time-out Enable Register 0x434 read-write n 0x0 0x0 TOUTEN0 PDMA Time-out Enable Bits 0 1 read-write 0 PDMA Channel n time-out function Disabled #0 1 PDMA Channel n time-out function Enabled #1 TOUTEN1 PDMA Time-out Enable Bits 1 1 read-write 0 PDMA Channel n time-out function Disabled #0 1 PDMA Channel n time-out function Enabled #1 PDMAx_TOUTIEN PDMAx_TOUTIEN PDMA Time-out Interrupt Enable Register 0x438 read-write n 0x0 0x0 TOUTIEN0 PDMA Time-out Interrupt Enable Bits 0 1 read-write 0 PDMA Channel n time-out interrupt Disabled #0 1 PDMA Channel n time-out interrupt Enabled #1 TOUTIEN1 PDMA Time-out Interrupt Enable Bits 1 1 read-write 0 PDMA Channel n time-out interrupt Disabled #0 1 PDMA Channel n time-out interrupt Enabled #1 PDMAx_TOUTPSC PDMAx_TOUTPSC PDMA Time-out Prescaler Register 0x430 read-write n 0x0 0x0 TOUTPSC0 PDMA Channel 0 Time-out Clock Source Prescaler Bits 0 3 read-write 0 PDMA channel 0 time-out clock source is HCLK/28 #000 1 PDMA channel 0 time-out clock source is HCLK/29 #001 2 PDMA channel 0 time-out clock source is HCLK/210 #010 3 PDMA channel 0 time-out clock source is HCLK/211 #011 4 PDMA channel 0 time-out clock source is HCLK/212 #100 5 PDMA channel 0 time-out clock source is HCLK/213 #101 6 PDMA channel 0 time-out clock source is HCLK/214 #110 7 PDMA channel 0 time-out clock source is HCLK/215 #111 TOUTPSC1 PDMA Channel 1 Time-out Clock Source Prescaler Bits 4 3 read-write 0 PDMA channel 1 time-out clock source is HCLK/28 #000 1 PDMA channel 1 time-out clock source is HCLK/29 #001 2 PDMA channel 1 time-out clock source is HCLK/210 #010 3 PDMA channel 1 time-out clock source is HCLK/211 #011 4 PDMA channel 1 time-out clock source is HCLK/212 #100 5 PDMA channel 1 time-out clock source is HCLK/213 #101 6 PDMA channel 1 time-out clock source is HCLK/214 #110 7 PDMA channel 1 time-out clock source is HCLK/215 #111 PDMAx_TRGSTS PDMAx_TRGSTS PDMA Channel Request Status Register 0x40C read-only n 0x0 0x0 REQSTS0 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 0 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS1 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 1 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS2 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 2 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS3 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 3 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS4 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 4 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS5 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 5 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS6 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 6 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS7 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 7 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 PDMA1 PDMA Register Map PDMA 0x0 0x0 0xA0 registers n 0x400 0x44 registers n 0x460 0x4 registers n 0x480 0x8 registers n 0x500 0x30 registers n PDMAx_ABTSTS PDMAx_ABTSTS PDMA Channel Read/Write Target Abort Flag Register 0x420 read-write n 0x0 0x0 ABTIF0 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 0 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF1 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 1 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF2 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 2 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF3 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 3 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF4 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 4 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF5 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 5 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF6 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 6 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF7 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel x target abort, REQSRCx should set 0 to disable peripheral request. 7 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 PDMAx_ALIGN PDMAx_ALIGN PDMA Transfer Alignment Status Register 0x428 read-write n 0x0 0x0 ALIGN0 Transfer Alignment Flag 0 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN1 Transfer Alignment Flag 1 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN2 Transfer Alignment Flag 2 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN3 Transfer Alignment Flag 3 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN4 Transfer Alignment Flag 4 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN5 Transfer Alignment Flag 5 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN6 Transfer Alignment Flag 6 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN7 Transfer Alignment Flag 7 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 PDMAx_ASOCR0 PDMAx_ASOCR0 Address Stride Offset Register of PDMA Channel 0 0x504 read-write n 0x0 0x0 DASOL VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row. 16 16 read-write SASOL VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row. 0 16 read-write PDMAx_ASOCR1 PDMAx_ASOCR1 Address Stride Offset Register of PDMA Channel 1 0x50C read-write n 0x0 0x0 PDMAx_ASOCR2 PDMAx_ASOCR2 Address Stride Offset Register of PDMA Channel 2 0x514 read-write n 0x0 0x0 PDMAx_ASOCR3 PDMAx_ASOCR3 Address Stride Offset Register of PDMA Channel 3 0x51C read-write n 0x0 0x0 PDMAx_ASOCR4 PDMAx_ASOCR4 Address Stride Offset Register of PDMA Channel 4 0x524 read-write n 0x0 0x0 PDMAx_ASOCR5 PDMAx_ASOCR5 Address Stride Offset Register of PDMA Channel 5 0x52C read-write n 0x0 0x0 PDMAx_CHCTL PDMAx_CHCTL PDMA Channel Control Register 0x400 read-write n 0x0 0x0 CHEN0 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 0 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN1 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 1 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN2 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 2 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN3 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 3 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN4 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 4 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN5 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 5 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN6 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 6 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN7 PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 7 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 PDMAx_CHRST PDMAx_CHRST PDMA Channel Reset Register 0x460 read-write n 0x0 0x0 CH0RST Channel N Reset 0 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 CH1RST Channel N Reset 1 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 CH2RST Channel N Reset 2 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 CH3RST Channel N Reset 3 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 CH4RST Channel N Reset 4 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 CH5RST Channel N Reset 5 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 CH6RST Channel N Reset 6 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 CH7RST Channel N Reset 7 1 read-write 0 corresponding channel n is not reset #0 1 corresponding channel n is reset #1 PDMAx_CURSCAT0 PDMAx_CURSCAT0 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x80 read-only n 0x0 0x0 CURADDR PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external description address. 0 32 read-only PDMAx_CURSCAT1 PDMAx_CURSCAT1 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x84 read-write n 0x0 0x0 PDMAx_CURSCAT2 PDMAx_CURSCAT2 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x88 read-write n 0x0 0x0 PDMAx_CURSCAT3 PDMAx_CURSCAT3 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x8C read-write n 0x0 0x0 PDMAx_CURSCAT4 PDMAx_CURSCAT4 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x90 read-write n 0x0 0x0 PDMAx_CURSCAT5 PDMAx_CURSCAT5 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x94 read-write n 0x0 0x0 PDMAx_CURSCAT6 PDMAx_CURSCAT6 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x98 read-write n 0x0 0x0 PDMAx_CURSCAT7 PDMAx_CURSCAT7 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 0x9C read-write n 0x0 0x0 PDMAx_DSCT0_CTL PDMAx_DSCT0_CTL Descriptor Table Control Register of PDMA Channel n 0x0 read-write n 0x0 0x0 BURSIZE Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type. 4 3 read-write 0 128 Transfers #000 1 64 Transfers #001 2 32 Transfers #010 3 16 Transfers #011 4 8 Transfers #100 5 4 Transfers #101 6 2 Transfers #110 7 1 Transfers #111 DAINC Destination Address Increment\nThis field is used to set the destination address increment size. 10 2 read-write 3 No increment (fixed address) #11 OPMODE PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table, user must check the PDMA_INTSTS[1] to make sure the curren task is complete. 0 2 read-write 0 Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically #00 1 Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[1] will be asserted #01 2 Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register PDMA controller will ignore this task, then load the next task to execute #10 3 Reserved #11 SAINC Source Address Increment\nThis field is used to set the source address increment size. 8 2 read-write 3 No increment (fixed address) #11 STRIDEEN Stride Mode Enable Bit 15 1 read-write 0 Stride transfer mode Disabled #0 1 Stride transfer mode Enabled #1 TBINTDIS Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function only for scatter-gather mode. 7 1 read-write 0 Table interrupt Enabled #0 1 Table interrupt Disabled #1 TXCNT Transfer Count The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field. Note: When PDMA finish each transfer data, this field will be decrease immediately. 16 16 read-write TXTYPE Transfer Type 2 1 read-write 0 Burst transfer type #0 1 Single transfer type #1 TXWIDTH Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection 12 2 read-write 0 One byte (8 bit) is transferred for every operation #00 1 One half-word (16 bit) is transferred for every operation #01 2 One word (32-bit) is transferred for every operation #10 3 Reserved #11 PDMAx_DSCT0_DA PDMAx_DSCT0_DA Destination Address Register of PDMA Channel n 0x8 read-write n 0x0 0x0 DA PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller. 0 32 read-write PDMAx_DSCT0_NEXT PDMAx_DSCT0_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0xC read-write n 0x0 0x0 EXENEXT PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: write operation is useless in this field. 16 16 read-write NEXT PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.\nRead Operation:\nWhen operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory..\nNote1: The descriptor table address must be word boundary.\nNote2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. 0 16 read-write PDMAx_DSCT0_SA PDMAx_DSCT0_SA Source Address Register of PDMA Channel n 0x4 read-write n 0x0 0x0 SA PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller. 0 32 read-write PDMAx_DSCT1_CTL PDMAx_DSCT1_CTL Descriptor Table Control Register of PDMA Channel n 0x10 read-write n 0x0 0x0 PDMAx_DSCT1_DA PDMAx_DSCT1_DA Destination Address Register of PDMA Channel n 0x18 read-write n 0x0 0x0 PDMAx_DSCT1_NEXT PDMAx_DSCT1_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0x1C read-write n 0x0 0x0 PDMAx_DSCT1_SA PDMAx_DSCT1_SA Source Address Register of PDMA Channel n 0x14 read-write n 0x0 0x0 PDMAx_DSCT2_CTL PDMAx_DSCT2_CTL Descriptor Table Control Register of PDMA Channel n 0x20 read-write n 0x0 0x0 PDMAx_DSCT2_DA PDMAx_DSCT2_DA Destination Address Register of PDMA Channel n 0x28 read-write n 0x0 0x0 PDMAx_DSCT2_NEXT PDMAx_DSCT2_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0x2C read-write n 0x0 0x0 PDMAx_DSCT2_SA PDMAx_DSCT2_SA Source Address Register of PDMA Channel n 0x24 read-write n 0x0 0x0 PDMAx_DSCT3_CTL PDMAx_DSCT3_CTL Descriptor Table Control Register of PDMA Channel n 0x30 read-write n 0x0 0x0 PDMAx_DSCT3_DA PDMAx_DSCT3_DA Destination Address Register of PDMA Channel n 0x38 read-write n 0x0 0x0 PDMAx_DSCT3_NEXT PDMAx_DSCT3_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0x3C read-write n 0x0 0x0 PDMAx_DSCT3_SA PDMAx_DSCT3_SA Source Address Register of PDMA Channel n 0x34 read-write n 0x0 0x0 PDMAx_DSCT4_CTL PDMAx_DSCT4_CTL Descriptor Table Control Register of PDMA Channel n 0x40 read-write n 0x0 0x0 PDMAx_DSCT4_DA PDMAx_DSCT4_DA Destination Address Register of PDMA Channel n 0x48 read-write n 0x0 0x0 PDMAx_DSCT4_NEXT PDMAx_DSCT4_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0x4C read-write n 0x0 0x0 PDMAx_DSCT4_SA PDMAx_DSCT4_SA Source Address Register of PDMA Channel n 0x44 read-write n 0x0 0x0 PDMAx_DSCT5_CTL PDMAx_DSCT5_CTL Descriptor Table Control Register of PDMA Channel n 0x50 read-write n 0x0 0x0 PDMAx_DSCT5_DA PDMAx_DSCT5_DA Destination Address Register of PDMA Channel n 0x58 read-write n 0x0 0x0 PDMAx_DSCT5_NEXT PDMAx_DSCT5_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0x5C read-write n 0x0 0x0 PDMAx_DSCT5_SA PDMAx_DSCT5_SA Source Address Register of PDMA Channel n 0x54 read-write n 0x0 0x0 PDMAx_DSCT6_CTL PDMAx_DSCT6_CTL Descriptor Table Control Register of PDMA Channel n 0x60 read-write n 0x0 0x0 PDMAx_DSCT6_DA PDMAx_DSCT6_DA Destination Address Register of PDMA Channel n 0x68 read-write n 0x0 0x0 PDMAx_DSCT6_NEXT PDMAx_DSCT6_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0x6C read-write n 0x0 0x0 PDMAx_DSCT6_SA PDMAx_DSCT6_SA Source Address Register of PDMA Channel n 0x64 read-write n 0x0 0x0 PDMAx_DSCT7_CTL PDMAx_DSCT7_CTL Descriptor Table Control Register of PDMA Channel n 0x70 read-write n 0x0 0x0 PDMAx_DSCT7_DA PDMAx_DSCT7_DA Destination Address Register of PDMA Channel n 0x78 read-write n 0x0 0x0 PDMAx_DSCT7_NEXT PDMAx_DSCT7_NEXT Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 0x7C read-write n 0x0 0x0 PDMAx_DSCT7_SA PDMAx_DSCT7_SA Source Address Register of PDMA Channel n 0x74 read-write n 0x0 0x0 PDMAx_INTEN PDMAx_INTEN PDMA Interrupt Enable Register 0x418 read-write n 0x0 0x0 INTEN0 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 0 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN1 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 1 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN2 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 2 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN3 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 3 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN4 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 4 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN5 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 5 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN6 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 6 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN7 PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align. 7 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 PDMAx_INTSTS PDMAx_INTSTS PDMA Interrupt Status Register 0x41C read-write n 0x0 0x0 ABTIF PDMA Read/Write Target Abort Interrupt Flag (Read Only) This bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error. 0 1 read-only 0 No AHB bus ERROR response received #0 1 AHB bus ERROR response received #1 ALIGNF Transfer Alignment Interrupt Flag (Read Only) 2 1 read-only 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 REQTOF0 Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear this bit. 8 1 read-write 0 No request time-out #0 1 Peripheral request time-out #1 REQTOF1 Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear this bit. 9 1 read-write 0 No request time-out #0 1 Peripheral request time-out #1 TDIF Transfer Done Interrupt Flag (Read Only) This bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer. 1 1 read-only 0 Not finished yet #0 1 PDMA channel has finished transmission #1 PDMAx_PAUSE PDMAx_PAUSE PDMA Transfer Pause Control Register 0x404 write-only n 0x0 0x0 PAUSE0 PDMA Channel N Transfer Pause Control (Write Only) 0 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE1 PDMA Channel N Transfer Pause Control (Write Only) 1 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE2 PDMA Channel N Transfer Pause Control (Write Only) 2 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE3 PDMA Channel N Transfer Pause Control (Write Only) 3 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE4 PDMA Channel N Transfer Pause Control (Write Only) 4 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE5 PDMA Channel N Transfer Pause Control (Write Only) 5 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE6 PDMA Channel N Transfer Pause Control (Write Only) 6 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE7 PDMA Channel N Transfer Pause Control (Write Only) 7 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PDMAx_PRICLR PDMAx_PRICLR PDMA Fixed Priority Clear Register 0x414 write-only n 0x0 0x0 FPRICLR0 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 0 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR1 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 1 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR2 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 2 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR3 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 3 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR4 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 4 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR5 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 5 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR6 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 6 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR7 PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 7 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 PDMAx_PRISET PDMAx_PRISET PDMA Fixed Priority Setting Register 0x410 read-write n 0x0 0x0 FPRISET0 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 0 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET1 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 1 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET2 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 2 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET3 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 3 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET4 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 4 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET5 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 5 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET6 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 6 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET7 PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 7 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 PDMAx_REQSEL0_3 PDMAx_REQSEL0_3 PDMA Request Source Select Register 0 0x480 read-write n 0x0 0x0 REQSRC0 Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote 1: A peripheral cannot be assigned to two channels at the same time.\nNote 2: This field is useless when transfer between memory and memory. 0 7 read-write 0 Disable PDMA peripheral request 0 1 Reserved 1 10 Channel connects to UART3_TX 10 11 Channel connects to UART3_RX 11 12 Channel connects to UART4_TX 12 13 Channel connects to UART4_RX 13 14 Channel connects to UART5_TX 14 15 Channel connects to UART5_RX 15 16 Channel connects to USCI0_TX 16 17 Channel connects to USCI0_RX 17 18 Channel connects to USCI1_TX 18 19 Channel connects to USCI1_RX 19 2 Channel connects to USB_TX 2 20 Channel connects to QSPI0_TX 20 21 Channel connects to QSPI0_RX 21 22 Channel connects to SPI0_TX 22 23 Channel connects to SPI0_RX 23 24 Channel connects to SPI1_TX 24 25 Channel connects to SPI1_RX 25 26 Channel connects to SPI2_TX 26 27 Channel connects to SPI2_RX 27 28 Channel connects to SPI3_TX 28 29 Channel connects to SPI3_RX 29 3 Channel connects to USB_RX 3 32 Channel connects to EPWM0_P1_RX 32 33 Channel connects to EPWM0_P2_RX 33 34 Channel connects to EPWM0_P3_RX 34 35 Channel connects to EPWM1_P1_RX 35 36 Channel connects to EPWM1_P2_RX 36 37 Channel connects to EPWM1_P3_RX 37 38 Channel connects to I2C0_TX 38 39 Channel connects to I2C0_RX 39 4 Channel connects to UART0_TX 4 40 Channel connects to I2C1_TX 40 41 Channel connects to I2C1_RX 41 42 Channel connects to I2C2_TX 42 43 Channel connects to I2C2_RX 43 44 Channel connects to I2S0_TX 44 45 Channel connects to I2S0_RX 45 46 Channel connects to TMR0 46 47 Channel connects to TMR1 47 48 Channel connects to TMR2 48 49 Channel connects to TMR3 49 5 Channel connects to UART0_RX 5 50 Channel connects to ADC_RX 50 51 Channel connects to DAC0_TX 51 52 Channel connects to DAC1_TX 52 53 Channel connects to EPWM0_CH0_TX 53 54 Channel connects to EPWM0_CH1_TX 54 55 Channel connects to EPWM0_CH2_TX 55 56 Channel connects to EPWM0_CH3_TX 56 57 Channel connects to EPWM0_CH4_TX 57 58 Channel connects to EPWM0_CH5_TX 58 59 Channel connects to EPWM1_CH0_TX 59 6 Channel connects to UART1_TX 6 60 Channel connects to EPWM1_CH1_TX 60 61 Channel connects to EPWM1_CH2_TX 61 62 Channel connects to EPWM1_CH3_TX 62 63 Channel connects to EPWM1_CH4_TX 63 64 Channel connects to EPWM1_CH5_TX 64 7 Channel connects to UART1_RX 7 8 Channel connects to UART2_TX 8 9 Channel connects to UART2_RX 9 REQSRC1 Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 8 7 read-write REQSRC2 Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 16 7 read-write REQSRC3 Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 24 7 read-write PDMAx_REQSEL4_7 PDMAx_REQSEL4_7 PDMA Request Source Select Register 1 0x484 read-write n 0x0 0x0 REQSRC4 Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 0 7 read-write REQSRC5 Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 8 7 read-write REQSRC6 Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 16 7 read-write REQSRC7 Channel 7 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 24 6 read-write PDMAx_SCATBA PDMAx_SCATBA PDMA Scatter-Gather Descriptor Table Base Address Register 0x43C -1 read-write n 0x0 0x0 SCATBA PDMA Scatter-gather Descriptor Table Address\nIn Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-Gather mode. 16 16 read-write PDMAx_STCR0 PDMAx_STCR0 Stride Transfer Count Register of PDMA Channel 0 0x500 read-write n 0x0 0x0 STC PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row. 0 16 read-write PDMAx_STCR1 PDMAx_STCR1 Stride Transfer Count Register of PDMA Channel 1 0x508 read-write n 0x0 0x0 PDMAx_STCR2 PDMAx_STCR2 Stride Transfer Count Register of PDMA Channel 2 0x510 read-write n 0x0 0x0 PDMAx_STCR3 PDMAx_STCR3 Stride Transfer Count Register of PDMA Channel 3 0x518 read-write n 0x0 0x0 PDMAx_STCR4 PDMAx_STCR4 Stride Transfer Count Register of PDMA Channel 4 0x520 read-write n 0x0 0x0 PDMAx_STCR5 PDMAx_STCR5 Stride Transfer Count Register of PDMA Channel 5 0x528 read-write n 0x0 0x0 PDMAx_SWREQ PDMAx_SWREQ PDMA Software Request Register 0x408 write-only n 0x0 0x0 SWREQ0 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 0 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ1 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 1 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ2 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 2 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ3 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 3 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ4 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 4 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ5 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 5 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ6 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 6 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ7 PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 7 1 write-only 0 No effect #0 1 Generate a software request #1 PDMAx_TACTSTS PDMAx_TACTSTS PDMA Transfer Active Flag Register 0x42C read-only n 0x0 0x0 TXACTF0 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 0 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF1 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 1 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF2 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 2 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF3 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 3 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF4 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 4 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF5 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 5 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF6 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 6 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF7 Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active. 7 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 PDMAx_TDSTS PDMAx_TDSTS PDMA Channel Transfer Done Flag Register 0x424 read-write n 0x0 0x0 TDIF0 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 0 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF1 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 1 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF2 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 2 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF3 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 3 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF4 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 4 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF5 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 5 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF6 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 6 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF7 Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 7 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 PDMAx_TOC0_1 PDMAx_TOC0_1 PDMA Time-out Counter Ch1 and Ch0 Register 0x440 read-write n 0x0 0x0 TOC0 Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock. 0 16 read-write TOC1 Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock. The example of time-out period can refer TOC0 bit description. 16 16 read-write PDMAx_TOUTEN PDMAx_TOUTEN PDMA Time-out Enable Register 0x434 read-write n 0x0 0x0 TOUTEN0 PDMA Time-out Enable Bits 0 1 read-write 0 PDMA Channel n time-out function Disabled #0 1 PDMA Channel n time-out function Enabled #1 TOUTEN1 PDMA Time-out Enable Bits 1 1 read-write 0 PDMA Channel n time-out function Disabled #0 1 PDMA Channel n time-out function Enabled #1 PDMAx_TOUTIEN PDMAx_TOUTIEN PDMA Time-out Interrupt Enable Register 0x438 read-write n 0x0 0x0 TOUTIEN0 PDMA Time-out Interrupt Enable Bits 0 1 read-write 0 PDMA Channel n time-out interrupt Disabled #0 1 PDMA Channel n time-out interrupt Enabled #1 TOUTIEN1 PDMA Time-out Interrupt Enable Bits 1 1 read-write 0 PDMA Channel n time-out interrupt Disabled #0 1 PDMA Channel n time-out interrupt Enabled #1 PDMAx_TOUTPSC PDMAx_TOUTPSC PDMA Time-out Prescaler Register 0x430 read-write n 0x0 0x0 TOUTPSC0 PDMA Channel 0 Time-out Clock Source Prescaler Bits 0 3 read-write 0 PDMA channel 0 time-out clock source is HCLK/28 #000 1 PDMA channel 0 time-out clock source is HCLK/29 #001 2 PDMA channel 0 time-out clock source is HCLK/210 #010 3 PDMA channel 0 time-out clock source is HCLK/211 #011 4 PDMA channel 0 time-out clock source is HCLK/212 #100 5 PDMA channel 0 time-out clock source is HCLK/213 #101 6 PDMA channel 0 time-out clock source is HCLK/214 #110 7 PDMA channel 0 time-out clock source is HCLK/215 #111 TOUTPSC1 PDMA Channel 1 Time-out Clock Source Prescaler Bits 4 3 read-write 0 PDMA channel 1 time-out clock source is HCLK/28 #000 1 PDMA channel 1 time-out clock source is HCLK/29 #001 2 PDMA channel 1 time-out clock source is HCLK/210 #010 3 PDMA channel 1 time-out clock source is HCLK/211 #011 4 PDMA channel 1 time-out clock source is HCLK/212 #100 5 PDMA channel 1 time-out clock source is HCLK/213 #101 6 PDMA channel 1 time-out clock source is HCLK/214 #110 7 PDMA channel 1 time-out clock source is HCLK/215 #111 PDMAx_TRGSTS PDMAx_TRGSTS PDMA Channel Request Status Register 0x40C read-only n 0x0 0x0 REQSTS0 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 0 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS1 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 1 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS2 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 2 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS3 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 3 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS4 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 4 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS5 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 5 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS6 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 6 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS7 PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 7 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 QEI0 QEI Register Map QEI 0x0 0x0 0x10 registers n 0x14 0x8 registers n 0x2C 0x4 registers n QEI_CNT QEI_CNT QEI Counter Register 0x0 read-write n 0x0 0x0 CNT Quadrature Encoder Interface Counter \nA 32-bit up/down counter. When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF(QEI_STATUS[8]) is 0. This register performs an integrator which count value is proportional to the encoder position. The pulse counter may be initialized to a predetermined value by one of three events occurs: 0 32 read-write QEI_CNTCMP QEI_CNTCMP QEI Counter Compare Register 0xC read-write n 0x0 0x0 CNTCMP Quadrature Encoder Interface Counter Compare 0 32 read-write QEI_CNTHOLD QEI_CNTHOLD QEI Counter Hold Register 0x4 read-write n 0x0 0x0 CNTHOLD Quadrature Encoder Interface Counter Hold\nWhen the bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register. 0 32 read-write QEI_CNTLATCH QEI_CNTLATCH QEI Counter Index Latch Register 0x8 read-write n 0x0 0x0 CNTLATCH Quadrature Encoder Interface Counter Index Latch\nWhen the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register. 0 32 read-write QEI_CNTMAX QEI_CNTMAX QEI Pre-set Maximum Count Register 0x14 read-write n 0x0 0x0 CNTMAX Quadrature Encoder Interface Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode. 0 32 read-write QEI_CTL QEI_CTL QEI Controller Control Register 0x18 read-write n 0x0 0x0 CHAEN QEA Input to QEI Controller Enable Bit 4 1 read-write 0 QEA input to QEI Controller Disabled #0 1 QEA input to QEI Controller Enabled #1 CHAINV Inverse QEA Input Polarity 12 1 read-write 0 Not inverse QEA input polarity #0 1 QEA input polarity is inversed to QEI controller #1 CHBEN QEB Input to QEI Controller Enable Bit 5 1 read-write 0 QEB input to QEI Controller Disabled #0 1 QEB input to QEI Controller Enabled #1 CHBINV Inverse QEB Input Polarity 13 1 read-write 0 Not inverse QEB input polarity #0 1 QEB input polarity is inversed to QEI controller #1 CMPEN The Compare Function Enable Bit\nThe compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set. 28 1 read-write 0 Compare function Disabled #0 1 Compare function Enabled #1 CMPIEN CMPF Trigger QEI Interrupt Enable Bit 18 1 read-write 0 CMPF can trigger QEI controller interrupt Disabled #0 1 CMPF can trigger QEI controller interrupt Enabled #1 DIRIEN DIRCHGF Trigger QEI Interrupt Enable Bit 17 1 read-write 0 DIRCHGF can trigger QEI controller interrupt Disabled #0 1 DIRCHGF can trigger QEI controller interrupt Enabled #1 HOLDCNT Hold QEI_CNT Control When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD(QEI_CNTHOLD[31:0]). This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value. 24 1 read-write 0 No operation #0 1 QEI_CNT content is captured and stored in CNTHOLD(QEI_CNTHOLD[31:0]) #1 HOLDTMR0 Hold QEI_CNT by Timer 0 20 1 read-write 0 TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT #0 1 A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1 #1 HOLDTMR1 Hold QEI_CNT by Timer 1 21 1 read-write 0 TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT #0 1 A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1 #1 HOLDTMR2 Hold QEI_CNT by Timer 2 22 1 read-write 0 TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT #0 1 A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1 #1 HOLDTMR3 Hold QEI_CNT by Timer 3 23 1 read-write 0 TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT #0 1 A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1 #1 IDXEN IDX Input to QEI Controller Enable Bit 6 1 read-write 0 IDX input to QEI Controller Disabled #0 1 IDX input to QEI Controller Enabled #1 IDXIEN IDXF Trigger QEI Interrupt Enable Bit 19 1 read-write 0 The IDXF can trigger QEI interrupt Disabled #0 1 The IDXF can trigger QEI interrupt Enabled #1 IDXINV Inverse IDX Input Polarity 14 1 read-write 0 Not inverse IDX input polarity #0 1 IDX input polarity is inversed to QEI controller #1 IDXLATEN Index Latch QEI_CNT Enable Bit\nIf this bit is set to high, the CNT(QEI_CNT[31:0]) content will be latched into CNTLATCH (QEI_CNTLATCH[31:0]) at every rising on signal CHX. 25 1 read-write 0 The index signal latch QEI counter function Disabled #0 1 The index signal latch QEI counter function Enabled #1 IDXRLDEN Index Trigger QEI_CNT Reload Enable Bit 27 1 read-write 0 Reload function Disabled #0 1 QEI_CNT re-initialized by Index signal Enabled #1 MODE QEI Counting Mode Selection\nThere are four quadrature encoder pulse counter operation modes. 8 2 read-write 0 X4 Free-counting Mode #00 1 X2 Free-counting Mode #01 2 X4 Compare-counting Mode #10 3 X2 Compare-counting Mode #11 NFCLKSEL Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock . 0 3 read-write 0 QEI_CLK #000 1 QEI_CLK/2 #001 2 QEI_CLK/4 #010 3 QEI_CLK/16 #011 4 QEI_CLK/32 #100 5 QEI_CLK/64 #101 NFDIS QEI Controller Input Noise Filter Disable Bit 3 1 read-write 0 The noise filter of QEI controller Enabled #0 1 The noise filter of QEI controller Disabled #1 OVUNIEN OVUNF Trigger QEI Interrupt Enable Bit 16 1 read-write 0 OVUNF can trigger QEI controller interrupt Disabled #0 1 OVUNF can trigger QEI controller interrupt Enabled #1 QEIEN Quadrature Encoder Interface Controller Enable Bit 29 1 read-write 0 QEI controller function Disabled #0 1 QEI controller function Enabled #1 QEI_STATUS QEI_STATUS QEI Controller Status Register 0x2C read-write n 0x0 0x0 CMPF Compare-match Flag\nIf the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).\nNote: This bit is only cleared by writing 1 to it. 1 1 read-write 0 QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]) #0 1 QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]) #1 DIRCHGF Direction Change Flag\nFlag is set by hardware while QEI counter counting direction is changed. Software can clear this bit by writing 1 to it.\nNote: This bit is only cleared by writing 1 to it. 3 1 read-write 0 No change in QEI counter counting direction #0 1 QEI counter counting direction is changed #1 DIRF QEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB. 8 1 read-write 0 QEI Counter is in down-counting #0 1 QEI Counter is in up-counting #1 IDXF IDX Detected Flag\nWhen the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it. 0 1 read-write 0 No rising edge detected on signal CHX #0 1 A rising edge occurs on signal CHX #1 OVUNF QEI Counter Overflow or Underflow Flag\nFlag is set by hardware while CNT(QEI_CNT[31:0]) overflows from 0xFFFF_FFFF to 0 in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to 0 in compare-counting mode. Similarly, the flag is set while QEI counter underflows from 0 to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]).\nNote: This bit is only cleared by writing 1 to it. 2 1 read-write 0 No overflow or underflow occurs in QEI counter #0 1 QEI counter occurs counting overflow or underflow #1 QEI1 QEI Register Map QEI 0x0 0x0 0x10 registers n 0x14 0x8 registers n 0x2C 0x4 registers n QEI_CNT QEI_CNT QEI Counter Register 0x0 read-write n 0x0 0x0 CNT Quadrature Encoder Interface Counter \nA 32-bit up/down counter. When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF(QEI_STATUS[8]) is 0. This register performs an integrator which count value is proportional to the encoder position. The pulse counter may be initialized to a predetermined value by one of three events occurs: 0 32 read-write QEI_CNTCMP QEI_CNTCMP QEI Counter Compare Register 0xC read-write n 0x0 0x0 CNTCMP Quadrature Encoder Interface Counter Compare 0 32 read-write QEI_CNTHOLD QEI_CNTHOLD QEI Counter Hold Register 0x4 read-write n 0x0 0x0 CNTHOLD Quadrature Encoder Interface Counter Hold\nWhen the bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register. 0 32 read-write QEI_CNTLATCH QEI_CNTLATCH QEI Counter Index Latch Register 0x8 read-write n 0x0 0x0 CNTLATCH Quadrature Encoder Interface Counter Index Latch\nWhen the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register. 0 32 read-write QEI_CNTMAX QEI_CNTMAX QEI Pre-set Maximum Count Register 0x14 read-write n 0x0 0x0 CNTMAX Quadrature Encoder Interface Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode. 0 32 read-write QEI_CTL QEI_CTL QEI Controller Control Register 0x18 read-write n 0x0 0x0 CHAEN QEA Input to QEI Controller Enable Bit 4 1 read-write 0 QEA input to QEI Controller Disabled #0 1 QEA input to QEI Controller Enabled #1 CHAINV Inverse QEA Input Polarity 12 1 read-write 0 Not inverse QEA input polarity #0 1 QEA input polarity is inversed to QEI controller #1 CHBEN QEB Input to QEI Controller Enable Bit 5 1 read-write 0 QEB input to QEI Controller Disabled #0 1 QEB input to QEI Controller Enabled #1 CHBINV Inverse QEB Input Polarity 13 1 read-write 0 Not inverse QEB input polarity #0 1 QEB input polarity is inversed to QEI controller #1 CMPEN The Compare Function Enable Bit\nThe compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set. 28 1 read-write 0 Compare function Disabled #0 1 Compare function Enabled #1 CMPIEN CMPF Trigger QEI Interrupt Enable Bit 18 1 read-write 0 CMPF can trigger QEI controller interrupt Disabled #0 1 CMPF can trigger QEI controller interrupt Enabled #1 DIRIEN DIRCHGF Trigger QEI Interrupt Enable Bit 17 1 read-write 0 DIRCHGF can trigger QEI controller interrupt Disabled #0 1 DIRCHGF can trigger QEI controller interrupt Enabled #1 HOLDCNT Hold QEI_CNT Control When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD(QEI_CNTHOLD[31:0]). This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value. 24 1 read-write 0 No operation #0 1 QEI_CNT content is captured and stored in CNTHOLD(QEI_CNTHOLD[31:0]) #1 HOLDTMR0 Hold QEI_CNT by Timer 0 20 1 read-write 0 TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT #0 1 A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1 #1 HOLDTMR1 Hold QEI_CNT by Timer 1 21 1 read-write 0 TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT #0 1 A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1 #1 HOLDTMR2 Hold QEI_CNT by Timer 2 22 1 read-write 0 TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT #0 1 A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1 #1 HOLDTMR3 Hold QEI_CNT by Timer 3 23 1 read-write 0 TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT #0 1 A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1 #1 IDXEN IDX Input to QEI Controller Enable Bit 6 1 read-write 0 IDX input to QEI Controller Disabled #0 1 IDX input to QEI Controller Enabled #1 IDXIEN IDXF Trigger QEI Interrupt Enable Bit 19 1 read-write 0 The IDXF can trigger QEI interrupt Disabled #0 1 The IDXF can trigger QEI interrupt Enabled #1 IDXINV Inverse IDX Input Polarity 14 1 read-write 0 Not inverse IDX input polarity #0 1 IDX input polarity is inversed to QEI controller #1 IDXLATEN Index Latch QEI_CNT Enable Bit\nIf this bit is set to high, the CNT(QEI_CNT[31:0]) content will be latched into CNTLATCH (QEI_CNTLATCH[31:0]) at every rising on signal CHX. 25 1 read-write 0 The index signal latch QEI counter function Disabled #0 1 The index signal latch QEI counter function Enabled #1 IDXRLDEN Index Trigger QEI_CNT Reload Enable Bit 27 1 read-write 0 Reload function Disabled #0 1 QEI_CNT re-initialized by Index signal Enabled #1 MODE QEI Counting Mode Selection\nThere are four quadrature encoder pulse counter operation modes. 8 2 read-write 0 X4 Free-counting Mode #00 1 X2 Free-counting Mode #01 2 X4 Compare-counting Mode #10 3 X2 Compare-counting Mode #11 NFCLKSEL Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock . 0 3 read-write 0 QEI_CLK #000 1 QEI_CLK/2 #001 2 QEI_CLK/4 #010 3 QEI_CLK/16 #011 4 QEI_CLK/32 #100 5 QEI_CLK/64 #101 NFDIS QEI Controller Input Noise Filter Disable Bit 3 1 read-write 0 The noise filter of QEI controller Enabled #0 1 The noise filter of QEI controller Disabled #1 OVUNIEN OVUNF Trigger QEI Interrupt Enable Bit 16 1 read-write 0 OVUNF can trigger QEI controller interrupt Disabled #0 1 OVUNF can trigger QEI controller interrupt Enabled #1 QEIEN Quadrature Encoder Interface Controller Enable Bit 29 1 read-write 0 QEI controller function Disabled #0 1 QEI controller function Enabled #1 QEI_STATUS QEI_STATUS QEI Controller Status Register 0x2C read-write n 0x0 0x0 CMPF Compare-match Flag\nIf the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).\nNote: This bit is only cleared by writing 1 to it. 1 1 read-write 0 QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]) #0 1 QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]) #1 DIRCHGF Direction Change Flag\nFlag is set by hardware while QEI counter counting direction is changed. Software can clear this bit by writing 1 to it.\nNote: This bit is only cleared by writing 1 to it. 3 1 read-write 0 No change in QEI counter counting direction #0 1 QEI counter counting direction is changed #1 DIRF QEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB. 8 1 read-write 0 QEI Counter is in down-counting #0 1 QEI Counter is in up-counting #1 IDXF IDX Detected Flag\nWhen the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it. 0 1 read-write 0 No rising edge detected on signal CHX #0 1 A rising edge occurs on signal CHX #1 OVUNF QEI Counter Overflow or Underflow Flag\nFlag is set by hardware while CNT(QEI_CNT[31:0]) overflows from 0xFFFF_FFFF to 0 in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to 0 in compare-counting mode. Similarly, the flag is set while QEI counter underflows from 0 to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]).\nNote: This bit is only cleared by writing 1 to it. 2 1 read-write 0 No overflow or underflow occurs in QEI counter #0 1 QEI counter occurs counting overflow or underflow #1 QSPI0 QSPI Register Map QSPI 0x0 0x0 0x18 registers n 0x20 0x4 registers n 0x30 0x4 registers n QSPIx_CLKDIV QSPIx_CLKDIV QSPI Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. 0 9 read-write QSPIx_CTL QSPIx_CTL QSPI Control Register 0x0 -1 read-write n 0x0 0x0 CLKPOL Clock Polarity 3 1 read-write 0 QSPI bus clock is idle low #0 1 QSPI bus clock is idle high #1 DATDIR Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer 20 1 read-write 0 QSPI data is input direction #0 1 QSPI data is output direction #1 DUALIOEN Dual I/O Mode Enable Bit 21 1 read-write 0 Dual I/O mode Disabled #0 1 Dual I/O mode Enabled #1 DWIDTH Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits. 8 5 read-write HALFDPX QSPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for QSPI transfer. The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. 14 1 read-write 0 QSPI operates in full-duplex transfer #0 1 QSPI operates in half-duplex transfer #1 LSB Send LSB First 13 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, bit 0 of the QSPIx TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPIx_RX) #1 QUADIOEN Quad I/O Mode Enable Bit 22 1 read-write 0 Quad I/O mode Disabled #0 1 Quad I/O mode Enabled #1 REORDER Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 19 1 read-write 0 Byte Reorder function Disabled #0 1 Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV #1 RXNEG Receive on Negative Edge 1 1 read-write 0 Received data input signal is latched on the rising edge of QSPI bus clock #0 1 Received data input signal is latched on the falling edge of QSPI bus clock #1 RXONLY Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode. In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. 15 1 read-write 0 Receive-only mode Disabled #0 1 Receive-only mode Enabled #1 SLAVE Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SPIEN QSPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the SPIEN (QSPIx_CTL[0]) and confirm the SPIENSTS (QSPIx_STATUS[15]) is 0. 0 1 read-write 0 Transfer control Disabled #0 1 Transfer control Enabled #1 SUSPITV Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of QSPI_CLK clock cycle\nExample: 4 4 read-write TWOBIT 2-bit Transfer Mode Enable Bit\nNote: When 2-bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. 16 1 read-write 0 2-bit Transfer mode Disabled #0 1 2-bit Transfer mode Enabled #1 TXNEG Transmit on Negative Edge 2 1 read-write 0 Transmitted data output signal is changed on the rising edge of QSPI bus clock #0 1 Transmitted data output signal is changed on the falling edge of QSPI bus clock #1 UNITIEN Unit Transfer Interrupt Enable Bit 17 1 read-write 0 QSPI unit transfer interrupt Disabled #0 1 QSPI unit transfer interrupt Enabled #1 QSPIx_FIFOCTL QSPIx_FIFOCTL QSPI FIFO Control Register 0x10 -1 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared. 8 1 read-write 0 No effect #0 1 Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 RXOVIEN Receive FIFO Overrun Interrupt Enable Bit 5 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RXRST Receive Reset 0 1 read-write 0 No effect #0 1 Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not #1 RXTH Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. 24 3 read-write RXTHIEN Receive FIFO Threshold Interrupt Enable Bit 2 1 read-write 0 RX FIFO threshold interrupt Disabled #0 1 RX FIFO threshold interrupt Enabled #1 RXTOIEN Slave Receive Time-out Interrupt Enable Bit 4 1 read-write 0 Receive time-out interrupt Disabled #0 1 Receive time-out interrupt Enabled #1 TXFBCLR Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared. 9 1 read-write 0 No effect #0 1 Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 TXRST Transmit Reset\nNote: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make SPI return to idle state. 1 1 read-write 0 No effect #0 1 Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not #1 TXTH Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. 28 3 read-write TXTHIEN Transmit FIFO Threshold Interrupt Enable Bit 3 1 read-write 0 TX FIFO threshold interrupt Disabled #0 1 TX FIFO threshold interrupt Enabled #1 TXUFIEN TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt. 7 1 read-write 0 Slave TX underflow interrupt Disabled #0 1 Slave TX underflow interrupt Enabled #1 TXUFPOL TX Underflow Data Polarity\nNote:\n1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\n2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame. 6 1 read-write 0 The QSPI data out is keep 0 if there is TX underflow event in Slave mode #0 1 The QSPI data out is keep 1 if there is TX underflow event in Slave mode #1 QSPIx_PDMACTL QSPIx_PDMACTL QSPI PDMA Control Register 0xC read-write n 0x0 0x0 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0 #1 RXPDMAEN Receive PDMA Enable Bit 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit\nNote: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 QSPIx_RX QSPIx_RX QSPI Data Receive Register 0x30 read-only n 0x0 0x0 RX Data Receive Register (Read Only)\nThere are 8-level FIFO buffers in this controller. The data receive register holds the data received from QSPI data input pin. If the RXEMPTY (QSPIx_STATUS[8) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. 0 32 read-only QSPIx_SSCTL QSPIx_SSCTL QSPI Slave Select Control Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit (Master Only) 3 1 read-write 0 Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]) #0 1 Automatic slave selection function Enabled #1 SLV3WIRE Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPIx_CLK, QSPIx_MISO and SPIx_MOSI pins. 4 1 read-write 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit 8 1 read-write 0 Slave mode bit count error interrupt Disabled #0 1 Slave mode bit count error interrupt Enabled #1 SLVTOCNT Slave Mode Time-out Period\nIn Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled. 16 16 read-write SLVTOIEN Slave Mode Time-out Interrupt Enable Bit 5 1 read-write 0 Slave mode time-out interrupt Disabled #0 1 Slave mode time-out interrupt Enabled #1 SLVTORST Slave Mode Time-out Reset Control 6 1 read-write 0 When Slave mode time-out event occurs, the TX and RX control circuit will not be reset #0 1 When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware #1 SLVURIEN Slave Mode TX Under Run Interrupt Enable Bit 9 1 read-write 0 Slave mode TX under run interrupt Disabled #0 1 Slave mode TX under run interrupt Enabled #1 SS Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0, 0 1 read-write 0 set the QSPIx_SS line to inactive state.\nKeep the QSPIx_SS line at inactive state #0 1 set the QSPIx_SS line to active state.\nQSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]) #1 SSACTIEN Slave Select Active Interrupt Enable Bit 12 1 read-write 0 Slave select active interrupt Disabled #0 1 Slave select active interrupt Enabled #1 SSACTPOL Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (QSPIx_SS). 2 1 read-write 0 The slave selection signal QSPIx_SS is active low #0 1 The slave selection signal QSPIx_SS is active high #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit 13 1 read-write 0 Slave select inactive interrupt Disabled #0 1 Slave select inactive interrupt Enabled #1 QSPIx_STATUS QSPIx_STATUS QSPI Status Register 0x14 -1 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 0 1 read-only 0 QSPI controller is in idle state #0 1 QSPI controller is in busy state #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write 0 No FIFO is overrun #0 1 Receive FIFO is overrun #1 RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 SLVBEIF Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it. 6 1 read-write 0 No Slave mode bit count error event #0 1 Slave mode bit count error event occurred #1 SLVTOIF Slave Time-out Interrupt Flag \nWhen the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in QSPI controller logic will be started. When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPIx_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.\nNote: This bit will be cleared by writing 1 to it. 5 1 read-write 0 Slave time-out is not active #0 1 Slave time-out is active #1 SLVURIF Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 7 1 read-write 0 No Slave TX under run event #0 1 Slave TX under run event occurred #1 SPIENSTS QSPI Enable Status (Read Only)\nNote: The QSPI peripheral clock is asynchronous with the system clock. In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller. 15 1 read-only 0 QSPI controller Disabled #0 1 QSPI controller Enabled #1 SSACTIF Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 2 1 read-write 0 Slave select active interrupt was cleared or not occurred #0 1 Slave select active interrupt event occurred #1 SSINAIF Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 3 1 read-write 0 Slave select inactive interrupt was cleared or not occurred #0 1 Slave select inactive interrupt event occurred #1 SSLINE Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status. 4 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 19 1 read-write 0 No effect #0 1 No data in Transmit FIFO and TX shift register when the slave selection signal is active #1 UNITIF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 1 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 QSPI controller has finished one unit transfer #1 QSPIx_TX QSPIx_TX QSPI Data Transmit Register 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in QSPI mode.\nIn QSPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the QSPI controller will perform a 32-bit transfer.\nNote: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 0 32 write-only RTC RTC Register Map RTC 0x0 0x0 0x80 registers n 0x100 0xC registers n 0x110 0x4 registers n 0x120 0x4 registers n 0x128 0x4 registers n 0x130 0x8 registers n 0x140 0x8 registers n CAL RTC_CAL RTC Calendar Loading Register 0x10 -1 read-write n 0x0 0x0 DAY 1-Day Calendar Digit (0~9) 0 4 read-write MON 1-Month Calendar Digit (0~9) 8 4 read-write TENDAY 10-Day Calendar Digit (0~3) 4 2 read-write TENMON 10-Month Calendar Digit (0~1) 12 1 read-write TENYEAR 10-Year Calendar Digit (0~9) 20 4 read-write YEAR 1-Year Calendar Digit (0~9) 16 4 read-write CALM RTC_CALM RTC Calendar Alarm Register 0x20 read-write n 0x0 0x0 DAY 1-Day Calendar Digit of Alarm Setting (0~9) 0 4 read-write MON 1-Month Calendar Digit of Alarm Setting (0~9) 8 4 read-write TENDAY 10-Day Calendar Digit of Alarm Setting (0~3) 4 2 read-write TENMON 10-Month Calendar Digit of Alarm Setting (0~1) 12 1 read-write TENYEAR 10-Year Calendar Digit of Alarm Setting (0~9) 20 4 read-write YEAR 1-Year Calendar Digit of Alarm Setting (0~9) 16 4 read-write CAMSK RTC_CAMSK RTC Calendar Alarm Mask Register 0x38 read-write n 0x0 0x0 MDAY Mask 1-Day Calendar Digit of Alarm Setting (0~9) 0 1 read-write MMON Mask 1-Month Calendar Digit of Alarm Setting (0~9) 2 1 read-write MTENDAY Mask 10-Day Calendar Digit of Alarm Setting (0~3) 1 1 read-write MTENMON Mask 10-Month Calendar Digit of Alarm Setting (0~1) 3 1 read-write MTENYEAR Mask 10-Year Calendar Digit of Alarm Setting (0~9) 5 1 read-write MYEAR Mask 1-Year Calendar Digit of Alarm Setting (0~9) 4 1 read-write CDBR RTC_CDBR Clock Frequency Detector Boundary Register 0x144 -1 read-write n 0x0 0x0 FAILBD LXT Clock Frequency Detector FAIL Boundary\nThe bits define the fail value of frequency monitor window.\nWhen LXT frequency monitor counter lower than Clock Frequency Detector fail Boundary , the LXT frequency detect fail interrupt flag will set to 1.\nNote: The boundary is defined as the minimun value of LXT among 256 LIRC32K clock time. 16 8 read-write STOPBD LXT Clock Stop Frequency Detector Stop Boundary\nThe bits define the stop value of frequency monitor window.\nWhen LXT frequency monitor counter lower than Clock Frequency Detector Stop Boundary , the LXT frequency detect Stop interrupt flag will set to 1.\nNote: The boundary is defined as the maximun value of LXT among 256 LIRC32K clock time. 0 8 read-write CLKDCTL RTC_CLKDCTL Clock Fail Detector Control Register 0x140 read-write n 0x0 0x0 CLKSWLIRCF LXT Clock Detector Fail/Stop Switch LIRC32K Flag (Read Only) 16 1 read-only 0 RTC clock source from LXT #0 1 RTC clock source from LIRC32K #1 LXTFDEN LXT Clock Fail/Stop Detector Enable Bit 0 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock fail/stop detector Disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock fail/stop detector Enabled #1 LXTFSW LXT Clock Fail Detector Switch LIRC32K Enable Bit 1 1 read-write 0 LXT clock Fail switch LIRC32K Disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock Fail detector rise, RTC 32K source switch from LIRC32K. #1 LXTSLOWF LXT Slower Than LIRC32K Flag (Read Only ) \nNote: LXTSLOWF is vaild during CLKSPIF (RTC_INTSTS[25]) or CLKFIF (RTC_INTSTS[24]) rising. 17 1 read-only 0 32.768 kHz external low speed crystal oscillator (LXT) frequency faster than LIRC32K #0 1 LXT frequency is slowly #1 LXTSPSW LXT Clock Stop Detector Switch LIRC32K Enable Bit 2 1 read-write 0 LXT clock Stop switch LIRC32K Disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock stop detector rise, RTC 32K source switch from LIRC32K. #1 CLKFMT RTC_CLKFMT RTC Time Scale Selection Register 0x14 -1 read-write n 0x0 0x0 HZCNTEN Sub-second Counter Enable Bit 8 1 read-write 0 HZCNT disabled in RTC_TIME and RTC_TALM #0 1 HZCNT enabled in RTC_TIME and RTC_TALM #1 _24HEN 24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale 0 1 read-write 0 12-hour time scale with AM and PM indication selected #0 1 24-hour time scale selected #1 DSTCTL RTC_DSTCTL RTC Daylight Saving Time Control Register 0x110 read-write n 0x0 0x0 ADDHR Add 1 Hour 0 1 read-write 0 No effect #0 1 Indicates RTC hour digit has been added one hour for summer time change #1 DSBAK Daylight Saving Back 2 1 read-write 0 Daylight Saving Change is not performed #0 1 Daylight Saving Change is performed #1 SUBHR Subtract 1 Hour 1 1 read-write 0 No effect #0 1 Indicates RTC hour digit has been subtracted one hour for winter time change #1 FREQADJ RTC_FREQADJ RTC Frequency Compensation Register 0x8 -1 read-write n 0x0 0x0 FREQADJ Frequency Compensation Register\nUser must to get actual LXT frequency for RTC application. 0 22 read-write GPIOCTL0 RTC_GPIOCTL0 RTC GPIO Control 0 Register 0x104 read-write n 0x0 0x0 CTLSEL0 I/O Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled, PF.4 pin (X32KO pin) can be used as GPIO function. User can program CTLSEL0 to decide PF.4 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\nPF.4 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1.\nNote: CTLSEL0 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 3 1 read-write 0 PF.4 pin I/O function is controlled by GPIO module #0 1 PF.4 pin I/O function is controlled by VBAT power domain #1 CTLSEL1 I/O Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled, PF.5 pin (X32KI pin) can be used as GPIO function. User can program CTLSEL1 to decide PF.5 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\nPF.5 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1.\nNote: CTLSEL1 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 11 1 read-write 0 PF.5 pin I/O function is controlled by GPIO module #0 1 PF.5 pin I/O function is controlled by VBAT power domain #1 CTLSEL2 I/O Pin State Backup Selection\nWhen TAMP0EN is disabled, PF.6 pin (TAMPER0 pin) can be used as GPIO function. User can program CTLSEL2 to decide PF.6 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\nPF.6 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1.\nNote: CTLSEL2 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 19 1 read-write 0 PF.6 pin I/O function is controlled by GPIO module #0 1 PF.6 pin I/O function is controlled by VBAT power domain #1 CTLSEL3 I/O Pin State Backup Selection\nWhen TAMP1EN is disabled, PF.7 pin (TAMPER1 pin) can be used as GPIO function. User can program CTLSEL3 to decide PF.7 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\nPF.7 pin function and I/O status are controlled by OPMODE3[1:0] and DOUT3 after CTLSEL3 is set to 1.\nNote: CTLSEL3 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1 27 1 read-write 0 PF.7 pin I/O function is controlled by GPIO module #0 1 PF.7 pin I/O function is controlled by VBAT power domain #1 DOUT0 I/O Output Data 2 1 read-write 0 PF.4 output low #0 1 PF.4 output high #1 DOUT1 I/O Output Data 10 1 read-write 0 PF.5 output low #0 1 PF.5 output high #1 DOUT2 I/O Output Data 18 1 read-write 0 PF.6 output low #0 1 PF.6 output high #1 DOUT3 I/O Output Data 26 1 read-write 0 PF.7 output low #0 1 PF.7 output high #1 OPMODE0 I/O Operation Mode 0 2 read-write 0 PF.4 is input only mode #00 1 PF.4 is output push pull mode #01 2 PF.4 is open drain mode #10 3 PF.4 is quasi-bidirectional mode #11 OPMODE1 I/O Operation Mode 8 2 read-write 0 PF.5 is input only mode #00 1 PF.5 is output push pull mode #01 2 PF.5 is open drain mode #10 3 PF.5 is quasi-bidirectional mode #11 OPMODE2 I/O Operation Mode 16 2 read-write 0 PF.6 is input only mode #00 1 PF.6 is output push pull mode #01 2 PF.6 is open drain mode #10 3 PF.6 is quasi-bidirectional mode #11 OPMODE3 I/O Operation Mode 24 2 read-write 0 PF.7 is input only mode #00 1 PF.7 is output push pull mode #01 2 PF.7 is open drain mode #10 3 PF.7 is quasi-bidirectional mode #11 PUSEL0 I/O Pull-up and Pull-down \nDetermine PF.4 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE0 set as input tri-state and open-drain mode. 4 2 read-write 0 PF.4 pull-up and pull-down disabled #00 1 PF.4 pull-up enabled #01 2 PF.4 pull-down enabled #10 3 PF.4 pull-up and pull-down disabled #11 PUSEL1 I/O Pull-up and Pull-down Enable Bits\nDetermine PF.5 I/O pullOpull-up or pull-down.\nNote:\nBasically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE1 set as input tri-state and open-drain mode. 12 2 read-write 0 PF.5 pull-up and pull-down disabled #00 1 PF.5 pull-up enabled #01 2 PF.5 pull-down enabled #10 3 PF.5 pull-up and pull-down disabled #11 PUSEL2 I/O Pull-up and Pull-down Enable Bits\nDetermine PF.6 I/O pull-up or pull-down.\nNote1:\nBasically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE2 set as input tri-state and open-drain mode. 20 2 read-write 0 PF.6 pull-up and pull-down disabled #00 1 PF.6 pull-up enabled #01 2 PF.6 pull-down enabled #10 3 PF.6 pull-up and pull-down disabled #11 PUSEL3 I/O Pull-up and Pull-down Enable Bits\nDetermine PF.7 I/O pull-up or pull-down.\nNote:\nBasically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE3 set as input tri-state and open-drain mode. 28 2 read-write 0 PF.7 pull-up and pull-down disabled #00 1 PF.7 pull-up enabled #01 2 PF.7 pull-down enabled #10 3 PF.7 pull-up and pull-down disabled #11 GPIOCTL1 RTC_GPIOCTL1 RTC GPIO Control 1 Register 0x108 read-write n 0x0 0x0 CTLSEL4 I/O Pin State Backup Selection\nWhen TAMP2EN is disabled, PF.8 pin (TAMPER2 pin) can be used as GPIO function. User can program CTLSEL4 to decide PF.8 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.\nPF.8 pin function and I/O status are controlled by OPMODE4[1:0] and DOUT4 after CTLSEL4 is set to 1.\nNote: CTLSEL4 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 3 1 read-write 0 PF.8 pin I/O function is controlled by GPIO module #0 1 PF.8 pin I/O function is controlled by VBAT power domain #1 CTLSEL5 I/O Pin State Backup Selection\nWhen TAMP3EN is disabled, PF.9 pin (TAMPER3 pin) can be used as GPIO function. User can program CTLSEL5 to decide PF.9 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.\nPF.9 pin function and I/O status are controlled by OPMODE5[1:0] and DOUT5 after CTLSEL5 is set to 1.\nNote: CTLSEL5 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 11 1 read-write 0 PF.9 pin I/O function is controlled by GPIO module #0 1 PF.9 pin I/O function is controlled by VBAT power domain #1 CTLSEL6 I/O Pin State Backup Selection\nWhen TAMP4EN is disabled, PF.10 pin (TAMPER4 pin) can be used as GPIO function. User can program CTLSEL6 to decide PF.10 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.\nPF.10 pin function and I/O status are controlled by OPMODE6[1:0] and DOUT6 after CTLSEL6 is set to 1.\nNote: CTLSEL6 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 19 1 read-write 0 PF.10 pin I/O function is controlled by GPIO module #0 1 PF.10 pin I/O function is controlled by VBAT power domain #1 CTLSEL7 I/O Pin State Backup Selection\nWhen TAMP5EN is disabled, PF.11 pin (TAMPER5 pin) can be used as GPIO function. User can program CTLSEL7 to decide PF.11 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.\nPF.11 pin function and I/O status are controlled by OPMODE7[1:0] and DOUT7 after CTLSEL7 is set to 1.\nNote: CTLSEL7 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 27 1 read-write 0 PF.11 pin I/O function is controlled by GPIO module #0 1 PF.11 pin I/O function is controlled by VBAT power domain #1 DOUT4 I/O Output Data 2 1 read-write 0 PF.8 output low #0 1 PF.8 output high #1 DOUT5 I/O Output Data 10 1 read-write 0 PF.9 output low #0 1 PF.9 output high #1 DOUT6 I/O Output Data 18 1 read-write 0 PF.10 output low #0 1 PF.10 output high #1 DOUT7 I/O Output Data 26 1 read-write 0 PF.11 output low #0 1 PF.11 output high #1 OPMODE4 I/O Operation Mode 0 2 read-write 0 PF.8 is input only mode #00 1 PF.8 is output push pull mode #01 2 PF.8 is open drain mode #10 3 PF.8 is quasi-bidirectional mode #11 OPMODE5 I/O Operation Mode 8 2 read-write 0 PF.9 is input only mode #00 1 PF.9 is output push pull mode #01 2 PF.9 is open drain mode #10 3 PF.9 is quasi-bidirectional mode #11 OPMODE6 I/O Operation Mode 16 2 read-write 0 PF.10 is input only mode #00 1 PF.10 is output push pull mode #01 2 PF.10 is open drain mode #10 3 PF.10 is quasi-bidirectional mode #11 OPMODE7 I/O Operation Mode 24 2 read-write 0 PF.11 is input only mode #00 1 PF.11 is output push pull mode #01 2 PF.11 is open drain mode #10 3 PF.11 is quasi-bidirectional mode #11 PUSEL4 I/O Pull-up and Pull-down \nDetermine PF.8 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE4 set as input tri-state and open-drain mode. 4 2 read-write 0 PF.8 pull-up and pull-down disabled #00 1 PF.8 pull-up enabled #01 2 PF.8 pull-down enabled #10 3 PF.8 pull-up and pull-down disabled #11 PUSEL5 I/O Pull-up and Pull-down Enable Bits\nDetermine PF.9 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE5 set as input tri-state and open-drain mode. 12 2 read-write 0 PF.9 pull-up and pull-down disabled #00 1 PF.9 pull-up enabled #01 2 PF.9 pull-down enabled #10 3 PF.9 pull-up and pull-down disabled #11 PUSEL6 I/O Pull-up and Pull-down Enable Bits\nDetermine PF.10 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE6 set as input tri-state and open-drain mode. 20 2 read-write 0 PF.10 pull-up and pull-down disabled #00 1 PF.10 pull-up enabled #01 2 PF.10 pull-down enabled #10 3 PF.10 pull-up and pull-down disabled #11 PUSEL7 I/O Pull-up and Pull-down Enable Bits\nDetermine PF.11 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE7 set as input tri-state and open-drain mode. 28 2 read-write 0 PF.11 pull-up and pull-down disabled #00 1 PF.11 pull-up enabled #01 2 PF.11 pull-down enabled #10 3 PF.11 pull-up and pull-down disabled #11 INIT RTC_INIT RTC Initiation Register 0x0 read-write n 0x0 0x0 INIT RTC Initiation\nWhen RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leave reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.\nThe INIT is a write-only field and read value will be always 0. 1 31 read-write INIT_ACTIVE RTC Active Status (Read Only) 0 1 read-only 0 RTC is at reset state #0 1 RTC is at normal active state #1 INTEN RTC_INTEN RTC Interrupt Enable Register 0x28 read-write n 0x0 0x0 ALMIEN Alarm Interrupt Enable Bit\nSet ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated. 0 1 read-write 0 RTC Alarm interrupt Disabled #0 1 RTC Alarm interrupt Enabled #1 CLKFIEN LXT Clock Frequency Monitor Fail Interrupt Enable Bit 24 1 read-write 0 LXT Frequency Stop interrupt Disabled #0 1 LXT Frequency Stop interrupt Enabled #1 CLKSTOPIEN LXT Clock Frequency Monitor STOP Interrupt Enable Bit 25 1 read-write 0 LXT Frequency Fail interrupt Disabled #0 1 LXT Frequency Fail interrupt Enabled #1 TAMP0IEN Tamper 0 Interrupt Enable Bit\nSet TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated. 8 1 read-write 0 Tamper 0 interrupt Disabled #0 1 Tamper 0 interrupt Enabled #1 TAMP1IEN Tamper 1 or Pair 0 Interrupt Enable Bit\nSet TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated. 9 1 read-write 0 Tamper 1 or Pair 0 interrupt Disabled #0 1 Tamper 1 or Pair 0 interrupt Enabled #1 TAMP2IEN Tamper 2 Interrupt Enable Bit\nSet TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated. 10 1 read-write 0 Tamper 2 interrupt Disabled #0 1 Tamper 2 interrupt Enabled #1 TAMP3IEN Tamper 3 or Pair 1 Interrupt Enable Bit\nSet TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated. 11 1 read-write 0 Tamper 3 or Pair 1 interrupt Disabled #0 1 Tamper 3 or Pair 1 interrupt Enabled #1 TAMP4IEN Tamper 4 Interrupt Enable Bit\nSet TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated. 12 1 read-write 0 Tamper 4 interrupt Disabled #0 1 Tamper 4 interrupt Enabled #1 TAMP5IEN Tamper 5 or Pair 2 Interrupt Enable Bit\nSet TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated. 13 1 read-write 0 Tamper 5 or Pair 2 interrupt Disabled #0 1 Tamper 5 or Pair 2 interrupt Enabled #1 TICKIEN Time Tick Interrupt Enable Bit\nSet TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated. 1 1 read-write 0 RTC Time Tick interrupt Disabled #0 1 RTC Time Tick interrupt Enabled #1 INTSTS RTC_INTSTS RTC Interrupt Status Register 0x2C read-write n 0x0 0x0 ALMIF RTC Alarm Interrupt Flag\nNote: Write 1 to clear this bit. 0 1 read-write 0 Alarm condition is not matched #0 1 Alarm condition is matched #1 CLKFIF LXT Clock Frequency Monitor Fail Interrupt Flag\nNote1: Write 1 to clear the bit to 0. 24 1 read-write 0 LXT frequency is normal #0 1 LXT frequency is abnormal #1 CLKSPIF LXT Clock Frequency Monitor STOP Interrupt Flag\nNote1: Write 1 to clear the bit to 0. 25 1 read-write 0 LXT frequency is normal #0 1 LXT frequency is almost stop . #1 TAMP0IF Tamper 0 Interrupt Flag\nThis bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]).\nNote1: Write 1 to clear this bit.\nNote2: This interrupt flag will generate again when Tamper setting condition is not restoration.\nNote3: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 8 1 read-write 0 No Tamper 0 interrupt flag is generated #0 1 Tamper 0 interrupt flag is generated #1 TAMP1IF Tamper 1 or Pair 0 Interrupt Flag\nThis bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated.\nNote1: Write 1 to clear this bit.\nNote2: This interrupt flag will generate again when Tamper setting condition is not restoration.\nNote3: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 9 1 read-write 0 No Tamper 1 or Pair 0 interrupt flag is generated #0 1 Tamper 1 or Pair 0 interrupt flag is generated #1 TAMP2IF Tamper 2 Interrupt Flag\nThis bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]).\nNote1: Write 1 to clear this bit.\nNote2: This interrupt flag will generate agan when Tamper setting condition is not restoration.\nNote3: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 10 1 read-write 0 No Tamper 2 interrupt flag is generated #0 1 Tamper 2 interrupt flag is generated #1 TAMP3IF Tamper 3 or Pair 1 Interrupt Flag\nThis bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated or TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated.\nNote1: Write 1 to clear this bit.\nNote2: This interrupt flag will generate again when Tamper setting condition is not restoration.\nNote3: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 11 1 read-write 0 No Tamper 3 or Pair 1 interrupt flag is generated #0 1 Tamper 3 or Pair 1 interrupt flag is generated #1 TAMP4IF Tamper 4 Interrupt Flag\nThis bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]).\nNote1: Write 1 to clear this bit.\nNote2: This interrupt flag will generate again when Tamper setting condition is not restoration.\nNote3: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 12 1 read-write 0 No Tamper 4 interrupt flag is generated #0 1 Tamper 4 interrupt flag is generated #1 TAMP5IF Tamper 5 or Pair 2 Interrupt Flag\nThis bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated or TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated.\nNote1: Write 1 to clear this bit.\nNote2: This interrupt flag will generate again when Tamper setting condition is not restoration.\nNote3: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 13 1 read-write 0 No Tamper 5 or Pair 2 interrupt flag is generated #0 1 Tamper 5 or Pair 2 interrupt flag is generated #1 TICKIF RTC Time Tick Interrupt Flag\nNote: Write 1 to clear this bit. 1 1 read-write 0 Tick condition did not occur #0 1 Tick condition occurred #1 LEAPYEAR RTC_LEAPYEAR RTC Leap Year Indicator Register 0x24 read-only n 0x0 0x0 LEAPYEAR Leap Year Indication (Read Only) 0 1 read-only 0 This year is not a leap year #0 1 This year is leap year #1 LXTCTL RTC_LXTCTL RTC 32.768 kHz Oscillator Control Register 0x100 -1 read-write n 0x0 0x0 C32KS Clock 32K Source Selection: 7 1 read-write 0 Internal 32K clock is from 32K crystal #0 1 Internal 32K clock is from LIRC32K #1 GAIN Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption. 1 2 read-write 0 L0 mode #00 1 L1 mode #01 2 L2 mode #10 3 L3 mode(Default) #11 LIRC32KEN Enable LIRC 32K Source 0 1 read-write 0 LIRC32K Disabled #0 1 LIRC32K Enabled #1 LVRDGSEL LVR Output De-glitch Time Select \nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 8 2 read-write 0 Without de-glitch function 000 1 31.25us 001 10 62.5us 010 11 Reserved 011 RTCLVDPD RTC Low Voltage Detector Power Down 13 1 read-write 0 RTC Low Voltage Detector active. #0 1 RTC Low Voltage Detector enter power down #1 RTCPORPD RTC Power on Reset Power Down\nNote:This bit only can be set to 1.. 14 1 read-write 0 RTC POR active 1sec after first power up #0 1 RTC POR enter power down #1 RWEN RTC_RWEN RTC Access Enable Register 0x4 -1 read-only n 0x0 0x0 RTCBUSY RTC Write Busy Flag\nThis bit indicates RTC registers are writable or not. RTC register R/W is invailid during RTCBUSY. 24 1 read-only 0 RTC registers are writable #0 1 RTC registers can't be written. RTC is under Busy Status #1 RWENF RTC Register Access Enable Flag (Read Only)\nNote: RWENF will be masked to 0 during RTCBUSY is 1. 16 1 read-only 0 RTC register read/write Disabled #0 1 RTC register read/write Enabled #1 SPR0 RTC_SPR0 RTC Spare Register 0 0x40 read-write n 0x0 0x0 SPARE Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register, user should check REWNF (RTC_RWEN[16]) is enabled. 0 32 read-write SPR1 RTC_SPR1 RTC Spare Register 1 0x44 read-write n 0x0 0x0 SPR10 RTC_SPR10 RTC Spare Register 10 0x68 read-write n 0x0 0x0 SPR11 RTC_SPR11 RTC Spare Register 11 0x6C read-write n 0x0 0x0 SPR12 RTC_SPR12 RTC Spare Register 12 0x70 read-write n 0x0 0x0 SPR13 RTC_SPR13 RTC Spare Register 13 0x74 read-write n 0x0 0x0 SPR14 RTC_SPR14 RTC Spare Register 14 0x78 read-write n 0x0 0x0 SPR15 RTC_SPR15 RTC Spare Register 15 0x7C read-write n 0x0 0x0 SPR16 RTC_SPR16 RTC Spare Register 16 0x80 read-write n 0x0 0x0 SPR17 RTC_SPR17 RTC Spare Register 17 0x84 read-write n 0x0 0x0 SPR18 RTC_SPR18 RTC Spare Register 18 0x88 read-write n 0x0 0x0 SPR19 RTC_SPR19 RTC Spare Register 19 0x8C read-write n 0x0 0x0 SPR2 RTC_SPR2 RTC Spare Register 2 0x48 read-write n 0x0 0x0 SPR3 RTC_SPR3 RTC Spare Register 3 0x4C read-write n 0x0 0x0 SPR4 RTC_SPR4 RTC Spare Register 4 0x50 read-write n 0x0 0x0 SPR5 RTC_SPR5 RTC Spare Register 5 0x54 read-write n 0x0 0x0 SPR6 RTC_SPR6 RTC Spare Register 6 0x58 read-write n 0x0 0x0 SPR7 RTC_SPR7 RTC Spare Register 7 0x5C read-write n 0x0 0x0 SPR8 RTC_SPR8 RTC Spare Register 8 0x60 read-write n 0x0 0x0 SPR9 RTC_SPR9 RTC Spare Register 9 0x64 read-write n 0x0 0x0 SPRCTL RTC_SPRCTL RTC Spare Functional Control Register 0x3C read-write n 0x0 0x0 LXTFCLR LXT Clock Fail/Stop to Clear Spare Enable Bit 16 1 read-write 0 LXT Fail/Stop to clear Spare register content is Disabled. #0 1 LXT Fail/Stop to clear Spare register content is Enabled #1 SPRCSTS SPR Clear Flag \nThis bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify tamper event is detected.\nNote1: Write 1 to clear this bit.\nNote2: This bit keeps 1 when RTC_INTSTS[13:8] is not equal to 0. 5 1 read-write 0 Spare register content is not cleared #0 1 Spare register content is cleared #1 SPRRWEN Spare Register Enable Bit\nNote: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed. 2 1 read-write 0 Spare register Disabled #0 1 Spare register Enabled #1 TALM RTC_TALM RTC Time Alarm Register 0x1C read-write n 0x0 0x0 HR 1-Hour Time Digit of Alarm Setting (0~9) 16 4 read-write HZCNT Index of sub-second counter(0x00 ~0x7F) 24 7 read-write MIN 1-Min Time Digit of Alarm Setting (0~9) 8 4 read-write SEC 1-Sec Time Digit of Alarm Setting (0~9) 0 4 read-write TENHR 10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) 20 2 read-write TENMIN 10-Min Time Digit of Alarm Setting (0~5) 12 3 read-write TENSEC 10-Sec Time Digit of Alarm Setting (0~5) 4 3 read-write TAMPCAL RTC_TAMPCAL RTC Tamper Calendar Register 0x134 read-only n 0x0 0x0 DAY 1-Day Calendar Digit of TAMPER Calendar (0~9) 0 4 read-only MON 1-Month Calendar Digit of TAMPER Calendar (0~9) 8 4 read-only TENDAY 10-Day Calendar Digit of TAMPER Calendar (0~3) 4 2 read-only TENMON 10-Month Calendar Digit of TAMPER Calendar (0~1) 12 1 read-only TENYEAR 10-Year Calendar Digit of TAMPER Calendar (0~9) 20 4 read-only YEAR 1-Year Calendar Digit of TAMPER Calendar (0~9) 16 4 read-only TAMPCTL RTC_TAMPCTL RTC Tamper Pin Control Register 0x120 read-write n 0x0 0x0 DYN1ISS Dynamic Pair 1 Input Source Select\nThis bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.\nNote: This bit is effective only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set 0 1 read-write 0 Tamper input is from Tamper 2 #0 1 Tamper input is from Tamper 0 #1 DYN2ISS Dynamic Pair 2 Input Source Select\nThis bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode.\nNote: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set 1 1 read-write 0 Tamper input is from Tamper 4 #0 1 Tamper input is from Tamper 0 #1 DYNPR0EN Dynamic Pair 0 Enable Bit 15 1 read-write 0 Static detect #0 1 Dynamic detect #1 DYNPR1EN Dynamic Pair 1 Enable Bit 23 1 read-write 0 Static detect #0 1 Dynamic detect #1 DYNPR2EN Dynamic Pair 2 Enable Bit 31 1 read-write 0 Static detect #0 1 Dynamic detect #1 DYNRATE Dynamic Change Rate\nThis item is choice the dynamic tamper output change rate.\nNote: After revising this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately. 5 3 read-write 0 210 * RTC_CLK #000 1 211 * RTC_CLK #001 2 212 * RTC_CLK #010 3 213 * RTC_CLK #011 4 214 * RTC_CLK #100 5 215 * RTC_CLK #101 6 216 * RTC_CLK #110 7 217 * RTC_CLK #111 DYNSRC Dynamic Reference Pattern\nThis fields determine the new reference pattern when current pattern run out in dynamic pair mode.\nNote: After this bit is modified, the SEEDRLD (RTC_TAMPCTL[4]) should be set. 2 2 read-write 1 The new reference pattern is repeated previous random value when the reference pattern run out #01 3 The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out #11 SEEDRLD Reload New Seed for PRNG Engine\nSetting this bit, the tamper configuration will be reload.\nNote: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed. 4 1 read-write 0 Generating key based on the current seed #0 1 Reload new seed #1 TAMP0DBEN Tamper 0 De-bounce Enable Bit 10 1 read-write 0 Tamper 0 de-bounce Disabled #0 1 Tamper 0 de-bounce Enabled, tamper detection pin will sync 1 RTC clock #1 TAMP0EN Tamper0 Detect Enable Bit\nNote1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.\nNote2: The tamper0 configuration should be setup before enable this bit. 8 1 read-write 0 Tamper 0 detect Disabled #0 1 Tamper 0 detect Enabled #1 TAMP0LV Tamper 0 Level\nThis bit depends on level attribute of tamper pin for static tamper detection. 9 1 read-write 0 Detect voltage level is low #0 1 Detect voltage level is high #1 TAMP1DBEN Tamper 1 De-bounce Enable Bit 14 1 read-write 0 Tamper 1 de-bounce Disabled #0 1 Tamper 1 de-bounce Enabled, tamper detection pin will sync 1 RTC clock #1 TAMP1EN Tamper 1 Detect Enable Bit\nNote1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.\nNote2: The tamper1 configuration should be setup before enable this bit. 12 1 read-write 0 Tamper 1 detect Disabled #0 1 Tamper 1 detect Enabled #1 TAMP1LV Tamper 1 Level\nThis bit depends on level attribute of tamper pin for static tamper detection. 13 1 read-write 0 Detect voltage level is low #0 1 Detect voltage level is high #1 TAMP2DBEN Tamper 2 De-bounce Enable Bit 18 1 read-write 0 Tamper 2 de-bounce Disabled #0 1 Tamper 2 de-bounce Enabled, tamper detection pin will sync 1 RTC clock #1 TAMP2EN Tamper 2 Detect Enable Bit\nNote1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.\nNote2: The tamper2 configuration should be setup before enable this bit. 16 1 read-write 0 Tamper 2 detect Disabled #0 1 Tamper 2 detect Enabled #1 TAMP2LV Tamper 2 Level\nThis bit depends on level attribute of tamper pin for static tamper detection. 17 1 read-write 0 Detect voltage level is low #0 1 Detect voltage level is high #1 TAMP3DBEN Tamper 3 De-bounce Enable Bit 22 1 read-write 0 Tamper 3 de-bounce Disabled #0 1 Tamper 3 de-bounce Enabled, tamper detection pin will sync 1 RTC clock #1 TAMP3EN Tamper 3 Detect Enable Bit\nNote1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.\nNote2: The tamper3 configuration should be setup before enable this bit. 20 1 read-write 0 Tamper 3 detect Disabled #0 1 Tamper 3 detect Enabled #1 TAMP3LV Tamper 3 Level\nThis bit depends on level attribute of tamper pin for static tamper detection. 21 1 read-write 0 Detect voltage level is low #0 1 Detect voltage level is high #1 TAMP4DBEN Tamper 4 De-bounce Enable Bit 26 1 read-write 0 Tamper 4 de-bounce Disabled #0 1 Tamper 4 de-bounce Enabled, tamper detection pin will sync 1 RTC clock #1 TAMP4EN Tamper4 Detect Enable Bit\nNote1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.\nNote2: The tamper4 configuration should be setup before enable this bit. 24 1 read-write 0 Tamper 4 detect Disabled #0 1 Tamper 4 detect Enabled #1 TAMP4LV Tamper 4 Level\nThis bit depends on level attribute of tamper pin for static tamper detection. 25 1 read-write 0 Detect voltage level is low #0 1 Detect voltage level is high #1 TAMP5DBEN Tamper 5 De-bounce Enable Bit 30 1 read-write 0 Tamper 5 de-bounce Disabled #0 1 Tamper 5 de-bounce Enabled, tamper detection pin will sync 1 RTC clock #1 TAMP5EN Tamper 5 Detect Enable Bit\nNote1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.\nNote2: The tamper5 configuration should be setup before enable this bit. 28 1 read-write 0 Tamper 5 detect Disabled #0 1 Tamper 5 detect Enabled #1 TAMP5LV Tamper 5 Level\nThis bit depends on level attribute of tamper pin for static tamper detection. 29 1 read-write 0 Detect voltage level is low #0 1 Detect voltage level is high #1 TAMPSEED RTC_TAMPSEED RTC Tamper Dynamic Seed Register 0x128 read-write n 0x0 0x0 SEED Seed Value 0 32 read-write TAMPTIME RTC_TAMPTIME RTC Tamper Time Register 0x130 read-only n 0x0 0x0 HR 1-Hour Time Digit of TAMPER Time (0~9) 16 4 read-only HZCNT Index of sub-second counter(0x00 ~0x7F) 24 7 read-only MIN 1-Min Time Digit of TAMPER Time (0~9) 8 4 read-only SEC 1-Sec Time Digit of TAMPER Time (0~9) 0 4 read-only TENHR 10-Hour Time Digit of TAMPER Time (0~2)Note: 24-hour time scale only . 20 2 read-only TENMIN 10-Min Time Digit of TAMPER Time (0~5) 12 3 read-only TENSEC 10-Sec Time Digit of TAMPER Time (0~5) 4 3 read-only TAMSK RTC_TAMSK RTC Time Alarm Mask Register 0x34 read-write n 0x0 0x0 MHR Mask 1-Hour Time Digit of Alarm Setting (0~9) 4 1 read-write MMIN Mask 1-Min Time Digit of Alarm Setting (0~9) 2 1 read-write MSEC Mask 1-Sec Time Digit of Alarm Setting (0~9) 0 1 read-write MTENHR Mask 10-Hour Time Digit of Alarm Setting (0~2) 5 1 read-write MTENMIN Mask 10-Min Time Digit of Alarm Setting (0~5) 3 1 read-write MTENSEC Mask 10-Sec Time Digit of Alarm Setting (0~5) 1 1 read-write TICK RTC_TICK RTC Time Tick Register 0x30 read-write n 0x0 0x0 TICK Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. \nNote: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active. 0 3 read-write 0 Time tick is 1 second #000 1 Time tick is 1/2 second #001 2 Time tick is 1/4 second #010 3 Time tick is 1/8 second #011 4 Time tick is 1/16 second #100 5 Time tick is 1/32 second #101 6 Time tick is 1/64 second #110 7 Time tick is 1/128 second #111 TIME RTC_TIME RTC Time Loading Register 0xC read-write n 0x0 0x0 HR 1-Hour Time Digit (0~9) 16 4 read-write HZCNT Index of sub-second counter(0x00 ~0x7F) 24 7 read-write MIN 1-Min Time Digit (0~9) 8 4 read-write SEC 1-Sec Time Digit (0~9) 0 4 read-write TENHR 10-Hour Time Digit (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) 20 2 read-write TENMIN 10-Min Time Digit (0~5) 12 3 read-write TENSEC 10-Sec Time Digit (0~5) 4 3 read-write WEEKDAY RTC_WEEKDAY RTC Day of the Week Register 0x18 -1 read-write n 0x0 0x0 WEEKDAY Day of the Week Register 0 3 read-write 0 Sunday #000 1 Monday #001 2 Tuesday #010 3 Wednesday #011 4 Thursday #100 5 Friday #101 6 Saturday #110 7 Reserved #111 SC0 SC Register Map SC 0x0 0x0 0x38 registers n 0x4C 0x4 registers n SC_ACTCTL SC_ACTCTL SC Activation Control Register 0x4C read-write n 0x0 0x0 T1EXT T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nThe cycle scaling factor is 2048.\nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3 0 5 read-write SC_ALTCTL SC_ALTCTL SC Alternate Control Register 0x8 read-write n 0x0 0x0 ACTEN Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]). Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.\nNote4: During the activation sequence, RX is disabled automatically and can not receive data. After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation. 3 1 read-write 0 No effect #0 1 Activation sequence generator Enabled #1 ACTSTS0 Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]). 13 1 read-only 0 Timer0 is not active #0 1 Timer0 is active #1 ACTSTS1 Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]). 14 1 read-only 0 Timer1 is not active #0 1 Timer1 is active #1 ACTSTS2 Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]). 15 1 read-only 0 Timer2 is not active #0 1 Timer2 is active #1 ADACEN Auto Deactivation When Card Removal\nThis bit is used for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set. If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also. 11 1 read-write 0 Auto deactivation Disabled #0 1 Auto deactivation Enabled #1 CNTEN0 Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 5 1 read-write 0 Stops counting #0 1 Start counting #1 CNTEN1 Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 6 1 read-write 0 Stops counting #0 1 Start counting #1 CNTEN2 Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 7 1 read-write 0 Stops counting #0 1 Start counting #1 DACTEN Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]). Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 2 1 read-write 0 No effect #0 1 Deactivation sequence generator Enabled #1 INITSEL Initial Timing Selection\nThis fields indicates the initial timing of hardware activation, warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Figure 6.174\nWarm-reset: refer to Warm-Reset Sequence in Figure 6.175.\nDeactivation: refer to Deactivation Sequence in Figure 6.176.\nNote: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles. 8 2 read-write RXBGTEN Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function. 12 1 read-write 0 Receiver block guard time function Disabled #0 1 Receiver block guard time function Enabled #1 RXRST Rx Software Reset\nWhen RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 1 1 read-write 0 No effect #0 1 Reset the Rx internal state machine and pointers #1 SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SCn_ALTCTL register #0 1 Last value is synchronizing #1 TXRST TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 0 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 WARSTEN Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]). Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.\nNote4: During the warm reset sequence, RX is disabled automatically and can not receive data. After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence. 4 1 read-write 0 No effect #0 1 Warm reset sequence generator Enabled #1 SC_CTL SC_CTL SC Control Register 0x4 read-write n 0x0 0x0 AUTOCEN Auto Convention Enable Bit\nThis bit is used for enable auto convention function.\nIf user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F. After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F. If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11.\nIf the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled. 3 1 read-write 0 Auto-convention Disabled #0 1 Auto-convention Enabled #1 BGT Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1. 8 5 read-write CDDBSEL Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved. 24 2 read-write 0 De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks #00 CDLV Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled. 26 1 read-write 0 When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected #0 1 When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected #1 CONSEL Convention Selection\nNote: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. 4 2 read-write 0 Direct convention #00 1 Reserved #01 2 Reserved #10 3 Inverse convention #11 NSB Stop Bit Length\nThis field indicates the length of stop bit.\nNote1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. \nNote2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. 15 1 read-write 0 The stop bit length is 2 ETU #0 1 The stop bit length is 1 ETU #1 RXOFF RX Transition Disable Control Bit\nThis bit is used for disable Rx transition function.\nNote: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. 1 1 read-write 0 The receiver Enabled #0 1 The receiver Disabled #1 RXRTY RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RXRTYEN enabled. The change flow is to disable RXRTYEN first and then fill in new retry value. 16 3 read-write RXRTYEN RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit. 19 1 read-write 0 RX error retry function Disabled #0 1 RX error retry function Enabled #1 RXTRGLV Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set. If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU. 6 2 read-write 0 Rx Buffer Trigger Level with 01 bytes #00 1 Rx Buffer Trigger Level with 02 bytes #01 2 Rx Buffer Trigger Level with 03 bytes #10 3 Reserved #11 SCEN SC Controller Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, \nNote: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. 0 1 read-write 0 SC will force all transition to IDLE state #0 1 SC controller is enabled and all function can work correctly #1 SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. 30 1 read-only 0 Synchronizing is completion, user can write new data to RXRTY and TXRTY #0 1 Last value is synchronizing #1 TMRSEL Timer Channel Selection \nOther configurations are reserved 13 2 read-write 0 All internal timer function Disabled #00 3 Internal 24 bit timer and two 8 bit timers Enabled. User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0] #11 TXOFF TX Transition Disable Control Bit\nThis bit is used for disable Tx transition function. 2 1 read-write 0 The transceiver Enabled #0 1 The transceiver Disabled #1 TXRTY TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TXRTYEN first and then fill in new retry value. 20 3 read-write TXRTYEN TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred. 23 1 read-write 0 TX error retry function Disabled #0 1 TX error retry function Enabled #1 SC_DAT SC_DAT SC Receive/Transmit Holding Buffer Register 0x0 read-write n 0x0 0x0 DAT Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data. 0 8 read-write SC_EGT SC_EGT SC Extra Guard Time Register 0xC read-write n 0x0 0x0 EGT Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base. 0 8 read-write SC_ETUCTL SC_ETUCTL SC Element Time Unit Control Register 0x14 -1 read-write n 0x0 0x0 ETURDIV ETU Rate Divider\nThe field is used for ETU clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: User can configure this field, but this field must be greater than 0x04. 0 12 read-write SC_INTEN SC_INTEN SC Interrupt Enable Control Register 0x18 read-write n 0x0 0x0 ACERRIEN Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt. 10 1 read-write 0 Auto-convention error interrupt Disabled #0 1 Auto-convention error interrupt Enabled #1 BGTIEN Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time. 6 1 read-write 0 Block guard time interrupt Disabled #0 1 Block guard time interrupt Enabled #1 CDIEN Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt. The card detect status is CDPINSTS (SCn_STATUS[13]). 7 1 read-write 0 Card detect interrupt Disabled #0 1 Card detect interrupt Enabled #1 INITIEN Initial End Interrupt Enable Bit 8 1 read-write 0 Initial end interrupt Disabled #0 1 Initial end interrupt Enabled #1 RDAIEN Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt. 0 1 read-write 0 Receive data reach trigger level interrupt Disabled #0 1 Receive data reach trigger level interrupt Enabled #1 RXTOIEN Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt. 9 1 read-write 0 Receiver buffer time-out interrupt Disabled #0 1 Receiver buffer time-out interrupt Enabled #1 TBEIEN Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt. 1 1 read-write 0 Transmit buffer empty interrupt Disabled #0 1 Transmit buffer empty interrupt Enabled #1 TERRIEN Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]). 2 1 read-write 0 Transfer error interrupt Disabled #0 1 Transfer error interrupt Enabled #1 TMR0IEN Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function. 3 1 read-write 0 Timer0 interrupt Disabled #0 1 Timer0 interrupt Enabled #1 TMR1IEN Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function. 4 1 read-write 0 Timer1 interrupt Disabled #0 1 Timer1 interrupt Enabled #1 TMR2IEN Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function. 5 1 read-write 0 Timer2 interrupt Disabled #0 1 Timer2 interrupt Enabled #1 SC_INTSTS SC_INTSTS SC Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ACERRIF Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it. 10 1 read-write 0 Received TS at ATR state is 0x3B or 0x3F #0 1 Received TS at ATR state is neither 0x3B nor 0x3F #1 BGTIF Block Guard Time Interrupt Status Flag\nThis field is used for indicate block guard time interrupt status flag in receive direction.\nNote1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.\nNote2: This bit can be cleared by writing 1 to it. 6 1 read-write 0 Block guard time interrupt did not occur #0 1 Block guard time interrupt occurred #1 CDIF Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).\nNote: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it. 7 1 read-only 0 Card detect event did not occur #0 1 Card detect event occurred #1 INITIF Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 8 1 read-write 0 Initial sequence is not complete #0 1 Initial sequence is completed #1 RDAIF Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.\nNote: This bit is read only. If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically. 0 1 read-only 0 Number of receive buffer is less than RXTRGLV setting #0 1 Number of receive buffer data equals the RXTRGLV setting #1 RXTOIF Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it. 9 1 read-only 0 Receive buffer time-out interrupt did not occur #0 1 Receive buffer time-out interrupt occurred #1 TBEIF Transmit Buffer Empty Interrupt Status Flag (Read Only) This field is used for transmit buffer empty interrupt status flag. Note: This bit is read only. If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically. 1 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 TERRIF Transfer Error Interrupt Status Flag\nThis field is used for transfer error interrupt status flag. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]).\nNote1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.\nNote2: This bit can be cleared by writing 1 to it. 2 1 read-write 0 Transfer error interrupt did not occur #0 1 Transfer error interrupt occurred #1 TMR0IF Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 3 1 read-write 0 Timer0 interrupt did not occur #0 1 Timer0 interrupt occurred #1 TMR1IF Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 4 1 read-write 0 Timer1 interrupt did not occur #0 1 Timer1 interrupt occurred #1 TMR2IF Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 5 1 read-write 0 Timer2 interrupt did not occur #0 1 Timer2 interrupt occurred #1 SC_PINCTL SC_PINCTL SC Pin Control State Register 0x24 read-write n 0x0 0x0 CLKKEEP SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. 6 1 read-write 0 SC clock generation Disabled #0 1 SC clock always keeps free running #1 DATASTS SCn_DATA Pin Status (Read Only)\nThis bit is the pin status of SCn_DATA. 16 1 read-only 0 The SCn_DATA pin status is low #0 1 The SCn_DATA pin status is high #1 PWREN SCn_PWR Pin Signal\nUser can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.\nWrite this field to drive SCn_PWR pin\nRefer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. \nRead this field to get SCn_PWR signal status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. 0 1 read-write 0 SCn_PWR signal status is low #0 1 SCn_PWR signal status is high #1 PWRINV SCn_PWR Pin Inverse\nThis bit is used for inverse the SCn_PWR pin.\nThere are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). \nPWRINV (SCn_PINCTL[11]) is bit 1 and PWREN (SCn_PINCTL[0]) is bit 0 and all conditions as below list, \nNote: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]). 11 1 read-write 0 SCn_PWR pin is 0 00 1 SCn_PWR pin is 1 01 10 SCn_PWR pin is 1 10 11 SCn_PWR pin is 0 11 PWRSTS SCn_PWR Pin Status (Read Only)\nThis bit is the pin status of SCn_PWR. 17 1 read-only 0 SCn_PWR pin to low #0 1 SCn_PWR pin to high #1 RSTEN SCn_RST Pin Signal\nUser can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.\nWrite this field to drive SCn_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. 1 1 read-write 0 Drive SCn_RST pin to low.\nSCn_RST signal status is low #0 1 Drive SCn_RST pin to high.\nSCn_RST signal status is high #1 RSTSTS SCn_RST Pin Status (Read Only)\nThis bit is the pin status of SCn_RST. 18 1 read-only 0 SCn_RST pin is low #0 1 SCn_RST pin is high #1 SCDATA SCn_DATA Pin Signal \nThis bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when SC is in these modes. 9 1 read-write 0 Drive SCn_DATA pin to low.\nSCn_DATA signal status is low #0 1 Drive SCn_DATA pin to high.\nSCn_DATA signal status is high #1 SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SCn_PINCTL register. 30 1 read-only 0 Synchronizing is completion, user can write new data to SCn_PINCTL register #0 1 Last value is synchronizing #1 SC_RXTOUT SC_RXTOUT SC Receive Buffer Time-out Counter Register 0x10 read-write n 0x0 0x0 RFTM SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the RX buffer received a new data. Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled.\nNote1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.\nNote2: Filling in all 0 to this field indicates to disable this function. 0 9 read-write SC_STATUS SC_STATUS SC Transfer Status Register 0x20 -1 read-write n 0x0 0x0 BEF Receiver Break Error Status Flag This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of 'start bit' + 'data bits' + 'parity bit' + 'stop bits'). Note1: This bit can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 6 1 read-write 0 Receiver break error flag did not occur #0 1 Receiver break error flag occurred #1 CDPINSTS Card Detect Pin Status (Read Only)\nThis bit is the pin status of SCn_CD. 13 1 read-only 0 The SCn_CD pin state at low #0 1 The SCn_CD pin state at high #1 CINSERT Card Insert Status of SCn_CD Pin\nThis bit is set whenever card has been inserted.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: The card detect function will start after SCEN (SCn_CTL[0]) set. 12 1 read-write 0 No effect #0 1 Card insert #1 CREMOVE Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: Card detect function will start after SCEN (SCn_CTL[0]) set. 11 1 read-write 0 No effect #0 1 Card removed #1 FEF Receiver Frame Error Status Flag This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note1: This bit can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 5 1 read-write 0 Receiver frame error flag did not occur #0 1 Receiver frame error flag occurred #1 PEF Receiver Parity Error Status Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note1: This bit can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 4 1 read-write 0 Receiver parity error flag did not occur #0 1 Receiver parity error flag occurred #1 RXACT Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status. 23 1 read-only 0 This bit is cleared automatically when Rx transfer is finished #0 1 This bit is set by hardware when Rx transfer is in active #1 RXEMPTY Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer empty or not. 1 1 read-only 0 Rx buffer is not empty #0 1 Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU #1 RXFULL Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer full or not. 2 1 read-only 0 Rx buffer count is less than 4 #0 1 Rx buffer count equals to 4 #1 RXOV Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it. 0 1 read-write 0 Rx buffer is not overflow #0 1 Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes) #1 RXOVERR Receiver over Retry Error\nThis bit is used for receiver retry counts over than retry number limitation.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 22 1 read-write 0 Receiver retries counts is less than RXRTY (SCn_CTL[18:16]) + 1 #0 1 Receiver retries counts is equal or over than RXRTY (SCn_CTL[18:16]) + 1 #1 RXPOINT Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status. When SC controller receives one byte from external device, RXPOINT increases one. When one byte of Rx buffer is read by CPU, RXPOINT decreases one. 16 3 read-only RXRERR Receiver Retry Error\nThis bit is used for receiver error retry and set by hardware.\nNote1: This bit can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 21 1 read-write 0 No Rx retry transfer #0 1 Rx has any error and retries transfer #1 TXACT Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status. 31 1 read-only 0 This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed #0 1 Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP bit of the last byte has not been transmitted #1 TXEMPTY Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nNote: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]). 9 1 read-only 0 Tx buffer is not empty #0 1 Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register #1 TXFULL Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer full or not. 10 1 read-only 0 Tx buffer count is less than 4 #0 1 Tx buffer count equals to 4 #1 TXOV Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow. \nNote: This bit can be cleared by writing 1 to it. 8 1 read-write 0 Tx buffer is not overflow #0 1 Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]) #1 TXOVERR Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it. 30 1 read-write 0 Transmitter retries counts is less than TXRTY (SCn_CTL[22:20]) + 1 #0 1 Transmitter retries counts is equal or over to TXRTY (SCn_CTL[22:20]) + 1 #1 TXPOINT Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status. When CPU writes data into SCn_DAT, TXPOINT increases one. When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one. 24 3 read-only TXRERR Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware..\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt to CPU. 29 1 read-write 0 No Tx retry transfer #0 1 Tx has any error and retries transfer #1 SC_TMRCTL0 SC_TMRCTL0 SC Internal Timer0 Control Register 0x28 read-write n 0x0 0x0 CNT Timer0 Counter Value\nThis field indicates the internal Timer0 counter values.\nNote: Unit of Timer0 counter is ETU base. 0 24 read-write OPMODE Timer0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Table 6.173 for programming Timer0. 24 4 read-write SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SCn_TMRCTL0 register #0 1 Last value is synchronizing #1 SC_TMRCTL1 SC_TMRCTL1 SC Internal Timer1 Control Register 0x2C read-write n 0x0 0x0 CNT Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values. \nNote: Unit of Timer1 counter is ETU base. 0 8 read-write OPMODE Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Table 6.173 for programming Timer1. 24 4 read-write SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SCn_TMRCTL1 register #0 1 Last value is synchronizing #1 SC_TMRCTL2 SC_TMRCTL2 SC Internal Timer2 Control Register 0x30 read-write n 0x0 0x0 CNT Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values. \nNote: Unit of Timer2 counter is ETU base. 0 8 read-write OPMODE Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Table 6.173 for programming Timer2. 24 4 read-write SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SCn_TMRCTL2 register #0 1 Last value is synchronizing #1 SC_UARTCTL SC_UARTCTL SC UART Mode Control Register 0x34 read-write n 0x0 0x0 OPE Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0. 7 1 read-write 0 Even number of logic 1 are transmitted or check the data word and parity bits in receiving mode #0 1 Odd number of logic 1 are transmitted or check the data word and parity bits in receiving mode #1 PBOFF Parity Bit Disable Bit\nSets this bit is used for disable parity check function.\nNote: In smart card mode, this field must be 0 (default setting is with parity bit). 6 1 read-write 0 Parity bit is generated or checked between the 'last data word bit' and 'stop bit' of the serial data #0 1 Parity bit is not generated (transmitting data) or checked (receiving data) during transfer #1 UARTEN UART Mode Enable Bit\nSets this bit to enable UART mode function.\nNote3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine. 0 1 read-write 0 Smart Card mode #0 1 UART mode #1 WLS Word Length Selection\nThis field is used for select UART data length.\nNote: In smart card mode, this WLS must be 00. 4 2 read-write 0 Word length is 8 bits #00 1 Word length is 7 bits #01 2 Word length is 6 bits #10 3 Word length is 5 bits #11 SC1 SC Register Map SC 0x0 0x0 0x38 registers n 0x4C 0x4 registers n SC_ACTCTL SC_ACTCTL SC Activation Control Register 0x4C read-write n 0x0 0x0 T1EXT T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nThe cycle scaling factor is 2048.\nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3 0 5 read-write SC_ALTCTL SC_ALTCTL SC Alternate Control Register 0x8 read-write n 0x0 0x0 ACTEN Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]). Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.\nNote4: During the activation sequence, RX is disabled automatically and can not receive data. After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation. 3 1 read-write 0 No effect #0 1 Activation sequence generator Enabled #1 ACTSTS0 Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]). 13 1 read-only 0 Timer0 is not active #0 1 Timer0 is active #1 ACTSTS1 Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]). 14 1 read-only 0 Timer1 is not active #0 1 Timer1 is active #1 ACTSTS2 Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]). 15 1 read-only 0 Timer2 is not active #0 1 Timer2 is active #1 ADACEN Auto Deactivation When Card Removal\nThis bit is used for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set. If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also. 11 1 read-write 0 Auto deactivation Disabled #0 1 Auto deactivation Enabled #1 CNTEN0 Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 5 1 read-write 0 Stops counting #0 1 Start counting #1 CNTEN1 Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 6 1 read-write 0 Stops counting #0 1 Start counting #1 CNTEN2 Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 7 1 read-write 0 Stops counting #0 1 Start counting #1 DACTEN Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]). Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 2 1 read-write 0 No effect #0 1 Deactivation sequence generator Enabled #1 INITSEL Initial Timing Selection\nThis fields indicates the initial timing of hardware activation, warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Figure 6.174\nWarm-reset: refer to Warm-Reset Sequence in Figure 6.175.\nDeactivation: refer to Deactivation Sequence in Figure 6.176.\nNote: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles. 8 2 read-write RXBGTEN Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function. 12 1 read-write 0 Receiver block guard time function Disabled #0 1 Receiver block guard time function Enabled #1 RXRST Rx Software Reset\nWhen RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 1 1 read-write 0 No effect #0 1 Reset the Rx internal state machine and pointers #1 SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SCn_ALTCTL register #0 1 Last value is synchronizing #1 TXRST TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 0 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 WARSTEN Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]). Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.\nNote4: During the warm reset sequence, RX is disabled automatically and can not receive data. After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence. 4 1 read-write 0 No effect #0 1 Warm reset sequence generator Enabled #1 SC_CTL SC_CTL SC Control Register 0x4 read-write n 0x0 0x0 AUTOCEN Auto Convention Enable Bit\nThis bit is used for enable auto convention function.\nIf user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F. After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F. If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11.\nIf the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled. 3 1 read-write 0 Auto-convention Disabled #0 1 Auto-convention Enabled #1 BGT Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1. 8 5 read-write CDDBSEL Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved. 24 2 read-write 0 De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks #00 CDLV Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled. 26 1 read-write 0 When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected #0 1 When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected #1 CONSEL Convention Selection\nNote: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. 4 2 read-write 0 Direct convention #00 1 Reserved #01 2 Reserved #10 3 Inverse convention #11 NSB Stop Bit Length\nThis field indicates the length of stop bit.\nNote1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. \nNote2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. 15 1 read-write 0 The stop bit length is 2 ETU #0 1 The stop bit length is 1 ETU #1 RXOFF RX Transition Disable Control Bit\nThis bit is used for disable Rx transition function.\nNote: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. 1 1 read-write 0 The receiver Enabled #0 1 The receiver Disabled #1 RXRTY RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RXRTYEN enabled. The change flow is to disable RXRTYEN first and then fill in new retry value. 16 3 read-write RXRTYEN RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit. 19 1 read-write 0 RX error retry function Disabled #0 1 RX error retry function Enabled #1 RXTRGLV Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set. If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU. 6 2 read-write 0 Rx Buffer Trigger Level with 01 bytes #00 1 Rx Buffer Trigger Level with 02 bytes #01 2 Rx Buffer Trigger Level with 03 bytes #10 3 Reserved #11 SCEN SC Controller Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, \nNote: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. 0 1 read-write 0 SC will force all transition to IDLE state #0 1 SC controller is enabled and all function can work correctly #1 SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. 30 1 read-only 0 Synchronizing is completion, user can write new data to RXRTY and TXRTY #0 1 Last value is synchronizing #1 TMRSEL Timer Channel Selection \nOther configurations are reserved 13 2 read-write 0 All internal timer function Disabled #00 3 Internal 24 bit timer and two 8 bit timers Enabled. User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0] #11 TXOFF TX Transition Disable Control Bit\nThis bit is used for disable Tx transition function. 2 1 read-write 0 The transceiver Enabled #0 1 The transceiver Disabled #1 TXRTY TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TXRTYEN first and then fill in new retry value. 20 3 read-write TXRTYEN TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred. 23 1 read-write 0 TX error retry function Disabled #0 1 TX error retry function Enabled #1 SC_DAT SC_DAT SC Receive/Transmit Holding Buffer Register 0x0 read-write n 0x0 0x0 DAT Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data. 0 8 read-write SC_EGT SC_EGT SC Extra Guard Time Register 0xC read-write n 0x0 0x0 EGT Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base. 0 8 read-write SC_ETUCTL SC_ETUCTL SC Element Time Unit Control Register 0x14 -1 read-write n 0x0 0x0 ETURDIV ETU Rate Divider\nThe field is used for ETU clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: User can configure this field, but this field must be greater than 0x04. 0 12 read-write SC_INTEN SC_INTEN SC Interrupt Enable Control Register 0x18 read-write n 0x0 0x0 ACERRIEN Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt. 10 1 read-write 0 Auto-convention error interrupt Disabled #0 1 Auto-convention error interrupt Enabled #1 BGTIEN Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time. 6 1 read-write 0 Block guard time interrupt Disabled #0 1 Block guard time interrupt Enabled #1 CDIEN Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt. The card detect status is CDPINSTS (SCn_STATUS[13]). 7 1 read-write 0 Card detect interrupt Disabled #0 1 Card detect interrupt Enabled #1 INITIEN Initial End Interrupt Enable Bit 8 1 read-write 0 Initial end interrupt Disabled #0 1 Initial end interrupt Enabled #1 RDAIEN Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt. 0 1 read-write 0 Receive data reach trigger level interrupt Disabled #0 1 Receive data reach trigger level interrupt Enabled #1 RXTOIEN Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt. 9 1 read-write 0 Receiver buffer time-out interrupt Disabled #0 1 Receiver buffer time-out interrupt Enabled #1 TBEIEN Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt. 1 1 read-write 0 Transmit buffer empty interrupt Disabled #0 1 Transmit buffer empty interrupt Enabled #1 TERRIEN Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]). 2 1 read-write 0 Transfer error interrupt Disabled #0 1 Transfer error interrupt Enabled #1 TMR0IEN Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function. 3 1 read-write 0 Timer0 interrupt Disabled #0 1 Timer0 interrupt Enabled #1 TMR1IEN Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function. 4 1 read-write 0 Timer1 interrupt Disabled #0 1 Timer1 interrupt Enabled #1 TMR2IEN Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function. 5 1 read-write 0 Timer2 interrupt Disabled #0 1 Timer2 interrupt Enabled #1 SC_INTSTS SC_INTSTS SC Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ACERRIF Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it. 10 1 read-write 0 Received TS at ATR state is 0x3B or 0x3F #0 1 Received TS at ATR state is neither 0x3B nor 0x3F #1 BGTIF Block Guard Time Interrupt Status Flag\nThis field is used for indicate block guard time interrupt status flag in receive direction.\nNote1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.\nNote2: This bit can be cleared by writing 1 to it. 6 1 read-write 0 Block guard time interrupt did not occur #0 1 Block guard time interrupt occurred #1 CDIF Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).\nNote: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it. 7 1 read-only 0 Card detect event did not occur #0 1 Card detect event occurred #1 INITIF Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 8 1 read-write 0 Initial sequence is not complete #0 1 Initial sequence is completed #1 RDAIF Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.\nNote: This bit is read only. If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically. 0 1 read-only 0 Number of receive buffer is less than RXTRGLV setting #0 1 Number of receive buffer data equals the RXTRGLV setting #1 RXTOIF Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it. 9 1 read-only 0 Receive buffer time-out interrupt did not occur #0 1 Receive buffer time-out interrupt occurred #1 TBEIF Transmit Buffer Empty Interrupt Status Flag (Read Only) This field is used for transmit buffer empty interrupt status flag. Note: This bit is read only. If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically. 1 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 TERRIF Transfer Error Interrupt Status Flag\nThis field is used for transfer error interrupt status flag. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]).\nNote1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.\nNote2: This bit can be cleared by writing 1 to it. 2 1 read-write 0 Transfer error interrupt did not occur #0 1 Transfer error interrupt occurred #1 TMR0IF Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 3 1 read-write 0 Timer0 interrupt did not occur #0 1 Timer0 interrupt occurred #1 TMR1IF Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 4 1 read-write 0 Timer1 interrupt did not occur #0 1 Timer1 interrupt occurred #1 TMR2IF Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 5 1 read-write 0 Timer2 interrupt did not occur #0 1 Timer2 interrupt occurred #1 SC_PINCTL SC_PINCTL SC Pin Control State Register 0x24 read-write n 0x0 0x0 CLKKEEP SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. 6 1 read-write 0 SC clock generation Disabled #0 1 SC clock always keeps free running #1 DATASTS SCn_DATA Pin Status (Read Only)\nThis bit is the pin status of SCn_DATA. 16 1 read-only 0 The SCn_DATA pin status is low #0 1 The SCn_DATA pin status is high #1 PWREN SCn_PWR Pin Signal\nUser can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.\nWrite this field to drive SCn_PWR pin\nRefer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. \nRead this field to get SCn_PWR signal status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. 0 1 read-write 0 SCn_PWR signal status is low #0 1 SCn_PWR signal status is high #1 PWRINV SCn_PWR Pin Inverse\nThis bit is used for inverse the SCn_PWR pin.\nThere are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). \nPWRINV (SCn_PINCTL[11]) is bit 1 and PWREN (SCn_PINCTL[0]) is bit 0 and all conditions as below list, \nNote: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]). 11 1 read-write 0 SCn_PWR pin is 0 00 1 SCn_PWR pin is 1 01 10 SCn_PWR pin is 1 10 11 SCn_PWR pin is 0 11 PWRSTS SCn_PWR Pin Status (Read Only)\nThis bit is the pin status of SCn_PWR. 17 1 read-only 0 SCn_PWR pin to low #0 1 SCn_PWR pin to high #1 RSTEN SCn_RST Pin Signal\nUser can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.\nWrite this field to drive SCn_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. 1 1 read-write 0 Drive SCn_RST pin to low.\nSCn_RST signal status is low #0 1 Drive SCn_RST pin to high.\nSCn_RST signal status is high #1 RSTSTS SCn_RST Pin Status (Read Only)\nThis bit is the pin status of SCn_RST. 18 1 read-only 0 SCn_RST pin is low #0 1 SCn_RST pin is high #1 SCDATA SCn_DATA Pin Signal \nThis bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when SC is in these modes. 9 1 read-write 0 Drive SCn_DATA pin to low.\nSCn_DATA signal status is low #0 1 Drive SCn_DATA pin to high.\nSCn_DATA signal status is high #1 SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SCn_PINCTL register. 30 1 read-only 0 Synchronizing is completion, user can write new data to SCn_PINCTL register #0 1 Last value is synchronizing #1 SC_RXTOUT SC_RXTOUT SC Receive Buffer Time-out Counter Register 0x10 read-write n 0x0 0x0 RFTM SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the RX buffer received a new data. Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled.\nNote1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.\nNote2: Filling in all 0 to this field indicates to disable this function. 0 9 read-write SC_STATUS SC_STATUS SC Transfer Status Register 0x20 -1 read-write n 0x0 0x0 BEF Receiver Break Error Status Flag This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of 'start bit' + 'data bits' + 'parity bit' + 'stop bits'). Note1: This bit can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 6 1 read-write 0 Receiver break error flag did not occur #0 1 Receiver break error flag occurred #1 CDPINSTS Card Detect Pin Status (Read Only)\nThis bit is the pin status of SCn_CD. 13 1 read-only 0 The SCn_CD pin state at low #0 1 The SCn_CD pin state at high #1 CINSERT Card Insert Status of SCn_CD Pin\nThis bit is set whenever card has been inserted.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: The card detect function will start after SCEN (SCn_CTL[0]) set. 12 1 read-write 0 No effect #0 1 Card insert #1 CREMOVE Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: Card detect function will start after SCEN (SCn_CTL[0]) set. 11 1 read-write 0 No effect #0 1 Card removed #1 FEF Receiver Frame Error Status Flag This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note1: This bit can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 5 1 read-write 0 Receiver frame error flag did not occur #0 1 Receiver frame error flag occurred #1 PEF Receiver Parity Error Status Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note1: This bit can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 4 1 read-write 0 Receiver parity error flag did not occur #0 1 Receiver parity error flag occurred #1 RXACT Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status. 23 1 read-only 0 This bit is cleared automatically when Rx transfer is finished #0 1 This bit is set by hardware when Rx transfer is in active #1 RXEMPTY Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer empty or not. 1 1 read-only 0 Rx buffer is not empty #0 1 Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU #1 RXFULL Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer full or not. 2 1 read-only 0 Rx buffer count is less than 4 #0 1 Rx buffer count equals to 4 #1 RXOV Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it. 0 1 read-write 0 Rx buffer is not overflow #0 1 Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes) #1 RXOVERR Receiver over Retry Error\nThis bit is used for receiver retry counts over than retry number limitation.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 22 1 read-write 0 Receiver retries counts is less than RXRTY (SCn_CTL[18:16]) + 1 #0 1 Receiver retries counts is equal or over than RXRTY (SCn_CTL[18:16]) + 1 #1 RXPOINT Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status. When SC controller receives one byte from external device, RXPOINT increases one. When one byte of Rx buffer is read by CPU, RXPOINT decreases one. 16 3 read-only RXRERR Receiver Retry Error\nThis bit is used for receiver error retry and set by hardware.\nNote1: This bit can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 21 1 read-write 0 No Rx retry transfer #0 1 Rx has any error and retries transfer #1 TXACT Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status. 31 1 read-only 0 This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed #0 1 Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP bit of the last byte has not been transmitted #1 TXEMPTY Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nNote: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]). 9 1 read-only 0 Tx buffer is not empty #0 1 Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register #1 TXFULL Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer full or not. 10 1 read-only 0 Tx buffer count is less than 4 #0 1 Tx buffer count equals to 4 #1 TXOV Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow. \nNote: This bit can be cleared by writing 1 to it. 8 1 read-write 0 Tx buffer is not overflow #0 1 Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]) #1 TXOVERR Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it. 30 1 read-write 0 Transmitter retries counts is less than TXRTY (SCn_CTL[22:20]) + 1 #0 1 Transmitter retries counts is equal or over to TXRTY (SCn_CTL[22:20]) + 1 #1 TXPOINT Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status. When CPU writes data into SCn_DAT, TXPOINT increases one. When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one. 24 3 read-only TXRERR Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware..\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt to CPU. 29 1 read-write 0 No Tx retry transfer #0 1 Tx has any error and retries transfer #1 SC_TMRCTL0 SC_TMRCTL0 SC Internal Timer0 Control Register 0x28 read-write n 0x0 0x0 CNT Timer0 Counter Value\nThis field indicates the internal Timer0 counter values.\nNote: Unit of Timer0 counter is ETU base. 0 24 read-write OPMODE Timer0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Table 6.173 for programming Timer0. 24 4 read-write SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SCn_TMRCTL0 register #0 1 Last value is synchronizing #1 SC_TMRCTL1 SC_TMRCTL1 SC Internal Timer1 Control Register 0x2C read-write n 0x0 0x0 CNT Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values. \nNote: Unit of Timer1 counter is ETU base. 0 8 read-write OPMODE Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Table 6.173 for programming Timer1. 24 4 read-write SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SCn_TMRCTL1 register #0 1 Last value is synchronizing #1 SC_TMRCTL2 SC_TMRCTL2 SC Internal Timer2 Control Register 0x30 read-write n 0x0 0x0 CNT Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values. \nNote: Unit of Timer2 counter is ETU base. 0 8 read-write OPMODE Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Table 6.173 for programming Timer2. 24 4 read-write SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SCn_TMRCTL2 register #0 1 Last value is synchronizing #1 SC_UARTCTL SC_UARTCTL SC UART Mode Control Register 0x34 read-write n 0x0 0x0 OPE Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0. 7 1 read-write 0 Even number of logic 1 are transmitted or check the data word and parity bits in receiving mode #0 1 Odd number of logic 1 are transmitted or check the data word and parity bits in receiving mode #1 PBOFF Parity Bit Disable Bit\nSets this bit is used for disable parity check function.\nNote: In smart card mode, this field must be 0 (default setting is with parity bit). 6 1 read-write 0 Parity bit is generated or checked between the 'last data word bit' and 'stop bit' of the serial data #0 1 Parity bit is not generated (transmitting data) or checked (receiving data) during transfer #1 UARTEN UART Mode Enable Bit\nSets this bit to enable UART mode function.\nNote3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine. 0 1 read-write 0 Smart Card mode #0 1 UART mode #1 WLS Word Length Selection\nThis field is used for select UART data length.\nNote: In smart card mode, this WLS must be 00. 4 2 read-write 0 Word length is 8 bits #00 1 Word length is 7 bits #01 2 Word length is 6 bits #10 3 Word length is 5 bits #11 SC2 SC Register Map SC 0x0 0x0 0x38 registers n 0x4C 0x4 registers n SC_ACTCTL SC_ACTCTL SC Activation Control Register 0x4C read-write n 0x0 0x0 T1EXT T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nThe cycle scaling factor is 2048.\nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3 0 5 read-write SC_ALTCTL SC_ALTCTL SC Alternate Control Register 0x8 read-write n 0x0 0x0 ACTEN Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]). Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.\nNote4: During the activation sequence, RX is disabled automatically and can not receive data. After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation. 3 1 read-write 0 No effect #0 1 Activation sequence generator Enabled #1 ACTSTS0 Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]). 13 1 read-only 0 Timer0 is not active #0 1 Timer0 is active #1 ACTSTS1 Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]). 14 1 read-only 0 Timer1 is not active #0 1 Timer1 is active #1 ACTSTS2 Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]). 15 1 read-only 0 Timer2 is not active #0 1 Timer2 is active #1 ADACEN Auto Deactivation When Card Removal\nThis bit is used for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set. If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also. 11 1 read-write 0 Auto deactivation Disabled #0 1 Auto deactivation Enabled #1 CNTEN0 Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 5 1 read-write 0 Stops counting #0 1 Start counting #1 CNTEN1 Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 6 1 read-write 0 Stops counting #0 1 Start counting #1 CNTEN2 Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 7 1 read-write 0 Stops counting #0 1 Start counting #1 DACTEN Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]). Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 2 1 read-write 0 No effect #0 1 Deactivation sequence generator Enabled #1 INITSEL Initial Timing Selection\nThis fields indicates the initial timing of hardware activation, warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Figure 6.174\nWarm-reset: refer to Warm-Reset Sequence in Figure 6.175.\nDeactivation: refer to Deactivation Sequence in Figure 6.176.\nNote: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles. 8 2 read-write RXBGTEN Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function. 12 1 read-write 0 Receiver block guard time function Disabled #0 1 Receiver block guard time function Enabled #1 RXRST Rx Software Reset\nWhen RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 1 1 read-write 0 No effect #0 1 Reset the Rx internal state machine and pointers #1 SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SCn_ALTCTL register #0 1 Last value is synchronizing #1 TXRST TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 0 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 WARSTEN Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]). Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.\nNote4: During the warm reset sequence, RX is disabled automatically and can not receive data. After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence. 4 1 read-write 0 No effect #0 1 Warm reset sequence generator Enabled #1 SC_CTL SC_CTL SC Control Register 0x4 read-write n 0x0 0x0 AUTOCEN Auto Convention Enable Bit\nThis bit is used for enable auto convention function.\nIf user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F. After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F. If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11.\nIf the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled. 3 1 read-write 0 Auto-convention Disabled #0 1 Auto-convention Enabled #1 BGT Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1. 8 5 read-write CDDBSEL Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved. 24 2 read-write 0 De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks #00 CDLV Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled. 26 1 read-write 0 When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected #0 1 When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected #1 CONSEL Convention Selection\nNote: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. 4 2 read-write 0 Direct convention #00 1 Reserved #01 2 Reserved #10 3 Inverse convention #11 NSB Stop Bit Length\nThis field indicates the length of stop bit.\nNote1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. \nNote2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. 15 1 read-write 0 The stop bit length is 2 ETU #0 1 The stop bit length is 1 ETU #1 RXOFF RX Transition Disable Control Bit\nThis bit is used for disable Rx transition function.\nNote: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. 1 1 read-write 0 The receiver Enabled #0 1 The receiver Disabled #1 RXRTY RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RXRTYEN enabled. The change flow is to disable RXRTYEN first and then fill in new retry value. 16 3 read-write RXRTYEN RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit. 19 1 read-write 0 RX error retry function Disabled #0 1 RX error retry function Enabled #1 RXTRGLV Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set. If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU. 6 2 read-write 0 Rx Buffer Trigger Level with 01 bytes #00 1 Rx Buffer Trigger Level with 02 bytes #01 2 Rx Buffer Trigger Level with 03 bytes #10 3 Reserved #11 SCEN SC Controller Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, \nNote: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. 0 1 read-write 0 SC will force all transition to IDLE state #0 1 SC controller is enabled and all function can work correctly #1 SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. 30 1 read-only 0 Synchronizing is completion, user can write new data to RXRTY and TXRTY #0 1 Last value is synchronizing #1 TMRSEL Timer Channel Selection \nOther configurations are reserved 13 2 read-write 0 All internal timer function Disabled #00 3 Internal 24 bit timer and two 8 bit timers Enabled. User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0] #11 TXOFF TX Transition Disable Control Bit\nThis bit is used for disable Tx transition function. 2 1 read-write 0 The transceiver Enabled #0 1 The transceiver Disabled #1 TXRTY TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TXRTYEN first and then fill in new retry value. 20 3 read-write TXRTYEN TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred. 23 1 read-write 0 TX error retry function Disabled #0 1 TX error retry function Enabled #1 SC_DAT SC_DAT SC Receive/Transmit Holding Buffer Register 0x0 read-write n 0x0 0x0 DAT Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data. 0 8 read-write SC_EGT SC_EGT SC Extra Guard Time Register 0xC read-write n 0x0 0x0 EGT Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base. 0 8 read-write SC_ETUCTL SC_ETUCTL SC Element Time Unit Control Register 0x14 -1 read-write n 0x0 0x0 ETURDIV ETU Rate Divider\nThe field is used for ETU clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: User can configure this field, but this field must be greater than 0x04. 0 12 read-write SC_INTEN SC_INTEN SC Interrupt Enable Control Register 0x18 read-write n 0x0 0x0 ACERRIEN Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt. 10 1 read-write 0 Auto-convention error interrupt Disabled #0 1 Auto-convention error interrupt Enabled #1 BGTIEN Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time. 6 1 read-write 0 Block guard time interrupt Disabled #0 1 Block guard time interrupt Enabled #1 CDIEN Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt. The card detect status is CDPINSTS (SCn_STATUS[13]). 7 1 read-write 0 Card detect interrupt Disabled #0 1 Card detect interrupt Enabled #1 INITIEN Initial End Interrupt Enable Bit 8 1 read-write 0 Initial end interrupt Disabled #0 1 Initial end interrupt Enabled #1 RDAIEN Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt. 0 1 read-write 0 Receive data reach trigger level interrupt Disabled #0 1 Receive data reach trigger level interrupt Enabled #1 RXTOIEN Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt. 9 1 read-write 0 Receiver buffer time-out interrupt Disabled #0 1 Receiver buffer time-out interrupt Enabled #1 TBEIEN Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt. 1 1 read-write 0 Transmit buffer empty interrupt Disabled #0 1 Transmit buffer empty interrupt Enabled #1 TERRIEN Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]). 2 1 read-write 0 Transfer error interrupt Disabled #0 1 Transfer error interrupt Enabled #1 TMR0IEN Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function. 3 1 read-write 0 Timer0 interrupt Disabled #0 1 Timer0 interrupt Enabled #1 TMR1IEN Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function. 4 1 read-write 0 Timer1 interrupt Disabled #0 1 Timer1 interrupt Enabled #1 TMR2IEN Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function. 5 1 read-write 0 Timer2 interrupt Disabled #0 1 Timer2 interrupt Enabled #1 SC_INTSTS SC_INTSTS SC Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ACERRIF Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it. 10 1 read-write 0 Received TS at ATR state is 0x3B or 0x3F #0 1 Received TS at ATR state is neither 0x3B nor 0x3F #1 BGTIF Block Guard Time Interrupt Status Flag\nThis field is used for indicate block guard time interrupt status flag in receive direction.\nNote1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.\nNote2: This bit can be cleared by writing 1 to it. 6 1 read-write 0 Block guard time interrupt did not occur #0 1 Block guard time interrupt occurred #1 CDIF Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).\nNote: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it. 7 1 read-only 0 Card detect event did not occur #0 1 Card detect event occurred #1 INITIF Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 8 1 read-write 0 Initial sequence is not complete #0 1 Initial sequence is completed #1 RDAIF Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.\nNote: This bit is read only. If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically. 0 1 read-only 0 Number of receive buffer is less than RXTRGLV setting #0 1 Number of receive buffer data equals the RXTRGLV setting #1 RXTOIF Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it. 9 1 read-only 0 Receive buffer time-out interrupt did not occur #0 1 Receive buffer time-out interrupt occurred #1 TBEIF Transmit Buffer Empty Interrupt Status Flag (Read Only) This field is used for transmit buffer empty interrupt status flag. Note: This bit is read only. If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically. 1 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 TERRIF Transfer Error Interrupt Status Flag\nThis field is used for transfer error interrupt status flag. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]).\nNote1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.\nNote2: This bit can be cleared by writing 1 to it. 2 1 read-write 0 Transfer error interrupt did not occur #0 1 Transfer error interrupt occurred #1 TMR0IF Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 3 1 read-write 0 Timer0 interrupt did not occur #0 1 Timer0 interrupt occurred #1 TMR1IF Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 4 1 read-write 0 Timer1 interrupt did not occur #0 1 Timer1 interrupt occurred #1 TMR2IF Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 5 1 read-write 0 Timer2 interrupt did not occur #0 1 Timer2 interrupt occurred #1 SC_PINCTL SC_PINCTL SC Pin Control State Register 0x24 read-write n 0x0 0x0 CLKKEEP SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. 6 1 read-write 0 SC clock generation Disabled #0 1 SC clock always keeps free running #1 DATASTS SCn_DATA Pin Status (Read Only)\nThis bit is the pin status of SCn_DATA. 16 1 read-only 0 The SCn_DATA pin status is low #0 1 The SCn_DATA pin status is high #1 PWREN SCn_PWR Pin Signal\nUser can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.\nWrite this field to drive SCn_PWR pin\nRefer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. \nRead this field to get SCn_PWR signal status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. 0 1 read-write 0 SCn_PWR signal status is low #0 1 SCn_PWR signal status is high #1 PWRINV SCn_PWR Pin Inverse\nThis bit is used for inverse the SCn_PWR pin.\nThere are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). \nPWRINV (SCn_PINCTL[11]) is bit 1 and PWREN (SCn_PINCTL[0]) is bit 0 and all conditions as below list, \nNote: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]). 11 1 read-write 0 SCn_PWR pin is 0 00 1 SCn_PWR pin is 1 01 10 SCn_PWR pin is 1 10 11 SCn_PWR pin is 0 11 PWRSTS SCn_PWR Pin Status (Read Only)\nThis bit is the pin status of SCn_PWR. 17 1 read-only 0 SCn_PWR pin to low #0 1 SCn_PWR pin to high #1 RSTEN SCn_RST Pin Signal\nUser can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.\nWrite this field to drive SCn_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. 1 1 read-write 0 Drive SCn_RST pin to low.\nSCn_RST signal status is low #0 1 Drive SCn_RST pin to high.\nSCn_RST signal status is high #1 RSTSTS SCn_RST Pin Status (Read Only)\nThis bit is the pin status of SCn_RST. 18 1 read-only 0 SCn_RST pin is low #0 1 SCn_RST pin is high #1 SCDATA SCn_DATA Pin Signal \nThis bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when SC is in these modes. 9 1 read-write 0 Drive SCn_DATA pin to low.\nSCn_DATA signal status is low #0 1 Drive SCn_DATA pin to high.\nSCn_DATA signal status is high #1 SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SCn_PINCTL register. 30 1 read-only 0 Synchronizing is completion, user can write new data to SCn_PINCTL register #0 1 Last value is synchronizing #1 SC_RXTOUT SC_RXTOUT SC Receive Buffer Time-out Counter Register 0x10 read-write n 0x0 0x0 RFTM SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the RX buffer received a new data. Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled.\nNote1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.\nNote2: Filling in all 0 to this field indicates to disable this function. 0 9 read-write SC_STATUS SC_STATUS SC Transfer Status Register 0x20 -1 read-write n 0x0 0x0 BEF Receiver Break Error Status Flag This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of 'start bit' + 'data bits' + 'parity bit' + 'stop bits'). Note1: This bit can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 6 1 read-write 0 Receiver break error flag did not occur #0 1 Receiver break error flag occurred #1 CDPINSTS Card Detect Pin Status (Read Only)\nThis bit is the pin status of SCn_CD. 13 1 read-only 0 The SCn_CD pin state at low #0 1 The SCn_CD pin state at high #1 CINSERT Card Insert Status of SCn_CD Pin\nThis bit is set whenever card has been inserted.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: The card detect function will start after SCEN (SCn_CTL[0]) set. 12 1 read-write 0 No effect #0 1 Card insert #1 CREMOVE Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: Card detect function will start after SCEN (SCn_CTL[0]) set. 11 1 read-write 0 No effect #0 1 Card removed #1 FEF Receiver Frame Error Status Flag This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note1: This bit can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 5 1 read-write 0 Receiver frame error flag did not occur #0 1 Receiver frame error flag occurred #1 PEF Receiver Parity Error Status Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note1: This bit can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 4 1 read-write 0 Receiver parity error flag did not occur #0 1 Receiver parity error flag occurred #1 RXACT Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status. 23 1 read-only 0 This bit is cleared automatically when Rx transfer is finished #0 1 This bit is set by hardware when Rx transfer is in active #1 RXEMPTY Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer empty or not. 1 1 read-only 0 Rx buffer is not empty #0 1 Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU #1 RXFULL Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer full or not. 2 1 read-only 0 Rx buffer count is less than 4 #0 1 Rx buffer count equals to 4 #1 RXOV Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it. 0 1 read-write 0 Rx buffer is not overflow #0 1 Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes) #1 RXOVERR Receiver over Retry Error\nThis bit is used for receiver retry counts over than retry number limitation.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 22 1 read-write 0 Receiver retries counts is less than RXRTY (SCn_CTL[18:16]) + 1 #0 1 Receiver retries counts is equal or over than RXRTY (SCn_CTL[18:16]) + 1 #1 RXPOINT Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status. When SC controller receives one byte from external device, RXPOINT increases one. When one byte of Rx buffer is read by CPU, RXPOINT decreases one. 16 3 read-only RXRERR Receiver Retry Error\nThis bit is used for receiver error retry and set by hardware.\nNote1: This bit can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 21 1 read-write 0 No Rx retry transfer #0 1 Rx has any error and retries transfer #1 TXACT Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status. 31 1 read-only 0 This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed #0 1 Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP bit of the last byte has not been transmitted #1 TXEMPTY Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nNote: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]). 9 1 read-only 0 Tx buffer is not empty #0 1 Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register #1 TXFULL Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer full or not. 10 1 read-only 0 Tx buffer count is less than 4 #0 1 Tx buffer count equals to 4 #1 TXOV Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow. \nNote: This bit can be cleared by writing 1 to it. 8 1 read-write 0 Tx buffer is not overflow #0 1 Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]) #1 TXOVERR Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it. 30 1 read-write 0 Transmitter retries counts is less than TXRTY (SCn_CTL[22:20]) + 1 #0 1 Transmitter retries counts is equal or over to TXRTY (SCn_CTL[22:20]) + 1 #1 TXPOINT Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status. When CPU writes data into SCn_DAT, TXPOINT increases one. When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one. 24 3 read-only TXRERR Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware..\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt to CPU. 29 1 read-write 0 No Tx retry transfer #0 1 Tx has any error and retries transfer #1 SC_TMRCTL0 SC_TMRCTL0 SC Internal Timer0 Control Register 0x28 read-write n 0x0 0x0 CNT Timer0 Counter Value\nThis field indicates the internal Timer0 counter values.\nNote: Unit of Timer0 counter is ETU base. 0 24 read-write OPMODE Timer0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Table 6.173 for programming Timer0. 24 4 read-write SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SCn_TMRCTL0 register #0 1 Last value is synchronizing #1 SC_TMRCTL1 SC_TMRCTL1 SC Internal Timer1 Control Register 0x2C read-write n 0x0 0x0 CNT Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values. \nNote: Unit of Timer1 counter is ETU base. 0 8 read-write OPMODE Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Table 6.173 for programming Timer1. 24 4 read-write SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SCn_TMRCTL1 register #0 1 Last value is synchronizing #1 SC_TMRCTL2 SC_TMRCTL2 SC Internal Timer2 Control Register 0x30 read-write n 0x0 0x0 CNT Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values. \nNote: Unit of Timer2 counter is ETU base. 0 8 read-write OPMODE Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Table 6.173 for programming Timer2. 24 4 read-write SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SCn_TMRCTL2 register #0 1 Last value is synchronizing #1 SC_UARTCTL SC_UARTCTL SC UART Mode Control Register 0x34 read-write n 0x0 0x0 OPE Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0. 7 1 read-write 0 Even number of logic 1 are transmitted or check the data word and parity bits in receiving mode #0 1 Odd number of logic 1 are transmitted or check the data word and parity bits in receiving mode #1 PBOFF Parity Bit Disable Bit\nSets this bit is used for disable parity check function.\nNote: In smart card mode, this field must be 0 (default setting is with parity bit). 6 1 read-write 0 Parity bit is generated or checked between the 'last data word bit' and 'stop bit' of the serial data #0 1 Parity bit is not generated (transmitting data) or checked (receiving data) during transfer #1 UARTEN UART Mode Enable Bit\nSets this bit to enable UART mode function.\nNote3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine. 0 1 read-write 0 Smart Card mode #0 1 UART mode #1 WLS Word Length Selection\nThis field is used for select UART data length.\nNote: In smart card mode, this WLS must be 00. 4 2 read-write 0 Word length is 8 bits #00 1 Word length is 7 bits #01 2 Word length is 6 bits #10 3 Word length is 5 bits #11 SCS SYST_SCR Register Map SYST_SCR 0x0 0x10 0xC registers n 0xD04 0x14 registers n 0xD1C 0xC registers n AIRCR AIRCR Application Interrupt and Reset Control Register 0xD0C -1 read-write n 0x0 0x0 ENDIANNESS Data Endianness 15 1 read-write 0 Little-endian #0 1 Big-endian #1 SYSRESETREQ System Reset Request Bit\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence. 2 1 read-write VECTCLRACTIVE Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack. 1 1 read-write VECTORKEY Register Access Key\nWhen writing this register, this field should be 0x05FA, otherwise the write action will be ignored.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status. 16 16 read-write CCR CCR Configuration and Control Register 0xD14 -1 read-write n 0x0 0x0 BFHFNMIGN BusFault in HardFault or NMI Ignore\nThis bit is RAZ/WI. 8 1 read-write BP Branch Prediction Enable Bit\nThis bit is RAZ/WI. 18 1 read-write DC Data Cache Enable Bit\nThis bit is RAZ/WI. 16 1 read-write DIV_0_TRP Divide by Zero Trap\nThis bit is RAZ/WI. 4 1 read-write IC Instruction Cache Enable Bit\nThis bit is RAZ/WI. 17 1 read-write STKOFHFNMIGN Stack Overflow in HardFault and NMI Ignore\nThis bit is RAZ/WI. 10 1 read-write UNALIGN_TRP Unaligned Trap\nThis bit is RAO/WI. 3 1 read-write ICSR ICSR Interrupt Control and State Register 0xD04 read-write n 0x0 0x0 ISRPENDING Interrupt Pending Flag, Excluding NMI and Faults (Read Only) 22 1 read-only 0 Interrupt not pending #0 1 Interrupt pending #1 ISRPREEMPT Interrupt Preempt Bit (Read Only)\nIf set, a pending exception will be serviced on exit from the debug halt state. 23 1 read-only NMIPENDCLR NMI Bit-pending Bit 30 1 read-write 0 No effect #0 1 Clear pending status #1 NMIPENDSET NMI Set-pending Bit\nWrite Operation: 31 1 read-write 0 No effect.\nNMI exception is not pending #0 1 Changes NMI exception state to pending.\nNMI exception is pending #1 PENDSTCLR SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDST bit, you must 'write 0 to PENDSTSET and write 1 to PENDSTCLR' at the same time. 25 1 read-write 0 No effect #0 1 Removes the pending state from the SysTick exception #1 PENDSTSET SysTick Exception Set-pending Bit\nWrite Operation: 26 1 read-write 0 No effect.\nSysTick exception is not pending #0 1 Changes SysTick exception state to pending.\nSysTick exception is pending #1 PENDSVCLR PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDSV bit, you must 'write 0 to PENDSVSET and write 1 to PENDSVCLR' at the same time. 27 1 read-write 0 No effect #0 1 Removes the pending state from the PendSV exception #1 PENDSVSET PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending. 28 1 read-write 0 No effect.\nPendSV exception is not pending #0 1 Changes PendSV exception state to pending.\nPendSV exception is pending #1 VECTACTIVE Number of the Current Active Exception 0 9 read-write 0 Thread mode 0 VECTPENDING Number of the Highest Pended Exception 12 9 read-write 0 no pending exceptions 0 SCR SCR System Control Register 0xD10 read-write n 0x0 0x0 SEVONPEND Send Event on Pending\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event. 4 1 read-write 0 Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded #0 1 Enabled events and all interrupts, including disabled interrupts, can wake up the processor #1 SLEEPDEEP Processor Deep Sleep and Sleep Mode Selection\nControl Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode. 2 1 read-write 0 Sleep #0 1 Deep sleep #1 SLEEPONEXIT Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 1 1 read-write 0 Do not sleep when returning to Thread mode #0 1 Enters sleep, or deep sleep, on return from an ISR to Thread mode #1 SHCSR SHCSR System Handler Control and State Register 0xD24 read-write n 0x0 0x0 HARDFAULTPENDED HardFault Exception Pended State \nThis bit indicates and allows modification of the pending state of the HardFault exception.\nThe possible values of this bit are: 21 1 read-write 0 HardFault exception not pending #0 1 HardFault exception pending #1 SHPR2 SHPR2 System Handler Priority Register 2 0xD1C read-write n 0x0 0x0 PRI_11 Priority of System Handler 11 - SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write SHPR3 SHPR3 System Handler Priority Register 3 0xD20 read-write n 0x0 0x0 PRI_14 Priority of System Handler 14 - PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority. 22 2 read-write PRI_15 Priority of System Handler 15 - SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write SYST_CTRL SYST_CTRL SysTick Control and Status Register 0x10 read-write n 0x0 0x0 CLKSRC System Tick Clock Source Selection 2 1 read-write 0 Clock source is the (optional) external reference clock #0 1 Core clock used for SysTick #1 COUNTFLAG System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register. 16 1 read-write ENABLE System Tick Counter Enabled 0 1 read-write 0 Counter Disabled #0 1 Counter will operate in a multi-shot manner #1 TICKINT System Tick Interrupt Enabled 1 1 read-write 0 Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended #1 SYST_LOAD SYST_LOAD SysTick Reload Value Register 0x14 read-write n 0x0 0x0 RELOAD System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0. 0 24 read-write SYST_VAL SYST_VAL SysTick Current Value Register 0x18 read-write n 0x0 0x0 CURRENT System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ. 0 24 read-write VTOR VTOR Vector Table Offset Register 0xD08 read-write n 0x0 0x0 TBLOFF Table Offset Bits\nThe vector table address. 8 24 read-write SDH0 SDH Register Map SDH 0x0 0x0 0x2C registers n 0x400 0x4 registers n 0x408 0x10 registers n 0x800 0xC registers n 0x820 0x20 registers n SDH_BLEN SDH_BLEN SD Block Length Register 0x838 -1 read-write n 0x0 0x0 BLKLEN SD BLOCK LENGTH in Byte Unit\nAn 11-bit value specifies the SD transfer byte count of a block. The actual byte count is equal to BLKLEN+1.\nNote: The default SD block length is 512 bytes 0 11 read-write SDH_CMDARG SDH_CMDARG SD Command Argument Register 0x824 read-write n 0x0 0x0 ARGUMENT SD Command Argument\nThis register contains a 32-bit value specifies the argument of SD command from host controller to SD card. Before trigger COEN (SDH_CTL [0]), software should fill argument in this field. 0 32 read-write SDH_CTL SDH_CTL SD Control and Status Register 0x820 -1 read-write n 0x0 0x0 BLKCNT Block Counts to Be Transferred or Received\nThis field contains the block counts for data-in and data-out transfer. For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance. Don't fill 0x0 to this field.\nNote: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1). 16 8 read-write CLK74OEN Initial 74 Clock Cycles Output Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). 5 1 read-write 0 No effect. (Please use DMARST (SDH_DMACTL[1]) to clear this bit.) #0 1 Enabled. The SD host will output 74 clock cycles to SD card #1 CLK8OEN Generating 8 Clock Cycles Output Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). 6 1 read-write 0 No effect. (Please use DMARST (SDH_DMACTL[1]) to clear this bit.) #0 1 Enabled. The SD host will output 8 clock cycles #1 CLKKEEP SD Clock Enable Control 7 1 read-write 0 SD host decided when to output clock and when to disable clock output automatically #0 1 SD clock always keeps free running #1 CMDCODE SD Command Code\nThe bits contain the SD command code (0x00 - 0x3F). 8 6 read-write COEN Command Output Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). 0 1 read-write 0 No effect. (Please use DMARST (SDH_DMACTL[1]) to clear this bit.) #0 1 Enabled. The SD host will output a command to SD card #1 CTLRST Software Engine Reset 14 1 read-write 0 No effect #0 1 Reset the internal state machine and counters. The contents of control register will not be cleared (but RIEN (SDH_CTL[1]), DIEN (SDH_CTL[2]), DOEN (SDH_CTL[3]) and R2EN (SDH_CTL[4]) will be cleared). This bit will be auto cleared after few clock cycles #1 DBW SD Data Bus Width (for 1-bit / 4-bit Selection) 15 1 read-write 0 Data bus width is 1-bit #0 1 Data bus width is 4-bit #1 DIEN Data Input Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). 2 1 read-write 0 No effect. (Please use DMARST (SDH_DMACTL[1]) to clear this bit.) #0 1 Enabled. The SD host will wait to receive block data and the CRC16 value from SD card #1 DOEN Data Output Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). 3 1 read-write 0 No effect. (Please use DMARST (SDH_DMACTL[1]) to clear this bit.) #0 1 Enabled. The SD host will transfer block data and the CRC16 value to SD card #1 R2EN Response R2 Input Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). 4 1 read-write 0 No effect. (Please use DMARST (SDH_DMACTL[1]) to clear this bit.) #0 1 Enabled. The SD host will wait to receive a response R2 from SD card and store the response data into DMC's Flash buffer (exclude CRC7) #1 RIEN Response Input Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). 1 1 read-write 0 No effect. (Please use DMARST (SDH_DMACTL[1]) to clear this bit.) #0 1 Enabled. The SD host will wait to receive a response from SD card #1 SDNWR NWR Parameter for Block Write Operation\nThis value indicates the NWR parameter for data block write operation in SD clock counts. The actual clock cycle will be SDNWR+1. 24 4 read-write SDH_DMABCNT SDH_DMABCNT DMA Transfer Byte Count Register 0x40C read-only n 0x0 0x0 BCNT DMA Transfer Byte Count (Read Only) This field indicates the remained byte count of DMA transfer. The value of this field is valid only when DMA is busy otherwise, it is 0. 0 26 read-only SDH_DMACTL SDH_DMACTL DMA Control and Status Register 0x400 read-write n 0x0 0x0 DMABUSY DMA Transfer Is in Progress\nThis bit indicates if SD Host is granted and doing DMA transfer or not. 9 1 read-write 0 DMA transfer is not in progress #0 1 DMA transfer is in progress #1 DMAEN DMA Engine Enable Bit\nNote1: If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.\nNote2: If target abort occurred, DMAEN will be cleared. 0 1 read-write 0 DMA Disabled #0 1 DMA Enabled #1 DMARST Software Engine Reset\nNote: The software reset DMA related registers. 1 1 read-write 0 No effect #0 1 Reset internal state machine and pointers. The contents of control register will not be cleared. This bit will auto be cleared after few clock cycles #1 SGEN Scatter-gather Function Enable Bit 3 1 read-write 0 Scatter-gather function Disabled (DMA will treat the starting address in DMASA as starting pointer of a single block memory) #0 1 Scatter-gather function Enabled (DMA will treat the starting address in DMASA as a starting address of Physical Address Descriptor (PAD) table. The format of these Pads' will be described later) #1 SDH_DMAINTEN SDH_DMAINTEN DMA Interrupt Enable Control Register 0x410 -1 read-write n 0x0 0x0 ABORTIEN DMA Read/Write Target Abort Interrupt Enable Bit 0 1 read-write 0 Target abort interrupt generation Disabled during DMA transfer #0 1 Target abort interrupt generation Enabled during DMA transfer #1 WEOTIEN Wrong EOT Encountered Interrupt Enable Bit 1 1 read-write 0 Interrupt generation Disabled when wrong EOT is encountered #0 1 Interrupt generation Enabled when wrong EOT is encountered #1 SDH_DMAINTSTS SDH_DMAINTSTS DMA Interrupt Status Register 0x414 read-write n 0x0 0x0 ABORTIF DMA Read/Write Target Abort Interrupt Flag (Read Only)\nNote1: This bit is read only, but can be cleared by writing '1' to it.\nNote2: When DMA's bus master received ERROR response, it means that target abort is happened. DMA will stop transfer and respond this event and then go to IDLE state. When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again. 0 1 read-only 0 No bus ERROR response received #0 1 Bus ERROR response received #1 WEOTIF Wrong EOT Encountered Interrupt Flag (Read Only)\nWhen DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it. 1 1 read-only 0 No EOT encountered before DMA transfer finished #0 1 EOT encountered before DMA transfer finished #1 SDH_DMASA SDH_DMASA DMA Transfer Starting Address Register 0x408 read-write n 0x0 0x0 DMASA DMA Transfer Starting Address\nThis field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.\nIf DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.\nNote: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004. 1 31 read-write ORDER Determined to the PAD Table Fetching Is in Order or Out of Order 0 1 read-write 0 PAD table is fetched in order #0 1 PAD table is fetched out of order #1 SDH_FB_0 SDH_FB_0 Shared Buffer (FIFO) 0x0 read-write n 0x0 0x0 SDH_FB_1 SDH_FB_1 Shared Buffer (FIFO) 0x4 read-write n 0x0 0x0 SDH_FB_10 SDH_FB_10 Shared Buffer (FIFO) 0x28 read-write n 0x0 0x0 SDH_FB_11 SDH_FB_11 Shared Buffer (FIFO) 0x2C read-write n 0x0 0x0 SDH_FB_12 SDH_FB_12 Shared Buffer (FIFO) 0x30 read-write n 0x0 0x0 SDH_FB_13 SDH_FB_13 Shared Buffer (FIFO) 0x34 read-write n 0x0 0x0 SDH_FB_14 SDH_FB_14 Shared Buffer (FIFO) 0x38 read-write n 0x0 0x0 SDH_FB_15 SDH_FB_15 Shared Buffer (FIFO) 0x3C read-write n 0x0 0x0 SDH_FB_16 SDH_FB_16 Shared Buffer (FIFO) 0x40 read-write n 0x0 0x0 SDH_FB_17 SDH_FB_17 Shared Buffer (FIFO) 0x44 read-write n 0x0 0x0 SDH_FB_18 SDH_FB_18 Shared Buffer (FIFO) 0x48 read-write n 0x0 0x0 SDH_FB_19 SDH_FB_19 Shared Buffer (FIFO) 0x4C read-write n 0x0 0x0 SDH_FB_2 SDH_FB_2 Shared Buffer (FIFO) 0x8 read-write n 0x0 0x0 SDH_FB_20 SDH_FB_20 Shared Buffer (FIFO) 0x50 read-write n 0x0 0x0 SDH_FB_21 SDH_FB_21 Shared Buffer (FIFO) 0x54 read-write n 0x0 0x0 SDH_FB_22 SDH_FB_22 Shared Buffer (FIFO) 0x58 read-write n 0x0 0x0 SDH_FB_23 SDH_FB_23 Shared Buffer (FIFO) 0x5C read-write n 0x0 0x0 SDH_FB_24 SDH_FB_24 Shared Buffer (FIFO) 0x60 read-write n 0x0 0x0 SDH_FB_25 SDH_FB_25 Shared Buffer (FIFO) 0x64 read-write n 0x0 0x0 SDH_FB_26 SDH_FB_26 Shared Buffer (FIFO) 0x68 read-write n 0x0 0x0 SDH_FB_27 SDH_FB_27 Shared Buffer (FIFO) 0x6C read-write n 0x0 0x0 SDH_FB_28 SDH_FB_28 Shared Buffer (FIFO) 0x70 read-write n 0x0 0x0 SDH_FB_29 SDH_FB_29 Shared Buffer (FIFO) 0x74 read-write n 0x0 0x0 SDH_FB_3 SDH_FB_3 Shared Buffer (FIFO) 0xC read-write n 0x0 0x0 SDH_FB_30 SDH_FB_30 Shared Buffer (FIFO) 0x78 read-write n 0x0 0x0 SDH_FB_31 SDH_FB_31 Shared Buffer (FIFO) 0x7C read-write n 0x0 0x0 SDH_FB_4 SDH_FB_4 Shared Buffer (FIFO) 0x10 read-write n 0x0 0x0 SDH_FB_5 SDH_FB_5 Shared Buffer (FIFO) 0x14 read-write n 0x0 0x0 SDH_FB_6 SDH_FB_6 Shared Buffer (FIFO) 0x18 read-write n 0x0 0x0 SDH_FB_7 SDH_FB_7 Shared Buffer (FIFO) 0x1C read-write n 0x0 0x0 SDH_FB_8 SDH_FB_8 Shared Buffer (FIFO) 0x20 read-write n 0x0 0x0 SDH_FB_9 SDH_FB_9 Shared Buffer (FIFO) 0x24 read-write n 0x0 0x0 SDH_GCTL SDH_GCTL Global Control and Status Register 0x800 read-write n 0x0 0x0 GCTLRST Software Engine Reset 0 1 read-write 0 No effect #0 1 Reset SD host. The contents of control register will not be cleared. This bit will auto cleared after reset complete #1 SDEN Secure Digital Functionality Enable Bit 1 1 read-write 0 SD functionality Disabled #0 1 SD functionality Enabled #1 SDH_GINTEN SDH_GINTEN Global Interrupt Control Register 0x804 -1 read-write n 0x0 0x0 DTAIEN DMA READ/WRITE Target Abort Interrupt Enable Bit 0 1 read-write 0 DMA READ/WRITE target abort interrupt generation Disabled #0 1 DMA READ/WRITE target abort interrupt generation Enabled #1 SDH_GINTSTS SDH_GINTSTS Global Interrupt Status Register 0x808 read-write n 0x0 0x0 DTAIF DMA READ/WRITE Target Abort Interrupt Flag (Read Only)\nThis bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation. When Target Abort is occurred, please reset all engine.\nNote: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only 0 No bus ERROR response received #0 1 Bus ERROR response received #1 SDH_INTEN SDH_INTEN SD Interrupt Control Register 0x828 -1 read-write n 0x0 0x0 BLKDIEN Block Transfer Done Interrupt Enable Bit 0 1 read-write 0 BLKDIF (SDH_INTSTS[0]) trigger interrupt Disabled #0 1 BLKDIF (SDH_INTSTS[0]) trigger interrupt Enabled #1 CDIEN SD Card Detection Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when card is inserted or removed. 8 1 read-write 0 CDIF (SDH_INTSTS[8]) trigger interrupt Disabled #0 1 CDIF (SDH_INTSTS[8]) trigger interrupt Enabled #1 CDSRC SD Card Detect Source Selection 30 1 read-write 0 From SD card's DAT3 pin #0 1 From GPIO pin #1 CRCIEN CRC7, CRC16 and CRC Status Error Interrupt Enable Bit 1 1 read-write 0 CRCIF (SDH_INTSTS[1]) trigger interrupt Disabled #0 1 CRCIF (SDH_INTSTS[1]) trigger interrupt Enabled #1 DITOIEN Data Input Time-out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when data input time-out. The time-out value is specified at TOUT register. 13 1 read-write 0 DITOIF (SDH_INTSTS[13]) trigger interrupt Disabled #0 1 DITOIF (SDH_INTSTS[13]) trigger interrupt Enabled #1 RTOIEN Response Time-out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when receiving response or R2 time-out. The time-out value is specified at TOUT register. 12 1 read-write 0 RTOIF (SDH_INTSTS[12]) trigger interrupt Disabled #0 1 RTOIF (SDH_INTSTS[12]) trigger interrupt Enabled #1 WKIEN Wake-up Signal Generating Enable Bit\nEnable/Disable wake-up signal generating of SD controller when card is inserted or removed. 14 1 read-write 0 SD Card interrupt to wake-up chip Disabled #0 1 SD Card interrupt to wake-up chip Enabled #1 SDH_INTSTS SDH_INTSTS SD Interrupt Status Register 0x82C -1 read-write n 0x0 0x0 BLKDIF Block Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that SD host has finished all data-in or data-out block transfer. If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.\nNote: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only 0 Not finished yet #0 1 Done #1 CDIF SD Card Detection Interrupt Flag (Read Only)\nThis bit indicates that SD card is inserted or removed. Only when CDIEN (SDH_INTEN[8]) is set to 1, this bit is active.\nNote: This bit is read only, but can be cleared by writing '1' to it. 8 1 read-only 0 No card is inserted or removed #0 1 There is a card inserted in or removed from SD #1 CDSTS Card Detect Status of SD (Read Only)\nThis bit indicates the card detect pin status of SD, and is used for card detection. When there is a card inserted in or removed from SD, software should check this bit to confirm if there is really a card insertion or removal. 16 1 read-only 0 Card removed.\nCard inserted #0 1 Card inserted.\nCard removed #1 CRC16 CRC16 Check Status of Data-in Transfer (Read Only)\nSD host will check CRC16 correctness after data-in transfer. 3 1 read-only 0 Fault #0 1 OK #1 CRC7 CRC7 Check Status (Read Only)\nSD host will check CRC7 correctness during each response in. If that response does not contain CRC7 information (ex. R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit. 2 1 read-only 0 Fault #0 1 OK #1 CRCIF CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only) This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer. When CRC error is occurred, software should reset SD engine. Some response (ex. R3) doesn't have CRC7 information with it SD host will still calculate CRC7, get CRC error and set this flag. In this condition, software should ignore CRC error and clears this bit manually. Note: This bit is read only, but can be cleared by writing '1' to it. 1 1 read-only 0 No CRC error is occurred #0 1 CRC error is occurred #1 CRCSTS CRC Status Value of Data-out Transfer (Read Only)\nSD host will record CRC status of data-out transfer. Software could use this value to identify what type of error is during data-out transfer. 4 3 read-only 2 Positive CRC status #010 5 Negative CRC status #101 7 SD card programming error occurs #111 DAT0STS DAT0 Pin Status of Current Selected SD Port (Read Only)\nThis bit is the DAT0 pin status of current selected SD port. 7 1 read-only DAT1STS DAT1 Pin Status of SD Card (Read Only)\nThis bit indicates the DAT1 pin status of SD card. 18 1 read-only DITOIF Data Input Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving data (waiting start bit).\nNote: This bit is read only, but can be cleared by writing '1' to it. 13 1 read-only 0 Not time-out #0 1 Data input time-out #1 RTOIF Response Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).\nNote: This bit is read only, but can be cleared by writing '1' to it. 12 1 read-only 0 Not time-out #0 1 Response time-out #1 SDH_RESP0 SDH_RESP0 SD Receiving Response Token Register 0 0x830 read-only n 0x0 0x0 RESPTK0 SD Receiving Response Token 0 (Read Only)\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This field contains response bit 47-16 of the response token. 0 32 read-only SDH_RESP1 SDH_RESP1 SD Receiving Response Token Register 1 0x834 read-only n 0x0 0x0 RESPTK1 SD Receiving Response Token 1 (Read Only)\nThe SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This register contains the bit 15-8 of the response token. 0 8 read-only SDH_TOUT SDH_TOUT SD Response/Data-in Time-out Register 0x83C read-write n 0x0 0x0 TOUT SD Response/Data-in Time-out Value\nA 24-bit value specifies the time-out counts of response and data input. SD host controller will wait start bit of response or data-in until this value reached. The time period depends on SD engine clock frequency. Do not write a small number into this field, or you may never get response or data due to time-out.\nNote: Filling 0x0 into this field will disable hardware time-out function. 0 24 read-write SPI0 SPI Register Map SPI 0x0 0x0 0x18 registers n 0x20 0x4 registers n 0x30 0x4 registers n 0x60 0xC registers n SPIx_CLKDIV SPIx_CLKDIV SPI Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.\nNote: Not supported in I2S mode. 0 9 read-write SPIx_CTL SPIx_CTL SPI Control Register 0x0 -1 read-write n 0x0 0x0 CLKPOL Clock Polarity 3 1 read-write 0 SPI bus clock is idle low #0 1 SPI bus clock is idle high #1 DATDIR Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer 20 1 read-write 0 SPI data is input direction #0 1 SPI data is output direction #1 DWIDTH Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically. 8 5 read-write HALFDPX SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. 14 1 read-write 0 SPI operates in full-duplex transfer #0 1 SPI operates in half-duplex transfer #1 LSB Send LSB First 13 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX) #1 REORDER Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 19 1 read-write 0 Byte Reorder function Disabled #0 1 Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV #1 RXNEG Receive on Negative Edge 1 1 read-write 0 Received data input signal is latched on the rising edge of SPI bus clock #0 1 Received data input signal is latched on the falling edge of SPI bus clock #1 RXONLY Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. 15 1 read-write 0 Receive-only mode Disabled #0 1 Receive-only mode Enabled #1 SLAVE Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SPIEN SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. 0 1 read-write 0 Transfer control Disabled #0 1 Transfer control Enabled #1 SUSPITV Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\nExample: 4 4 read-write TXNEG Transmit on Negative Edge 2 1 read-write 0 Transmitted data output signal is changed on the rising edge of SPI bus clock #0 1 Transmitted data output signal is changed on the falling edge of SPI bus clock #1 UNITIEN Unit Transfer Interrupt Enable Bit 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 SPIx_FIFOCTL SPIx_FIFOCTL SPI FIFO Control Register 0x10 -1 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared. 8 1 read-write 0 No effect #0 1 Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 RXOVIEN Receive FIFO Overrun Interrupt Enable Bit 5 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RXRST Receive Reset 0 1 read-write 0 No effect #0 1 Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 RXTH Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. 24 3 read-write RXTHIEN Receive FIFO Threshold Interrupt Enable Bit 2 1 read-write 0 RX FIFO threshold interrupt Disabled #0 1 RX FIFO threshold interrupt Enabled #1 RXTOIEN Slave Receive Time-out Interrupt Enable Bit 4 1 read-write 0 Receive time-out interrupt Disabled #0 1 Receive time-out interrupt Enabled #1 TXFBCLR Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared. 9 1 read-write 0 No effect #0 1 Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 TXRST Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. 1 1 read-write 0 No effect #0 1 Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 TXTH Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. 28 3 read-write TXTHIEN Transmit FIFO Threshold Interrupt Enable Bit 3 1 read-write 0 TX FIFO threshold interrupt Disabled #0 1 TX FIFO threshold interrupt Enabled #1 TXUFIEN TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt. 7 1 read-write 0 Slave TX underflow interrupt Disabled #0 1 Slave TX underflow interrupt Enabled #1 TXUFPOL TX Underflow Data Polarity\nNote:\n1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\n2. This bit should be set as 0 in I2S mode.\n3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. 6 1 read-write 0 The SPI data out is keep 0 if there is TX underflow event in Slave mode #0 1 The SPI data out is keep 1 if there is TX underflow event in Slave mode #1 SPIx_I2SCLK SPIx_I2SCLK I2S Clock Divider Control Register 0x64 read-write n 0x0 0x0 BCLKDIV Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock , fBCLK, is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.\nIn I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . \nThe peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. 8 10 read-write MCLKDIV Master Clock Divider\nIf MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate. 0 7 read-write SPIx_I2SCTL SPIx_I2SCTL I2S Control Register 0x60 read-write n 0x0 0x0 FORMAT Data Format Selection 28 2 read-write 0 I2S data format #00 1 MSB justified data format #01 2 PCM mode A #10 3 PCM mode B #11 I2SEN I2S Controller Enable Bit\nNote:\n1. If enabling this bit, I2Sx_BCLK will start to output in Master mode.\n2. Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. 0 1 read-write 0 I2S mode Disabled #0 1 I2S mode Enabled #1 LZCEN Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 17 1 read-write 0 Left channel zero cross detection Disabled #0 1 Left channel zero cross detection Enabled #1 LZCIEN Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs. 25 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 MCLKEN Master Clock Enable Bit\nIf MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. 15 1 read-write 0 Master clock Disabled #0 1 Master clock Enabled #1 MONO Monaural Data 6 1 read-write 0 Data is stereo format #0 1 Data is monaural format #1 MUTE Transmit Mute Enable Bit 3 1 read-write 0 Transmit data is shifted from buffer #0 1 Transmit channel zero #1 ORDER Stereo Data Order in FIFO 7 1 read-write 0 Left channel data at high byte #0 1 Left channel data at low byte #1 RXEN Receive Enable Bit 2 1 read-write 0 Data receive Disabled #0 1 Data receive Enabled #1 RXLCH Receive Left Channel Enable Bit 23 1 read-write 0 Receive right channel data in Mono mode #0 1 Receive left channel data in Mono mode #1 RZCEN Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 16 1 read-write 0 Right channel zero cross detection Disabled #0 1 Right channel zero cross detection Enabled #1 RZCIEN Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs. 24 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 SLAVE Slave Mode\nI2S can operate as master or slave. For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. 8 1 read-write 0 Master mode #0 1 Slave mode #1 TXEN Transmit Enable Bit 1 1 read-write 0 Data transmit Disabled #0 1 Data transmit Enabled #1 WDWIDTH Word Width 4 2 read-write 0 data size is 8-bit #00 1 data size is 16-bit #01 2 data size is 24-bit #10 3 data size is 32-bit #11 SPIx_I2SSTS SPIx_I2SSTS I2S Status Register 0x68 -1 read-write n 0x0 0x0 I2SENSTS I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. 15 1 read-only 0 The SPI/I2S control logic is disabled #0 1 The SPI/I2S control logic is enabled #1 LZCIF Left Channel Zero Cross Interrupt Flag 21 1 read-write 0 No zero cross event occurred on left channel #0 1 Zero cross event occurred on left channel #1 RIGHT Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel. 4 1 read-only 0 Left channel #0 1 Right channel #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 3 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 RZCIF Right Channel Zero Cross Interrupt Flag 20 1 read-write 0 No zero cross event occurred on right channel #0 1 Zero cross event occurred on right channel #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 3 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 19 1 read-write SPIx_PDMACTL SPIx_PDMACTL SPI PDMA Control Register 0xC read-write n 0x0 0x0 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0 #1 RXPDMAEN Receive PDMA Enable Bit 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPIx_RX SPIx_RX SPI Data Receive Register 0x30 read-only n 0x0 0x0 RX Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. 0 32 read-only SPIx_SSCTL SPIx_SSCTL SPI Slave Select Control Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit (Master Only) 3 1 read-write 0 Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]) #0 1 Automatic slave selection function Enabled #1 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit 8 1 read-write 0 Slave mode bit count error interrupt Disabled #0 1 Slave mode bit count error interrupt Enabled #1 SLVURIEN Slave Mode TX Under Run Interrupt Enable Bit 9 1 read-write 0 Slave mode TX under run interrupt Disabled #0 1 Slave mode TX under run interrupt Enabled #1 SS Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0, 0 1 read-write 0 set the SPIx_SS line to inactive state.\nKeep the SPIx_SS line at inactive state #0 1 set the SPIx_SS line to active state.\nSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]) #1 SSACTIEN Slave Select Active Interrupt Enable Bit 12 1 read-write 0 Slave select active interrupt Disabled #0 1 Slave select active interrupt Enabled #1 SSACTPOL Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS). 2 1 read-write 0 The slave selection signal SPIx_SS is active low #0 1 The slave selection signal SPIx_SS is active high #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit 13 1 read-write 0 Slave select inactive interrupt Disabled #0 1 Slave select inactive interrupt Enabled #1 SPIx_STATUS SPIx_STATUS SPI Status Register 0x14 -1 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 0 1 read-only 0 SPI controller is in idle state #0 1 SPI controller is in busy state #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write 0 No FIFO is overrun #0 1 Receive FIFO is overrun #1 RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 SLVBEIF Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it. 6 1 read-write 0 No Slave mode bit count error event #0 1 Slave mode bit count error event occurred #1 SLVURIF Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 7 1 read-write 0 No Slave TX under run event #0 1 Slave TX under run event occurred #1 SPIENSTS SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. 15 1 read-only 0 SPI controller Disabled #0 1 SPI controller Enabled #1 SSACTIF Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 2 1 read-write 0 Slave select active interrupt was cleared or not occurred #0 1 Slave select active interrupt event occurred #1 SSINAIF Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 3 1 read-write 0 Slave select inactive interrupt was cleared or not occurred #0 1 Slave select inactive interrupt event occurred #1 SSLINE Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 4 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 19 1 read-write 0 No effect #0 1 No data in Transmit FIFO and TX shift register when the slave selection signal is active #1 UNITIF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 1 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 SPIx_TX SPIx_TX SPI Data Transmit Register 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.\nIn SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.\nIn I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section\nNote: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 0 32 write-only SPI1 SPI Register Map SPI 0x0 0x0 0x18 registers n 0x20 0x4 registers n 0x30 0x4 registers n 0x60 0xC registers n SPIx_CLKDIV SPIx_CLKDIV SPI Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.\nNote: Not supported in I2S mode. 0 9 read-write SPIx_CTL SPIx_CTL SPI Control Register 0x0 -1 read-write n 0x0 0x0 CLKPOL Clock Polarity 3 1 read-write 0 SPI bus clock is idle low #0 1 SPI bus clock is idle high #1 DATDIR Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer 20 1 read-write 0 SPI data is input direction #0 1 SPI data is output direction #1 DWIDTH Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically. 8 5 read-write HALFDPX SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. 14 1 read-write 0 SPI operates in full-duplex transfer #0 1 SPI operates in half-duplex transfer #1 LSB Send LSB First 13 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX) #1 REORDER Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 19 1 read-write 0 Byte Reorder function Disabled #0 1 Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV #1 RXNEG Receive on Negative Edge 1 1 read-write 0 Received data input signal is latched on the rising edge of SPI bus clock #0 1 Received data input signal is latched on the falling edge of SPI bus clock #1 RXONLY Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. 15 1 read-write 0 Receive-only mode Disabled #0 1 Receive-only mode Enabled #1 SLAVE Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SPIEN SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. 0 1 read-write 0 Transfer control Disabled #0 1 Transfer control Enabled #1 SUSPITV Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\nExample: 4 4 read-write TXNEG Transmit on Negative Edge 2 1 read-write 0 Transmitted data output signal is changed on the rising edge of SPI bus clock #0 1 Transmitted data output signal is changed on the falling edge of SPI bus clock #1 UNITIEN Unit Transfer Interrupt Enable Bit 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 SPIx_FIFOCTL SPIx_FIFOCTL SPI FIFO Control Register 0x10 -1 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared. 8 1 read-write 0 No effect #0 1 Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 RXOVIEN Receive FIFO Overrun Interrupt Enable Bit 5 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RXRST Receive Reset 0 1 read-write 0 No effect #0 1 Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 RXTH Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. 24 3 read-write RXTHIEN Receive FIFO Threshold Interrupt Enable Bit 2 1 read-write 0 RX FIFO threshold interrupt Disabled #0 1 RX FIFO threshold interrupt Enabled #1 RXTOIEN Slave Receive Time-out Interrupt Enable Bit 4 1 read-write 0 Receive time-out interrupt Disabled #0 1 Receive time-out interrupt Enabled #1 TXFBCLR Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared. 9 1 read-write 0 No effect #0 1 Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 TXRST Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. 1 1 read-write 0 No effect #0 1 Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 TXTH Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. 28 3 read-write TXTHIEN Transmit FIFO Threshold Interrupt Enable Bit 3 1 read-write 0 TX FIFO threshold interrupt Disabled #0 1 TX FIFO threshold interrupt Enabled #1 TXUFIEN TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt. 7 1 read-write 0 Slave TX underflow interrupt Disabled #0 1 Slave TX underflow interrupt Enabled #1 TXUFPOL TX Underflow Data Polarity\nNote:\n1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\n2. This bit should be set as 0 in I2S mode.\n3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. 6 1 read-write 0 The SPI data out is keep 0 if there is TX underflow event in Slave mode #0 1 The SPI data out is keep 1 if there is TX underflow event in Slave mode #1 SPIx_I2SCLK SPIx_I2SCLK I2S Clock Divider Control Register 0x64 read-write n 0x0 0x0 BCLKDIV Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock , fBCLK, is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.\nIn I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . \nThe peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. 8 10 read-write MCLKDIV Master Clock Divider\nIf MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate. 0 7 read-write SPIx_I2SCTL SPIx_I2SCTL I2S Control Register 0x60 read-write n 0x0 0x0 FORMAT Data Format Selection 28 2 read-write 0 I2S data format #00 1 MSB justified data format #01 2 PCM mode A #10 3 PCM mode B #11 I2SEN I2S Controller Enable Bit\nNote:\n1. If enabling this bit, I2Sx_BCLK will start to output in Master mode.\n2. Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. 0 1 read-write 0 I2S mode Disabled #0 1 I2S mode Enabled #1 LZCEN Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 17 1 read-write 0 Left channel zero cross detection Disabled #0 1 Left channel zero cross detection Enabled #1 LZCIEN Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs. 25 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 MCLKEN Master Clock Enable Bit\nIf MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. 15 1 read-write 0 Master clock Disabled #0 1 Master clock Enabled #1 MONO Monaural Data 6 1 read-write 0 Data is stereo format #0 1 Data is monaural format #1 MUTE Transmit Mute Enable Bit 3 1 read-write 0 Transmit data is shifted from buffer #0 1 Transmit channel zero #1 ORDER Stereo Data Order in FIFO 7 1 read-write 0 Left channel data at high byte #0 1 Left channel data at low byte #1 RXEN Receive Enable Bit 2 1 read-write 0 Data receive Disabled #0 1 Data receive Enabled #1 RXLCH Receive Left Channel Enable Bit 23 1 read-write 0 Receive right channel data in Mono mode #0 1 Receive left channel data in Mono mode #1 RZCEN Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 16 1 read-write 0 Right channel zero cross detection Disabled #0 1 Right channel zero cross detection Enabled #1 RZCIEN Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs. 24 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 SLAVE Slave Mode\nI2S can operate as master or slave. For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. 8 1 read-write 0 Master mode #0 1 Slave mode #1 TXEN Transmit Enable Bit 1 1 read-write 0 Data transmit Disabled #0 1 Data transmit Enabled #1 WDWIDTH Word Width 4 2 read-write 0 data size is 8-bit #00 1 data size is 16-bit #01 2 data size is 24-bit #10 3 data size is 32-bit #11 SPIx_I2SSTS SPIx_I2SSTS I2S Status Register 0x68 -1 read-write n 0x0 0x0 I2SENSTS I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. 15 1 read-only 0 The SPI/I2S control logic is disabled #0 1 The SPI/I2S control logic is enabled #1 LZCIF Left Channel Zero Cross Interrupt Flag 21 1 read-write 0 No zero cross event occurred on left channel #0 1 Zero cross event occurred on left channel #1 RIGHT Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel. 4 1 read-only 0 Left channel #0 1 Right channel #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 3 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 RZCIF Right Channel Zero Cross Interrupt Flag 20 1 read-write 0 No zero cross event occurred on right channel #0 1 Zero cross event occurred on right channel #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 3 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 19 1 read-write SPIx_PDMACTL SPIx_PDMACTL SPI PDMA Control Register 0xC read-write n 0x0 0x0 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0 #1 RXPDMAEN Receive PDMA Enable Bit 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPIx_RX SPIx_RX SPI Data Receive Register 0x30 read-only n 0x0 0x0 RX Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. 0 32 read-only SPIx_SSCTL SPIx_SSCTL SPI Slave Select Control Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit (Master Only) 3 1 read-write 0 Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]) #0 1 Automatic slave selection function Enabled #1 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit 8 1 read-write 0 Slave mode bit count error interrupt Disabled #0 1 Slave mode bit count error interrupt Enabled #1 SLVURIEN Slave Mode TX Under Run Interrupt Enable Bit 9 1 read-write 0 Slave mode TX under run interrupt Disabled #0 1 Slave mode TX under run interrupt Enabled #1 SS Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0, 0 1 read-write 0 set the SPIx_SS line to inactive state.\nKeep the SPIx_SS line at inactive state #0 1 set the SPIx_SS line to active state.\nSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]) #1 SSACTIEN Slave Select Active Interrupt Enable Bit 12 1 read-write 0 Slave select active interrupt Disabled #0 1 Slave select active interrupt Enabled #1 SSACTPOL Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS). 2 1 read-write 0 The slave selection signal SPIx_SS is active low #0 1 The slave selection signal SPIx_SS is active high #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit 13 1 read-write 0 Slave select inactive interrupt Disabled #0 1 Slave select inactive interrupt Enabled #1 SPIx_STATUS SPIx_STATUS SPI Status Register 0x14 -1 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 0 1 read-only 0 SPI controller is in idle state #0 1 SPI controller is in busy state #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write 0 No FIFO is overrun #0 1 Receive FIFO is overrun #1 RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 SLVBEIF Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it. 6 1 read-write 0 No Slave mode bit count error event #0 1 Slave mode bit count error event occurred #1 SLVURIF Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 7 1 read-write 0 No Slave TX under run event #0 1 Slave TX under run event occurred #1 SPIENSTS SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. 15 1 read-only 0 SPI controller Disabled #0 1 SPI controller Enabled #1 SSACTIF Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 2 1 read-write 0 Slave select active interrupt was cleared or not occurred #0 1 Slave select active interrupt event occurred #1 SSINAIF Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 3 1 read-write 0 Slave select inactive interrupt was cleared or not occurred #0 1 Slave select inactive interrupt event occurred #1 SSLINE Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 4 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 19 1 read-write 0 No effect #0 1 No data in Transmit FIFO and TX shift register when the slave selection signal is active #1 UNITIF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 1 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 SPIx_TX SPIx_TX SPI Data Transmit Register 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.\nIn SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.\nIn I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section\nNote: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 0 32 write-only SPI2 SPI Register Map SPI 0x0 0x0 0x18 registers n 0x20 0x4 registers n 0x30 0x4 registers n 0x60 0xC registers n SPIx_CLKDIV SPIx_CLKDIV SPI Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.\nNote: Not supported in I2S mode. 0 9 read-write SPIx_CTL SPIx_CTL SPI Control Register 0x0 -1 read-write n 0x0 0x0 CLKPOL Clock Polarity 3 1 read-write 0 SPI bus clock is idle low #0 1 SPI bus clock is idle high #1 DATDIR Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer 20 1 read-write 0 SPI data is input direction #0 1 SPI data is output direction #1 DWIDTH Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically. 8 5 read-write HALFDPX SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. 14 1 read-write 0 SPI operates in full-duplex transfer #0 1 SPI operates in half-duplex transfer #1 LSB Send LSB First 13 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX) #1 REORDER Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 19 1 read-write 0 Byte Reorder function Disabled #0 1 Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV #1 RXNEG Receive on Negative Edge 1 1 read-write 0 Received data input signal is latched on the rising edge of SPI bus clock #0 1 Received data input signal is latched on the falling edge of SPI bus clock #1 RXONLY Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. 15 1 read-write 0 Receive-only mode Disabled #0 1 Receive-only mode Enabled #1 SLAVE Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SPIEN SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. 0 1 read-write 0 Transfer control Disabled #0 1 Transfer control Enabled #1 SUSPITV Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\nExample: 4 4 read-write TXNEG Transmit on Negative Edge 2 1 read-write 0 Transmitted data output signal is changed on the rising edge of SPI bus clock #0 1 Transmitted data output signal is changed on the falling edge of SPI bus clock #1 UNITIEN Unit Transfer Interrupt Enable Bit 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 SPIx_FIFOCTL SPIx_FIFOCTL SPI FIFO Control Register 0x10 -1 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared. 8 1 read-write 0 No effect #0 1 Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 RXOVIEN Receive FIFO Overrun Interrupt Enable Bit 5 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RXRST Receive Reset 0 1 read-write 0 No effect #0 1 Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 RXTH Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. 24 3 read-write RXTHIEN Receive FIFO Threshold Interrupt Enable Bit 2 1 read-write 0 RX FIFO threshold interrupt Disabled #0 1 RX FIFO threshold interrupt Enabled #1 RXTOIEN Slave Receive Time-out Interrupt Enable Bit 4 1 read-write 0 Receive time-out interrupt Disabled #0 1 Receive time-out interrupt Enabled #1 TXFBCLR Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared. 9 1 read-write 0 No effect #0 1 Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 TXRST Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. 1 1 read-write 0 No effect #0 1 Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 TXTH Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. 28 3 read-write TXTHIEN Transmit FIFO Threshold Interrupt Enable Bit 3 1 read-write 0 TX FIFO threshold interrupt Disabled #0 1 TX FIFO threshold interrupt Enabled #1 TXUFIEN TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt. 7 1 read-write 0 Slave TX underflow interrupt Disabled #0 1 Slave TX underflow interrupt Enabled #1 TXUFPOL TX Underflow Data Polarity\nNote:\n1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\n2. This bit should be set as 0 in I2S mode.\n3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. 6 1 read-write 0 The SPI data out is keep 0 if there is TX underflow event in Slave mode #0 1 The SPI data out is keep 1 if there is TX underflow event in Slave mode #1 SPIx_I2SCLK SPIx_I2SCLK I2S Clock Divider Control Register 0x64 read-write n 0x0 0x0 BCLKDIV Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock , fBCLK, is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.\nIn I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . \nThe peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. 8 10 read-write MCLKDIV Master Clock Divider\nIf MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate. 0 7 read-write SPIx_I2SCTL SPIx_I2SCTL I2S Control Register 0x60 read-write n 0x0 0x0 FORMAT Data Format Selection 28 2 read-write 0 I2S data format #00 1 MSB justified data format #01 2 PCM mode A #10 3 PCM mode B #11 I2SEN I2S Controller Enable Bit\nNote:\n1. If enabling this bit, I2Sx_BCLK will start to output in Master mode.\n2. Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. 0 1 read-write 0 I2S mode Disabled #0 1 I2S mode Enabled #1 LZCEN Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 17 1 read-write 0 Left channel zero cross detection Disabled #0 1 Left channel zero cross detection Enabled #1 LZCIEN Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs. 25 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 MCLKEN Master Clock Enable Bit\nIf MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. 15 1 read-write 0 Master clock Disabled #0 1 Master clock Enabled #1 MONO Monaural Data 6 1 read-write 0 Data is stereo format #0 1 Data is monaural format #1 MUTE Transmit Mute Enable Bit 3 1 read-write 0 Transmit data is shifted from buffer #0 1 Transmit channel zero #1 ORDER Stereo Data Order in FIFO 7 1 read-write 0 Left channel data at high byte #0 1 Left channel data at low byte #1 RXEN Receive Enable Bit 2 1 read-write 0 Data receive Disabled #0 1 Data receive Enabled #1 RXLCH Receive Left Channel Enable Bit 23 1 read-write 0 Receive right channel data in Mono mode #0 1 Receive left channel data in Mono mode #1 RZCEN Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 16 1 read-write 0 Right channel zero cross detection Disabled #0 1 Right channel zero cross detection Enabled #1 RZCIEN Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs. 24 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 SLAVE Slave Mode\nI2S can operate as master or slave. For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. 8 1 read-write 0 Master mode #0 1 Slave mode #1 TXEN Transmit Enable Bit 1 1 read-write 0 Data transmit Disabled #0 1 Data transmit Enabled #1 WDWIDTH Word Width 4 2 read-write 0 data size is 8-bit #00 1 data size is 16-bit #01 2 data size is 24-bit #10 3 data size is 32-bit #11 SPIx_I2SSTS SPIx_I2SSTS I2S Status Register 0x68 -1 read-write n 0x0 0x0 I2SENSTS I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. 15 1 read-only 0 The SPI/I2S control logic is disabled #0 1 The SPI/I2S control logic is enabled #1 LZCIF Left Channel Zero Cross Interrupt Flag 21 1 read-write 0 No zero cross event occurred on left channel #0 1 Zero cross event occurred on left channel #1 RIGHT Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel. 4 1 read-only 0 Left channel #0 1 Right channel #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 3 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 RZCIF Right Channel Zero Cross Interrupt Flag 20 1 read-write 0 No zero cross event occurred on right channel #0 1 Zero cross event occurred on right channel #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 3 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 19 1 read-write SPIx_PDMACTL SPIx_PDMACTL SPI PDMA Control Register 0xC read-write n 0x0 0x0 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0 #1 RXPDMAEN Receive PDMA Enable Bit 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPIx_RX SPIx_RX SPI Data Receive Register 0x30 read-only n 0x0 0x0 RX Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. 0 32 read-only SPIx_SSCTL SPIx_SSCTL SPI Slave Select Control Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit (Master Only) 3 1 read-write 0 Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]) #0 1 Automatic slave selection function Enabled #1 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit 8 1 read-write 0 Slave mode bit count error interrupt Disabled #0 1 Slave mode bit count error interrupt Enabled #1 SLVURIEN Slave Mode TX Under Run Interrupt Enable Bit 9 1 read-write 0 Slave mode TX under run interrupt Disabled #0 1 Slave mode TX under run interrupt Enabled #1 SS Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0, 0 1 read-write 0 set the SPIx_SS line to inactive state.\nKeep the SPIx_SS line at inactive state #0 1 set the SPIx_SS line to active state.\nSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]) #1 SSACTIEN Slave Select Active Interrupt Enable Bit 12 1 read-write 0 Slave select active interrupt Disabled #0 1 Slave select active interrupt Enabled #1 SSACTPOL Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS). 2 1 read-write 0 The slave selection signal SPIx_SS is active low #0 1 The slave selection signal SPIx_SS is active high #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit 13 1 read-write 0 Slave select inactive interrupt Disabled #0 1 Slave select inactive interrupt Enabled #1 SPIx_STATUS SPIx_STATUS SPI Status Register 0x14 -1 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 0 1 read-only 0 SPI controller is in idle state #0 1 SPI controller is in busy state #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write 0 No FIFO is overrun #0 1 Receive FIFO is overrun #1 RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 SLVBEIF Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it. 6 1 read-write 0 No Slave mode bit count error event #0 1 Slave mode bit count error event occurred #1 SLVURIF Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 7 1 read-write 0 No Slave TX under run event #0 1 Slave TX under run event occurred #1 SPIENSTS SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. 15 1 read-only 0 SPI controller Disabled #0 1 SPI controller Enabled #1 SSACTIF Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 2 1 read-write 0 Slave select active interrupt was cleared or not occurred #0 1 Slave select active interrupt event occurred #1 SSINAIF Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 3 1 read-write 0 Slave select inactive interrupt was cleared or not occurred #0 1 Slave select inactive interrupt event occurred #1 SSLINE Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 4 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 19 1 read-write 0 No effect #0 1 No data in Transmit FIFO and TX shift register when the slave selection signal is active #1 UNITIF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 1 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 SPIx_TX SPIx_TX SPI Data Transmit Register 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.\nIn SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.\nIn I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section\nNote: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 0 32 write-only SPI3 SPI Register Map SPI 0x0 0x0 0x18 registers n 0x20 0x4 registers n 0x30 0x4 registers n 0x60 0xC registers n SPIx_CLKDIV SPIx_CLKDIV SPI Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.\nNote: Not supported in I2S mode. 0 9 read-write SPIx_CTL SPIx_CTL SPI Control Register 0x0 -1 read-write n 0x0 0x0 CLKPOL Clock Polarity 3 1 read-write 0 SPI bus clock is idle low #0 1 SPI bus clock is idle high #1 DATDIR Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer 20 1 read-write 0 SPI data is input direction #0 1 SPI data is output direction #1 DWIDTH Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically. 8 5 read-write HALFDPX SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. 14 1 read-write 0 SPI operates in full-duplex transfer #0 1 SPI operates in half-duplex transfer #1 LSB Send LSB First 13 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX) #1 REORDER Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 19 1 read-write 0 Byte Reorder function Disabled #0 1 Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV #1 RXNEG Receive on Negative Edge 1 1 read-write 0 Received data input signal is latched on the rising edge of SPI bus clock #0 1 Received data input signal is latched on the falling edge of SPI bus clock #1 RXONLY Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. 15 1 read-write 0 Receive-only mode Disabled #0 1 Receive-only mode Enabled #1 SLAVE Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SPIEN SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. 0 1 read-write 0 Transfer control Disabled #0 1 Transfer control Enabled #1 SUSPITV Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\nExample: 4 4 read-write TXNEG Transmit on Negative Edge 2 1 read-write 0 Transmitted data output signal is changed on the rising edge of SPI bus clock #0 1 Transmitted data output signal is changed on the falling edge of SPI bus clock #1 UNITIEN Unit Transfer Interrupt Enable Bit 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 SPIx_FIFOCTL SPIx_FIFOCTL SPI FIFO Control Register 0x10 -1 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared. 8 1 read-write 0 No effect #0 1 Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 RXOVIEN Receive FIFO Overrun Interrupt Enable Bit 5 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RXRST Receive Reset 0 1 read-write 0 No effect #0 1 Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 RXTH Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. 24 3 read-write RXTHIEN Receive FIFO Threshold Interrupt Enable Bit 2 1 read-write 0 RX FIFO threshold interrupt Disabled #0 1 RX FIFO threshold interrupt Enabled #1 RXTOIEN Slave Receive Time-out Interrupt Enable Bit 4 1 read-write 0 Receive time-out interrupt Disabled #0 1 Receive time-out interrupt Enabled #1 TXFBCLR Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared. 9 1 read-write 0 No effect #0 1 Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 TXRST Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. 1 1 read-write 0 No effect #0 1 Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 TXTH Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. 28 3 read-write TXTHIEN Transmit FIFO Threshold Interrupt Enable Bit 3 1 read-write 0 TX FIFO threshold interrupt Disabled #0 1 TX FIFO threshold interrupt Enabled #1 TXUFIEN TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt. 7 1 read-write 0 Slave TX underflow interrupt Disabled #0 1 Slave TX underflow interrupt Enabled #1 TXUFPOL TX Underflow Data Polarity\nNote:\n1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\n2. This bit should be set as 0 in I2S mode.\n3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. 6 1 read-write 0 The SPI data out is keep 0 if there is TX underflow event in Slave mode #0 1 The SPI data out is keep 1 if there is TX underflow event in Slave mode #1 SPIx_I2SCLK SPIx_I2SCLK I2S Clock Divider Control Register 0x64 read-write n 0x0 0x0 BCLKDIV Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock , fBCLK, is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.\nIn I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . \nThe peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. 8 10 read-write MCLKDIV Master Clock Divider\nIf MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate. 0 7 read-write SPIx_I2SCTL SPIx_I2SCTL I2S Control Register 0x60 read-write n 0x0 0x0 FORMAT Data Format Selection 28 2 read-write 0 I2S data format #00 1 MSB justified data format #01 2 PCM mode A #10 3 PCM mode B #11 I2SEN I2S Controller Enable Bit\nNote:\n1. If enabling this bit, I2Sx_BCLK will start to output in Master mode.\n2. Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. 0 1 read-write 0 I2S mode Disabled #0 1 I2S mode Enabled #1 LZCEN Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 17 1 read-write 0 Left channel zero cross detection Disabled #0 1 Left channel zero cross detection Enabled #1 LZCIEN Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs. 25 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 MCLKEN Master Clock Enable Bit\nIf MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. 15 1 read-write 0 Master clock Disabled #0 1 Master clock Enabled #1 MONO Monaural Data 6 1 read-write 0 Data is stereo format #0 1 Data is monaural format #1 MUTE Transmit Mute Enable Bit 3 1 read-write 0 Transmit data is shifted from buffer #0 1 Transmit channel zero #1 ORDER Stereo Data Order in FIFO 7 1 read-write 0 Left channel data at high byte #0 1 Left channel data at low byte #1 RXEN Receive Enable Bit 2 1 read-write 0 Data receive Disabled #0 1 Data receive Enabled #1 RXLCH Receive Left Channel Enable Bit 23 1 read-write 0 Receive right channel data in Mono mode #0 1 Receive left channel data in Mono mode #1 RZCEN Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 16 1 read-write 0 Right channel zero cross detection Disabled #0 1 Right channel zero cross detection Enabled #1 RZCIEN Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs. 24 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 SLAVE Slave Mode\nI2S can operate as master or slave. For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. 8 1 read-write 0 Master mode #0 1 Slave mode #1 TXEN Transmit Enable Bit 1 1 read-write 0 Data transmit Disabled #0 1 Data transmit Enabled #1 WDWIDTH Word Width 4 2 read-write 0 data size is 8-bit #00 1 data size is 16-bit #01 2 data size is 24-bit #10 3 data size is 32-bit #11 SPIx_I2SSTS SPIx_I2SSTS I2S Status Register 0x68 -1 read-write n 0x0 0x0 I2SENSTS I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. 15 1 read-only 0 The SPI/I2S control logic is disabled #0 1 The SPI/I2S control logic is enabled #1 LZCIF Left Channel Zero Cross Interrupt Flag 21 1 read-write 0 No zero cross event occurred on left channel #0 1 Zero cross event occurred on left channel #1 RIGHT Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel. 4 1 read-only 0 Left channel #0 1 Right channel #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 3 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 RZCIF Right Channel Zero Cross Interrupt Flag 20 1 read-write 0 No zero cross event occurred on right channel #0 1 Zero cross event occurred on right channel #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 3 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 19 1 read-write SPIx_PDMACTL SPIx_PDMACTL SPI PDMA Control Register 0xC read-write n 0x0 0x0 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0 #1 RXPDMAEN Receive PDMA Enable Bit 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPIx_RX SPIx_RX SPI Data Receive Register 0x30 read-only n 0x0 0x0 RX Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. 0 32 read-only SPIx_SSCTL SPIx_SSCTL SPI Slave Select Control Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit (Master Only) 3 1 read-write 0 Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]) #0 1 Automatic slave selection function Enabled #1 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit 8 1 read-write 0 Slave mode bit count error interrupt Disabled #0 1 Slave mode bit count error interrupt Enabled #1 SLVURIEN Slave Mode TX Under Run Interrupt Enable Bit 9 1 read-write 0 Slave mode TX under run interrupt Disabled #0 1 Slave mode TX under run interrupt Enabled #1 SS Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0, 0 1 read-write 0 set the SPIx_SS line to inactive state.\nKeep the SPIx_SS line at inactive state #0 1 set the SPIx_SS line to active state.\nSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]) #1 SSACTIEN Slave Select Active Interrupt Enable Bit 12 1 read-write 0 Slave select active interrupt Disabled #0 1 Slave select active interrupt Enabled #1 SSACTPOL Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS). 2 1 read-write 0 The slave selection signal SPIx_SS is active low #0 1 The slave selection signal SPIx_SS is active high #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit 13 1 read-write 0 Slave select inactive interrupt Disabled #0 1 Slave select inactive interrupt Enabled #1 SPIx_STATUS SPIx_STATUS SPI Status Register 0x14 -1 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 0 1 read-only 0 SPI controller is in idle state #0 1 SPI controller is in busy state #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write 0 No FIFO is overrun #0 1 Receive FIFO is overrun #1 RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 SLVBEIF Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it. 6 1 read-write 0 No Slave mode bit count error event #0 1 Slave mode bit count error event occurred #1 SLVURIF Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 7 1 read-write 0 No Slave TX under run event #0 1 Slave TX under run event occurred #1 SPIENSTS SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. 15 1 read-only 0 SPI controller Disabled #0 1 SPI controller Enabled #1 SSACTIF Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 2 1 read-write 0 Slave select active interrupt was cleared or not occurred #0 1 Slave select active interrupt event occurred #1 SSINAIF Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 3 1 read-write 0 Slave select inactive interrupt was cleared or not occurred #0 1 Slave select inactive interrupt event occurred #1 SSLINE Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 4 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 19 1 read-write 0 No effect #0 1 No data in Transmit FIFO and TX shift register when the slave selection signal is active #1 UNITIF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 1 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 SPIx_TX SPIx_TX SPI Data Transmit Register 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.\nIn SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.\nIn I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section\nNote: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 0 32 write-only SYS SYS Register Map SYS 0x0 0x0 0x14 registers n 0x100 0x4 registers n 0x18 0x8 registers n 0x1EC 0x4 registers n 0x1F8 0x8 registers n 0x24 0x4C registers n 0x80 0x20 registers n 0xC0 0xC registers n 0xDC 0x20 registers n BODCTL SYS_BODCTL Brown-out Detector Control Register 0x18 -1 read-write n 0x0 0x0 BODDGSEL Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 8 3 read-write 0 BOD output is sampled by LIRC clock #000 1 4 system clock (HCLK) #001 2 8 system clock (HCLK) #010 3 16 system clock (HCLK) #011 4 32 system clock (HCLK) #100 5 64 system clock (HCLK) #101 6 128 system clock (HCLK) #110 7 256 system clock (HCLK) #111 BODEN Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBODEN (CONFIG0 [23]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Brown-out Detector function Disabled #0 1 Brown-out Detector function Enabled #1 BODIF Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0. 4 1 read-write 0 Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting #0 1 When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled #1 BODLPM Brown-out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 BOD operate in normal mode (default) #0 1 BOD Low Power mode Enabled #1 BODOUT Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled, this bit always responds 0. 6 1 read-write 0 Brown-out Detector output status is 0 #0 1 Brown-out Detector output status is 1 #1 BODRSTEN Brown-out Reset Enable Bit (Write Protect) The default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit . Note1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if AVDD.than BODVL, BOD interrupt will keep till to the BODIF set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 Brown-out 'INTERRUPT' function Enabled #0 1 Brown-out 'RESET' function Enabled #1 BODVL Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by Flash controller user configuration register CBOV (CONFIG0 [23:21]).\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 16 3 read-write 0 Brown-out Detector threshold voltage is 1.6V #000 1 Brown-out Detector threshold voltage is 1.8V #001 2 Brown-out Detector threshold voltage is 2.0V #010 3 Brown-out Detector threshold voltage is 2.2V #011 4 Brown-out Detector threshold voltage is 2.4V #100 5 Brown-out Detector threshold voltage is 2.6V #101 6 Brown-out Detector threshold voltage is 2.8V #110 7 Brown-out Detector threshold voltage is 3.0V #111 LVRDGSEL LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 12 3 read-write 0 Without de-glitch function #000 1 4 system clock (HCLK) #001 2 8 system clock (HCLK) #010 3 16 system clock (HCLK) #011 4 32 system clock (HCLK) #100 5 64 system clock (HCLK) #101 6 128 system clock (HCLK) #110 7 256 system clock (HCLK) #111 LVREN Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Low Voltage Reset function Disabled #0 1 Low Voltage Reset function Enabled #1 GPA_MFOS SYS_GPA_MFOS GPIOA Multiple Function Output Select Register 0x80 read-write n 0x0 0x0 MFOS0 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 0 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS1 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 1 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS10 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 10 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS11 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 11 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS12 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 12 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS13 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 13 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS14 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 14 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS15 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 15 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS2 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 2 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS3 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 3 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS4 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 4 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS5 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 5 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS6 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 6 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS7 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 7 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS8 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 8 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 MFOS9 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin 9 1 read-write 0 Multiple funtion pin output mode type is Push-pull mode #0 1 Multiple funtion pin output mode type is Open-drain mode #1 GPA_MFPH SYS_GPA_MFPH GPIOA High Byte Multiple Function Control Register 0x34 read-write n 0x0 0x0 PA10MFP PA.10 Multi-function Pin Selection 8 4 read-write PA11MFP PA.11 Multi-function Pin Selection 12 4 read-write PA12MFP PA.12 Multi-function Pin Selection 16 4 read-write PA13MFP PA.13 Multi-function Pin Selection 20 4 read-write PA14MFP PA.14 Multi-function Pin Selection 24 4 read-write PA15MFP PA.15 Multi-function Pin Selection 28 4 read-write PA8MFP PA.8 Multi-function Pin Selection 0 4 read-write PA9MFP PA.9 Multi-function Pin Selection 4 4 read-write GPA_MFPL SYS_GPA_MFPL GPIOA Low Byte Multiple Function Control Register 0x30 read-write n 0x0 0x0 PA0MFP PA.0 Multi-function Pin Selection 0 4 read-write PA1MFP PA.1 Multi-function Pin Selection 4 4 read-write PA2MFP PA.2 Multi-function Pin Selection 8 4 read-write PA3MFP PA.3 Multi-function Pin Selection 12 4 read-write PA4MFP PA.4 Multi-function Pin Selection 16 4 read-write PA5MFP PA.5 Multi-function Pin Selection 20 4 read-write PA6MFP PA.6 Multi-function Pin Selection 24 4 read-write PA7MFP PA.7 Multi-function Pin Selection 28 4 read-write GPB_MFOS SYS_GPB_MFOS GPIOB Multiple Function Output Select Register 0x84 read-write n 0x0 0x0 GPB_MFPH SYS_GPB_MFPH GPIOB High Byte Multiple Function Control Register 0x3C read-write n 0x0 0x0 PB10MFP PB.10 Multi-function Pin Selection 8 4 read-write PB11MFP PB.11 Multi-function Pin Selection 12 4 read-write PB12MFP PB.12 Multi-function Pin Selection 16 4 read-write PB13MFP PB.13 Multi-function Pin Selection 20 4 read-write PB14MFP PB.14 Multi-function Pin Selection 24 4 read-write PB15MFP PB.15 Multi-function Pin Selection 28 4 read-write PB8MFP PB.8 Multi-function Pin Selection 0 4 read-write PB9MFP PB.9 Multi-function Pin Selection 4 4 read-write GPB_MFPL SYS_GPB_MFPL GPIOB Low Byte Multiple Function Control Register 0x38 read-write n 0x0 0x0 PB0MFP PB.0 Multi-function Pin Selection 0 4 read-write PB1MFP PB.1 Multi-function Pin Selection 4 4 read-write PB2MFP PB.2 Multi-function Pin Selection 8 4 read-write PB3MFP PB.3 Multi-function Pin Selection 12 4 read-write PB4MFP PB.4 Multi-function Pin Selection 16 4 read-write PB5MFP PB.5 Multi-function Pin Selection 20 4 read-write PB6MFP PB.6 Multi-function Pin Selection 24 4 read-write PB7MFP PB.7 Multi-function Pin Selection 28 4 read-write GPC_MFOS SYS_GPC_MFOS GPIOC Multiple Function Output Select Register 0x88 read-write n 0x0 0x0 GPC_MFPH SYS_GPC_MFPH GPIOC High Byte Multiple Function Control Register 0x44 read-write n 0x0 0x0 PC10MFP PC.10 Multi-function Pin Selection 8 4 read-write PC11MFP PC.11 Multi-function Pin Selection 12 4 read-write PC12MFP PC.12 Multi-function Pin Selection 16 4 read-write PC13MFP PC.13 Multi-function Pin Selection 20 4 read-write PC8MFP PC.8 Multi-function Pin Selection 0 4 read-write PC9MFP PC.9 Multi-function Pin Selection 4 4 read-write GPC_MFPL SYS_GPC_MFPL GPIOC Low Byte Multiple Function Control Register 0x40 read-write n 0x0 0x0 PC0MFP PC.0 Multi-function Pin Selection 0 4 read-write PC1MFP PC.1 Multi-function Pin Selection 4 4 read-write PC2MFP PC.2 Multi-function Pin Selection 8 4 read-write PC3MFP PC.3 Multi-function Pin Selection 12 4 read-write PC4MFP PC.4 Multi-function Pin Selection 16 4 read-write PC5MFP PC.5 Multi-function Pin Selection 20 4 read-write PC6MFP PC.6 Multi-function Pin Selection 24 4 read-write PC7MFP PC.7 Multi-function Pin Selection 28 4 read-write GPD_MFOS SYS_GPD_MFOS GPIOD Multiple Function Output Select Register 0x8C read-write n 0x0 0x0 GPD_MFPH SYS_GPD_MFPH GPIOD High Byte Multiple Function Control Register 0x4C read-write n 0x0 0x0 PD10MFP PD.10 Multi-function Pin Selection 8 4 read-write PD11MFP PD.11 Multi-function Pin Selection 12 4 read-write PD12MFP PD.12 Multi-function Pin Selection 16 4 read-write PD13MFP PD.13 Multi-function Pin Selection 20 4 read-write PD14MFP PD.14 Multi-function Pin Selection 24 4 read-write PD8MFP PD.8 Multi-function Pin Selection 0 4 read-write PD9MFP PD.9 Multi-function Pin Selection 4 4 read-write GPD_MFPL SYS_GPD_MFPL GPIOD Low Byte Multiple Function Control Register 0x48 read-write n 0x0 0x0 PD0MFP PD.0 Multi-function Pin Selection 0 4 read-write PD1MFP PD.1 Multi-function Pin Selection 4 4 read-write PD2MFP PD.2 Multi-function Pin Selection 8 4 read-write PD3MFP PD.3 Multi-function Pin Selection 12 4 read-write PD4MFP PD.4 Multi-function Pin Selection 16 4 read-write PD5MFP PD.5 Multi-function Pin Selection 20 4 read-write PD6MFP PD.6 Multi-function Pin Selection 24 4 read-write PD7MFP PD.7 Multi-function Pin Selection 28 4 read-write GPE_MFOS SYS_GPE_MFOS GPIOE Multiple Function Output Select Register 0x90 read-write n 0x0 0x0 GPE_MFPH SYS_GPE_MFPH GPIOE High Byte Multiple Function Control Register 0x54 read-write n 0x0 0x0 PE10MFP PE.10 Multi-function Pin Selection 8 4 read-write PE11MFP PE.11 Multi-function Pin Selection 12 4 read-write PE12MFP PE.12 Multi-function Pin Selection 16 4 read-write PE13MFP PE.13 Multi-function Pin Selection 20 4 read-write PE14MFP PE.14 Multi-function Pin Selection 24 4 read-write PE15MFP PE.15 Multi-function Pin Selection 28 4 read-write PE8MFP PE.8 Multi-function Pin Selection 0 4 read-write PE9MFP PE.9 Multi-function Pin Selection 4 4 read-write GPE_MFPL SYS_GPE_MFPL GPIOE Low Byte Multiple Function Control Register 0x50 read-write n 0x0 0x0 PE0MFP PE.0 Multi-function Pin Selection 0 4 read-write PE1MFP PE.1 Multi-function Pin Selection 4 4 read-write PE2MFP PE.2 Multi-function Pin Selection 8 4 read-write PE3MFP PE.3 Multi-function Pin Selection 12 4 read-write PE4MFP PE.4 Multi-function Pin Selection 16 4 read-write PE5MFP PE.5 Multi-function Pin Selection 20 4 read-write PE6MFP PE.6 Multi-function Pin Selection 24 4 read-write PE7MFP PE.7 Multi-function Pin Selection 28 4 read-write GPF_MFOS SYS_GPF_MFOS GPIOF Multiple Function Output Select Register 0x94 read-write n 0x0 0x0 GPF_MFPH SYS_GPF_MFPH GPIOF High Byte Multiple Function Control Register 0x5C read-write n 0x0 0x0 PF10MFP PF.10 Multi-function Pin Selection 8 4 read-write PF11MFP PF.11 Multi-function Pin Selection 12 4 read-write PF8MFP PF.8 Multi-function Pin Selection 0 4 read-write PF9MFP PF.9 Multi-function Pin Selection 4 4 read-write GPF_MFPL SYS_GPF_MFPL GPIOF Low Byte Multiple Function Control Register 0x58 -1 read-write n 0x0 0x0 PF0MFP PF.0 Multi-function Pin Selection 0 4 read-write PF1MFP PF.1 Multi-function Pin Selection 4 4 read-write PF2MFP PF.2 Multi-function Pin Selection 8 4 read-write PF3MFP PF.3 Multi-function Pin Selection 12 4 read-write PF4MFP PF.4 Multi-function Pin Selection 16 4 read-write PF5MFP PF.5 Multi-function Pin Selection 20 4 read-write PF6MFP PF.6 Multi-function Pin Selection 24 4 read-write PF7MFP PF.7 Multi-function Pin Selection 28 4 read-write GPG_MFOS SYS_GPG_MFOS GPIOG Multiple Function Output Select Register 0x98 read-write n 0x0 0x0 GPG_MFPH SYS_GPG_MFPH GPIOG High Byte Multiple Function Control Register 0x64 read-write n 0x0 0x0 PG10MFP PG.10 Multi-function Pin Selection 8 4 read-write PG11MFP PG.11 Multi-function Pin Selection 12 4 read-write PG12MFP PG.12 Multi-function Pin Selection 16 4 read-write PG13MFP PG.13 Multi-function Pin Selection 20 4 read-write PG14MFP PG.14 Multi-function Pin Selection 24 4 read-write PG15MFP PG.15 Multi-function Pin Selection 28 4 read-write PG8MFP PG.8 Multi-function Pin Selection 0 4 read-write PG9MFP PG.9 Multi-function Pin Selection 4 4 read-write GPG_MFPL SYS_GPG_MFPL GPIOG Low Byte Multiple Function Control Register 0x60 read-write n 0x0 0x0 PG2MFP PG.2 Multi-function Pin Selection 8 4 read-write PG3MFP PG.3 Multi-function Pin Selection 12 4 read-write PG4MFP PG.4 Multi-function Pin Selection 16 4 read-write GPH_MFOS SYS_GPH_MFOS GPIOH Multiple Function Output Select Register 0x9C read-write n 0x0 0x0 GPH_MFPH SYS_GPH_MFPH GPIOH High Byte Multiple Function Control Register 0x6C read-write n 0x0 0x0 PH10MFP PH.10 Multi-function Pin Selection 8 4 read-write PH11MFP PH.11 Multi-function Pin Selection 12 4 read-write PH8MFP PH.8 Multi-function Pin Selection 0 4 read-write PH9MFP PH.9 Multi-function Pin Selection 4 4 read-write GPH_MFPL SYS_GPH_MFPL GPIOH Low Byte Multiple Function Control Register 0x68 read-write n 0x0 0x0 PH4MFP PH.4 Multi-function Pin Selection 16 4 read-write PH5MFP PH.5 Multi-function Pin Selection 20 4 read-write PH6MFP PH.6 Multi-function Pin Selection 24 4 read-write PH7MFP PH.7 Multi-function Pin Selection 28 4 read-write IPRST0 SYS_IPRST0 Peripheral Reset Control Register 0 0x8 read-write n 0x0 0x0 CHIPRST Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload.\nAbout the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Chip normal operation #0 1 Chip one-shot reset #1 CPURST Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Processor core normal operation #0 1 Processor core one-shot reset #1 CRCRST CRC Calculation Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 CRC calculation controller normal operation #0 1 CRC calculation controller reset #1 CRPTRST CRYPTO Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CRYPTO controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 12 1 read-write 0 CRYPTO controller normal operation #0 1 CRYPTO controller reset #1 EBIRST EBI Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 EBI controller normal operation #0 1 EBI controller reset #1 PDMA0RST PDMA0 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA0. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 PDMA0 controller normal operation #0 1 PDMA0 controller reset #1 PDMA1RST PDMA1 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA1. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 29 1 read-write 0 PDMA1 controller normal operation #0 1 PDMA1 controller reset #1 SDH0RST SDHOST0 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the SDHOST0 controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 SDHOST0 controller normal operation #0 1 SDHOST0 controller reset #1 USBHRST USB Host Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the USB Host. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 USB Host controller normal operation #0 1 USB Host controller reset #1 IPRST1 SYS_IPRST1 Peripheral Reset Control Register 1 0xC read-write n 0x0 0x0 ACMP01RST Analog Comparator 0/1 Controller Reset 7 1 read-write 0 Analog Comparator 0/1 controller normal operation #0 1 Analog Comparator 0/1 controller reset #1 CAN0RST CAN0 Controller Reset 24 1 read-write 0 CAN0 controller normal operation #0 1 CAN0 controller reset #1 EADCRST EADC Controller Reset 28 1 read-write 0 EADC controller normal operation #0 1 EADC controller reset #1 GPIORST GPIO Controller Reset 1 1 read-write 0 GPIO controller normal operation #0 1 GPIO controller reset #1 I2C0RST I2C0 Controller Reset 8 1 read-write 0 I2C0 controller normal operation #0 1 I2C0 controller reset #1 I2C1RST I2C1 Controller Reset 9 1 read-write 0 I2C1 controller normal operation #0 1 I2C1 controller reset #1 I2C2RST I2C2 Controller Reset 10 1 read-write 0 I2C2 controller normal operation #0 1 I2C2 controller reset #1 I2S0RST I2S0 Controller Reset 29 1 read-write 0 I2S0 controller normal operation #0 1 I2S0 controller reset #1 OTGRST OTG Controller Reset 26 1 read-write 0 OTG controller normal operation #0 1 OTG controller reset #1 QSPI0RST QSPI0 Controller Reset 12 1 read-write 0 QSPI0 controller normal operation #0 1 QSPI0 controller reset #1 SPI0RST SPI0 Controller Reset 13 1 read-write 0 SPI0 controller normal operation #0 1 SPI0 controller reset #1 SPI1RST SPI1 Controller Reset 14 1 read-write 0 SPI1 controller normal operation #0 1 SPI1 controller reset #1 SPI2RST SPI2 Controller Reset 15 1 read-write 0 SPI2 controller normal operation #0 1 SPI2 controller reset #1 TMR0RST Timer0 Controller Reset 2 1 read-write 0 Timer0 controller normal operation #0 1 Timer0 controller reset #1 TMR1RST Timer1 Controller Reset 3 1 read-write 0 Timer1 controller normal operation #0 1 Timer1 controller reset #1 TMR2RST Timer2 Controller Reset 4 1 read-write 0 Timer2 controller normal operation #0 1 Timer2 controller reset #1 TMR3RST Timer3 Controller Reset 5 1 read-write 0 Timer3 controller normal operation #0 1 Timer3 controller reset #1 TRNGRST TRNG Controller Reset 31 1 read-write 0 TRNG controller normal operation #0 1 TRNG controller reset #1 UART0RST UART0 Controller Reset 16 1 read-write 0 UART0 controller normal operation #0 1 UART0 controller reset #1 UART1RST UART1 Controller Reset 17 1 read-write 0 UART1 controller normal operation #0 1 UART1 controller reset #1 UART2RST UART2 Controller Reset 18 1 read-write 0 UART2 controller normal operation #0 1 UART2 controller reset #1 UART3RST UART3 Controller Reset 19 1 read-write 0 UART3 controller normal operation #0 1 UART3 controller reset #1 UART4RST UART4 Controller Reset 20 1 read-write 0 UART4 controller normal operation #0 1 UART4 controller reset #1 UART5RST UART5 Controller Reset 21 1 read-write 0 UART5 controller normal operation #0 1 UART5 controller reset #1 USBDRST USBD Controller Reset 27 1 read-write 0 USBD controller normal operation #0 1 USBD controller reset #1 IPRST2 SYS_IPRST2 Peripheral Reset Control Register 2 0x10 read-write n 0x0 0x0 BPWM0RST BPWM0 Controller Reset 18 1 read-write 0 BPWM0 controller normal operation #0 1 BPWM0 controller reset #1 BPWM1RST BPWM1 Controller Reset 19 1 read-write 0 BPWM1 controller normal operation #0 1 BPWM1 controller reset #1 DACRST DAC Controller Reset 12 1 read-write 0 DAC controller normal operation #0 1 DAC controller reset #1 ECAP0RST ECAP0 Controller Reset 26 1 read-write 0 ECAP0 controller normal operation #0 1 ECAP0 controller reset #1 ECAP1RST ECAP1 Controller Reset 27 1 read-write 0 ECAP1 controller normal operation #0 1 ECAP1 controller reset #1 EPWM0RST EPWM0 Controller Reset 16 1 read-write 0 EPWM0 controller normal operation #0 1 EPWM0 controller reset #1 EPWM1RST EPWM1 Controller Reset 17 1 read-write 0 EPWM1 controller normal operation #0 1 EPWM1 controller reset #1 QEI0RST QEI0 Controller Reset 22 1 read-write 0 QEI0 controller normal operation #0 1 QEI0 controller reset #1 QEI1RST QEI1 Controller Reset 23 1 read-write 0 QEI1 controller normal operation #0 1 QEI1 controller reset #1 SC0RST SC0 Controller Reset 0 1 read-write 0 SC0 controller normal operation #0 1 SC0 controller reset #1 SC1RST SC1 Controller Reset 1 1 read-write 0 SC1 controller normal operation #0 1 SC1 controller reset #1 SC2RST SC2 Controller Reset 2 1 read-write 0 SC2 controller normal operation #0 1 SC2 controller reset #1 SPI3RST SPI3 Controller Reset 6 1 read-write 0 SPI3 controller normal operation #0 1 SPI3 controller reset #1 USCI0RST USCI0 Controller Reset 8 1 read-write 0 USCI0 controller normal operation #0 1 USCI0 controller reset #1 USCI1RST USCI1 Controller Reset 9 1 read-write 0 USCI1 controller normal operation #0 1 USCI1 controller reset #1 IVSCTL SYS_IVSCTL Internal Voltage Source Control Register 0x1C read-write n 0x0 0x0 VBATUGEN VBAT Unity Gain Buffer Enable Bit\nThis bit is used to enable/disable VBAT unity gain buffer function.\nNote: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result. 1 1 read-write 0 VBAT unity gain buffer function Disabled (default) #0 1 VBAT unity gain buffer function Enabled #1 VTEMPEN Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function chapter for details. 0 1 read-write 0 Temperature sensor function Disabled (default) #0 1 Temperature sensor function Enabled #1 PDID SYS_PDID Part Device Identification Number Register 0x0 -1 read-only n 0x0 0x0 PDID Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used. 0 32 read-only PLCTL SYS_PLCTL Power Level Control Register 0x1F8 read-write n 0x0 0x0 LVSPRD LDO Voltage Scaling Period (Write Protect)\nThe LVSPRD value is the period of each LDO voltage rising step.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 24 8 read-write LVSSTEP LDO Voltage Scaling Step (Write Protect)\nThe LVSSTEP value is LDO voltage rising step.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 16 6 read-write MVRS Main Voltage Regulator Type Select (Write Protect)\nThis bit filed sets main voltage regulator type.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 Set main voltage regulator to LDO #0 1 Set main voltage regulator to DCDC #1 PLSEL Power Level Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 0 2 read-write 0 Set to Power level 0 (PL0) #00 1 Set to Power level 1 (PL1) #01 PLSTS SYS_PLSTS Power Level Status Register 0x1FC read-write n 0x0 0x0 CURMVR Current Main Voltage Regulator Type (Read Only)\nThis bit field reflects current main voltage regulator type. 12 1 read-only 0 Current main voltage regulator in active and Idle mode is LDO #0 1 Current main voltage regulator in active mode and Idle is DCDC #1 LCONS Inductor for DC-dC Connect Status (Read Only) \nNote: This bit is 1 when main viltage regulator is LDO. 3 1 read-only 0 Inductor connect between Vsw and LDO_CAP pin #0 1 No Inductor connect between Vsw and LDO_CAP pin #1 MVRCBUSY Main Voltage Regulator Type Change Busy Bit (Read Only)\nThis bit is set by hardware when main voltage regulator type is changing. After main voltage regulator type change is completed, this bit will be cleared automatically by hardware. 1 1 read-only 0 Main voltage regulator type change is completed #0 1 Main voltage regulator type change is ongoing #1 MVRCERR Main Voltage Regulator Type Change Error Bit (Write Protect)\nThis bit Is set by Hardware When Main Voltage Regulator Type Change From LDO to DCDC Error Occurred\nThis bit is set to 1 when main voltage regulator type change from LDO to DCDC error, the following conditions will cause change errors\n1.System change to DC-DC mode but LDO change voltage process not finish\n2.Detect inductor fail.\n\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 No main voltage regulator type change error.\nNo effect #0 1 Main voltage regulator type change to DCDC error occurred.\nClears MVRCERR to 0 #1 PDINVTRF Power-down Mode Invalid Transition Flag (Write Protect)\nThis bit is set by hardware if the requested active DCDC mode to Power-down mode transition is invalid. This transition request will be aborted by hardware. The bit can be cleared by software.\nRead:\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 No Power-dwon mode invalid transition.\nNo effect #0 1 Power-dwon mode invalid transition occurred.\nClears this bit to 0 #1 PLCBUSY Power Level Change Busy Bit (Read Only)\nThis bit is set by hardware when power level is changing . After power level change is completed, this bit will be cleared automatically by hardware. 0 1 read-only 0 Power level change is completed #0 1 Power level change is ongoing #1 PLSTATUS Power Level Status (Read Only)\nThis bit field reflect the current power level. 8 2 read-only 0 Power level is PL0 #00 1 Power level is PL1 #01 PORCTL0 SYS_PORCTL0 Power-on Reset Controller Register 0 0x24 read-write n 0x0 0x0 PORMASK Power-on Reset Mask Enable Bit (Write Protect)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can mask internal POR signal to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will be active again when this field is set to another value or chip is reset by other reset source, including:\nnRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 0 16 read-write PORCTL1 SYS_PORCTL1 Power-on Reset Controller Register 1 0x1EC read-write n 0x0 0x0 POROFF Power-on Reset Enable Bit (Write Protect)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will be active again when this field is set to another value or chip is reset by other reset source, including:\nnRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 0 16 read-write REGLCTL SYS_REGLCTL Register Lock Control Register 0x100 read-write n 0x0 0x0 REGLCTL Register Lock Control Code \nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.\n\nREGLCTL[0]\nRegister Lock Control Disable Index 0 8 read-write 0 Write-protection Enabled for writing protected registers. Any write to the protected register is ignored 0 1 Write-protection Disabled for writing protected registers 1 RSTSTS SYS_RSTSTS System Reset Status Register 0x4 -1 read-write n 0x0 0x0 BODRF BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0. 4 1 read-write 0 No reset from BOD #0 1 The BOD had issued the reset signal to reset the system #1 CPULKRF CPU Lockup Reset Flag\nThe CPU Lockup reset flag is set by hardware if Cortex-M23 lockup happened.\nNote1: Write 1 to clear this bit to 0.\nNote2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset. 8 1 read-write 0 No reset from CPU lockup happened #0 1 The Cortex-M23 lockup happened and chip is reset #1 CPURF CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset the Cortex-M23 core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0. 7 1 read-write 0 No reset from CPU #0 1 The Cortex-M23 Core and FMC are reset by software setting CPURST to 1 #1 LVRF LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0. 3 1 read-write 0 No reset from LVR #0 1 LVR controller had issued the reset signal to reset the system #1 PINRF nRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0. 1 1 read-write 0 No reset from nRESET pin #0 1 Pin nRESET had issued the reset signal to reset the system #1 PORF POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0. 0 1 read-write 0 No reset from POR or CHIPRST #0 1 Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system #1 SYSRF System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M23 Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0. 5 1 read-write 0 No reset from the Cortex-M23 #0 1 The Cortex-M23 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M23 core #1 WDTRF WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote1: Write 1 to clear this bit to 0.\nNote2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. 2 1 read-write 0 No reset from watchdog timer or window watchdog timer #0 1 The watchdog timer or window watchdog timer had issued the reset signal to reset the system #1 SRAMEADR SYS_SRAMEADR System SRAM Parity Check Error Address Register 0xC8 read-only n 0x0 0x0 ERRADDR System SRAM Parity Error Address\nThis register shows system SRAM parity error byte address. 0 32 read-only SRAMICTL SYS_SRAMICTL System SRAM Interrupt Enable Control Register 0xC0 read-write n 0x0 0x0 PERRIEN SRAM Parity Check Error Interrupt Enable Bit 0 1 read-write 0 SRAM parity check error interrupt Disabled #0 1 SRAM parity check error interrupt Enabled #1 SRAMPCTL SYS_SRAMPCTL System SRAM Power Mode Control Register 0xDC -1 read-write n 0x0 0x0 RETCNT SRAM Retention Count (Write Protect)\nThis field can configure SRAM marco retention time in unit of HIRC period.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 4 2 read-write 0 one HIRC period #00 1 two HIRC periods #01 2 three HIRC periods #10 3 four HIRC periods #11 SRAM0PM0 Bank0 SRAM Power Mode Select 0 (Write Protect)\nThis field can control bank0 SRAM (32 KB) power mode when system enters Power-down mode for range 0x2000_0000 - 0x2000_1FFF.\nNote1: Bank 0 SRAM is always operating in power shut down mode for system enter Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register. 8 2 read-write 0 Normal mode #00 1 Retention mode #01 2 Power shut down mode #10 3 Reserved (Write Ignore) #11 SRAM0PM1 Bank0 SRAM Power Mode Select 1 (Write Protect)\nThis field can control bank0 sram (32k) power mode when system enters Power-down mode for range 0x2000_2000 - 0x2000_3FFF.\nNote1: Bank 0 SRAM is always operating in power shut down mode for system enter Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register. 10 2 read-write 0 Normal mode #00 1 Retention mode #01 2 Power shut down mode #10 3 Reserved (Write Ignore) #11 SRAM0PM2 Bank0 SRAM Power Mode Select 2 (Write Protect)\nThis field can control bank0 SRAM (32 KB) power mode when system enters Power-down mode for range 0x2004_0000 - 0x2000_5FFF.\nNote1: Bank 0 SRAM is always operating in power shut down mode for system enter Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register. 12 2 read-write 0 Normal mode #00 1 Retention mode #01 2 Power shut down mode #10 3 Reserved (Write Ignore) #11 SRAM0PM3 Bank0 SRAM Power Mode Select 3 (Write Protect)\nThis field can control bank0 SRAM (32 KB) power mode when system enters Power-down mode for range 0x2006_0000 - 0x2000_7FFF.\nNote1: Bank 0 SRAM is always operating in power shut down mode for system enter Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register. 14 2 read-write 0 Normal mode #00 1 Retention mode #01 2 Power shut down mode #10 3 Reserved (Write Ignore) #11 SRAM1PM0 Bank1 SRAM Power Mode Select 0 (Write Protect)\nThis field can control bank1 SRAM (64 KB) power mode when system enters Power-down mode for range 0x2000_8000 - 0x2000_BFFF.\nNote1: Bank 1 SRAM is always operating in power shut down mode for system enter StandbyPower-down Mode (SPD) and Deep Power-down Mode (DPD). \nNote2: These bits are write protected. Refer to the SYS_REGLCTL register. 16 2 read-write 0 Normal mode #00 1 Retention mode #01 2 Power shut down mode #10 3 Reserved (Write Ignore) #11 SRAM1PM1 Bank1 SRAM Power Mode Select 1 (Write Protect)\nThis field can control bank1 SRAM (64 KB) power mode when system enters Power-down mode for range 0x2000_C000 - 0x2000_FFFF.\nNote1: Bank 1 SRAM is always operating in power shut down mode for system enter StandbyPower-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register. 18 2 read-write 0 Normal mode #00 1 Retention mode #01 2 Power shut down mode #10 3 Reserved (Write Ignore) #11 SRAM1PM2 Bank1 SRAM Power Mode Select 2 (Write Protect)\nThis field can control bank1 SRAM (64 KB) power mode when system enters Power-down mode for range 0x2001_0000 - 0x2001_3FFF.\nNote1: Bank 1 SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register. 20 2 read-write 0 Normal mode #00 1 Retention mode #01 2 Power shut down mode #10 3 Reserved (Write Ignore) #11 SRAM1PM3 Bank1 SRAM Power Mode Select 3 (Write Protect)\nThis field can control bank1 SRAM (64 KB) power mode when system enters Power-down mode for range 0x2001_4000 - 0x2001_7FFF.\nNote1: Bank 1 SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register. 22 2 read-write 0 Normal mode #00 1 Retention mode #01 2 Power shut down mode #10 3 Reserved (Write Ignore) #11 STACK System SRAM Stack Position (Write Protect)\nThis field must configure the system SRAM marco that first SRAM address accessed by CPU in power-on process.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 0 4 read-write SRAMPPCT SYS_SRAMPPCT Peripheral SRAM Power Mode Control Register 0xE0 read-write n 0x0 0x0 CAN CAN SRAM Power Mode Select (Write Protect)\nThis field can control CAN SRAM power mode for system enter Power-down mode.\nNote1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register. 0 2 read-write 0 Normal mode #00 1 Retention mode #01 2 Power shut down mode #10 3 Reserved #11 FMC FMC SRAM Power Mode Select (Write Protect)\nThis field can control FMC cache SRAM power mode for system enter Power-down mode.\nNote1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register. 8 2 read-write 0 Normal mode #00 1 Retention mode #01 2 Power shut down mode #10 3 Reserved (Write Ignore) #11 PDMA0 PDMA SRAM Power Mode Select (Write Protect)\nThis field can control PDMA0 SRAM power mode for system enter Power-down mode.\nNote1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register. 4 2 read-write 0 Normal mode #00 1 Retention mode #01 2 Power shut down mode #10 3 Reserved (Write Ignore) #11 PDMA1 PDMA SRAM Power Mode Select (Write Protect)\nThis field can control PDMA1 SRAM power mode for system enter Power-down mode.\nNote1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register. 6 2 read-write 0 Normal mode #00 1 Retention mode #01 2 Power shut down mode #10 3 Reserved (Write Ignore) #11 USBD USB Device SRAM Power Mode Select (Write Protect)\nThis field can control USB device SRAM power mode for system enter Power-down mode.\nNote1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register. 2 2 read-write 0 Normal mode #00 1 Retention mode #01 2 Power shut down mode #10 3 Reserved (Write Ignore) #11 SRAMSTS SYS_SRAMSTS System SRAM Parity Error Status Register 0xC4 read-only n 0x0 0x0 PERRIF SRAM Parity Check Error Flag\nThis bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0. 0 1 read-only 0 No System SRAM parity error #0 1 System SRAM parity error occur #1 TCTL12M SYS_TCTL12M HIRC 12M Trim Control Register 0xF0 read-write n 0x0 0x0 CESTOPEN Clock Error Stop Enable Bit 8 1 read-write 0 The trim operation is keep going if clock is inaccuracy #0 1 The trim operation is stopped if clock is inaccuracy #1 FREQSEL Trim Frequency Selection\nThis field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 0 2 read-write 0 Disable HIRC auto trim function #00 1 Enable HIRC auto trim function and trim HIRC to 12 MHz #01 2 Reserved. #10 3 Reserved #11 LOOPSEL Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 4 2 read-write 0 Trim value calculation is based on average difference in 4 clocks of reference clock #00 1 Trim value calculation is based on average difference in 8 clocks of reference clock #01 2 Trim value calculation is based on average difference in 16 clocks of reference clock #10 3 Trim value calculation is based on average difference in 32 clocks of reference clock #11 REFCKSEL Reference Clock Selection 10 1 read-write 0 HIRC trim reference clock is from external 32.768 kHz crystal oscillator #0 1 HIRC trim reference clock is from internal USB synchronous mode #1 RETRYCNT Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 6 2 read-write 0 Trim retry count limitation is 64 loops #00 1 Trim retry count limitation is 128 loops #01 2 Trim retry count limitation is 256 loops #10 3 Trim retry count limitation is 512 loops #11 TCTL48M SYS_TCTL48M HIRC 48M Trim Control Register 0xE4 read-write n 0x0 0x0 CESTOPEN Clock Error Stop Enable Bit 8 1 read-write 0 The trim operation is keep going if clock is inaccuracy #0 1 The trim operation is stopped if clock is inaccuracy #1 FREQSEL Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 0 2 read-write 0 Disable HIRC auto trim function #00 1 Enable HIRC auto trim function and trim HIRC to 48 MHz #01 2 Reserved. #10 3 Reserved #11 LOOPSEL Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 4 2 read-write 0 Trim value calculation is based on average difference in 4 clocks of reference clock #00 1 Trim value calculation is based on average difference in 8 clocks of reference clock #01 2 Trim value calculation is based on average difference in 16 clocks of reference clock #10 3 Trim value calculation is based on average difference in 32 clocks of reference clock #11 REFCKSEL Reference Clock Selection 10 1 read-write 0 HIRC trim 48M reference clock is from external 32.768 kHz crystal oscillator #0 1 HIRC trim 48M reference clock is from internal USB synchronous mode #1 RETRYCNT Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 6 2 read-write 0 Trim retry count limitation is 64 loops #00 1 Trim retry count limitation is 128 loops #01 2 Trim retry count limitation is 256 loops #10 3 Trim retry count limitation is 512 loops #11 TIEN12M SYS_TIEN12M HIRC 12M Trim Interrupt Enable Register 0xF4 read-write n 0x0 0x0 CLKEIEN Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_TISTS12M[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 2 1 read-write 0 Disable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU #0 1 Enable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU #1 TFAILIEN Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL12M[1:0]).\nIf this bit is high and TFAILIF(SYS_TSTS12M[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 1 1 read-write 0 Disable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU #0 1 Enable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU #1 TIEN48M SYS_TIEN48M HIRC 48M Trim Interrupt Enable Register 0xE8 read-write n 0x0 0x0 CLKEIEN Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_TISTS48M [2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 2 1 read-write 0 Disable CLKERRIF(SYS_TISTS48M [2]) status to trigger an interrupt to CPU #0 1 Enable CLKERRIF(SYS_TISTS48M [2]) status to trigger an interrupt to CPU #1 TFAILIEN Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL48M[1:0]).\nIf this bit is high and TFAILIF(SYS_TSTS48M [1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 1 1 read-write 0 Disable TFAILIF(SYS_TISTS48M [1]) status to trigger an interrupt to CPU #0 1 Enable TFAILIF(SYS_TISTS48M[1]) status to trigger an interrupt to CPU #1 TISTS12M SYS_TISTS12M HIRC 12M Trim Interrupt Status Register 0xF8 read-write n 0x0 0x0 CLKERRIF Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TCTL12M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL12M[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0. 2 1 read-write 0 Clock frequency is accuracy #0 1 Clock frequency is inaccuracy #1 FREQLOCK HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.\nWrite 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled. 0 1 read-write 0 The internal high-speed oscillator frequency doesn't lock at 12 MHz yet #0 1 The internal high-speed oscillator frequency locked at 12 MHz #1 TFAILIF Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL12M[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_TIEN12M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0. 1 1 read-write 0 Trim value update limitation count does not reach #0 1 Trim value update limitation count reached and HIRC frequency still not locked #1 TISTS48M SYS_TISTS48M HIRC 48M Trim Interrupt Status Register 0xEC read-write n 0x0 0x0 CLKERRIF Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TCTL48M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL48M[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_TIEN48M[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0. 2 1 read-write 0 Clock frequency is accuracy #0 1 Clock frequency is inaccuracy #1 FREQLOCK HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.\nWrite 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled. 0 1 read-write 0 The internal high-speed oscillator frequency doesn't lock at 48 MHz yet #0 1 The internal high-speed oscillator frequency locked at 48 MHz #1 TFAILIF Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL48M[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_TIEN48M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0. 1 1 read-write 0 Trim value update limitation count does not reach #0 1 Trim value update limitation count reached and HIRC frequency still not locked #1 USBPHY SYS_USBPHY USB PHY Control Register 0x2C -1 read-write n 0x0 0x0 OTGPHYEN USB OTG PHY Enable \nThis bit is used to enable/disable OTG PHY function. 8 1 read-write 0 OTG PHY function Disabled (default) #0 1 OTG PHY function Enabled #1 SBO Note: This bit must always be kept 1. If set to 0, the result is unpredictable. 2 1 read-write USBROLE USB Role Option (Write Protect)\nThese two bits are used to select the role of USB.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 0 2 read-write 0 Standard USB Device mode #00 1 Standard USB Host mode #01 2 ID dependent mode #10 3 On-The-Go device mode (default) #11 VREFCTL SYS_VREFCTL VREF Control Register 0x28 -1 read-write n 0x0 0x0 IBIASSEL VREF Bias Current Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 Bias current from MEGBIAS #0 1 Bias current from internal #1 PRELOADSEL Pre-load Timing Selection (Write Protect)\nNote: These bits is write protected. Refer to the SYS_REGLCTL register. 6 2 read-write 0 pre-load time is 60us for 0.1uF Capacitor #00 1 pre-load time is 310us for 1uF Capacitor #01 2 pre-load time is 2100us for 4.7uF Capacitor #10 3 pre-load time is 2850us for 10uF Capacitor #11 VREFCTL VREF Control Bits (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 0 5 read-write 0 VREF is from external pin #00000 3 VREF is internal 1.6V #00011 7 VREF is internal 2.0V #00111 11 VREF is internal 2.5V #01011 15 VREF is internal 3.0V #01111 TMR01 TIMER Register Map TIMER 0x0 0x0 0x24 registers n 0x100 0x24 registers n 0x140 0x58 registers n 0x19C 0xC registers n 0x40 0x68 registers n TIMER0_ALTCTL TIMER0_ALTCTL Timer0 Alternative Control Register 0x20 read-write n 0x0 0x0 FUNCSEL Function Selection\nNote: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. 0 1 read-write 0 timer controller is used as timer function #0 1 timer controller is used as PWM function #1 TIMER0_CAP TIMER0_CAP Timer0 Capture Data Register 0x10 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 0 24 read-only TIMER0_CMP TIMER0_CMP Timer0 Comparator Register 0x4 read-write n 0x0 0x0 CMPDAT Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. 0 24 read-write TIMER0_CNT TIMER0_CNT Timer0 Data Register 0xC read-write n 0x0 0x0 CNT Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.\nWrite operation.\nWriting any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. 0 24 read-write RSTACT Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically. 31 1 read-only 0 Reset operation is done #0 1 Reset operation triggered by writing TIMERx_CNT is in progress #1 TIMER0_CTL TIMER0_CTL Timer0 Control Register 0x0 -1 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1. 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CAPSRC Capture Pin Source Selection 22 1 read-write 0 Capture Function source is from TMx_EXT (x= 0~3) pin #0 1 Capture Function source is from internal ACMP output signal. User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source #1 CNTEN Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 EXTCNTEN Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. 24 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 ICEDEBUG ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer time-out interrupt Disabled #0 1 Timer time-out interrupt Enabled #1 INTRGEN Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.\nNote: For Timer1/3, this bit is ineffective and the read back value is always 0. 19 1 read-write 0 Inter-Timer Trigger Capture mode Disabled #0 1 Inter-Timer Trigger Capture mode Enabled #1 OPMODE Timer Counting Mode Select 27 2 read-write 0 The timer controller is operated in One-shot mode #00 1 The timer controller is operated in Periodic mode #01 2 The timer controller is operated in Toggle-output mode #10 3 The timer controller is operated in Continuous Counting mode #11 PERIOSEL Periodic Mode Behavior Selection Enable Bit If updated CMPDAT value CNT, CNT will be reset to default value. 20 1 read-write 0 The behavior selection in periodic mode is Disabled #0 1 The behavior selection in periodic mode is Enabled #1 PSC Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. 0 8 read-write TGLPINSEL Toggle-output Pin Select 21 1 read-write 0 Toggle mode output to TMx (Timer Event Counter Pin) #0 1 Toggle mode output to TMx_EXT (Timer External Capture Pin) #1 WKEN Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. 23 1 read-write 0 Wake-up function Disabled if timer interrupt signal generated #0 1 Wake-up function Enabled if timer interrupt signal generated #1 TIMER0_EINTSTS TIMER0_EINTSTS Timer0 External Interrupt Status Register 0x18 read-write n 0x0 0x0 CAPIF Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 0 1 read-write 0 TMx_EXT (x= 0~3) pin interrupt did not occur #0 1 TMx_EXT (x= 0~3) pin interrupt occurred #1 TIMER0_EXTCTL TIMER0_EXTCTL Timer0 External Control Register 0x14 read-write n 0x0 0x0 ACMPSSEL ACMP Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. 8 1 read-write 0 Capture Function source is from internal ACMP0 output signal #0 1 Capture Function source is from internal ACMP1 output signal #1 CAPDBEN Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. 6 1 read-write 0 TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled #0 1 TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled #1 CAPEDGE Timer External Capture Pin Edge Detect\nWhen first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. 12 3 read-write 0 Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin #000 1 Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin #001 2 Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer #010 3 Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer #011 6 First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin #110 7 First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin #111 CAPEN Timer External Capture Pin Enable Bit\nThis bit enables the TMx_EXT capture pin input function. 3 1 read-write 0 TMx_EXT (x= 0~3) pin Disabled #0 1 TMx_EXT (x= 0~3) pin Enabled #1 CAPFUNCS Capture Function Selection 4 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 CAPIEN Timer External Capture Interrupt Enable Bit 5 1 read-write 0 TMx_EXT (x= 0~3) pin detection Interrupt Disabled #0 1 TMx_EXT (x= 0~3) pin detection Interrupt Enabled #1 CNTDBEN Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. 7 1 read-write 0 TMx (x= 0~3) pin de-bounce Disabled #0 1 TMx (x= 0~3) pin de-bounce Enabled #1 CNTPHASE Timer External Count Phase 0 1 read-write 0 A falling edge of external counting pin will be counted #0 1 A rising edge of external counting pin will be counted #1 ECNTSSEL Event Counter Source Selection to Trigger Event Counter Function 16 1 read-write 0 Event Counter input source is from TMx (x= 0~3) pin #0 1 Event Counter input source is from USB internal SOF output signal #1 TIMER0_INTSTS TIMER0_INTSTS Timer0 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT value matches the CMPDAT value #1 TWKF Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated #1 TIMER0_PWMADCTS TIMER0_PWMADCTS Timer0 PWM ADC Trigger Source Select Register 0x90 read-write n 0x0 0x0 TRGEN PWM Counter Event Trigger ADC Conversion Enable Bit 7 1 read-write 0 PWM counter event trigger ADC conversion Disabled #0 1 PWM counter event trigger ADC conversion Enabled #1 TRGSEL PWM Counter Event Source Select to Trigger EADC Conversion 0 3 read-write 0 Trigger EADC conversion at zero point (ZIF) #000 1 Trigger EADC conversion at period point (PIF) #001 2 Trigger EADC conversion at zero or period point (ZIF or PIF) #010 3 Trigger EADC conversion at compare up count point (CMPUIF) #011 4 Trigger EADC conversion at compare down count point (CMPDIF) #100 TIMER0_PWMBNF TIMER0_PWMBNF Timer0 PWM Brake Pin Noise Filter Register 0x68 read-write n 0x0 0x0 BKPINSRC Brake Pin Source Select 16 2 read-write 0 Brake pin source comes from PWM0_BRAKE0 pin #00 1 Brake pin source comes from PWM0_BRAKE1 pin #01 2 Brake pin source comes from PWM1_BRAKE0 pin #10 3 Brake pin source comes from PWM1_BRAKE1 pin #11 BRKFCNT Brake Pin Noise Filter Count\nThe fields is used to control the active noise filter sample time. 4 3 read-write BRKNFEN Brake Pin Noise Filter Enable Bit 0 1 read-write 0 Pin noise filter detect of PWMx_BRAKEy Disabled #0 1 Pin noise filter detect of PWMx_BRAKEy Enabled #1 BRKNFSEL Brake Pin Noise Filter Clock Selection 1 3 read-write 0 Noise filter clock is PCLKx #000 1 Noise filter clock is PCLKx/2 #001 2 Noise filter clock is PCLKx/4 #010 3 Noise filter clock is PCLKx/8 #011 4 Noise filter clock is PCLKx/16 #100 5 Noise filter clock is PCLKx/32 #101 6 Noise filter clock is PCLKx/64 #110 7 Noise filter clock is PCLKx/128 #111 BRKPINV Brake Pin Detection Control Bit 7 1 read-write 0 Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 TIMER0_PWMBRKCTL TIMER0_PWMBRKCTL Timer0 PWM Brake Control Register 0x70 read-write n 0x0 0x0 BRKAEVEN PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 16 2 read-write 0 PWMx_BRAKEy brake event will not affect PWMx_CH0 output #00 1 PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened #01 2 PWMx_CH0 output low level when PWMx_BRAKEy brake event happened #10 3 PWMx_CH0 output high level when PWMx_BRAKEy brake event happened #11 BRKAODD PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 18 2 read-write 0 PWMx_BRAKEy brake event will not affect PWMx_CH1 output #00 1 PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened #01 2 PWMx_CH1 output low level when PWMx_BRAKEy brake event happened #10 3 PWMx_CH1 output high level when PWMx_BRAKEy brake event happened #11 BRKPEEN Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 PWMx_BRAKEy pin event as edge-detect brake source Disabled #0 1 PWMx_BRAKEy pin event as edge-detect brake source Enabled #1 BRKPLEN Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 PWMx_BRAKEy pin event as level-detect brake source Disabled #0 1 PWMx_BRAKEy pin event as level-detect brake source Enabled #1 CPO0EBEN Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 Internal ACMP0_O signal as edge-detect brake source Disabled #0 1 Internal ACMP0_O signal as edge-detect brake source Enabled #1 CPO0LBEN Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 Internal ACMP0_O signal as level-detect brake source Disabled #0 1 Internal ACMP0_O signal as level-detect brake source Enabled #1 CPO1EBEN Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 Internal ACMP1_O signal as edge-detect brake source Disabled #0 1 Internal ACMP1_O signal as edge-detect brake source Enabled #1 CPO1LBEN Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 Internal ACMP1_O signal as level-detect brake source Disabled #0 1 Internal ACMP1_O signal as level-detect brake source Enabled #1 SYSEBEN Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 7 1 read-write 0 System fail condition as edge-detect brake source Disabled #0 1 System fail condition as edge-detect brake source Enabled #1 SYSLBEN Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 15 1 read-write 0 System fail condition as level-detect brake source Disabled #0 1 System fail condition as level-detect brake source Enabled #1 TIMER0_PWMCLKPSC TIMER0_PWMCLKPSC Timer0 PWM Counter Clock Pre-scale Register 0x48 read-write n 0x0 0x0 CLKPSC PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0, then there is no scaling in PWM counter clock source. 0 12 read-write TIMER0_PWMCLKSRC TIMER0_PWMCLKSRC Timer0 PWM Counter Clock Source Register 0x44 read-write n 0x0 0x0 CLKSRC PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events. 0 3 read-write 0 TMRx_CLK #000 1 Internal TIMER0 time-out or capture event #001 2 Internal TIMER1 time-out or capture event #010 3 Internal TIMER2 time-out or capture event #011 4 Internal TIMER3 time-out or capture event #100 TIMER0_PWMCMPBUF TIMER0_PWMCMPBUF Timer0 PWM Comparator Buffer Register 0xA4 read-only n 0x0 0x0 CMPBUF PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register. 0 16 read-only TIMER0_PWMCMPDAT TIMER0_PWMCMPDAT Timer0 PWM Comparator Register 0x54 read-write n 0x0 0x0 CMP PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert. 0 16 read-write TIMER0_PWMCNT TIMER0_PWMCNT Timer0 PWM Counter Register 0x5C read-only n 0x0 0x0 CNT PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter. 0 16 read-only DIRF PWM Counter Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is active in down count #0 1 Counter is active up count #1 TIMER0_PWMCNTCLR TIMER0_PWMCNTCLR Timer0 PWM Clear Counter Register 0x4C read-write n 0x0 0x0 CNTCLR Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type #1 TIMER0_PWMCTL TIMER0_PWMCTL Timer0 PWM Control Register 0x40 read-write n 0x0 0x0 CNTEN PWM Counter Enable Bit 0 1 read-write 0 PWM counter and clock prescale Stop Running #0 1 PWM counter and clock prescale Start Running #1 CNTMODE PWM Counter Mode 3 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTTYPE PWM Counter Behavior Type 1 2 read-write 0 Up count type #00 1 Down count type #01 2 Up-down count type #10 3 Reserved #11 CTRLD Center Re-load\nIn up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period. 8 1 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt disable #0 1 ICE debug mode counter halt enable #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects PWM output #0 1 ICE debug mode acknowledgement disabled #1 IMMLDEN Immediately Load Enable Bit\nNote: If IMMLDEN is enabled, CTRLD will be invalid. 9 1 read-write 0 PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled. If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period #0 1 PERIOD/CMP will load to PBUF/CMPBUF immediately when user updates PERIOD/CMP #1 OUTMODE PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel. 16 1 read-write 0 PWM independent mode #0 1 PWM complementary mode #1 TIMER0_PWMDTCTL TIMER0_PWMDTCTL Timer0 PWM Dead-Time Control Register 0x58 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 24 1 read-write 0 Dead-time clock source from TMRx_PWMCLK without counter clock prescale #0 1 Dead-time clock source from TMRx_PWMCLK with counter clock prescale #1 DTCNT Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 12 read-write DTEN Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 TIMER0_PWMFAILBRK TIMER0_PWMFAILBRK Timer0 PWM System Fail Brake Control Register 0x6C read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger PWM Brake Function Enable Bit 1 1 read-write 0 Brake Function triggered by BOD event Disabled #0 1 Brake Function triggered by BOD event Enabled #1 CORBRKEN Core Lockup Detection Trigger PWM Brake Function Enable Bit 3 1 read-write 0 Brake Function triggered by core lockup event Disabled #0 1 Brake Function triggered by core lockup event Enabled #1 CSSBRKEN Clock Security System Detection Trigger PWM Brake Function Enable Bit 0 1 read-write 0 Brake Function triggered by clock fail detection Disabled #0 1 Brake Function triggered by clock fail detection Enabled #1 RAMBRKEN SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit 2 1 read-write 0 Brake Function triggered by SRAM parity error detection Disabled #0 1 Brake Function triggered by SRAM parity error detection Enabled #1 TIMER0_PWMINTEN0 TIMER0_PWMINTEN0 Timer0 PWM Interrupt Enable Register 0 0x80 read-write n 0x0 0x0 CMPDIEN PWM Compare Down Count Interrupt Enable Bit 3 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPUIEN PWM Compare Up Count Interrupt Enable Bit 2 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 PIEN PWM Period Point Interrupt Enable Bit\nNote: In up-down count type, period point means the center point of current PWM period. 1 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN PWM Zero Point Interrupt Enable Bit 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 TIMER0_PWMINTEN1 TIMER0_PWMINTEN1 Timer0 PWM Interrupt Enable Register 1 0x84 read-write n 0x0 0x0 BRKEIEN PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 PWM edge-detect brake interrupt Disabled #0 1 PWM edge-detect brake interrupt Enabled #1 BRKLIEN PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 PWM level-detect brake interrupt Disabled #0 1 PWM level-detect brake interrupt Enabled #1 TIMER0_PWMINTSTS0 TIMER0_PWMINTSTS0 Timer0 PWM Interrupt Status Register 0 0x88 read-write n 0x0 0x0 CMPDIF PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type.\nNote2: This bit is cleared by writing 1 to it. 3 1 read-write CMPUIF PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type.\nNote2: This bit is cleared by writing 1 to it. 2 1 read-write PIF PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote1: In up-down count type, PIF flag means the center point flag of current PWM period.\nNote2: This bit is cleared by writing 1 to it. 1 1 read-write ZIF PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches 0.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write TIMER0_PWMINTSTS1 TIMER0_PWMINTSTS1 Timer0 PWM Interrupt Status Register 1 0x8C read-write n 0x0 0x0 BRKEIF0 Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 PWMx_CH0 edge-detect brake event do not happened #0 1 PWMx_CH0 edge-detect brake event happened #1 BRKEIF1 Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 PWMx_CH1 edge-detect brake event do not happened #0 1 PWMx_CH1 edge-detect brake event happened #1 BRKESTS0 Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period. 16 1 read-only 0 PWMx_CH0 edge-detect brake state is released #0 1 PWMx_CH0 at edge-detect brake state #1 BRKESTS1 Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period. 17 1 read-only 0 PWMx_CH1 edge-detect brake state is released #0 1 PWMx_CH1 at edge-detect brake state #1 BRKLIF0 Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 PWMx_CH0 level-detect brake event do not happened #0 1 PWMx_CH0 level-detect brake event happened #1 BRKLIF1 Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 PWMx_CH1 level-detect brake event do not happened #0 1 PWMx_CH1 level-detect brake event happened #1 BRKLSTS0 Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. 24 1 read-only 0 PWMx_CH0 level-detect brake state is released #0 1 PWMx_CH0 at level-detect brake state #1 BRKLSTS1 Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. 25 1 read-only 0 PWMx_CH1 level-detect brake state is released #0 1 PWMx_CH1 at level-detect brake state #1 TIMER0_PWMMSK TIMER0_PWMMSK Timer0 PWM Output Mask Data Control Register 0x64 read-write n 0x0 0x0 MSKDAT0 PWMx_CH0 Output Mask Data Control Bit 0 1 read-write 0 Output logic Low to PWMx_CH0 #0 1 Output logic High to PWMx_CH0 #1 MSKDAT1 PWMx_CH1 Output Mask Data Control Bit 1 1 read-write 0 Output logic Low to PWMx_CH1 #0 1 Output logic High to PWMx_CH1 #1 TIMER0_PWMMSKEN TIMER0_PWMMSKEN Timer0 PWM Output Mask Enable Register 0x60 read-write n 0x0 0x0 MSKEN0 PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data. 0 1 read-write 0 PWMx_CH0 output signal is non-masked #0 1 PWMx_CH0 output signal is masked and output MSKDAT0 data #1 MSKEN1 PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data. 1 1 read-write 0 PWMx_CH1 output signal is non-masked #0 1 PWMx_CH1 output signal is masked and output MSKDAT1 data #1 TIMER0_PWMPBUF TIMER0_PWMPBUF Timer0 PWM Period Buffer Register 0xA0 read-only n 0x0 0x0 PBUF PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register. 0 16 read-only TIMER0_PWMPERIOD TIMER0_PWMPERIOD Timer0 PWM Period Register 0x50 read-write n 0x0 0x0 PERIOD PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.\nIn up and down count type:\nNote: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type. 0 16 read-write TIMER0_PWMPOEN TIMER0_PWMPOEN Timer0 PWM Pin Output Enable Register 0x78 read-write n 0x0 0x0 POEN0 PWMx_CH0 Output Pin Enable Bit 0 1 read-write 0 PWMx_CH0 pin at tri-state mode #0 1 PWMx_CH0 pin in output mode #1 POEN1 PWMx_CH1 Output Pin Enable Bit 1 1 read-write 0 PWMx_CH1 pin at tri-state mode #0 1 PWMx_CH1 pin in output mode #1 TIMER0_PWMPOLCTL TIMER0_PWMPOLCTL Timer0 PWM Pin Output Polar Control Register 0x74 read-write n 0x0 0x0 PINV0 PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin. 0 1 read-write 0 PWMx_CH0 output pin polar inverse Disabled #0 1 PWMx_CH0 output pin polar inverse Enabled #1 PINV1 PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin. 1 1 read-write 0 PWMx_CH1 output pin polar inverse Disabled #0 1 PWMx_CH1 output pin polar inverse Enabled #1 TIMER0_PWMSCTL TIMER0_PWMSCTL Timer0 PWM Synchronous Control Register 0x94 read-write n 0x0 0x0 SYNCMODE PWM Synchronous Mode Enable Select 0 2 read-write 0 PWM synchronous function Disabled #00 1 PWM synchronous counter start function Enabled #01 2 Reserved #10 3 PWM synchronous counter clear function Enabled #11 SYNCSRC PWM Synchronous Counter Start/Clear Source Select\nNote1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.\nNote2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1. 8 1 read-write 0 Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN #0 1 Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN #1 TIMER0_PWMSTATUS TIMER0_PWMSTATUS Timer0 PWM Status Register 0x9C read-write n 0x0 0x0 CNTMAXF PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 The PWM counter value never reached its maximum value 0xFFFF #0 1 The PWM counter value has reached its maximum value #1 EADCTRGF Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it. 16 1 read-write 0 PWM counter event trigger EADC start conversion is not occurred #0 1 PWM counter event trigger EADC start conversion has occurred #1 TIMER0_PWMSTRG TIMER0_PWMSTRG Timer0 PWM Synchronous Trigger Register 0x98 write-only n 0x0 0x0 STRGEN PWM Counter Synchronous Trigger Enable Bit (Write Only)\nPMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting.\nNote: This bit is only available in TIMER0 and TIMER2. 0 1 write-only TIMER0_PWMSWBRK TIMER0_PWMSWBRK Timer0 PWM Software Trigger Brake Control Register 0x7C write-only n 0x0 0x0 BRKETRG Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 write-only BRKLTRG Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 write-only TIMER0_TRGCTL TIMER0_TRGCTL Timer0 Trigger Control Register 0x1C read-write n 0x0 0x0 TRGDAC Trigger DAC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC. 3 1 read-write 0 Timer interrupt trigger DAC Disabled #0 1 Timer interrupt trigger DAC Enabled #1 TRGEADC Trigger EADC Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. 2 1 read-write 0 Timer interrupt trigger EADC Disabled #0 1 Timer interrupt trigger EADC Enabled #1 TRGPDMA Trigger PDMA Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. 4 1 read-write 0 Timer interrupt trigger PDMA Disabled #0 1 Timer interrupt trigger PDMA Enabled #1 TRGPWM Trigger PWM Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be as PWM counter clock source. 1 1 read-write 0 Timer interrupt trigger PWM Disabled #0 1 Timer interrupt trigger PWM Enabled #1 TRGSSEL Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal. 0 1 read-write 0 Time-out interrupt signal is used to internal trigger PWM, PDMA, DAC, and ADC #0 1 Capture interrupt signal is used to internal trigger PWM, PDMA, DAC, and ADC #1 TIMER1_ALTCTL TIMER1_ALTCTL Timer1 Alternative Control Register 0x120 read-write n 0x0 0x0 TIMER1_CAP TIMER1_CAP Timer1 Capture Data Register 0x110 read-write n 0x0 0x0 TIMER1_CMP TIMER1_CMP Timer1 Comparator Register 0x104 read-write n 0x0 0x0 TIMER1_CNT TIMER1_CNT Timer1 Data Register 0x10C read-write n 0x0 0x0 TIMER1_CTL TIMER1_CTL Timer1 Control Register 0x100 read-write n 0x0 0x0 TIMER1_EINTSTS TIMER1_EINTSTS Timer1 External Interrupt Status Register 0x118 read-write n 0x0 0x0 TIMER1_EXTCTL TIMER1_EXTCTL Timer1 External Control Register 0x114 read-write n 0x0 0x0 TIMER1_INTSTS TIMER1_INTSTS Timer1 Interrupt Status Register 0x108 read-write n 0x0 0x0 TIMER1_PWMADCTS TIMER1_PWMADCTS Timer1 PWM ADC Trigger Source Select Register 0x190 read-write n 0x0 0x0 TIMER1_PWMBNF TIMER1_PWMBNF Timer1 PWM Brake Pin Noise Filter Register 0x168 read-write n 0x0 0x0 TIMER1_PWMBRKCTL TIMER1_PWMBRKCTL Timer1 PWM Brake Control Register 0x170 read-write n 0x0 0x0 TIMER1_PWMCLKPSC TIMER1_PWMCLKPSC Timer1 PWM Counter Clock Pre-scale Register 0x148 read-write n 0x0 0x0 TIMER1_PWMCLKSRC TIMER1_PWMCLKSRC Timer1 PWM Counter Clock Source Register 0x144 read-write n 0x0 0x0 TIMER1_PWMCMPBUF TIMER1_PWMCMPBUF Timer1 PWM Comparator Buffer Register 0x1A4 read-write n 0x0 0x0 TIMER1_PWMCMPDAT TIMER1_PWMCMPDAT Timer1 PWM Comparator Register 0x154 read-write n 0x0 0x0 TIMER1_PWMCNT TIMER1_PWMCNT Timer1 PWM Counter Register 0x15C read-write n 0x0 0x0 TIMER1_PWMCNTCLR TIMER1_PWMCNTCLR Timer1 PWM Clear Counter Register 0x14C read-write n 0x0 0x0 TIMER1_PWMCTL TIMER1_PWMCTL Timer1 PWM Control Register 0x140 read-write n 0x0 0x0 TIMER1_PWMDTCTL TIMER1_PWMDTCTL Timer1 PWM Dead-Time Control Register 0x158 read-write n 0x0 0x0 TIMER1_PWMFAILBRK TIMER1_PWMFAILBRK Timer1 PWM System Fail Brake Control Register 0x16C read-write n 0x0 0x0 TIMER1_PWMINTEN0 TIMER1_PWMINTEN0 Timer1 PWM Interrupt Enable Register 0 0x180 read-write n 0x0 0x0 TIMER1_PWMINTEN1 TIMER1_PWMINTEN1 Timer1 PWM Interrupt Enable Register 1 0x184 read-write n 0x0 0x0 TIMER1_PWMINTSTS0 TIMER1_PWMINTSTS0 Timer1 PWM Interrupt Status Register 0 0x188 read-write n 0x0 0x0 TIMER1_PWMINTSTS1 TIMER1_PWMINTSTS1 Timer1 PWM Interrupt Status Register 1 0x18C read-write n 0x0 0x0 TIMER1_PWMMSK TIMER1_PWMMSK Timer1 PWM Output Mask Data Control Register 0x164 read-write n 0x0 0x0 TIMER1_PWMMSKEN TIMER1_PWMMSKEN Timer1 PWM Output Mask Enable Register 0x160 read-write n 0x0 0x0 TIMER1_PWMPBUF TIMER1_PWMPBUF Timer1 PWM Period Buffer Register 0x1A0 read-write n 0x0 0x0 TIMER1_PWMPERIOD TIMER1_PWMPERIOD Timer1 PWM Period Register 0x150 read-write n 0x0 0x0 TIMER1_PWMPOEN TIMER1_PWMPOEN Timer1 PWM Pin Output Enable Register 0x178 read-write n 0x0 0x0 TIMER1_PWMPOLCTL TIMER1_PWMPOLCTL Timer1 PWM Pin Output Polar Control Register 0x174 read-write n 0x0 0x0 TIMER1_PWMSCTL TIMER1_PWMSCTL Timer1 PWM Synchronous Control Register 0x194 read-write n 0x0 0x0 TIMER1_PWMSTATUS TIMER1_PWMSTATUS Timer1 PWM Status Register 0x19C read-write n 0x0 0x0 TIMER1_PWMSWBRK TIMER1_PWMSWBRK Timer1 PWM Software Trigger Brake Control Register 0x17C read-write n 0x0 0x0 TIMER1_TRGCTL TIMER1_TRGCTL Timer1 Trigger Control Register 0x11C read-write n 0x0 0x0 TMR23 TIMER Register Map TIMER 0x0 0x0 0x24 registers n 0x100 0x24 registers n 0x140 0x58 registers n 0x19C 0xC registers n 0x40 0x68 registers n TIMER2_ALTCTL TIMER2_ALTCTL Timer2 Alternative Control Register 0x20 read-write n 0x0 0x0 FUNCSEL Function Selection\nNote: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. 0 1 read-write 0 timer controller is used as timer function #0 1 timer controller is used as PWM function #1 TIMER2_CAP TIMER2_CAP Timer2 Capture Data Register 0x10 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 0 24 read-only TIMER2_CMP TIMER2_CMP Timer2 Comparator Register 0x4 read-write n 0x0 0x0 CMPDAT Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. 0 24 read-write TIMER2_CNT TIMER2_CNT Timer2 Data Register 0xC read-write n 0x0 0x0 CNT Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.\nWrite operation.\nWriting any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. 0 24 read-write RSTACT Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically. 31 1 read-only 0 Reset operation is done #0 1 Reset operation triggered by writing TIMERx_CNT is in progress #1 TIMER2_CTL TIMER2_CTL Timer2 Control Register 0x0 -1 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1. 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CAPSRC Capture Pin Source Selection 22 1 read-write 0 Capture Function source is from TMx_EXT (x= 0~3) pin #0 1 Capture Function source is from internal ACMP output signal. User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source #1 CNTEN Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 EXTCNTEN Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. 24 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 ICEDEBUG ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer time-out interrupt Disabled #0 1 Timer time-out interrupt Enabled #1 INTRGEN Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.\nNote: For Timer1/3, this bit is ineffective and the read back value is always 0. 19 1 read-write 0 Inter-Timer Trigger Capture mode Disabled #0 1 Inter-Timer Trigger Capture mode Enabled #1 OPMODE Timer Counting Mode Select 27 2 read-write 0 The timer controller is operated in One-shot mode #00 1 The timer controller is operated in Periodic mode #01 2 The timer controller is operated in Toggle-output mode #10 3 The timer controller is operated in Continuous Counting mode #11 PERIOSEL Periodic Mode Behavior Selection Enable Bit If updated CMPDAT value CNT, CNT will be reset to default value. 20 1 read-write 0 The behavior selection in periodic mode is Disabled #0 1 The behavior selection in periodic mode is Enabled #1 PSC Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. 0 8 read-write TGLPINSEL Toggle-output Pin Select 21 1 read-write 0 Toggle mode output to TMx (Timer Event Counter Pin) #0 1 Toggle mode output to TMx_EXT (Timer External Capture Pin) #1 WKEN Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. 23 1 read-write 0 Wake-up function Disabled if timer interrupt signal generated #0 1 Wake-up function Enabled if timer interrupt signal generated #1 TIMER2_EINTSTS TIMER2_EINTSTS Timer2 External Interrupt Status Register 0x18 read-write n 0x0 0x0 CAPIF Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 0 1 read-write 0 TMx_EXT (x= 0~3) pin interrupt did not occur #0 1 TMx_EXT (x= 0~3) pin interrupt occurred #1 TIMER2_EXTCTL TIMER2_EXTCTL Timer2 External Control Register 0x14 read-write n 0x0 0x0 ACMPSSEL ACMP Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. 8 1 read-write 0 Capture Function source is from internal ACMP0 output signal #0 1 Capture Function source is from internal ACMP1 output signal #1 CAPDBEN Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. 6 1 read-write 0 TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled #0 1 TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled #1 CAPEDGE Timer External Capture Pin Edge Detect\nWhen first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. 12 3 read-write 0 Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin #000 1 Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin #001 2 Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer #010 3 Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer #011 6 First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin #110 7 First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin #111 CAPEN Timer External Capture Pin Enable Bit\nThis bit enables the TMx_EXT capture pin input function. 3 1 read-write 0 TMx_EXT (x= 0~3) pin Disabled #0 1 TMx_EXT (x= 0~3) pin Enabled #1 CAPFUNCS Capture Function Selection 4 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 CAPIEN Timer External Capture Interrupt Enable Bit 5 1 read-write 0 TMx_EXT (x= 0~3) pin detection Interrupt Disabled #0 1 TMx_EXT (x= 0~3) pin detection Interrupt Enabled #1 CNTDBEN Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. 7 1 read-write 0 TMx (x= 0~3) pin de-bounce Disabled #0 1 TMx (x= 0~3) pin de-bounce Enabled #1 CNTPHASE Timer External Count Phase 0 1 read-write 0 A falling edge of external counting pin will be counted #0 1 A rising edge of external counting pin will be counted #1 ECNTSSEL Event Counter Source Selection to Trigger Event Counter Function 16 1 read-write 0 Event Counter input source is from TMx (x= 0~3) pin #0 1 Event Counter input source is from USB internal SOF output signal #1 TIMER2_INTSTS TIMER2_INTSTS Timer2 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT value matches the CMPDAT value #1 TWKF Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated #1 TIMER2_PWMADCTS TIMER2_PWMADCTS Timer2 PWM ADC Trigger Source Select Register 0x90 read-write n 0x0 0x0 TRGEN PWM Counter Event Trigger ADC Conversion Enable Bit 7 1 read-write 0 PWM counter event trigger ADC conversion Disabled #0 1 PWM counter event trigger ADC conversion Enabled #1 TRGSEL PWM Counter Event Source Select to Trigger EADC Conversion 0 3 read-write 0 Trigger EADC conversion at zero point (ZIF) #000 1 Trigger EADC conversion at period point (PIF) #001 2 Trigger EADC conversion at zero or period point (ZIF or PIF) #010 3 Trigger EADC conversion at compare up count point (CMPUIF) #011 4 Trigger EADC conversion at compare down count point (CMPDIF) #100 TIMER2_PWMBNF TIMER2_PWMBNF Timer2 PWM Brake Pin Noise Filter Register 0x68 read-write n 0x0 0x0 BKPINSRC Brake Pin Source Select 16 2 read-write 0 Brake pin source comes from PWM0_BRAKE0 pin #00 1 Brake pin source comes from PWM0_BRAKE1 pin #01 2 Brake pin source comes from PWM1_BRAKE0 pin #10 3 Brake pin source comes from PWM1_BRAKE1 pin #11 BRKFCNT Brake Pin Noise Filter Count\nThe fields is used to control the active noise filter sample time. 4 3 read-write BRKNFEN Brake Pin Noise Filter Enable Bit 0 1 read-write 0 Pin noise filter detect of PWMx_BRAKEy Disabled #0 1 Pin noise filter detect of PWMx_BRAKEy Enabled #1 BRKNFSEL Brake Pin Noise Filter Clock Selection 1 3 read-write 0 Noise filter clock is PCLKx #000 1 Noise filter clock is PCLKx/2 #001 2 Noise filter clock is PCLKx/4 #010 3 Noise filter clock is PCLKx/8 #011 4 Noise filter clock is PCLKx/16 #100 5 Noise filter clock is PCLKx/32 #101 6 Noise filter clock is PCLKx/64 #110 7 Noise filter clock is PCLKx/128 #111 BRKPINV Brake Pin Detection Control Bit 7 1 read-write 0 Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 TIMER2_PWMBRKCTL TIMER2_PWMBRKCTL Timer2 PWM Brake Control Register 0x70 read-write n 0x0 0x0 BRKAEVEN PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 16 2 read-write 0 PWMx_BRAKEy brake event will not affect PWMx_CH0 output #00 1 PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened #01 2 PWMx_CH0 output low level when PWMx_BRAKEy brake event happened #10 3 PWMx_CH0 output high level when PWMx_BRAKEy brake event happened #11 BRKAODD PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 18 2 read-write 0 PWMx_BRAKEy brake event will not affect PWMx_CH1 output #00 1 PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened #01 2 PWMx_CH1 output low level when PWMx_BRAKEy brake event happened #10 3 PWMx_CH1 output high level when PWMx_BRAKEy brake event happened #11 BRKPEEN Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 PWMx_BRAKEy pin event as edge-detect brake source Disabled #0 1 PWMx_BRAKEy pin event as edge-detect brake source Enabled #1 BRKPLEN Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 PWMx_BRAKEy pin event as level-detect brake source Disabled #0 1 PWMx_BRAKEy pin event as level-detect brake source Enabled #1 CPO0EBEN Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 Internal ACMP0_O signal as edge-detect brake source Disabled #0 1 Internal ACMP0_O signal as edge-detect brake source Enabled #1 CPO0LBEN Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 Internal ACMP0_O signal as level-detect brake source Disabled #0 1 Internal ACMP0_O signal as level-detect brake source Enabled #1 CPO1EBEN Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 Internal ACMP1_O signal as edge-detect brake source Disabled #0 1 Internal ACMP1_O signal as edge-detect brake source Enabled #1 CPO1LBEN Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 Internal ACMP1_O signal as level-detect brake source Disabled #0 1 Internal ACMP1_O signal as level-detect brake source Enabled #1 SYSEBEN Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 7 1 read-write 0 System fail condition as edge-detect brake source Disabled #0 1 System fail condition as edge-detect brake source Enabled #1 SYSLBEN Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 15 1 read-write 0 System fail condition as level-detect brake source Disabled #0 1 System fail condition as level-detect brake source Enabled #1 TIMER2_PWMCLKPSC TIMER2_PWMCLKPSC Timer2 PWM Counter Clock Pre-scale Register 0x48 read-write n 0x0 0x0 CLKPSC PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0, then there is no scaling in PWM counter clock source. 0 12 read-write TIMER2_PWMCLKSRC TIMER2_PWMCLKSRC Timer2 PWM Counter Clock Source Register 0x44 read-write n 0x0 0x0 CLKSRC PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events. 0 3 read-write 0 TMRx_CLK #000 1 Internal TIMER0 time-out or capture event #001 2 Internal TIMER1 time-out or capture event #010 3 Internal TIMER2 time-out or capture event #011 4 Internal TIMER3 time-out or capture event #100 TIMER2_PWMCMPBUF TIMER2_PWMCMPBUF Timer2 PWM Comparator Buffer Register 0xA4 read-only n 0x0 0x0 CMPBUF PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register. 0 16 read-only TIMER2_PWMCMPDAT TIMER2_PWMCMPDAT Timer2 PWM Comparator Register 0x54 read-write n 0x0 0x0 CMP PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert. 0 16 read-write TIMER2_PWMCNT TIMER2_PWMCNT Timer2 PWM Counter Register 0x5C read-only n 0x0 0x0 CNT PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter. 0 16 read-only DIRF PWM Counter Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is active in down count #0 1 Counter is active up count #1 TIMER2_PWMCNTCLR TIMER2_PWMCNTCLR Timer2 PWM Clear Counter Register 0x4C read-write n 0x0 0x0 CNTCLR Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type #1 TIMER2_PWMCTL TIMER2_PWMCTL Timer2 PWM Control Register 0x40 read-write n 0x0 0x0 CNTEN PWM Counter Enable Bit 0 1 read-write 0 PWM counter and clock prescale Stop Running #0 1 PWM counter and clock prescale Start Running #1 CNTMODE PWM Counter Mode 3 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTTYPE PWM Counter Behavior Type 1 2 read-write 0 Up count type #00 1 Down count type #01 2 Up-down count type #10 3 Reserved #11 CTRLD Center Re-load\nIn up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period. 8 1 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt disable #0 1 ICE debug mode counter halt enable #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects PWM output #0 1 ICE debug mode acknowledgement disabled #1 IMMLDEN Immediately Load Enable Bit\nNote: If IMMLDEN is enabled, CTRLD will be invalid. 9 1 read-write 0 PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled. If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period #0 1 PERIOD/CMP will load to PBUF/CMPBUF immediately when user updates PERIOD/CMP #1 OUTMODE PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel. 16 1 read-write 0 PWM independent mode #0 1 PWM complementary mode #1 TIMER2_PWMDTCTL TIMER2_PWMDTCTL Timer2 PWM Dead-Time Control Register 0x58 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 24 1 read-write 0 Dead-time clock source from TMRx_PWMCLK without counter clock prescale #0 1 Dead-time clock source from TMRx_PWMCLK with counter clock prescale #1 DTCNT Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 12 read-write DTEN Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 TIMER2_PWMFAILBRK TIMER2_PWMFAILBRK Timer2 PWM System Fail Brake Control Register 0x6C read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger PWM Brake Function Enable Bit 1 1 read-write 0 Brake Function triggered by BOD event Disabled #0 1 Brake Function triggered by BOD event Enabled #1 CORBRKEN Core Lockup Detection Trigger PWM Brake Function Enable Bit 3 1 read-write 0 Brake Function triggered by core lockup event Disabled #0 1 Brake Function triggered by core lockup event Enabled #1 CSSBRKEN Clock Security System Detection Trigger PWM Brake Function Enable Bit 0 1 read-write 0 Brake Function triggered by clock fail detection Disabled #0 1 Brake Function triggered by clock fail detection Enabled #1 RAMBRKEN SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit 2 1 read-write 0 Brake Function triggered by SRAM parity error detection Disabled #0 1 Brake Function triggered by SRAM parity error detection Enabled #1 TIMER2_PWMINTEN0 TIMER2_PWMINTEN0 Timer2 PWM Interrupt Enable Register 0 0x80 read-write n 0x0 0x0 CMPDIEN PWM Compare Down Count Interrupt Enable Bit 3 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPUIEN PWM Compare Up Count Interrupt Enable Bit 2 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 PIEN PWM Period Point Interrupt Enable Bit\nNote: In up-down count type, period point means the center point of current PWM period. 1 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN PWM Zero Point Interrupt Enable Bit 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 TIMER2_PWMINTEN1 TIMER2_PWMINTEN1 Timer2 PWM Interrupt Enable Register 1 0x84 read-write n 0x0 0x0 BRKEIEN PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 PWM edge-detect brake interrupt Disabled #0 1 PWM edge-detect brake interrupt Enabled #1 BRKLIEN PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 PWM level-detect brake interrupt Disabled #0 1 PWM level-detect brake interrupt Enabled #1 TIMER2_PWMINTSTS0 TIMER2_PWMINTSTS0 Timer2 PWM Interrupt Status Register 0 0x88 read-write n 0x0 0x0 CMPDIF PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type.\nNote2: This bit is cleared by writing 1 to it. 3 1 read-write CMPUIF PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type.\nNote2: This bit is cleared by writing 1 to it. 2 1 read-write PIF PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote1: In up-down count type, PIF flag means the center point flag of current PWM period.\nNote2: This bit is cleared by writing 1 to it. 1 1 read-write ZIF PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches 0.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write TIMER2_PWMINTSTS1 TIMER2_PWMINTSTS1 Timer2 PWM Interrupt Status Register 1 0x8C read-write n 0x0 0x0 BRKEIF0 Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 PWMx_CH0 edge-detect brake event do not happened #0 1 PWMx_CH0 edge-detect brake event happened #1 BRKEIF1 Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 PWMx_CH1 edge-detect brake event do not happened #0 1 PWMx_CH1 edge-detect brake event happened #1 BRKESTS0 Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period. 16 1 read-only 0 PWMx_CH0 edge-detect brake state is released #0 1 PWMx_CH0 at edge-detect brake state #1 BRKESTS1 Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period. 17 1 read-only 0 PWMx_CH1 edge-detect brake state is released #0 1 PWMx_CH1 at edge-detect brake state #1 BRKLIF0 Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 PWMx_CH0 level-detect brake event do not happened #0 1 PWMx_CH0 level-detect brake event happened #1 BRKLIF1 Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 PWMx_CH1 level-detect brake event do not happened #0 1 PWMx_CH1 level-detect brake event happened #1 BRKLSTS0 Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. 24 1 read-only 0 PWMx_CH0 level-detect brake state is released #0 1 PWMx_CH0 at level-detect brake state #1 BRKLSTS1 Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. 25 1 read-only 0 PWMx_CH1 level-detect brake state is released #0 1 PWMx_CH1 at level-detect brake state #1 TIMER2_PWMMSK TIMER2_PWMMSK Timer2 PWM Output Mask Data Control Register 0x64 read-write n 0x0 0x0 MSKDAT0 PWMx_CH0 Output Mask Data Control Bit 0 1 read-write 0 Output logic Low to PWMx_CH0 #0 1 Output logic High to PWMx_CH0 #1 MSKDAT1 PWMx_CH1 Output Mask Data Control Bit 1 1 read-write 0 Output logic Low to PWMx_CH1 #0 1 Output logic High to PWMx_CH1 #1 TIMER2_PWMMSKEN TIMER2_PWMMSKEN Timer2 PWM Output Mask Enable Register 0x60 read-write n 0x0 0x0 MSKEN0 PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data. 0 1 read-write 0 PWMx_CH0 output signal is non-masked #0 1 PWMx_CH0 output signal is masked and output MSKDAT0 data #1 MSKEN1 PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data. 1 1 read-write 0 PWMx_CH1 output signal is non-masked #0 1 PWMx_CH1 output signal is masked and output MSKDAT1 data #1 TIMER2_PWMPBUF TIMER2_PWMPBUF Timer2 PWM Period Buffer Register 0xA0 read-only n 0x0 0x0 PBUF PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register. 0 16 read-only TIMER2_PWMPERIOD TIMER2_PWMPERIOD Timer2 PWM Period Register 0x50 read-write n 0x0 0x0 PERIOD PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.\nIn up and down count type:\nNote: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type. 0 16 read-write TIMER2_PWMPOEN TIMER2_PWMPOEN Timer2 PWM Pin Output Enable Register 0x78 read-write n 0x0 0x0 POEN0 PWMx_CH0 Output Pin Enable Bit 0 1 read-write 0 PWMx_CH0 pin at tri-state mode #0 1 PWMx_CH0 pin in output mode #1 POEN1 PWMx_CH1 Output Pin Enable Bit 1 1 read-write 0 PWMx_CH1 pin at tri-state mode #0 1 PWMx_CH1 pin in output mode #1 TIMER2_PWMPOLCTL TIMER2_PWMPOLCTL Timer2 PWM Pin Output Polar Control Register 0x74 read-write n 0x0 0x0 PINV0 PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin. 0 1 read-write 0 PWMx_CH0 output pin polar inverse Disabled #0 1 PWMx_CH0 output pin polar inverse Enabled #1 PINV1 PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin. 1 1 read-write 0 PWMx_CH1 output pin polar inverse Disabled #0 1 PWMx_CH1 output pin polar inverse Enabled #1 TIMER2_PWMSCTL TIMER2_PWMSCTL Timer2 PWM Synchronous Control Register 0x94 read-write n 0x0 0x0 SYNCMODE PWM Synchronous Mode Enable Select 0 2 read-write 0 PWM synchronous function Disabled #00 1 PWM synchronous counter start function Enabled #01 2 Reserved #10 3 PWM synchronous counter clear function Enabled #11 SYNCSRC PWM Synchronous Counter Start/Clear Source Select\nNote1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.\nNote2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1. 8 1 read-write 0 Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN #0 1 Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN #1 TIMER2_PWMSTATUS TIMER2_PWMSTATUS Timer2 PWM Status Register 0x9C read-write n 0x0 0x0 CNTMAXF PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 The PWM counter value never reached its maximum value 0xFFFF #0 1 The PWM counter value has reached its maximum value #1 EADCTRGF Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it. 16 1 read-write 0 PWM counter event trigger EADC start conversion is not occurred #0 1 PWM counter event trigger EADC start conversion has occurred #1 TIMER2_PWMSTRG TIMER2_PWMSTRG Timer2 PWM Synchronous Trigger Register 0x98 write-only n 0x0 0x0 STRGEN PWM Counter Synchronous Trigger Enable Bit (Write Only)\nPMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting.\nNote: This bit is only available in TIMER0 and TIMER2. 0 1 write-only TIMER2_PWMSWBRK TIMER2_PWMSWBRK Timer2 PWM Software Trigger Brake Control Register 0x7C write-only n 0x0 0x0 BRKETRG Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 write-only BRKLTRG Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 write-only TIMER2_TRGCTL TIMER2_TRGCTL Timer2 Trigger Control Register 0x1C read-write n 0x0 0x0 TRGDAC Trigger DAC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC. 3 1 read-write 0 Timer interrupt trigger DAC Disabled #0 1 Timer interrupt trigger DAC Enabled #1 TRGEADC Trigger EADC Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. 2 1 read-write 0 Timer interrupt trigger EADC Disabled #0 1 Timer interrupt trigger EADC Enabled #1 TRGPDMA Trigger PDMA Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. 4 1 read-write 0 Timer interrupt trigger PDMA Disabled #0 1 Timer interrupt trigger PDMA Enabled #1 TRGPWM Trigger PWM Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be as PWM counter clock source. 1 1 read-write 0 Timer interrupt trigger PWM Disabled #0 1 Timer interrupt trigger PWM Enabled #1 TRGSSEL Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal. 0 1 read-write 0 Time-out interrupt signal is used to internal trigger PWM, PDMA, DAC, and ADC #0 1 Capture interrupt signal is used to internal trigger PWM, PDMA, DAC, and ADC #1 TIMER3_ALTCTL TIMER3_ALTCTL Timer3 Alternative Control Register 0x120 read-write n 0x0 0x0 TIMER3_CAP TIMER3_CAP Timer3 Capture Data Register 0x110 read-write n 0x0 0x0 TIMER3_CMP TIMER3_CMP Timer3 Comparator Register 0x104 read-write n 0x0 0x0 TIMER3_CNT TIMER3_CNT Timer3 Data Register 0x10C read-write n 0x0 0x0 TIMER3_CTL TIMER3_CTL Timer3 Control Register 0x100 read-write n 0x0 0x0 TIMER3_EINTSTS TIMER3_EINTSTS Timer3 External Interrupt Status Register 0x118 read-write n 0x0 0x0 TIMER3_EXTCTL TIMER3_EXTCTL Timer3 External Control Register 0x114 read-write n 0x0 0x0 TIMER3_INTSTS TIMER3_INTSTS Timer3 Interrupt Status Register 0x108 read-write n 0x0 0x0 TIMER3_PWMADCTS TIMER3_PWMADCTS Timer3 PWM ADC Trigger Source Select Register 0x190 read-write n 0x0 0x0 TIMER3_PWMBNF TIMER3_PWMBNF Timer3 PWM Brake Pin Noise Filter Register 0x168 read-write n 0x0 0x0 TIMER3_PWMBRKCTL TIMER3_PWMBRKCTL Timer3 PWM Brake Control Register 0x170 read-write n 0x0 0x0 TIMER3_PWMCLKPSC TIMER3_PWMCLKPSC Timer3 PWM Counter Clock Pre-scale Register 0x148 read-write n 0x0 0x0 TIMER3_PWMCLKSRC TIMER3_PWMCLKSRC Timer3 PWM Counter Clock Source Register 0x144 read-write n 0x0 0x0 TIMER3_PWMCMPBUF TIMER3_PWMCMPBUF Timer3 PWM Comparator Buffer Register 0x1A4 read-write n 0x0 0x0 TIMER3_PWMCMPDAT TIMER3_PWMCMPDAT Timer3 PWM Comparator Register 0x154 read-write n 0x0 0x0 TIMER3_PWMCNT TIMER3_PWMCNT Timer3 PWM Counter Register 0x15C read-write n 0x0 0x0 TIMER3_PWMCNTCLR TIMER3_PWMCNTCLR Timer3 PWM Clear Counter Register 0x14C read-write n 0x0 0x0 TIMER3_PWMCTL TIMER3_PWMCTL Timer3 PWM Control Register 0x140 read-write n 0x0 0x0 TIMER3_PWMDTCTL TIMER3_PWMDTCTL Timer3 PWM Dead-Time Control Register 0x158 read-write n 0x0 0x0 TIMER3_PWMFAILBRK TIMER3_PWMFAILBRK Timer3 PWM System Fail Brake Control Register 0x16C read-write n 0x0 0x0 TIMER3_PWMINTEN0 TIMER3_PWMINTEN0 Timer3 PWM Interrupt Enable Register 0 0x180 read-write n 0x0 0x0 TIMER3_PWMINTEN1 TIMER3_PWMINTEN1 Timer3 PWM Interrupt Enable Register 1 0x184 read-write n 0x0 0x0 TIMER3_PWMINTSTS0 TIMER3_PWMINTSTS0 Timer3 PWM Interrupt Status Register 0 0x188 read-write n 0x0 0x0 TIMER3_PWMINTSTS1 TIMER3_PWMINTSTS1 Timer3 PWM Interrupt Status Register 1 0x18C read-write n 0x0 0x0 TIMER3_PWMMSK TIMER3_PWMMSK Timer3 PWM Output Mask Data Control Register 0x164 read-write n 0x0 0x0 TIMER3_PWMMSKEN TIMER3_PWMMSKEN Timer3 PWM Output Mask Enable Register 0x160 read-write n 0x0 0x0 TIMER3_PWMPBUF TIMER3_PWMPBUF Timer3 PWM Period Buffer Register 0x1A0 read-write n 0x0 0x0 TIMER3_PWMPERIOD TIMER3_PWMPERIOD Timer3 PWM Period Register 0x150 read-write n 0x0 0x0 TIMER3_PWMPOEN TIMER3_PWMPOEN Timer3 PWM Pin Output Enable Register 0x178 read-write n 0x0 0x0 TIMER3_PWMPOLCTL TIMER3_PWMPOLCTL Timer3 PWM Pin Output Polar Control Register 0x174 read-write n 0x0 0x0 TIMER3_PWMSCTL TIMER3_PWMSCTL Timer3 PWM Synchronous Control Register 0x194 read-write n 0x0 0x0 TIMER3_PWMSTATUS TIMER3_PWMSTATUS Timer3 PWM Status Register 0x19C read-write n 0x0 0x0 TIMER3_PWMSWBRK TIMER3_PWMSWBRK Timer3 PWM Software Trigger Brake Control Register 0x17C read-write n 0x0 0x0 TIMER3_TRGCTL TIMER3_TRGCTL Timer3 Trigger Control Register 0x11C read-write n 0x0 0x0 TRNG TRNG Register Map TRNG 0x0 0x0 0x8 registers n 0xC 0x4 registers n ACT TRNG_ACT TRNG Activation Register 0xC -1 read-write n 0x0 0x0 ACT Random Number Generator Activation\nAfter enable the ACT bit, it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1.\nNote: ACT is an enable bit of analog part. When TRNG is not required to generate random number, TRNGEN (TRNG_CTL[0]) bit and ACT bit should be set to 0 to reduce power consumption. 7 1 read-write 0 TRNG inactive #0 1 TRNG active #1 CTL TRNG_CTL TRNG Control Register and Status 0x0 read-write n 0x0 0x0 CLKPSC Clock Prescaler\nThe CLKPSC is the peripheral clock frequency range for the selected value , the CLKPSC setting must be higher than or equal to the actual peripheral clock frequency (for correct random bit generation). To change the CLKPSC setting, set TRNGEN bit to 0, change CLKPSC, and set TRNGEN bit to 1 to re-enable the TRNG. 2 4 read-write 0 80 ~ 100 MHz #0000 1 60 ~ 80 MHz #0001 2 50 ~60 MHz #0010 3 40 ~50 MHz #0011 4 30 ~40 MHz #0100 5 25 ~30 MHz #0101 6 20 ~25 MHz #0110 7 15 ~20 MHz #0111 8 12 ~15 MHz #1000 9 9 ~12 MHz #1001 10 7 ~9 MHz #1010 11 6 ~7 MHz #1011 12 5 ~6 MHz #1100 13 4 ~5 MHz #1101 15 Reserved #1111 DVIEN Data Valid Interrupt Enable Bit 6 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 DVIF Data Valid (Read Only)\nThis bit is cleared to '0' by read TRNG_DATA. 1 1 read-only 0 Data is not valid. Reading from RNGD returns 0x00000000 #0 1 Data is valid. A valid random number can be read form RNGD #1 READY Random Number Generator Ready (Read Only)\nAfter ACT (TRNG_ACT[7]) bit is set, the READY bit become to 1 after a delay of 90us~120us. 7 1 read-only 0 RNG is not ready or was not activated #0 1 RNG is ready to be enabled #1 Reversed Reversed 8 24 read-write TRNGEN Random Number Generator Enable Bit\nThis bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became 1.\nNote: TRNGEN is an enable bit of digital part. When TRNG is not required to generate random number, TRNGEN bit and ACT (TRNG_ACT[7]) bit should be set to 0 to reduce power consumption. 0 1 read-write 0 TRNG Disabled #0 1 TRNG Enabled #1 DATA TRNG_DATA TRNG Data Register 0x4 read-only n 0x0 0x0 DATA Random Number Generator Data (Read Only)\nThe DATA store the random number generated by TRNG and can be read only once. 0 8 read-only UART0 UART Register Map UART 0x0 0x0 0x4C registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.164. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.164.\nNote: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.164. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.164. 24 4 read-write UART_BRCOMP UART_BRCOMP UART Baud Rate Compensation Register 0x3C read-write n 0x0 0x0 BRCOMP Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit. 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Incoming Data Wake-up Compensation Register 0x48 read-write n 0x0 0x0 STCOMP Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select 0 2 read-write 0 UART function #00 1 LIN function #01 2 IrDA function #10 3 RS-485 function #11 TXRXDIS TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated. #1 RDAIF Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-write 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-write 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-write 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINCTL UART_LINCTL UART LIN Control Register 0x34 -1 read-write n 0x0 0x0 BITERREN Bit Error Detect Enable Bit 12 1 read-write 0 Bit error detection function Disabled #0 1 Bit error detection function Enabled #1 BRKDETEN LIN Break Detection Enable Bit 10 1 read-write 0 LIN break detection Disabled #0 1 LIN break detection Enabled #1 BRKFL LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1. 16 4 read-write BSL LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field. 20 2 read-write 0 The LIN break/sync delimiter length is 1-bit time #00 1 The LIN break/sync delimiter length is 2-bit time #01 2 The LIN break/sync delimiter length is 3-bit time #10 3 The LIN break/sync delimiter length is 4-bit time #11 HSEL LIN Header Select 22 2 read-write 0 The LIN header includes 'break field' #00 1 The LIN header includes 'break field' and 'sync field' #01 2 The LIN header includes 'break field', 'sync field' and 'frame ID field' #10 3 Reserved #11 IDPEN LIN ID Parity Enable Bit 9 1 read-write 0 LIN frame ID parity Disabled #0 1 LIN frame ID parity Enabled #1 LINRXOFF LIN Receiver Disable Bit 11 1 read-write 0 LIN receiver Enabled #0 1 LIN receiver Disabled #1 MUTE LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.16.5.10 (LIN slave mode). 4 1 read-write 0 LIN mute mode Disabled #0 1 LIN mute mode Enabled #1 PID LIN PID Bits\nIf the parity generated by hardware, user fill ID0~ID5 (PID [29:24]), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode. 24 8 read-write SENDH LIN TX Send Header Enable Bit The LIN TX header can be 'break field' or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]). Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]) user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]). Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 8 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 SLVAREN LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.16.5.10 (Slave mode with automatic resynchronization). 2 1 read-write 0 LIN automatic resynchronization Disabled #0 1 LIN automatic resynchronization Enabled #1 SLVDUEN LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.16.5.10 (Slave mode with automatic resynchronization). 3 1 read-write 0 UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time) #0 1 UART_BAUD is updated at the next received character. User must set the bit before checksum reception #1 SLVEN LIN Slave Mode Enable Bit 0 1 read-write 0 LIN slave mode Disabled #0 1 LIN slave mode Enabled #1 SLVHDEN LIN Slave Header Detection Enable Bit 1 1 read-write 0 LIN slave header detection Disabled #0 1 LIN slave header detection Enabled #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 Parity bit generated Disabled #0 1 Parity bit generated Enabled #1 PSS Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 Parity bit generated and checked by software #1 RXDINV RX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection\nThis field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_LINSTS UART_LINSTS UART LIN Status Register 0x38 read-write n 0x0 0x0 BITEF Bit Error Detect Status Flag \nAt TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. 9 1 read-write 0 Bit error not detected #0 1 Bit error detected #1 BRKDETF LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. 8 1 read-write 0 LIN break not detected #0 1 LIN break detected #1 SLVHDETF LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not. 0 1 read-write 0 LIN header not detected #0 1 LIN header detected (break + sync + frame ID) #1 SLVHEF LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', 'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', 'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'. 1 1 read-write 0 LIN header error not detected #0 1 LIN header error detected #1 SLVIDPEF LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct. 2 1 read-write 0 No active #0 1 Receipted frame ID parity is not correct #1 SLVSYNCF LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. 3 1 read-write 0 The current character is not at LIN sync state #0 1 The current character is at LIN sync state #1 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1613 and Figure 6.1614 for UART function mode.\nNote2: Refer to Figure 6.1624 and Figure 6.1625 for RS-485 function mode.\nNote3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode. 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out #1 UART1 UART Register Map UART 0x0 0x0 0x4C registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.164. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.164.\nNote: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.164. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.164. 24 4 read-write UART_BRCOMP UART_BRCOMP UART Baud Rate Compensation Register 0x3C read-write n 0x0 0x0 BRCOMP Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit. 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Incoming Data Wake-up Compensation Register 0x48 read-write n 0x0 0x0 STCOMP Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select 0 2 read-write 0 UART function #00 1 LIN function #01 2 IrDA function #10 3 RS-485 function #11 TXRXDIS TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-write 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-write 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-write 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINCTL UART_LINCTL UART LIN Control Register 0x34 -1 read-write n 0x0 0x0 BITERREN Bit Error Detect Enable Bit 12 1 read-write 0 Bit error detection function Disabled #0 1 Bit error detection function Enabled #1 BRKDETEN LIN Break Detection Enable Bit 10 1 read-write 0 LIN break detection Disabled #0 1 LIN break detection Enabled #1 BRKFL LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1. 16 4 read-write BSL LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field. 20 2 read-write 0 The LIN break/sync delimiter length is 1-bit time #00 1 The LIN break/sync delimiter length is 2-bit time #01 2 The LIN break/sync delimiter length is 3-bit time #10 3 The LIN break/sync delimiter length is 4-bit time #11 HSEL LIN Header Select 22 2 read-write 0 The LIN header includes 'break field' #00 1 The LIN header includes 'break field' and 'sync field' #01 2 The LIN header includes 'break field', 'sync field' and 'frame ID field' #10 3 Reserved #11 IDPEN LIN ID Parity Enable Bit 9 1 read-write 0 LIN frame ID parity Disabled #0 1 LIN frame ID parity Enabled #1 LINRXOFF LIN Receiver Disable Bit 11 1 read-write 0 LIN receiver Enabled #0 1 LIN receiver Disabled #1 MUTE LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.16.5.10 (LIN slave mode). 4 1 read-write 0 LIN mute mode Disabled #0 1 LIN mute mode Enabled #1 PID LIN PID Bits\nIf the parity generated by hardware, user fill ID0~ID5 (PID [29:24]), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode. 24 8 read-write SENDH LIN TX Send Header Enable Bit The LIN TX header can be 'break field' or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]). Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]) user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]). Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 8 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 SLVAREN LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.16.5.10 (Slave mode with automatic resynchronization). 2 1 read-write 0 LIN automatic resynchronization Disabled #0 1 LIN automatic resynchronization Enabled #1 SLVDUEN LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.16.5.10 (Slave mode with automatic resynchronization). 3 1 read-write 0 UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time) #0 1 UART_BAUD is updated at the next received character. User must set the bit before checksum reception #1 SLVEN LIN Slave Mode Enable Bit 0 1 read-write 0 LIN slave mode Disabled #0 1 LIN slave mode Enabled #1 SLVHDEN LIN Slave Header Detection Enable Bit 1 1 read-write 0 LIN slave header detection Disabled #0 1 LIN slave header detection Enabled #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 Parity bit generated Disabled #0 1 Parity bit generated Enabled #1 PSS Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 Parity bit generated and checked by software #1 RXDINV RX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection\nThis field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_LINSTS UART_LINSTS UART LIN Status Register 0x38 read-write n 0x0 0x0 BITEF Bit Error Detect Status Flag \nAt TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. 9 1 read-write 0 Bit error not detected #0 1 Bit error detected #1 BRKDETF LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. 8 1 read-write 0 LIN break not detected #0 1 LIN break detected #1 SLVHDETF LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not. 0 1 read-write 0 LIN header not detected #0 1 LIN header detected (break + sync + frame ID) #1 SLVHEF LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', 'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', 'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'. 1 1 read-write 0 LIN header error not detected #0 1 LIN header error detected #1 SLVIDPEF LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct. 2 1 read-write 0 No active #0 1 Receipted frame ID parity is not correct #1 SLVSYNCF LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. 3 1 read-write 0 The current character is not at LIN sync state #0 1 The current character is at LIN sync state #1 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1613 and Figure 6.1614 for UART function mode.\nNote2: Refer to Figure 6.1624 and Figure 6.1625 for RS-485 function mode.\nNote3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode. 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out #1 UART2 UART Register Map UART 0x0 0x0 0x30 registers n 0x3C 0x10 registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.164. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.164.\nNote: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.164. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.164. 24 4 read-write UART_BRCOMP UART_BRCOMP UART Baud Rate Compensation Register 0x3C read-write n 0x0 0x0 BRCOMP Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit. 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Incoming Data Wake-up Compensation Register 0x48 read-write n 0x0 0x0 STCOMP Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select 0 2 read-write 0 UART function #00 1 LIN function #01 2 IrDA function #10 3 RS-485 function #11 TXRXDIS TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-write 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-write 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-write 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 Parity bit generated Disabled #0 1 Parity bit generated Enabled #1 PSS Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 Parity bit generated and checked by software #1 RXDINV RX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection\nThis field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1613 and Figure 6.1614 for UART function mode.\nNote2: Refer to Figure 6.1624 and Figure 6.1625 for RS-485 function mode.\nNote3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode. 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out #1 UART3 UART Register Map UART 0x0 0x0 0x30 registers n 0x3C 0x10 registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.164. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.164.\nNote: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.164. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.164. 24 4 read-write UART_BRCOMP UART_BRCOMP UART Baud Rate Compensation Register 0x3C read-write n 0x0 0x0 BRCOMP Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit. 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Incoming Data Wake-up Compensation Register 0x48 read-write n 0x0 0x0 STCOMP Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select 0 2 read-write 0 UART function #00 1 LIN function #01 2 IrDA function #10 3 RS-485 function #11 TXRXDIS TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-write 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-write 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-write 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 Parity bit generated Disabled #0 1 Parity bit generated Enabled #1 PSS Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 Parity bit generated and checked by software #1 RXDINV RX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection\nThis field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1613 and Figure 6.1614 for UART function mode.\nNote2: Refer to Figure 6.1624 and Figure 6.1625 for RS-485 function mode.\nNote3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode. 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out #1 UART4 UART Register Map UART 0x0 0x0 0x30 registers n 0x3C 0x10 registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.164. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.164.\nNote: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.164. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.164. 24 4 read-write UART_BRCOMP UART_BRCOMP UART Baud Rate Compensation Register 0x3C read-write n 0x0 0x0 BRCOMP Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit. 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Incoming Data Wake-up Compensation Register 0x48 read-write n 0x0 0x0 STCOMP Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select 0 2 read-write 0 UART function #00 1 LIN function #01 2 IrDA function #10 3 RS-485 function #11 TXRXDIS TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-write 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-write 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-write 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 Parity bit generated Disabled #0 1 Parity bit generated Enabled #1 PSS Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 Parity bit generated and checked by software #1 RXDINV RX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection\nThis field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1613 and Figure 6.1614 for UART function mode.\nNote2: Refer to Figure 6.1624 and Figure 6.1625 for RS-485 function mode.\nNote3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode. 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out #1 UART5 UART Register Map UART 0x0 0x0 0x30 registers n 0x3C 0x10 registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.164. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.164.\nNote: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.164. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.164. 24 4 read-write UART_BRCOMP UART_BRCOMP UART Baud Rate Compensation Register 0x3C read-write n 0x0 0x0 BRCOMP Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit. 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Incoming Data Wake-up Compensation Register 0x48 read-write n 0x0 0x0 STCOMP Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select 0 2 read-write 0 UART function #00 1 LIN function #01 2 IrDA function #10 3 RS-485 function #11 TXRXDIS TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-write 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-write 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-write 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 Parity bit generated Disabled #0 1 Parity bit generated Enabled #1 PSS Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 Parity bit generated and checked by software #1 RXDINV RX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection\nThis field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1613 and Figure 6.1614 for UART function mode.\nNote2: Refer to Figure 6.1624 and Figure 6.1625 for RS-485 function mode.\nNote3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode. 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out #1 UI2C0 UI2CI2C Register Map UI2CI2C 0x0 0x0 0x4 registers n 0x2C 0xC registers n 0x44 0x24 registers n 0x8 0x4 registers n 0x88 0x8 registers n UI2C_ADDRMSK0 UI2C_ADDRMSK0 USCI Device Address Mask Register 0 0x4C read-write n 0x0 0x0 ADDRMSK USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\nNote: The wake-up function can not use address mask. 0 10 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 UI2C_ADDRMSK1 UI2C_ADDRMSK1 USCI Device Address Mask Register 1 0x50 read-write n 0x0 0x0 UI2C_ADMAT UI2C_ADMAT I2C Slave Match Address Register 0x88 read-write n 0x0 0x0 ADMAT0 USCI Address 0 Match Status Register\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 0 1 read-write ADMAT1 USCI Address 1 Match Status Register\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 1 1 read-write UI2C_BRGEN UI2C_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider 16 10 read-write DSCNT Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter is Disabled #0 1 Time measurement counter is Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 UI2C_CTL UI2C_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UI2C_DEVADDR0 UI2C_DEVADDR0 USCI Device Address Register 0 0x44 read-write n 0x0 0x0 DEVADDR Device Address\nIn I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].\nNote 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.\nNote 2: When software set 10'h000, the address can not be used. 0 10 read-write UI2C_DEVADDR1 UI2C_DEVADDR1 USCI Device Address Register 1 0x48 read-write n 0x0 0x0 UI2C_LINECTL UI2C_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0]. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UI2C_PROTCTL UI2C_PROTCTL USCI Protocol Control Register 0x5C read-write n 0x0 0x0 AA Assert Acknowledge Control 1 1 read-write ADDR10EN Address 10-bit Function Enable Bit 4 1 read-write 0 Address match 10 bit function Disabled #0 1 Address match 10 bit function Enabled #1 GCFUNC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 MONEN Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. 9 1 read-write 0 The monitor mode Disabled #0 1 The monitor mode Enabled #1 PROTEN I2C Protocol Enable Bit 31 1 read-write 0 I2C Protocol Disabled #0 1 I2C Protocol Enabled #1 PTRG I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. 5 1 write-only 0 I2C's stretch disabled and the I2C protocol function will go ahead #0 1 I2C's stretch active #1 SCLOUTEN SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt. 8 1 read-write 0 SCL output will be forced high due to open drain mechanism #0 1 I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt #1 STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 3 1 read-write STO I2C STOP Control 2 1 read-write TOCNT Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode. 16 10 read-write UI2C_PROTIEN UI2C_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 ACKIEN Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. 6 1 read-write 0 The acknowledge interrupt Disabled #0 1 The acknowledge interrupt Enabled #1 ARBLOIEN Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected. 4 1 read-write 0 The arbitration lost interrupt Disabled #0 1 The arbitration lost interrupt Enabled #1 ERRIEN Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])). 5 1 read-write 0 The error interrupt Disabled #0 1 The error interrupt Enabled #1 NACKIEN Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master. 3 1 read-write 0 The non - acknowledge interrupt Disabled #0 1 The non - acknowledge interrupt Enabled #1 STARIEN START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected. 1 1 read-write 0 The start condition interrupt Disabled #0 1 The start condition interrupt Enabled #1 STORIEN STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected. 2 1 read-write 0 The stop condition interrupt Disabled #0 1 The stop condition interrupt Enabled #1 TOIEN Time-out Interrupt Enable Bit\nIn I2C protocol, this bit enables the interrupt generation in case of a time-out event. 0 1 read-write 0 The time-out interrupt Disabled #0 1 The time-out interrupt Enabled #1 UI2C_PROTSTS UI2C_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 ACKIF Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit 13 1 read-write 0 An acknowledge has not been received #0 1 An acknowledge has been received #1 ARBLOIF Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit 11 1 read-write 0 An arbitration has not been lost #0 1 An arbitration has been lost #1 BUSHANG Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. 18 1 read-write 0 The bus is normal status for transmission #0 1 The bus is hang-up status for transmission #1 ERRARBLO Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. 19 1 read-write 0 The bus is normal status for transmission #0 1 The bus is error arbitration lost status for transmission #1 ERRIF Error Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit\nNote2: This bit is set for slave mode, and user must write 1 into STO register to the defined 'not addressed' slave mode. 12 1 read-write 0 An I2C error has not been detected #0 1 An I2C error has been detected #1 NACKIF Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit 10 1 read-write 0 A non - acknowledge has not been received #0 1 A non - acknowledge has been received #1 ONBUSY On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 6 1 read-write 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 SLAREAD Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 15 1 read-write 0 A slave R/W bit is 1 has not been detected #0 1 A slave R/W bit is 1 has been detected #1 SLASEL Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 14 1 read-write 0 The device is not selected as slave #0 1 The device is selected as slave #1 STARIF Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.\nNote: It is cleared by software writing 1 into this bit 8 1 read-write 0 A start condition has not yet been detected #0 1 A start condition has been detected #1 STORIF Stop Condition Received Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit 9 1 read-write 0 A stop condition has not yet been detected #0 1 A stop condition has been detected #1 TOIF Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit 5 1 read-write 0 A time-out interrupt status has not occurred #0 1 A time-out interrupt status has occurred #1 WKAKDONE Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set. 16 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WRSTSWK Read/Write Status Bit in Address Wake-up Frame 17 1 read-write 0 Write command be record on the address match wake-up frame #0 1 Read command be record on the address match wake-up frame #1 UI2C_RXDAT UI2C_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C. 0 16 read-only UI2C_TMCTL UI2C_TMCTL I2C Timing Configure Control Register 0x8C read-write n 0x0 0x0 HTCTL Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode. 16 9 read-write STCTL Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.. 0 9 read-write UI2C_TXDAT UI2C_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 TXDAT Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. 0 16 write-only UI2C_WKCTL UI2C_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 WKADDREN Wake-up Address Match Enable Bit 1 1 read-write 0 The chip is woken up according data toggle #0 1 The chip is woken up according address match #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UI2C_WKSTS UI2C_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write UI2C1 UI2CI2C Register Map UI2CI2C 0x0 0x0 0x4 registers n 0x2C 0xC registers n 0x44 0x24 registers n 0x8 0x4 registers n 0x88 0x8 registers n UI2C_ADDRMSK0 UI2C_ADDRMSK0 USCI Device Address Mask Register 0 0x4C read-write n 0x0 0x0 ADDRMSK USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\nNote: The wake-up function can not use address mask. 0 10 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 UI2C_ADDRMSK1 UI2C_ADDRMSK1 USCI Device Address Mask Register 1 0x50 read-write n 0x0 0x0 UI2C_ADMAT UI2C_ADMAT I2C Slave Match Address Register 0x88 read-write n 0x0 0x0 ADMAT0 USCI Address 0 Match Status Register\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 0 1 read-write ADMAT1 USCI Address 1 Match Status Register\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 1 1 read-write UI2C_BRGEN UI2C_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider 16 10 read-write DSCNT Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter is Disabled #0 1 Time measurement counter is Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 UI2C_CTL UI2C_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UI2C_DEVADDR0 UI2C_DEVADDR0 USCI Device Address Register 0 0x44 read-write n 0x0 0x0 DEVADDR Device Address\nIn I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].\nNote 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.\nNote 2: When software set 10'h000, the address can not be used. 0 10 read-write UI2C_DEVADDR1 UI2C_DEVADDR1 USCI Device Address Register 1 0x48 read-write n 0x0 0x0 UI2C_LINECTL UI2C_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0]. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UI2C_PROTCTL UI2C_PROTCTL USCI Protocol Control Register 0x5C read-write n 0x0 0x0 AA Assert Acknowledge Control 1 1 read-write ADDR10EN Address 10-bit Function Enable Bit 4 1 read-write 0 Address match 10 bit function Disabled #0 1 Address match 10 bit function Enabled #1 GCFUNC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 MONEN Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. 9 1 read-write 0 The monitor mode Disabled #0 1 The monitor mode Enabled #1 PROTEN I2C Protocol Enable Bit 31 1 read-write 0 I2C Protocol Disabled #0 1 I2C Protocol Enabled #1 PTRG I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. 5 1 write-only 0 I2C's stretch disabled and the I2C protocol function will go ahead #0 1 I2C's stretch active #1 SCLOUTEN SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt. 8 1 read-write 0 SCL output will be forced high due to open drain mechanism #0 1 I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt #1 STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 3 1 read-write STO I2C STOP Control 2 1 read-write TOCNT Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode. 16 10 read-write UI2C_PROTIEN UI2C_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 ACKIEN Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. 6 1 read-write 0 The acknowledge interrupt Disabled #0 1 The acknowledge interrupt Enabled #1 ARBLOIEN Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected. 4 1 read-write 0 The arbitration lost interrupt Disabled #0 1 The arbitration lost interrupt Enabled #1 ERRIEN Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])). 5 1 read-write 0 The error interrupt Disabled #0 1 The error interrupt Enabled #1 NACKIEN Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master. 3 1 read-write 0 The non - acknowledge interrupt Disabled #0 1 The non - acknowledge interrupt Enabled #1 STARIEN START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected. 1 1 read-write 0 The start condition interrupt Disabled #0 1 The start condition interrupt Enabled #1 STORIEN STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected. 2 1 read-write 0 The stop condition interrupt Disabled #0 1 The stop condition interrupt Enabled #1 TOIEN Time-out Interrupt Enable Bit\nIn I2C protocol, this bit enables the interrupt generation in case of a time-out event. 0 1 read-write 0 The time-out interrupt Disabled #0 1 The time-out interrupt Enabled #1 UI2C_PROTSTS UI2C_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 ACKIF Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit 13 1 read-write 0 An acknowledge has not been received #0 1 An acknowledge has been received #1 ARBLOIF Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit 11 1 read-write 0 An arbitration has not been lost #0 1 An arbitration has been lost #1 BUSHANG Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. 18 1 read-write 0 The bus is normal status for transmission #0 1 The bus is hang-up status for transmission #1 ERRARBLO Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. 19 1 read-write 0 The bus is normal status for transmission #0 1 The bus is error arbitration lost status for transmission #1 ERRIF Error Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit\nNote2: This bit is set for slave mode, and user must write 1 into STO register to the defined 'not addressed' slave mode. 12 1 read-write 0 An I2C error has not been detected #0 1 An I2C error has been detected #1 NACKIF Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit 10 1 read-write 0 A non - acknowledge has not been received #0 1 A non - acknowledge has been received #1 ONBUSY On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 6 1 read-write 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 SLAREAD Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 15 1 read-write 0 A slave R/W bit is 1 has not been detected #0 1 A slave R/W bit is 1 has been detected #1 SLASEL Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 14 1 read-write 0 The device is not selected as slave #0 1 The device is selected as slave #1 STARIF Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.\nNote: It is cleared by software writing 1 into this bit 8 1 read-write 0 A start condition has not yet been detected #0 1 A start condition has been detected #1 STORIF Stop Condition Received Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit 9 1 read-write 0 A stop condition has not yet been detected #0 1 A stop condition has been detected #1 TOIF Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit 5 1 read-write 0 A time-out interrupt status has not occurred #0 1 A time-out interrupt status has occurred #1 WKAKDONE Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set. 16 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WRSTSWK Read/Write Status Bit in Address Wake-up Frame 17 1 read-write 0 Write command be record on the address match wake-up frame #0 1 Read command be record on the address match wake-up frame #1 UI2C_RXDAT UI2C_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C. 0 16 read-only UI2C_TMCTL UI2C_TMCTL I2C Timing Configure Control Register 0x8C read-write n 0x0 0x0 HTCTL Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode. 16 9 read-write STCTL Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.. 0 9 read-write UI2C_TXDAT UI2C_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 TXDAT Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. 0 16 write-only UI2C_WKCTL UI2C_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 WKADDREN Wake-up Address Match Enable Bit 1 1 read-write 0 The chip is woken up according data toggle #0 1 The chip is woken up according address match #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UI2C_WKSTS UI2C_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write USBD USBD Register Map USBD 0x0 0x0 0x1C registers n 0x20 0x8 registers n 0x500 0xC0 registers n 0x88 0xC registers n ATTR USBD_ATTR USB Device Bus Status and Attribution Register 0x10 -1 read-write n 0x0 0x0 BYTEM CPU Access USB SRAM Size Mode Selection 10 1 read-write 0 Word mode: The size of the transfer from CPU to USB SRAM can be Word only #0 1 Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only #1 DPPUEN Pull-up Resistor on USB_DP Enable Bit 8 1 read-write 0 Pull-up resistor in USB_D+ bus Disabled #0 1 Pull-up resistor in USB_D+ bus Active #1 L1RESUME LPM L1 Resume\nNote: This bit is read only. 13 1 read-write 0 Bus no LPM L1 state resume #0 1 LPM L1 state Resume from LPM L1 state suspend #1 L1SUSPEND LPM L1 Suspend\nNote: This bit is read only. 12 1 read-write 0 Bus no L1 state suspend #0 1 This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged #1 LPMACK LPM Token Acknowledge Enable Bit 11 1 read-write 0 the valid LPM Token will be NYET #0 1 the valid LPM Token will be ACK #1 PHYEN PHY Transceiver Function Enable Bit 4 1 read-write 0 PHY transceiver function Disabled #0 1 PHY transceiver function Enabled #1 RESUME Resume Status\nNote: This bit is read only. 2 1 read-write 0 No bus resume #0 1 Resume from suspend #1 RWAKEUP Remote Wake-up 5 1 read-write 0 Release the USB bus from K state #0 1 Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up #1 SUSPEND Suspend Status\nNote: This bit is read only. 1 1 read-write 0 Bus no suspend #0 1 Bus idle more than 3ms, either cable is plugged out or host is sleeping #1 TOUT Time-out Status\nNote: This bit is read only. 3 1 read-write 0 No time-out #0 1 No Bus response more than 18 bits time #1 USBEN USB Controller Enable Bit 7 1 read-write 0 USB Controller Disabled #0 1 USB Controller Enabled #1 USBRST USB Reset Status\nNote: This bit is read only. 0 1 read-write 0 Bus no reset #0 1 Bus reset when SE0 (single-ended 0) more than 2.5us #1 BUFSEG0 USBD_BUFSEG0 Endpoint 0 Buffer Segmentation Register 0x500 read-write n 0x0 0x0 BUFSEG Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is\nUSBD_SRAM address + { BUFSEG, 3'b000}\nRefer to the section 6.29.5.7 for the endpoint SRAM structure and its description. 3 6 read-write BUFSEG1 USBD_BUFSEG1 Endpoint 1 Buffer Segmentation Register 0x510 read-write n 0x0 0x0 BUFSEG10 USBD_BUFSEG10 Endpoint 10 Buffer Segmentation Register 0x5A0 read-write n 0x0 0x0 BUFSEG11 USBD_BUFSEG11 Endpoint 11 Buffer Segmentation Register 0x5B0 read-write n 0x0 0x0 BUFSEG2 USBD_BUFSEG2 Endpoint 2 Buffer Segmentation Register 0x520 read-write n 0x0 0x0 BUFSEG3 USBD_BUFSEG3 Endpoint 3 Buffer Segmentation Register 0x530 read-write n 0x0 0x0 BUFSEG4 USBD_BUFSEG4 Endpoint 4 Buffer Segmentation Register 0x540 read-write n 0x0 0x0 BUFSEG5 USBD_BUFSEG5 Endpoint 5 Buffer Segmentation Register 0x550 read-write n 0x0 0x0 BUFSEG6 USBD_BUFSEG6 Endpoint 6 Buffer Segmentation Register 0x560 read-write n 0x0 0x0 BUFSEG7 USBD_BUFSEG7 Endpoint 7 Buffer Segmentation Register 0x570 read-write n 0x0 0x0 BUFSEG8 USBD_BUFSEG8 Endpoint 8 Buffer Segmentation Register 0x580 read-write n 0x0 0x0 BUFSEG9 USBD_BUFSEG9 Endpoint 9 Buffer Segmentation Register 0x590 read-write n 0x0 0x0 CFG0 USBD_CFG0 Endpoint 0 Configuration Register 0x508 read-write n 0x0 0x0 CSTALL Clear STALL Response 9 1 read-write 0 Disable the device to clear the STALL handshake in setup stage #0 1 Clear the device to response STALL handshake in setup stage #1 DSQSYNC Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on this bit. 7 1 read-write 0 DATA0 PID #0 1 DATA1 PID #1 EPNUM Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint. 0 4 read-write ISOCH Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake. 4 1 read-write 0 No Isochronous endpoint #0 1 Isochronous endpoint #1 STATE Endpoint STATE 5 2 read-write 0 Endpoint is Disabled #00 1 Out endpoint #01 2 IN endpoint #10 3 Undefined #11 CFG1 USBD_CFG1 Endpoint 1 Configuration Register 0x518 read-write n 0x0 0x0 CFG10 USBD_CFG10 Endpoint 10 Configuration Register 0x5A8 read-write n 0x0 0x0 CFG11 USBD_CFG11 Endpoint 11 Configuration Register 0x5B8 read-write n 0x0 0x0 CFG2 USBD_CFG2 Endpoint 2 Configuration Register 0x528 read-write n 0x0 0x0 CFG3 USBD_CFG3 Endpoint 3 Configuration Register 0x538 read-write n 0x0 0x0 CFG4 USBD_CFG4 Endpoint 4 Configuration Register 0x548 read-write n 0x0 0x0 CFG5 USBD_CFG5 Endpoint 5 Configuration Register 0x558 read-write n 0x0 0x0 CFG6 USBD_CFG6 Endpoint 6 Configuration Register 0x568 read-write n 0x0 0x0 CFG7 USBD_CFG7 Endpoint 7 Configuration Register 0x578 read-write n 0x0 0x0 CFG8 USBD_CFG8 Endpoint 8 Configuration Register 0x588 read-write n 0x0 0x0 CFG9 USBD_CFG9 Endpoint 9 Configuration Register 0x598 read-write n 0x0 0x0 CFGP0 USBD_CFGP0 Endpoint 0 Set Stall and Clear In/Out Ready Control Register 0x50C read-write n 0x0 0x0 CLRRDY Clear Ready\nWhen the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.\nFor IN token, write '1' to clear the IN token had ready to transmit the data to host.\nFor OUT token, write '1' to clear the OUT token had ready to receive the data from host.\nThis bit is write 1 only and is always 0 when it is read back. 0 1 read-write SSTALL Set STALL 1 1 read-write 0 Disable the device to response STALL #0 1 Set the device to respond STALL automatically #1 CFGP1 USBD_CFGP1 Endpoint 1 Set Stall and Clear In/Out Ready Control Register 0x51C read-write n 0x0 0x0 CFGP10 USBD_CFGP10 Endpoint 10 Set Stall and Clear In/Out Ready Control Register 0x5AC read-write n 0x0 0x0 CFGP11 USBD_CFGP11 Endpoint 11 Set Stall and Clear In/Out Ready Control Register 0x5BC read-write n 0x0 0x0 CFGP2 USBD_CFGP2 Endpoint 2 Set Stall and Clear In/Out Ready Control Register 0x52C read-write n 0x0 0x0 CFGP3 USBD_CFGP3 Endpoint 3 Set Stall and Clear In/Out Ready Control Register 0x53C read-write n 0x0 0x0 CFGP4 USBD_CFGP4 Endpoint 4 Set Stall and Clear In/Out Ready Control Register 0x54C read-write n 0x0 0x0 CFGP5 USBD_CFGP5 Endpoint 5 Set Stall and Clear In/Out Ready Control Register 0x55C read-write n 0x0 0x0 CFGP6 USBD_CFGP6 Endpoint 6 Set Stall and Clear In/Out Ready Control Register 0x56C read-write n 0x0 0x0 CFGP7 USBD_CFGP7 Endpoint 7 Set Stall and Clear In/Out Ready Control Register 0x57C read-write n 0x0 0x0 CFGP8 USBD_CFGP8 Endpoint 8 Set Stall and Clear In/Out Ready Control Register 0x58C read-write n 0x0 0x0 CFGP9 USBD_CFGP9 Endpoint 9 Set Stall and Clear In/Out Ready Control Register 0x59C read-write n 0x0 0x0 EPSTS USBD_EPSTS USB Device Endpoint Status Register 0xC read-only n 0x0 0x0 OV Overrun\nIt indicates that the received data is over the maximum payload number or not. 7 1 read-only 0 No overrun #0 1 Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes #1 EPSTS0 USBD_EPSTS0 USB Device Endpoint Status Register 0 0x20 read-only n 0x0 0x0 EPSTS5 Endpoint 5 Status\nThese bits are used to indicate the current status of this endpoint 20 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS6 Endpoint 6 Status\nThese bits are used to indicate the current status of this endpoint 24 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS7 Endpoint 7 Status\nThese bits are used to indicate the current status of this endpoint 28 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS1 USBD_EPSTS1 USB Device Endpoint Status Register 1 0x24 read-only n 0x0 0x0 EPSTS10 Endpoint 10 Status\nThese bits are used to indicate the current status of this endpoint 8 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS11 Endpoint 11 Status\nThese bits are used to indicate the current status of this endpoint 12 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS8 Endpoint 8 Status\nThese bits are used to indicate the current status of this endpoint 0 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS9 Endpoint 9 Status\nThese bits are used to indicate the current status of this endpoint 4 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 FADDR USBD_FADDR USB Device Function Address Register 0x8 read-write n 0x0 0x0 FADDR USB Device Function Address 0 7 read-write FN USBD_FN USB Frame number Register 0x8C read-only n 0x0 0x0 FN Frame Number\nThese bits contain the 11-bits frame number in the last received SOF packet. 0 11 read-only INTEN USBD_INTEN USB Device Interrupt Enable Register 0x0 read-write n 0x0 0x0 BUSIEN Bus Event Interrupt Enable Bit 0 1 read-write 0 BUS event interrupt Disabled #0 1 BUS event interrupt Enabled #1 INNAKEN Active NAK Function and Its Status in IN Token 15 1 read-write 0 When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1 register, so that the USB interrupt event will not be asserted #0 1 IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token #1 NEVWKIEN USB No-event-wake-up Interrupt Enable Bit 3 1 read-write 0 No-event-wake-up Interrupt Disabled #0 1 No-event-wake-up Interrupt Enabled #1 SOFIEN Start of Frame Interrupt Enable Bit 4 1 read-write 0 SOF Interrupt Disabled #0 1 SOF Interrupt Enabled #1 USBIEN USB Event Interrupt Enable Bit 1 1 read-write 0 USB event interrupt Disabled #0 1 USB event interrupt Enabled #1 VBDETIEN VBUS Detection Interrupt Enable Bit 2 1 read-write 0 VBUS detection Interrupt Disabled #0 1 VBUS detection Interrupt Enabled #1 WKEN Wake-up Function Enable Bit 8 1 read-write 0 USB wake-up function Disabled #0 1 USB wake-up function Enabled #1 INTSTS USBD_INTSTS USB Device Interrupt Event Status Register 0x4 read-write n 0x0 0x0 BUSIF BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus. 0 1 read-write 0 No BUS event occurred #0 1 Bus event occurred check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0] #1 EPEVT0 Endpoint 0's USB Event Status 16 1 read-write 0 No event occurred in endpoint 0 #0 1 USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1] #1 EPEVT1 Endpoint 1's USB Event Status 17 1 read-write 0 No event occurred in endpoint 1 #0 1 USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1] #1 EPEVT10 Endpoint 10's USB Event Status 26 1 read-write 0 No event occurred in endpoint 10 #0 1 USB event occurred on Endpoint 10, check USBD_EPSTS1[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1] #1 EPEVT11 Endpoint 11's USB Event Status 27 1 read-write 0 No event occurred in endpoint 11 #0 1 USB event occurred on Endpoint 11, check USBD_EPSTS1[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1] #1 EPEVT2 Endpoint 2's USB Event Status 18 1 read-write 0 No event occurred in endpoint 2 #0 1 USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1] #1 EPEVT3 Endpoint 3's USB Event Status 19 1 read-write 0 No event occurred in endpoint 3 #0 1 USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1] #1 EPEVT4 Endpoint 4's USB Event Status 20 1 read-write 0 No event occurred in endpoint 4 #0 1 USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1] #1 EPEVT5 Endpoint 5's USB Event Status 21 1 read-write 0 No event occurred in endpoint 5 #0 1 USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1] #1 EPEVT6 Endpoint 6's USB Event Status 22 1 read-write 0 No event occurred in endpoint 6 #0 1 USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1] #1 EPEVT7 Endpoint 7's USB Event Status 23 1 read-write 0 No event occurred in endpoint 7 #0 1 USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1] #1 EPEVT8 Endpoint 8's USB Event Status 24 1 read-write 0 No event occurred in endpoint 8 #0 1 USB event occurred on Endpoint 8, check USBD_EPSTS1[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1] #1 EPEVT9 Endpoint 9's USB Event Status 25 1 read-write 0 No event occurred in endpoint 9 #0 1 USB event occurred on Endpoint 9, check USBD_EPSTS1[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1] #1 NEVWKIF No-event-wake-up Interrupt Status 3 1 read-write 0 NEVWK event does not occur #0 1 No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3] #1 SETUP Setup Event Status 31 1 read-write 0 No Setup event #0 1 Setup event occurred, cleared by write 1 to USBD_INTSTS[31] #1 SOFIF Start of Frame Interrupt Status 4 1 read-write 0 SOF event does not occur #0 1 SOF event occurred, cleared by write 1 to USBD_INTSTS[4] #1 USBIF USB Event Interrupt Status\nThe USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. 1 1 read-write 0 No USB event occurred #0 1 USB event occurred, check EPSTS0~11[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or SETUP (USBD_INTSTS[31]) #1 VBDETIF VBUS Detection Interrupt Status 2 1 read-write 0 There is not attached/detached event in the USB #0 1 There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2] #1 LPMATTR USBD_LPMATTR USB LPM Attribution Register 0x88 read-only n 0x0 0x0 LPMBESL LPM Best Effort Service Latency\nThese bits contain the BESL value received with last ACK LPM Token 4 4 read-only 0 125us #0000 1 150us #0001 2 200us #0010 3 300us #0011 4 400us #0100 5 500us #0101 6 1000us #0110 7 2000us #0111 8 3000us #1000 9 4000us #1001 10 5000us #1010 11 6000us #1011 12 7000us #1100 13 8000us #1101 14 9000us #1110 15 10000us #1111 LPMLINKSTS LPM Link State\nThese bits contain the bLinkState received with last ACK LPM Token 0 4 read-only 0 Reserve #0000 1 L1 (Sleep) #0001 LPMRWAKUP LPM Remote Wakeup\nThis bit contains the bRemoteWake value received with last ACK LPM Token 8 1 read-only MXPLD0 USBD_MXPLD0 Endpoint 0 Maximal Payload Register 0x504 read-write n 0x0 0x0 MXPLD Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.\n(1) When the register is written by CPU, \nFor IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.\nFor OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.\n(2) When the register is read by CPU,\nFor IN token, the value of MXPLD is indicated by the data length be transmitted to host\nFor OUT token, the value of MXPLD is indicated the actual data length receiving from host.\nNote: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 0 9 read-write MXPLD1 USBD_MXPLD1 Endpoint 1 Maximal Payload Register 0x514 read-write n 0x0 0x0 MXPLD10 USBD_MXPLD10 Endpoint 10 Maximal Payload Register 0x5A4 read-write n 0x0 0x0 MXPLD11 USBD_MXPLD11 Endpoint 11 Maximal Payload Register 0x5B4 read-write n 0x0 0x0 MXPLD2 USBD_MXPLD2 Endpoint 2 Maximal Payload Register 0x524 read-write n 0x0 0x0 MXPLD3 USBD_MXPLD3 Endpoint 3 Maximal Payload Register 0x534 read-write n 0x0 0x0 MXPLD4 USBD_MXPLD4 Endpoint 4 Maximal Payload Register 0x544 read-write n 0x0 0x0 MXPLD5 USBD_MXPLD5 Endpoint 5 Maximal Payload Register 0x554 read-write n 0x0 0x0 MXPLD6 USBD_MXPLD6 Endpoint 6 Maximal Payload Register 0x564 read-write n 0x0 0x0 MXPLD7 USBD_MXPLD7 Endpoint 7 Maximal Payload Register 0x574 read-write n 0x0 0x0 MXPLD8 USBD_MXPLD8 Endpoint 8 Maximal Payload Register 0x584 read-write n 0x0 0x0 MXPLD9 USBD_MXPLD9 Endpoint 9 Maximal Payload Register 0x594 read-write n 0x0 0x0 SE0 USBD_SE0 USB Device Drive SE0 Control Register 0x90 -1 read-write n 0x0 0x0 SE0 Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low. 0 1 read-write 0 Normal operation #0 1 Force USB PHY transceiver to drive SE0 #1 STBUFSEG USBD_STBUFSEG SETUP Token Buffer Segmentation Register 0x18 read-write n 0x0 0x0 STBUFSEG SETUP Token Buffer Segmentation\nIt is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is\nUSBD_SRAM address + {STBUFSEG, 3'b000} \nNote: It is used for SETUP token only. 3 6 read-write VBUSDET USBD_VBUSDET USB Device VBUS Detection Register 0x14 read-only n 0x0 0x0 VBUSDET Device VBUS Detection 0 1 read-only 0 Controller is not attached to the USB host #0 1 Controller is attached to the USB host #1 USBH USBH Register Map USBH 0x0 0x0 0x54 registers n 0x200 0x8 registers n 0x58 0x4 registers n HcBulkCurrentED HcBulkCurrentED Host Controller Bulk Current ED Register 0x2C read-write n 0x0 0x0 BCED Bulk Current Head ED\nPointer to indicate the physical address of the current endpoint of the Bulk list. 4 28 read-write HcBulkHeadED HcBulkHeadED Host Controller Bulk Head ED Register 0x28 read-write n 0x0 0x0 BHED Bulk Head ED\nPointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list. 4 28 read-write HcCommandStatus HcCommandStatus Host Controller Command Status Register 0x8 read-write n 0x0 0x0 BLF Bulk List Filled\nSet high to indicate there is an active TD on the Bulk list. This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list. 2 1 read-write 0 No active TD found or Host Controller begins to process the head of the Bulk list #0 1 An active TD added or found on the Bulk list #1 CLF Control List Filled\nSet high to indicate there is an active TD on the Control List. It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List. 1 1 read-write 0 No active TD found or Host Controller begins to process the head of the Control list #0 1 An active TD added or found on the Control list #1 HCR Host Controller Reset\nThis bit is set to initiate the software reset of Host Controller. This bit is cleared by the Host Controller, upon completed of the reset operation.\nThis bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports. 0 1 read-write 0 Host Controller is not in software reset state #0 1 Host Controller is in software reset state #1 SOC Schedule Overrun Count\nThese bits are incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set. 16 2 read-write HcControl HcControl Host Controller Control Register 0x4 read-write n 0x0 0x0 BLE Bulk List Enable Bit 5 1 read-write 0 Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled #0 1 Processing of the Bulk list in the next frame Enabled #1 CBSR Control Bulk Service Ratio\nThis specifies the service ratio between Control and Bulk EDs. Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs. The internal count will be retained when crossing the frame boundary. In case of reset, HCD is responsible for restoring this\nValue. 0 2 read-write 0 Number of Control EDs over Bulk EDs served is 1:1 #00 1 Number of Control EDs over Bulk EDs served is 2:1 #01 2 Number of Control EDs over Bulk EDs served is 3:1 #10 3 Number of Control EDs over Bulk EDs served is 4:1 #11 CLE Control List Enable Bit 4 1 read-write 0 Processing of the Control list after next SOF (Start-Of-Frame) Disabled #0 1 Processing of the Control list in the next frame Enabled #1 HCFS Host Controller Functional State\nThis field sets the Host Controller state. The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port. States are: 6 2 read-write 0 USBSUSPEND #00 1 USBOPERATIONAL #01 2 USBRESUME #10 3 USBRESET #11 IE Isochronous List Enable Bit\nBoth ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list. Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list. 3 1 read-write 0 Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled #0 1 Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too #1 PLE Periodic List Enable Bit When set, this bit enables processing of the Periodic (interrupt and isochronous) list. The Host Controller checks this bit prior to attempting any periodic transfers in a frame. Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high. 2 1 read-write 0 Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled #0 1 Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled #1 HcControlCurrentED HcControlCurrentED Host Controller Control Current ED Register 0x24 read-write n 0x0 0x0 CCED Control Current Head ED\nPointer to indicate the physical address of the current Endpoint Descriptor of the Control list. 4 28 read-write HcControlHeadED HcControlHeadED Host Controller Control Head ED Register 0x20 read-write n 0x0 0x0 CHED Control Head ED\nPointer to indicate physical address of the first Endpoint Descriptor of the Control list. 4 28 read-write HcDoneHead HcDoneHead Host Controller Done Head Register 0x30 read-write n 0x0 0x0 DH Done Head\nPointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue. 4 28 read-write HcFmInterval HcFmInterval Host Controller Frame Interval Register 0x34 -1 read-write n 0x0 0x0 FI Frame Interval\nThis field specifies the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999 is stored here. 0 14 read-write FIT Frame Interval Toggle\nThis bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]). 31 1 read-write 0 Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]) #0 1 Host Controller Driver loads a new value into FI (HcFmInterval[13:0]) #1 FSMPS FS Largest Data Packet\nThis field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. 16 15 read-write HcFmNumber HcFmNumber Host Controller Frame Number Register 0x3C read-only n 0x0 0x0 FN Frame Number\nThis 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]). The count rolls over from 'FFFFh' to '0h.' 0 16 read-only HcFmRemaining HcFmRemaining Host Controller Frame Remaining Register 0x38 read-only n 0x0 0x0 FR Frame Remaining\nWhen the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period. When the count reaches 0, (end of frame) the counter reloads with Frame Interval. In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL. 0 14 read-only FRT Frame Remaining Toggle\nThis bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0. 31 1 read-only HcHCCA HcHCCA Host Controller Communication Area Register 0x18 read-write n 0x0 0x0 HCCA Host Controller Communication Area\nPointer to indicate base address of the Host Controller Communication Area (HCCA). 8 24 read-write HcInterruptDisable HcInterruptDisable Host Controller Interrupt Disable Register 0x14 read-write n 0x0 0x0 FNO Frame Number Overflow Disable Bit\nWrite Operation: 5 1 read-write 0 No effect.\nInterrupt generation due to FNO (HcInterruptStatus[5]) Disabled #0 1 Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.\nInterrupt generation due to FNO (HcInterruptStatus[5]) Enabled #1 MIE Master Interrupt Disable Bit\nGlobal interrupt disable. Writing '1' to disable all interrupts.\nWrite Operation: 31 1 read-write 0 No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high #0 1 Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high.\nInterrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high #1 RD Resume Detected Disable Bit\nWrite Operation: 3 1 read-write 0 No effect.\nInterrupt generation due to RD (HcInterruptStatus[3]) Disabled #0 1 Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.\nInterrupt generation due to RD (HcInterruptStatus[3]) Enabled #1 RHSC Root Hub Status Change Disable Bit\nWrite Operation: 6 1 read-write 0 No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]) Disabled #0 1 Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.\nInterrupt generation due to RHSC (HcInterruptStatus[6]) Enabled #1 SF Start of Frame Disable Bit\nWrite Operation: 2 1 read-write 0 No effect.\nInterrupt generation due to SF (HcInterruptStatus[2]) Disabled #0 1 Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.\nInterrupt generation due to SF (HcInterruptStatus[2]) Enabled #1 SO Scheduling Overrun Disable Bit\nWrite Operation: 0 1 read-write 0 No effect.\nInterrupt generation due to SO (HcInterruptStatus[0]) Disabled #0 1 Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.\nInterrupt generation due to SO (HcInterruptStatus[0]) Enabled #1 WDH Write Back Done Head Disable Bit\nWrite Operation: 1 1 read-write 0 No effect.\nInterrupt generation due to WDH (HcInterruptStatus[1]) Disabled #0 1 Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.\nInterrupt generation due to WDH (HcInterruptStatus[1]) Enabled #1 HcInterruptEnable HcInterruptEnable Host Controller Interrupt Enable Register 0x10 read-write n 0x0 0x0 FNO Frame Number Overflow Enable Bit\nWrite Operation: 5 1 read-write 0 No effect.\nInterrupt generation due to FNO (HcInterruptStatus[5]) Disabled #0 1 Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled #1 MIE Master Interrupt Enable Bit\nThis bit is a global interrupt enable. A write of '1' allows interrupts to be enabled via the specific enable bits listed above.\nWrite Operation: 31 1 read-write 0 No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high #0 1 Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high #1 RD Resume Detected Enable Bit\nWrite Operation: 3 1 read-write 0 No effect.\nInterrupt generation due to RD (HcInterruptStatus[3]) Disabled #0 1 Interrupt generation due to RD (HcInterruptStatus[3]) Enabled #1 RHSC Root Hub Status Change Enable Bit\nWrite Operation: 6 1 read-write 0 No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]) Disabled #0 1 Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled #1 SF Start of Frame Enable Bit\nWrite Operation: 2 1 read-write 0 No effect.\nInterrupt generation due to SF (HcInterruptStatus[2]) Disabled #0 1 Interrupt generation due to SF (HcInterruptStatus[2]) Enabled #1 SO Scheduling Overrun Enable Bit\nWrite Operation: 0 1 read-write 0 No effect.\nInterrupt generation due to SO (HcInterruptStatus[0]) Disabled #0 1 Interrupt generation due to SO (HcInterruptStatus[0]) Enabled #1 WDH Write Back Done Head Enable Bit\nWrite Operation: 1 1 read-write 0 No effect.\nInterrupt generation due to WDH (HcInterruptStatus[1]) Disabled #0 1 Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled #1 HcInterruptStatus HcInterruptStatus Host Controller Interrupt Status Register 0xC read-write n 0x0 0x0 FNO Frame Number Overflow\nThis bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. 5 1 read-write 0 The bit 15 of Frame Number didn't change #0 1 The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1 #1 RD Resume Detected\nSet when Host Controller detects resume signaling on a downstream port. 3 1 read-write 0 No resume signaling detected on a downstream port #0 1 Resume signaling detected on a downstream port #1 RHSC Root Hub Status Change\nThis bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed. 6 1 read-write 0 The content of HcRhStatus and the content of HcRhPortStatus1 register didn't change #0 1 The content of HcRhStatus or the content of HcRhPortStatus1 register has changed #1 SF Start of Frame\nSet when the Frame Management functional block signals a 'Start of Frame' event. Host Control generates a SOF token at the same time. 2 1 read-write 0 Not the start of a frame #0 1 Indicate the start of a frame and Host Controller generates a SOF token #1 SO Scheduling Overrun\nSet when the List Processor determines a Schedule Overrun has occurred. 0 1 read-write 0 Schedule Overrun didn't occur #0 1 Schedule Overrun has occurred #1 WDH Write Back Done Head\nSet after the Host Controller has written HcDoneHead to HccaDoneHead. Further updates of the HccaDoneHead will not occur until this bit has been cleared. 1 1 read-write 0 Host Controller didn't update HccaDoneHead #0 1 Host Controller has written HcDoneHead to HccaDoneHead #1 HcLSThreshold HcLSThreshold Host Controller Low-speed Threshold Register 0x44 -1 read-write n 0x0 0x0 LST Low-speed Threshold 0 12 read-write HcMiscControl HcMiscControl Host Controller Miscellaneous Control Register 0x204 read-write n 0x0 0x0 ABORT AHB Bus ERROR Response\nThis bit indicates there is an ERROR response received in AHB bus. 1 1 read-write 0 No ERROR response received #0 1 ERROR response received #1 DPRT1 Disable Port 1\nThis bit controls if the connection between USB host controller and transceiver of port 1 is disabled. If the connection is disabled, the USB host controller will not recognize any event of USB bus.\nSet this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is. 16 1 read-write 0 The connection between USB host controller and transceiver of port 1 Enabled #0 1 The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode #1 OCAL Over Current Active Low\nThis bit controls the polarity of over current flag from external power IC. 3 1 read-write 0 Over current flag is high active #0 1 Over current flag is low active #1 PPCAL Port Power Control Active Low\nThis bit controls the polarity of port power control to external power IC. 4 1 read-write 0 Port power control is high active #0 1 Port power control is low active #1 HcPeriodCurrentED HcPeriodCurrentED Host Controller Period Current ED Register 0x1C read-write n 0x0 0x0 PCED Periodic Current ED\nPointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor. 4 28 read-write HcPeriodicStart HcPeriodicStart Host Controller Periodic Start Register 0x40 read-write n 0x0 0x0 PS Periodic Start\nThis field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. 0 14 read-write HcPhyControl HcPhyControl Host Controller PHY Control Register 0x200 -1 read-write n 0x0 0x0 STBYEN USB Transceiver Standby Enable Bit\nThis bit controls if USB transceiver could enter the standby mode to reduce power consumption. 27 1 read-write 0 The USB transceiver would never enter the standby mode #0 1 The USB transceiver will enter standby mode while port is in power off state (port power is inactive) #1 HcRevision HcRevision Host Controller Revision Register 0x0 -1 read-only n 0x0 0x0 REV Revision Number\nIndicates the Open HCI Specification revision number implemented by the Hardware. Host Controller supports 1.1 specification. 0 8 read-only HcRhDescriptorA HcRhDescriptorA Host Controller Root Hub Descriptor A Register 0x48 -1 read-write n 0x0 0x0 NDP Number Downstream Ports\nUSB host control supports two downstream ports and only one port is available in this series of chip. 0 8 read-write NOCP No over Current Protection\nThis bit describes how the over current status for the Root Hub ports reported. 12 1 read-write 0 Over current status is reported #0 1 Over current status is not reported #1 OCPM over Current Protection Mode\nThis bit describes how the over current status for the Root Hub ports reported. This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared. 11 1 read-write 0 Global Over current #0 1 Individual Over current #1 PSM Power Switching Mode\nThis bit is used to specify how the power switching of the Root Hub ports is controlled. 8 1 read-write 0 Global Switching #0 1 Individual Switching #1 HcRhDescriptorB HcRhDescriptorB Host Controller Root Hub Descriptor B Register 0x4C read-write n 0x0 0x0 PPCM Port Power Control Mask\nGlobal power switching. This field is only valid if PowerSwitchingMode is set (individual port switching). When set, the port only responds to individual port power switching commands (Set/ClearPortPower). When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).\nNote: PPCM[15:2] and PPCM[0] are reserved. 16 16 read-write 0 Port power controlled by global power switching 0 1 Port power controlled by port power switching 1 HcRhPortStatus1 HcRhPortStatus1 Host Controller Root Hub Port Status [1] 0x58 read-write n 0x0 0x0 CCS CurrentConnectStatus (Read) or ClearPortEnable Bit (Write)\nWrite Operation: 0 1 read-write 0 No effect.\nNo device connected #0 1 Clear port enable.\nDevice connected #1 CSC Connect Status Change\nThis bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).\nWrite 1 to clear this bit to zero. 16 1 read-write 0 No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change) #0 1 Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed) #1 LSDA Low Speed Device Attached (Read) or Clear Port Power (Write)\nThis bit defines the speed (and bud idle) of the attached device. It is only valid when CCS (HcRhPortStatus1[0]) is set.\nThis bit is also used to clear port power.\nWrite Operation: 9 1 read-write 0 No effect.\nFull Speed device #0 1 Clear PPS (HcRhPortStatus1[8]).\nLow-speed device #1 OCIC Port over Current Indicator Change\nThis bit is set when POCI (HcRhPortStatus1[3]) changes.\nWrite 1 to clear this bit to zero. 19 1 read-write 0 POCI (HcRhPortStatus1[3]) didn't change #0 1 POCI (HcRhPortStatus1[3]) changes #1 PES Port Enable Status\nWrite Operation: 1 1 read-write 0 No effect.\nPort Disabled #0 1 Set port enable.\nPort Enabled #1 PESC Port Enable Status Change\nThis bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.\nWrite 1 to clear this bit to zero. 17 1 read-write 0 PES (HcRhPortStatus1[1]) didn't change #0 1 PES (HcRhPortStatus1[1]) changed #1 POCI Port over Current Indicator (Read) or Clear Port Suspend (Write)\nThis bit reflects the state of the over current status pin dedicated to this port. This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.\nThis bit is also used to initiate the selective result sequence for the port.\nWrite Operation: 3 1 read-write 0 No effect.\nNo over current condition #0 1 Clear port suspend.\nOver current condition #1 PPS Port Power Status\nThis bit reflects the power state of the port regardless of the power switching mode.\nWrite Operation: 8 1 read-write 0 No effect.\nPort power is Disabled #0 1 Port Power Enabled.\nPort power is Enabled #1 PRS Port Reset Status\nThis bit reflects the reset state of the port.\nWrite Operation: 4 1 read-write 0 No effect.\nPort reset signal is not active #0 1 Set port reset.\nPort reset signal is active #1 PRSC Port Reset Status Change\nThis bit indicates that the port reset signal has completed.\nWrite 1 to clear this bit to zero. 20 1 read-write 0 Port reset is not complete #0 1 Port reset is complete #1 PSS Port Suspend Status\nThis bit indicates the port is suspended\nWrite Operation: 2 1 read-write 0 No effect.\nPort is not suspended #0 1 Set port suspend.\nPort is selectively suspended #1 PSSC Port Suspend Status Change\nThis bit indicates the completion of the selective resume sequence for the port.\nWrite 1 to clear this bit to zero. 18 1 read-write 0 Port resume is not completed #0 1 Port resume completed #1 HcRhStatus HcRhStatus Host Controller Root Hub Status Register 0x50 read-write n 0x0 0x0 CRWE Clear Remote Wake-up Enable Bit\nThis bit is use to clear DRWE (HcRhStatus[15]).\nThis bit always read as zero.\nWrite Operation: 31 1 read-write 0 No effect #0 1 Clear DRWE (HcRhStatus[15]) #1 DRWE Device Remote Wakeup Enable Bit\nThis bit controls if port's Connect Status Change as a remote wake-up event.\nWrite Operation: 15 1 read-write 0 No effect.\nConnect Status Change as a remote wake-up event Disabled #0 1 Connect Status Change as a remote wake-up event Enabled #1 LPS Clear Global Power 0 1 read-write 0 No effect #0 1 Clear global power #1 LPSC Set Global Power 16 1 read-write 0 No effect #0 1 Set global power #1 OCI over Current Indicator\nThis bit reflects the state of the over current status pin. This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared. 1 1 read-write 0 No over current condition #0 1 Over current condition #1 OCIC over Current Indicator Change\nThis bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).\nWrite 1 to clear this bit to zero. 17 1 read-write 0 OCI (HcRhStatus[1]) didn't change #0 1 OCI (HcRhStatus[1]) change #1 USPI0 USCISPI Register Map USCISPI 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x1C registers n 0x54 0x14 registers n USPI_BRGEN USPI_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider 16 10 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fDIV_CLK #00 1 fPROT_CLK #01 2 fSCLK #10 3 fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter Disabled #0 1 Time measurement counter Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 USPI_BUFCTL USPI_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 read-write n 0x0 0x0 RXCLR Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Interrupt Enable Bit 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset\nNote: It is cleared automatically after one PCLK cycle. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 TXUDRIEN Slave Transmit Under-run Interrupt Enable Bit 6 1 read-write 0 Transmit under-run interrupt Disabled #0 1 Transmit under-run interrupt Enabled #1 USPI_BUFSTS USPI_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-write n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator (Read Only) 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator (Read Only) 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit. 3 1 read-write 0 A receive buffer overrun event has not been detected #0 1 A receive buffer overrun event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator (Read Only) 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty and available for the next transmission datum #1 TXFULL Transmit Buffer Full Indicator (Read Only) 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 TXUDRIF Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit 11 1 read-write 0 A transmit buffer under-run event has not been detected #0 1 A transmit buffer under-run event has been detected #1 USPI_CLKIN USPI_CLKIN USCI Input Clock Signal Configuration Register 0x28 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_CTL USPI_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 USPI_CTLIN0 USPI_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_DATIN0 USPI_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_INTEN USPI_INTEN USCI Interrupt Enable Register 0x4 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event. 4 1 read-write 0 The receive end interrupt Disabled #0 1 The receive end interrupt Enabled #1 RXSTIEN Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event. 3 1 read-write 0 The receive start interrupt Disabled #0 1 The receive start interrupt Enabled #1 TXENDIEN Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event. 2 1 read-write 0 The transmit finish interrupt Disabled #0 1 The transmit finish interrupt Enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event. 1 1 read-write 0 The transmit start interrupt Disabled #0 1 The transmit start interrupt Enabled #1 USPI_LINECTL USPI_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin. 5 1 read-write 0 Data output level is not inverted #0 1 Data output level is inverted #1 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0]. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 USPI_PDMACTL USPI_PDMACTL USCI PDMA Control Register 0x40 read-write n 0x0 0x0 PDMAEN PDMA Mode Enable Bit 3 1 read-write 0 PDMA function Disabled #0 1 PDMA function Enabled #1 PDMARST PDMA Reset 0 1 read-write 0 No effect #0 1 Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically #1 RXPDMAEN PDMA Receive Channel Available 2 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN PDMA Transmit Channel Available 1 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 USPI_PROTCTL USPI_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable (Master Only) 3 1 read-write 0 Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit #0 1 Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 PROTEN SPI Protocol Enable Bit 31 1 read-write 0 SPI Protocol Disabled #0 1 SPI Protocol Enabled #1 SCLKMODE Serial Bus Clock Mode\nThis bit field defines the SCLK idle status, data transmit, and data receive edge. 6 2 read-write SLAVE Slave Mode Selection 0 1 read-write 0 Master mode #0 1 Slave mode #1 SLV3WIRE Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. 1 1 read-write 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 SLVTOCNT Slave Mode Time-out Period (Slave Only)\nIn Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function.\nExample: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. 16 10 read-write SS Slave Select Control (Master Only)\nIf AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol, the internal slave select signal is active high. 2 1 read-write SUSPITV Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\nExample: 8 4 read-write TSMSEL Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. 12 3 read-write TXUDRPOL Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level when no data is available for transferring. 28 1 read-write 0 The output data level is 0 if TX under run event occurs #0 1 The output data level is 1 if TX under run event occurs #1 USPI_PROTIEN USPI_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]), bit count error event occurs. 3 1 read-write 0 The Slave mode bit count error interrupt Disabled #0 1 The Slave mode bit count error interrupt Enabled #1 SLVTOIEN Slave Time-out Interrupt Enable Bit\nIn SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. 2 1 read-write 0 The Slave time-out interrupt Disabled #0 1 The Slave time-out interrupt Enabled #1 SSACTIEN Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active. 1 1 read-write 0 Slave select active interrupt generation Disabled #0 1 Slave select active interrupt generation Enabled #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. 0 1 read-write 0 Slave select inactive interrupt generation Disabled #0 1 Slave select inactive interrupt generation Enabled #1 USPI_PROTSTS USPI_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 17 1 read-only 0 SPI is in idle state #0 1 SPI is in busy state #1 RXENDIF Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit 4 1 read-write 0 Receive end event did not occur #0 1 Receive end event occurred #1 RXSTIF Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit 3 1 read-write 0 Receive start event did not occur #0 1 Receive start event occurred #1 SLVBEIF Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit. 6 1 read-write 0 Slave bit count error event did not occur #0 1 Slave bit count error event occurred #1 SLVTOIF Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit 5 1 read-write 0 Slave time-out event did not occur #0 1 Slave time-out event occurred #1 SLVUDR Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. 18 1 read-only 0 Slave transmit under-run event does not occur #0 1 Slave transmit under-run event occurs #1 SSACTIF Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high. 9 1 read-write 0 The slave select signal has not changed to active #0 1 The slave select signal has changed to active #1 SSINAIF Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high. 8 1 read-write 0 The slave select signal has not changed to inactive #0 1 The slave select signal has changed to inactive #1 SSLINE Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus. 16 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXENDIF Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit 2 1 read-write 0 Transmit end event did not occur #0 1 Transmit end event occurred #1 TXSTIF Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit 1 1 read-write 0 Transmit start event did not occur #0 1 Transmit start event occurred #1 USPI_RXDAT USPI_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer. 0 16 read-only USPI_TXDAT USPI_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 PORTDIR Port Direction Control 16 1 write-only 0 The data pin is configured as output mode #0 1 The data pin is configured as input mode #1 TXDAT Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user has to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. 0 16 write-only USPI_WKCTL USPI_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 USPI_WKSTS USPI_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write USPI1 USCISPI Register Map USCISPI 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x1C registers n 0x54 0x14 registers n USPI_BRGEN USPI_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider 16 10 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fDIV_CLK #00 1 fPROT_CLK #01 2 fSCLK #10 3 fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter Disabled #0 1 Time measurement counter Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 USPI_BUFCTL USPI_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 read-write n 0x0 0x0 RXCLR Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Interrupt Enable Bit 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset\nNote: It is cleared automatically after one PCLK cycle. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 TXUDRIEN Slave Transmit Under-run Interrupt Enable Bit 6 1 read-write 0 Transmit under-run interrupt Disabled #0 1 Transmit under-run interrupt Enabled #1 USPI_BUFSTS USPI_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-write n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator (Read Only) 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator (Read Only) 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit. 3 1 read-write 0 A receive buffer overrun event has not been detected #0 1 A receive buffer overrun event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator (Read Only) 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty and available for the next transmission datum #1 TXFULL Transmit Buffer Full Indicator (Read Only) 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 TXUDRIF Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit 11 1 read-write 0 A transmit buffer under-run event has not been detected #0 1 A transmit buffer under-run event has been detected #1 USPI_CLKIN USPI_CLKIN USCI Input Clock Signal Configuration Register 0x28 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_CTL USPI_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 USPI_CTLIN0 USPI_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_DATIN0 USPI_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_INTEN USPI_INTEN USCI Interrupt Enable Register 0x4 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event. 4 1 read-write 0 The receive end interrupt Disabled #0 1 The receive end interrupt Enabled #1 RXSTIEN Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event. 3 1 read-write 0 The receive start interrupt Disabled #0 1 The receive start interrupt Enabled #1 TXENDIEN Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event. 2 1 read-write 0 The transmit finish interrupt Disabled #0 1 The transmit finish interrupt Enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event. 1 1 read-write 0 The transmit start interrupt Disabled #0 1 The transmit start interrupt Enabled #1 USPI_LINECTL USPI_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin. 5 1 read-write 0 Data output level is not inverted #0 1 Data output level is inverted #1 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0]. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 USPI_PDMACTL USPI_PDMACTL USCI PDMA Control Register 0x40 read-write n 0x0 0x0 PDMAEN PDMA Mode Enable Bit 3 1 read-write 0 PDMA function Disabled #0 1 PDMA function Enabled #1 PDMARST PDMA Reset 0 1 read-write 0 No effect #0 1 Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically #1 RXPDMAEN PDMA Receive Channel Available 2 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN PDMA Transmit Channel Available 1 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 USPI_PROTCTL USPI_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable (Master Only) 3 1 read-write 0 Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit #0 1 Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 PROTEN SPI Protocol Enable Bit 31 1 read-write 0 SPI Protocol Disabled #0 1 SPI Protocol Enabled #1 SCLKMODE Serial Bus Clock Mode\nThis bit field defines the SCLK idle status, data transmit, and data receive edge. 6 2 read-write SLAVE Slave Mode Selection 0 1 read-write 0 Master mode #0 1 Slave mode #1 SLV3WIRE Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. 1 1 read-write 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 SLVTOCNT Slave Mode Time-out Period (Slave Only)\nIn Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function.\nExample: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. 16 10 read-write SS Slave Select Control (Master Only)\nIf AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol, the internal slave select signal is active high. 2 1 read-write SUSPITV Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\nExample: 8 4 read-write TSMSEL Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. 12 3 read-write TXUDRPOL Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level when no data is available for transferring. 28 1 read-write 0 The output data level is 0 if TX under run event occurs #0 1 The output data level is 1 if TX under run event occurs #1 USPI_PROTIEN USPI_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]), bit count error event occurs. 3 1 read-write 0 The Slave mode bit count error interrupt Disabled #0 1 The Slave mode bit count error interrupt Enabled #1 SLVTOIEN Slave Time-out Interrupt Enable Bit\nIn SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. 2 1 read-write 0 The Slave time-out interrupt Disabled #0 1 The Slave time-out interrupt Enabled #1 SSACTIEN Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active. 1 1 read-write 0 Slave select active interrupt generation Disabled #0 1 Slave select active interrupt generation Enabled #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. 0 1 read-write 0 Slave select inactive interrupt generation Disabled #0 1 Slave select inactive interrupt generation Enabled #1 USPI_PROTSTS USPI_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 17 1 read-only 0 SPI is in idle state #0 1 SPI is in busy state #1 RXENDIF Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit 4 1 read-write 0 Receive end event did not occur #0 1 Receive end event occurred #1 RXSTIF Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit 3 1 read-write 0 Receive start event did not occur #0 1 Receive start event occurred #1 SLVBEIF Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit. 6 1 read-write 0 Slave bit count error event did not occur #0 1 Slave bit count error event occurred #1 SLVTOIF Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit 5 1 read-write 0 Slave time-out event did not occur #0 1 Slave time-out event occurred #1 SLVUDR Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. 18 1 read-only 0 Slave transmit under-run event does not occur #0 1 Slave transmit under-run event occurs #1 SSACTIF Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high. 9 1 read-write 0 The slave select signal has not changed to active #0 1 The slave select signal has changed to active #1 SSINAIF Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high. 8 1 read-write 0 The slave select signal has not changed to inactive #0 1 The slave select signal has changed to inactive #1 SSLINE Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus. 16 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXENDIF Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit 2 1 read-write 0 Transmit end event did not occur #0 1 Transmit end event occurred #1 TXSTIF Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit 1 1 read-write 0 Transmit start event did not occur #0 1 Transmit start event occurred #1 USPI_RXDAT USPI_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer. 0 16 read-only USPI_TXDAT USPI_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 PORTDIR Port Direction Control 16 1 write-only 0 The data pin is configured as output mode #0 1 The data pin is configured as input mode #1 TXDAT Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user has to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. 0 16 write-only USPI_WKCTL USPI_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 USPI_WKSTS USPI_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write UUART0 UUARTUART Register Map UUARTUART 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x1C registers n 0x54 0x14 registers n UUART_BRGEN UUART_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write DSCNT Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK is selected to fDIV_CLK #00 1 fSAMP_CLK is selected to fPROT_CLK #01 2 fSAMP_CLK is selected to fSCLK #10 3 fSAMP_CLK is selected to fREF_CLK #11 TMCNTEN Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Timing measurement counter is Disabled #0 1 Timing measurement counter is Enabled #1 TMCNTSRC Timing Measurement Counter Clock Source Selection 5 1 read-write 0 Timing measurement counter with fPROT_CLK #0 1 Timing measurement counter with fDIV_CLK #1 UUART_BUFCTL UUART_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 read-write n 0x0 0x0 RXCLR Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Error Interrupt Enable Bit 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset\nNote1: It is cleared automatically after one PCLK cycle.\nNote2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset\nNote: It is cleared automatically after one PCLK cycle. 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 UUART_BUFSTS UUART_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-write n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator (Read Only) 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator (Read Only) 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. \nNote: It is cleared by software writing 1 into this bit. 3 1 read-write 0 A receive buffer overrun error event has not been detected #0 1 A receive buffer overrun error event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator (Read Only) 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 TXFULL Transmit Buffer Full Indicator (Read Only) 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 UUART_CLKIN UUART_CLKIN USCI Input Clock Signal Configuration Register 0x28 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_CTL UUART_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UUART_CTLIN0 UUART_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_DATIN0 UUART_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 read-write n 0x0 0x0 EDGEDET Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode, it is suggested to set this bit field as 0x2. 3 2 read-write 0 The trigger event activation is disabled #00 1 A rising edge activates the trigger event of input data signal #01 2 A falling edge activates the trigger event of input data signal #10 3 Both edges activate the trigger event of input data signal #11 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_INTEN UUART_INTEN USCI Interrupt Enable Register 0x4 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event. 4 1 read-write 0 The receive end interrupt Disabled #0 1 The receive end interrupt Enabled #1 RXSTIEN Receive Start Interrupt Enable BIt\nThis bit enables the interrupt generation in case of a receive start event. 3 1 read-write 0 The receive start interrupt Disabled #0 1 The receive start interrupt Enabled #1 TXENDIEN Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event. 2 1 read-write 0 The transmit finish interrupt Disabled #0 1 The transmit finish interrupt Enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event. 1 1 read-write 0 The transmit start interrupt Disabled #0 1 The transmit start interrupt Enabled #1 UUART_LINECTL UUART_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol, the control signal means nRTS signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. 5 1 read-write 0 The value of USCIx_DAT1 is equal to the data shift register #0 1 The value of USCIx_DAT1 is the inversion of data shift register #1 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\nNote: In UART protocol, the length can be configured as 6~13 bits. 8 4 read-write 0 The data word contains 16 bits located at bit positions [15:0] #0000 1 Reserved #0001 2 Reserved #0010 3 Reserved #0011 4 The data word contains 4 bits located at bit positions [3:0] #0100 5 The data word contains 5 bits located at bit positions [4:0] #0101 6 The data word contains 6 bits located at bit positions [5:0] #0110 7 The data word contains 7 bits located at bit positions [6:0] #0111 8 The data word contains 8 bits located at bit positions [7:0] #1000 9 The data word contains 9 bits located at bit positions [8:0] #1001 10 The data word contains 10 bits located at bit positions [9:0] #1010 11 The data word contains 11 bits located at bit positions [10:0] #1011 12 The data word contains 12 bits located at bit positions [11:0] #1100 13 The data word contains 13 bits located at bit positions [12:0] #1101 14 The data word contains 14 bits located at bit positions [13:0] #1110 15 The data word contains 15 bits located at bit positions [14:0] #1111 LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UUART_PDMACTL UUART_PDMACTL USCI PDMA Control Register 0x40 read-write n 0x0 0x0 PDMAEN PDMA Mode Enable Bit 3 1 read-write 0 PDMA function Disabled #0 1 PDMA function Enabled #1 PDMARST PDMA Reset 0 1 read-write 0 No effect #0 1 Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically #1 RXPDMAEN PDMA Receive Channel Available 2 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN PDMA Transmit Channel Available 1 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 UUART_PROTCTL UUART_PROTCTL USCI Protocol Control Register 0x5C read-write n 0x0 0x0 ABREN Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTSTS[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled). 6 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 BCEN Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 29 1 read-write 0 Transmit Break Control Disabled #0 1 Transmit Break Control Enabled #1 BRDETITV Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.\nNote: This bit can be cleared to 0 by software writing '0' to the BRDETITV. 16 9 read-write CTSAUTOEN nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). 4 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 CTSWKEN nCTS Wake-up Mode Enable Bit 10 1 read-write 0 nCTS wake-up mode Disabled #0 1 nCTS wake-up mode Enabled #1 DATWKEN Data Wake-up Mode Enable Bit 9 1 read-write 0 Data wake-up mode Disabled #0 1 Data wake-up mode Enabled #1 EVENPARITY Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set. 2 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 PARITYEN Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame. 1 1 read-write 0 The parity bit Disabled #0 1 The parity bit Enabled #1 PROTEN UART Protocol Enable Bit 31 1 read-write 0 UART Protocol Disabled #0 1 UART Protocol Enabled #1 RTSAUDIREN nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the nRTS signal is inactive automatically.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2: This bit has effect only when the RTSAUTOEN is not set. 5 1 read-write 0 nRTS auto direction control Disabled #0 1 nRTS auto direction control Enabled #1 RTSAUTOEN nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set. 3 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 STICKEN Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information. 26 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 STOPB Stop Bits\nThis bit defines the number of stop bits in an UART frame. 0 1 read-write 0 The number of stop bits is 1 #0 1 The number of stop bits is 2 #1 WAKECNT Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is woken up from Power-down mode. 11 4 read-write UUART_PROTIEN UUART_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 1 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. 2 1 read-write 0 Receive line status interrupt Disabled #0 1 Receive line status interrupt Enabled #1 UUART_PROTSTS UUART_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 ABERRSTS Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.\nNote 1: This bit is set at the same time of ABRDETIF.\nNote 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS. 11 1 read-write 0 Auto-baud rate detect counter is not overrun #0 1 Auto-baud rate detect counter is overrun #1 ABRDETIF Auto-baud Rate Interrupt Flag This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. Note: This bit can be cleared by writing '1' to it. 9 1 read-write 0 Auto-baud rate detect function is not done #0 1 One Bit auto-baud rate detect function is done #1 BREAK Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits. 7 1 read-write 0 No Break is generated #0 1 Break is generated in the receiver bus #1 CTSLV nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input. 17 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 CTSSYNCLV nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal. 16 1 read-only 0 The internal synchronized nCTS is low #0 1 The internal synchronized nCTS is high #1 FRMERR Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits. 6 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PARITYERR Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits. 5 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXBUSY RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver. 10 1 read-only 0 The receiver is Idle #0 1 The receiver is BUSY #1 RXENDIF Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit. 4 1 read-write 0 A receive finish interrupt status has not occurred #0 1 A receive finish interrupt status has occurred #1 RXSTIF Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit. 3 1 read-write 0 A receive start interrupt status has not occurred #0 1 A receive start interrupt status has occurred #1 TXENDIF Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit. 2 1 read-write 0 A transmit end interrupt status has not occurred #0 1 A transmit end interrupt status has occurred #1 TXSTIF Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer. 1 1 read-write 0 A transmit start interrupt status has not occurred #0 1 A transmit start interrupt status has occurred #1 UUART_RXDAT UUART_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]). 0 16 read-only UUART_TXDAT UUART_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 TXDAT Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. 0 16 write-only UUART_WKCTL UUART_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UUART_WKSTS UUART_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write UUART1 UUARTUART Register Map UUARTUART 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x1C registers n 0x54 0x14 registers n UUART_BRGEN UUART_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write DSCNT Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK is selected to fDIV_CLK #00 1 fSAMP_CLK is selected to fPROT_CLK #01 2 fSAMP_CLK is selected to fSCLK #10 3 fSAMP_CLK is selected to fREF_CLK #11 TMCNTEN Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Timing measurement counter is Disabled #0 1 Timing measurement counter is Enabled #1 TMCNTSRC Timing Measurement Counter Clock Source Selection 5 1 read-write 0 Timing measurement counter with fPROT_CLK #0 1 Timing measurement counter with fDIV_CLK #1 UUART_BUFCTL UUART_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 read-write n 0x0 0x0 RXCLR Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Error Interrupt Enable Bit 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset\nNote1: It is cleared automatically after one PCLK cycle.\nNote2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset\nNote: It is cleared automatically after one PCLK cycle. 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 UUART_BUFSTS UUART_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-write n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator (Read Only) 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator (Read Only) 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. \nNote: It is cleared by software writing 1 into this bit. 3 1 read-write 0 A receive buffer overrun error event has not been detected #0 1 A receive buffer overrun error event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator (Read Only) 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 TXFULL Transmit Buffer Full Indicator (Read Only) 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 UUART_CLKIN UUART_CLKIN USCI Input Clock Signal Configuration Register 0x28 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_CTL UUART_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UUART_CTLIN0 UUART_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_DATIN0 UUART_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 read-write n 0x0 0x0 EDGEDET Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode, it is suggested to set this bit field as 0x2. 3 2 read-write 0 The trigger event activation is disabled #00 1 A rising edge activates the trigger event of input data signal #01 2 A falling edge activates the trigger event of input data signal #10 3 Both edges activate the trigger event of input data signal #11 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_INTEN UUART_INTEN USCI Interrupt Enable Register 0x4 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event. 4 1 read-write 0 The receive end interrupt Disabled #0 1 The receive end interrupt Enabled #1 RXSTIEN Receive Start Interrupt Enable BIt\nThis bit enables the interrupt generation in case of a receive start event. 3 1 read-write 0 The receive start interrupt Disabled #0 1 The receive start interrupt Enabled #1 TXENDIEN Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event. 2 1 read-write 0 The transmit finish interrupt Disabled #0 1 The transmit finish interrupt Enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event. 1 1 read-write 0 The transmit start interrupt Disabled #0 1 The transmit start interrupt Enabled #1 UUART_LINECTL UUART_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol, the control signal means nRTS signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. 5 1 read-write 0 The value of USCIx_DAT1 is equal to the data shift register #0 1 The value of USCIx_DAT1 is the inversion of data shift register #1 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\nNote: In UART protocol, the length can be configured as 6~13 bits. 8 4 read-write 0 The data word contains 16 bits located at bit positions [15:0] #0000 1 Reserved #0001 2 Reserved #0010 3 Reserved #0011 4 The data word contains 4 bits located at bit positions [3:0] #0100 5 The data word contains 5 bits located at bit positions [4:0] #0101 6 The data word contains 6 bits located at bit positions [5:0] #0110 7 The data word contains 7 bits located at bit positions [6:0] #0111 8 The data word contains 8 bits located at bit positions [7:0] #1000 9 The data word contains 9 bits located at bit positions [8:0] #1001 10 The data word contains 10 bits located at bit positions [9:0] #1010 11 The data word contains 11 bits located at bit positions [10:0] #1011 12 The data word contains 12 bits located at bit positions [11:0] #1100 13 The data word contains 13 bits located at bit positions [12:0] #1101 14 The data word contains 14 bits located at bit positions [13:0] #1110 15 The data word contains 15 bits located at bit positions [14:0] #1111 LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UUART_PDMACTL UUART_PDMACTL USCI PDMA Control Register 0x40 read-write n 0x0 0x0 PDMAEN PDMA Mode Enable Bit 3 1 read-write 0 PDMA function Disabled #0 1 PDMA function Enabled #1 PDMARST PDMA Reset 0 1 read-write 0 No effect #0 1 Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically #1 RXPDMAEN PDMA Receive Channel Available 2 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN PDMA Transmit Channel Available 1 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 UUART_PROTCTL UUART_PROTCTL USCI Protocol Control Register 0x5C read-write n 0x0 0x0 ABREN Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTSTS[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled). 6 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 BCEN Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 29 1 read-write 0 Transmit Break Control Disabled #0 1 Transmit Break Control Enabled #1 BRDETITV Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.\nNote: This bit can be cleared to 0 by software writing '0' to the BRDETITV. 16 9 read-write CTSAUTOEN nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). 4 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 CTSWKEN nCTS Wake-up Mode Enable Bit 10 1 read-write 0 nCTS wake-up mode Disabled #0 1 nCTS wake-up mode Enabled #1 DATWKEN Data Wake-up Mode Enable Bit 9 1 read-write 0 Data wake-up mode Disabled #0 1 Data wake-up mode Enabled #1 EVENPARITY Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set. 2 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 PARITYEN Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame. 1 1 read-write 0 The parity bit Disabled #0 1 The parity bit Enabled #1 PROTEN UART Protocol Enable Bit 31 1 read-write 0 UART Protocol Disabled #0 1 UART Protocol Enabled #1 RTSAUDIREN nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the nRTS signal is inactive automatically.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2: This bit has effect only when the RTSAUTOEN is not set. 5 1 read-write 0 nRTS auto direction control Disabled #0 1 nRTS auto direction control Enabled #1 RTSAUTOEN nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set. 3 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 STICKEN Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information. 26 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 STOPB Stop Bits\nThis bit defines the number of stop bits in an UART frame. 0 1 read-write 0 The number of stop bits is 1 #0 1 The number of stop bits is 2 #1 WAKECNT Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is woken up from Power-down mode. 11 4 read-write UUART_PROTIEN UUART_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 1 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. 2 1 read-write 0 Receive line status interrupt Disabled #0 1 Receive line status interrupt Enabled #1 UUART_PROTSTS UUART_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 ABERRSTS Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.\nNote 1: This bit is set at the same time of ABRDETIF.\nNote 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS. 11 1 read-write 0 Auto-baud rate detect counter is not overrun #0 1 Auto-baud rate detect counter is overrun #1 ABRDETIF Auto-baud Rate Interrupt Flag This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. Note: This bit can be cleared by writing '1' to it. 9 1 read-write 0 Auto-baud rate detect function is not done #0 1 One Bit auto-baud rate detect function is done #1 BREAK Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits. 7 1 read-write 0 No Break is generated #0 1 Break is generated in the receiver bus #1 CTSLV nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input. 17 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 CTSSYNCLV nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal. 16 1 read-only 0 The internal synchronized nCTS is low #0 1 The internal synchronized nCTS is high #1 FRMERR Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits. 6 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PARITYERR Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits. 5 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXBUSY RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver. 10 1 read-only 0 The receiver is Idle #0 1 The receiver is BUSY #1 RXENDIF Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit. 4 1 read-write 0 A receive finish interrupt status has not occurred #0 1 A receive finish interrupt status has occurred #1 RXSTIF Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit. 3 1 read-write 0 A receive start interrupt status has not occurred #0 1 A receive start interrupt status has occurred #1 TXENDIF Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit. 2 1 read-write 0 A transmit end interrupt status has not occurred #0 1 A transmit end interrupt status has occurred #1 TXSTIF Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer. 1 1 read-write 0 A transmit start interrupt status has not occurred #0 1 A transmit start interrupt status has occurred #1 UUART_RXDAT UUART_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]). 0 16 read-only UUART_TXDAT UUART_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 TXDAT Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. 0 16 write-only UUART_WKCTL UUART_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UUART_WKSTS UUART_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write WDT WDT Register Map WDT 0x0 0x0 0xC registers n ALTCTL WDT_ALTCTL WDT Alternative Control Register 0x4 read-write n 0x0 0x0 RSTDSEL WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by programming 0x5AA5 to RSTCNT to prevent WDT time-out reset happened. User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This register will be reset to 0 if WDT time-out reset happened. 0 2 read-write 0 WDT Reset Delay Period is 1026 * WDT_CLK #00 1 WDT Reset Delay Period is 130 * WDT_CLK #01 2 WDT Reset Delay Period is 18 * WDT_CLK #10 3 WDT Reset Delay Period is 3 * WDT_CLK #11 CTL WDT_CTL WDT Control Register 0x0 -1 read-write n 0x0 0x0 ICEDEBUG ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement affects WDT counting #0 1 ICE debug mode acknowledgement Disabled #1 IF WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it. 3 1 read-write 0 WDT time-out interrupt did not occur #0 1 WDT time-out interrupt occurred #1 INTEN WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. \nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 WDT time-out interrupt Disabled #0 1 WDT time-out interrupt Enabled #1 RSTEN WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 WDT time-out reset function Disabled #0 1 WDT time-out reset function Enabled #1 RSTF WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it. 2 1 read-write 0 WDT time-out reset did not occur #0 1 WDT time-out reset occurred #1 SYNC WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user executes enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Performing enable or disable WDTEN bit needs 2 * WDT_CLK period to become active. 30 1 read-only 0 Set WDTEN bit is completed #0 1 Set WDTEN bit is synchronizing and not become active yet #1 TOUTSEL WDT Time-out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 8 3 read-write 0 24 * WDT_CLK #000 1 26 * WDT_CLK #001 2 28 * WDT_CLK #010 3 210 * WDT_CLK #011 4 212 * WDT_CLK #100 5 214 * WDT_CLK #101 6 216 * WDT_CLK #110 7 218 * WDT_CLK #111 WDTEN WDT Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111, this bit is forced as 1 and user cannot change this bit to 0. 7 1 read-write 0 WDT Disabled (This action will reset the internal up counter value) #0 1 WDT Enabled #1 WKEN WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Chip can be woken up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT. 4 1 read-write 0 Wake-up trigger event Disabled if WDT time-out interrupt signal generated #0 1 Wake-up trigger event Enabled if WDT time-out interrupt signal generated #1 WKF WDT Time-out Wake-up Flag \nThis bit indicates the interrupt wake-up flag status of WDT\nNote: This bit is cleared by writing 1 to it. 5 1 read-write 0 WDT does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated #1 RSTCNT WDT_RSTCNT WDT Reset Counter Register 0x8 write-only n 0x0 0x0 RSTCNT WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.\nNote: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active.\nRSTCNT (WDT_RSTCNT[31:0]) bits are not write protected. 0 32 write-only WWDT WWDT Register Map WWDT 0x0 0x0 0x10 registers n CNT WWDT_CNT WWDT Counter Value Register 0xC -1 read-only n 0x0 0x0 CNTDAT WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. 0 6 read-only CTL WWDT_CTL WWDT Control Register 0x4 -1 read-write n 0x0 0x0 CMPDAT WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately. 16 6 read-write ICEDEBUG ICE Debug Mode Acknowledge Disable Bit\nWWDT down counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects WWDT counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN WWDT Interrupt Enable Bit\nIf this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU. 1 1 read-write 0 WWDT counter compare match interrupt Disabled #0 1 WWDT counter compare match interrupt Enabled #1 PSCSEL WWDT Counter Prescale Period Selection 8 4 read-write 0 Pre-scale is 1 Max time-out period is 1 * 64 * WWDT_CLK #0000 1 Pre-scale is 2 Max time-out period is 2 * 64 * WWDT_CLK #0001 2 Pre-scale is 4 Max time-out period is 4 * 64 * WWDT_CLK #0010 3 Pre-scale is 8 Max time-out period is 8 * 64 * WWDT_CLK #0011 4 Pre-scale is 16 Max time-out period is 16 * 64 * WWDT_CLK #0100 5 Pre-scale is 32 Max time-out period is 32 * 64 * WWDT_CLK #0101 6 Pre-scale is 64 Max time-out period is 64 * 64 * WWDT_CLK #0110 7 Pre-scale is 128 Max time-out period is 128 * 64 * WWDT_CLK #0111 8 Pre-scale is 192 Max time-out period is 192 * 64 * WWDT_CLK #1000 9 Pre-scale is 256 Max time-out period is 256 * 64 * WWDT_CLK #1001 10 Pre-scale is 384 Max time-out period is 384 * 64 * WWDT_CLK #1010 11 Pre-scale is 512 Max time-out period is 512 * 64 * WWDT_CLK #1011 12 Pre-scale is 768 Max time-out period is 768 * 64 * WWDT_CLK #1100 13 Pre-scale is 1024 Max time-out period is 1024 * 64 * WWDT_CLK #1101 14 Pre-scale is 1536 Max time-out period is 1536 * 64 * WWDT_CLK #1110 15 Pre-scale is 2048 Max time-out period is 2048 * 64 * WWDT_CLK #1111 WWDTEN WWDT Enable Bit 0 1 read-write 0 WWDT counter is stopped #0 1 WWDT counter starts counting #1 RLDCNT WWDT_RLDCNT WWDT Reload Counter Register 0x0 write-only n 0x0 0x0 RLDCNT WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]). If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated immediately. 0 32 write-only STATUS WWDT_STATUS WWDT Status Register 0x8 read-write n 0x0 0x0 WWDTIF WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 WWDT counter value matches CMPDAT #1 WWDTRF WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 WWDT time-out reset did not occur #0 1 WWDT time-out reset occurred #1