nuvoTon M471 2024.04.28 M471 SVD file 8 32 ACMP01 ACMP Register Map ACMP 0x0 0x0 0x18 registers n ACMP_CALCTL ACMP_CALCTL Analog Comparator Calibration Control Register 0x10 -1 read-write n 0x0 0x0 CALTRG0 Comparator0 Calibration Trigger Bit Note 1: Before this bit is enabled,ACMPEN(ACMP_CTL0[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance. Note 2: Hardware will auto clear this bit when the next calibration is triggered by software. Note 3: If user must trigger calibration twice or more times, the second trigger has to wait at least 300us after the previous calibration is done. 0 1 read-write 0 Calibration is stopped #0 1 Calibration is triggered #1 CALTRG1 Comparator1 Calibration Trigger Bit Note 1: Before this bit is enabled, ACMPEN(ACMP_CTL1[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance. Note 2: Hardware will auto clear this bit when the next calibration is triggered by software. Note 3: If user must trigger calibration twice or more times, the second trigger has to wait at least 300us after the previous calibration is done. 1 1 read-write 0 Calibration is stopped #0 1 Calibration is triggered #1 ACMP_CALSR ACMP_CALSR Analog Comparator Calibration Status Register 0x14 -1 read-only n 0x0 0x0 CALNS0 Comparator0 Calibration Result Status for NMOS 1 1 read-only 0 Pass #0 1 Fail #1 CALNS1 Comparator1 Calibration Result Status for NMOS 5 1 read-only 0 Pass #0 1 Fail #1 CALPS0 Comparator0 Calibration Result Status for PMOS 2 1 read-only 0 Pass #0 1 Fail #1 CALPS1 Comparator1 Calibration Result Status for PMOS 6 1 read-only 0 Pass #0 1 Fail #1 DONE0 Comparator0 Calibration Done Status 0 1 read-only 0 Calibrating #0 1 Calibration done #1 DONE1 Comparator1 Calibration Done Status 4 1 read-only 0 Calibrating #0 1 Calibration done #1 ACMP_CTL0 ACMP_CTL0 Analog Comparator 0 Control Register 0x0 -1 read-write n 0x0 0x0 ACMPEN Comparator Enable Bit 0 1 read-write 0 Comparator 0 Disabled #0 1 Comparator 0 Enabled #1 ACMPIE Comparator Interrupt Enable Bit 1 1 read-write 0 Comparator 0 interrupt Disabled #0 1 Comparator 0 interrupt Enabled. If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well #1 ACMPOINV Comparator Output Inverse 3 1 read-write 0 Comparator 0 output inverse Disabled #0 1 Comparator 0 output inverse Enabled #1 FCLKDIV Comparator Output Filter Clock Divider 20 2 read-write 0 Comparator output filter clock = PCLK #00 1 Comparator output filter clock = PCLK/2 #01 2 Comparator output filter clock = PCLK/4 #10 3 Reserved. #11 FILTSEL Comparator Output Filter Count Selection 13 3 read-write 0 Filter function is Disabled #000 1 ACMP0 output is sampled 1 consecutive PCLK #001 2 ACMP0 output is sampled 2 consecutive PCLKs #010 3 ACMP0 output is sampled 4 consecutive PCLKs #011 4 ACMP0 output is sampled 8 consecutive PCLKs #100 5 ACMP0 output is sampled 16 consecutive PCLKs #101 6 ACMP0 output is sampled 32 consecutive PCLKs #110 7 ACMP0 output is sampled 64 consecutive PCLKs #111 HYSSEL Hysteresis Mode Selection 24 3 read-write 0 Hysteresis is 0mV #000 2 Hysteresis is 20mV #010 4 Hysteresis is 40mV #100 INTPOL Interrupt Condition Polarity Selection ACMPIF0 will be set to 1 when comparator output edge condition is detected. 8 2 read-write 0 Rising edge or falling edge #00 1 Rising edge #01 2 Falling edge #10 3 Reserved. #11 NEGSEL Comparator Negative Input Selection Note: NEGSEL must select 2'b01 in calibration mode. 4 2 read-write 0 ACMP0_N pin #00 1 Internal comparator reference voltage (CRV0) #01 2 Band-gap voltage #10 3 DAC0 output #11 OUTSEL Comparator Output Select 12 1 read-write 0 Comparator 0 output to ACMP0_O pin is unfiltered comparator output #0 1 Comparator 0 output to ACMP0_O pin is from filter output #1 POSSEL Comparator Positive Input Selection 6 2 read-write 0 Input from ACMP0_P0 #00 1 Input from ACMP0_P1 #01 2 Input from ACMP0_P2 #10 3 Input from ACMP0_P3 #11 WCMPSEL Window Compare Mode Selection 18 1 read-write 0 Window Compare Mode Disabled #0 1 Window Compare Mode is Selected #1 WKEN Power-down Wake-up Enable Bit 16 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 WLATEN Window Latch Mode Enable Bit 17 1 read-write 0 Window Latch Mode Disabled #0 1 Window Latch Mode Enabled #1 ACMP_CTL1 ACMP_CTL1 Analog Comparator 1 Control Register 0x4 -1 read-write n 0x0 0x0 ACMPEN Comparator Enable Bit 0 1 read-write 0 Comparator 1 Disabled #0 1 Comparator 1 Enabled #1 ACMPIE Comparator Interrupt Enable Bit 1 1 read-write 0 Comparator 1 interrupt Disabled #0 1 Comparator 1 interrupt Enabled. If WKEN (ACMP_CTL1[16]) is set to 1, the wake-up interrupt function will be enabled as well #1 ACMPOINV Comparator Output Inverse Control 3 1 read-write 0 Comparator 1 output inverse Disabled #0 1 Comparator 1 output inverse Enabled #1 FCLKDIV Comparator Output Filter Clock Divider 20 2 read-write 0 comparator output filter clock = PCLK #00 1 comparator output filter clock = PCLK/2 #01 2 comparator output filter clock = PCLK/4 #10 3 Reserved. #11 FILTSEL Comparator Output Filter Count Selection 13 3 read-write 0 Filter function is Disabled #000 1 ACMP1 output is sampled 1 consecutive PCLK #001 2 ACMP1 output is sampled 2 consecutive PCLKs #010 3 ACMP1 output is sampled 4 consecutive PCLKs #011 4 ACMP1 output is sampled 8 consecutive PCLKs #100 5 ACMP1 output is sampled 16 consecutive PCLKs #101 6 ACMP1 output is sampled 32 consecutive PCLKs #110 7 ACMP1 output is sampled 64 consecutive PCLKs #111 HYSSEL Hysteresis Mode Selection 24 3 read-write 0 Hysteresis is 0mV #000 2 Hysteresis is 20mV #010 4 Hysteresis is 40mV #100 INTPOL Interrupt Condition Polarity Selection ACMPIF1 will be set to 1 when comparator output edge condition is detected. 8 2 read-write 0 Rising edge or falling edge #00 1 Rising edge #01 2 Falling edge #10 3 Reserved. #11 NEGSEL Comparator Negative Input Selection Note: NEGSEL must select 2'b01 in calibration mode. 4 2 read-write 0 ACMP1_N pin #00 1 Internal comparator reference voltage (CRV1) #01 2 Band-gap voltage #10 3 DAC0 output #11 OUTSEL Comparator Output Select 12 1 read-write 0 Comparator 1 output to ACMP1_O pin is unfiltered comparator output #0 1 Comparator 1 output to ACMP1_O pin is from filter output #1 POSSEL Comparator Positive Input Selection 6 2 read-write 0 Input from ACMP1_P0 #00 1 Input from ACMP1_P1 #01 2 Input from ACMP1_P2 #10 3 Input from ACMP1_P3 #11 WCMPSEL Window Compare Mode Selection 18 1 read-write 0 Window Compare Mode Disabled #0 1 Window Compare Mode is Selected #1 WKEN Power-down Wakeup Enable Bit 16 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 WLATEN Window Latch Mode Enable Bit 17 1 read-write 0 Window Latch Mode Disabled #0 1 Window Latch Mode Enabled #1 ACMP_STATUS ACMP_STATUS Analog Comparator Status Register 0x8 -1 read-write n 0x0 0x0 ACMPIF0 Comparator 0 Interrupt Flag This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1. Note: Write 1 to clear this bit to 0. 0 1 read-write ACMPIF1 Comparator 1 Interrupt Flag This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output. This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1. Note: Write 1 to clear this bit to 0. 1 1 read-write ACMPO0 Comparator 0 Output Synchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0. 4 1 read-write ACMPO1 Comparator 1 Output Synchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0. 5 1 read-write ACMPS0 Comparator 0 Status Synchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0. 12 1 read-write ACMPS1 Comparator 1 Status Synchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0. 13 1 read-write ACMPWO Comparator Window Output This bit shows the output status of window compare mode 16 1 read-write 0 The positive input voltage is outside the window #0 1 The positive input voltage is in the window #1 WKIF0 Comparator 0 Power-down Wake-up Interrupt Flag This bit will be set to 1 when ACMP0 wake-up interrupt event occurs. Note: Write 1 to clear this bit to 0. 8 1 read-write 0 No power-down wake-up occurred #0 1 Power-down wake-up occurred #1 WKIF1 Comparator 1 Power-down Wake-up Interrupt Flag This bit will be set to 1 when ACMP1 wake-up interrupt event occurs. Note: Write 1 to clear this bit to 0. 9 1 read-write 0 No power-down wake-up occurred #0 1 Power-down wake-up occurred #1 ACMP_VREF ACMP_VREF Analog Comparator Reference Voltage Control Register 0xC -1 read-write n 0x0 0x0 CRV0EN CRV0 Enable Bit 8 1 read-write 0 CRV0 Disabled #0 1 CRV0 Enabled #1 CRV0SEL Comparator0 Reference Voltage Setting 0 6 read-write CRV0SSEL CRV0 Source Voltage Selection 6 1 read-write 0 AVDD is selected as CRV0 source voltage #0 1 The reference voltage defined by SYS_VREFCTL register is selected as CRV0 source voltage #1 CRV1EN CRV1 Enable Bit 24 1 read-write 0 CRV1 Disabled #0 1 CRV1 Enabled #1 CRV1SEL Comparator1 Reference Voltage Setting 16 6 read-write CRV1SSEL CRV1 Source Voltage Selection 22 1 read-write 0 AVDD is selected as CRV1 source voltage #0 1 The reference voltage defined by SYS_VREFCTL register is selected as CRV1 source voltage #1 BPWM0 BPWM Register Map BPWM 0x0 0x0 0x8 registers n 0x10 0x8 registers n 0x110 0x8 registers n 0x120 0x4 registers n 0x20 0x8 registers n 0x200 0x3C registers n 0x250 0x8 registers n 0x30 0x4 registers n 0x304 0x4 registers n 0x31C 0x18 registers n 0x50 0x18 registers n 0x90 0x4 registers n 0xB0 0x10 registers n 0xD4 0x8 registers n 0xE0 0x4 registers n 0xE8 0x4 registers n 0xF8 0x8 registers n BPWM_CAPCTL BPWM_CAPCTL BPWM Capture Control Register 0x204 -1 read-write n 0x0 0x0 CAPEN0 Capture Function Enable Bits Each bit n controls the corresponding BPWM channel n. 0 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN1 Capture Function Enable Bits Each bit n controls the corresponding BPWM channel n. 1 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN2 Capture Function Enable Bits Each bit n controls the corresponding BPWM channel n. 2 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN3 Capture Function Enable Bits Each bit n controls the corresponding BPWM channel n. 3 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN4 Capture Function Enable Bits Each bit n controls the corresponding BPWM channel n. 4 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN5 Capture Function Enable Bits Each bit n controls the corresponding BPWM channel n. 5 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPINV0 Capture Inverter Enable Bits Each bit n controls the corresponding BPWM channel n. 8 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV1 Capture Inverter Enable Bits Each bit n controls the corresponding BPWM channel n. 9 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV2 Capture Inverter Enable Bits Each bit n controls the corresponding BPWM channel n. 10 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV3 Capture Inverter Enable Bits Each bit n controls the corresponding BPWM channel n. 11 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV4 Capture Inverter Enable Bits Each bit n controls the corresponding BPWM channel n. 12 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV5 Capture Inverter Enable Bits Each bit n controls the corresponding BPWM channel n. 13 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 FCRLDEN0 Falling Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 24 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN1 Falling Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 25 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN2 Falling Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 26 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN3 Falling Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 27 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN4 Falling Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 28 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN5 Falling Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 29 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 RCRLDEN0 Rising Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 16 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN1 Rising Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 17 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN2 Rising Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 18 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN3 Rising Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 19 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN4 Rising Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 20 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN5 Rising Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 21 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 BPWM_CAPIEN BPWM_CAPIEN BPWM Capture Interrupt Enable Register 0x250 -1 read-write n 0x0 0x0 CAPFIENn BPWM Capture Falling Latch Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 8 6 read-write 0 Capture falling edge latch interrupt Disabled 0 1 Capture falling edge latch interrupt Enabled 1 CAPRIENn BPWM Capture Rising Latch Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 0 6 read-write 0 Capture rising edge latch interrupt Disabled 0 1 Capture rising edge latch interrupt Enabled 1 BPWM_CAPIF BPWM_CAPIF BPWM Capture Interrupt Flag Register 0x254 -1 read-write n 0x0 0x0 CAPFIF0 BPWM Capture Falling Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 8 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF1 BPWM Capture Falling Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 9 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF2 BPWM Capture Falling Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 10 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF3 BPWM Capture Falling Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 11 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF4 BPWM Capture Falling Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 12 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF5 BPWM Capture Falling Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 13 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPRIF0 BPWM Capture Rising Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 0 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF1 BPWM Capture Rising Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF2 BPWM Capture Rising Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 2 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF3 BPWM Capture Rising Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 3 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF4 BPWM Capture Rising Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 4 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF5 BPWM Capture Rising Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 5 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 BPWM_CAPINEN BPWM_CAPINEN BPWM Capture Input Enable Register 0x200 -1 read-write n 0x0 0x0 CAPINEN0 Capture Input Enable Bits Each bit n controls the corresponding BPWM channel n. 0 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN1 Capture Input Enable Bits Each bit n controls the corresponding BPWM channel n. 1 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN2 Capture Input Enable Bits Each bit n controls the corresponding BPWM channel n. 2 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN3 Capture Input Enable Bits Each bit n controls the corresponding BPWM channel n. 3 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN4 Capture Input Enable Bits Each bit n controls the corresponding BPWM channel n. 4 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN5 Capture Input Enable Bits Each bit n controls the corresponding BPWM channel n. 5 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 BPWM_CAPSTS BPWM_CAPSTS BPWM Capture Status Register 0x208 -1 read-only n 0x0 0x0 CFIFOV0 Capture Falling Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPFIF. 8 1 read-only CFIFOV1 Capture Falling Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPFIF. 9 1 read-only CFIFOV2 Capture Falling Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPFIF. 10 1 read-only CFIFOV3 Capture Falling Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPFIF. 11 1 read-only CFIFOV4 Capture Falling Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPFIF. 12 1 read-only CFIFOV5 Capture Falling Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPFIF. 13 1 read-only CRIFOV0 Capture Rising Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPRIF. 0 1 read-only CRIFOV1 Capture Rising Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPRIF. 1 1 read-only CRIFOV2 Capture Rising Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPRIF. 2 1 read-only CRIFOV3 Capture Rising Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPRIF. 3 1 read-only CRIFOV4 Capture Rising Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPRIF. 4 1 read-only CRIFOV5 Capture Rising Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPRIF. 5 1 read-only BPWM_CLKPSC BPWM_CLKPSC BPWM Clock Prescale Register 0x14 -1 read-write n 0x0 0x0 CLKPSC BPWM Counter Clock Prescale The clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1). 0 12 read-write BPWM_CLKSRC BPWM_CLKSRC BPWM Clock Source Register 0x10 -1 read-write n 0x0 0x0 ECLKSRC0 BPWM_CH01 External Clock Source Select 0 3 read-write 0 BPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 BPWM_CMPBUF0 BPWM_CMPBUF0 BPWM CMPDAT 0 Buffer 0x31C -1 read-only n 0x0 0x0 CMPBUF BPWM Comparator Buffer (Read Only) Used as CMP active register. 0 16 read-only BPWM_CMPBUF1 BPWM_CMPBUF1 BPWM CMPDAT 1 Buffer 0x320 -1 read-write n 0x0 0x0 BPWM_CMPBUF2 BPWM_CMPBUF2 BPWM CMPDAT 2 Buffer 0x324 -1 read-write n 0x0 0x0 BPWM_CMPBUF3 BPWM_CMPBUF3 BPWM CMPDAT 3 Buffer 0x328 -1 read-write n 0x0 0x0 BPWM_CMPBUF4 BPWM_CMPBUF4 BPWM CMPDAT 4 Buffer 0x32C -1 read-write n 0x0 0x0 BPWM_CMPBUF5 BPWM_CMPBUF5 BPWM CMPDAT 5 Buffer 0x330 -1 read-write n 0x0 0x0 BPWM_CMPDAT0 BPWM_CMPDAT0 BPWM Comparator Register 0 0x50 -1 read-write n 0x0 0x0 CMPDAT BPWM Comparator Register CMPDAT use to compare with CNT to generate BPWM waveform, interrupt and trigger EADC0. In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. 0 16 read-write BPWM_CMPDAT1 BPWM_CMPDAT1 BPWM Comparator Register 1 0x54 -1 read-write n 0x0 0x0 BPWM_CMPDAT2 BPWM_CMPDAT2 BPWM Comparator Register 2 0x58 -1 read-write n 0x0 0x0 BPWM_CMPDAT3 BPWM_CMPDAT3 BPWM Comparator Register 3 0x5C -1 read-write n 0x0 0x0 BPWM_CMPDAT4 BPWM_CMPDAT4 BPWM Comparator Register 4 0x60 -1 read-write n 0x0 0x0 BPWM_CMPDAT5 BPWM_CMPDAT5 BPWM Comparator Register 5 0x64 -1 read-write n 0x0 0x0 BPWM_CNT BPWM_CNT BPWM Counter Register 0x90 -1 read-only n 0x0 0x0 CNT BPWM Data Register (Read Only) User can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF BPWM Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 BPWM_CNTCLR BPWM_CNTCLR BPWM Clear Counter Register 0x24 -1 read-write n 0x0 0x0 CNTCLR0 Clear BPWM Counter Control Bit 0 It is automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Clear 16-bit BPWM counter to 0000H #1 BPWM_CNTEN BPWM_CNTEN BPWM Counter Enable Register 0x20 -1 read-write n 0x0 0x0 CNTEN0 BPWM Counter 0 Enable Bit 0 1 read-write 0 BPWM Counter and clock prescaler stop running #0 1 BPWM Counter and clock prescaler start running #1 BPWM_CTL0 BPWM_CTL0 BPWM Control Register 0 0x0 -1 read-write n 0x0 0x0 CTRLD0 Center Re-load Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 1 read-write CTRLD1 Center Re-load Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 1 1 read-write CTRLD2 Center Re-load Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 2 1 read-write CTRLD3 Center Re-load Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 3 1 read-write CTRLD4 Center Re-load Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 4 1 read-write CTRLD5 Center Re-load Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 5 1 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect) If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. Note: This bit is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect) BPWM pin will keep output no matter ICE debug mode acknowledged or not. Note: This bit is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects BPWM output #0 1 ICE debug mode acknowledgement Disabled #1 IMMLDEN0 Immediately Load Enable Bit(S) Each bit n controls the corresponding BPWM channel n. Note: If IMMLDENn is Enabled, CTRLDn will be invalid. 16 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN1 Immediately Load Enable Bit(S) Each bit n controls the corresponding BPWM channel n. Note: If IMMLDENn is Enabled, CTRLDn will be invalid. 17 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN2 Immediately Load Enable Bit(S) Each bit n controls the corresponding BPWM channel n. Note: If IMMLDENn is Enabled, CTRLDn will be invalid. 18 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN3 Immediately Load Enable Bit(S) Each bit n controls the corresponding BPWM channel n. Note: If IMMLDENn is Enabled, CTRLDn will be invalid. 19 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN4 Immediately Load Enable Bit(S) Each bit n controls the corresponding BPWM channel n. Note: If IMMLDENn is Enabled, CTRLDn will be invalid. 20 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN5 Immediately Load Enable Bit(S) Each bit n controls the corresponding BPWM channel n. Note: If IMMLDENn is Enabled, CTRLDn will be invalid. 21 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 BPWM_CTL1 BPWM_CTL1 BPWM Control Register 1 0x4 -1 read-write n 0x0 0x0 CNTTYPE0 BPWM Counter Behavior Type 0 Each bit n controls corresponding BPWM channel n. 0 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 BPWM_EADCTS0 BPWM_EADCTS0 BPWM Trigger EADC0 Source Select Register 0 0xF8 -1 read-write n 0x0 0x0 TRGEN0 BPWM_CH0 Trigger EADC0 Enable Bit 7 1 read-write TRGEN1 BPWM_CH1 Trigger EADC0 Enable Bit 15 1 read-write TRGEN2 BPWM_CH2 Trigger EADC0 Enable Bit 23 1 read-write TRGEN3 BPWM_CH3 Trigger EADC0 Enable Bit 31 1 read-write TRGSEL0 BPWM_CH0 Trigger EADC0 Source Select Others reserved 0 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count CMPDAT point #0011 4 BPWM_CH0 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 BPWM_CH1 up-count CMPDAT point #1000 9 BPWM_CH1 down-count CMPDAT point #1001 TRGSEL1 BPWM_CH1 Trigger EADC0 Source Select Others reserved 8 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count CMPDAT point #0011 4 BPWM_CH0 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 BPWM_CH1 up-count CMPDAT point #1000 9 BPWM_CH1 down-count CMPDAT point #1001 TRGSEL2 BPWM_CH2 Trigger EADC0 Source Select Others reserved 16 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count CMPDAT point #0011 4 BPWM_CH2 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 BPWM_CH3 up-count CMPDAT point #1000 9 BPWM_CH3 down-count CMPDAT point #1001 TRGSEL3 BPWM_CH3 Trigger EADC0 Source Select Others reserved. 24 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count CMPDAT point #0011 4 BPWM_CH2 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 BPWM_CH3 up-count CMPDAT point #1000 9 BPWM_CH3 down-count CMPDAT point #1001 BPWM_EADCTS1 BPWM_EADCTS1 BPWM Trigger EADC0 Source Select Register 1 0xFC -1 read-write n 0x0 0x0 TRGEN4 BPWM_CH4 Trigger EADC0 Enable Bit 7 1 read-write TRGEN5 BPWM_CH5 Trigger EADC0 Enable Bit 15 1 read-write TRGSEL4 BPWM_CH4 Trigger EADC0 Source Select Others reserved 0 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count CMPDAT point #0011 4 BPWM_CH4 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 BPWM_CH5 up-count CMPDAT point #1000 9 BPWM_CH5 down-count CMPDAT point #1001 TRGSEL5 BPWM_CH5 Trigger EADC0 Source Select Others reserved 8 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count CMPDAT point #0011 4 BPWM_CH4 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 BPWM_CH5 up-count CMPDAT point #1000 9 BPWM_CH5 down-count CMPDAT point #1001 BPWM_FCAPDAT0 BPWM_FCAPDAT0 BPWM Falling Capture Data Register 0 0x210 -1 read-only n 0x0 0x0 FCAPDAT BPWM Falling Capture Data (Read Only) When falling capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_FCAPDAT1 BPWM_FCAPDAT1 BPWM Falling Capture Data Register 1 0x218 -1 read-write n 0x0 0x0 BPWM_FCAPDAT2 BPWM_FCAPDAT2 BPWM Falling Capture Data Register 2 0x220 -1 read-write n 0x0 0x0 BPWM_FCAPDAT3 BPWM_FCAPDAT3 BPWM Falling Capture Data Register 3 0x228 -1 read-write n 0x0 0x0 BPWM_FCAPDAT4 BPWM_FCAPDAT4 BPWM Falling Capture Data Register 4 0x230 -1 read-write n 0x0 0x0 BPWM_FCAPDAT5 BPWM_FCAPDAT5 BPWM Falling Capture Data Register 5 0x238 -1 read-write n 0x0 0x0 BPWM_INTEN BPWM_INTEN BPWM Interrupt Enable Register 0xE0 -1 read-write n 0x0 0x0 CMPDIEN0 BPWM Compare Down Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 24 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN1 BPWM Compare Down Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 25 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN2 BPWM Compare Down Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 26 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN3 BPWM Compare Down Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 27 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN4 BPWM Compare Down Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 28 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN5 BPWM Compare Down Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 29 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPUIEN0 BPWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 16 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN1 BPWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 17 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN2 BPWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 18 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN3 BPWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 19 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN4 BPWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 20 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN5 BPWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 21 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 PIEN0 BPWM Period Point Interrupt 0 Enable Bit Note: When up-down counter type period point means center point. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 BPWM Zero Point Interrupt 0 Enable Bit 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 BPWM_INTSTS BPWM_INTSTS BPWM Interrupt Flag Register 0xE8 -1 read-write n 0x0 0x0 CMPDIF0 BPWM Compare Down Count Interrupt Flag Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 24 1 read-write CMPDIF1 BPWM Compare Down Count Interrupt Flag Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 25 1 read-write CMPDIF2 BPWM Compare Down Count Interrupt Flag Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 26 1 read-write CMPDIF3 BPWM Compare Down Count Interrupt Flag Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 27 1 read-write CMPDIF4 BPWM Compare Down Count Interrupt Flag Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 28 1 read-write CMPDIF5 BPWM Compare Down Count Interrupt Flag Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 29 1 read-write CMPUIF0 BPWM Compare Up Count Interrupt Flag Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 16 1 read-write CMPUIF1 BPWM Compare Up Count Interrupt Flag Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 17 1 read-write CMPUIF2 BPWM Compare Up Count Interrupt Flag Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 18 1 read-write CMPUIF3 BPWM Compare Up Count Interrupt Flag Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 19 1 read-write CMPUIF4 BPWM Compare Up Count Interrupt Flag Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 20 1 read-write CMPUIF5 BPWM Compare Up Count Interrupt Flag Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 21 1 read-write PIF0 BPWM Period Point Interrupt Flag 0 This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to 0. 8 1 read-write ZIF0 BPWM Zero Point Interrupt Flag 0 This bit is set by hardware when BPWM_CH0 counter reaches 0, software can write 1 to clear this bit to 0. 0 1 read-write BPWM_MSK BPWM_MSK BPWM Mask Data Register 0xBC -1 read-write n 0x0 0x0 MSKDAT0 BPWM Mask Data Bit This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 0 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT1 BPWM Mask Data Bit This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 1 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT2 BPWM Mask Data Bit This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 2 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT3 BPWM Mask Data Bit This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 3 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT4 BPWM Mask Data Bit This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 4 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT5 BPWM Mask Data Bit This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 5 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 BPWM_MSKEN BPWM_MSKEN BPWM Mask Enable Register 0xB8 -1 read-write n 0x0 0x0 MSKEN0 BPWM Mask Enable Bits Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 0 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN1 BPWM Mask Enable Bits Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 1 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN2 BPWM Mask Enable Bits Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 2 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN3 BPWM Mask Enable Bits Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 3 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN4 BPWM Mask Enable Bits Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 4 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN5 BPWM Mask Enable Bits Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 5 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 BPWM_PBUF BPWM_PBUF BPWM PERIOD Buffer 0x304 -1 read-only n 0x0 0x0 PBUF BPWM Period Buffer (Read Only) Used as PERIOD active register. 0 16 read-only BPWM_PERIOD BPWM_PERIOD BPWM Period Register 0x30 -1 read-write n 0x0 0x0 PERIOD BPWM Period Register Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0. Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD. 0 16 read-write BPWM_POEN BPWM_POEN BPWM Output Enable Register 0xD8 -1 read-write n 0x0 0x0 POEN0 BPWM Pin Output Enable Bits Each bit n controls the corresponding BPWM channel n. 0 1 read-write 0 BPWM pin at tri-state #0 1 BPWM pin in output mode #1 POEN1 BPWM Pin Output Enable Bits Each bit n controls the corresponding BPWM channel n. 1 1 read-write 0 BPWM pin at tri-state #0 1 BPWM pin in output mode #1 POEN2 BPWM Pin Output Enable Bits Each bit n controls the corresponding BPWM channel n. 2 1 read-write 0 BPWM pin at tri-state #0 1 BPWM pin in output mode #1 POEN3 BPWM Pin Output Enable Bits Each bit n controls the corresponding BPWM channel n. 3 1 read-write 0 BPWM pin at tri-state #0 1 BPWM pin in output mode #1 POEN4 BPWM Pin Output Enable Bits Each bit n controls the corresponding BPWM channel n. 4 1 read-write 0 BPWM pin at tri-state #0 1 BPWM pin in output mode #1 POEN5 BPWM Pin Output Enable Bits Each bit n controls the corresponding BPWM channel n. 5 1 read-write 0 BPWM pin at tri-state #0 1 BPWM pin in output mode #1 BPWM_POLCTL BPWM_POLCTL BPWM Pin Polar Inverse Register 0xD4 -1 read-write n 0x0 0x0 PINV0 BPWM PIN Polar Inverse Control The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n. 0 1 read-write 0 BPWM output polar inverse Disabled #0 1 BPWM output polar inverse Enabled #1 PINV1 BPWM PIN Polar Inverse Control The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n. 1 1 read-write 0 BPWM output polar inverse Disabled #0 1 BPWM output polar inverse Enabled #1 PINV2 BPWM PIN Polar Inverse Control The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n. 2 1 read-write 0 BPWM output polar inverse Disabled #0 1 BPWM output polar inverse Enabled #1 PINV3 BPWM PIN Polar Inverse Control The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n. 3 1 read-write 0 BPWM output polar inverse Disabled #0 1 BPWM output polar inverse Enabled #1 PINV4 BPWM PIN Polar Inverse Control The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n. 4 1 read-write 0 BPWM output polar inverse Disabled #0 1 BPWM output polar inverse Enabled #1 PINV5 BPWM PIN Polar Inverse Control The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n. 5 1 read-write 0 BPWM output polar inverse Disabled #0 1 BPWM output polar inverse Enabled #1 BPWM_RCAPDAT0 BPWM_RCAPDAT0 BPWM Rising Capture Data Register 0 0x20C -1 read-only n 0x0 0x0 RCAPDAT BPWM Rising Capture Data (Read Only) When rising capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_RCAPDAT1 BPWM_RCAPDAT1 BPWM Rising Capture Data Register 1 0x214 -1 read-write n 0x0 0x0 BPWM_RCAPDAT2 BPWM_RCAPDAT2 BPWM Rising Capture Data Register 2 0x21C -1 read-write n 0x0 0x0 BPWM_RCAPDAT3 BPWM_RCAPDAT3 BPWM Rising Capture Data Register 3 0x224 -1 read-write n 0x0 0x0 BPWM_RCAPDAT4 BPWM_RCAPDAT4 BPWM Rising Capture Data Register 4 0x22C -1 read-write n 0x0 0x0 BPWM_RCAPDAT5 BPWM_RCAPDAT5 BPWM Rising Capture Data Register 5 0x234 -1 read-write n 0x0 0x0 BPWM_SSCTL BPWM_SSCTL BPWM Synchronous Start Control Register 0x110 -1 read-write n 0x0 0x0 SSEN0 BPWM Synchronous Start Function 0 Enable Bit When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). 0 1 read-write 0 BPWM synchronous start function Disabled #0 1 BPWM synchronous start function Enabled #1 SSRC BPWM Synchronous Start Source Select 8 2 read-write 0 Synchronous start source come from PWM0 #00 1 Synchronous start source come from PWM1 #01 2 Synchronous start source come from BPWM0 #10 3 Synchronous start source come from BPWM1 #11 BPWM_SSTRG BPWM_SSTRG BPWM Synchronous Start Trigger Register 0x114 -1 write-only n 0x0 0x0 CNTSEN BPWM Counter Synchronous Start Enable Bit(Write Only) BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time. Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled. 0 1 write-only BPWM_STATUS BPWM_STATUS BPWM Status Register 0x120 -1 read-write n 0x0 0x0 CNTMAXF0 Time-base Counter 0 Equal to 0xFFFF Latched Flag 0 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value. Software can write 1 to clear this bit #1 EADCTRG0 EADC0 Start of Conversion Status Each bit n controls the corresponding BPWM channel n. 16 1 read-write 0 No EADC0 start of conversion trigger event has occurred #0 1 An EADC0 start of conversion trigger event has occurred. Software can write 1 to clear this bit #1 EADCTRG1 EADC0 Start of Conversion Status Each bit n controls the corresponding BPWM channel n. 17 1 read-write 0 No EADC0 start of conversion trigger event has occurred #0 1 An EADC0 start of conversion trigger event has occurred. Software can write 1 to clear this bit #1 EADCTRG2 EADC0 Start of Conversion Status Each bit n controls the corresponding BPWM channel n. 18 1 read-write 0 No EADC0 start of conversion trigger event has occurred #0 1 An EADC0 start of conversion trigger event has occurred. Software can write 1 to clear this bit #1 EADCTRG3 EADC0 Start of Conversion Status Each bit n controls the corresponding BPWM channel n. 19 1 read-write 0 No EADC0 start of conversion trigger event has occurred #0 1 An EADC0 start of conversion trigger event has occurred. Software can write 1 to clear this bit #1 EADCTRG4 EADC0 Start of Conversion Status Each bit n controls the corresponding BPWM channel n. 20 1 read-write 0 No EADC0 start of conversion trigger event has occurred #0 1 An EADC0 start of conversion trigger event has occurred. Software can write 1 to clear this bit #1 EADCTRG5 EADC0 Start of Conversion Status Each bit n controls the corresponding BPWM channel n. 21 1 read-write 0 No EADC0 start of conversion trigger event has occurred #0 1 An EADC0 start of conversion trigger event has occurred. Software can write 1 to clear this bit #1 BPWM_WGCTL0 BPWM_WGCTL0 BPWM Generation Register 0 0xB0 -1 read-write n 0x0 0x0 PRDPCTL0 BPWM Period (Center) Point Control Each bit n controls the corresponding BPWM channel n. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. 16 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL1 BPWM Period (Center) Point Control Each bit n controls the corresponding BPWM channel n. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. 18 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL2 BPWM Period (Center) Point Control Each bit n controls the corresponding BPWM channel n. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. 20 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL3 BPWM Period (Center) Point Control Each bit n controls the corresponding BPWM channel n. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. 22 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL4 BPWM Period (Center) Point Control Each bit n controls the corresponding BPWM channel n. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. 24 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL5 BPWM Period (Center) Point Control Each bit n controls the corresponding BPWM channel n. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. 26 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 ZPCTL0 BPWM Zero Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter counts to 0. 0 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL1 BPWM Zero Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter counts to 0. 2 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL2 BPWM Zero Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter counts to 0. 4 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL3 BPWM Zero Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter counts to 0. 6 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL4 BPWM Zero Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter counts to 0. 8 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL5 BPWM Zero Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter counts to 0. 10 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 BPWM_WGCTL1 BPWM_WGCTL1 BPWM Generation Register 1 0xB4 -1 read-write n 0x0 0x0 CMPDCTL0 BPWM Compare Down Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter down counts to CMPDAT. 16 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL1 BPWM Compare Down Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter down counts to CMPDAT. 18 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL2 BPWM Compare Down Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter down counts to CMPDAT. 20 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL3 BPWM Compare Down Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter down counts to CMPDAT. 22 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL4 BPWM Compare Down Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter down counts to CMPDAT. 24 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL5 BPWM Compare Down Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter down counts to CMPDAT. 26 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPUCTL0 BPWM Compare Up Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter up counts to CMPDAT. 0 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL1 BPWM Compare Up Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter up counts to CMPDAT. 2 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL2 BPWM Compare Up Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter up counts to CMPDAT. 4 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL3 BPWM Compare Up Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter up counts to CMPDAT. 6 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL4 BPWM Compare Up Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter up counts to CMPDAT. 8 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL5 BPWM Compare Up Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter up counts to CMPDAT. 10 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 BPWM1 BPWM Register Map BPWM 0x0 0x0 0x8 registers n 0x10 0x8 registers n 0x110 0x8 registers n 0x120 0x4 registers n 0x20 0x8 registers n 0x200 0x3C registers n 0x250 0x8 registers n 0x30 0x4 registers n 0x304 0x4 registers n 0x31C 0x18 registers n 0x50 0x18 registers n 0x90 0x4 registers n 0xB0 0x10 registers n 0xD4 0x8 registers n 0xE0 0x4 registers n 0xE8 0x4 registers n 0xF8 0x8 registers n BPWM_CAPCTL BPWM_CAPCTL BPWM Capture Control Register 0x204 -1 read-write n 0x0 0x0 CAPEN0 Capture Function Enable Bits Each bit n controls the corresponding BPWM channel n. 0 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN1 Capture Function Enable Bits Each bit n controls the corresponding BPWM channel n. 1 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN2 Capture Function Enable Bits Each bit n controls the corresponding BPWM channel n. 2 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN3 Capture Function Enable Bits Each bit n controls the corresponding BPWM channel n. 3 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN4 Capture Function Enable Bits Each bit n controls the corresponding BPWM channel n. 4 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN5 Capture Function Enable Bits Each bit n controls the corresponding BPWM channel n. 5 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated #0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPINV0 Capture Inverter Enable Bits Each bit n controls the corresponding BPWM channel n. 8 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV1 Capture Inverter Enable Bits Each bit n controls the corresponding BPWM channel n. 9 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV2 Capture Inverter Enable Bits Each bit n controls the corresponding BPWM channel n. 10 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV3 Capture Inverter Enable Bits Each bit n controls the corresponding BPWM channel n. 11 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV4 Capture Inverter Enable Bits Each bit n controls the corresponding BPWM channel n. 12 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV5 Capture Inverter Enable Bits Each bit n controls the corresponding BPWM channel n. 13 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 FCRLDEN0 Falling Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 24 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN1 Falling Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 25 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN2 Falling Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 26 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN3 Falling Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 27 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN4 Falling Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 28 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN5 Falling Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 29 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 RCRLDEN0 Rising Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 16 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN1 Rising Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 17 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN2 Rising Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 18 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN3 Rising Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 19 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN4 Rising Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 20 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN5 Rising Capture Reload Enable Bits Each bit n controls the corresponding BPWM channel n. 21 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 BPWM_CAPIEN BPWM_CAPIEN BPWM Capture Interrupt Enable Register 0x250 -1 read-write n 0x0 0x0 CAPFIENn BPWM Capture Falling Latch Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 8 6 read-write 0 Capture falling edge latch interrupt Disabled 0 1 Capture falling edge latch interrupt Enabled 1 CAPRIENn BPWM Capture Rising Latch Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 0 6 read-write 0 Capture rising edge latch interrupt Disabled 0 1 Capture rising edge latch interrupt Enabled 1 BPWM_CAPIF BPWM_CAPIF BPWM Capture Interrupt Flag Register 0x254 -1 read-write n 0x0 0x0 CAPFIF0 BPWM Capture Falling Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 8 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF1 BPWM Capture Falling Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 9 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF2 BPWM Capture Falling Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 10 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF3 BPWM Capture Falling Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 11 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF4 BPWM Capture Falling Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 12 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPFIF5 BPWM Capture Falling Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 13 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CAPRIF0 BPWM Capture Rising Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 0 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF1 BPWM Capture Rising Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF2 BPWM Capture Rising Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 2 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF3 BPWM Capture Rising Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 3 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF4 BPWM Capture Rising Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 4 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CAPRIF5 BPWM Capture Rising Latch Interrupt Flag Each bit n controls the corresponding BPWM channel n. Note: This bit is cleared by writing 1 to it. 5 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 BPWM_CAPINEN BPWM_CAPINEN BPWM Capture Input Enable Register 0x200 -1 read-write n 0x0 0x0 CAPINEN0 Capture Input Enable Bits Each bit n controls the corresponding BPWM channel n. 0 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN1 Capture Input Enable Bits Each bit n controls the corresponding BPWM channel n. 1 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN2 Capture Input Enable Bits Each bit n controls the corresponding BPWM channel n. 2 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN3 Capture Input Enable Bits Each bit n controls the corresponding BPWM channel n. 3 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN4 Capture Input Enable Bits Each bit n controls the corresponding BPWM channel n. 4 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 CAPINEN5 Capture Input Enable Bits Each bit n controls the corresponding BPWM channel n. 5 1 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 #0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin #1 BPWM_CAPSTS BPWM_CAPSTS BPWM Capture Status Register 0x208 -1 read-only n 0x0 0x0 CFIFOV0 Capture Falling Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPFIF. 8 1 read-only CFIFOV1 Capture Falling Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPFIF. 9 1 read-only CFIFOV2 Capture Falling Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPFIF. 10 1 read-only CFIFOV3 Capture Falling Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPFIF. 11 1 read-only CFIFOV4 Capture Falling Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPFIF. 12 1 read-only CFIFOV5 Capture Falling Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPFIF. 13 1 read-only CRIFOV0 Capture Rising Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPRIF. 0 1 read-only CRIFOV1 Capture Rising Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPRIF. 1 1 read-only CRIFOV2 Capture Rising Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPRIF. 2 1 read-only CRIFOV3 Capture Rising Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPRIF. 3 1 read-only CRIFOV4 Capture Rising Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPRIF. 4 1 read-only CRIFOV5 Capture Rising Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clears corresponding CAPRIF. 5 1 read-only BPWM_CLKPSC BPWM_CLKPSC BPWM Clock Prescale Register 0x14 -1 read-write n 0x0 0x0 CLKPSC BPWM Counter Clock Prescale The clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1). 0 12 read-write BPWM_CLKSRC BPWM_CLKSRC BPWM Clock Source Register 0x10 -1 read-write n 0x0 0x0 ECLKSRC0 BPWM_CH01 External Clock Source Select 0 3 read-write 0 BPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 BPWM_CMPBUF0 BPWM_CMPBUF0 BPWM CMPDAT 0 Buffer 0x31C -1 read-only n 0x0 0x0 CMPBUF BPWM Comparator Buffer (Read Only) Used as CMP active register. 0 16 read-only BPWM_CMPBUF1 BPWM_CMPBUF1 BPWM CMPDAT 1 Buffer 0x320 -1 read-write n 0x0 0x0 BPWM_CMPBUF2 BPWM_CMPBUF2 BPWM CMPDAT 2 Buffer 0x324 -1 read-write n 0x0 0x0 BPWM_CMPBUF3 BPWM_CMPBUF3 BPWM CMPDAT 3 Buffer 0x328 -1 read-write n 0x0 0x0 BPWM_CMPBUF4 BPWM_CMPBUF4 BPWM CMPDAT 4 Buffer 0x32C -1 read-write n 0x0 0x0 BPWM_CMPBUF5 BPWM_CMPBUF5 BPWM CMPDAT 5 Buffer 0x330 -1 read-write n 0x0 0x0 BPWM_CMPDAT0 BPWM_CMPDAT0 BPWM Comparator Register 0 0x50 -1 read-write n 0x0 0x0 CMPDAT BPWM Comparator Register CMPDAT use to compare with CNT to generate BPWM waveform, interrupt and trigger EADC0. In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. 0 16 read-write BPWM_CMPDAT1 BPWM_CMPDAT1 BPWM Comparator Register 1 0x54 -1 read-write n 0x0 0x0 BPWM_CMPDAT2 BPWM_CMPDAT2 BPWM Comparator Register 2 0x58 -1 read-write n 0x0 0x0 BPWM_CMPDAT3 BPWM_CMPDAT3 BPWM Comparator Register 3 0x5C -1 read-write n 0x0 0x0 BPWM_CMPDAT4 BPWM_CMPDAT4 BPWM Comparator Register 4 0x60 -1 read-write n 0x0 0x0 BPWM_CMPDAT5 BPWM_CMPDAT5 BPWM Comparator Register 5 0x64 -1 read-write n 0x0 0x0 BPWM_CNT BPWM_CNT BPWM Counter Register 0x90 -1 read-only n 0x0 0x0 CNT BPWM Data Register (Read Only) User can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF BPWM Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 BPWM_CNTCLR BPWM_CNTCLR BPWM Clear Counter Register 0x24 -1 read-write n 0x0 0x0 CNTCLR0 Clear BPWM Counter Control Bit 0 It is automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Clear 16-bit BPWM counter to 0000H #1 BPWM_CNTEN BPWM_CNTEN BPWM Counter Enable Register 0x20 -1 read-write n 0x0 0x0 CNTEN0 BPWM Counter 0 Enable Bit 0 1 read-write 0 BPWM Counter and clock prescaler stop running #0 1 BPWM Counter and clock prescaler start running #1 BPWM_CTL0 BPWM_CTL0 BPWM Control Register 0 0x0 -1 read-write n 0x0 0x0 CTRLD0 Center Re-load Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 1 read-write CTRLD1 Center Re-load Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 1 1 read-write CTRLD2 Center Re-load Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 2 1 read-write CTRLD3 Center Re-load Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 3 1 read-write CTRLD4 Center Re-load Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 4 1 read-write CTRLD5 Center Re-load Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 5 1 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect) If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. Note: This bit is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect) BPWM pin will keep output no matter ICE debug mode acknowledged or not. Note: This bit is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects BPWM output #0 1 ICE debug mode acknowledgement Disabled #1 IMMLDEN0 Immediately Load Enable Bit(S) Each bit n controls the corresponding BPWM channel n. Note: If IMMLDENn is Enabled, CTRLDn will be invalid. 16 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN1 Immediately Load Enable Bit(S) Each bit n controls the corresponding BPWM channel n. Note: If IMMLDENn is Enabled, CTRLDn will be invalid. 17 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN2 Immediately Load Enable Bit(S) Each bit n controls the corresponding BPWM channel n. Note: If IMMLDENn is Enabled, CTRLDn will be invalid. 18 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN3 Immediately Load Enable Bit(S) Each bit n controls the corresponding BPWM channel n. Note: If IMMLDENn is Enabled, CTRLDn will be invalid. 19 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN4 Immediately Load Enable Bit(S) Each bit n controls the corresponding BPWM channel n. Note: If IMMLDENn is Enabled, CTRLDn will be invalid. 20 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 IMMLDEN5 Immediately Load Enable Bit(S) Each bit n controls the corresponding BPWM channel n. Note: If IMMLDENn is Enabled, CTRLDn will be invalid. 21 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 BPWM_CTL1 BPWM_CTL1 BPWM Control Register 1 0x4 -1 read-write n 0x0 0x0 CNTTYPE0 BPWM Counter Behavior Type 0 Each bit n controls corresponding BPWM channel n. 0 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 BPWM_EADCTS0 BPWM_EADCTS0 BPWM Trigger EADC0 Source Select Register 0 0xF8 -1 read-write n 0x0 0x0 TRGEN0 BPWM_CH0 Trigger EADC0 Enable Bit 7 1 read-write TRGEN1 BPWM_CH1 Trigger EADC0 Enable Bit 15 1 read-write TRGEN2 BPWM_CH2 Trigger EADC0 Enable Bit 23 1 read-write TRGEN3 BPWM_CH3 Trigger EADC0 Enable Bit 31 1 read-write TRGSEL0 BPWM_CH0 Trigger EADC0 Source Select Others reserved 0 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count CMPDAT point #0011 4 BPWM_CH0 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 BPWM_CH1 up-count CMPDAT point #1000 9 BPWM_CH1 down-count CMPDAT point #1001 TRGSEL1 BPWM_CH1 Trigger EADC0 Source Select Others reserved 8 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count CMPDAT point #0011 4 BPWM_CH0 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 BPWM_CH1 up-count CMPDAT point #1000 9 BPWM_CH1 down-count CMPDAT point #1001 TRGSEL2 BPWM_CH2 Trigger EADC0 Source Select Others reserved 16 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count CMPDAT point #0011 4 BPWM_CH2 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 BPWM_CH3 up-count CMPDAT point #1000 9 BPWM_CH3 down-count CMPDAT point #1001 TRGSEL3 BPWM_CH3 Trigger EADC0 Source Select Others reserved. 24 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count CMPDAT point #0011 4 BPWM_CH2 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 BPWM_CH3 up-count CMPDAT point #1000 9 BPWM_CH3 down-count CMPDAT point #1001 BPWM_EADCTS1 BPWM_EADCTS1 BPWM Trigger EADC0 Source Select Register 1 0xFC -1 read-write n 0x0 0x0 TRGEN4 BPWM_CH4 Trigger EADC0 Enable Bit 7 1 read-write TRGEN5 BPWM_CH5 Trigger EADC0 Enable Bit 15 1 read-write TRGSEL4 BPWM_CH4 Trigger EADC0 Source Select Others reserved 0 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count CMPDAT point #0011 4 BPWM_CH4 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 BPWM_CH5 up-count CMPDAT point #1000 9 BPWM_CH5 down-count CMPDAT point #1001 TRGSEL5 BPWM_CH5 Trigger EADC0 Source Select Others reserved 8 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count CMPDAT point #0011 4 BPWM_CH4 down-count CMPDAT point #0100 5 Reserved. #0101 6 Reserved. #0110 7 Reserved. #0111 8 BPWM_CH5 up-count CMPDAT point #1000 9 BPWM_CH5 down-count CMPDAT point #1001 BPWM_FCAPDAT0 BPWM_FCAPDAT0 BPWM Falling Capture Data Register 0 0x210 -1 read-only n 0x0 0x0 FCAPDAT BPWM Falling Capture Data (Read Only) When falling capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_FCAPDAT1 BPWM_FCAPDAT1 BPWM Falling Capture Data Register 1 0x218 -1 read-write n 0x0 0x0 BPWM_FCAPDAT2 BPWM_FCAPDAT2 BPWM Falling Capture Data Register 2 0x220 -1 read-write n 0x0 0x0 BPWM_FCAPDAT3 BPWM_FCAPDAT3 BPWM Falling Capture Data Register 3 0x228 -1 read-write n 0x0 0x0 BPWM_FCAPDAT4 BPWM_FCAPDAT4 BPWM Falling Capture Data Register 4 0x230 -1 read-write n 0x0 0x0 BPWM_FCAPDAT5 BPWM_FCAPDAT5 BPWM Falling Capture Data Register 5 0x238 -1 read-write n 0x0 0x0 BPWM_INTEN BPWM_INTEN BPWM Interrupt Enable Register 0xE0 -1 read-write n 0x0 0x0 CMPDIEN0 BPWM Compare Down Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 24 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN1 BPWM Compare Down Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 25 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN2 BPWM Compare Down Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 26 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN3 BPWM Compare Down Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 27 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN4 BPWM Compare Down Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 28 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN5 BPWM Compare Down Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 29 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPUIEN0 BPWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 16 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN1 BPWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 17 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN2 BPWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 18 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN3 BPWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 19 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN4 BPWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 20 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN5 BPWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding BPWM channel n. 21 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 PIEN0 BPWM Period Point Interrupt 0 Enable Bit Note: When up-down counter type period point means center point. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 BPWM Zero Point Interrupt 0 Enable Bit 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 BPWM_INTSTS BPWM_INTSTS BPWM Interrupt Flag Register 0xE8 -1 read-write n 0x0 0x0 CMPDIF0 BPWM Compare Down Count Interrupt Flag Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 24 1 read-write CMPDIF1 BPWM Compare Down Count Interrupt Flag Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 25 1 read-write CMPDIF2 BPWM Compare Down Count Interrupt Flag Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 26 1 read-write CMPDIF3 BPWM Compare Down Count Interrupt Flag Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 27 1 read-write CMPDIF4 BPWM Compare Down Count Interrupt Flag Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 28 1 read-write CMPDIF5 BPWM Compare Down Count Interrupt Flag Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 29 1 read-write CMPUIF0 BPWM Compare Up Count Interrupt Flag Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 16 1 read-write CMPUIF1 BPWM Compare Up Count Interrupt Flag Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 17 1 read-write CMPUIF2 BPWM Compare Up Count Interrupt Flag Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 18 1 read-write CMPUIF3 BPWM Compare Up Count Interrupt Flag Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 19 1 read-write CMPUIF4 BPWM Compare Up Count Interrupt Flag Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 20 1 read-write CMPUIF5 BPWM Compare Up Count Interrupt Flag Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 21 1 read-write PIF0 BPWM Period Point Interrupt Flag 0 This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to 0. 8 1 read-write ZIF0 BPWM Zero Point Interrupt Flag 0 This bit is set by hardware when BPWM_CH0 counter reaches 0, software can write 1 to clear this bit to 0. 0 1 read-write BPWM_MSK BPWM_MSK BPWM Mask Data Register 0xBC -1 read-write n 0x0 0x0 MSKDAT0 BPWM Mask Data Bit This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 0 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT1 BPWM Mask Data Bit This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 1 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT2 BPWM Mask Data Bit This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 2 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT3 BPWM Mask Data Bit This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 3 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT4 BPWM Mask Data Bit This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 4 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 MSKDAT5 BPWM Mask Data Bit This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n. 5 1 read-write 0 Output logic low to BPWMn #0 1 Output logic high to BPWMn #1 BPWM_MSKEN BPWM_MSKEN BPWM Mask Enable Register 0xB8 -1 read-write n 0x0 0x0 MSKEN0 BPWM Mask Enable Bits Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 0 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN1 BPWM Mask Enable Bits Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 1 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN2 BPWM Mask Enable Bits Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 2 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN3 BPWM Mask Enable Bits Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 3 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN4 BPWM Mask Enable Bits Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 4 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 MSKEN5 BPWM Mask Enable Bits Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 5 1 read-write 0 BPWM output signal is non-masked #0 1 BPWM output signal is masked and output MSKDATn data #1 BPWM_PBUF BPWM_PBUF BPWM PERIOD Buffer 0x304 -1 read-only n 0x0 0x0 PBUF BPWM Period Buffer (Read Only) Used as PERIOD active register. 0 16 read-only BPWM_PERIOD BPWM_PERIOD BPWM Period Register 0x30 -1 read-write n 0x0 0x0 PERIOD BPWM Period Register Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0. Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD. 0 16 read-write BPWM_POEN BPWM_POEN BPWM Output Enable Register 0xD8 -1 read-write n 0x0 0x0 POEN0 BPWM Pin Output Enable Bits Each bit n controls the corresponding BPWM channel n. 0 1 read-write 0 BPWM pin at tri-state #0 1 BPWM pin in output mode #1 POEN1 BPWM Pin Output Enable Bits Each bit n controls the corresponding BPWM channel n. 1 1 read-write 0 BPWM pin at tri-state #0 1 BPWM pin in output mode #1 POEN2 BPWM Pin Output Enable Bits Each bit n controls the corresponding BPWM channel n. 2 1 read-write 0 BPWM pin at tri-state #0 1 BPWM pin in output mode #1 POEN3 BPWM Pin Output Enable Bits Each bit n controls the corresponding BPWM channel n. 3 1 read-write 0 BPWM pin at tri-state #0 1 BPWM pin in output mode #1 POEN4 BPWM Pin Output Enable Bits Each bit n controls the corresponding BPWM channel n. 4 1 read-write 0 BPWM pin at tri-state #0 1 BPWM pin in output mode #1 POEN5 BPWM Pin Output Enable Bits Each bit n controls the corresponding BPWM channel n. 5 1 read-write 0 BPWM pin at tri-state #0 1 BPWM pin in output mode #1 BPWM_POLCTL BPWM_POLCTL BPWM Pin Polar Inverse Register 0xD4 -1 read-write n 0x0 0x0 PINV0 BPWM PIN Polar Inverse Control The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n. 0 1 read-write 0 BPWM output polar inverse Disabled #0 1 BPWM output polar inverse Enabled #1 PINV1 BPWM PIN Polar Inverse Control The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n. 1 1 read-write 0 BPWM output polar inverse Disabled #0 1 BPWM output polar inverse Enabled #1 PINV2 BPWM PIN Polar Inverse Control The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n. 2 1 read-write 0 BPWM output polar inverse Disabled #0 1 BPWM output polar inverse Enabled #1 PINV3 BPWM PIN Polar Inverse Control The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n. 3 1 read-write 0 BPWM output polar inverse Disabled #0 1 BPWM output polar inverse Enabled #1 PINV4 BPWM PIN Polar Inverse Control The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n. 4 1 read-write 0 BPWM output polar inverse Disabled #0 1 BPWM output polar inverse Enabled #1 PINV5 BPWM PIN Polar Inverse Control The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n. 5 1 read-write 0 BPWM output polar inverse Disabled #0 1 BPWM output polar inverse Enabled #1 BPWM_RCAPDAT0 BPWM_RCAPDAT0 BPWM Rising Capture Data Register 0 0x20C -1 read-only n 0x0 0x0 RCAPDAT BPWM Rising Capture Data (Read Only) When rising capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_RCAPDAT1 BPWM_RCAPDAT1 BPWM Rising Capture Data Register 1 0x214 -1 read-write n 0x0 0x0 BPWM_RCAPDAT2 BPWM_RCAPDAT2 BPWM Rising Capture Data Register 2 0x21C -1 read-write n 0x0 0x0 BPWM_RCAPDAT3 BPWM_RCAPDAT3 BPWM Rising Capture Data Register 3 0x224 -1 read-write n 0x0 0x0 BPWM_RCAPDAT4 BPWM_RCAPDAT4 BPWM Rising Capture Data Register 4 0x22C -1 read-write n 0x0 0x0 BPWM_RCAPDAT5 BPWM_RCAPDAT5 BPWM Rising Capture Data Register 5 0x234 -1 read-write n 0x0 0x0 BPWM_SSCTL BPWM_SSCTL BPWM Synchronous Start Control Register 0x110 -1 read-write n 0x0 0x0 SSEN0 BPWM Synchronous Start Function 0 Enable Bit When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). 0 1 read-write 0 BPWM synchronous start function Disabled #0 1 BPWM synchronous start function Enabled #1 SSRC BPWM Synchronous Start Source Select 8 2 read-write 0 Synchronous start source come from PWM0 #00 1 Synchronous start source come from PWM1 #01 2 Synchronous start source come from BPWM0 #10 3 Synchronous start source come from BPWM1 #11 BPWM_SSTRG BPWM_SSTRG BPWM Synchronous Start Trigger Register 0x114 -1 write-only n 0x0 0x0 CNTSEN BPWM Counter Synchronous Start Enable Bit(Write Only) BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time. Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled. 0 1 write-only BPWM_STATUS BPWM_STATUS BPWM Status Register 0x120 -1 read-write n 0x0 0x0 CNTMAXF0 Time-base Counter 0 Equal to 0xFFFF Latched Flag 0 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value. Software can write 1 to clear this bit #1 EADCTRG0 EADC0 Start of Conversion Status Each bit n controls the corresponding BPWM channel n. 16 1 read-write 0 No EADC0 start of conversion trigger event has occurred #0 1 An EADC0 start of conversion trigger event has occurred. Software can write 1 to clear this bit #1 EADCTRG1 EADC0 Start of Conversion Status Each bit n controls the corresponding BPWM channel n. 17 1 read-write 0 No EADC0 start of conversion trigger event has occurred #0 1 An EADC0 start of conversion trigger event has occurred. Software can write 1 to clear this bit #1 EADCTRG2 EADC0 Start of Conversion Status Each bit n controls the corresponding BPWM channel n. 18 1 read-write 0 No EADC0 start of conversion trigger event has occurred #0 1 An EADC0 start of conversion trigger event has occurred. Software can write 1 to clear this bit #1 EADCTRG3 EADC0 Start of Conversion Status Each bit n controls the corresponding BPWM channel n. 19 1 read-write 0 No EADC0 start of conversion trigger event has occurred #0 1 An EADC0 start of conversion trigger event has occurred. Software can write 1 to clear this bit #1 EADCTRG4 EADC0 Start of Conversion Status Each bit n controls the corresponding BPWM channel n. 20 1 read-write 0 No EADC0 start of conversion trigger event has occurred #0 1 An EADC0 start of conversion trigger event has occurred. Software can write 1 to clear this bit #1 EADCTRG5 EADC0 Start of Conversion Status Each bit n controls the corresponding BPWM channel n. 21 1 read-write 0 No EADC0 start of conversion trigger event has occurred #0 1 An EADC0 start of conversion trigger event has occurred. Software can write 1 to clear this bit #1 BPWM_WGCTL0 BPWM_WGCTL0 BPWM Generation Register 0 0xB0 -1 read-write n 0x0 0x0 PRDPCTL0 BPWM Period (Center) Point Control Each bit n controls the corresponding BPWM channel n. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. 16 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL1 BPWM Period (Center) Point Control Each bit n controls the corresponding BPWM channel n. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. 18 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL2 BPWM Period (Center) Point Control Each bit n controls the corresponding BPWM channel n. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. 20 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL3 BPWM Period (Center) Point Control Each bit n controls the corresponding BPWM channel n. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. 22 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL4 BPWM Period (Center) Point Control Each bit n controls the corresponding BPWM channel n. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. 24 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 PRDPCTL5 BPWM Period (Center) Point Control Each bit n controls the corresponding BPWM channel n. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. 26 2 read-write 0 Do nothing #00 1 BPWM period (center) point output Low #01 2 BPWM period (center) point output High #10 3 BPWM period (center) point output Toggle #11 ZPCTL0 BPWM Zero Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter counts to 0. 0 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL1 BPWM Zero Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter counts to 0. 2 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL2 BPWM Zero Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter counts to 0. 4 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL3 BPWM Zero Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter counts to 0. 6 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL4 BPWM Zero Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter counts to 0. 8 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 ZPCTL5 BPWM Zero Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter counts to 0. 10 2 read-write 0 Do nothing #00 1 BPWM zero point output Low #01 2 BPWM zero point output High #10 3 BPWM zero point output Toggle #11 BPWM_WGCTL1 BPWM_WGCTL1 BPWM Generation Register 1 0xB4 -1 read-write n 0x0 0x0 CMPDCTL0 BPWM Compare Down Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter down counts to CMPDAT. 16 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL1 BPWM Compare Down Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter down counts to CMPDAT. 18 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL2 BPWM Compare Down Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter down counts to CMPDAT. 20 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL3 BPWM Compare Down Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter down counts to CMPDAT. 22 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL4 BPWM Compare Down Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter down counts to CMPDAT. 24 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPDCTL5 BPWM Compare Down Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter down counts to CMPDAT. 26 2 read-write 0 Do nothing #00 1 BPWM compare down point output Low #01 2 BPWM compare down point output High #10 3 BPWM compare down point output Toggle #11 CMPUCTL0 BPWM Compare Up Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter up counts to CMPDAT. 0 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL1 BPWM Compare Up Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter up counts to CMPDAT. 2 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL2 BPWM Compare Up Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter up counts to CMPDAT. 4 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL3 BPWM Compare Up Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter up counts to CMPDAT. 6 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL4 BPWM Compare Up Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter up counts to CMPDAT. 8 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CMPUCTL5 BPWM Compare Up Point Control Each bit n controls the corresponding BPWM channel n. Note: BPWM can control output level when BPWM counter up counts to CMPDAT. 10 2 read-write 0 Do nothing #00 1 BPWM compare up point output Low #01 2 BPWM compare up point output High #10 3 BPWM compare up point output Toggle #11 CIR0 CIR0 Register Map CIR0 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x18 0x14 registers n 0x38 0x10 registers n CIR_CMPCTL CIR_CMPCTL CIR Data Compare Control Register 0x4 -1 read-write n 0x0 0x0 CMPDAT Compared Match Data This bit field should be filled with the expected data. It will be compared with CIR_DATA0[N:0]. Note: N is determined by CMPVALID(CIR_CMPCTL[26:24]). 0 8 read-write CMPMSK Data Compared Mask Initialization Note: This bit is auto cleared by hardware. 16 1 read-write 0 No effect #0 1 Re-initialize the data compared match function to monitor DATA0[N:0] (CIR_DATA0[N:0) #1 CMPVALID Data Compared Valid Bit Selection Note: The sampling clock should be less than PCLK1. 24 3 read-write 0 Compare bit 0 #000 1 Compare bit 0 to bit 1 #001 2 Compare bit 0 to bit 2 #010 3 Compare bit 0 to bit 3 #011 4 Compare bit 0 to bit 4 #100 5 Compare bit 0 to bit 5 #101 6 Compare bit 0 to bit 6 #110 7 Compare bit 0 to bit 7 #111 DCMPEN Data Compared Match Function Selection 8 1 read-write 0 Data compared match function Disabled #0 1 Data compared match function Enabled #1 CIR_CTL CIR_CTL CIR Control Register 0x0 -1 read-write n 0x0 0x0 CNTEN CIR Counter Enable Note: When user changes CNTEN (CIR_CTL[0]) from 0 to 1, system will generate a signal to initialize all interrupt flags, RBITCNT (CIR_RDBC[5:0])and ITVR (CIR_ITVR[31:0]). 0 1 read-write 0 CIR counter Disabled #0 1 CIR counter Enabled #1 DBSEL Debounce Sampling Selection 9 2 read-write 0 CIR noise filter Disabled #00 1 CIR input debounce count Enabled with two sample matched #01 2 CIR input debounce count Enabled with three sample matched #10 3 CIR input debounce count Enabled with four sample matched #11 ERRBYP Error Pattern Bypass Note: 1.If user clears RERRF(CIR_STATUS[6]), then CIR will keep to convert data and store in CIR_DATAx. 2.User must set ERRBYP (CIR_CTL[4]) to 1 before entering Power-down mode. 4 1 read-write 0 Data will be dropped if RERRF(CIR_STATUS[6]) is 1 #0 1 Data will keep to save in DATAx if RERRF(CIR_STATUS[6]) flag is 1 #1 FOSTRS Filter Output Signal Stored in Register Selection 11 1 read-write 0 Filter output signal stored in CIR_STATUS[16] Disabled #0 1 Filter output signal stored in CIR_STATUS[16] Enabled #1 PATTYP CIR Pattern Format Selection 5 2 read-write 0 Standardized positive edge mode #00 1 Standardized negative edge mode #01 2 Flexible positive edge mode #10 3 Reserved. #11 POLINV CIR Input Polarity Inverse 1 1 read-write 0 CIR input polarity is normal #0 1 CIR input polarity is inversed #1 PSCALER Sampling Clock Prescaler Note: The sampling clock should be less than PCLK1. 16 3 read-write 0 No prescaler #000 1 Prescaler is 2 clocks #001 2 Prescaler is 4 clocks #010 3 Prescaler is 8 clocks #011 4 Prescaler is 16 clocks #100 5 Prescaler is 32 clocks #101 6 Prescaler is 64 clocks #110 7 Prescaler is 128 clocks #111 CIR_D0BOUND CIR_D0BOUND CIR Data 0 Pattern Boundry Register 0x1C -1 read-write n 0x0 0x0 HBOUND High Boundary Data0 Pattern Upper limit of Data 0 pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Data0 pattern boundary. 16 11 read-write LBOUND Low Boundary Data0 Pattern Lower limit of Data 0 pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Data0 pattern boundary. 0 11 read-write CIR_D1BOUND CIR_D1BOUND CIR Data 1 Pattern Boundry Register 0x20 -1 read-write n 0x0 0x0 HBOUND High Boundary Data 1 Pattern Upper limit of Data 1 pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Data1 pattern boundary. 16 11 read-write LBOUND Low Boundary Data 1 Pattern Upper limit of Data 1 pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Data1 pattern boundary. 0 11 read-write CIR_DATA0 CIR_DATA0 CIR Receive Data0 Register 0x40 -1 read-write n 0x0 0x0 DATA0 CIR DATA0 Register CIR converts data and stores the data in Data0 when RBITCNT(CIR_RDBC[5:0]) value is between 0 to 31. Note: User can write 1 to CIR_DATA0[31:0] to clean DATA0 value only when the register CNTEN(CIR_CTL[0]) is set to 0. 0 32 read-write CIR_DATA1 CIR_DATA1 CIR Receive Data1 Register 0x44 -1 read-write n 0x0 0x0 DATA1 CIR DATA1 Register CIR converts data and stores the data in Data1 when RBITCNT(CIR_RDBC[5:0]) value is between 32 to 63. Note: User can write 1 to CIR_DATA1[31:0] to clean DATA1 value only when the register CNTEN(CIR_CTL[0]) is set to 0. 0 32 read-write CIR_ENDBOUND CIR_ENDBOUND CIR End Pattern Boundry Register 0x28 -1 read-write n 0x0 0x0 LBOUND Low Boundary End Pattern Lower limit of End pattern input range. 0 11 read-write CIR_HDBOUND CIR_HDBOUND CIR Header Pattern Boundry Register 0x18 -1 read-write n 0x0 0x0 HBOUND High Boundary Header Pattern Upper limit of Header pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Header pattern boundary. 16 11 read-write LBOUND Low Boundary Header Pattern Lower limit of Header pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Header pattern boundary. 0 11 read-write CIR_INTCTL CIR_INTCTL CIR Interrupt Control Register 0x10 -1 read-write n 0x0 0x0 CMPMIEN Compare Match Interrupt Enable Bit 7 1 read-write 0 Compare match interrupt Disabled #0 1 Compare match interrupt Enabled #1 D0PMIEN Data0 Pattern Match Interrupt Enable Bit 2 1 read-write 0 Data0 pattern match interrupt Disabled #0 1 Data0 pattern match interrupt Enabled #1 D1PMIEN Data1 Pattern Match Interrupt Enable Bit 1 1 read-write 0 Data1 pattern match interrupt Disabled #0 1 Data1 pattern match interrupt Enabled #1 DRECIEN Data Receive Interrupt Enable Bit 5 1 read-write 0 Data receive interrupt Disabled #0 1 Data receive interrupt Enabled #1 EPMIEN End Pattern Match Interrupt Enable Bit 8 1 read-write 0 End pattern match interrupt Disabled #0 1 End pattern match interrupt Enabled #1 HPMIEN Header Pattern Match Interrupt Enable Bit 3 1 read-write 0 Header pattern match interrupt Disabled #0 1 Header pattern match interrupt Enabled #1 PDWKIEN Power Down Wake-up interrupt Enable Bit 10 1 read-write 0 Power down wake-up interrupt Disabled #0 1 Power down wake-up interrupt Enabled #1 PERRIEN Pattern Error Interrupt Enable Bit 6 1 read-write 0 Pattern error interrupt Disabled #0 1 Pattern error interrupt Enabled #1 RBMIEN Receive Bit Match Interrupt Enable Bit 9 1 read-write 0 Receive bit match interrupt Disabled #0 1 Receive bit match interrupt Enabled #1 RBUFIEN Receive Buffer Full Interrupt Enable Bit 4 1 read-write 0 Receive buffer full interrupt Disabled #0 1 Receive buffer full interrupt Enabled #1 SPMIEN Special Pattern Match Interrupt Enable Bit 0 1 read-write 0 Special pattern match interrupt Disabled #0 1 Special pattern match interrupt Enabled #1 CIR_LTVR CIR_LTVR CIR Latch Timer Value Register 0x38 -1 read-only n 0x0 0x0 LTV Latch Timer Value The register is used to record CIR latch timer value. Note: User can only read this register when HPMF (CIR_STATUS[3]), D0PMF (CIR_STATUS[2]), D1PMF (CIR_STATUS[1]), SPMF (CIR_STATUS[0]) or RERRF (CIR_STATUS[6]) occurred. 0 11 read-only CIR_RDBC CIR_RDBC CIR Receive Data Bit Count Register 0x3C -1 read-write n 0x0 0x0 BCCMEN Bit Count Compared Match Selection 8 1 read-write 0 Bit count compared match function Disabled #0 1 Bit count compared match function Enabled #1 RBITCMP Receive Data Bit Compare Data User can limit the converted data length by RBITCMP register. When CIR starts to convert data and RBITCNT(CIR_RDBC[5:0]) is equal to RBITCMP (CIR_RDBC[21:16]), the flag RBMF(CIR_STATUS[9]) will be asserted Note: The maximum value of RBITCMP (CIR_RDBC[22:16]) is 7'h40. 16 7 read-write RBITCNT Receive Data Bit Counts RBITCNT (CIR_RDBC[5:0]) correspond to CIR_DATA0 and CIR_DATA1 when CIR starts to convert data. Note: 1. User can write 1 to CIR_RDBC[5:0] to clean RBITCNT (CIR_RDBC[5:0]) value. 2. RBITCNT (CIR_RDBC[5:0]) value indicates the amount of data DATA0 (CIR_DATA0) that has already been confirmed. 3. The maximum value of RBITCNT (CIR_RDBC[5:0]) is 7'h40. 0 7 read-write CIR_SPBOUND CIR_SPBOUND CIR Special Pattern Boundry Register 0x24 -1 read-write n 0x0 0x0 HBOUND High Boundary Special Pattern Upper limit of Special pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Special pattern boundary. 16 11 read-write LBOUND Low Boundary Special Pattern Lower limit of Special pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Special pattern boundary. 0 11 read-write CIR_STATUS CIR_STATUS CIR Status Register 0x8 -1 read-write n 0x0 0x0 COMPMF Compare Match Flag Note: This bit is only cleared by writing 1 to it. 7 1 read-write 0 Compare match never happened #0 1 Compare match happened #1 D0PMF Data0 Pattern Match Flag Note: This bit is only cleared by writing 1 to it. 2 1 read-write 0 Data0 pattern never happened #0 1 Data0 pattern happened #1 D1PMF Data1 Pattern Match Flag Note: This bit is only cleared by writing 1 to it. 1 1 read-write 0 Data1 pattern never happened #0 1 Data1 pattern happened #1 DRECF Data Receive Flag Note: This bit is only cleared by writing 1 to it. 5 1 read-write 0 CIR has not started to convert data #0 1 CIR has started to convert data #1 EPMF End Pattern Match Flag Note: This bit is only cleared by writing 1 to it. 8 1 read-write 0 End pattern match never happened #0 1 End pattern match happened #1 HPMF Header Pattern Match Flag Note: This bit is only cleared by writing 1 to it. 3 1 read-write 0 Header pattern never happened #0 1 Header pattern happened #1 NFOS Noise Filter Output Signal Status 16 1 read-write 0 Noise filter output value is 0 #0 1 Noise filter output value is 1 #1 PDWKF Power Down Wake Up Flag Note: This bit is only cleared by writing 1 to it. 10 1 read-write 0 Power down wake up never happened #0 1 Power down wake up happened #1 RBITCBS RBITCNT Busy Clearing Status 17 1 read-write 0 RBITCNT has completed the clearing process when user writes 1 to RBITCNT(CIR_RDBC[5:0]) or user changes CNTEN (CIR_CTL[0]) from 0 to 1, and system will generate a signal to initialize RBITCNT (CIR_RDBC[5:0]) #0 1 RBITCNT undergoes clearing process when user writes 1 to RBITCNT(CIR_RDBC[5:0]) or user changes CNTEN (CIR_CTL[0]) from 0 to 1, and system will generate a signal to initialize RBITCNT (CIR_RDBC[5:0]) #1 RBMF Receive Bit Match Flag Note: This bit is only cleared by writing 1 to it. 9 1 read-write 0 Receive bit match never happened #0 1 Receive bit match happened #1 RBUFF Receiving Buffer Full Flag Note: This bit is only cleared by writing 1 to it. 4 1 read-write 0 Receiving buffer full never happened #0 1 Receiving buffer full happened #1 RERRF Receive Error Flag Note: This bit is only cleared by writing 1 to it. 6 1 read-write 0 Receive error never happened #0 1 Receive error happened #1 SPMF Special Pattern Match Flag Note: This bit is only cleared by writing 1 to it. 0 1 read-write 0 Special pattern never happened #0 1 Special pattern happened #1 CLK CLK Register Map CLK 0x0 0x0 0x24 registers n 0x30 0x8 registers n 0x40 0x4 registers n 0x50 0x4 registers n 0x60 0x4 registers n 0x70 0x10 registers n 0x90 0x4 registers n AHBCLK CLK_AHBCLK AHB Devices Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 CRCCKEN CRC Generator Controller Clock Enable Bit 7 1 read-write 0 CRC peripheral clock Disabled #0 1 CRC peripheral clock Enabled #1 FMCIDLE Flash Memory Controller Clock Enable Bit in IDLE Mode 15 1 read-write 0 FMC clock Disabled when chip is under IDLE mode #0 1 FMC clock Enabled when chip is under IDLE mode #1 GPACKEN GPIOA Clock Enable Bit 24 1 read-write 0 GPIOA port clock Disabled #0 1 GPIOA port clock Enabled #1 GPBCKEN GPIOB Clock Enable Bit 25 1 read-write 0 GPIOB port clock Disabled #0 1 GPIOB port clock Enabled #1 GPCCKEN GPIOC Clock Enable Bit 26 1 read-write 0 GPIOC port clock Disabled #0 1 GPIOC port clock Enabled #1 GPDCKEN GPIOD Clock Enable Bit 27 1 read-write 0 GPIOD port clock Disabled #0 1 GPIOD port clock Enabled #1 GPECKEN GPIOE Clock Enable Bit 28 1 read-write 0 GPIOE port clock Disabled #0 1 GPIOE port clock Enabled #1 GPFCKEN GPIOF Clock Enable Bit 29 1 read-write 0 GPIOF port clock Disabled #0 1 GPIOF port clock Enabled #1 GPGCKEN GPIOG Clock Enable Bit 30 1 read-write 0 GPIOG port clock Disabled #0 1 GPIOG port clock Enabled #1 GPHCKEN GPIOH Clock Enable Bit 31 1 read-write 0 GPIOH port clock Disabled #0 1 GPIOH port clock Enabled #1 GPICKEN GPIOI Clock Enable Bit 23 1 read-write 0 GPIOI port clock Disabled #0 1 GPIOI port clock Enabled #1 ISPCKEN Flash ISP Controller Clock Enable Bit 2 1 read-write 0 Flash ISP peripheral clock Disabled #0 1 Flash ISP peripheral clock Enabled #1 PDMACKEN PDMA Controller Clock Enable Bit 1 1 read-write 0 PDMA peripheral clock Disabled #0 1 PDMA peripheral clock Enabled #1 STCLKEN Cortex-M4 SysTick Clock Enable Bit 4 1 read-write 0 Cortex-M4 sys tick clock Disabled #0 1 Cortex-M4 sys tick clock Enabled #1 TRACECKEN TRACE Clock Enable Bit 19 1 read-write 0 TRACE clock Disabled #0 1 TRACE clock Enabled #1 APBCLK0 CLK_APBCLK0 APB Devices Clock Enable Control Register 0 0x8 -1 read-write n 0x0 0x0 ACMP01CKEN Analog Comparator 0/1 Clock Enable Bit 7 1 read-write 0 Analog comparator 0/1 clock Disabled #0 1 Analog comparator 0/1 clock Enabled #1 CLKOCKEN CLKO Clock Enable Bit 6 1 read-write 0 CLKO clock Disabled #0 1 CLKO clock Enabled #1 EADCCKEN Enhanced Analog-digital-converter (EADC) Clock Enable Bit 28 1 read-write 0 EADC clock Disabled #0 1 EADC clock Enabled #1 I2C0CKEN I2C0 Clock Enable Bit 8 1 read-write 0 I2C0 clock Disabled #0 1 I2C0 clock Enabled #1 I2C1CKEN I2C1 Clock Enable Bit 9 1 read-write 0 I2C1 clock Disabled #0 1 I2C1 clock Enabled #1 RTCCKEN Real-time-clock APB Interface Clock Enable Bit This bit is used to control the RTC APB clock only. 1 1 read-write 0 RTC clock Disabled #0 1 RTC clock Enabled #1 SPI0CKEN SPI0 Clock Enable Bit 13 1 read-write 0 SPI0 clock Disabled #0 1 SPI0 clock Enabled #1 SPI1CKEN SPI1 Clock Enable Bit 14 1 read-write 0 SPI1 clock Disabled #0 1 SPI1 clock Enabled #1 TMR0CKEN Timer0 Clock Enable Bit 2 1 read-write 0 Timer0 clock Disabled #0 1 Timer0 clock Enabled #1 TMR1CKEN Timer1 Clock Enable Bit 3 1 read-write 0 Timer1 clock Disabled #0 1 Timer1 clock Enabled #1 TMR2CKEN Timer2 Clock Enable Bit 4 1 read-write 0 Timer2 clock Disabled #0 1 Timer2 clock Enabled #1 TMR3CKEN Timer3 Clock Enable Bit 5 1 read-write 0 Timer3 clock Disabled #0 1 Timer3 clock Enabled #1 UART0CKEN UART0 Clock Enable Bit 16 1 read-write 0 UART0 clock Disabled #0 1 UART0 clock Enabled #1 UART1CKEN UART1 Clock Enable Bit 17 1 read-write 0 UART1 clock Disabled #0 1 UART1 clock Enabled #1 UART2CKEN UART2 Clock Enable Bit 18 1 read-write 0 UART2 clock Disabled #0 1 UART2 clock Enabled #1 UART3CKEN UART3 Clock Enable Bit 19 1 read-write 0 UART3 clock Disabled #0 1 UART3 clock Enabled #1 UART4CKEN UART4 Clock Enable Bit 20 1 read-write 0 UART4 clock Disabled #0 1 UART4 clock Enabled #1 UART5CKEN UART5 Clock Enable Bit 21 1 read-write 0 UART5 clock Disabled #0 1 UART5 clock Enabled #1 WDTCKEN Watchdog Timer Clock Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Watchdog timer clock Disabled #0 1 Watchdog timer clock Enabled #1 APBCLK1 CLK_APBCLK1 APB Devices Clock Enable Control Register 1 0xC -1 read-write n 0x0 0x0 BPWM0CKEN BPWM0 Clock Enable Bit 18 1 read-write 0 BPWM0 clock Disabled #0 1 BPWM0 clock Enabled #1 BPWM1CKEN BPWM1 Clock Enable Bit 19 1 read-write 0 BPWM1 clock Disabled #0 1 BPWM1 clock Enabled #1 CIR0CKEN CIR0 Clock Enable Bit 15 1 read-write 0 CIR0 clock Disabled #0 1 CIR0 clock Enabled #1 DACCKEN DAC Clock Enable Bit 12 1 read-write 0 DAC clock Disabled #0 1 DAC clock Enabled #1 EPWM0CKEN EPWM0 Clock Enable Bit 16 1 read-write 0 EPWM0 clock Disabled #0 1 EPWM0 clock Enabled #1 EPWM1CKEN EPWM1 Clock Enable Bit 17 1 read-write 0 EPWM1 clock Disabled #0 1 EPWM1 clock Enabled #1 PRNGCKEN PRNG Clock Enable Bit 24 1 read-write 0 PRNG clock Disabled #0 1 PRNG clock Enabled #1 CDLOWB CLK_CDLOWB Clock Frequency Range Detector Lower Boundary Register 0x7C -1 read-write n 0x0 0x0 LOWERBD HXT Clock Frequency Range Detector Lower Boundary Value The bits define the minimum value of frequency range detector window. When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will be set to 1. 0 11 read-write CDUPB CLK_CDUPB Clock Frequency Range Detector Upper Boundary Register 0x78 -1 read-write n 0x0 0x0 UPERBD HXT Clock Frequency Range Detector Upper Boundary Value The bits define the maximum value of frequency range detector window. When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will be set to 1. 0 11 read-write CLKDCTL CLK_CLKDCTL Clock Fail Detector Control Register 0x70 -1 read-write n 0x0 0x0 HXTFDEN HXT Clock Fail Detector Enable Bit 4 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled #1 HXTFIEN HXT Clock Fail Interrupt Enable Bit 5 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled #1 HXTFQDEN HXT Clock Frequency Range Detector Enable Bit 16 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled #1 HXTFQIEN HXT Clock Frequency Range Detector Interrupt Enable Bit 17 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled #1 LXTFDEN LXT Clock Fail Detector Enable Bit 12 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled #1 LXTFIEN LXT Clock Fail Interrupt Enable Bit 13 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled #1 CLKDIV0 CLK_CLKDIV0 Clock Divider Number Register 0 0x20 -1 read-write n 0x0 0x0 EADCDIV EADC Clock Divide Number From EADC Clock Source 16 8 read-write HCLKDIV HCLK Clock Divide Number From HCLK Clock Source 0 4 read-write UART0DIV UART0 Clock Divide Number From UART0 Clock Source 8 4 read-write UART1DIV UART1 Clock Divide Number From UART1 Clock Source 12 4 read-write CLKDIV4 CLK_CLKDIV4 Clock Divider Number Register 4 0x30 -1 read-write n 0x0 0x0 TRACEDIV Cortex M4 ETM Trace Clock Divide Number From ETM Trace Clock Source 24 8 read-write UART2DIV UART2 Clock Divide Number From UART2 Clock Source 0 4 read-write UART3DIV UART3 Clock Divide Number From UART3 Clock Source 4 4 read-write UART4DIV UART4 Clock Divide Number From UART4 Clock Source 8 4 read-write UART5DIV UART5 Clock Divide Number From UART5 Clock Source 12 4 read-write CLKDSTS CLK_CLKDSTS Clock Fail Detector Status Register 0x74 -1 read-write n 0x0 0x0 HXTFIF HXT Clock Fail Interrupt Flag Note: Write 1 to clear the bit to 0. 0 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock is normal #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock stops #1 HXTFQIF HXT Clock Frequency Range Detector Interrupt Flag Note: Write 1 to clear the bit to 0. 8 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is normal #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal #1 LXTFIF LXT Clock Fail Interrupt Flag Note: Write 1 to clear the bit to 0. 1 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock is normal #0 1 32.768 kHz external low speed crystal oscillator (LXT) stops #1 CLKOCTL CLK_CLKOCTL Clock Output Control Register 0x60 -1 read-write n 0x0 0x0 CLK1HZEN Clock Output 1Hz Enable Bit Note: Output for 32.768 kHz(LXT) or 38 kHz(LIRC) based on RTCCKSEL(RTC_LXTCTL[7]). 6 1 read-write 0 1 Hz clock output for 32.768 kHz or 38 kHz frequency compensation Disabled #0 1 1 Hz clock output for 32.768 kHz or 38 kHz frequency compensation Enabled #1 CLKOEN Clock Output Enable Bit 4 1 read-write 0 Clock Output function Disabled #0 1 Clock Output function Enabled #1 DIV1EN Clock Output Divide One Enable Bit 5 1 read-write 0 Clock Output will output clock with source frequency divided by FREQSEL #0 1 Clock Output will output clock with source frequency #1 FREQSEL Clock Output Frequency Selection The formula of output frequency is: Fin is the input clock frequency. Fout is the frequency of divider output clock. N is the 4-bit value of FREQSEL[3:0]. 0 4 read-write CLKSEL0 CLK_CLKSEL0 Clock Source Select Control Register 0 0x10 -1 read-write n 0x0 0x0 HCLKSEL HCLK Clock Source Selection (Write Protect) Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. The default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 3 read-write 0 Clock source from HXT #000 1 Clock source from LXT #001 2 Clock source from PLL #010 3 Clock source from LIRC #011 7 Clock source from HIRC #111 STCLKSEL Cortex-M4 SysTick Clock Source Selection (Write Protect) Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 3 3 read-write 0 Clock source from HXT #000 1 Clock source from LXT #001 2 Clock source from HXT/2 #010 3 Clock source from HCLK/2 #011 7 Clock source from HIRC/2 #111 CLKSEL1 CLK_CLKSEL1 Clock Source Select Control Register 1 0x14 -1 read-write n 0x0 0x0 CLKOSEL Clock Divider Clock Source Selection 28 2 read-write 0 Clock source from external high speed crystal oscillator (HXT) #00 1 Clock source from external low speed crystal oscillator (LXT) #01 2 Clock source from HCLK #10 3 Clock source from internal high speed RC oscillator (HIRC) #11 TMR0SEL TIMER0 Clock Source Selection 8 3 read-write 0 Clock source from external high speed crystal oscillator (HXT) #000 1 Clock source from external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK0 #010 3 Clock source from external clock TM0 pin #011 5 Clock source from internal low speed RC oscillator (LIRC) #101 7 Clock source from internal high speed RC oscillator (HIRC) #111 TMR1SEL TIMER1 Clock Source Selection 12 3 read-write 0 Clock source from external high speed crystal oscillator (HXT) #000 1 Clock source from external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK0 #010 3 Clock source from external clock TM1 pin #011 5 Clock source from internal low speed RC oscillator (LIRC) #101 7 Clock source from internal high speed RC oscillator (HIRC) #111 TMR2SEL TIMER2 Clock Source Selection 16 3 read-write 0 Clock source from external high speed crystal oscillator (HXT) #000 1 Clock source from external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK1 #010 3 Clock source from external clock TM2 pin #011 5 Clock source from internal low speed RC oscillator (LIRC) #101 7 Clock source from internal high speed RC oscillator (HIRC) #111 TMR3SEL TIMER3 Clock Source Selection 20 3 read-write 0 Clock source from external high speed crystal oscillator (HXT) #000 1 Clock source from external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK1 #010 3 Clock source from external clock TM3 pin #011 5 Clock source from internal low speed RC oscillator (LIRC) #101 7 Clock source from internal high speed RC oscillator (HIRC) #111 UART0SEL UART0 Clock Source Selection 24 2 read-write 0 Clock source from external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from external low speed crystal oscillator (LXT) #10 3 Clock source from internal high speed RC oscillator (HIRC) #11 UART1SEL UART1 Clock Source Selection 26 2 read-write 0 Clock source from external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from external low speed crystal oscillator (LXT) #10 3 Clock source from internal high speed RC oscillator (HIRC) #11 WDTSEL Watchdog Timer Clock Source Selection (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 2 read-write 0 Reserved. #00 1 Clock source from external low speed crystal oscillator (LXT) #01 2 Clock source from HCLK/2048 #10 3 Clock source from internal low speed RC oscillator (LIRC) #11 WWDTSEL Window Watchdog Timer Clock Source Selection 30 2 read-write 2 Clock source from HCLK/2048 #10 3 Clock source from internal low speed RC oscillator (LIRC) #11 CLKSEL2 CLK_CLKSEL2 Clock Source Select Control Register 2 0x18 -1 read-write n 0x0 0x0 BPWM0SEL BPWM0 Clock Source Selection The peripheral clock source of BPWM0 is defined by BPWM0SEL. 8 1 read-write 0 Clock source from HCLK #0 1 Clock source from PCLK0 #1 BPWM1SEL BPWM1 Clock Source Selection The peripheral clock source of BPWM1 is defined by BPWM1SEL. 9 1 read-write 0 Clock source from HCLK #0 1 Clock source from PCLK1 #1 CIR0SEL CIR0 Clock Source Selection 24 3 read-write 0 Clock source from external high speed crystal oscillator (HXT) #000 1 Clock source from external low speed crystal oscillator (LXT) #001 2 Clock source from Timer0 clock output (TM0) #010 3 Clock source from internal low speed RC oscillator (LIRC) #011 4 Clock source from internal high speed RC oscillator (HIRC) #100 EPWM0SEL EPWM0 Clock Source Selection The peripheral clock source of EPWM0 is defined by EPWM0SEL. 0 1 read-write 0 Clock source from HCLK #0 1 Clock source from PCLK0 #1 EPWM1SEL EPWM1 Clock Source Selection The peripheral clock source of EPWM1 is defined by EPWM1SEL. 1 1 read-write 0 Clock source from HCLK #0 1 Clock source from PCLK1 #1 SPI0SEL SPI0 Clock Source Selection 4 2 read-write 0 Clock source from external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from PCLK1 #10 3 Clock source from internal high speed RC oscillator (HIRC) #11 SPI1SEL SPI1 Clock Source Selection 6 2 read-write 0 Clock source from external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from PCLK0 #10 3 Clock source from internal high speed RC oscillator (HIRC) #11 CLKSEL3 CLK_CLKSEL3 Clock Source Select Control Register 3 0x1C -1 read-write n 0x0 0x0 UART2SEL UART2 Clock Source Selection 24 2 read-write 0 Clock source from external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from external low speed crystal oscillator (LXT) #10 3 Clock source from internal high speed RC oscillator (HIRC) #11 UART3SEL UART3 Clock Source Selection 26 2 read-write 0 Clock source from external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from external low speed crystal oscillator (LXT) #10 3 Clock source from internal high speed RC oscillator (HIRC) #11 UART4SEL UART4 Clock Source Selection 28 2 read-write 0 Clock source from external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from external low speed crystal oscillator (LXT) #10 3 Clock source from internal high speed RC oscillator (HIRC) #11 UART5SEL UART5 Clock Source Selection 30 2 read-write 0 Clock source from external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from external low speed crystal oscillator (LXT) #10 3 Clock source from internal high speed RC oscillator (HIRC) #11 PCLKDIV CLK_PCLKDIV APB Clock Divider Register 0x34 -1 read-write n 0x0 0x0 APB0DIV APB0 Clock Divider APB0 clock can be divided from HCLK Others: Reserved. 0 3 read-write APB1DIV APB1 Clock Divider APB1 clock can be divided from HCLK Others: Reserved. 4 3 read-write PLLCTL CLK_PLLCTL PLL Control Register 0x40 -1 read-write n 0x0 0x0 BP PLL Bypass Control (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 17 1 read-write 0 PLL is in normal mode (default) #0 1 PLL clock output is same as PLL input clock FIN #1 FBDIV PLL Feedback Divider Control (Write Protect) Refer to the formulas below the table. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 9 read-write INDIV PLL Input Divider Control (Write Protect) Refer to the formulas below the table. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 9 5 read-write OE PLL OE (FOUT Enable) Pin Control (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 18 1 read-write 0 PLL FOUT Enabled #0 1 PLL FOUT is fixed low #1 OUTDIV PLL Output Divider Control (Write Protect) Refer to the formulas below the table. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 14 2 read-write PD Power-down Mode (Write Protect) If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 16 1 read-write 0 PLL is in normal mode #0 1 PLL is in Power-down mode (default) #1 PLLSRC PLL Source Clock Selection (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 19 1 read-write 0 PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT) #0 1 PLL source clock from 48 MHz internal high-speed oscillator divided by 4 (HIRC/4) #1 STBSEL PLL Stable Counter Selection (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 23 1 read-write 0 PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz) #0 1 PLL stable time is 16128 PLL source clock (suitable for source clock is larger than 12 MHz) #1 PMUCTL CLK_PMUCTL Power Manager Control Register 0x90 -1 read-write n 0x0 0x0 PDMSEL Power-down Mode Selection (Write Protect) This is a protected bit. Please refer to open lock sequence to program it. These bits control chip Power-down mode grade selection when CPU executes WFI/WFE instruction. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 3 read-write 0 Power-down mode is selected. (NPD) #000 1 Reserved. #001 2 Reserved. #010 3 Reserved. #011 4 Reserved. #100 5 Reserved. #101 6 Reserved. #110 7 Reserved. #111 PWRCTL CLK_PWRCTL System Power-down Control Register 0x0 -1 read-write n 0x0 0x0 HIRCEN HIRC Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 48 MHz internal high speed RC oscillator (HIRC) Disabled #0 1 48 MHz internal high speed RC oscillator (HIRC) Enabled #1 HIRCSTBS HIRC Stable Count Select (Write Protect) Others: Reserved Note: This bit is write protected. Refer to the SYS_REGLCTL register. 16 2 read-write 0 HIRC stable count = 512 clocks #00 1 HIRC stable count = 1024 clocks #01 2 HIRC stable count = 2048 clocks #10 3 HIRC stable count = 256 clocks #11 HXTEN HXT Enable Bit (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: When HXT is enabled, GPF.2 and GPF.3 must be set as input mode. 0 1 read-write 0 4~24 MHz external high speed crystal (HXT) Disabled #0 1 4~24 MHz external high speed crystal (HXT) Enabled #1 HXTGAIN HXT Gain Control Bit (Write Protect) This is a protected register. Please refer to open lock sequence to program it. Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. Others: Reserved Note: This bit is write protected. Refer to the SYS_REGLCTL register. 20 3 read-write 0 HXT frequency is from 4 MHz to 8 MHz. HXT frequency is from 4 MHz to 8 MHz. (Crystal) #000 1 HXT frequency is from 8 MHz to 12 MHz. HXT frequency is from 8 MHz to 12 MHz. (Crystal) #001 2 HXT frequency is from 12 MHz to 16 MHz. HXT frequency is from 12 MHz to 16 MHz. (Crystal) #010 3 HXT frequency is from 16 MHz to 24 MHz. HXT frequency is from 16 MHz to 24 MHz. (Crystal) #011 4 HXT frequency is from 4 MHz to 8 MHz. (Resonator) #100 5 HXT frequency is from 8 MHz to 12 MHz. (Resonator) #101 6 HXT frequency is from 12 MHz to 16 MHz. (Resonator) #110 7 HXT frequency is from 16 MHz to 24 MHz. (Resonator) #111 HXTMD HXT Bypass Mode (Write Protect) This is a protected register. Please refer to open lock sequence to program it. Note 2: This bit is write protected. Refer to the SYS_REGCTL register. 31 1 read-write 0 HXT work as crystal mode. PF.2 and PF.3 are configured as external high speed crystal (HXT) pins #0 1 HXT works as external clock mode. PF.3 is configured as external clock input pin #1 LIRCEN LIRC Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 38.4 kHz internal low speed RC oscillator (LIRC) Disabled #0 1 38.4 kHz internal low speed RC oscillator (LIRC) Enabled #1 LXTEN LXT Enable Bit (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: When LXT is enabled, GPF.4 and GPF.5 must be set as input mode. 1 1 read-write 0 32.768 kHz external low speed crystal (LXT) Disabled #0 1 32.768 kHz external low speed crystal (LXT) Enabled #1 PDEN System Power-down Enable (Write Protect) When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down. In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Chip will not enter Power-down mode after CPU sleep command WFI #0 1 Chip enters Power-down mode after CPU sleep command WFI #1 PDWKDLY Enable the Wake-up Delay Counter (Write Protect) When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 48 MHz internal high speed RC oscillator (HIRC). Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 Clock cycles delay Disabled #0 1 Clock cycles delay Enabled #1 PDWKIEN Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) Note 1: The interrupt will occur when both PDWKIF and PDWKIEN are high. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 Power-down mode wake-up interrupt Disabled #0 1 Power-down mode wake-up interrupt Enabled #1 PDWKIF Power-down Mode Wake-up Interrupt Status Set by 'Power-down wake-up event', it indicates that resume from Power-down mode' The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter. Note 1: Write 1 to clear the bit to 0. Note 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) is set to 1. 6 1 read-write STATUS CLK_STATUS Clock Status Monitor Register 0x50 -1 read-only n 0x0 0x0 CLKSFAIL Clock Switching Fail Flag (Read Only) This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1. Note: Write 1 to clear the bit to 0. 7 1 read-only 0 Clock switching success #0 1 Clock switching failure #1 HIRCSTB HIRC Clock Source Stable Flag (Read Only) 4 1 read-only 0 48 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled #0 1 48 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled #1 HXTSTB HXT Clock Source Stable Flag (Read Only) 0 1 read-only 0 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled #1 LIRCSTB LIRC Clock Source Stable Flag (Read Only) 3 1 read-only 0 38.4 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled #0 1 38.4 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled #1 LXTSTB LXT Clock Source Stable Flag (Read Only) 1 1 read-only 0 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled #1 PLLSTB Internal PLL Clock Source Stable Flag (Read Only) 2 1 read-only 0 Internal PLL clock is not stable or disabled #0 1 Internal PLL clock is stable and enabled #1 CRC CRC Register Map CRC 0x0 0x0 0x10 registers n CHECKSUM CRC_CHECKSUM CRC Checksum Register 0xC -1 read-only n 0x0 0x0 CHECKSUM CRC Checksum Results This field indicates the CRC checksum result. 0 32 read-only CTL CRC_CTL CRC Control Register 0x0 -1 read-write n 0x0 0x0 CHKSFMT Checksum 1's Complement This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. 27 1 read-write 0 1's complement for CRC checksum Disabled #0 1 1's complement for CRC checksum Enabled #1 CHKSINIT Checksum Initialization Note: This bit will be cleared automatically. 1 1 read-write 0 No effect #0 1 Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value #1 CHKSREV Checksum Bit Order Reverse This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register. Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB. 25 1 read-write 0 Bit order reverse for CRC checksum Disabled #0 1 Bit order reverse for CRC checksum Enabled #1 CRCEN CRC Channel Enable Bit 0 1 read-write 0 No effect #0 1 CRC operation Enabled #1 CRCMODE CRC Polynomial Mode This field indicates the CRC operation polynomial mode. 30 2 read-write 0 CRC-CCITT Polynomial mode #00 1 CRC-8 Polynomial mode #01 2 CRC-16 Polynomial mode #10 3 CRC-32 Polynomial mode #11 DATFMT Write Data 1's Complement This bit is used to enable the 1's complement function for write data value in CRC_DAT register. 26 1 read-write 0 1's complement for CRC writes data in Disabled #0 1 1's complement for CRC writes data in Enabled #1 DATLEN CPU Write Data Length This field indicates the write data length. Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. 28 2 read-write 0 Data length is 8-bit mode #00 1 Data length is 16-bit mode. Data length is 32-bit mode #01 DATREV Write Data Bit Order Reverse This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register. Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB. 24 1 read-write 0 Bit order reversed for CRC write data in Disabled #0 1 Bit order reversed for CRC write data in Enabled (per byte) #1 DAT CRC_DAT CRC Write Data Register 0x4 -1 read-write n 0x0 0x0 DATA CRC Write Data Bits User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. 0 32 read-write SEED CRC_SEED CRC Seed Register 0x8 -1 read-write n 0x0 0x0 SEED CRC Seed Value This field indicates the CRC seed value. Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]). 0 32 read-write DAC DAC Register Map DAC 0x0 0x0 0x18 registers n 0x20 0x4 registers n DAC0_CTL DAC0_CTL DAC0 Control Register 0x0 -1 read-write n 0x0 0x0 DACEN DAC Enable Bit 0 1 read-write 0 DAC Disabled #0 1 DAC Enabled #1 DACIEN DAC Interrupt Enable Bit 1 1 read-write 0 DAC interrupt Disabled #0 1 DAC interrupt Enabled #1 DMAEN DMA Mode Enable Bit 2 1 read-write 0 DMA mode Disabled #0 1 DMA mode Enabled #1 DMAURIEN DMA Under-run Interrupt Enable Bit 3 1 read-write 0 DMA under-run interrupt Disabled #0 1 DMA under-run interrupt Enabled #1 ETRGSEL External Pin Trigger Selection 12 2 read-write 0 Low level trigger #00 1 High level trigger #01 2 Falling edge trigger #10 3 Rising edge trigger #11 TRGEN Trigger Mode Enable Bit 4 1 read-write 0 DAC event trigger mode Disabled #0 1 DAC event trigger mode Enabled #1 TRGSEL Trigger Source Selection 5 3 read-write 0 Software trigger #000 1 External pin DAC0_ST trigger #001 2 Timer 0 trigger #010 3 Timer 1 trigger #011 4 Timer 2 trigger #100 5 Timer 3 trigger #101 6 EPWM0 trigger #110 7 EPWM1 trigger #111 DAC0_DAT DAC0_DAT DAC0 Data Holding Register 0x8 -1 read-write n 0x0 0x0 DACDAT DAC 8-bit Holding Data These bits are written by user software which specifies 8-bit conversion data for DAC output. 0 8 read-write DAC0_DATOUT DAC0_DATOUT DAC0 Data Output Register 0xC -1 read-only n 0x0 0x0 DATOUT DAC 8-bit Output Data These bits are current digital data for DAC output conversion. It is loaded from DAC_DAT register and user cannot write it directly. 0 12 read-only DAC0_STATUS DAC0_STATUS DAC0 Status Register 0x10 -1 read-write n 0x0 0x0 BUSY DAC Busy Flag (Read Only) 8 1 read-only 0 DAC is ready for next conversion #0 1 DAC is busy in conversion #1 DMAUDR DMA Under-run Interrupt Flag Note: User writes 1 to clear this bit. 1 1 read-write 0 No DMA under-run error condition occurred #0 1 DMA under-run error condition occurred #1 FINISH DAC Conversion Complete Finish Flag Note: This bit is set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. User writes 1 to clear this bit to 0. 0 1 read-write 0 DAC is in conversion state #0 1 DAC conversion finish #1 DAC0_SWTRG DAC0_SWTRG DAC0 Software Trigger Control Register 0x4 -1 read-write n 0x0 0x0 SWTRG Software Trigger Note: User writes this bit to generate one shot pulse and this bit is cleared to 0 by hardware automatically reading this bit will always get 0. 0 1 read-write 0 Software trigger Disabled #0 1 Software trigger Enabled #1 DAC0_TCTL DAC0_TCTL DAC0 Timing Control Register 0x14 -1 read-write n 0x0 0x0 SETTLET DAC Output Settling Time User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed. For example, DAC controller clock speed is 80 MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x50. 0 10 read-write DAC0_VREF DAC0_VREF DAC0 Reference Voltage Control Register 0x20 -1 read-write n 0x0 0x0 OUTFLOAT DAC Output Floating Selection 5 1 read-write 0 DAC_OUT output DAC_ROUT #0 1 DAC_OUT output Hi-z #1 SELVREF DAC Reference Voltage Selection 4 1 read-write 0 DAC reference voltage is from AVDD #0 1 DAC reference voltage is from VREFP #1 DFMC DFMC Register Map DFMC 0x0 0x0 0x14 registers n 0x40 0x4 registers n 0x4C 0x4 registers n CYCCTL DFMC_CYCCTL Data Flash Access Cycle Control Register 0x4C -1 read-write n 0x0 0x0 CYCLE Data Flash Access Cycle Control (Write Protect) This register is updated by software. The optimized HCLK working frequency range is 192 MHz Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 4 read-write 0 CPU access with zero wait cycle Flash access cycle is 1 #0000 1 CPU access with one wait cycle if cache miss Flash access cycle is 1 #0001 2 CPU access with two wait cycles if cache miss Flash access cycle is 2 #0010 3 CPU access with three wait cycles if cache miss Flash access cycle is 3 #0011 4 CPU access with four wait cycles if cache miss Flash access cycle is 4 #0100 5 CPU access with five wait cycles if cache miss Flash access cycle is 5 #0101 6 CPU access with six wait cycles if cache miss Flash access cycle is 6 #0110 7 CPU access with seven wait cycles if cache miss Flash access cycle is 7 #0111 8 CPU access with eight wait cycles if cache miss Flash access cycle is 8 #1000 ISPADDR DFMC_ISPADDR ISP Address Register 0x4 -1 read-write n 0x0 0x0 ISPADDR ISP Address The M471V/M471K is equipped with embedded Data Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. For CRC32 Checksum Calculation command, this field is the Data Flash starting address for checksum calculation, 256 bytes alignment is necessary for CRC32 checksum calculation. For Data Flash32-bit Program, ISP address needs word alignment (4-byte). 0 32 read-write ISPCMD DFMC_ISPCMD ISP Command Register 0xC -1 read-write n 0x0 0x0 CMD ISP Command ISP command table is shown below: The other commands are invalid. 0 7 read-write 0 Data FLASH Read 0x00 8 Read Data Flash All-One Result 0x08 11 Read Company ID 0x0b 12 Read Device ID 0x0c 13 Read Checksum 0x0d 33 Data FLASH 32-bit Program 0x21 34 Data FLASH Page Erase. Erase any page in Data Flash 0x22 38 Data FLASH Mass Erase. Erase all pages in Data Flash 0x26 40 Run Data Flash All-One Verification 0x28 45 Run Checksum Calculation 0x2d ISPCTL DFMC_ISPCTL ISP Control Register 0x0 -1 read-write n 0x0 0x0 DATAEN Data Flash Update Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 Data Flash cannot be updated #0 1 Data Flash can be updated #1 ISPEN ISP Enable Bit (Write Protect) ISP function enable bit. Set this bit to enable ISP function. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 ISP function Disabled #0 1 ISP function Enabled #1 ISPFF ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: This bit needs to be cleared by writing 1 to it. Data Flash writes to itself if DATAEN is set to 0. Erase or Program command at brown-out detected Destination address is illegal, such as over an available range. Invalid ISP commands Violate the load code read protection Checksum or Flash All One Verification is not executed in their valid range Mass erase is not executed in Data Flash Note: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write ISPIFEN ISP Interrupt Enable bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 24 1 read-write 0 ISP Interrupt Disabled #0 1 ISP Interrupt Enabled #1 ISPDAT DFMC_ISPDAT ISP Data Register 0x8 -1 read-write n 0x0 0x0 ISPDAT ISP Data Write data to this register before ISP program operation. Read data from this register after ISP read operation. 0 32 read-write ISPSTS DFMC_ISPSTS ISP Status Register 0x40 -1 read-write n 0x0 0x0 ALLONE Data Flash All-one Verification Flag This bit is set by hardware if all of Flash bits are 1, and clear if Flash bits are not all 1 after 'Run Data Flash All-One Verification' complete this bit also can be clear by writing 1 7 1 read-write 0 Data Flash bits are not all 1 after 'Run Data Flash All-One Verification' is complete #0 1 All of Data Flash bits are 1 after 'Run Data Flash All-One Verification' is complete #1 ISPBUSY ISP Busy Flag (Read Only) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. This bit is the mirror of ISPGO(DFMC_ISPTRG[0]). 0 1 read-only 0 ISP operation is finished #0 1 ISP is progressed #1 ISPFF ISP Fail Flag (Write Protect) This bit is the mirror of ISPFF (DFMC_ISPCTL[6]), it needs to be cleared by writing 1 to DFMC_ISPCTL[6] or DFMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions: Data Flash writes to itself if DATAEN is set to 0. Erase or Program command at brown-out detected Destination address is illegal, such as over an available range. Invalid ISP commands Violate the load code read protection Checksum or Flash All One Verification is not executed in their valid range Mass erase is not executed in Data Flash Note: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write ISPIF ISP Interrupt Flag Note: Write 1 to clear this bit. 24 1 read-write 0 ISP command not finish or ISP fail flag is 0 #0 1 ISP command finish or ISP fail is 1 #1 ISPTRG DFMC_ISPTRG ISP Trigger Control Register 0x10 -1 read-write n 0x0 0x0 ISPGO ISP Start Trigger (Write Protect) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 ISP operation is finished #0 1 ISP is progressed #1 EADC EADC Register Map EADC 0x0 0x0 0x64 registers n 0x114 0x8 registers n 0x130 0x4 registers n 0x140 0x60 registers n 0x200 0x40 registers n 0x80 0x4C registers n 0xD0 0x40 registers n 0xFF8 0x4 registers n CALCTL EADC_CALCTL EADC Calibration Control Register 0x114 -1 read-write n 0x0 0x0 CAL Calibration Enable Bit Note: This bit is hardware auto cleared when calibration is done 0 1 read-write 0 = Calibration Disabled #0 1 = Calibration Enabled #1 CALADDR Calibration Data Address 8 5 read-write CALIE Calibration Interrupt Enable Bit 1 1 read-write 0 Calibration interrupt Disabled #0 1 Calibration interrupt Enabled #1 CALWRDATA Calibration Write Data 24 8 read-write CALSR EADC_CALSR EADC Calibration Status Register 0x118 -1 read-write n 0x0 0x0 CALIF Calibration Finish Interrupt Flag If calibration is finished, this flag will be set to 1. It is cleared by writing 1 to it. 16 1 read-write CMP0 EADC_CMP0 EADC Result Compare Register 0 0xE0 -1 read-write n 0x0 0x0 ADCMPEN EADC Result Compare Enable Bit 0 1 read-write 0 Compare Disabled #0 1 Compare Enabled #1 ADCMPIE EADC Result Compare Interrupt Enable Bit 1 1 read-write 0 Compare function interrupt Disabled #0 1 Compare function interrupt Enabled #1 CMPCOND Compare Condition 2 1 read-write 0 Set the compare condition as that when a 12-bit EADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one #0 1 Set the compare condition as that when a 12-bit EADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one #1 CMPDAT Comparison Data The 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software. 16 12 read-write CMPMCNT Compare Match Count 8 4 read-write CMPSPL Compare Sample Module Selection 3 5 read-write 0 Sample Module 0 conversion result EADC_DAT0 is selected to be compared #00000 1 Sample Module 1 conversion result EADC_DAT1 is selected to be compared #00001 2 Sample Module 2 conversion result EADC_DAT2 is selected to be compared #00010 3 Sample Module 3 conversion result EADC_DAT3 is selected to be compared #00011 4 Sample Module 4 conversion result EADC_DAT4 is selected to be compared #00100 5 Sample Module 5 conversion result EADC_DAT5 is selected to be compared #00101 6 Sample Module 6 conversion result EADC_DAT6 is selected to be compared #00110 7 Sample Module 7 conversion result EADC_DAT7 is selected to be compared #00111 8 Sample Module 8 conversion result EADC_DAT8 is selected to be compared #01000 9 Sample Module 9 conversion result EADC_DAT9 is selected to be compared #01001 10 Sample Module 10 conversion result EADC_DAT10 is selected to be compared #01010 11 Sample Module 11 conversion result EADC_DAT11 is selected to be compared #01011 12 Sample Module 12 conversion result EADC_DAT12 is selected to be compared #01100 13 Sample Module 13 conversion result EADC_DAT13 is selected to be compared #01101 14 Sample Module 14 conversion result EADC_DAT14 is selected to be compared #01110 15 Sample Module 15 conversion result EADC_DAT15 is selected to be compared #01111 16 Sample Module 16 conversion result EADC_DAT16 is selected to be compared #10000 17 Sample Module 17 conversion result EADC_DAT17 is selected to be compared #10001 18 Sample Module 18 conversion result EADC_DAT18 is selected to be compared #10010 19 Sample Module 19 conversion result EADC_DAT19 is selected to be compared #10011 20 Sample Module 20 conversion result EADC_DAT20 is selected to be compared #10100 21 Sample Module 21 conversion result EADC_DAT21 is selected to be compared #10101 22 Sample Module 22 conversion result EADC_DAT22 is selected to be compared #10110 23 Sample Module 23 conversion result EADC_DAT23 is selected to be compared #10111 24 Sample Module 24 conversion result EADC_DAT24 is selected to be compared #11000 25 Sample Module 25 conversion result EADC_DAT25 is selected to be compared #11001 26 Sample Module 26 conversion result EADC_DAT26 is selected to be compared #11010 CMPWEN Compare Window Mode Enable Bit Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. 15 1 read-write 0 EADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched. EADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched #0 1 EADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. EADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched #1 CMP1 EADC_CMP1 EADC Result Compare Register 1 0xE4 -1 read-write n 0x0 0x0 CMP2 EADC_CMP2 EADC Result Compare Register 2 0xE8 -1 read-write n 0x0 0x0 CMP3 EADC_CMP3 EADC Result Compare Register 3 0xEC -1 read-write n 0x0 0x0 CTL EADC_CTL EADC Control Register 0x50 -1 read-write n 0x0 0x0 ADCEN EADC Converter Enable Bit Note: Before starting EADC conversion function, this bit should be set to 1. Clear it to 0 to disable EADC converter analog circuit power consumption. 0 1 read-write 0 EADC Disabled #0 1 EADC Enabled #1 ADCIEN0 Specific Sample Module EADC ADINT0 Interrupt Enable Bit The EADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module EADC conversion. If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. 2 1 read-write 0 Specific sample module EADC ADINT0 interrupt function Disabled #0 1 Specific sample module EADC ADINT0 interrupt function Enabled #1 ADCIEN1 Specific Sample Module EADC ADINT1 Interrupt Enable Bit The EADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module EADC conversion. If EADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. 3 1 read-write 0 Specific sample module EADC ADINT1 interrupt function Disabled #0 1 Specific sample module EADC ADINT1 interrupt function Enabled #1 ADCIEN2 Specific Sample Module EADC ADINT2 Interrupt Enable Bit The EADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module EADC conversion. If EADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. 4 1 read-write 0 Specific sample module EADC ADINT2 interrupt function Disabled #0 1 Specific sample module EADC ADINT2 interrupt function Enabled #1 ADCIEN3 Specific Sample Module EADC ADINT3 Interrupt Enable Bit The EADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module EADC conversion. If EADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. 5 1 read-write 0 Specific sample module EADC ADINT3 interrupt function Disabled #0 1 Specific sample module EADC ADINT3 interrupt function Enabled #1 ADCRST EADC Converter Control Circuits Reset Note: EADCRST bit remains 1 during EADC reset, when EADC reset end, the EADCRST bit is automatically cleared to 0. 1 1 read-write 0 No effect #0 1 Cause EADC control circuits reset to initial state, but not change the EADC registers value #1 DIFFEN Differential Analog Input Mode Enable Bit Note: In the differential mode, the input channel pair must be configured to EADC_CH15, EADC_CH14 8 1 read-write 0 Single-end analog input mode #0 1 Differential analog input mode #1 CTL1 EADC_CTL1 EADC Control1 Register 0x60 -1 read-write n 0x0 0x0 DECSET High Speed Oversampling Mode Enable Bit 16 1 read-write 0 High speed oversampling mode Disabled #0 1 High speed oversampling mode Enabled #1 DISCHEN Discharge Enable Note: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enabled. 1 1 read-write 0 Channel discharge Disabled #0 1 Channel discharge Enabled #1 FDETCHEN Floating Detect Channel Enable Bit Note: if FDETCHEN is enabled, internal floating detect channel is always turn on. 8 1 read-write 0 Floating Detect Channel Disabled #0 1 Floating Detect Channel Enabled #1 OSR Repeat Conversion Times Select Note: The other steps of selection not listed above follow the same rule. 24 8 read-write PRECHEN Precharge Enable Note: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enabled. 0 1 read-write 0 Channel precharge Disabled #0 1 Channel precharge Enabled #1 ULPDIV Ultra Low Power Mode Prescalar selection 13 3 read-write 0 ADC_CLK divided by 1 #000 1 ADC_CLK divided by 2 #001 2 ADC_CLK divided by 4 #010 3 ADC_CLK divided by 8 #011 4 ADC_CLK divided by 16 #100 ULPEN Ultra Low Power Mode Enable Bit 12 1 read-write 0 Ultra low power mode Disabled #0 1 Ultra low power mode Enabled #1 CURDAT EADC_CURDAT EADC PDMA Current Transfer Data Register 0x4C -1 read-only n 0x0 0x0 CURDAT EADC PDMA Current Transfer Data (Read Only) 0 27 read-only DAT0 EADC_DAT0 EADC Data Register 0 for Sample Module 0 0x0 -1 read-only n 0x0 0x0 OV Overrun Flag If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. Note: It is cleared by hardware after EADC_DAT register is read. 16 1 read-only 0 Data in RESULT[11:0] is recent conversion result #0 1 Data in RESULT[11:0] is overwrite #1 RESULT EADC Conversion Result This field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. Note: When operating in oversampling mode, RESULT[15:0] can represent oversampling results. 0 16 read-only VALID Valid Flag This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. 17 1 read-only 0 Data in RESULT[11:0] bits is not valid #0 1 Data in RESULT[11:0] bits is valid #1 DAT1 EADC_DAT1 EADC Data Register 1 for Sample Module 1 0x4 -1 read-write n 0x0 0x0 DAT10 EADC_DAT10 EADC Data Register 10 for Sample Module 10 0x28 -1 read-write n 0x0 0x0 DAT11 EADC_DAT11 EADC Data Register 11 for Sample Module 11 0x2C -1 read-write n 0x0 0x0 DAT12 EADC_DAT12 EADC Data Register 12 for Sample Module 12 0x30 -1 read-write n 0x0 0x0 DAT13 EADC_DAT13 EADC Data Register 13 for Sample Module 13 0x34 -1 read-write n 0x0 0x0 DAT14 EADC_DAT14 EADC Data Register 14 for Sample Module 14 0x38 -1 read-write n 0x0 0x0 DAT15 EADC_DAT15 EADC Data Register 15 for Sample Module 15 0x3C -1 read-write n 0x0 0x0 DAT16 EADC_DAT16 EADC Data Register 16 for Sample Module 16 0x40 -1 read-write n 0x0 0x0 DAT17 EADC_DAT17 EADC Data Register 17 for Sample Module 17 0x44 -1 read-write n 0x0 0x0 DAT18 EADC_DAT18 EADC Data Register 18 for Sample Module 18 0x48 -1 read-write n 0x0 0x0 DAT19 EADC_DAT19 EADC Data Register 19 for Sample Module 19 0x200 -1 read-only n 0x0 0x0 OV Overrun Flag If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. Note: It is cleared by hardware after EADC_DAT register is read. 16 1 read-only 0 Data in RESULT[11:0] is recent conversion result #0 1 Data in RESULT[11:0] is overwrite #1 RESULT EADC Conversion Result This field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. 0 16 read-only VALID Valid Flag This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. 17 1 read-only 0 Data in RESULT[11:0] bits is not valid #0 1 Data in RESULT[11:0] bits is valid #1 DAT2 EADC_DAT2 EADC Data Register 2 for Sample Module 2 0x8 -1 read-write n 0x0 0x0 DAT20 EADC_DAT20 EADC Data Register 20 for Sample Module 20 0x204 -1 read-write n 0x0 0x0 DAT21 EADC_DAT21 EADC Data Register 21 for Sample Module 21 0x208 -1 read-write n 0x0 0x0 DAT22 EADC_DAT22 EADC Data Register 22 for Sample Module 22 0x20C -1 read-write n 0x0 0x0 DAT23 EADC_DAT23 EADC Data Register 23 for Sample Module 23 0x210 -1 read-write n 0x0 0x0 DAT24 EADC_DAT24 EADC Data Register 24 for Sample Module 24 0x214 -1 read-write n 0x0 0x0 DAT25 EADC_DAT25 EADC Data Register 25 for Sample Module 25 0x218 -1 read-write n 0x0 0x0 DAT26 EADC_DAT26 EADC Data Register 26 for Sample Module 26 0x21C -1 read-write n 0x0 0x0 DAT3 EADC_DAT3 EADC Data Register 3 for Sample Module 3 0xC -1 read-write n 0x0 0x0 DAT4 EADC_DAT4 EADC Data Register 4 for Sample Module 4 0x10 -1 read-write n 0x0 0x0 DAT5 EADC_DAT5 EADC Data Register 5 for Sample Module 5 0x14 -1 read-write n 0x0 0x0 DAT6 EADC_DAT6 EADC Data Register 6 for Sample Module 6 0x18 -1 read-write n 0x0 0x0 DAT7 EADC_DAT7 EADC Data Register 7 for Sample Module 7 0x1C -1 read-write n 0x0 0x0 DAT8 EADC_DAT8 EADC Data Register 8 for Sample Module 8 0x20 -1 read-write n 0x0 0x0 DAT9 EADC_DAT9 EADC Data Register 9 for Sample Module 9 0x24 -1 read-write n 0x0 0x0 DDAT0 EADC_DDAT0 EADC Double Data Register 0 for Sample Module 0 0x100 -1 read-only n 0x0 0x0 OV Overrun Flag If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after EADC_DDAT register is read. 16 1 read-only 0 Double Data in RESULT (EADC_DDATn[15:0], n=0~3) is recent conversion result #0 1 Double Data in RESULT (EADC_DDATn[15:0], n=0~3) is overwrite #1 RESULT EADC Conversion Results This field contains 12 bits conversion results. The 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. 0 16 read-only VALID Valid Flag 17 1 read-only 0 Double data in RESULT (EADC_DDATn[15:0]) is not valid #0 1 Double data in RESULT (EADC_DDATn[15:0]) is valid #1 DDAT1 EADC_DDAT1 EADC Double Data Register 1 for Sample Module 1 0x104 -1 read-write n 0x0 0x0 DDAT2 EADC_DDAT2 EADC Double Data Register 2 for Sample Module 2 0x108 -1 read-write n 0x0 0x0 DDAT3 EADC_DDAT3 EADC Double Data Register 3 for Sample Module 3 0x10C -1 read-write n 0x0 0x0 INTSRC0 EADC_INTSRC0 EADC Interrupt 0 Source Enable Control Register. 0xD0 -1 read-write n 0x0 0x0 SPLIE0 Sample Module 0 Interrupt Enable Bit 0 1 read-write 0 Sample Module 0 interrupt Disabled #0 1 Sample Module 0 interrupt Enabled #1 SPLIE1 Sample Module 1 Interrupt Enable Bit 1 1 read-write 0 Sample Module 1 interrupt Disabled #0 1 Sample Module 1 interrupt Enabled #1 SPLIE10 Sample Module 10 Interrupt Enable Bit 10 1 read-write 0 Sample Module 10 interrupt Disabled #0 1 Sample Module 10 interrupt Enabled #1 SPLIE11 Sample Module 11 Interrupt Enable Bit 11 1 read-write 0 Sample Module 11 interrupt Disabled #0 1 Sample Module 11 interrupt Enabled #1 SPLIE12 Sample Module 12 Interrupt Enable Bit 12 1 read-write 0 Sample Module 12 interrupt Disabled #0 1 Sample Module 12 interrupt Enabled #1 SPLIE13 Sample Module 13 Interrupt Enable Bit 13 1 read-write 0 Sample Module 13 interrupt Disabled #0 1 Sample Module 13 interrupt Enabled #1 SPLIE14 Sample Module 14 Interrupt Enable Bit 14 1 read-write 0 Sample Module 14 interrupt Disabled #0 1 Sample Module 14 interrupt Enabled #1 SPLIE15 Sample Module 15 Interrupt Enable Bit 15 1 read-write 0 Sample Module 15 interrupt Disabled #0 1 Sample Module 15 interrupt Enabled #1 SPLIE16 Sample Module 16 Interrupt Enable Bit 16 1 read-write 0 Sample Module 16 interrupt Disabled #0 1 Sample Module 16 interrupt Enabled #1 SPLIE17 Sample Module 17 Interrupt Enable Bit 17 1 read-write 0 Sample Module 17 interrupt Disabled #0 1 Sample Module 17 interrupt Enabled #1 SPLIE18 Sample Module 18 Interrupt Enable Bit 18 1 read-write 0 Sample Module 18 interrupt Disabled #0 1 Sample Module 18 interrupt Enabled #1 SPLIE19 Sample Module 19 Interrupt Enable Bit 19 1 read-write 0 Sample Module 19 interrupt Disabled #0 1 Sample Module 19 interrupt Enabled #1 SPLIE2 Sample Module 2 Interrupt Enable Bit 2 1 read-write 0 Sample Module 2 interrupt Disabled #0 1 Sample Module 2 interrupt Enabled #1 SPLIE20 Sample Module 20 Interrupt Enable Bit 20 1 read-write 0 Sample Module 20 interrupt Disabled #0 1 Sample Module 20 interrupt Enabled #1 SPLIE21 Sample Module 21 Interrupt Enable Bit 21 1 read-write 0 Sample Module 21 interrupt Disabled #0 1 Sample Module 21 interrupt Enabled #1 SPLIE22 Sample Module 22 Interrupt Enable Bit 22 1 read-write 0 Sample Module 22 interrupt Disabled #0 1 Sample Module 22 interrupt Enabled #1 SPLIE23 Sample Module 23 Interrupt Enable Bit 23 1 read-write 0 Sample Module 23 interrupt Disabled #0 1 Sample Module 23 interrupt Enabled #1 SPLIE24 Sample Module 24 Interrupt Enable Bit 24 1 read-write 0 Sample Module 24 interrupt Disabled #0 1 Sample Module 24 interrupt Enabled #1 SPLIE25 Sample Module 25 Interrupt Enable Bit 25 1 read-write 0 Sample Module 25 interrupt Disabled #0 1 Sample Module 25 interrupt Enabled #1 SPLIE26 Sample Module 26 Interrupt Enable Bit 26 1 read-write 0 Sample Module 26 interrupt Disabled #0 1 Sample Module 26 interrupt Enabled #1 SPLIE3 Sample Module 3 Interrupt Enable Bit 3 1 read-write 0 Sample Module 3 interrupt Disabled #0 1 Sample Module 3 interrupt Enabled #1 SPLIE4 Sample Module 4 Interrupt Enable Bit 4 1 read-write 0 Sample Module 4 interrupt Disabled #0 1 Sample Module 4 interrupt Enabled #1 SPLIE5 Sample Module 5 Interrupt Enable Bit 5 1 read-write 0 Sample Module 5 interrupt Disabled #0 1 Sample Module 5 interrupt Enabled #1 SPLIE6 Sample Module 6 Interrupt Enable Bit 6 1 read-write 0 Sample Module 6 interrupt Disabled #0 1 Sample Module 6 interrupt Enabled #1 SPLIE7 Sample Module 7 Interrupt Enable Bit 7 1 read-write 0 Sample Module 7 interrupt Disabled #0 1 Sample Module 7 interrupt Enabled #1 SPLIE8 Sample Module 8 Interrupt Enable Bit 8 1 read-write 0 Sample Module 8 interrupt Disabled #0 1 Sample Module 8 interrupt Enabled #1 SPLIE9 Sample Module 9 Interrupt Enable Bit 9 1 read-write 0 Sample Module 9 interrupt Disabled #0 1 Sample Module 9 interrupt Enabled #1 INTSRC1 EADC_INTSRC1 EADC Interrupt 1 Source Enable Control Register. 0xD4 -1 read-write n 0x0 0x0 INTSRC2 EADC_INTSRC2 EADC Interrupt 2 Source Enable Control Register. 0xD8 -1 read-write n 0x0 0x0 INTSRC3 EADC_INTSRC3 EADC Interrupt 3 Source Enable Control Register. 0xDC -1 read-write n 0x0 0x0 M0CTL1 EADC_M0CTL1 EADC Sample Module0 Control Register 1 0x140 -1 read-write n 0x0 0x0 ACU Number of Accumulated Conversion Results Selection 4 4 read-write 0 1 conversion result will be accumulated #0000 1 2 conversion result will be accumulated #0001 2 4 conversion result will be accumulated #0010 3 8 conversion result will be accumulated #0011 4 16 conversion result will be accumulated #0100 5 32 conversion result will be accumulated #0101 6 64 conversion result will be accumulated #0110 7 128 conversion result will be accumulated #0111 8 256 conversion result will be accumulated #1000 ALIGN Alignment Selection 0 1 read-write 0 The conversion result will be right aligned in data register #0 1 The conversion result will be left aligned in data register #1 AVG Average Mode Selection 1 1 read-write 0 Conversion results will be stored in data register without averaging #0 1 Conversion results in data register will be averaged #1 M10CTL1 EADC_M10CTL1 EADC Sample Module10 Control Register 1 0x168 -1 read-write n 0x0 0x0 M11CTL1 EADC_M11CTL1 EADC Sample Module11 Control Register 1 0x16C -1 read-write n 0x0 0x0 M12CTL1 EADC_M12CTL1 EADC Sample Module12 Control Register 1 0x170 -1 read-write n 0x0 0x0 M13CTL1 EADC_M13CTL1 EADC Sample Module13 Control Register 1 0x174 -1 read-write n 0x0 0x0 M14CTL1 EADC_M14CTL1 EADC Sample Module14 Control Register 1 0x178 -1 read-write n 0x0 0x0 M15CTL1 EADC_M15CTL1 EADC Sample Module15 Control Register 1 0x17C -1 read-write n 0x0 0x0 M16CTL1 EADC_M16CTL1 EADC Sample Module16 Control Register 1 0x180 -1 read-write n 0x0 0x0 M17CTL1 EADC_M17CTL1 EADC Sample Module17 Control Register 1 0x184 -1 read-write n 0x0 0x0 M18CTL1 EADC_M18CTL1 EADC Sample Module18 Control Register 1 0x188 -1 read-write n 0x0 0x0 M19CTL1 EADC_M19CTL1 EADC Sample Module19 Control Register 1 0x18C -1 read-write n 0x0 0x0 M1CTL1 EADC_M1CTL1 EADC Sample Module1 Control Register 1 0x144 -1 read-write n 0x0 0x0 M20CTL1 EADC_M20CTL1 EADC Sample Module20 Control Register 1 0x190 -1 read-write n 0x0 0x0 M21CTL1 EADC_M21CTL1 EADC Sample Module21 Control Register 1 0x194 -1 read-write n 0x0 0x0 M22CTL1 EADC_M22CTL1 EADC Sample Module22 Control Register 1 0x198 -1 read-write n 0x0 0x0 M23CTL1 EADC_M23CTL1 EADC Sample Module23 Control Register 1 0x19C -1 read-write n 0x0 0x0 M2CTL1 EADC_M2CTL1 EADC Sample Module2 Control Register 1 0x148 -1 read-write n 0x0 0x0 M3CTL1 EADC_M3CTL1 EADC Sample Module3 Control Register 1 0x14C -1 read-write n 0x0 0x0 M4CTL1 EADC_M4CTL1 EADC Sample Module4 Control Register 1 0x150 -1 read-write n 0x0 0x0 M5CTL1 EADC_M5CTL1 EADC Sample Module5 Control Register 1 0x154 -1 read-write n 0x0 0x0 M6CTL1 EADC_M6CTL1 EADC Sample Module6 Control Register 1 0x158 -1 read-write n 0x0 0x0 M7CTL1 EADC_M7CTL1 EADC Sample Module7 Control Register 1 0x15C -1 read-write n 0x0 0x0 M8CTL1 EADC_M8CTL1 EADC Sample Module8 Control Register 1 0x160 -1 read-write n 0x0 0x0 M9CTL1 EADC_M9CTL1 EADC Sample Module9 Control Register 1 0x164 -1 read-write n 0x0 0x0 OVSTS EADC_OVSTS EADC Sample Module Start of Conversion Overrun Flag Register 0x5C -1 read-write n 0x0 0x0 SPOVF EADC SAMPLE0~26 Overrun Flag Note: This bit is cleared by writing 1 to it. 0 27 read-write 0 No sample module event overrun 0 1 Indicates a new sample module event is generated while an old one event is pending 1 PDMACTL EADC_PDMACTL EADC PDMA Control Register 0x130 -1 read-write n 0x0 0x0 PDMATEN PDMA Transfer Enable Bit When EADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 26) register, user can enable this bit to generate a PDMA data transfer request. 0 27 read-write 0 PDMA data transfer Disabled 0 1 PDMA data transfer Enabled 1 PENDSTS EADC_PENDSTS EADC Start of Conversion Pending Flag Register 0x58 -1 read-write n 0x0 0x0 STPF EADC Sample Module 0~26 Start of Conversion Pending Flag Read Operation: 0 27 read-write 0 There is no pending conversion for sample module 0 1 Sample module EADC start of conversion is pending. Clear pending flag cancel the conversion for sample module 1 SCTL0 EADC_SCTL0 EADC Sample Module 0 Control Register 0x80 -1 read-write n 0x0 0x0 CHSEL EADC Sample Module Channel Selection 0 5 read-write DBMEN Double Buffer Mode Enable Bit 23 1 read-write 0 Sample has one sample result register (default) #0 1 Sample has two sample result registers #1 EXTFEN EADC External Trigger Falling Edge Enable Bit 22 1 read-write 0 Falling edge Disabled when EADC selects EADC0_ST as trigger source #0 1 Falling edge Enabled when EADC selects EADC0_ST as trigger source #1 EXTREN EADC External Trigger Rising Edge Enable Bit 21 1 read-write 0 Rising edge Disabled when EADC selects EADC0_ST as trigger source #0 1 Rising edge Enabled when EADC selects EADC0_ST as trigger source #1 EXTSMPT EADC Sampling Time Extend When EADC convertes at high conversion rate, the sampling time of analog input voltage may not be enough if input channel loading is heavy, and user can extend EADC sampling time after trigger source is coming to get enough sampling time. The range of start delay time is from 0~255 EADC clock. 24 8 read-write INTPOS Interrupt Flag Position Select 5 1 read-write 0 Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC end of conversion #0 1 Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC start of conversion #1 TRGDLYCNT EADC Sample Module Start of Conversion Trigger Delay Time 8 8 read-write TRGDLYDIV EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection Trigger delay clock frequency: 6 2 read-write 0 EADC_CLK/1 #00 1 EADC_CLK/2 #01 2 EADC_CLK/4 #10 3 EADC_CLK/16 #11 TRGSEL EADC Sample Module Start of Conversion Trigger Source Selection 16 5 read-write SCTL1 EADC_SCTL1 EADC Sample Module 1 Control Register 0x84 -1 read-write n 0x0 0x0 SCTL10 EADC_SCTL10 EADC Sample Module 10 Control Register 0xA8 -1 read-write n 0x0 0x0 SCTL11 EADC_SCTL11 EADC Sample Module 11 Control Register 0xAC -1 read-write n 0x0 0x0 SCTL12 EADC_SCTL12 EADC Sample Module 12 Control Register 0xB0 -1 read-write n 0x0 0x0 SCTL13 EADC_SCTL13 EADC Sample Module 13 Control Register 0xB4 -1 read-write n 0x0 0x0 SCTL14 EADC_SCTL14 EADC Sample Module 14 Control Register 0xB8 -1 read-write n 0x0 0x0 SCTL15 EADC_SCTL15 EADC Sample Module 15 Control Register 0xBC -1 read-write n 0x0 0x0 SCTL16 EADC_SCTL16 EADC Sample Module 16 Control Register 0xC0 -1 read-write n 0x0 0x0 SCTL17 EADC_SCTL17 EADC Sample Module 17 Control Register 0xC4 -1 read-write n 0x0 0x0 SCTL18 EADC_SCTL18 EADC Sample Module 18 Control Register 0xC8 -1 read-write n 0x0 0x0 SCTL19 EADC_SCTL19 EADC Sample Module 19 Control Register 0x220 -1 read-write n 0x0 0x0 CHSEL EADC Sample Module Channel Selection 0 5 read-write EXTFEN EADC External Trigger Falling Edge Enable Bit 22 1 read-write 0 Falling edge Disabled when EADC selects EADC0_ST as trigger source #0 1 Falling edge Enabled when EADC selects EADC0_ST as trigger source #1 EXTREN EADC External Trigger Rising Edge Enable Bit 21 1 read-write 0 Rising edge Disabled when EADC selects EADC0_ST as trigger source #0 1 Rising edge Enabled when EADC selects EADC0_ST as trigger source #1 EXTSMPT EADC Sampling Time Extend When EADC is converting at high conversion rate, the sampling time of analog input voltage may not be enough if input channel loading is heavy, and software can extend EADC sampling time after trigger source is coming to get enough sampling time. The range of start delay time is from 0~255 EADC clock. 24 8 read-write INTPOS Interrupt Flag Position Select 5 1 read-write 0 Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC end of conversion #0 1 Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC start of conversion #1 TRGDLYCNT EADC Sample Module Start of Conversion Trigger Delay Time 8 8 read-write TRGDLYDIV EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection Trigger delay clock frequency: 6 2 read-write 0 EADC_CLK/1 #00 1 EADC_CLK/2 #01 2 EADC_CLK/4 #10 3 EADC_CLK/16 #11 TRGSEL EADC Sample Module Start of Conversion Trigger Source Selection 16 5 read-write SCTL2 EADC_SCTL2 EADC Sample Module 2 Control Register 0x88 -1 read-write n 0x0 0x0 SCTL20 EADC_SCTL20 EADC Sample Module 20 Control Register 0x224 -1 read-write n 0x0 0x0 SCTL21 EADC_SCTL21 EADC Sample Module 21 Control Register 0x228 -1 read-write n 0x0 0x0 SCTL22 EADC_SCTL22 EADC Sample Module 22 Control Register 0x22C -1 read-write n 0x0 0x0 SCTL23 EADC_SCTL23 EADC Sample Module 23 Control Register 0x230 -1 read-write n 0x0 0x0 SCTL24 EADC_SCTL24 EADC Sample Module 24 Control Register 0x234 -1 read-write n 0x0 0x0 EXTSMPT EADC Sampling Time Extend When EADC is converting at high conversion rate, the sampling time of analog input voltage may not be enough if input channel loading is heavy, and software can extend EADC sampling time after trigger source is coming to get enough sampling time. The range of start delay time is from 0~255 EADC clock. 24 8 read-write SCTL25 EADC_SCTL25 EADC Sample Module 25 Control Register 0x238 -1 read-write n 0x0 0x0 SCTL26 EADC_SCTL26 EADC Sample Module 26 Control Register 0x23C -1 read-write n 0x0 0x0 SCTL3 EADC_SCTL3 EADC Sample Module 3 Control Register 0x8C -1 read-write n 0x0 0x0 SCTL4 EADC_SCTL4 EADC Sample Module 4 Control Register 0x90 -1 read-write n 0x0 0x0 CHSEL EADC Sample Module Channel Selection 0 5 read-write EXTFEN EADC External Trigger Falling Edge Enable Bit 22 1 read-write 0 Falling edge Disabled when EADC selects EADC0_ST as trigger source #0 1 Falling edge Enabled when EADC selects EADC0_ST as trigger source #1 EXTREN EADC External Trigger Rising Edge Enable Bit 21 1 read-write 0 Rising edge Disabled when EADC selects EADC0_ST as trigger source #0 1 Rising edge Enabled when EADC selects EADC0_ST as trigger source #1 EXTSMPT EADC Sampling Time Extend When EADC is converting at high conversion rate, the sampling time of analog input voltage may not be enough if input channel loading is heavy, and software can extend EADC sampling time after trigger source is coming to get enough sampling time. The range of start delay time is from 0~255 EADC clock. 24 8 read-write INTPOS Interrupt Flag Position Select 5 1 read-write 0 Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC end of conversion #0 1 Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC start of conversion #1 TRGDLYCNT EADC Sample Module Start of Conversion Trigger Delay Time 8 8 read-write TRGDLYDIV EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection Trigger delay clock frequency: 6 2 read-write 0 EADC_CLK/1 #00 1 EADC_CLK/2 #01 2 EADC_CLK/4 #10 3 EADC_CLK/16 #11 TRGSEL EADC Sample Module Start of Conversion Trigger Source Selection 16 5 read-write SCTL5 EADC_SCTL5 EADC Sample Module 5 Control Register 0x94 -1 read-write n 0x0 0x0 SCTL6 EADC_SCTL6 EADC Sample Module 6 Control Register 0x98 -1 read-write n 0x0 0x0 SCTL7 EADC_SCTL7 EADC Sample Module 7 Control Register 0x9C -1 read-write n 0x0 0x0 SCTL8 EADC_SCTL8 EADC Sample Module 8 Control Register 0xA0 -1 read-write n 0x0 0x0 SCTL9 EADC_SCTL9 EADC Sample Module 9 Control Register 0xA4 -1 read-write n 0x0 0x0 STATUS0 EADC_STATUS0 EADC Status Register 0 0xF0 -1 read-only n 0x0 0x0 OV EADC_DAT0~15 Overrun Flag 16 16 read-only VALID EADC_DAT0~15 Data Valid Flag 0 16 read-only STATUS1 EADC_STATUS1 EADC Status Register 1 0xF4 -1 read-only n 0x0 0x0 OV EADC_DAT16~26 Overrun Flag 16 11 read-only VALID EADC_DAT16~26 Data Valid Flag 0 11 read-only STATUS2 EADC_STATUS2 EADC Status Register 2 0xF8 -1 read-write n 0x0 0x0 ADCMPF0 EADC Compare 0 Flag When the specific sample module EADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. Note: This bit is cleared by writing 1 to it. 4 1 read-write 0 Conversion result in EADC_DAT does not meet EADC_CMP0 register setting #0 1 Conversion result in EADC_DAT meets EADC_CMP0 register setting #1 ADCMPF1 EADC Compare 1 Flag When the specific sample module EADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1. Note: This bit is cleared by writing 1 to it. 5 1 read-write 0 Conversion result in EADC_DAT does not meet EADC_CMP1 register setting #0 1 Conversion result in EADC_DAT meets EADC_CMP1 register setting #1 ADCMPF2 EADC Compare 2 Flag When the specific sample module EADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1. Note: This bit is cleared by writing 1 to it. 6 1 read-write 0 Conversion result in EADC_DAT does not meet EADC_CMP2 register setting #0 1 Conversion result in EADC_DAT meets EADC_CMP2 register setting #1 ADCMPF3 EADC Compare 3 Flag When the specific sample module EADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1. Note: This bit is cleared by writing 1 to it. 7 1 read-write 0 Conversion result in EADC_DAT does not meet EADC_CMP3 register setting #0 1 Conversion result in EADC_DAT meets EADC_CMP3 register setting #1 ADCMPO0 EADC Compare 0 Output Status (Read Only) The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status. 12 1 read-only 0 Conversion result in EADC_DAT less than CMPDAT0 setting #0 1 Conversion result in EADC_DAT great than or equal CMPDAT0 setting #1 ADCMPO1 EADC Compare 1 Output Status (Read Only) The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status. 13 1 read-only 0 Conversion result in EADC_DAT less than CMPDAT1 setting #0 1 Conversion result in EADC_DAT great than or equal to CMPDAT1 setting #1 ADCMPO2 EADC Compare 2 Output Status (Read Only) The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status. 14 1 read-only 0 Conversion result in EADC_DAT less than CMPDAT2 setting #0 1 Conversion result in EADC_DAT great than or equal to CMPDAT2 setting #1 ADCMPO3 EADC Compare 3 Output Status (Read Only) The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status. 15 1 read-only 0 Conversion result in EADC_DAT less than CMPDAT3 setting #0 1 Conversion result in EADC_DAT great than or equal to CMPDAT3 setting #1 ADIF0 EADC ADINT0 Interrupt Flag Note 1: This bit is cleared by writing 1 to it. Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed 0 1 read-write 0 No ADINT0 interrupt pulse received #0 1 ADINT0 interrupt pulse has been received #1 ADIF1 EADC ADINT1 Interrupt Flag Note 1: This bit is cleared by writing 1 to it. Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed 1 1 read-write 0 No ADINT1 interrupt pulse received #0 1 ADINT1 interrupt pulse has been received #1 ADIF2 EADC ADINT2 Interrupt Flag Note 1: This bit is cleared by writing 1 to it. Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed 2 1 read-write 0 No ADINT2 interrupt pulse received #0 1 ADINT2 interrupt pulse has been received #1 ADIF3 EADC ADINT3 Interrupt Flag Note 1: This bit is cleared by writing 1 to it. Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed 3 1 read-write 0 No ADINT3 interrupt pulse received #0 1 ADINT3 interrupt pulse has been received #1 ADOVIF All EADC Interrupt Flag Overrun Bits Check (Read Only) Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1. 24 1 read-only 0 None of ADINT interrupt flag ADOVIFn, n=0~3 is overwritten to 1 #0 1 Any one of ADINT interrupt flag ADOVIFn, n=0~3 is overwritten to 1 #1 ADOVIF0 EADC ADINT0 Interrupt Flag Overrun Note: This bit is cleared by writing 1 to it. 8 1 read-write 0 ADINT0 interrupt flag is not overwritten to 1 #0 1 ADINT0 interrupt flag is overwritten to 1 #1 ADOVIF1 EADC ADINT1 Interrupt Flag Overrun Note: This bit is cleared by writing 1 to it. 9 1 read-write 0 ADINT1 interrupt flag is not overwritten to 1 #0 1 ADINT1 interrupt flag is overwritten to 1 #1 ADOVIF2 EADC ADINT2 Interrupt Flag Overrun Note: This bit is cleared by writing 1 to it. 10 1 read-write 0 ADINT2 interrupt flag is not overwritten to 1 #0 1 ADINT2 interrupt flag is s overwritten to 1 #1 ADOVIF3 EADC ADINT3 Interrupt Flag Overrun Note: This bit is cleared by writing 1 to it. 11 1 read-write 0 ADINT3 interrupt flag is not overwritten to 1 #0 1 ADINT3 interrupt flag is overwritten to 1 #1 AOV for All Sample Module EADC Result Data Register Overrun Flags Check (Read Only) Note: This bit will keep 1 when any OVn Flag is equal to 1. 27 1 read-only 0 None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1 #0 1 Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1 #1 AVALID for All Sample Module EADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only) Note: This bit will keep 1 when any VALIDn Flag is equal to 1. 26 1 read-only 0 None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1 #0 1 Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1 #1 BUSY Busy/Idle (Read Only) Note: this flag will be high after 4*EADC_CLK cycles, when the trigger source is coming. 23 1 read-only 0 EADC is in idle state #0 1 EADC is busy at conversion #1 CHANNEL Current Conversion Channel (Read Only) 16 5 read-only STOVF for All EADC Sample Module Start of Conversion Overrun Flags Check (Read Only) Note: This bit will keep 1 when any SPOVFn Flag is equal to 1. 25 1 read-only 0 None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1 #0 1 Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1 #1 STATUS3 EADC_STATUS3 EADC Status Register 3 0xFC -1 read-only n 0x0 0x0 CURSPL EADC Current Sample Module (Read Only) This register shows the current EADC is controlled by which sample module control logic modules. If the EADC is Idle, the bit filed will set to 0x1F. 0 5 read-only SWTRG EADC_SWTRG EADC Sample Module Software Start Register 0x54 -1 write-only n 0x0 0x0 SWTRG EADC Sample Module 0~26 Software Force to Start EADC Conversion Note: After writing this register to start EADC conversion, the EADC_PENDSTS register will show which sample module will conversion. If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. 0 27 write-only 0 No effect 0 1 Cause an EADC conversion when the priority is given to sample module 1 VREF EADC_VREF EADC Reference Voltage Control Register 0xFF8 -1 read-write n 0x0 0x0 REFSEL Positive Reference Voltage Source Selection 1 1 read-write 0 Positive Reference Voltage Source from AVDD #0 1 Positive Reference Voltage Source from VREFP #1 EPWM0 EPWM Register Map EPWM 0x0 0x0 0x2C registers n 0x110 0x14 registers n 0x130 0x18 registers n 0x150 0xC registers n 0x160 0x38 registers n 0x200 0x4C registers n 0x250 0x74 registers n 0x30 0x18 registers n 0x304 0x7C registers n 0x50 0x18 registers n 0x70 0xC registers n 0x80 0xC registers n 0x90 0x18 registers n 0xB0 0x40 registers n 0xF4 0x18 registers n EPWM_AINTEN EPWM_AINTEN EPWM Accumulator Interrupt Enable Register 0x154 -1 read-write n 0x0 0x0 IFAIEN0 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 0 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN1 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN2 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 2 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN3 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 3 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN4 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 4 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN5 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 5 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 EPWM_AINTSTS EPWM_AINTSTS EPWM Accumulator Interrupt Flag Register 0x150 -1 read-write n 0x0 0x0 IFAIF0 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 0 1 read-write IFAIF1 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1 1 read-write IFAIF2 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 2 1 read-write IFAIF3 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 3 1 read-write IFAIF4 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 4 1 read-write IFAIF5 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 5 1 read-write EPWM_APDMACTL EPWM_APDMACTL EPWM Accumulator PDMA Control Register 0x158 -1 read-write n 0x0 0x0 APDMAEN0 Channel n Accumulator PDMA Enable Bits 0 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN1 Channel n Accumulator PDMA Enable Bits 1 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN2 Channel n Accumulator PDMA Enable Bits 2 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN3 Channel n Accumulator PDMA Enable Bits 3 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN4 Channel n Accumulator PDMA Enable Bits 4 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN5 Channel n Accumulator PDMA Enable Bits 5 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 EPWM_BNF EPWM_BNF EPWM Brake Noise Filter Register 0xC0 -1 read-write n 0x0 0x0 BK0SRC Brake 0 Pin Source Select For EPWM0 setting: 16 1 read-write 0 Brake 0 pin source come from EPWM0_BRAKE0. Brake 0 pin source come from EPWM1_BRAKE0 #0 1 Brake 0 pin source come from EPWM1_BRAKE0. Brake 0 pin source come from EPWM0_BRAKE0 #1 BK1SRC Brake 1 Pin Source Select For EPWM0 setting: 24 1 read-write 0 Brake 1 pin source come from EPWM0_BRAKE1. Brake 1 pin source come from EPWM1_BRAKE1 #0 1 Brake 1 pin source come from EPWM1_BRAKE1. Brake 1 pin source come from EPWM0_BRAKE1 #1 BRK0FCNT Brake 0 Edge Detector Filter Count The register bits control the Brake0 filter counter to count from 0 to BRK0FCNT. 4 3 read-write BRK0NFEN EPWM Brake 0 Noise Filter Enable Bit 0 1 read-write 0 Noise filter of EPWM Brake 0 Disabled #0 1 Noise filter of EPWM Brake 0 Enabled #1 BRK0NFSEL Brake 0 Edge Detector Filter Clock Selection 1 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK0PINV Brake 0 Pin Inverse 7 1 read-write 0 brake pin event will be detected if EPWMx_BRAKE0 pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 brake pin event will be detected if EPWMx_BRAKE0 pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 BRK1FCNT Brake 1 Edge Detector Filter Count The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 12 3 read-write BRK1NFEN EPWM Brake 1 Noise Filter Enable Bit 8 1 read-write 0 Noise filter of EPWM Brake 1 Disabled #0 1 Noise filter of EPWM Brake 1 Enabled #1 BRK1NFSEL Brake 1 Edge Detector Filter Clock Selection 9 3 read-write 0 Filter clock = PCLK #000 1 Filter clock = PCLK/2 #001 2 Filter clock = PCLK/4 #010 3 Filter clock = PCLK/8 #011 4 Filter clock = PCLK/16 #100 5 Filter clock = PCLK/32 #101 6 Filter clock = PCLK/64 #110 7 Filter clock = PCLK/128 #111 BRK1PINV Brake 1 Pin Inverse 15 1 read-write 0 brake pin event will be detected if EPWMx_BRAKE1 pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 brake pin event will be detected if EPWMx_BRAKE1 pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 EPWM_BRKCTL0_1 EPWM_BRKCTL0_1 EPWM Brake Edge Detect Control Register 0/1 0xC8 -1 read-write n 0x0 0x0 BRKAEVEN EPWM Brake Action Select for Even Channel (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 16 2 read-write 0 EPWMx brake event will not affect even channels output #00 1 EPWM even channel output tri-state when EPWMx brake event happened #01 2 EPWM even channel output low level when EPWMx brake event happened #10 3 EPWM even channel output high level when EPWMx brake event happened #11 BRKAODD EPWM Brake Action Select for Odd Channel (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 18 2 read-write 0 EPWMx brake event will not affect odd channels output #00 1 EPWM odd channel output tri-state when EPWMx brake event happened #01 2 EPWM odd channel output low level when EPWMx brake event happened #10 3 EPWM odd channel output high level when EPWMx brake event happened #11 BRKP0EEN Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 4 1 read-write 0 EPWMx_BRAKE0 pin as edge-detect brake source Disabled #0 1 EPWMx_BRAKE0 pin as edge-detect brake source Enabled #1 BRKP0LEN Enable BKP0 Pin As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 12 1 read-write 0 EPWMx_BRAKE0 pin as level-detect brake source Disabled #0 1 EPWMx_BRAKE0 pin as level-detect brake source Enabled #1 BRKP1EEN Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 5 1 read-write 0 EPWMx_BRAKE1 pin as edge-detect brake source Disabled #0 1 EPWMx_BRAKE1 pin as edge-detect brake source Enabled #1 BRKP1LEN Enable BKP1 Pin As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 13 1 read-write 0 EPWMx_BRAKE1 pin as level-detect brake source Disabled #0 1 EPWMx_BRAKE1 pin as level-detect brake source Enabled #1 CPO0EBEN Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 0 1 read-write 0 ACMP0_O as edge-detect brake source Disabled #0 1 ACMP0_O as edge-detect brake source Enabled #1 CPO0LBEN Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 8 1 read-write 0 ACMP0_O as level-detect brake source Disabled #0 1 ACMP0_O as level-detect brake source Enabled #1 CPO1EBEN Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 1 1 read-write 0 ACMP1_O as edge-detect brake source Disabled #0 1 ACMP1_O as edge-detect brake source Enabled #1 CPO1LBEN Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 9 1 read-write 0 ACMP1_O as level-detect brake source Disabled #0 1 ACMP1_O as level-detect brake source Enabled #1 EADC0EBEN Enable EADC0 Result Monitor (EADC0RM) As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 20 1 read-write 0 EADC0RM as edge-detect brake source Disabled #0 1 EADC0RM as edge-detect brake source Enabled #1 EADC0LBEN Enable EADC0 Result Monitor (EADC0RM) As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 28 1 read-write 0 EADC0RM as level-detect brake source Disabled #0 1 EADC0RM as level-detect brake source Enabled #1 SYSEBEN Enable System Fail As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 7 1 read-write 0 System Fail condition as edge-detect brake source Disabled #0 1 System Fail condition as edge-detect brake source Enabled #1 SYSLBEN Enable System Fail As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 15 1 read-write 0 System Fail condition as level-detect brake source Disabled #0 1 System Fail condition as level-detect brake source Enabled #1 EPWM_BRKCTL2_3 EPWM_BRKCTL2_3 EPWM Brake Edge Detect Control Register 2/3 0xCC -1 read-write n 0x0 0x0 EPWM_BRKCTL4_5 EPWM_BRKCTL4_5 EPWM Brake Edge Detect Control Register 4/5 0xD0 -1 read-write n 0x0 0x0 EPWM_CAPCTL EPWM_CAPCTL EPWM Capture Control Register 0x204 -1 read-write n 0x0 0x0 CAPEN0 Capture Function Enable Bits 0 1 read-write 0 Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN1 Capture Function Enable Bits 1 1 read-write 0 Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN2 Capture Function Enable Bits 2 1 read-write 0 Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN3 Capture Function Enable Bits 3 1 read-write 0 Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN4 Capture Function Enable Bits 4 1 read-write 0 Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN5 Capture Function Enable Bits 5 1 read-write 0 Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPINV0 Capture Inverter Enable Bits 8 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV1 Capture Inverter Enable Bits 9 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV2 Capture Inverter Enable Bits 10 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV3 Capture Inverter Enable Bits 11 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV4 Capture Inverter Enable Bits 12 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV5 Capture Inverter Enable Bits 13 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 FCRLDEN0 Falling Capture Reload Enable Bits 24 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN1 Falling Capture Reload Enable Bits 25 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN2 Falling Capture Reload Enable Bits 26 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN3 Falling Capture Reload Enable Bits 27 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN4 Falling Capture Reload Enable Bits 28 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN5 Falling Capture Reload Enable Bits 29 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 RCRLDEN0 Rising Capture Reload Enable Bits 16 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN1 Rising Capture Reload Enable Bits 17 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN2 Rising Capture Reload Enable Bits 18 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN3 Rising Capture Reload Enable Bits 19 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN4 Rising Capture Reload Enable Bits 20 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN5 Rising Capture Reload Enable Bits 21 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 EPWM_CAPIEN EPWM_CAPIEN EPWM Capture Interrupt Enable Register 0x250 -1 read-write n 0x0 0x0 CAPFIEN0 EPWM Capture Falling Latch Interrupt Enable Bits 8 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN1 EPWM Capture Falling Latch Interrupt Enable Bits 9 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN2 EPWM Capture Falling Latch Interrupt Enable Bits 10 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN3 EPWM Capture Falling Latch Interrupt Enable Bits 11 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN4 EPWM Capture Falling Latch Interrupt Enable Bits 12 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN5 EPWM Capture Falling Latch Interrupt Enable Bits 13 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPRIEN0 EPWM Capture Rising Latch Interrupt Enable Bits 0 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN1 EPWM Capture Rising Latch Interrupt Enable Bits 1 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN2 EPWM Capture Rising Latch Interrupt Enable Bits 2 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN3 EPWM Capture Rising Latch Interrupt Enable Bits 3 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN4 EPWM Capture Rising Latch Interrupt Enable Bits 4 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN5 EPWM Capture Rising Latch Interrupt Enable Bits 5 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 EPWM_CAPIF EPWM_CAPIF EPWM Capture Interrupt Flag Register 0x254 -1 read-write n 0x0 0x0 CFLIF0 EPWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 8 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF1 EPWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 9 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF2 EPWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 10 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF3 EPWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 11 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF4 EPWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 12 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF5 EPWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 13 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CRLIF0 EPWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 0 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF1 EPWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 1 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF2 EPWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 2 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF3 EPWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 3 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF4 EPWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 4 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF5 EPWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 5 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 EPWM_CAPINEN EPWM_CAPINEN EPWM Capture Input Enable Register 0x200 -1 read-write n 0x0 0x0 CAPINEN0 Capture Input Enable Bits 0 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN1 Capture Input Enable Bits 1 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN2 Capture Input Enable Bits 2 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN3 Capture Input Enable Bits 3 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN4 Capture Input Enable Bits 4 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN5 Capture Input Enable Bits 5 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 EPWM_CAPNF0 EPWM_CAPNF0 EPWM Capture Input Noise Filter Register 0 0x258 -1 read-write n 0x0 0x0 CAPNFCNT Capture Edge Detector Noise Filter Count The register bits control the capture filter counter to count from 0 to CAPNFCNT. 8 3 read-write CAPNFEN Capture Noise Filter Enable 0 1 read-write 0 Capture Noise Filter function Disabled #0 1 Capture Noise Filter function Enabled #1 CAPNFSEL Capture Edge Detector Noise Filter Clock Selection 4 3 read-write 0 Filter clock = PCLK #000 1 Filter clock = PCLK/2 #001 2 Filter clock = PCLK/4 #010 3 Filter clock = PCLK/8 #011 4 Filter clock = PCLK/16 #100 5 Filter clock = PCLK/32 #101 6 Filter clock = PCLK/64 #110 7 Filter clock = PCLK/128 #111 EPWM_CAPNF1 EPWM_CAPNF1 EPWM Capture Input Noise Filter Register 1 0x25C -1 read-write n 0x0 0x0 EPWM_CAPNF2 EPWM_CAPNF2 EPWM Capture Input Noise Filter Register 2 0x260 -1 read-write n 0x0 0x0 EPWM_CAPNF3 EPWM_CAPNF3 EPWM Capture Input Noise Filter Register 3 0x264 -1 read-write n 0x0 0x0 EPWM_CAPNF4 EPWM_CAPNF4 EPWM Capture Input Noise Filter Register 4 0x268 -1 read-write n 0x0 0x0 EPWM_CAPNF5 EPWM_CAPNF5 EPWM Capture Input Noise Filter Register 5 0x26C -1 read-write n 0x0 0x0 EPWM_CAPSTS EPWM_CAPSTS EPWM Capture Status Register 0x208 -1 read-only n 0x0 0x0 CFLIFOV0 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]). 8 1 read-only CFLIFOV1 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]). 9 1 read-only CFLIFOV2 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]). 10 1 read-only CFLIFOV3 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]). 11 1 read-only CFLIFOV4 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]). 12 1 read-only CFLIFOV5 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]). 13 1 read-only CRLIFOV0 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]). 0 1 read-only CRLIFOV1 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]). 1 1 read-only CRLIFOV2 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]). 2 1 read-only CRLIFOV3 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]). 3 1 read-only CRLIFOV4 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]). 4 1 read-only CRLIFOV5 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]). 5 1 read-only EPWM_CLKPSC0 EPWM_CLKPSC0 EPWM Clock Prescale Register 0 0x290 -1 read-write n 0x0 0x0 CLKPSC EPWM Counter Clock Prescale The clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1). 0 12 read-write EPWM_CLKPSC0_1 EPWM_CLKPSC0_1 EPWM Clock Prescale Register 0/1 0x14 -1 read-write n 0x0 0x0 CLKPSC EPWM Counter Clock Prescale The clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1). 0 12 read-write EPWM_CLKPSC1 EPWM_CLKPSC1 EPWM Clock Prescale Register 1 0x294 -1 read-write n 0x0 0x0 EPWM_CLKPSC2 EPWM_CLKPSC2 EPWM Clock Prescale Register 2 0x298 -1 read-write n 0x0 0x0 EPWM_CLKPSC2_3 EPWM_CLKPSC2_3 EPWM Clock Prescale Register 2/3 0x18 -1 read-write n 0x0 0x0 EPWM_CLKPSC3 EPWM_CLKPSC3 EPWM Clock Prescale Register 3 0x29C -1 read-write n 0x0 0x0 EPWM_CLKPSC4 EPWM_CLKPSC4 EPWM Clock Prescale Register 4 0x2A0 -1 read-write n 0x0 0x0 EPWM_CLKPSC4_5 EPWM_CLKPSC4_5 EPWM Clock Prescale Register 4/5 0x1C -1 read-write n 0x0 0x0 EPWM_CLKPSC5 EPWM_CLKPSC5 EPWM Clock Prescale Register 5 0x2A4 -1 read-write n 0x0 0x0 EPWM_CLKSRC EPWM_CLKSRC EPWM Clock Source Register 0x10 -1 read-write n 0x0 0x0 ECLKSRC0 EPWM_CH01 External Clock Source Select 0 3 read-write 0 EPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC2 EPWM_CH23 External Clock Source Select 8 3 read-write 0 EPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC4 EPWM_CH45 External Clock Source Select 16 3 read-write 0 EPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 EPWM_CMPBUF0 EPWM_CMPBUF0 EPWM CMPDAT0 Buffer 0x31C -1 read-only n 0x0 0x0 CMPBUF EPWM Comparator Register Buffer (Read Only) Used as CMP active register. 0 16 read-only EPWM_CMPBUF1 EPWM_CMPBUF1 EPWM CMPDAT1 Buffer 0x320 -1 read-write n 0x0 0x0 EPWM_CMPBUF2 EPWM_CMPBUF2 EPWM CMPDAT2 Buffer 0x324 -1 read-write n 0x0 0x0 EPWM_CMPBUF3 EPWM_CMPBUF3 EPWM CMPDAT3 Buffer 0x328 -1 read-write n 0x0 0x0 EPWM_CMPBUF4 EPWM_CMPBUF4 EPWM CMPDAT4 Buffer 0x32C -1 read-write n 0x0 0x0 EPWM_CMPBUF5 EPWM_CMPBUF5 EPWM CMPDAT5 Buffer 0x330 -1 read-write n 0x0 0x0 EPWM_CMPDAT0 EPWM_CMPDAT0 EPWM Comparator Register 0 0x50 -1 read-write n 0x0 0x0 CMP EPWM Comparator Register CMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform, interrupt and trigger EADC/DAC. In complementary mode, EPWM_CMPDAT0, EPWM_CMPDAT2, EPWM_CMPDAT4 denote as first compared point, and EPWM_CMPDAT1, EPWM_CMPDAT3, EPWM_CMPDAT5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. 0 16 read-write EPWM_CMPDAT1 EPWM_CMPDAT1 EPWM Comparator Register 1 0x54 -1 read-write n 0x0 0x0 EPWM_CMPDAT2 EPWM_CMPDAT2 EPWM Comparator Register 2 0x58 -1 read-write n 0x0 0x0 EPWM_CMPDAT3 EPWM_CMPDAT3 EPWM Comparator Register 3 0x5C -1 read-write n 0x0 0x0 EPWM_CMPDAT4 EPWM_CMPDAT4 EPWM Comparator Register 4 0x60 -1 read-write n 0x0 0x0 EPWM_CMPDAT5 EPWM_CMPDAT5 EPWM Comparator Register 5 0x64 -1 read-write n 0x0 0x0 EPWM_CNT0 EPWM_CNT0 EPWM Counter Register 0 0x90 -1 read-only n 0x0 0x0 CNT EPWM Data Register (Read Only) User can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF EPWM Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is counting down #0 1 Counter is counting up #1 EPWM_CNT1 EPWM_CNT1 EPWM Counter Register 1 0x94 -1 read-write n 0x0 0x0 EPWM_CNT2 EPWM_CNT2 EPWM Counter Register 2 0x98 -1 read-write n 0x0 0x0 EPWM_CNT3 EPWM_CNT3 EPWM Counter Register 3 0x9C -1 read-write n 0x0 0x0 EPWM_CNT4 EPWM_CNT4 EPWM Counter Register 4 0xA0 -1 read-write n 0x0 0x0 EPWM_CNT5 EPWM_CNT5 EPWM Counter Register 5 0xA4 -1 read-write n 0x0 0x0 EPWM_CNTCLR EPWM_CNTCLR EPWM Clear Counter Register 0x24 -1 read-write n 0x0 0x0 CNTCLR0 Clear EPWM Counter Control Bit It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 0 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR1 Clear EPWM Counter Control Bit It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 1 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR2 Clear EPWM Counter Control Bit It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 2 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR3 Clear EPWM Counter Control Bit It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 3 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR4 Clear EPWM Counter Control Bit It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 4 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR5 Clear EPWM Counter Control Bit It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 5 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 EPWM_CNTEN EPWM_CNTEN EPWM Counter Enable Register 0x20 -1 read-write n 0x0 0x0 CNTEN0 EPWM Counter Enable Bits Note: In complementary mode, not only even channels, but also odd channels need to be enabled at the same time. 0 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN1 EPWM Counter Enable Bits Note: In complementary mode, not only even channels, but also odd channels need to be enabled at the same time. 1 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN2 EPWM Counter Enable Bits Note: In complementary mode, not only even channels, but also odd channels need to be enabled at the same time. 2 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN3 EPWM Counter Enable Bits Note: In complementary mode, not only even channels, but also odd channels need to be enabled at the same time. 3 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN4 EPWM Counter Enable Bits Note: In complementary mode, not only even channels, but also odd channels need to be enabled at the same time. 4 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN5 EPWM Counter Enable Bits Note: In complementary mode, not only even channels, but also odd channels need to be enabled at the same time. 5 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 EPWM_CPSCBUF0 EPWM_CPSCBUF0 EPWM CLKPSC0 Buffer 0x350 -1 read-only n 0x0 0x0 CPSCBUF EPWM Counter Clock Prescale Buffer Used as EPWM counter clock pre-scale active register. 0 12 read-only EPWM_CPSCBUF0_1 EPWM_CPSCBUF0_1 EPWM CLKPSC0_1 Buffer 0x334 -1 read-only n 0x0 0x0 CPSCBUF EPWM Counter Clock Prescale Buffer Used as EPWM counter clock pre-scale active register. 0 12 read-only EPWM_CPSCBUF1 EPWM_CPSCBUF1 EPWM CLKPSC1 Buffer 0x354 -1 read-write n 0x0 0x0 EPWM_CPSCBUF2 EPWM_CPSCBUF2 EPWM CLKPSC2 Buffer 0x358 -1 read-write n 0x0 0x0 EPWM_CPSCBUF2_3 EPWM_CPSCBUF2_3 EPWM CLKPSC2_3 Buffer 0x338 -1 read-write n 0x0 0x0 EPWM_CPSCBUF3 EPWM_CPSCBUF3 EPWM CLKPSC3 Buffer 0x35C -1 read-write n 0x0 0x0 EPWM_CPSCBUF4 EPWM_CPSCBUF4 EPWM CLKPSC4 Buffer 0x360 -1 read-write n 0x0 0x0 EPWM_CPSCBUF4_5 EPWM_CPSCBUF4_5 EPWM CLKPSC4_5 Buffer 0x33C -1 read-write n 0x0 0x0 EPWM_CPSCBUF5 EPWM_CPSCBUF5 EPWM CLKPSC5 Buffer 0x364 -1 read-write n 0x0 0x0 EPWM_CTL0 EPWM_CTL0 EPWM Control Register 0 0x0 -1 read-write n 0x0 0x0 CTRLD0 Center Re-load In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period. 0 1 read-write CTRLD1 Center Re-load In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period. 1 1 read-write CTRLD2 Center Re-load In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period. 2 1 read-write CTRLD3 Center Re-load In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period. 3 1 read-write CTRLD4 Center Re-load In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period. 4 1 read-write CTRLD5 Center Re-load In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period. 5 1 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect) If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode. Note: This bit is write protected. Refer toSYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable Bit (Write Protect) EPWM pin will keep output no matter ICE debug mode acknowledged or not. Note: This bit is write protected. Refer toSYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects EPWM output #0 1 ICE debug mode acknowledgement disabled #1 GROUPEN Group Function Enable Bit 24 1 read-write 0 The output waveform of each EPWM channel are independent #0 1 Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1 #1 IMMLDEN0 Immediately Load Enable Bits Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 16 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP #1 IMMLDEN1 Immediately Load Enable Bits Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 17 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP #1 IMMLDEN2 Immediately Load Enable Bits Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 18 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP #1 IMMLDEN3 Immediately Load Enable Bits Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 19 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP #1 IMMLDEN4 Immediately Load Enable Bits Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 20 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP #1 IMMLDEN5 Immediately Load Enable Bits Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 21 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP #1 WINLDEN0 Window Load Enable Bits 8 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN1 Window Load Enable Bits 9 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN2 Window Load Enable Bits 10 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN3 Window Load Enable Bits 11 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN4 Window Load Enable Bits 12 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN5 Window Load Enable Bits 13 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 EPWM_CTL1 EPWM_CTL1 EPWM Control Register 1 0x4 -1 read-write n 0x0 0x0 CNTMODE0 EPWM Counter Mode 16 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE1 EPWM Counter Mode 17 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE2 EPWM Counter Mode 18 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE3 EPWM Counter Mode 19 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE4 EPWM Counter Mode 20 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE5 EPWM Counter Mode 21 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTTYPE0 EPWM Counter Behavior Type 0 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE1 EPWM Counter Behavior Type 2 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE2 EPWM Counter Behavior Type 4 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE3 EPWM Counter Behavior Type 6 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE4 EPWM Counter Behavior Type 8 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE5 EPWM Counter Behavior Type 10 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 OUTMODE0 EPWM Output Mode Each bit n controls the output mode of corresponding EPWM channel n. Note: When operating in group function, these bits must all set to the same mode. 24 1 read-write 0 EPWM independent mode #0 1 EPWM complementary mode #1 OUTMODE2 EPWM Output Mode Each bit n controls the output mode of corresponding EPWM channel n. Note: When operating in group function, these bits must all set to the same mode. 25 1 read-write 0 EPWM independent mode #0 1 EPWM complementary mode #1 OUTMODE4 EPWM Output Mode Each bit n controls the output mode of corresponding EPWM channel n. Note: When operating in group function, these bits must all set to the same mode. 26 1 read-write 0 EPWM independent mode #0 1 EPWM complementary mode #1 EPWM_DACTRGEN EPWM_DACTRGEN EPWM Trigger DAC Enable Register 0xF4 -1 read-write n 0x0 0x0 CDTRGE0 EPWM Compare Down Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 24 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE1 EPWM Compare Down Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 25 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE2 EPWM Compare Down Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 26 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE3 EPWM Compare Down Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 27 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE4 EPWM Compare Down Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 28 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE5 EPWM Compare Down Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 29 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CUTRGE0 EPWM Compare Up Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 16 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE1 EPWM Compare Up Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 17 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE2 EPWM Compare Up Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 18 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE3 EPWM Compare Up Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 19 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE4 EPWM Compare Up Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 20 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE5 EPWM Compare Up Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 21 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 PTE0 EPWM Period Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 8 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE1 EPWM Period Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 9 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE2 EPWM Period Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 10 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE3 EPWM Period Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 11 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE4 EPWM Period Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 12 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE5 EPWM Period Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 13 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE0 EPWM Zero Point Trigger DAC Enable Bits EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 0 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE1 EPWM Zero Point Trigger DAC Enable Bits EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE2 EPWM Zero Point Trigger DAC Enable Bits EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 2 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE3 EPWM Zero Point Trigger DAC Enable Bits EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 3 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE4 EPWM Zero Point Trigger DAC Enable Bits EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 4 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE5 EPWM Zero Point Trigger DAC Enable Bits EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 5 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 EPWM_DTCTL EPWM_DTCTL EPWM Dead-time Control Register 0x2C0 -1 read-write n 0x0 0x0 DTCKSELn Dead-time Clock Select for EPWM Pair (EPWM_CH(n/2), EPWM_CH(n/2+1)) (Write Protect) Note: This bit is write protected. Refer to REGWRPROT register. 16 1 read-write 0 Dead-time clock source from EPWM_CLK #0 1 Dead-time clock source from prescaler output #1 FDTEN0 Enable Falling Dead-time Insertion for EPWM Pair (EPWM_CH(n/2), EPWM_CH(n/2+1)) (Write Protect) Falling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. Note: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 Falling Dead-time insertion Disabled on the pin pair #0 1 Falling Dead-time insertion Enabled on the pin pair #1 FDTEN2 Enable Falling Dead-time Insertion for EPWM Pair (EPWM_CH(n/2), EPWM_CH(n/2+1)) (Write Protect) Falling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. Note: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 Falling Dead-time insertion Disabled on the pin pair #0 1 Falling Dead-time insertion Enabled on the pin pair #1 FDTEN4 Enable Falling Dead-time Insertion for EPWM Pair (EPWM_CH(n/2), EPWM_CH(n/2+1)) (Write Protect) Falling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. Note: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 Falling Dead-time insertion Disabled on the pin pair #0 1 Falling Dead-time insertion Enabled on the pin pair #1 RDTEN0 Enable Rising Dead-time Insertion for EPWM Pair (EPWM_CH(n/2), EPWM_CH(n/2+1)) (Write Protect) Rising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. Note: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 Rising Dead-time insertion Disabled on the pin pair #0 1 Rising Dead-time insertion Enabled on the pin pair #1 RDTEN2 Enable Rising Dead-time Insertion for EPWM Pair (EPWM_CH(n/2), EPWM_CH(n/2+1)) (Write Protect) Rising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. Note: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 Rising Dead-time insertion Disabled on the pin pair #0 1 Rising Dead-time insertion Enabled on the pin pair #1 RDTEN4 Enable Rising Dead-time Insertion for EPWM Pair (EPWM_CH(n/2), EPWM_CH(n/2+1)) (Write Protect) Rising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. Note: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 Rising Dead-time insertion Disabled on the pin pair #0 1 Rising Dead-time insertion Enabled on the pin pair #1 EPWM_DTCTL0_1 EPWM_DTCTL0_1 EPWM Dead-time Control Register 0/1 0x70 -1 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect) Note: This bit is write protected. Refer to REGWRPROT register. 24 1 read-write 0 Dead-time clock source from EPWM_CLK #0 1 Dead-time clock source from prescaler output #1 DTCNT Dead-time Counter (Write Protect) The dead-time can be calculated from the following formula: Note: This bit is write protected. Refer to SYS_REGLCTL register. 0 12 read-write DTEN Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect) Dead-time insertion is only active when this pair of complementary EPWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. Note: This bit is write protected. Refer to SYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 EPWM_DTCTL2_3 EPWM_DTCTL2_3 EPWM Dead-time Control Register 2/3 0x74 -1 read-write n 0x0 0x0 EPWM_DTCTL4_5 EPWM_DTCTL4_5 EPWM Dead-time Control Register 4/5 0x78 -1 read-write n 0x0 0x0 EPWM_EADCPSC0 EPWM_EADCPSC0 EPWM Trigger EADC Prescale Register 0 0x188 -1 read-write n 0x0 0x0 EADCPSC0 EPWM Channel 0 Trigger EADC Prescale The register sets the count number which defines (EADCPSC0+1) times of EPWM_CH0 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF0. 0 4 read-write EADCPSC1 EPWM Channel 1 Trigger EADC Prescale The register sets the count number which defines (EADCPSC1+1) times of EPWM_CH1 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF1. 8 4 read-write EADCPSC2 EPWM Channel 2 Trigger EADC Prescale The register sets the count number which defines (EADCPSC2+1) times of EPWM_CH2 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF2. 16 4 read-write EADCPSC3 EPWM Channel 3 Trigger EADC Prescale The register sets the count number which defines (EADCPSC3+1) times of EPWM_CH3 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF3. 24 4 read-write EPWM_EADCPSC1 EPWM_EADCPSC1 EPWM Trigger EADC Prescale Register 1 0x18C -1 read-write n 0x0 0x0 EADCPSC4 EPWM Channel 4 Trigger EADC Prescale The register sets the count number which defines (EADCPSC4+1) times of EPWM_CH4 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF4. 0 4 read-write EADCPSC5 EPWM Channel 5 Trigger EADC Prescale The register sets the count number which defines (EADCPSC5+1) times of EPWM_CH5 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF5. 8 4 read-write EPWM_EADCPSCCTL EPWM_EADCPSCCTL EPWM Trigger EADC Prescale Control Register 0x184 -1 read-write n 0x0 0x0 PSCEN0 EPWM Trigger EADC Pre-scale Function Enable Bits 0 1 read-write 0 EPWM Trigger EADC Pre-scale function Disabled #0 1 EPWM Trigger EADC Pre-scale function Enabled #1 PSCEN1 EPWM Trigger EADC Pre-scale Function Enable Bits 1 1 read-write 0 EPWM Trigger EADC Pre-scale function Disabled #0 1 EPWM Trigger EADC Pre-scale function Enabled #1 PSCEN2 EPWM Trigger EADC Pre-scale Function Enable Bits 2 1 read-write 0 EPWM Trigger EADC Pre-scale function Disabled #0 1 EPWM Trigger EADC Pre-scale function Enabled #1 PSCEN3 EPWM Trigger EADC Pre-scale Function Enable Bits 3 1 read-write 0 EPWM Trigger EADC Pre-scale function Disabled #0 1 EPWM Trigger EADC Pre-scale function Enabled #1 PSCEN4 EPWM Trigger EADC Pre-scale Function Enable Bits 4 1 read-write 0 EPWM Trigger EADC Pre-scale function Disabled #0 1 EPWM Trigger EADC Pre-scale function Enabled #1 PSCEN5 EPWM Trigger EADC Pre-scale Function Enable Bits 5 1 read-write 0 EPWM Trigger EADC Pre-scale function Disabled #0 1 EPWM Trigger EADC Pre-scale function Enabled #1 EPWM_EADCPSCNT0 EPWM_EADCPSCNT0 EPWM Trigger EADC Prescale Counter Register 0 0x190 -1 read-write n 0x0 0x0 PSCNT0 EPWM Trigger EADC Prescale Counter 0 User can monitor PSCNT0 to know the current value in 4-bit trigger EADC prescale counter. Note 1: user can write only when PSCEN0 is 0. Note 2: Write data limitation: PSCNT0 EADCPSC0. 0 4 read-write PSCNT1 EPWM Trigger EADC Prescale Counter 1 User can monitor PSCNT1 to know the current value in 4-bit trigger EADC prescale counter. Note 1: user can write only when PSCEN1 is 0. Note 2: Write data limitation: PSCNT1 EADCPSC1. 8 4 read-write PSCNT2 EPWM Trigger EADC Prescale Counter 2 User can monitor PSCNT2 to know the current value in 4-bit trigger EADC prescale counter. Note 1: user can write only when PSCEN2 is 0. Note 2: Write data limitation: PSCNT2 EADCPSC2. 16 4 read-write PSCNT3 EPWM Trigger EADC Prescale Counter 3 User can monitor PSCNT3 to know the current value in 4-bit trigger EADC prescale counter. Note 1: user can write only when PSCEN3 is 0. Note 2: Write data limitation: PSCNT3 EADCPSC3. 24 4 read-write EPWM_EADCPSCNT1 EPWM_EADCPSCNT1 EPWM Trigger EADC Prescale Counter Register 1 0x194 -1 read-write n 0x0 0x0 PSCNT4 EPWM Trigger EADC Prescale Counter 4 User can monitor PSCNT4 to know the current value in 4-bit trigger EADC prescale counter. Note 1: user can write only when PSCEN4 is 0. Note 2: Write data limitation: PSCNT4 EADCPSC4. 0 4 read-write PSCNT5 EPWM Trigger EADC Prescale Counter 5 User can monitor PSCNT5 to know the current value in 4-bit trigger EADC prescale counter. Note 1: user can write only when PSCEN5 is 0. Note 2: Write data limitation: PSCNT5 EADCPSC5. 8 4 read-write EPWM_EADCTS0 EPWM_EADCTS0 EPWM Trigger EADC Source Select Register 0 0xF8 -1 read-write n 0x0 0x0 TRGEN0 EPWM_CH0 Trigger EADC Enable Bit 7 1 read-write 0 EPWM_CH0 Trigger EADC function Disabled #0 1 EPWM_CH0 Trigger EADC function Enabled #1 TRGEN1 EPWM_CH1 Trigger EADC Enable Bit 15 1 read-write 0 EPWM_CH1 Trigger EADC function Disabled #0 1 EPWM_CH1 Trigger EADC function Enabled #1 TRGEN2 EPWM_CH2 Trigger EADC Enable Bit 23 1 read-write 0 EPWM_CH2 Trigger EADC function Disabled #0 1 EPWM_CH2 Trigger EADC function Enabled #1 TRGEN3 EPWM_CH3 Trigger EADC Enable Bit 31 1 read-write 0 EPWM_CH3 Trigger EADC function Disabled #0 1 EPWM_CH3 Trigger EADC function Enabled #1 TRGSEL0 EPWM_CH0 Trigger EADC Source Select 0 4 read-write 0 EPWM_CH0 zero point #0000 1 EPWM_CH0 period point #0001 2 EPWM_CH0 zero or period point #0010 3 EPWM_CH0 up-count compared point #0011 4 EPWM_CH0 down-count compared point #0100 5 EPWM_CH1 zero point #0101 6 EPWM_CH1 period point #0110 7 EPWM_CH1 zero or period point #0111 8 EPWM_CH1 up-count compared point #1000 9 EPWM_CH1 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL1 EPWM_CH1 Trigger EADC Source Select 8 4 read-write 0 EPWM_CH0 zero point #0000 1 EPWM_CH0 period point #0001 2 EPWM_CH0 zero or period point #0010 3 EPWM_CH0 up-count compared point #0011 4 EPWM_CH0 down-count compared point #0100 5 EPWM_CH1 zero point #0101 6 EPWM_CH1 period point #0110 7 EPWM_CH1 zero or period point #0111 8 EPWM_CH1 up-count compared point #1000 9 EPWM_CH1 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL2 EPWM_CH2 Trigger EADC Source Select 16 4 read-write 0 EPWM_CH2 zero point #0000 1 EPWM_CH2 period point #0001 2 EPWM_CH2 zero or period point #0010 3 EPWM_CH2 up-count compared point #0011 4 EPWM_CH2 down-count compared point #0100 5 EPWM_CH3 zero point #0101 6 EPWM_CH3 period point #0110 7 EPWM_CH3 zero or period point #0111 8 EPWM_CH3 up-count compared point #1000 9 EPWM_CH3 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL3 EPWM_CH3 Trigger EADC Source Select 24 4 read-write 0 EPWM_CH2 zero point #0000 1 EPWM_CH2 period point #0001 2 EPWM_CH2 zero or period point #0010 3 EPWM_CH2 up-count compared point #0011 4 EPWM_CH2 down-count compared point #0100 5 EPWM_CH3 zero point #0101 6 EPWM_CH3 period point #0110 7 EPWM_CH3 zero or period point #0111 8 EPWM_CH3 up-count compared point #1000 9 EPWM_CH3 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 EPWM_EADCTS1 EPWM_EADCTS1 EPWM Trigger EADC Source Select Register 1 0xFC -1 read-write n 0x0 0x0 TRGEN4 EPWM_CH4 Trigger EADC Enable Bit 7 1 read-write 0 EPWM_CH4 Trigger EADC function Disabled #0 1 EPWM_CH4 Trigger EADC function Enabled #1 TRGEN5 EPWM_CH5 Trigger EADC Enable Bit 15 1 read-write 0 EPWM_CH5 Trigger EADC function Disabled #0 1 EPWM_CH5 Trigger EADC function Enabled #1 TRGSEL4 EPWM_CH4 Trigger EADC Source Select 0 4 read-write 0 EPWM_CH4 zero point #0000 1 EPWM_CH4 period point #0001 2 EPWM_CH4 zero or period point #0010 3 EPWM_CH4 up-count compared point #0011 4 EPWM_CH4 down-count compared point #0100 5 EPWM_CH5 zero point #0101 6 EPWM_CH5 period point #0110 7 EPWM_CH5 zero or period point #0111 8 EPWM_CH5 up-count compared point #1000 9 EPWM_CH5 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL5 EPWM_CH5 Trigger EADC Source Select 8 4 read-write 0 EPWM_CH4 zero point #0000 1 EPWM_CH4 period point #0001 2 EPWM_CH4 zero or period point #0010 3 EPWM_CH4 up-count compared point #0011 4 EPWM_CH4 down-count compared point #0100 5 EPWM_CH5 zero point #0101 6 EPWM_CH5 period point #0110 7 EPWM_CH5 zero or period point #0111 8 EPWM_CH5 up-count compared point #1000 9 EPWM_CH5 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 EPWM_EXTETCTL0 EPWM_EXTETCTL0 EPWM External Event Trigger Control Register 0 0x270 -1 read-write n 0x0 0x0 CNTACTS Counter Action Selection 4 2 read-write 0 Counter reset #00 1 Counter start #01 2 Counter reset and start #10 3 Reseved #11 EXETEN External Event Trigger Enable Bit 0 1 read-write 0 External Event Trigger function Disabled #0 1 External Event Trigger function Enabled #1 EXTTRGS External Trigger Selection 8 4 read-write 0 INT0 #0000 1 INT1 #0001 2 INT2 #0010 3 INT3 #0011 4 INT4 #0100 5 INT5 #0101 6 INT6 #0110 7 INT7 #0111 EPWM_EXTETCTL1 EPWM_EXTETCTL1 EPWM External Event Trigger Control Register 1 0x274 -1 read-write n 0x0 0x0 EPWM_EXTETCTL2 EPWM_EXTETCTL2 EPWM External Event Trigger Control Register 2 0x278 -1 read-write n 0x0 0x0 EPWM_EXTETCTL3 EPWM_EXTETCTL3 EPWM External Event Trigger Control Register 3 0x27C -1 read-write n 0x0 0x0 EPWM_EXTETCTL4 EPWM_EXTETCTL4 EPWM External Event Trigger Control Register 4 0x280 -1 read-write n 0x0 0x0 EPWM_EXTETCTL5 EPWM_EXTETCTL5 EPWM External Event Trigger Control Register 5 0x284 -1 read-write n 0x0 0x0 EPWM_FAILBRK EPWM_FAILBRK EPWM System Fail Brake Control Register 0xC4 -1 read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit 1 1 read-write 0 Brake Function triggered by BOD Disabled #0 1 Brake Function triggered by BOD Enabled #1 CORBRKEN Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit 3 1 read-write 0 Brake Function triggered by Core lockup detection Disabled #0 1 Brake Function triggered by Core lockup detection Enabled #1 CSSBRKEN Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit 0 1 read-write 0 Brake Function triggered by CSS detection Disabled #0 1 Brake Function triggered by CSS detection Enabled #1 RAMBRKEN SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit 2 1 read-write 0 Brake Function triggered by SRAM parity error detection Disabled #0 1 Brake Function triggered by SRAM parity error detection Enabled #1 EPWM_FCAPDAT0 EPWM_FCAPDAT0 EPWM Falling Capture Data Register 0 0x210 -1 read-only n 0x0 0x0 FCAPDAT EPWM Falling Capture Data Register (Read Only) When falling capture condition happened, the EPWM counter value will be saved in this register. 0 16 read-only EPWM_FCAPDAT1 EPWM_FCAPDAT1 EPWM Falling Capture Data Register 1 0x218 -1 read-write n 0x0 0x0 EPWM_FCAPDAT2 EPWM_FCAPDAT2 EPWM Falling Capture Data Register 2 0x220 -1 read-write n 0x0 0x0 EPWM_FCAPDAT3 EPWM_FCAPDAT3 EPWM Falling Capture Data Register 3 0x228 -1 read-write n 0x0 0x0 EPWM_FCAPDAT4 EPWM_FCAPDAT4 EPWM Falling Capture Data Register 4 0x230 -1 read-write n 0x0 0x0 EPWM_FCAPDAT5 EPWM_FCAPDAT5 EPWM Falling Capture Data Register 5 0x238 -1 read-write n 0x0 0x0 EPWM_FDCTL0 EPWM_FDCTL0 EPWM Fault Detect Control Register 0 0x164 -1 read-write n 0x0 0x0 DGSMPCYC Deglitch Sampling Cycle FDCKS is set to 0: Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times FDCKS is set to 1: Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times Note: CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 16 3 read-write FDCKSEL EPWM Channel Fault Detect Clock Select 28 2 read-write 0 FLT_CLK/1 #00 1 FLT_CLK/2 #01 2 FLT_CLK/4 #10 3 FLT_CLK/8 #11 FDDGEN Fault Detect Deglitch Enable Bit 31 1 read-write 0 Fault detect deglitch function Disabled #0 1 Fault detect deglitch function Enabled #1 FDMSKEN Fault Detect Mask Enable Bit 15 1 read-write 0 Fault detect mask function Disabled #0 1 Fault detect mask function Enabled #1 TRMSKCNT Transition Mask Counter The fault detect result will be masked before counter count from 0 to TRMSKCNT. FDCKS is set to 0: Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2) FDCKS is set to 1: Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT+2) Note: CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 0 7 read-write EPWM_FDCTL1 EPWM_FDCTL1 EPWM Fault Detect Control Register 1 0x168 -1 read-write n 0x0 0x0 EPWM_FDCTL2 EPWM_FDCTL2 EPWM Fault Detect Control Register 2 0x16C -1 read-write n 0x0 0x0 EPWM_FDCTL3 EPWM_FDCTL3 EPWM Fault Detect Control Register 3 0x170 -1 read-write n 0x0 0x0 EPWM_FDCTL4 EPWM_FDCTL4 EPWM Fault Detect Control Register 4 0x174 -1 read-write n 0x0 0x0 EPWM_FDCTL5 EPWM_FDCTL5 EPWM Fault Detect Control Register 5 0x178 -1 read-write n 0x0 0x0 EPWM_FDEN EPWM_FDEN EPWM Fault Detect Enable Register 0x160 -1 read-write n 0x0 0x0 FDCKS0 EPWM Channel n Fault Detect Clock Source Select Bits 16 1 read-write 0 EPWMx_CLK, x denotes 0 or 1 #0 1 EPWMx_CLK divide by prescaler, x denotes 0 or 1 #1 FDCKS1 EPWM Channel n Fault Detect Clock Source Select Bits 17 1 read-write 0 EPWMx_CLK, x denotes 0 or 1 #0 1 EPWMx_CLK divide by prescaler, x denotes 0 or 1 #1 FDCKS2 EPWM Channel n Fault Detect Clock Source Select Bits 18 1 read-write 0 EPWMx_CLK, x denotes 0 or 1 #0 1 EPWMx_CLK divide by prescaler, x denotes 0 or 1 #1 FDCKS3 EPWM Channel n Fault Detect Clock Source Select Bits 19 1 read-write 0 EPWMx_CLK, x denotes 0 or 1 #0 1 EPWMx_CLK divide by prescaler, x denotes 0 or 1 #1 FDCKS4 EPWM Channel n Fault Detect Clock Source Select Bits 20 1 read-write 0 EPWMx_CLK, x denotes 0 or 1 #0 1 EPWMx_CLK divide by prescaler, x denotes 0 or 1 #1 FDCKS5 EPWM Channel n Fault Detect Clock Source Select Bits 21 1 read-write 0 EPWMx_CLK, x denotes 0 or 1 #0 1 EPWMx_CLK divide by prescaler, x denotes 0 or 1 #1 FDEN0 EPWM Fault Detect Function Enable Bits 0 1 read-write 0 Fault detect function Disabled #0 1 Fault detect function Enabled #1 FDEN1 EPWM Fault Detect Function Enable Bits 1 1 read-write 0 Fault detect function Disabled #0 1 Fault detect function Enabled #1 FDEN2 EPWM Fault Detect Function Enable Bits 2 1 read-write 0 Fault detect function Disabled #0 1 Fault detect function Enabled #1 FDEN3 EPWM Fault Detect Function Enable Bits 3 1 read-write 0 Fault detect function Disabled #0 1 Fault detect function Enabled #1 FDEN4 EPWM Fault Detect Function Enable Bits 4 1 read-write 0 Fault detect function Disabled #0 1 Fault detect function Enabled #1 FDEN5 EPWM Fault Detect Function Enable Bits 5 1 read-write 0 Fault detect function Disabled #0 1 Fault detect function Enabled #1 FDODIS0 EPWM Channel n Output Fault Detect Disable Bits 8 1 read-write 0 EPWM detect fault and output Enabled #0 1 EPWM detect fault and output Disabled #1 FDODIS1 EPWM Channel n Output Fault Detect Disable Bits 9 1 read-write 0 EPWM detect fault and output Enabled #0 1 EPWM detect fault and output Disabled #1 FDODIS2 EPWM Channel n Output Fault Detect Disable Bits 10 1 read-write 0 EPWM detect fault and output Enabled #0 1 EPWM detect fault and output Disabled #1 FDODIS3 EPWM Channel n Output Fault Detect Disable Bits 11 1 read-write 0 EPWM detect fault and output Enabled #0 1 EPWM detect fault and output Disabled #1 FDODIS4 EPWM Channel n Output Fault Detect Disable Bits 12 1 read-write 0 EPWM detect fault and output Enabled #0 1 EPWM detect fault and output Disabled #1 FDODIS5 EPWM Channel n Output Fault Detect Disable Bits 13 1 read-write 0 EPWM detect fault and output Enabled #0 1 EPWM detect fault and output Disabled #1 EPWM_FDIEN EPWM_FDIEN EPWM Fault Detect Interrupt Enable Register 0x17C -1 read-write n 0x0 0x0 FDIENn EPWM Channel n Fault Detect Interrupt Enable Bit 0 1 read-write 0 EPWM Channel n Fault Detect Interrupt Disabled #0 1 EPWM Channel n Fault Detect Interrupt Enabled #1 EPWM_FDSTS EPWM_FDSTS EPWM Fault Detect Interrupt Flag Register 0x180 -1 read-write n 0x0 0x0 FDIFn EPWM Channel n Fault Detect Interrupt Flag Bit Fault Detect Interrupt Flag will be set when EPWM output short. Software can clear this bit by writing 1 to it. 0 6 read-write EPWM_FDTCNT0_1 EPWM_FDTCNT0_1 EPWM Falling Dead-time Counter Register 0/1 0x2B4 -1 read-write n 0x0 0x0 FDTCNT Falling Dead-time Counter (Write Protect) The dead-time can be calculated from the following formula: Note: This bit is write protected. Refer to SYS_REGLCTL register. 0 12 read-write EPWM_FDTCNT2_3 EPWM_FDTCNT2_3 EPWM Falling Dead-time Counter Register 2/3 0x2B8 -1 read-write n 0x0 0x0 EPWM_FDTCNT4_5 EPWM_FDTCNT4_5 EPWM Falling Dead-time Counter Register 4/5 0x2BC -1 read-write n 0x0 0x0 EPWM_FTCBUF0_1 EPWM_FTCBUF0_1 EPWM FTCMPDAT0_1 Buffer 0x340 -1 read-only n 0x0 0x0 FTCMPBUF EPWM FTCMPDAT Buffer (Read Only) Used as FTCMP active buffer. 0 16 read-only EPWM_FTCBUF2_3 EPWM_FTCBUF2_3 EPWM FTCMPDAT2_3 Buffer 0x344 -1 read-write n 0x0 0x0 EPWM_FTCBUF4_5 EPWM_FTCBUF4_5 EPWM FTCMPDAT4_5 Buffer 0x348 -1 read-write n 0x0 0x0 EPWM_FTCI EPWM_FTCI EPWM FTCMPDAT Indicator Register 0x34C -1 read-write n 0x0 0x0 FTCMD0 EPWM FTCMPDAT Down Indicator Indicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 8 1 read-write FTCMD2 EPWM FTCMPDAT Down Indicator Indicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 9 1 read-write FTCMD4 EPWM FTCMPDAT Down Indicator Indicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 10 1 read-write FTCMU0 EPWM FTCMPDAT Up Indicator Indicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 0 1 read-write FTCMU2 EPWM FTCMPDAT Up Indicator Indicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 1 1 read-write FTCMU4 EPWM FTCMPDAT Up Indicator Indicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 2 1 read-write EPWM_FTCMPDAT0_1 EPWM_FTCMPDAT0_1 EPWM Free Trigger Compare Register 0/1 0x100 -1 read-write n 0x0 0x0 FTCMP EPWM Free Trigger Compare Register 0 16 read-write EPWM_FTCMPDAT2_3 EPWM_FTCMPDAT2_3 EPWM Free Trigger Compare Register 2/3 0x104 -1 read-write n 0x0 0x0 EPWM_FTCMPDAT4_5 EPWM_FTCMPDAT4_5 EPWM Free Trigger Compare Register 4/5 0x108 -1 read-write n 0x0 0x0 EPWM_IFA0 EPWM_IFA0 EPWM Interrupt Flag Accumulator Register 0 0x130 -1 read-write n 0x0 0x0 IFACNT EPWM_CHn Interrupt Flag Counter The register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.EPWM flag will be set in every IFACNT[15:0] times of EPWM period. 0 16 read-write IFAEN EPWM_CHn Interrupt Flag Accumulator Enable Bit Note: Disabling this bit will reset related EPWM_IFACNT 31 1 read-write 0 EPWM_CHn interrupt flag accumulator Disabled #0 1 EPWM_CHn interrupt flag accumulator Enabled #1 IFASEL EPWM_CHn Interrupt Flag Accumulator Source Select 28 2 read-write 0 EPWM_CHn zero point #00 1 EPWM_CHn period in channel n #01 2 EPWM_CHn up-count compared point #10 3 EPWM_CHn down-count compared point #11 STPMOD EPWM_CHn Accumulator Stop Mode Enable Bit 24 1 read-write 0 EPWM_CHn Stop Mode Disabled #0 1 EPWM_CHn Stop Mode Enabled #1 EPWM_IFA1 EPWM_IFA1 EPWM Interrupt Flag Accumulator Register 1 0x134 -1 read-write n 0x0 0x0 EPWM_IFA2 EPWM_IFA2 EPWM Interrupt Flag Accumulator Register 2 0x138 -1 read-write n 0x0 0x0 EPWM_IFA3 EPWM_IFA3 EPWM Interrupt Flag Accumulator Register 3 0x13C -1 read-write n 0x0 0x0 EPWM_IFA4 EPWM_IFA4 EPWM Interrupt Flag Accumulator Register 4 0x140 -1 read-write n 0x0 0x0 EPWM_IFA5 EPWM_IFA5 EPWM Interrupt Flag Accumulator Register 5 0x144 -1 read-write n 0x0 0x0 EPWM_IFACNT0 EPWM_IFACNT0 EPWM Interrupt Flag Accumulator Counter 0 0x368 -1 read-only n 0x0 0x0 ACUCNT Accumulator Counter (Read Only) This value indicates how many interrupt are accumulated when using interrupt flag accumulator function. 0 16 read-only EPWM_IFACNT1 EPWM_IFACNT1 EPWM Interrupt Flag Accumulator Counter 1 0x36C -1 read-write n 0x0 0x0 EPWM_IFACNT2 EPWM_IFACNT2 EPWM Interrupt Flag Accumulator Counter 2 0x370 -1 read-write n 0x0 0x0 EPWM_IFACNT3 EPWM_IFACNT3 EPWM Interrupt Flag Accumulator Counter 3 0x374 -1 read-write n 0x0 0x0 EPWM_IFACNT4 EPWM_IFACNT4 EPWM Interrupt Flag Accumulator Counter 4 0x378 -1 read-write n 0x0 0x0 EPWM_IFACNT5 EPWM_IFACNT5 EPWM Interrupt Flag Accumulator Counter 5 0x37C -1 read-write n 0x0 0x0 EPWM_INTEN0 EPWM_INTEN0 EPWM Interrupt Enable Register 0 0xE0 -1 read-write n 0x0 0x0 CMPDIEN0 EPWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 24 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN1 EPWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 25 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN2 EPWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 26 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN3 EPWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 27 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN4 EPWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 28 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN5 EPWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 29 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPUIEN0 EPWM Compare Up Count Interrupt Enable Bits Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 16 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN1 EPWM Compare Up Count Interrupt Enable Bits Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 17 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN2 EPWM Compare Up Count Interrupt Enable Bits Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 18 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN3 EPWM Compare Up Count Interrupt Enable Bits Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 19 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN4 EPWM Compare Up Count Interrupt Enable Bits Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 20 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN5 EPWM Compare Up Count Interrupt Enable Bits Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 21 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 PIEN0 EPWM Period Point Interrupt Enable Bits Note 1: When up-down counter type period point means center point. Note 2: Odd channels will read always 0 at complementary mode. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN1 EPWM Period Point Interrupt Enable Bits Note 1: When up-down counter type period point means center point. Note 2: Odd channels will read always 0 at complementary mode. 9 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN2 EPWM Period Point Interrupt Enable Bits Note 1: When up-down counter type period point means center point. Note 2: Odd channels will read always 0 at complementary mode. 10 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN3 EPWM Period Point Interrupt Enable Bits Note 1: When up-down counter type period point means center point. Note 2: Odd channels will read always 0 at complementary mode. 11 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN4 EPWM Period Point Interrupt Enable Bits Note 1: When up-down counter type period point means center point. Note 2: Odd channels will read always 0 at complementary mode. 12 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN5 EPWM Period Point Interrupt Enable Bits Note 1: When up-down counter type period point means center point. Note 2: Odd channels will read always 0 at complementary mode. 13 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 EPWM Zero Point Interrupt Enable Bits Note: Odd channels will read always 0 at complementary mode. 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN1 EPWM Zero Point Interrupt Enable Bits Note: Odd channels will read always 0 at complementary mode. 1 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN2 EPWM Zero Point Interrupt Enable Bits Note: Odd channels will read always 0 at complementary mode. 2 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN3 EPWM Zero Point Interrupt Enable Bits Note: Odd channels will read always 0 at complementary mode. 3 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN4 EPWM Zero Point Interrupt Enable Bits Note: Odd channels will read always 0 at complementary mode. 4 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN5 EPWM Zero Point Interrupt Enable Bits Note: Odd channels will read always 0 at complementary mode. 5 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 EPWM_INTEN1 EPWM_INTEN1 EPWM Interrupt Enable Register 1 0xE4 -1 read-write n 0x0 0x0 BRKEIEN0_1 EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 0 1 read-write 0 Edge-detect Brake interrupt for channel0/1 Disabled #0 1 Edge-detect Brake interrupt for channel0/1 Enabled #1 BRKEIEN2_3 EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 1 1 read-write 0 Edge-detect Brake interrupt for channel2/3 Disabled #0 1 Edge-detect Brake interrupt for channel2/3 Enabled #1 BRKEIEN4_5 EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 2 1 read-write 0 Edge-detect Brake interrupt for channel4/5 Disabled #0 1 Edge-detect Brake interrupt for channel4/5 Enabled #1 BRKLIEN0_1 EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 8 1 read-write 0 Level-detect Brake interrupt for channel0/1 Disabled #0 1 Level-detect Brake interrupt for channel0/1 Enabled #1 BRKLIEN2_3 EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 9 1 read-write 0 Level-detect Brake interrupt for channel2/3 Disabled #0 1 Level-detect Brake interrupt for channel2/3 Enabled #1 BRKLIEN4_5 EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 10 1 read-write 0 Level-detect Brake interrupt for channel4/5 Disabled #0 1 Level-detect Brake interrupt for channel4/5 Enabled #1 EPWM_INTSTS0 EPWM_INTSTS0 EPWM Interrupt Flag Register 0 0xE8 -1 read-write n 0x0 0x0 CMPDIF0 EPWM Compare Down Count Interrupt Flag Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. Note: In complementary mode, CMPDIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 24 1 read-write CMPDIF1 EPWM Compare Down Count Interrupt Flag Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. Note: In complementary mode, CMPDIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 25 1 read-write CMPDIF2 EPWM Compare Down Count Interrupt Flag Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. Note: In complementary mode, CMPDIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 26 1 read-write CMPDIF3 EPWM Compare Down Count Interrupt Flag Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. Note: In complementary mode, CMPDIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 27 1 read-write CMPDIF4 EPWM Compare Down Count Interrupt Flag Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. Note: In complementary mode, CMPDIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 28 1 read-write CMPDIF5 EPWM Compare Down Count Interrupt Flag Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. Note: In complementary mode, CMPDIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 29 1 read-write CMPUIF0 EPWM Compare Up Count Interrupt Flag Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. Note: In complementary mode, CMPUIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 16 1 read-write CMPUIF1 EPWM Compare Up Count Interrupt Flag Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. Note: In complementary mode, CMPUIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 17 1 read-write CMPUIF2 EPWM Compare Up Count Interrupt Flag Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. Note: In complementary mode, CMPUIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 18 1 read-write CMPUIF3 EPWM Compare Up Count Interrupt Flag Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. Note: In complementary mode, CMPUIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 19 1 read-write CMPUIF4 EPWM Compare Up Count Interrupt Flag Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. Note: In complementary mode, CMPUIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 20 1 read-write CMPUIF5 EPWM Compare Up Count Interrupt Flag Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. Note: In complementary mode, CMPUIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 21 1 read-write PIF0 EPWM Period Point Interrupt Flag This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. Note: This bit can be cleared to 0 by software writing 1. 8 1 read-write PIF1 EPWM Period Point Interrupt Flag This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. Note: This bit can be cleared to 0 by software writing 1. 9 1 read-write PIF2 EPWM Period Point Interrupt Flag This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. Note: This bit can be cleared to 0 by software writing 1. 10 1 read-write PIF3 EPWM Period Point Interrupt Flag This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. Note: This bit can be cleared to 0 by software writing 1. 11 1 read-write PIF4 EPWM Period Point Interrupt Flag This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. Note: This bit can be cleared to 0 by software writing 1. 12 1 read-write PIF5 EPWM Period Point Interrupt Flag This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. Note: This bit can be cleared to 0 by software writing 1. 13 1 read-write ZIF0 EPWM Zero Point Interrupt Flag This bit is set by hardware when EPWM counter reaches 0. Note: This bit can be cleared to 0 by software writing 1 0 1 read-write ZIF1 EPWM Zero Point Interrupt Flag This bit is set by hardware when EPWM counter reaches 0. Note: This bit can be cleared to 0 by software writing 1 1 1 read-write ZIF2 EPWM Zero Point Interrupt Flag This bit is set by hardware when EPWM counter reaches 0. Note: This bit can be cleared to 0 by software writing 1 2 1 read-write ZIF3 EPWM Zero Point Interrupt Flag This bit is set by hardware when EPWM counter reaches 0. Note: This bit can be cleared to 0 by software writing 1 3 1 read-write ZIF4 EPWM Zero Point Interrupt Flag This bit is set by hardware when EPWM counter reaches 0. Note: This bit can be cleared to 0 by software writing 1 4 1 read-write ZIF5 EPWM Zero Point Interrupt Flag This bit is set by hardware when EPWM counter reaches 0. Note: This bit can be cleared to 0 by software writing 1 5 1 read-write EPWM_INTSTS1 EPWM_INTSTS1 EPWM Interrupt Flag Register 1 0xEC -1 read-write n 0x0 0x0 BRKEIF0 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 0 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF1 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 1 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF2 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 2 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF3 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 3 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF4 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 4 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF5 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 5 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKESTS0 EPWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 16 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS1 EPWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 17 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS2 EPWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 18 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS3 EPWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 19 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS4 EPWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 20 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS5 EPWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 21 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLIF0 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 8 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF1 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 9 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF2 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 10 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF3 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 11 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF4 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 12 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF5 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 13 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLSTS0 EPWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 24 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS1 EPWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 25 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS2 EPWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 26 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS3 EPWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 27 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS4 EPWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 28 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS5 EPWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 29 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 EPWM_LEBCNT EPWM_LEBCNT EPWM Leading Edge Blanking Counter Register 0x11C -1 read-write n 0x0 0x0 LEBCNT EPWM Leading Edge Blanking Counter 0 9 read-write EPWM_LEBCTL EPWM_LEBCTL EPWM Leading Edge Blanking Control Register 0x118 -1 read-write n 0x0 0x0 LEBEN EPWM Leading Edge Blanking Enable Bit 0 1 read-write 0 EPWM Leading Edge Blanking Disabled #0 1 EPWM Leading Edge Blanking Enabled #1 SRCEN0 EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit 8 1 read-write 0 EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled #0 1 EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled #1 SRCEN2 EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit 9 1 read-write 0 EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled #0 1 EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled #1 SRCEN4 EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit 10 1 read-write 0 EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled #0 1 EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled #1 TRGTYPE EPWM Leading Edge Blanking Trigger Type 16 2 read-write 0 When detect leading edge blanking source rising edge, blanking counter start counting 0 1 When detect leading edge blanking source falling edge, blanking counter start counting 1 2 When detect leading edge blanking source rising or falling edge, blanking counter start counting 2 3 Reserved. 3 EPWM_LOAD EPWM_LOAD EPWM Load Register 0x28 -1 read-write n 0x0 0x0 LOAD0 Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit This bit is software write, hardware clear when current EPWM period end. Write Operation: 0 1 read-write 0 No effect. No load window is set #0 1 Set load window of window loading mode. Load window is set #1 LOAD1 Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit This bit is software write, hardware clear when current EPWM period end. Write Operation: 1 1 read-write 0 No effect. No load window is set #0 1 Set load window of window loading mode. Load window is set #1 LOAD2 Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit This bit is software write, hardware clear when current EPWM period end. Write Operation: 2 1 read-write 0 No effect. No load window is set #0 1 Set load window of window loading mode. Load window is set #1 LOAD3 Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit This bit is software write, hardware clear when current EPWM period end. Write Operation: 3 1 read-write 0 No effect. No load window is set #0 1 Set load window of window loading mode. Load window is set #1 LOAD4 Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit This bit is software write, hardware clear when current EPWM period end. Write Operation: 4 1 read-write 0 No effect. No load window is set #0 1 Set load window of window loading mode. Load window is set #1 LOAD5 Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit This bit is software write, hardware clear when current EPWM period end. Write Operation: 5 1 read-write 0 No effect. No load window is set #0 1 Set load window of window loading mode. Load window is set #1 EPWM_MSK EPWM_MSK EPWM Mask Data Register 0xBC -1 read-write n 0x0 0x0 MSKDAT0 EPWM Mask Data Bit This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 0 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT1 EPWM Mask Data Bit This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 1 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT2 EPWM Mask Data Bit This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 2 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT3 EPWM Mask Data Bit This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 3 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT4 EPWM Mask Data Bit This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 4 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT5 EPWM Mask Data Bit This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 5 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 EPWM_MSKEN EPWM_MSKEN EPWM Mask Enable Register 0xB8 -1 read-write n 0x0 0x0 MSKEN0 EPWM Mask Enable Bits The EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 0 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN1 EPWM Mask Enable Bits The EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 1 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN2 EPWM Mask Enable Bits The EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 2 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN3 EPWM Mask Enable Bits The EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 3 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN4 EPWM Mask Enable Bits The EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 4 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN5 EPWM Mask Enable Bits The EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 5 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 EPWM_PBUF0 EPWM_PBUF0 EPWM PERIOD0 Buffer 0x304 -1 read-only n 0x0 0x0 PBUF EPWM Period Register Buffer (Read Only) Used as PERIOD active register. 0 16 read-only EPWM_PBUF1 EPWM_PBUF1 EPWM PERIOD1 Buffer 0x308 -1 read-write n 0x0 0x0 EPWM_PBUF2 EPWM_PBUF2 EPWM PERIOD2 Buffer 0x30C -1 read-write n 0x0 0x0 EPWM_PBUF3 EPWM_PBUF3 EPWM PERIOD3 Buffer 0x310 -1 read-write n 0x0 0x0 EPWM_PBUF4 EPWM_PBUF4 EPWM PERIOD4 Buffer 0x314 -1 read-write n 0x0 0x0 EPWM_PBUF5 EPWM_PBUF5 EPWM PERIOD5 Buffer 0x318 -1 read-write n 0x0 0x0 EPWM_PDMACAP0_1 EPWM_PDMACAP0_1 EPWM Capture Channel 01 PDMA Register 0x240 -1 read-only n 0x0 0x0 CAPBUF EPWM Capture PDMA Register (Read Only) This register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. 0 16 read-only EPWM_PDMACAP2_3 EPWM_PDMACAP2_3 EPWM Capture Channel 23 PDMA Register 0x244 -1 read-write n 0x0 0x0 EPWM_PDMACAP4_5 EPWM_PDMACAP4_5 EPWM Capture Channel 45 PDMA Register 0x248 -1 read-write n 0x0 0x0 EPWM_PDMACTL EPWM_PDMACTL EPWM PDMA Control Register 0x23C -1 read-write n 0x0 0x0 CAPMOD0_1 Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer 1 2 read-write 0 Reserved. #00 1 EPWM_RCAPDAT0/1 #01 2 EPWM_FCAPDAT0/1 #10 3 Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1 #11 CAPMOD2_3 Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer 9 2 read-write 0 Reserved. #00 1 EPWM_RCAPDAT2/3 #01 2 EPWM_FCAPDAT2/3 #10 3 Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3 #11 CAPMOD4_5 Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer 17 2 read-write 0 Reserved. #00 1 EPWM_RCAPDAT4/5 #01 2 EPWM_FCAPDAT4/5 #10 3 Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5 #11 CAPORD0_1 Capture Channel 0/1 Rising/Falling Order 3 1 read-write 0 EPWM_FCAPDAT0/1 is the first captured data to memory #0 1 EPWM_RCAPDAT0/1 is the first captured data to memory #1 CAPORD2_3 Capture Channel 2/3 Rising/Falling Order 11 1 read-write 0 EPWM_FCAPDAT2/3 is the first captured data to memory #0 1 EPWM_RCAPDAT2/3 is the first captured data to memory #1 CAPORD4_5 Capture Channel 4/5 Rising/Falling Order 19 1 read-write 0 EPWM_FCAPDAT4/5 is the first captured data to memory #0 1 EPWM_RCAPDAT4/5 is the first captured data to memory #1 CHEN0_1 Channel 0/1 PDMA Enable Bit 0 1 read-write 0 Channel 0/1 PDMA function Disabled #0 1 Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory #1 CHEN2_3 Channel 2/3 PDMA Enable Bit 8 1 read-write 0 Channel 2/3 PDMA function Disabled #0 1 Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory #1 CHEN4_5 Channel 4/5 PDMA Enable Bit 16 1 read-write 0 Channel 4/5 PDMA function Disabled #0 1 Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory #1 CHSEL0_1 Select Channel 0/1 to Do PDMA Transfer 4 1 read-write 0 Channel0 #0 1 Channel1 #1 CHSEL2_3 Select Channel 2/3 to Do PDMA Transfer 12 1 read-write 0 Channel2 #0 1 Channel3 #1 CHSEL4_5 Select Channel 4/5 to Do PDMA Transfer 20 1 read-write 0 Channel4 #0 1 Channel5 #1 EPWM_PERIOD0 EPWM_PERIOD0 EPWM Period Register 0 0x30 -1 read-write n 0x0 0x0 PERIOD EPWM Period Register Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. 0 16 read-write EPWM_PERIOD1 EPWM_PERIOD1 EPWM Period Register 1 0x34 -1 read-write n 0x0 0x0 EPWM_PERIOD2 EPWM_PERIOD2 EPWM Period Register 2 0x38 -1 read-write n 0x0 0x0 EPWM_PERIOD3 EPWM_PERIOD3 EPWM Period Register 3 0x3C -1 read-write n 0x0 0x0 EPWM_PERIOD4 EPWM_PERIOD4 EPWM Period Register 4 0x40 -1 read-write n 0x0 0x0 EPWM_PERIOD5 EPWM_PERIOD5 EPWM Period Register 5 0x44 -1 read-write n 0x0 0x0 EPWM_PHS0_1 EPWM_PHS0_1 EPWM Counter Phase Register 0/1 0x80 -1 read-write n 0x0 0x0 PHS EPWM Synchronous Start Phase Bits PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function. 0 16 read-write EPWM_PHS2_3 EPWM_PHS2_3 EPWM Counter Phase Register 2/3 0x84 -1 read-write n 0x0 0x0 EPWM_PHS4_5 EPWM_PHS4_5 EPWM Counter Phase Register 4/5 0x88 -1 read-write n 0x0 0x0 EPWM_POEN EPWM_POEN EPWM Output Enable Register 0xD8 -1 read-write n 0x0 0x0 POEN0 EPWM Pin Output Enable Bits 0 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN1 EPWM Pin Output Enable Bits 1 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN2 EPWM Pin Output Enable Bits 2 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN3 EPWM Pin Output Enable Bits 3 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN4 EPWM Pin Output Enable Bits 4 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN5 EPWM Pin Output Enable Bits 5 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 EPWM_POLCTL EPWM_POLCTL EPWM Pin Polar Inverse Register 0xD4 -1 read-write n 0x0 0x0 PINV0 EPWM PIN Polar Inverse Control The register controls polarity state of EPWMx_CHn output pin. 0 1 read-write 0 EPWMx_CHn output pin polar inverse Disabled #0 1 EPWMx_CHn output pin polar inverse Enabled #1 PINV1 EPWM PIN Polar Inverse Control The register controls polarity state of EPWMx_CHn output pin. 1 1 read-write 0 EPWMx_CHn output pin polar inverse Disabled #0 1 EPWMx_CHn output pin polar inverse Enabled #1 PINV2 EPWM PIN Polar Inverse Control The register controls polarity state of EPWMx_CHn output pin. 2 1 read-write 0 EPWMx_CHn output pin polar inverse Disabled #0 1 EPWMx_CHn output pin polar inverse Enabled #1 PINV3 EPWM PIN Polar Inverse Control The register controls polarity state of EPWMx_CHn output pin. 3 1 read-write 0 EPWMx_CHn output pin polar inverse Disabled #0 1 EPWMx_CHn output pin polar inverse Enabled #1 PINV4 EPWM PIN Polar Inverse Control The register controls polarity state of EPWMx_CHn output pin. 4 1 read-write 0 EPWMx_CHn output pin polar inverse Disabled #0 1 EPWMx_CHn output pin polar inverse Enabled #1 PINV5 EPWM PIN Polar Inverse Control The register controls polarity state of EPWMx_CHn output pin. 5 1 read-write 0 EPWMx_CHn output pin polar inverse Disabled #0 1 EPWMx_CHn output pin polar inverse Enabled #1 EPWM_RCAPDAT0 EPWM_RCAPDAT0 EPWM Rising Capture Data Register 0 0x20C -1 read-only n 0x0 0x0 RCAPDAT EPWM Rising Capture Data Register (Read Only) When rising capture condition happened, the EPWM counter value will be saved in this register. 0 16 read-only EPWM_RCAPDAT1 EPWM_RCAPDAT1 EPWM Rising Capture Data Register 1 0x214 -1 read-write n 0x0 0x0 EPWM_RCAPDAT2 EPWM_RCAPDAT2 EPWM Rising Capture Data Register 2 0x21C -1 read-write n 0x0 0x0 EPWM_RCAPDAT3 EPWM_RCAPDAT3 EPWM Rising Capture Data Register 3 0x224 -1 read-write n 0x0 0x0 EPWM_RCAPDAT4 EPWM_RCAPDAT4 EPWM Rising Capture Data Register 4 0x22C -1 read-write n 0x0 0x0 EPWM_RCAPDAT5 EPWM_RCAPDAT5 EPWM Rising Capture Data Register 5 0x234 -1 read-write n 0x0 0x0 EPWM_RDTCNT0_1 EPWM_RDTCNT0_1 EPWM Rising Dead-time Counter Register 0/1 0x2A8 -1 read-write n 0x0 0x0 RDTCNT Rising Dead-time Counter (Write Protect) The Rising dead-time can be calculated from the following formula: Note: This bit is write protected. Refer to SYS_REGLCTL register. 0 12 read-write EPWM_RDTCNT2_3 EPWM_RDTCNT2_3 EPWM Rising Dead-time Counter Register 2/3 0x2AC -1 read-write n 0x0 0x0 EPWM_RDTCNT4_5 EPWM_RDTCNT4_5 EPWM Rising Dead-time Counter Register 4/5 0x2B0 -1 read-write n 0x0 0x0 EPWM_SSCTL EPWM_SSCTL EPWM Synchronous Start Control Register 0x110 -1 read-write n 0x0 0x0 SSEN0 EPWM Synchronous Start Function Enable Bits When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 0 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN1 EPWM Synchronous Start Function Enable Bits When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN2 EPWM Synchronous Start Function Enable Bits When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 2 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN3 EPWM Synchronous Start Function Enable Bits When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 3 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN4 EPWM Synchronous Start Function Enable Bits When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 4 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN5 EPWM Synchronous Start Function Enable Bits When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 5 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSRC EPWM Synchronous Start Source Select Bits 8 2 read-write 0 Synchronous start source come from EPWM0 #00 1 Synchronous start source come from EPWM1 #01 2 Synchronous start source come from BPWM0 #10 3 Synchronous start source come from BPWM1 #11 EPWM_SSTRG EPWM_SSTRG EPWM Synchronous Start Trigger Register 0x114 -1 write-only n 0x0 0x0 CNTSEN EPWM Counter Synchronous Start Enable (Write Only) PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time. Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled. 0 1 write-only EPWM_STATUS EPWM_STATUS EPWM Status Register 0x120 -1 read-write n 0x0 0x0 CNTMAXF0 Time-base Counter Equal to 0xFFFF Latched Flag Note: This bit can be cleared by software writing 1. 0 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF1 Time-base Counter Equal to 0xFFFF Latched Flag Note: This bit can be cleared by software writing 1. 1 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF2 Time-base Counter Equal to 0xFFFF Latched Flag Note: This bit can be cleared by software writing 1. 2 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF3 Time-base Counter Equal to 0xFFFF Latched Flag Note: This bit can be cleared by software writing 1. 3 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF4 Time-base Counter Equal to 0xFFFF Latched Flag Note: This bit can be cleared by software writing 1. 4 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF5 Time-base Counter Equal to 0xFFFF Latched Flag Note: This bit can be cleared by software writing 1. 5 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 DACTRGF DAC Start of Conversion Flag Note: This bit can be cleared by software writing 1. 24 1 read-write 0 No DAC start of conversion trigger event has occurred #0 1 A DAC start of conversion trigger event has occurred #1 EADCTRGF0 EADC Start of Conversion Flag Note: This bit can be cleared by software writing 1. 16 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF1 EADC Start of Conversion Flag Note: This bit can be cleared by software writing 1. 17 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF2 EADC Start of Conversion Flag Note: This bit can be cleared by software writing 1. 18 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF3 EADC Start of Conversion Flag Note: This bit can be cleared by software writing 1. 19 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF4 EADC Start of Conversion Flag Note: This bit can be cleared by software writing 1. 20 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF5 EADC Start of Conversion Flag Note: This bit can be cleared by software writing 1. 21 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 SYNCINF0 Input Synchronization Latched Flag Note: This bit can be cleared by software writing 1. 8 1 read-write 0 No SYNC_IN event has occurred #0 1 A SYNC_IN event has occurred #1 SYNCINF2 Input Synchronization Latched Flag Note: This bit can be cleared by software writing 1. 9 1 read-write 0 No SYNC_IN event has occurred #0 1 A SYNC_IN event has occurred #1 SYNCINF4 Input Synchronization Latched Flag Note: This bit can be cleared by software writing 1. 10 1 read-write 0 No SYNC_IN event has occurred #0 1 A SYNC_IN event has occurred #1 EPWM_SWBRK EPWM_SWBRK EPWM Software Brake Control Register 0xDC -1 write-only n 0x0 0x0 BRKETRG0 EPWM Edge Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 write-only BRKETRG2 EPWM Edge Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 write-only BRKETRG4 EPWM Edge Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 write-only BRKLTRG0 EPWM Level Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 write-only BRKLTRG2 EPWM Level Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 write-only BRKLTRG4 EPWM Level Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 write-only EPWM_SWEOFCTL EPWM_SWEOFCTL EPWM Software Event Output Force Control Register 0x288 -1 read-write n 0x0 0x0 OUTACTS0 Output Action Selection 0 2 read-write 0 Do nothing #00 1 EPWM output Low #01 2 EPWM output High #10 3 EPWM output Toggle #11 OUTACTS1 Output Action Selection 2 2 read-write 0 Do nothing #00 1 EPWM output Low #01 2 EPWM output High #10 3 EPWM output Toggle #11 OUTACTS2 Output Action Selection 4 2 read-write 0 Do nothing #00 1 EPWM output Low #01 2 EPWM output High #10 3 EPWM output Toggle #11 OUTACTS3 Output Action Selection 6 2 read-write 0 Do nothing #00 1 EPWM output Low #01 2 EPWM output High #10 3 EPWM output Toggle #11 OUTACTS4 Output Action Selection 8 2 read-write 0 Do nothing #00 1 EPWM output Low #01 2 EPWM output High #10 3 EPWM output Toggle #11 OUTACTS5 Output Action Selection 10 2 read-write 0 Do nothing #00 1 EPWM output Low #01 2 EPWM output High #10 3 EPWM output Toggle #11 EPWM_SWEOFTRG EPWM_SWEOFTRG EPWM Software Event Output Force Trigger Register 0x28C -1 read-write n 0x0 0x0 SWETRG0 Software Event Trigger Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. Note: This bit will auto cleared by hardware. 0 1 read-write SWETRG1 Software Event Trigger Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. Note: This bit will auto cleared by hardware. 1 1 read-write SWETRG2 Software Event Trigger Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. Note: This bit will auto cleared by hardware. 2 1 read-write SWETRG3 Software Event Trigger Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. Note: This bit will auto cleared by hardware. 3 1 read-write SWETRG4 Software Event Trigger Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. Note: This bit will auto cleared by hardware. 4 1 read-write SWETRG5 Software Event Trigger Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. Note: This bit will auto cleared by hardware. 5 1 read-write EPWM_SWSYNC EPWM_SWSYNC EPWM Software Control Synchronization Register 0xC -1 read-write n 0x0 0x0 SWSYNC0 Software SYNC Function When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. 0 1 read-write SWSYNC2 Software SYNC Function When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. 1 1 read-write SWSYNC4 Software SYNC Function When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. 2 1 read-write EPWM_SYNC EPWM_SYNC EPWM Synchronization Register 0x8 -1 read-write n 0x0 0x0 PHSDIR0 EPWM Phase Direction Control 24 1 read-write 0 Control EPWM counter count decrement after synchronizing #0 1 Control EPWM counter count increment after synchronizing #1 PHSDIR2 EPWM Phase Direction Control 25 1 read-write 0 Control EPWM counter count decrement after synchronizing #0 1 Control EPWM counter count increment after synchronizing #1 PHSDIR4 EPWM Phase Direction Control 26 1 read-write 0 Control EPWM counter count decrement after synchronizing #0 1 Control EPWM counter count increment after synchronizing #1 PHSEN0 SYNC Phase Enable Bits 0 1 read-write 0 EPWM counter disabled to load PHS value #0 1 EPWM counter enabled to load PHS value #1 PHSEN2 SYNC Phase Enable Bits 1 1 read-write 0 EPWM counter disabled to load PHS value #0 1 EPWM counter enabled to load PHS value #1 PHSEN4 SYNC Phase Enable Bits 2 1 read-write 0 EPWM counter disabled to load PHS value #0 1 EPWM counter enabled to load PHS value #1 SFLTCNT SYNC Edge Detector Filter Count The register bits control the counter number of edge detector. 20 3 read-write SFLTCSEL SYNC Edge Detector Filter Clock Selection 17 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 SINPINV SYNC Input Pin Inverse 23 1 read-write 0 The state of pin SYNC is passed to the negative edge detector #0 1 The inversed state of pin SYNC is passed to the negative edge detector #1 SINSRC0 EPWM0_SYNC_IN Source Selection 8 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT will not be generated #11 SINSRC2 EPWM0_SYNC_IN Source Selection 10 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT will not be generated #11 SINSRC4 EPWM0_SYNC_IN Source Selection 12 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT will not be generated #11 SNFLTEN EPWM0_SYNC_IN Noise Filter Enable Bits 16 1 read-write 0 Noise filter of input pin EPWM0_SYNC_IN Disabled #0 1 Noise filter of input pin EPWM0_SYNC_IN Enabled #1 EPWM_WGCTL0 EPWM_WGCTL0 EPWM Generation Register 0 0xB0 -1 read-write n 0x0 0x0 PRDPCTL0 EPWM Period (Center) Point Control EPWM can control output level when EPWM counter counts to (PERIODn+1). Note: This bit is center point control when EPWM counter operating in up-down counter type. 16 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL1 EPWM Period (Center) Point Control EPWM can control output level when EPWM counter counts to (PERIODn+1). Note: This bit is center point control when EPWM counter operating in up-down counter type. 18 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL2 EPWM Period (Center) Point Control EPWM can control output level when EPWM counter counts to (PERIODn+1). Note: This bit is center point control when EPWM counter operating in up-down counter type. 20 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL3 EPWM Period (Center) Point Control EPWM can control output level when EPWM counter counts to (PERIODn+1). Note: This bit is center point control when EPWM counter operating in up-down counter type. 22 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL4 EPWM Period (Center) Point Control EPWM can control output level when EPWM counter counts to (PERIODn+1). Note: This bit is center point control when EPWM counter operating in up-down counter type. 24 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL5 EPWM Period (Center) Point Control EPWM can control output level when EPWM counter counts to (PERIODn+1). Note: This bit is center point control when EPWM counter operating in up-down counter type. 26 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 ZPCTL0 EPWM Zero Point Control EPWM can control output level when EPWM counter counts to 0. 0 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL1 EPWM Zero Point Control EPWM can control output level when EPWM counter counts to 0. 2 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL2 EPWM Zero Point Control EPWM can control output level when EPWM counter counts to 0. 4 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL3 EPWM Zero Point Control EPWM can control output level when EPWM counter counts to 0. 6 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL4 EPWM Zero Point Control EPWM can control output level when EPWM counter counts to 0. 8 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL5 EPWM Zero Point Control EPWM can control output level when EPWM counter counts to 0. 10 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 EPWM_WGCTL1 EPWM_WGCTL1 EPWM Generation Register 1 0xB4 -1 read-write n 0x0 0x0 CMPDCTL0 EPWM Compare Down Point Control EPWM can control output level when EPWM counter counts down to CMP. Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 16 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL1 EPWM Compare Down Point Control EPWM can control output level when EPWM counter counts down to CMP. Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 18 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL2 EPWM Compare Down Point Control EPWM can control output level when EPWM counter counts down to CMP. Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 20 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL3 EPWM Compare Down Point Control EPWM can control output level when EPWM counter counts down to CMP. Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 22 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL4 EPWM Compare Down Point Control EPWM can control output level when EPWM counter counts down to CMP. Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 24 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL5 EPWM Compare Down Point Control EPWM can control output level when EPWM counter counts down to CMP. Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 26 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPUCTL0 EPWM Compare Up Point Control EPWM can control output level when EPWM counter counts up to CMP. Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 0 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL1 EPWM Compare Up Point Control EPWM can control output level when EPWM counter counts up to CMP. Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 2 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL2 EPWM Compare Up Point Control EPWM can control output level when EPWM counter counts up to CMP. Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 4 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL3 EPWM Compare Up Point Control EPWM can control output level when EPWM counter counts up to CMP. Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 6 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL4 EPWM Compare Up Point Control EPWM can control output level when EPWM counter counts up to CMP. Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 8 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL5 EPWM Compare Up Point Control EPWM can control output level when EPWM counter counts up to CMP. Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 10 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 EPWM1 EPWM Register Map EPWM 0x0 0x0 0x2C registers n 0x110 0x14 registers n 0x130 0x18 registers n 0x150 0xC registers n 0x160 0x38 registers n 0x200 0x4C registers n 0x250 0x74 registers n 0x30 0x18 registers n 0x304 0x7C registers n 0x50 0x18 registers n 0x70 0xC registers n 0x80 0xC registers n 0x90 0x18 registers n 0xB0 0x40 registers n 0xF4 0x18 registers n EPWM_AINTEN EPWM_AINTEN EPWM Accumulator Interrupt Enable Register 0x154 -1 read-write n 0x0 0x0 IFAIEN0 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 0 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN1 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN2 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 2 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN3 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 3 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN4 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 4 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN5 EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 5 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 EPWM_AINTSTS EPWM_AINTSTS EPWM Accumulator Interrupt Flag Register 0x150 -1 read-write n 0x0 0x0 IFAIF0 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 0 1 read-write IFAIF1 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1 1 read-write IFAIF2 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 2 1 read-write IFAIF3 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 3 1 read-write IFAIF4 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 4 1 read-write IFAIF5 EPWM_CHn Interrupt Flag Accumulator Interrupt Flag Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 5 1 read-write EPWM_APDMACTL EPWM_APDMACTL EPWM Accumulator PDMA Control Register 0x158 -1 read-write n 0x0 0x0 APDMAEN0 Channel n Accumulator PDMA Enable Bits 0 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN1 Channel n Accumulator PDMA Enable Bits 1 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN2 Channel n Accumulator PDMA Enable Bits 2 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN3 Channel n Accumulator PDMA Enable Bits 3 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN4 Channel n Accumulator PDMA Enable Bits 4 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 APDMAEN5 Channel n Accumulator PDMA Enable Bits 5 1 read-write 0 Channel n PDMA function Disabled #0 1 Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register #1 EPWM_BNF EPWM_BNF EPWM Brake Noise Filter Register 0xC0 -1 read-write n 0x0 0x0 BK0SRC Brake 0 Pin Source Select For EPWM0 setting: 16 1 read-write 0 Brake 0 pin source come from EPWM0_BRAKE0. Brake 0 pin source come from EPWM1_BRAKE0 #0 1 Brake 0 pin source come from EPWM1_BRAKE0. Brake 0 pin source come from EPWM0_BRAKE0 #1 BK1SRC Brake 1 Pin Source Select For EPWM0 setting: 24 1 read-write 0 Brake 1 pin source come from EPWM0_BRAKE1. Brake 1 pin source come from EPWM1_BRAKE1 #0 1 Brake 1 pin source come from EPWM1_BRAKE1. Brake 1 pin source come from EPWM0_BRAKE1 #1 BRK0FCNT Brake 0 Edge Detector Filter Count The register bits control the Brake0 filter counter to count from 0 to BRK0FCNT. 4 3 read-write BRK0NFEN EPWM Brake 0 Noise Filter Enable Bit 0 1 read-write 0 Noise filter of EPWM Brake 0 Disabled #0 1 Noise filter of EPWM Brake 0 Enabled #1 BRK0NFSEL Brake 0 Edge Detector Filter Clock Selection 1 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK0PINV Brake 0 Pin Inverse 7 1 read-write 0 brake pin event will be detected if EPWMx_BRAKE0 pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 brake pin event will be detected if EPWMx_BRAKE0 pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 BRK1FCNT Brake 1 Edge Detector Filter Count The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 12 3 read-write BRK1NFEN EPWM Brake 1 Noise Filter Enable Bit 8 1 read-write 0 Noise filter of EPWM Brake 1 Disabled #0 1 Noise filter of EPWM Brake 1 Enabled #1 BRK1NFSEL Brake 1 Edge Detector Filter Clock Selection 9 3 read-write 0 Filter clock = PCLK #000 1 Filter clock = PCLK/2 #001 2 Filter clock = PCLK/4 #010 3 Filter clock = PCLK/8 #011 4 Filter clock = PCLK/16 #100 5 Filter clock = PCLK/32 #101 6 Filter clock = PCLK/64 #110 7 Filter clock = PCLK/128 #111 BRK1PINV Brake 1 Pin Inverse 15 1 read-write 0 brake pin event will be detected if EPWMx_BRAKE1 pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 brake pin event will be detected if EPWMx_BRAKE1 pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 EPWM_BRKCTL0_1 EPWM_BRKCTL0_1 EPWM Brake Edge Detect Control Register 0/1 0xC8 -1 read-write n 0x0 0x0 BRKAEVEN EPWM Brake Action Select for Even Channel (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 16 2 read-write 0 EPWMx brake event will not affect even channels output #00 1 EPWM even channel output tri-state when EPWMx brake event happened #01 2 EPWM even channel output low level when EPWMx brake event happened #10 3 EPWM even channel output high level when EPWMx brake event happened #11 BRKAODD EPWM Brake Action Select for Odd Channel (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 18 2 read-write 0 EPWMx brake event will not affect odd channels output #00 1 EPWM odd channel output tri-state when EPWMx brake event happened #01 2 EPWM odd channel output low level when EPWMx brake event happened #10 3 EPWM odd channel output high level when EPWMx brake event happened #11 BRKP0EEN Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 4 1 read-write 0 EPWMx_BRAKE0 pin as edge-detect brake source Disabled #0 1 EPWMx_BRAKE0 pin as edge-detect brake source Enabled #1 BRKP0LEN Enable BKP0 Pin As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 12 1 read-write 0 EPWMx_BRAKE0 pin as level-detect brake source Disabled #0 1 EPWMx_BRAKE0 pin as level-detect brake source Enabled #1 BRKP1EEN Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 5 1 read-write 0 EPWMx_BRAKE1 pin as edge-detect brake source Disabled #0 1 EPWMx_BRAKE1 pin as edge-detect brake source Enabled #1 BRKP1LEN Enable BKP1 Pin As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 13 1 read-write 0 EPWMx_BRAKE1 pin as level-detect brake source Disabled #0 1 EPWMx_BRAKE1 pin as level-detect brake source Enabled #1 CPO0EBEN Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 0 1 read-write 0 ACMP0_O as edge-detect brake source Disabled #0 1 ACMP0_O as edge-detect brake source Enabled #1 CPO0LBEN Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 8 1 read-write 0 ACMP0_O as level-detect brake source Disabled #0 1 ACMP0_O as level-detect brake source Enabled #1 CPO1EBEN Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 1 1 read-write 0 ACMP1_O as edge-detect brake source Disabled #0 1 ACMP1_O as edge-detect brake source Enabled #1 CPO1LBEN Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 9 1 read-write 0 ACMP1_O as level-detect brake source Disabled #0 1 ACMP1_O as level-detect brake source Enabled #1 EADC0EBEN Enable EADC0 Result Monitor (EADC0RM) As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 20 1 read-write 0 EADC0RM as edge-detect brake source Disabled #0 1 EADC0RM as edge-detect brake source Enabled #1 EADC0LBEN Enable EADC0 Result Monitor (EADC0RM) As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer to SYS_REGLCTL register. 28 1 read-write 0 EADC0RM as level-detect brake source Disabled #0 1 EADC0RM as level-detect brake source Enabled #1 SYSEBEN Enable System Fail As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 7 1 read-write 0 System Fail condition as edge-detect brake source Disabled #0 1 System Fail condition as edge-detect brake source Enabled #1 SYSLBEN Enable System Fail As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 15 1 read-write 0 System Fail condition as level-detect brake source Disabled #0 1 System Fail condition as level-detect brake source Enabled #1 EPWM_BRKCTL2_3 EPWM_BRKCTL2_3 EPWM Brake Edge Detect Control Register 2/3 0xCC -1 read-write n 0x0 0x0 EPWM_BRKCTL4_5 EPWM_BRKCTL4_5 EPWM Brake Edge Detect Control Register 4/5 0xD0 -1 read-write n 0x0 0x0 EPWM_CAPCTL EPWM_CAPCTL EPWM Capture Control Register 0x204 -1 read-write n 0x0 0x0 CAPEN0 Capture Function Enable Bits 0 1 read-write 0 Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN1 Capture Function Enable Bits 1 1 read-write 0 Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN2 Capture Function Enable Bits 2 1 read-write 0 Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN3 Capture Function Enable Bits 3 1 read-write 0 Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN4 Capture Function Enable Bits 4 1 read-write 0 Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPEN5 Capture Function Enable Bits 5 1 read-write 0 Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated #0 1 Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) #1 CAPINV0 Capture Inverter Enable Bits 8 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV1 Capture Inverter Enable Bits 9 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV2 Capture Inverter Enable Bits 10 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV3 Capture Inverter Enable Bits 11 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV4 Capture Inverter Enable Bits 12 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV5 Capture Inverter Enable Bits 13 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 FCRLDEN0 Falling Capture Reload Enable Bits 24 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN1 Falling Capture Reload Enable Bits 25 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN2 Falling Capture Reload Enable Bits 26 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN3 Falling Capture Reload Enable Bits 27 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN4 Falling Capture Reload Enable Bits 28 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN5 Falling Capture Reload Enable Bits 29 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 RCRLDEN0 Rising Capture Reload Enable Bits 16 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN1 Rising Capture Reload Enable Bits 17 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN2 Rising Capture Reload Enable Bits 18 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN3 Rising Capture Reload Enable Bits 19 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN4 Rising Capture Reload Enable Bits 20 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN5 Rising Capture Reload Enable Bits 21 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 EPWM_CAPIEN EPWM_CAPIEN EPWM Capture Interrupt Enable Register 0x250 -1 read-write n 0x0 0x0 CAPFIEN0 EPWM Capture Falling Latch Interrupt Enable Bits 8 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN1 EPWM Capture Falling Latch Interrupt Enable Bits 9 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN2 EPWM Capture Falling Latch Interrupt Enable Bits 10 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN3 EPWM Capture Falling Latch Interrupt Enable Bits 11 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN4 EPWM Capture Falling Latch Interrupt Enable Bits 12 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN5 EPWM Capture Falling Latch Interrupt Enable Bits 13 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPRIEN0 EPWM Capture Rising Latch Interrupt Enable Bits 0 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN1 EPWM Capture Rising Latch Interrupt Enable Bits 1 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN2 EPWM Capture Rising Latch Interrupt Enable Bits 2 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN3 EPWM Capture Rising Latch Interrupt Enable Bits 3 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN4 EPWM Capture Rising Latch Interrupt Enable Bits 4 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN5 EPWM Capture Rising Latch Interrupt Enable Bits 5 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 EPWM_CAPIF EPWM_CAPIF EPWM Capture Interrupt Flag Register 0x254 -1 read-write n 0x0 0x0 CFLIF0 EPWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 8 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF1 EPWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 9 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF2 EPWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 10 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF3 EPWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 11 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF4 EPWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 12 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF5 EPWM Capture Falling Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 13 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CRLIF0 EPWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 0 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF1 EPWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 1 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF2 EPWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 2 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF3 EPWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 3 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF4 EPWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 4 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF5 EPWM Capture Rising Latch Interrupt Flag Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. Note 2: This bit is cleared by writing 1 to it. 5 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 EPWM_CAPINEN EPWM_CAPINEN EPWM Capture Input Enable Register 0x200 -1 read-write n 0x0 0x0 CAPINEN0 Capture Input Enable Bits 0 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN1 Capture Input Enable Bits 1 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN2 Capture Input Enable Bits 2 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN3 Capture Input Enable Bits 3 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN4 Capture Input Enable Bits 4 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 CAPINEN5 Capture Input Enable Bits 5 1 read-write 0 EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0 #0 1 EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin #1 EPWM_CAPNF0 EPWM_CAPNF0 EPWM Capture Input Noise Filter Register 0 0x258 -1 read-write n 0x0 0x0 CAPNFCNT Capture Edge Detector Noise Filter Count The register bits control the capture filter counter to count from 0 to CAPNFCNT. 8 3 read-write CAPNFEN Capture Noise Filter Enable 0 1 read-write 0 Capture Noise Filter function Disabled #0 1 Capture Noise Filter function Enabled #1 CAPNFSEL Capture Edge Detector Noise Filter Clock Selection 4 3 read-write 0 Filter clock = PCLK #000 1 Filter clock = PCLK/2 #001 2 Filter clock = PCLK/4 #010 3 Filter clock = PCLK/8 #011 4 Filter clock = PCLK/16 #100 5 Filter clock = PCLK/32 #101 6 Filter clock = PCLK/64 #110 7 Filter clock = PCLK/128 #111 EPWM_CAPNF1 EPWM_CAPNF1 EPWM Capture Input Noise Filter Register 1 0x25C -1 read-write n 0x0 0x0 EPWM_CAPNF2 EPWM_CAPNF2 EPWM Capture Input Noise Filter Register 2 0x260 -1 read-write n 0x0 0x0 EPWM_CAPNF3 EPWM_CAPNF3 EPWM Capture Input Noise Filter Register 3 0x264 -1 read-write n 0x0 0x0 EPWM_CAPNF4 EPWM_CAPNF4 EPWM Capture Input Noise Filter Register 4 0x268 -1 read-write n 0x0 0x0 EPWM_CAPNF5 EPWM_CAPNF5 EPWM Capture Input Noise Filter Register 5 0x26C -1 read-write n 0x0 0x0 EPWM_CAPSTS EPWM_CAPSTS EPWM Capture Status Register 0x208 -1 read-only n 0x0 0x0 CFLIFOV0 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]). 8 1 read-only CFLIFOV1 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]). 9 1 read-only CFLIFOV2 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]). 10 1 read-only CFLIFOV3 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]). 11 1 read-only CFLIFOV4 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]). 12 1 read-only CFLIFOV5 Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]). 13 1 read-only CRLIFOV0 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]). 0 1 read-only CRLIFOV1 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]). 1 1 read-only CRLIFOV2 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]). 2 1 read-only CRLIFOV3 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]). 3 1 read-only CRLIFOV4 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]). 4 1 read-only CRLIFOV5 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]). 5 1 read-only EPWM_CLKPSC0 EPWM_CLKPSC0 EPWM Clock Prescale Register 0 0x290 -1 read-write n 0x0 0x0 CLKPSC EPWM Counter Clock Prescale The clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1). 0 12 read-write EPWM_CLKPSC0_1 EPWM_CLKPSC0_1 EPWM Clock Prescale Register 0/1 0x14 -1 read-write n 0x0 0x0 CLKPSC EPWM Counter Clock Prescale The clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1). 0 12 read-write EPWM_CLKPSC1 EPWM_CLKPSC1 EPWM Clock Prescale Register 1 0x294 -1 read-write n 0x0 0x0 EPWM_CLKPSC2 EPWM_CLKPSC2 EPWM Clock Prescale Register 2 0x298 -1 read-write n 0x0 0x0 EPWM_CLKPSC2_3 EPWM_CLKPSC2_3 EPWM Clock Prescale Register 2/3 0x18 -1 read-write n 0x0 0x0 EPWM_CLKPSC3 EPWM_CLKPSC3 EPWM Clock Prescale Register 3 0x29C -1 read-write n 0x0 0x0 EPWM_CLKPSC4 EPWM_CLKPSC4 EPWM Clock Prescale Register 4 0x2A0 -1 read-write n 0x0 0x0 EPWM_CLKPSC4_5 EPWM_CLKPSC4_5 EPWM Clock Prescale Register 4/5 0x1C -1 read-write n 0x0 0x0 EPWM_CLKPSC5 EPWM_CLKPSC5 EPWM Clock Prescale Register 5 0x2A4 -1 read-write n 0x0 0x0 EPWM_CLKSRC EPWM_CLKSRC EPWM Clock Source Register 0x10 -1 read-write n 0x0 0x0 ECLKSRC0 EPWM_CH01 External Clock Source Select 0 3 read-write 0 EPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC2 EPWM_CH23 External Clock Source Select 8 3 read-write 0 EPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC4 EPWM_CH45 External Clock Source Select 16 3 read-write 0 EPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 EPWM_CMPBUF0 EPWM_CMPBUF0 EPWM CMPDAT0 Buffer 0x31C -1 read-only n 0x0 0x0 CMPBUF EPWM Comparator Register Buffer (Read Only) Used as CMP active register. 0 16 read-only EPWM_CMPBUF1 EPWM_CMPBUF1 EPWM CMPDAT1 Buffer 0x320 -1 read-write n 0x0 0x0 EPWM_CMPBUF2 EPWM_CMPBUF2 EPWM CMPDAT2 Buffer 0x324 -1 read-write n 0x0 0x0 EPWM_CMPBUF3 EPWM_CMPBUF3 EPWM CMPDAT3 Buffer 0x328 -1 read-write n 0x0 0x0 EPWM_CMPBUF4 EPWM_CMPBUF4 EPWM CMPDAT4 Buffer 0x32C -1 read-write n 0x0 0x0 EPWM_CMPBUF5 EPWM_CMPBUF5 EPWM CMPDAT5 Buffer 0x330 -1 read-write n 0x0 0x0 EPWM_CMPDAT0 EPWM_CMPDAT0 EPWM Comparator Register 0 0x50 -1 read-write n 0x0 0x0 CMP EPWM Comparator Register CMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform, interrupt and trigger EADC/DAC. In complementary mode, EPWM_CMPDAT0, EPWM_CMPDAT2, EPWM_CMPDAT4 denote as first compared point, and EPWM_CMPDAT1, EPWM_CMPDAT3, EPWM_CMPDAT5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. 0 16 read-write EPWM_CMPDAT1 EPWM_CMPDAT1 EPWM Comparator Register 1 0x54 -1 read-write n 0x0 0x0 EPWM_CMPDAT2 EPWM_CMPDAT2 EPWM Comparator Register 2 0x58 -1 read-write n 0x0 0x0 EPWM_CMPDAT3 EPWM_CMPDAT3 EPWM Comparator Register 3 0x5C -1 read-write n 0x0 0x0 EPWM_CMPDAT4 EPWM_CMPDAT4 EPWM Comparator Register 4 0x60 -1 read-write n 0x0 0x0 EPWM_CMPDAT5 EPWM_CMPDAT5 EPWM Comparator Register 5 0x64 -1 read-write n 0x0 0x0 EPWM_CNT0 EPWM_CNT0 EPWM Counter Register 0 0x90 -1 read-only n 0x0 0x0 CNT EPWM Data Register (Read Only) User can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF EPWM Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is counting down #0 1 Counter is counting up #1 EPWM_CNT1 EPWM_CNT1 EPWM Counter Register 1 0x94 -1 read-write n 0x0 0x0 EPWM_CNT2 EPWM_CNT2 EPWM Counter Register 2 0x98 -1 read-write n 0x0 0x0 EPWM_CNT3 EPWM_CNT3 EPWM Counter Register 3 0x9C -1 read-write n 0x0 0x0 EPWM_CNT4 EPWM_CNT4 EPWM Counter Register 4 0xA0 -1 read-write n 0x0 0x0 EPWM_CNT5 EPWM_CNT5 EPWM Counter Register 5 0xA4 -1 read-write n 0x0 0x0 EPWM_CNTCLR EPWM_CNTCLR EPWM Clear Counter Register 0x24 -1 read-write n 0x0 0x0 CNTCLR0 Clear EPWM Counter Control Bit It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 0 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR1 Clear EPWM Counter Control Bit It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 1 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR2 Clear EPWM Counter Control Bit It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 2 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR3 Clear EPWM Counter Control Bit It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 3 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR4 Clear EPWM Counter Control Bit It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 4 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 CNTCLR5 Clear EPWM Counter Control Bit It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 5 1 read-write 0 No effect #0 1 Clear 16-bit EPWM counter to 0000H #1 EPWM_CNTEN EPWM_CNTEN EPWM Counter Enable Register 0x20 -1 read-write n 0x0 0x0 CNTEN0 EPWM Counter Enable Bits Note: In complementary mode, not only even channels, but also odd channels need to be enabled at the same time. 0 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN1 EPWM Counter Enable Bits Note: In complementary mode, not only even channels, but also odd channels need to be enabled at the same time. 1 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN2 EPWM Counter Enable Bits Note: In complementary mode, not only even channels, but also odd channels need to be enabled at the same time. 2 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN3 EPWM Counter Enable Bits Note: In complementary mode, not only even channels, but also odd channels need to be enabled at the same time. 3 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN4 EPWM Counter Enable Bits Note: In complementary mode, not only even channels, but also odd channels need to be enabled at the same time. 4 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 CNTEN5 EPWM Counter Enable Bits Note: In complementary mode, not only even channels, but also odd channels need to be enabled at the same time. 5 1 read-write 0 EPWM Counter and clock prescaler stop running #0 1 EPWM Counter and clock prescaler start running #1 EPWM_CPSCBUF0 EPWM_CPSCBUF0 EPWM CLKPSC0 Buffer 0x350 -1 read-only n 0x0 0x0 CPSCBUF EPWM Counter Clock Prescale Buffer Used as EPWM counter clock pre-scale active register. 0 12 read-only EPWM_CPSCBUF0_1 EPWM_CPSCBUF0_1 EPWM CLKPSC0_1 Buffer 0x334 -1 read-only n 0x0 0x0 CPSCBUF EPWM Counter Clock Prescale Buffer Used as EPWM counter clock pre-scale active register. 0 12 read-only EPWM_CPSCBUF1 EPWM_CPSCBUF1 EPWM CLKPSC1 Buffer 0x354 -1 read-write n 0x0 0x0 EPWM_CPSCBUF2 EPWM_CPSCBUF2 EPWM CLKPSC2 Buffer 0x358 -1 read-write n 0x0 0x0 EPWM_CPSCBUF2_3 EPWM_CPSCBUF2_3 EPWM CLKPSC2_3 Buffer 0x338 -1 read-write n 0x0 0x0 EPWM_CPSCBUF3 EPWM_CPSCBUF3 EPWM CLKPSC3 Buffer 0x35C -1 read-write n 0x0 0x0 EPWM_CPSCBUF4 EPWM_CPSCBUF4 EPWM CLKPSC4 Buffer 0x360 -1 read-write n 0x0 0x0 EPWM_CPSCBUF4_5 EPWM_CPSCBUF4_5 EPWM CLKPSC4_5 Buffer 0x33C -1 read-write n 0x0 0x0 EPWM_CPSCBUF5 EPWM_CPSCBUF5 EPWM CLKPSC5 Buffer 0x364 -1 read-write n 0x0 0x0 EPWM_CTL0 EPWM_CTL0 EPWM Control Register 0 0x0 -1 read-write n 0x0 0x0 CTRLD0 Center Re-load In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period. 0 1 read-write CTRLD1 Center Re-load In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period. 1 1 read-write CTRLD2 Center Re-load In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period. 2 1 read-write CTRLD3 Center Re-load In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period. 3 1 read-write CTRLD4 Center Re-load In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period. 4 1 read-write CTRLD5 Center Re-load In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period. 5 1 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect) If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode. Note: This bit is write protected. Refer toSYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable Bit (Write Protect) EPWM pin will keep output no matter ICE debug mode acknowledged or not. Note: This bit is write protected. Refer toSYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects EPWM output #0 1 ICE debug mode acknowledgement disabled #1 GROUPEN Group Function Enable Bit 24 1 read-write 0 The output waveform of each EPWM channel are independent #0 1 Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1 #1 IMMLDEN0 Immediately Load Enable Bits Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 16 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP #1 IMMLDEN1 Immediately Load Enable Bits Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 17 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP #1 IMMLDEN2 Immediately Load Enable Bits Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 18 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP #1 IMMLDEN3 Immediately Load Enable Bits Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 19 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP #1 IMMLDEN4 Immediately Load Enable Bits Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 20 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP #1 IMMLDEN5 Immediately Load Enable Bits Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 21 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP #1 WINLDEN0 Window Load Enable Bits 8 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN1 Window Load Enable Bits 9 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN2 Window Load Enable Bits 10 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN3 Window Load Enable Bits 11 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN4 Window Load Enable Bits 12 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 WINLDEN5 Window Load Enable Bits 13 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success #1 EPWM_CTL1 EPWM_CTL1 EPWM Control Register 1 0x4 -1 read-write n 0x0 0x0 CNTMODE0 EPWM Counter Mode 16 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE1 EPWM Counter Mode 17 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE2 EPWM Counter Mode 18 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE3 EPWM Counter Mode 19 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE4 EPWM Counter Mode 20 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE5 EPWM Counter Mode 21 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTTYPE0 EPWM Counter Behavior Type 0 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE1 EPWM Counter Behavior Type 2 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE2 EPWM Counter Behavior Type 4 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE3 EPWM Counter Behavior Type 6 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE4 EPWM Counter Behavior Type 8 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE5 EPWM Counter Behavior Type 10 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 OUTMODE0 EPWM Output Mode Each bit n controls the output mode of corresponding EPWM channel n. Note: When operating in group function, these bits must all set to the same mode. 24 1 read-write 0 EPWM independent mode #0 1 EPWM complementary mode #1 OUTMODE2 EPWM Output Mode Each bit n controls the output mode of corresponding EPWM channel n. Note: When operating in group function, these bits must all set to the same mode. 25 1 read-write 0 EPWM independent mode #0 1 EPWM complementary mode #1 OUTMODE4 EPWM Output Mode Each bit n controls the output mode of corresponding EPWM channel n. Note: When operating in group function, these bits must all set to the same mode. 26 1 read-write 0 EPWM independent mode #0 1 EPWM complementary mode #1 EPWM_DACTRGEN EPWM_DACTRGEN EPWM Trigger DAC Enable Register 0xF4 -1 read-write n 0x0 0x0 CDTRGE0 EPWM Compare Down Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 24 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE1 EPWM Compare Down Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 25 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE2 EPWM Compare Down Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 26 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE3 EPWM Compare Down Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 27 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE4 EPWM Compare Down Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 28 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CDTRGE5 EPWM Compare Down Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 29 1 read-write 0 EPWM Compare Down count point trigger DAC function Disabled #0 1 EPWM Compare Down count point trigger DAC function Enabled #1 CUTRGE0 EPWM Compare Up Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 16 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE1 EPWM Compare Up Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 17 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE2 EPWM Compare Up Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 18 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE3 EPWM Compare Up Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 19 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE4 EPWM Compare Up Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 20 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 CUTRGE5 EPWM Compare Up Count Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 21 1 read-write 0 EPWM Compare Up point trigger DAC function Disabled #0 1 EPWM Compare Up point trigger DAC function Enabled #1 PTE0 EPWM Period Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 8 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE1 EPWM Period Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 9 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE2 EPWM Period Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 10 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE3 EPWM Period Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 11 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE4 EPWM Period Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 12 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 PTE5 EPWM Period Point Trigger DAC Enable Bits EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 13 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE0 EPWM Zero Point Trigger DAC Enable Bits EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 0 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE1 EPWM Zero Point Trigger DAC Enable Bits EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE2 EPWM Zero Point Trigger DAC Enable Bits EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 2 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE3 EPWM Zero Point Trigger DAC Enable Bits EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 3 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE4 EPWM Zero Point Trigger DAC Enable Bits EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 4 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 ZTE5 EPWM Zero Point Trigger DAC Enable Bits EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 5 1 read-write 0 EPWM period point trigger DAC function Disabled #0 1 EPWM period point trigger DAC function Enabled #1 EPWM_DTCTL EPWM_DTCTL EPWM Dead-time Control Register 0x2C0 -1 read-write n 0x0 0x0 DTCKSELn Dead-time Clock Select for EPWM Pair (EPWM_CH(n/2), EPWM_CH(n/2+1)) (Write Protect) Note: This bit is write protected. Refer to REGWRPROT register. 16 1 read-write 0 Dead-time clock source from EPWM_CLK #0 1 Dead-time clock source from prescaler output #1 FDTEN0 Enable Falling Dead-time Insertion for EPWM Pair (EPWM_CH(n/2), EPWM_CH(n/2+1)) (Write Protect) Falling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. Note: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 Falling Dead-time insertion Disabled on the pin pair #0 1 Falling Dead-time insertion Enabled on the pin pair #1 FDTEN2 Enable Falling Dead-time Insertion for EPWM Pair (EPWM_CH(n/2), EPWM_CH(n/2+1)) (Write Protect) Falling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. Note: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 Falling Dead-time insertion Disabled on the pin pair #0 1 Falling Dead-time insertion Enabled on the pin pair #1 FDTEN4 Enable Falling Dead-time Insertion for EPWM Pair (EPWM_CH(n/2), EPWM_CH(n/2+1)) (Write Protect) Falling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. Note: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 Falling Dead-time insertion Disabled on the pin pair #0 1 Falling Dead-time insertion Enabled on the pin pair #1 RDTEN0 Enable Rising Dead-time Insertion for EPWM Pair (EPWM_CH(n/2), EPWM_CH(n/2+1)) (Write Protect) Rising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. Note: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 Rising Dead-time insertion Disabled on the pin pair #0 1 Rising Dead-time insertion Enabled on the pin pair #1 RDTEN2 Enable Rising Dead-time Insertion for EPWM Pair (EPWM_CH(n/2), EPWM_CH(n/2+1)) (Write Protect) Rising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. Note: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 Rising Dead-time insertion Disabled on the pin pair #0 1 Rising Dead-time insertion Enabled on the pin pair #1 RDTEN4 Enable Rising Dead-time Insertion for EPWM Pair (EPWM_CH(n/2), EPWM_CH(n/2+1)) (Write Protect) Rising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. Note: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 Rising Dead-time insertion Disabled on the pin pair #0 1 Rising Dead-time insertion Enabled on the pin pair #1 EPWM_DTCTL0_1 EPWM_DTCTL0_1 EPWM Dead-time Control Register 0/1 0x70 -1 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect) Note: This bit is write protected. Refer to REGWRPROT register. 24 1 read-write 0 Dead-time clock source from EPWM_CLK #0 1 Dead-time clock source from prescaler output #1 DTCNT Dead-time Counter (Write Protect) The dead-time can be calculated from the following formula: Note: This bit is write protected. Refer to SYS_REGLCTL register. 0 12 read-write DTEN Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect) Dead-time insertion is only active when this pair of complementary EPWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. Note: This bit is write protected. Refer to SYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 EPWM_DTCTL2_3 EPWM_DTCTL2_3 EPWM Dead-time Control Register 2/3 0x74 -1 read-write n 0x0 0x0 EPWM_DTCTL4_5 EPWM_DTCTL4_5 EPWM Dead-time Control Register 4/5 0x78 -1 read-write n 0x0 0x0 EPWM_EADCPSC0 EPWM_EADCPSC0 EPWM Trigger EADC Prescale Register 0 0x188 -1 read-write n 0x0 0x0 EADCPSC0 EPWM Channel 0 Trigger EADC Prescale The register sets the count number which defines (EADCPSC0+1) times of EPWM_CH0 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF0. 0 4 read-write EADCPSC1 EPWM Channel 1 Trigger EADC Prescale The register sets the count number which defines (EADCPSC1+1) times of EPWM_CH1 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF1. 8 4 read-write EADCPSC2 EPWM Channel 2 Trigger EADC Prescale The register sets the count number which defines (EADCPSC2+1) times of EPWM_CH2 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF2. 16 4 read-write EADCPSC3 EPWM Channel 3 Trigger EADC Prescale The register sets the count number which defines (EADCPSC3+1) times of EPWM_CH3 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF3. 24 4 read-write EPWM_EADCPSC1 EPWM_EADCPSC1 EPWM Trigger EADC Prescale Register 1 0x18C -1 read-write n 0x0 0x0 EADCPSC4 EPWM Channel 4 Trigger EADC Prescale The register sets the count number which defines (EADCPSC4+1) times of EPWM_CH4 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF4. 0 4 read-write EADCPSC5 EPWM Channel 5 Trigger EADC Prescale The register sets the count number which defines (EADCPSC5+1) times of EPWM_CH5 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF5. 8 4 read-write EPWM_EADCPSCCTL EPWM_EADCPSCCTL EPWM Trigger EADC Prescale Control Register 0x184 -1 read-write n 0x0 0x0 PSCEN0 EPWM Trigger EADC Pre-scale Function Enable Bits 0 1 read-write 0 EPWM Trigger EADC Pre-scale function Disabled #0 1 EPWM Trigger EADC Pre-scale function Enabled #1 PSCEN1 EPWM Trigger EADC Pre-scale Function Enable Bits 1 1 read-write 0 EPWM Trigger EADC Pre-scale function Disabled #0 1 EPWM Trigger EADC Pre-scale function Enabled #1 PSCEN2 EPWM Trigger EADC Pre-scale Function Enable Bits 2 1 read-write 0 EPWM Trigger EADC Pre-scale function Disabled #0 1 EPWM Trigger EADC Pre-scale function Enabled #1 PSCEN3 EPWM Trigger EADC Pre-scale Function Enable Bits 3 1 read-write 0 EPWM Trigger EADC Pre-scale function Disabled #0 1 EPWM Trigger EADC Pre-scale function Enabled #1 PSCEN4 EPWM Trigger EADC Pre-scale Function Enable Bits 4 1 read-write 0 EPWM Trigger EADC Pre-scale function Disabled #0 1 EPWM Trigger EADC Pre-scale function Enabled #1 PSCEN5 EPWM Trigger EADC Pre-scale Function Enable Bits 5 1 read-write 0 EPWM Trigger EADC Pre-scale function Disabled #0 1 EPWM Trigger EADC Pre-scale function Enabled #1 EPWM_EADCPSCNT0 EPWM_EADCPSCNT0 EPWM Trigger EADC Prescale Counter Register 0 0x190 -1 read-write n 0x0 0x0 PSCNT0 EPWM Trigger EADC Prescale Counter 0 User can monitor PSCNT0 to know the current value in 4-bit trigger EADC prescale counter. Note 1: user can write only when PSCEN0 is 0. Note 2: Write data limitation: PSCNT0 EADCPSC0. 0 4 read-write PSCNT1 EPWM Trigger EADC Prescale Counter 1 User can monitor PSCNT1 to know the current value in 4-bit trigger EADC prescale counter. Note 1: user can write only when PSCEN1 is 0. Note 2: Write data limitation: PSCNT1 EADCPSC1. 8 4 read-write PSCNT2 EPWM Trigger EADC Prescale Counter 2 User can monitor PSCNT2 to know the current value in 4-bit trigger EADC prescale counter. Note 1: user can write only when PSCEN2 is 0. Note 2: Write data limitation: PSCNT2 EADCPSC2. 16 4 read-write PSCNT3 EPWM Trigger EADC Prescale Counter 3 User can monitor PSCNT3 to know the current value in 4-bit trigger EADC prescale counter. Note 1: user can write only when PSCEN3 is 0. Note 2: Write data limitation: PSCNT3 EADCPSC3. 24 4 read-write EPWM_EADCPSCNT1 EPWM_EADCPSCNT1 EPWM Trigger EADC Prescale Counter Register 1 0x194 -1 read-write n 0x0 0x0 PSCNT4 EPWM Trigger EADC Prescale Counter 4 User can monitor PSCNT4 to know the current value in 4-bit trigger EADC prescale counter. Note 1: user can write only when PSCEN4 is 0. Note 2: Write data limitation: PSCNT4 EADCPSC4. 0 4 read-write PSCNT5 EPWM Trigger EADC Prescale Counter 5 User can monitor PSCNT5 to know the current value in 4-bit trigger EADC prescale counter. Note 1: user can write only when PSCEN5 is 0. Note 2: Write data limitation: PSCNT5 EADCPSC5. 8 4 read-write EPWM_EADCTS0 EPWM_EADCTS0 EPWM Trigger EADC Source Select Register 0 0xF8 -1 read-write n 0x0 0x0 TRGEN0 EPWM_CH0 Trigger EADC Enable Bit 7 1 read-write 0 EPWM_CH0 Trigger EADC function Disabled #0 1 EPWM_CH0 Trigger EADC function Enabled #1 TRGEN1 EPWM_CH1 Trigger EADC Enable Bit 15 1 read-write 0 EPWM_CH1 Trigger EADC function Disabled #0 1 EPWM_CH1 Trigger EADC function Enabled #1 TRGEN2 EPWM_CH2 Trigger EADC Enable Bit 23 1 read-write 0 EPWM_CH2 Trigger EADC function Disabled #0 1 EPWM_CH2 Trigger EADC function Enabled #1 TRGEN3 EPWM_CH3 Trigger EADC Enable Bit 31 1 read-write 0 EPWM_CH3 Trigger EADC function Disabled #0 1 EPWM_CH3 Trigger EADC function Enabled #1 TRGSEL0 EPWM_CH0 Trigger EADC Source Select 0 4 read-write 0 EPWM_CH0 zero point #0000 1 EPWM_CH0 period point #0001 2 EPWM_CH0 zero or period point #0010 3 EPWM_CH0 up-count compared point #0011 4 EPWM_CH0 down-count compared point #0100 5 EPWM_CH1 zero point #0101 6 EPWM_CH1 period point #0110 7 EPWM_CH1 zero or period point #0111 8 EPWM_CH1 up-count compared point #1000 9 EPWM_CH1 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL1 EPWM_CH1 Trigger EADC Source Select 8 4 read-write 0 EPWM_CH0 zero point #0000 1 EPWM_CH0 period point #0001 2 EPWM_CH0 zero or period point #0010 3 EPWM_CH0 up-count compared point #0011 4 EPWM_CH0 down-count compared point #0100 5 EPWM_CH1 zero point #0101 6 EPWM_CH1 period point #0110 7 EPWM_CH1 zero or period point #0111 8 EPWM_CH1 up-count compared point #1000 9 EPWM_CH1 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL2 EPWM_CH2 Trigger EADC Source Select 16 4 read-write 0 EPWM_CH2 zero point #0000 1 EPWM_CH2 period point #0001 2 EPWM_CH2 zero or period point #0010 3 EPWM_CH2 up-count compared point #0011 4 EPWM_CH2 down-count compared point #0100 5 EPWM_CH3 zero point #0101 6 EPWM_CH3 period point #0110 7 EPWM_CH3 zero or period point #0111 8 EPWM_CH3 up-count compared point #1000 9 EPWM_CH3 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL3 EPWM_CH3 Trigger EADC Source Select 24 4 read-write 0 EPWM_CH2 zero point #0000 1 EPWM_CH2 period point #0001 2 EPWM_CH2 zero or period point #0010 3 EPWM_CH2 up-count compared point #0011 4 EPWM_CH2 down-count compared point #0100 5 EPWM_CH3 zero point #0101 6 EPWM_CH3 period point #0110 7 EPWM_CH3 zero or period point #0111 8 EPWM_CH3 up-count compared point #1000 9 EPWM_CH3 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 EPWM_EADCTS1 EPWM_EADCTS1 EPWM Trigger EADC Source Select Register 1 0xFC -1 read-write n 0x0 0x0 TRGEN4 EPWM_CH4 Trigger EADC Enable Bit 7 1 read-write 0 EPWM_CH4 Trigger EADC function Disabled #0 1 EPWM_CH4 Trigger EADC function Enabled #1 TRGEN5 EPWM_CH5 Trigger EADC Enable Bit 15 1 read-write 0 EPWM_CH5 Trigger EADC function Disabled #0 1 EPWM_CH5 Trigger EADC function Enabled #1 TRGSEL4 EPWM_CH4 Trigger EADC Source Select 0 4 read-write 0 EPWM_CH4 zero point #0000 1 EPWM_CH4 period point #0001 2 EPWM_CH4 zero or period point #0010 3 EPWM_CH4 up-count compared point #0011 4 EPWM_CH4 down-count compared point #0100 5 EPWM_CH5 zero point #0101 6 EPWM_CH5 period point #0110 7 EPWM_CH5 zero or period point #0111 8 EPWM_CH5 up-count compared point #1000 9 EPWM_CH5 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 TRGSEL5 EPWM_CH5 Trigger EADC Source Select 8 4 read-write 0 EPWM_CH4 zero point #0000 1 EPWM_CH4 period point #0001 2 EPWM_CH4 zero or period point #0010 3 EPWM_CH4 up-count compared point #0011 4 EPWM_CH4 down-count compared point #0100 5 EPWM_CH5 zero point #0101 6 EPWM_CH5 period point #0110 7 EPWM_CH5 zero or period point #0111 8 EPWM_CH5 up-count compared point #1000 9 EPWM_CH5 down-count compared point #1001 10 EPWM_CH0 up-count free trigger compared point #1010 11 EPWM_CH0 down-count free trigger compared point #1011 12 EPWM_CH2 up-count free trigger compared point #1100 13 EPWM_CH2 down-count free trigger compared point #1101 14 EPWM_CH4 up-count free trigger compared point #1110 15 EPWM_CH4 down-count free trigger compared point #1111 EPWM_EXTETCTL0 EPWM_EXTETCTL0 EPWM External Event Trigger Control Register 0 0x270 -1 read-write n 0x0 0x0 CNTACTS Counter Action Selection 4 2 read-write 0 Counter reset #00 1 Counter start #01 2 Counter reset and start #10 3 Reseved #11 EXETEN External Event Trigger Enable Bit 0 1 read-write 0 External Event Trigger function Disabled #0 1 External Event Trigger function Enabled #1 EXTTRGS External Trigger Selection 8 4 read-write 0 INT0 #0000 1 INT1 #0001 2 INT2 #0010 3 INT3 #0011 4 INT4 #0100 5 INT5 #0101 6 INT6 #0110 7 INT7 #0111 EPWM_EXTETCTL1 EPWM_EXTETCTL1 EPWM External Event Trigger Control Register 1 0x274 -1 read-write n 0x0 0x0 EPWM_EXTETCTL2 EPWM_EXTETCTL2 EPWM External Event Trigger Control Register 2 0x278 -1 read-write n 0x0 0x0 EPWM_EXTETCTL3 EPWM_EXTETCTL3 EPWM External Event Trigger Control Register 3 0x27C -1 read-write n 0x0 0x0 EPWM_EXTETCTL4 EPWM_EXTETCTL4 EPWM External Event Trigger Control Register 4 0x280 -1 read-write n 0x0 0x0 EPWM_EXTETCTL5 EPWM_EXTETCTL5 EPWM External Event Trigger Control Register 5 0x284 -1 read-write n 0x0 0x0 EPWM_FAILBRK EPWM_FAILBRK EPWM System Fail Brake Control Register 0xC4 -1 read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit 1 1 read-write 0 Brake Function triggered by BOD Disabled #0 1 Brake Function triggered by BOD Enabled #1 CORBRKEN Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit 3 1 read-write 0 Brake Function triggered by Core lockup detection Disabled #0 1 Brake Function triggered by Core lockup detection Enabled #1 CSSBRKEN Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit 0 1 read-write 0 Brake Function triggered by CSS detection Disabled #0 1 Brake Function triggered by CSS detection Enabled #1 RAMBRKEN SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit 2 1 read-write 0 Brake Function triggered by SRAM parity error detection Disabled #0 1 Brake Function triggered by SRAM parity error detection Enabled #1 EPWM_FCAPDAT0 EPWM_FCAPDAT0 EPWM Falling Capture Data Register 0 0x210 -1 read-only n 0x0 0x0 FCAPDAT EPWM Falling Capture Data Register (Read Only) When falling capture condition happened, the EPWM counter value will be saved in this register. 0 16 read-only EPWM_FCAPDAT1 EPWM_FCAPDAT1 EPWM Falling Capture Data Register 1 0x218 -1 read-write n 0x0 0x0 EPWM_FCAPDAT2 EPWM_FCAPDAT2 EPWM Falling Capture Data Register 2 0x220 -1 read-write n 0x0 0x0 EPWM_FCAPDAT3 EPWM_FCAPDAT3 EPWM Falling Capture Data Register 3 0x228 -1 read-write n 0x0 0x0 EPWM_FCAPDAT4 EPWM_FCAPDAT4 EPWM Falling Capture Data Register 4 0x230 -1 read-write n 0x0 0x0 EPWM_FCAPDAT5 EPWM_FCAPDAT5 EPWM Falling Capture Data Register 5 0x238 -1 read-write n 0x0 0x0 EPWM_FDCTL0 EPWM_FDCTL0 EPWM Fault Detect Control Register 0 0x164 -1 read-write n 0x0 0x0 DGSMPCYC Deglitch Sampling Cycle FDCKS is set to 0: Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times FDCKS is set to 1: Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times Note: CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 16 3 read-write FDCKSEL EPWM Channel Fault Detect Clock Select 28 2 read-write 0 FLT_CLK/1 #00 1 FLT_CLK/2 #01 2 FLT_CLK/4 #10 3 FLT_CLK/8 #11 FDDGEN Fault Detect Deglitch Enable Bit 31 1 read-write 0 Fault detect deglitch function Disabled #0 1 Fault detect deglitch function Enabled #1 FDMSKEN Fault Detect Mask Enable Bit 15 1 read-write 0 Fault detect mask function Disabled #0 1 Fault detect mask function Enabled #1 TRMSKCNT Transition Mask Counter The fault detect result will be masked before counter count from 0 to TRMSKCNT. FDCKS is set to 0: Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2) FDCKS is set to 1: Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT+2) Note: CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 0 7 read-write EPWM_FDCTL1 EPWM_FDCTL1 EPWM Fault Detect Control Register 1 0x168 -1 read-write n 0x0 0x0 EPWM_FDCTL2 EPWM_FDCTL2 EPWM Fault Detect Control Register 2 0x16C -1 read-write n 0x0 0x0 EPWM_FDCTL3 EPWM_FDCTL3 EPWM Fault Detect Control Register 3 0x170 -1 read-write n 0x0 0x0 EPWM_FDCTL4 EPWM_FDCTL4 EPWM Fault Detect Control Register 4 0x174 -1 read-write n 0x0 0x0 EPWM_FDCTL5 EPWM_FDCTL5 EPWM Fault Detect Control Register 5 0x178 -1 read-write n 0x0 0x0 EPWM_FDEN EPWM_FDEN EPWM Fault Detect Enable Register 0x160 -1 read-write n 0x0 0x0 FDCKS0 EPWM Channel n Fault Detect Clock Source Select Bits 16 1 read-write 0 EPWMx_CLK, x denotes 0 or 1 #0 1 EPWMx_CLK divide by prescaler, x denotes 0 or 1 #1 FDCKS1 EPWM Channel n Fault Detect Clock Source Select Bits 17 1 read-write 0 EPWMx_CLK, x denotes 0 or 1 #0 1 EPWMx_CLK divide by prescaler, x denotes 0 or 1 #1 FDCKS2 EPWM Channel n Fault Detect Clock Source Select Bits 18 1 read-write 0 EPWMx_CLK, x denotes 0 or 1 #0 1 EPWMx_CLK divide by prescaler, x denotes 0 or 1 #1 FDCKS3 EPWM Channel n Fault Detect Clock Source Select Bits 19 1 read-write 0 EPWMx_CLK, x denotes 0 or 1 #0 1 EPWMx_CLK divide by prescaler, x denotes 0 or 1 #1 FDCKS4 EPWM Channel n Fault Detect Clock Source Select Bits 20 1 read-write 0 EPWMx_CLK, x denotes 0 or 1 #0 1 EPWMx_CLK divide by prescaler, x denotes 0 or 1 #1 FDCKS5 EPWM Channel n Fault Detect Clock Source Select Bits 21 1 read-write 0 EPWMx_CLK, x denotes 0 or 1 #0 1 EPWMx_CLK divide by prescaler, x denotes 0 or 1 #1 FDEN0 EPWM Fault Detect Function Enable Bits 0 1 read-write 0 Fault detect function Disabled #0 1 Fault detect function Enabled #1 FDEN1 EPWM Fault Detect Function Enable Bits 1 1 read-write 0 Fault detect function Disabled #0 1 Fault detect function Enabled #1 FDEN2 EPWM Fault Detect Function Enable Bits 2 1 read-write 0 Fault detect function Disabled #0 1 Fault detect function Enabled #1 FDEN3 EPWM Fault Detect Function Enable Bits 3 1 read-write 0 Fault detect function Disabled #0 1 Fault detect function Enabled #1 FDEN4 EPWM Fault Detect Function Enable Bits 4 1 read-write 0 Fault detect function Disabled #0 1 Fault detect function Enabled #1 FDEN5 EPWM Fault Detect Function Enable Bits 5 1 read-write 0 Fault detect function Disabled #0 1 Fault detect function Enabled #1 FDODIS0 EPWM Channel n Output Fault Detect Disable Bits 8 1 read-write 0 EPWM detect fault and output Enabled #0 1 EPWM detect fault and output Disabled #1 FDODIS1 EPWM Channel n Output Fault Detect Disable Bits 9 1 read-write 0 EPWM detect fault and output Enabled #0 1 EPWM detect fault and output Disabled #1 FDODIS2 EPWM Channel n Output Fault Detect Disable Bits 10 1 read-write 0 EPWM detect fault and output Enabled #0 1 EPWM detect fault and output Disabled #1 FDODIS3 EPWM Channel n Output Fault Detect Disable Bits 11 1 read-write 0 EPWM detect fault and output Enabled #0 1 EPWM detect fault and output Disabled #1 FDODIS4 EPWM Channel n Output Fault Detect Disable Bits 12 1 read-write 0 EPWM detect fault and output Enabled #0 1 EPWM detect fault and output Disabled #1 FDODIS5 EPWM Channel n Output Fault Detect Disable Bits 13 1 read-write 0 EPWM detect fault and output Enabled #0 1 EPWM detect fault and output Disabled #1 EPWM_FDIEN EPWM_FDIEN EPWM Fault Detect Interrupt Enable Register 0x17C -1 read-write n 0x0 0x0 FDIENn EPWM Channel n Fault Detect Interrupt Enable Bit 0 1 read-write 0 EPWM Channel n Fault Detect Interrupt Disabled #0 1 EPWM Channel n Fault Detect Interrupt Enabled #1 EPWM_FDSTS EPWM_FDSTS EPWM Fault Detect Interrupt Flag Register 0x180 -1 read-write n 0x0 0x0 FDIFn EPWM Channel n Fault Detect Interrupt Flag Bit Fault Detect Interrupt Flag will be set when EPWM output short. Software can clear this bit by writing 1 to it. 0 6 read-write EPWM_FDTCNT0_1 EPWM_FDTCNT0_1 EPWM Falling Dead-time Counter Register 0/1 0x2B4 -1 read-write n 0x0 0x0 FDTCNT Falling Dead-time Counter (Write Protect) The dead-time can be calculated from the following formula: Note: This bit is write protected. Refer to SYS_REGLCTL register. 0 12 read-write EPWM_FDTCNT2_3 EPWM_FDTCNT2_3 EPWM Falling Dead-time Counter Register 2/3 0x2B8 -1 read-write n 0x0 0x0 EPWM_FDTCNT4_5 EPWM_FDTCNT4_5 EPWM Falling Dead-time Counter Register 4/5 0x2BC -1 read-write n 0x0 0x0 EPWM_FTCBUF0_1 EPWM_FTCBUF0_1 EPWM FTCMPDAT0_1 Buffer 0x340 -1 read-only n 0x0 0x0 FTCMPBUF EPWM FTCMPDAT Buffer (Read Only) Used as FTCMP active buffer. 0 16 read-only EPWM_FTCBUF2_3 EPWM_FTCBUF2_3 EPWM FTCMPDAT2_3 Buffer 0x344 -1 read-write n 0x0 0x0 EPWM_FTCBUF4_5 EPWM_FTCBUF4_5 EPWM FTCMPDAT4_5 Buffer 0x348 -1 read-write n 0x0 0x0 EPWM_FTCI EPWM_FTCI EPWM FTCMPDAT Indicator Register 0x34C -1 read-write n 0x0 0x0 FTCMD0 EPWM FTCMPDAT Down Indicator Indicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 8 1 read-write FTCMD2 EPWM FTCMPDAT Down Indicator Indicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 9 1 read-write FTCMD4 EPWM FTCMPDAT Down Indicator Indicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 10 1 read-write FTCMU0 EPWM FTCMPDAT Up Indicator Indicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 0 1 read-write FTCMU2 EPWM FTCMPDAT Up Indicator Indicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 1 1 read-write FTCMU4 EPWM FTCMPDAT Up Indicator Indicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. 2 1 read-write EPWM_FTCMPDAT0_1 EPWM_FTCMPDAT0_1 EPWM Free Trigger Compare Register 0/1 0x100 -1 read-write n 0x0 0x0 FTCMP EPWM Free Trigger Compare Register 0 16 read-write EPWM_FTCMPDAT2_3 EPWM_FTCMPDAT2_3 EPWM Free Trigger Compare Register 2/3 0x104 -1 read-write n 0x0 0x0 EPWM_FTCMPDAT4_5 EPWM_FTCMPDAT4_5 EPWM Free Trigger Compare Register 4/5 0x108 -1 read-write n 0x0 0x0 EPWM_IFA0 EPWM_IFA0 EPWM Interrupt Flag Accumulator Register 0 0x130 -1 read-write n 0x0 0x0 IFACNT EPWM_CHn Interrupt Flag Counter The register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.EPWM flag will be set in every IFACNT[15:0] times of EPWM period. 0 16 read-write IFAEN EPWM_CHn Interrupt Flag Accumulator Enable Bit Note: Disabling this bit will reset related EPWM_IFACNT 31 1 read-write 0 EPWM_CHn interrupt flag accumulator Disabled #0 1 EPWM_CHn interrupt flag accumulator Enabled #1 IFASEL EPWM_CHn Interrupt Flag Accumulator Source Select 28 2 read-write 0 EPWM_CHn zero point #00 1 EPWM_CHn period in channel n #01 2 EPWM_CHn up-count compared point #10 3 EPWM_CHn down-count compared point #11 STPMOD EPWM_CHn Accumulator Stop Mode Enable Bit 24 1 read-write 0 EPWM_CHn Stop Mode Disabled #0 1 EPWM_CHn Stop Mode Enabled #1 EPWM_IFA1 EPWM_IFA1 EPWM Interrupt Flag Accumulator Register 1 0x134 -1 read-write n 0x0 0x0 EPWM_IFA2 EPWM_IFA2 EPWM Interrupt Flag Accumulator Register 2 0x138 -1 read-write n 0x0 0x0 EPWM_IFA3 EPWM_IFA3 EPWM Interrupt Flag Accumulator Register 3 0x13C -1 read-write n 0x0 0x0 EPWM_IFA4 EPWM_IFA4 EPWM Interrupt Flag Accumulator Register 4 0x140 -1 read-write n 0x0 0x0 EPWM_IFA5 EPWM_IFA5 EPWM Interrupt Flag Accumulator Register 5 0x144 -1 read-write n 0x0 0x0 EPWM_IFACNT0 EPWM_IFACNT0 EPWM Interrupt Flag Accumulator Counter 0 0x368 -1 read-only n 0x0 0x0 ACUCNT Accumulator Counter (Read Only) This value indicates how many interrupt are accumulated when using interrupt flag accumulator function. 0 16 read-only EPWM_IFACNT1 EPWM_IFACNT1 EPWM Interrupt Flag Accumulator Counter 1 0x36C -1 read-write n 0x0 0x0 EPWM_IFACNT2 EPWM_IFACNT2 EPWM Interrupt Flag Accumulator Counter 2 0x370 -1 read-write n 0x0 0x0 EPWM_IFACNT3 EPWM_IFACNT3 EPWM Interrupt Flag Accumulator Counter 3 0x374 -1 read-write n 0x0 0x0 EPWM_IFACNT4 EPWM_IFACNT4 EPWM Interrupt Flag Accumulator Counter 4 0x378 -1 read-write n 0x0 0x0 EPWM_IFACNT5 EPWM_IFACNT5 EPWM Interrupt Flag Accumulator Counter 5 0x37C -1 read-write n 0x0 0x0 EPWM_INTEN0 EPWM_INTEN0 EPWM Interrupt Enable Register 0 0xE0 -1 read-write n 0x0 0x0 CMPDIEN0 EPWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 24 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN1 EPWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 25 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN2 EPWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 26 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN3 EPWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 27 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN4 EPWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 28 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN5 EPWM Compare Down Count Interrupt Enable Bits Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 29 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPUIEN0 EPWM Compare Up Count Interrupt Enable Bits Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 16 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN1 EPWM Compare Up Count Interrupt Enable Bits Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 17 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN2 EPWM Compare Up Count Interrupt Enable Bits Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 18 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN3 EPWM Compare Up Count Interrupt Enable Bits Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 19 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN4 EPWM Compare Up Count Interrupt Enable Bits Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 20 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN5 EPWM Compare Up Count Interrupt Enable Bits Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 21 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 PIEN0 EPWM Period Point Interrupt Enable Bits Note 1: When up-down counter type period point means center point. Note 2: Odd channels will read always 0 at complementary mode. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN1 EPWM Period Point Interrupt Enable Bits Note 1: When up-down counter type period point means center point. Note 2: Odd channels will read always 0 at complementary mode. 9 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN2 EPWM Period Point Interrupt Enable Bits Note 1: When up-down counter type period point means center point. Note 2: Odd channels will read always 0 at complementary mode. 10 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN3 EPWM Period Point Interrupt Enable Bits Note 1: When up-down counter type period point means center point. Note 2: Odd channels will read always 0 at complementary mode. 11 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN4 EPWM Period Point Interrupt Enable Bits Note 1: When up-down counter type period point means center point. Note 2: Odd channels will read always 0 at complementary mode. 12 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN5 EPWM Period Point Interrupt Enable Bits Note 1: When up-down counter type period point means center point. Note 2: Odd channels will read always 0 at complementary mode. 13 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 EPWM Zero Point Interrupt Enable Bits Note: Odd channels will read always 0 at complementary mode. 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN1 EPWM Zero Point Interrupt Enable Bits Note: Odd channels will read always 0 at complementary mode. 1 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN2 EPWM Zero Point Interrupt Enable Bits Note: Odd channels will read always 0 at complementary mode. 2 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN3 EPWM Zero Point Interrupt Enable Bits Note: Odd channels will read always 0 at complementary mode. 3 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN4 EPWM Zero Point Interrupt Enable Bits Note: Odd channels will read always 0 at complementary mode. 4 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN5 EPWM Zero Point Interrupt Enable Bits Note: Odd channels will read always 0 at complementary mode. 5 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 EPWM_INTEN1 EPWM_INTEN1 EPWM Interrupt Enable Register 1 0xE4 -1 read-write n 0x0 0x0 BRKEIEN0_1 EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 0 1 read-write 0 Edge-detect Brake interrupt for channel0/1 Disabled #0 1 Edge-detect Brake interrupt for channel0/1 Enabled #1 BRKEIEN2_3 EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 1 1 read-write 0 Edge-detect Brake interrupt for channel2/3 Disabled #0 1 Edge-detect Brake interrupt for channel2/3 Enabled #1 BRKEIEN4_5 EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 2 1 read-write 0 Edge-detect Brake interrupt for channel4/5 Disabled #0 1 Edge-detect Brake interrupt for channel4/5 Enabled #1 BRKLIEN0_1 EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 8 1 read-write 0 Level-detect Brake interrupt for channel0/1 Disabled #0 1 Level-detect Brake interrupt for channel0/1 Enabled #1 BRKLIEN2_3 EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 9 1 read-write 0 Level-detect Brake interrupt for channel2/3 Disabled #0 1 Level-detect Brake interrupt for channel2/3 Enabled #1 BRKLIEN4_5 EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 10 1 read-write 0 Level-detect Brake interrupt for channel4/5 Disabled #0 1 Level-detect Brake interrupt for channel4/5 Enabled #1 EPWM_INTSTS0 EPWM_INTSTS0 EPWM Interrupt Flag Register 0 0xE8 -1 read-write n 0x0 0x0 CMPDIF0 EPWM Compare Down Count Interrupt Flag Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. Note: In complementary mode, CMPDIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 24 1 read-write CMPDIF1 EPWM Compare Down Count Interrupt Flag Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. Note: In complementary mode, CMPDIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 25 1 read-write CMPDIF2 EPWM Compare Down Count Interrupt Flag Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. Note: In complementary mode, CMPDIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 26 1 read-write CMPDIF3 EPWM Compare Down Count Interrupt Flag Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. Note: In complementary mode, CMPDIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 27 1 read-write CMPDIF4 EPWM Compare Down Count Interrupt Flag Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. Note: In complementary mode, CMPDIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 28 1 read-write CMPDIF5 EPWM Compare Down Count Interrupt Flag Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. Note: In complementary mode, CMPDIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 29 1 read-write CMPUIF0 EPWM Compare Up Count Interrupt Flag Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. Note: In complementary mode, CMPUIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 16 1 read-write CMPUIF1 EPWM Compare Up Count Interrupt Flag Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. Note: In complementary mode, CMPUIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 17 1 read-write CMPUIF2 EPWM Compare Up Count Interrupt Flag Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. Note: In complementary mode, CMPUIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 18 1 read-write CMPUIF3 EPWM Compare Up Count Interrupt Flag Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. Note: In complementary mode, CMPUIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 19 1 read-write CMPUIF4 EPWM Compare Up Count Interrupt Flag Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. Note: In complementary mode, CMPUIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 20 1 read-write CMPUIF5 EPWM Compare Up Count Interrupt Flag Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. Note: In complementary mode, CMPUIF1, 3, 5 will be set when the corresponding counter enable bits are set at the same time with even channels 21 1 read-write PIF0 EPWM Period Point Interrupt Flag This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. Note: This bit can be cleared to 0 by software writing 1. 8 1 read-write PIF1 EPWM Period Point Interrupt Flag This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. Note: This bit can be cleared to 0 by software writing 1. 9 1 read-write PIF2 EPWM Period Point Interrupt Flag This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. Note: This bit can be cleared to 0 by software writing 1. 10 1 read-write PIF3 EPWM Period Point Interrupt Flag This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. Note: This bit can be cleared to 0 by software writing 1. 11 1 read-write PIF4 EPWM Period Point Interrupt Flag This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. Note: This bit can be cleared to 0 by software writing 1. 12 1 read-write PIF5 EPWM Period Point Interrupt Flag This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. Note: This bit can be cleared to 0 by software writing 1. 13 1 read-write ZIF0 EPWM Zero Point Interrupt Flag This bit is set by hardware when EPWM counter reaches 0. Note: This bit can be cleared to 0 by software writing 1 0 1 read-write ZIF1 EPWM Zero Point Interrupt Flag This bit is set by hardware when EPWM counter reaches 0. Note: This bit can be cleared to 0 by software writing 1 1 1 read-write ZIF2 EPWM Zero Point Interrupt Flag This bit is set by hardware when EPWM counter reaches 0. Note: This bit can be cleared to 0 by software writing 1 2 1 read-write ZIF3 EPWM Zero Point Interrupt Flag This bit is set by hardware when EPWM counter reaches 0. Note: This bit can be cleared to 0 by software writing 1 3 1 read-write ZIF4 EPWM Zero Point Interrupt Flag This bit is set by hardware when EPWM counter reaches 0. Note: This bit can be cleared to 0 by software writing 1 4 1 read-write ZIF5 EPWM Zero Point Interrupt Flag This bit is set by hardware when EPWM counter reaches 0. Note: This bit can be cleared to 0 by software writing 1 5 1 read-write EPWM_INTSTS1 EPWM_INTSTS1 EPWM Interrupt Flag Register 1 0xEC -1 read-write n 0x0 0x0 BRKEIF0 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 0 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF1 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 1 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF2 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 2 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF3 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 3 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF4 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 4 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF5 EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 5 1 read-write 0 EPWM channel n edge-detect brake event do not happened #0 1 When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKESTS0 EPWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 16 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS1 EPWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 17 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS2 EPWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 18 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS3 EPWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 19 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS4 EPWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 20 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKESTS5 EPWM Channel N Edge-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 21 1 read-only 0 EPWM channel n edge-detect brake state is released #0 1 When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLIF0 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 8 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF1 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 9 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF2 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 10 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF3 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 11 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF4 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 12 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF5 EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register. 13 1 read-write 0 EPWM channel n level-detect brake event do not happened #0 1 When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLSTS0 EPWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 24 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS1 EPWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 25 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS2 EPWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 26 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS3 EPWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 27 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS4 EPWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 28 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 BRKLSTS5 EPWM Channel N Level-detect Brake Status (Read Only) Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 29 1 read-only 0 EPWM channel n level-detect brake state is released #0 1 When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state #1 EPWM_LEBCNT EPWM_LEBCNT EPWM Leading Edge Blanking Counter Register 0x11C -1 read-write n 0x0 0x0 LEBCNT EPWM Leading Edge Blanking Counter 0 9 read-write EPWM_LEBCTL EPWM_LEBCTL EPWM Leading Edge Blanking Control Register 0x118 -1 read-write n 0x0 0x0 LEBEN EPWM Leading Edge Blanking Enable Bit 0 1 read-write 0 EPWM Leading Edge Blanking Disabled #0 1 EPWM Leading Edge Blanking Enabled #1 SRCEN0 EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit 8 1 read-write 0 EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled #0 1 EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled #1 SRCEN2 EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit 9 1 read-write 0 EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled #0 1 EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled #1 SRCEN4 EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit 10 1 read-write 0 EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled #0 1 EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled #1 TRGTYPE EPWM Leading Edge Blanking Trigger Type 16 2 read-write 0 When detect leading edge blanking source rising edge, blanking counter start counting 0 1 When detect leading edge blanking source falling edge, blanking counter start counting 1 2 When detect leading edge blanking source rising or falling edge, blanking counter start counting 2 3 Reserved. 3 EPWM_LOAD EPWM_LOAD EPWM Load Register 0x28 -1 read-write n 0x0 0x0 LOAD0 Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit This bit is software write, hardware clear when current EPWM period end. Write Operation: 0 1 read-write 0 No effect. No load window is set #0 1 Set load window of window loading mode. Load window is set #1 LOAD1 Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit This bit is software write, hardware clear when current EPWM period end. Write Operation: 1 1 read-write 0 No effect. No load window is set #0 1 Set load window of window loading mode. Load window is set #1 LOAD2 Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit This bit is software write, hardware clear when current EPWM period end. Write Operation: 2 1 read-write 0 No effect. No load window is set #0 1 Set load window of window loading mode. Load window is set #1 LOAD3 Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit This bit is software write, hardware clear when current EPWM period end. Write Operation: 3 1 read-write 0 No effect. No load window is set #0 1 Set load window of window loading mode. Load window is set #1 LOAD4 Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit This bit is software write, hardware clear when current EPWM period end. Write Operation: 4 1 read-write 0 No effect. No load window is set #0 1 Set load window of window loading mode. Load window is set #1 LOAD5 Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit This bit is software write, hardware clear when current EPWM period end. Write Operation: 5 1 read-write 0 No effect. No load window is set #0 1 Set load window of window loading mode. Load window is set #1 EPWM_MSK EPWM_MSK EPWM Mask Data Register 0xBC -1 read-write n 0x0 0x0 MSKDAT0 EPWM Mask Data Bit This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 0 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT1 EPWM Mask Data Bit This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 1 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT2 EPWM Mask Data Bit This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 2 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT3 EPWM Mask Data Bit This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 3 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT4 EPWM Mask Data Bit This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 4 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 MSKDAT5 EPWM Mask Data Bit This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 5 1 read-write 0 Output logic low to EPWM channel n #0 1 Output logic high to EPWM channel n #1 EPWM_MSKEN EPWM_MSKEN EPWM Mask Enable Register 0xB8 -1 read-write n 0x0 0x0 MSKEN0 EPWM Mask Enable Bits The EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 0 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN1 EPWM Mask Enable Bits The EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 1 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN2 EPWM Mask Enable Bits The EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 2 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN3 EPWM Mask Enable Bits The EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 3 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN4 EPWM Mask Enable Bits The EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 4 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 MSKEN5 EPWM Mask Enable Bits The EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 5 1 read-write 0 EPWM output signal is non-masked #0 1 EPWM output signal is masked and output MSKDATn data #1 EPWM_PBUF0 EPWM_PBUF0 EPWM PERIOD0 Buffer 0x304 -1 read-only n 0x0 0x0 PBUF EPWM Period Register Buffer (Read Only) Used as PERIOD active register. 0 16 read-only EPWM_PBUF1 EPWM_PBUF1 EPWM PERIOD1 Buffer 0x308 -1 read-write n 0x0 0x0 EPWM_PBUF2 EPWM_PBUF2 EPWM PERIOD2 Buffer 0x30C -1 read-write n 0x0 0x0 EPWM_PBUF3 EPWM_PBUF3 EPWM PERIOD3 Buffer 0x310 -1 read-write n 0x0 0x0 EPWM_PBUF4 EPWM_PBUF4 EPWM PERIOD4 Buffer 0x314 -1 read-write n 0x0 0x0 EPWM_PBUF5 EPWM_PBUF5 EPWM PERIOD5 Buffer 0x318 -1 read-write n 0x0 0x0 EPWM_PDMACAP0_1 EPWM_PDMACAP0_1 EPWM Capture Channel 01 PDMA Register 0x240 -1 read-only n 0x0 0x0 CAPBUF EPWM Capture PDMA Register (Read Only) This register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. 0 16 read-only EPWM_PDMACAP2_3 EPWM_PDMACAP2_3 EPWM Capture Channel 23 PDMA Register 0x244 -1 read-write n 0x0 0x0 EPWM_PDMACAP4_5 EPWM_PDMACAP4_5 EPWM Capture Channel 45 PDMA Register 0x248 -1 read-write n 0x0 0x0 EPWM_PDMACTL EPWM_PDMACTL EPWM PDMA Control Register 0x23C -1 read-write n 0x0 0x0 CAPMOD0_1 Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer 1 2 read-write 0 Reserved. #00 1 EPWM_RCAPDAT0/1 #01 2 EPWM_FCAPDAT0/1 #10 3 Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1 #11 CAPMOD2_3 Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer 9 2 read-write 0 Reserved. #00 1 EPWM_RCAPDAT2/3 #01 2 EPWM_FCAPDAT2/3 #10 3 Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3 #11 CAPMOD4_5 Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer 17 2 read-write 0 Reserved. #00 1 EPWM_RCAPDAT4/5 #01 2 EPWM_FCAPDAT4/5 #10 3 Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5 #11 CAPORD0_1 Capture Channel 0/1 Rising/Falling Order 3 1 read-write 0 EPWM_FCAPDAT0/1 is the first captured data to memory #0 1 EPWM_RCAPDAT0/1 is the first captured data to memory #1 CAPORD2_3 Capture Channel 2/3 Rising/Falling Order 11 1 read-write 0 EPWM_FCAPDAT2/3 is the first captured data to memory #0 1 EPWM_RCAPDAT2/3 is the first captured data to memory #1 CAPORD4_5 Capture Channel 4/5 Rising/Falling Order 19 1 read-write 0 EPWM_FCAPDAT4/5 is the first captured data to memory #0 1 EPWM_RCAPDAT4/5 is the first captured data to memory #1 CHEN0_1 Channel 0/1 PDMA Enable Bit 0 1 read-write 0 Channel 0/1 PDMA function Disabled #0 1 Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory #1 CHEN2_3 Channel 2/3 PDMA Enable Bit 8 1 read-write 0 Channel 2/3 PDMA function Disabled #0 1 Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory #1 CHEN4_5 Channel 4/5 PDMA Enable Bit 16 1 read-write 0 Channel 4/5 PDMA function Disabled #0 1 Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory #1 CHSEL0_1 Select Channel 0/1 to Do PDMA Transfer 4 1 read-write 0 Channel0 #0 1 Channel1 #1 CHSEL2_3 Select Channel 2/3 to Do PDMA Transfer 12 1 read-write 0 Channel2 #0 1 Channel3 #1 CHSEL4_5 Select Channel 4/5 to Do PDMA Transfer 20 1 read-write 0 Channel4 #0 1 Channel5 #1 EPWM_PERIOD0 EPWM_PERIOD0 EPWM Period Register 0 0x30 -1 read-write n 0x0 0x0 PERIOD EPWM Period Register Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. 0 16 read-write EPWM_PERIOD1 EPWM_PERIOD1 EPWM Period Register 1 0x34 -1 read-write n 0x0 0x0 EPWM_PERIOD2 EPWM_PERIOD2 EPWM Period Register 2 0x38 -1 read-write n 0x0 0x0 EPWM_PERIOD3 EPWM_PERIOD3 EPWM Period Register 3 0x3C -1 read-write n 0x0 0x0 EPWM_PERIOD4 EPWM_PERIOD4 EPWM Period Register 4 0x40 -1 read-write n 0x0 0x0 EPWM_PERIOD5 EPWM_PERIOD5 EPWM Period Register 5 0x44 -1 read-write n 0x0 0x0 EPWM_PHS0_1 EPWM_PHS0_1 EPWM Counter Phase Register 0/1 0x80 -1 read-write n 0x0 0x0 PHS EPWM Synchronous Start Phase Bits PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function. 0 16 read-write EPWM_PHS2_3 EPWM_PHS2_3 EPWM Counter Phase Register 2/3 0x84 -1 read-write n 0x0 0x0 EPWM_PHS4_5 EPWM_PHS4_5 EPWM Counter Phase Register 4/5 0x88 -1 read-write n 0x0 0x0 EPWM_POEN EPWM_POEN EPWM Output Enable Register 0xD8 -1 read-write n 0x0 0x0 POEN0 EPWM Pin Output Enable Bits 0 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN1 EPWM Pin Output Enable Bits 1 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN2 EPWM Pin Output Enable Bits 2 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN3 EPWM Pin Output Enable Bits 3 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN4 EPWM Pin Output Enable Bits 4 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 POEN5 EPWM Pin Output Enable Bits 5 1 read-write 0 EPWMx_CHn pin at tri-state #0 1 EPWMx_CHn pin in output mode #1 EPWM_POLCTL EPWM_POLCTL EPWM Pin Polar Inverse Register 0xD4 -1 read-write n 0x0 0x0 PINV0 EPWM PIN Polar Inverse Control The register controls polarity state of EPWMx_CHn output pin. 0 1 read-write 0 EPWMx_CHn output pin polar inverse Disabled #0 1 EPWMx_CHn output pin polar inverse Enabled #1 PINV1 EPWM PIN Polar Inverse Control The register controls polarity state of EPWMx_CHn output pin. 1 1 read-write 0 EPWMx_CHn output pin polar inverse Disabled #0 1 EPWMx_CHn output pin polar inverse Enabled #1 PINV2 EPWM PIN Polar Inverse Control The register controls polarity state of EPWMx_CHn output pin. 2 1 read-write 0 EPWMx_CHn output pin polar inverse Disabled #0 1 EPWMx_CHn output pin polar inverse Enabled #1 PINV3 EPWM PIN Polar Inverse Control The register controls polarity state of EPWMx_CHn output pin. 3 1 read-write 0 EPWMx_CHn output pin polar inverse Disabled #0 1 EPWMx_CHn output pin polar inverse Enabled #1 PINV4 EPWM PIN Polar Inverse Control The register controls polarity state of EPWMx_CHn output pin. 4 1 read-write 0 EPWMx_CHn output pin polar inverse Disabled #0 1 EPWMx_CHn output pin polar inverse Enabled #1 PINV5 EPWM PIN Polar Inverse Control The register controls polarity state of EPWMx_CHn output pin. 5 1 read-write 0 EPWMx_CHn output pin polar inverse Disabled #0 1 EPWMx_CHn output pin polar inverse Enabled #1 EPWM_RCAPDAT0 EPWM_RCAPDAT0 EPWM Rising Capture Data Register 0 0x20C -1 read-only n 0x0 0x0 RCAPDAT EPWM Rising Capture Data Register (Read Only) When rising capture condition happened, the EPWM counter value will be saved in this register. 0 16 read-only EPWM_RCAPDAT1 EPWM_RCAPDAT1 EPWM Rising Capture Data Register 1 0x214 -1 read-write n 0x0 0x0 EPWM_RCAPDAT2 EPWM_RCAPDAT2 EPWM Rising Capture Data Register 2 0x21C -1 read-write n 0x0 0x0 EPWM_RCAPDAT3 EPWM_RCAPDAT3 EPWM Rising Capture Data Register 3 0x224 -1 read-write n 0x0 0x0 EPWM_RCAPDAT4 EPWM_RCAPDAT4 EPWM Rising Capture Data Register 4 0x22C -1 read-write n 0x0 0x0 EPWM_RCAPDAT5 EPWM_RCAPDAT5 EPWM Rising Capture Data Register 5 0x234 -1 read-write n 0x0 0x0 EPWM_RDTCNT0_1 EPWM_RDTCNT0_1 EPWM Rising Dead-time Counter Register 0/1 0x2A8 -1 read-write n 0x0 0x0 RDTCNT Rising Dead-time Counter (Write Protect) The Rising dead-time can be calculated from the following formula: Note: This bit is write protected. Refer to SYS_REGLCTL register. 0 12 read-write EPWM_RDTCNT2_3 EPWM_RDTCNT2_3 EPWM Rising Dead-time Counter Register 2/3 0x2AC -1 read-write n 0x0 0x0 EPWM_RDTCNT4_5 EPWM_RDTCNT4_5 EPWM Rising Dead-time Counter Register 4/5 0x2B0 -1 read-write n 0x0 0x0 EPWM_SSCTL EPWM_SSCTL EPWM Synchronous Start Control Register 0x110 -1 read-write n 0x0 0x0 SSEN0 EPWM Synchronous Start Function Enable Bits When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 0 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN1 EPWM Synchronous Start Function Enable Bits When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN2 EPWM Synchronous Start Function Enable Bits When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 2 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN3 EPWM Synchronous Start Function Enable Bits When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 3 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN4 EPWM Synchronous Start Function Enable Bits When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 4 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSEN5 EPWM Synchronous Start Function Enable Bits When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 5 1 read-write 0 EPWM synchronous start function Disabled #0 1 EPWM synchronous start function Enabled #1 SSRC EPWM Synchronous Start Source Select Bits 8 2 read-write 0 Synchronous start source come from EPWM0 #00 1 Synchronous start source come from EPWM1 #01 2 Synchronous start source come from BPWM0 #10 3 Synchronous start source come from BPWM1 #11 EPWM_SSTRG EPWM_SSTRG EPWM Synchronous Start Trigger Register 0x114 -1 write-only n 0x0 0x0 CNTSEN EPWM Counter Synchronous Start Enable (Write Only) PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time. Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled. 0 1 write-only EPWM_STATUS EPWM_STATUS EPWM Status Register 0x120 -1 read-write n 0x0 0x0 CNTMAXF0 Time-base Counter Equal to 0xFFFF Latched Flag Note: This bit can be cleared by software writing 1. 0 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF1 Time-base Counter Equal to 0xFFFF Latched Flag Note: This bit can be cleared by software writing 1. 1 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF2 Time-base Counter Equal to 0xFFFF Latched Flag Note: This bit can be cleared by software writing 1. 2 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF3 Time-base Counter Equal to 0xFFFF Latched Flag Note: This bit can be cleared by software writing 1. 3 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF4 Time-base Counter Equal to 0xFFFF Latched Flag Note: This bit can be cleared by software writing 1. 4 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 CNTMAXF5 Time-base Counter Equal to 0xFFFF Latched Flag Note: This bit can be cleared by software writing 1. 5 1 read-write 0 The time-base counter never reached its maximum value 0xFFFF #0 1 The time-base counter reached its maximum value #1 DACTRGF DAC Start of Conversion Flag Note: This bit can be cleared by software writing 1. 24 1 read-write 0 No DAC start of conversion trigger event has occurred #0 1 A DAC start of conversion trigger event has occurred #1 EADCTRGF0 EADC Start of Conversion Flag Note: This bit can be cleared by software writing 1. 16 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF1 EADC Start of Conversion Flag Note: This bit can be cleared by software writing 1. 17 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF2 EADC Start of Conversion Flag Note: This bit can be cleared by software writing 1. 18 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF3 EADC Start of Conversion Flag Note: This bit can be cleared by software writing 1. 19 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF4 EADC Start of Conversion Flag Note: This bit can be cleared by software writing 1. 20 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 EADCTRGF5 EADC Start of Conversion Flag Note: This bit can be cleared by software writing 1. 21 1 read-write 0 No EADC start of conversion trigger event has occurred #0 1 An EADC start of conversion trigger event has occurred #1 SYNCINF0 Input Synchronization Latched Flag Note: This bit can be cleared by software writing 1. 8 1 read-write 0 No SYNC_IN event has occurred #0 1 A SYNC_IN event has occurred #1 SYNCINF2 Input Synchronization Latched Flag Note: This bit can be cleared by software writing 1. 9 1 read-write 0 No SYNC_IN event has occurred #0 1 A SYNC_IN event has occurred #1 SYNCINF4 Input Synchronization Latched Flag Note: This bit can be cleared by software writing 1. 10 1 read-write 0 No SYNC_IN event has occurred #0 1 A SYNC_IN event has occurred #1 EPWM_SWBRK EPWM_SWBRK EPWM Software Brake Control Register 0xDC -1 write-only n 0x0 0x0 BRKETRG0 EPWM Edge Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 write-only BRKETRG2 EPWM Edge Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 write-only BRKETRG4 EPWM Edge Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 write-only BRKLTRG0 EPWM Level Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 write-only BRKLTRG2 EPWM Level Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 write-only BRKLTRG4 EPWM Level Brake Software Trigger (Write Only) (Write Protect) Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. Note: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 write-only EPWM_SWEOFCTL EPWM_SWEOFCTL EPWM Software Event Output Force Control Register 0x288 -1 read-write n 0x0 0x0 OUTACTS0 Output Action Selection 0 2 read-write 0 Do nothing #00 1 EPWM output Low #01 2 EPWM output High #10 3 EPWM output Toggle #11 OUTACTS1 Output Action Selection 2 2 read-write 0 Do nothing #00 1 EPWM output Low #01 2 EPWM output High #10 3 EPWM output Toggle #11 OUTACTS2 Output Action Selection 4 2 read-write 0 Do nothing #00 1 EPWM output Low #01 2 EPWM output High #10 3 EPWM output Toggle #11 OUTACTS3 Output Action Selection 6 2 read-write 0 Do nothing #00 1 EPWM output Low #01 2 EPWM output High #10 3 EPWM output Toggle #11 OUTACTS4 Output Action Selection 8 2 read-write 0 Do nothing #00 1 EPWM output Low #01 2 EPWM output High #10 3 EPWM output Toggle #11 OUTACTS5 Output Action Selection 10 2 read-write 0 Do nothing #00 1 EPWM output Low #01 2 EPWM output High #10 3 EPWM output Toggle #11 EPWM_SWEOFTRG EPWM_SWEOFTRG EPWM Software Event Output Force Trigger Register 0x28C -1 read-write n 0x0 0x0 SWETRG0 Software Event Trigger Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. Note: This bit will auto cleared by hardware. 0 1 read-write SWETRG1 Software Event Trigger Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. Note: This bit will auto cleared by hardware. 1 1 read-write SWETRG2 Software Event Trigger Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. Note: This bit will auto cleared by hardware. 2 1 read-write SWETRG3 Software Event Trigger Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. Note: This bit will auto cleared by hardware. 3 1 read-write SWETRG4 Software Event Trigger Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. Note: This bit will auto cleared by hardware. 4 1 read-write SWETRG5 Software Event Trigger Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. Note: This bit will auto cleared by hardware. 5 1 read-write EPWM_SWSYNC EPWM_SWSYNC EPWM Software Control Synchronization Register 0xC -1 read-write n 0x0 0x0 SWSYNC0 Software SYNC Function When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. 0 1 read-write SWSYNC2 Software SYNC Function When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. 1 1 read-write SWSYNC4 Software SYNC Function When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. 2 1 read-write EPWM_SYNC EPWM_SYNC EPWM Synchronization Register 0x8 -1 read-write n 0x0 0x0 PHSDIR0 EPWM Phase Direction Control 24 1 read-write 0 Control EPWM counter count decrement after synchronizing #0 1 Control EPWM counter count increment after synchronizing #1 PHSDIR2 EPWM Phase Direction Control 25 1 read-write 0 Control EPWM counter count decrement after synchronizing #0 1 Control EPWM counter count increment after synchronizing #1 PHSDIR4 EPWM Phase Direction Control 26 1 read-write 0 Control EPWM counter count decrement after synchronizing #0 1 Control EPWM counter count increment after synchronizing #1 PHSEN0 SYNC Phase Enable Bits 0 1 read-write 0 EPWM counter disabled to load PHS value #0 1 EPWM counter enabled to load PHS value #1 PHSEN2 SYNC Phase Enable Bits 1 1 read-write 0 EPWM counter disabled to load PHS value #0 1 EPWM counter enabled to load PHS value #1 PHSEN4 SYNC Phase Enable Bits 2 1 read-write 0 EPWM counter disabled to load PHS value #0 1 EPWM counter enabled to load PHS value #1 SFLTCNT SYNC Edge Detector Filter Count The register bits control the counter number of edge detector. 20 3 read-write SFLTCSEL SYNC Edge Detector Filter Clock Selection 17 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 SINPINV SYNC Input Pin Inverse 23 1 read-write 0 The state of pin SYNC is passed to the negative edge detector #0 1 The inversed state of pin SYNC is passed to the negative edge detector #1 SINSRC0 EPWM0_SYNC_IN Source Selection 8 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT will not be generated #11 SINSRC2 EPWM0_SYNC_IN Source Selection 10 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT will not be generated #11 SINSRC4 EPWM0_SYNC_IN Source Selection 12 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT will not be generated #11 SNFLTEN EPWM0_SYNC_IN Noise Filter Enable Bits 16 1 read-write 0 Noise filter of input pin EPWM0_SYNC_IN Disabled #0 1 Noise filter of input pin EPWM0_SYNC_IN Enabled #1 EPWM_WGCTL0 EPWM_WGCTL0 EPWM Generation Register 0 0xB0 -1 read-write n 0x0 0x0 PRDPCTL0 EPWM Period (Center) Point Control EPWM can control output level when EPWM counter counts to (PERIODn+1). Note: This bit is center point control when EPWM counter operating in up-down counter type. 16 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL1 EPWM Period (Center) Point Control EPWM can control output level when EPWM counter counts to (PERIODn+1). Note: This bit is center point control when EPWM counter operating in up-down counter type. 18 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL2 EPWM Period (Center) Point Control EPWM can control output level when EPWM counter counts to (PERIODn+1). Note: This bit is center point control when EPWM counter operating in up-down counter type. 20 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL3 EPWM Period (Center) Point Control EPWM can control output level when EPWM counter counts to (PERIODn+1). Note: This bit is center point control when EPWM counter operating in up-down counter type. 22 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL4 EPWM Period (Center) Point Control EPWM can control output level when EPWM counter counts to (PERIODn+1). Note: This bit is center point control when EPWM counter operating in up-down counter type. 24 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 PRDPCTL5 EPWM Period (Center) Point Control EPWM can control output level when EPWM counter counts to (PERIODn+1). Note: This bit is center point control when EPWM counter operating in up-down counter type. 26 2 read-write 0 Do nothing #00 1 EPWM period (center) point output Low #01 2 EPWM period (center) point output High #10 3 EPWM period (center) point output Toggle #11 ZPCTL0 EPWM Zero Point Control EPWM can control output level when EPWM counter counts to 0. 0 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL1 EPWM Zero Point Control EPWM can control output level when EPWM counter counts to 0. 2 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL2 EPWM Zero Point Control EPWM can control output level when EPWM counter counts to 0. 4 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL3 EPWM Zero Point Control EPWM can control output level when EPWM counter counts to 0. 6 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL4 EPWM Zero Point Control EPWM can control output level when EPWM counter counts to 0. 8 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 ZPCTL5 EPWM Zero Point Control EPWM can control output level when EPWM counter counts to 0. 10 2 read-write 0 Do nothing #00 1 EPWM zero point output Low #01 2 EPWM zero point output High #10 3 EPWM zero point output Toggle #11 EPWM_WGCTL1 EPWM_WGCTL1 EPWM Generation Register 1 0xB4 -1 read-write n 0x0 0x0 CMPDCTL0 EPWM Compare Down Point Control EPWM can control output level when EPWM counter counts down to CMP. Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 16 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL1 EPWM Compare Down Point Control EPWM can control output level when EPWM counter counts down to CMP. Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 18 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL2 EPWM Compare Down Point Control EPWM can control output level when EPWM counter counts down to CMP. Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 20 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL3 EPWM Compare Down Point Control EPWM can control output level when EPWM counter counts down to CMP. Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 22 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL4 EPWM Compare Down Point Control EPWM can control output level when EPWM counter counts down to CMP. Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 24 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPDCTL5 EPWM Compare Down Point Control EPWM can control output level when EPWM counter counts down to CMP. Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 26 2 read-write 0 Do nothing #00 1 EPWM compare down point output Low #01 2 EPWM compare down point output High #10 3 EPWM compare down point output Toggle #11 CMPUCTL0 EPWM Compare Up Point Control EPWM can control output level when EPWM counter counts up to CMP. Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 0 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL1 EPWM Compare Up Point Control EPWM can control output level when EPWM counter counts up to CMP. Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 2 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL2 EPWM Compare Up Point Control EPWM can control output level when EPWM counter counts up to CMP. Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 4 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL3 EPWM Compare Up Point Control EPWM can control output level when EPWM counter counts up to CMP. Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 6 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL4 EPWM Compare Up Point Control EPWM can control output level when EPWM counter counts up to CMP. Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 8 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 CMPUCTL5 EPWM Compare Up Point Control EPWM can control output level when EPWM counter counts up to CMP. Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 10 2 read-write 0 Do nothing #00 1 EPWM compare up point output Low #01 2 EPWM compare up point output High #10 3 EPWM compare up point output Toggle #11 FMC FMC Register Map FMC 0x0 0x0 0x14 registers n 0x40 0x4 registers n 0x4C 0x4 registers n 0x80 0x10 registers n 0xC0 0x8 registers n 0xD0 0x14 registers n CYCCTL FMC_CYCCTL Flash Access Cycle Control Register 0x4C -1 read-write n 0x0 0x0 CYCLE Flash Access Cycle Control (Write Protect) This register is updated by software.User needs to check the speed of HCLK and set the cycle 0 The optimized HCLK working frequency range is 192 MHz Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 4 read-write 1 CPU access with one wait cycle if cache miss Flash access cycle is 1 #0001 2 CPU access with two wait cycles if cache miss Flash access cycle is 2 #0010 3 CPU access with three wait cycles if cache miss Flash access cycle is 3 #0011 4 CPU access with four wait cycles if cache miss Flash access cycle is 4 #0100 5 CPU access with five wait cycles if cache miss Flash access cycle is 5 #0101 6 CPU access with six wait cycles if cache miss Flash access cycle is 6 #0110 7 CPU access with seven wait cycles if cache miss Flash access cycle is 7 #0111 8 CPU access with eight wait cycles if cache miss Flash access cycle is 8 #1000 FADIS Flash Access Cycle Auto-tuning Disable Bit (Write Protect) Set this bit to disable Flash access cycle auto-tuning function Note: This bit is write protected. Refer to the SYS_REGLCTL register. When FMC is doing auto-tuning, we considered as an ISP operation need to monitor busy flag. 8 1 read-write 0 Flash access cycle auto-tuning Enabled #0 1 Flash access cycle auto-tuning Disabled #1 ISPADDR FMC_ISPADDR ISP Address Register 0x4 -1 read-write n 0x0 0x0 ISPADDR ISP Address The M471V/M471K series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. For CRC32 Checksum Calculation command, this field is the Flash starting address for checksum calculation, 2 Kbytes alignment is necessary for CRC32 checksum calculation. For Flash32-bit Program, ISP address needs word alignment (4-byte). For Flash 64-bit Program, ISP address needs double word alignment (8-byte). 0 32 read-write ISPCMD FMC_ISPCMD ISP Command Register 0xC -1 read-write n 0x0 0x0 CMD ISP Command ISP command table is shown below: The other commands are invalid. 0 7 read-write 0 FLASH Read 0x00 4 Read Unique ID 0x04 8 Read Flash All-One Result 0x08 9 FLASH Read (Program Verify) 0x09 10 FLASH Read (Erase Verify) 0x0a 11 Read Company ID 0x0b 12 Read Device ID 0x0c 13 Read Checksum 0x0d 33 FLASH 32-bit Program 0x21 34 FLASH Page Erase. Erase any page in two banks 0x22 35 FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1 0x23 38 FLASH Mass Erase. Erase all pages in two banks 0x26 39 FLASH Multi-Word Program 0x27 40 Run Flash All-One Verification 0x28 45 Run Checksum Calculation 0x2d 46 Vector Remap 0x2e 64 FLASH 64-bit Read 0x40 97 FLASH 64-bit Program 0x61 ISPCTL FMC_ISPCTL ISP Control Register 0x0 -1 read-write n 0x0 0x0 APUEN APROM Update Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 APROM cannot be updated when the chip runs in APROM #0 1 APROM can be updated when the chip runs in APROM #1 BS Boot Select (Write Protect) When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Boot from APROM when MBS (CONFIG0[5]) is 1 #0 1 Boot from LDROM when MBS (CONFIG0[5]) is 1 #1 CFGUEN CONFIG Update Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 CONFIG cannot be updated #0 1 CONFIG can be updated #1 INTEN Secure ISP INT Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.Before using INT,user needs to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time. 24 1 read-write 0 ISP INT Disabled #0 1 ISP INT Enabled #1 ISPEN ISP Enable Bit (Write Protect) ISP function enable bit. Set this bit to enable ISP function. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 ISP function Disabled #0 1 ISP function Enabled #1 ISPFF ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: This bit needs to be cleared by writing 1 to it. APROM writes to itself if APUEN is set to 0. LDROM writes to itself if LDUEN is set to 0. CONFIG is erased/programmed if CFGUEN is set to 0. Erase or Program command at brown-out detected Destination address is illegal, such as over an available range. Invalid ISP commands The base and size of new XOM regions is wrong, overlap or writed twice The input setting of XOM page erase function is wrong The active XOM regions is accessed (except for chip erase, page erase, checksum and read CID/DID) The XOM setting page is accessed (except for chip erase, word program and read) Violate the load code read protection Checksum or Flash All One Verification is not executed in their valid range Bank erase is not executed in APROM Note: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write LDUEN LDROM Update Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 LDROM cannot be updated #0 1 LDROM can be updated #1 ISPDAT FMC_ISPDAT ISP Data Register 0x8 -1 read-write n 0x0 0x0 ISPDAT ISP Data Write data to this register before ISP program operation. Read data from this register after ISP read operation. 0 32 read-write ISPSTS FMC_ISPSTS ISP Status Register 0x40 -1 read-write n 0x0 0x0 ALLONE Flash All-one Verification Flag This bit is set by hardware if all of Flash bits are 1, and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete this bit also can be clear by writing 1 7 1 read-write 0 Flash bits are not all 1 after 'Run Flash All-One Verification' complete #0 1 All of Flash bits are 1 after 'Run Flash All-One Verification' complete #1 CBS Boot Selection of CONFIG (Read Only) This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. 1 2 read-only 0 LDROM with IAP mode #00 1 LDROM without IAP mode #01 2 APROM with IAP mode #10 3 APROM without IAP mode #11 FCYCDIS Flash Access Cycle Auto-tuning Disable Flag (Read Only) This bit is set if Flash access cycle auto-tunning function is disabled. The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready. 4 1 read-only 0 Flash access cycle auto-tuning Enabled #0 1 Flash access cyle auto-tuning Disabled #1 INTFLAG ISP Interuppt Flag Note: This function needs to be enabled by FMC_ISPCTRL[24]. 24 1 read-write 0 ISP Not Finished #0 1 ISP done or ISPFF set #1 ISPBUSY ISP Busy Flag (Read Only) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. This bit is the mirror of ISPGO(FMC_ISPTRG[0]). 0 1 read-only 0 ISP operation is finished #0 1 ISP is progressed #1 ISPFF ISP Fail Flag (Write Protect) This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions: APROM writes to itself if APUEN is set to 0. LDROM writes to itself if LDUEN is set to 0. CONFIG is erased/programmed if CFGUEN is set to 0. Erase or Program command at brown-out detected Destination address is illegal, such as over an available range. Invalid ISP commands The base and size of new XOM regions is wrong, overlap or writed twice The input setting of XOM page erase function is wrong The active XOM regions is accessed (except for chip erase, page erase, checksum and read CID/DID) The XOM setting page is accessed (except for chip erase, word program and read) Violate the load code read protection Checksum or Flash All One Verification is not executed in their valid range Bank erase is not executed in APROM Note: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write PGFF Flash Program with Fast Verification Flag (Read Only) This bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP Flash erase or ISP read CID operation 5 1 read-only 0 Flash Program is success #0 1 Flash Program is fail. Program data is different with data in the Flash memory #1 VECMAP Vector Page Mapping Address (Read Only) All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF} 9 15 read-only ISPTRG FMC_ISPTRG ISP Trigger Control Register 0x10 -1 read-write n 0x0 0x0 ISPGO ISP Start Trigger (Write Protect) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 ISP operation is finished #0 1 ISP is progressed #1 MPADDR FMC_MPADDR ISP Multi-program Address Register 0xC4 -1 read-only n 0x0 0x0 MPADDR ISP Multi-word Program Address MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. MPADDR will keep the final ISP address when ISP multi-word program is complete. 0 32 read-only MPDAT0 FMC_MPDAT0 ISP Data0 Register 0x80 -1 read-write n 0x0 0x0 ISPDAT0 ISP Data 0 This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data. 0 32 read-write MPDAT1 FMC_MPDAT1 ISP Data1 Register 0x84 -1 read-write n 0x0 0x0 ISPDAT1 ISP Data 1 This register is the second 32-bit data for 64-bit/multi-word programming. 0 32 read-write MPDAT2 FMC_MPDAT2 ISP Data2 Register 0x88 -1 read-write n 0x0 0x0 ISPDAT2 ISP Data 2 This register is the third 32-bit data for multi-word programming. 0 32 read-write MPDAT3 FMC_MPDAT3 ISP Data3 Register 0x8C -1 read-write n 0x0 0x0 ISPDAT3 ISP Data 3 This register is the fourth 32-bit data for multi-word programming. 0 32 read-write MPSTS FMC_MPSTS ISP Multi-program Status Register 0xC0 -1 read-only n 0x0 0x0 D0 ISP DATA 0 Flag (Read Only) This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete. 4 1 read-only 0 FMC_MPDAT0 register is empty, or program to Flash complete #0 1 FMC_MPDAT0 register has been written, and not program to Flash complete #1 D1 ISP DATA 1 Flag (Read Only) This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete. 5 1 read-only 0 FMC_MPDAT1 register is empty, or program to Flash complete #0 1 FMC_MPDAT1 register has been written, and not program to Flash complete #1 D2 ISP DATA 2 Flag (Read Only) This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete. 6 1 read-only 0 FMC_MPDAT2 register is empty, or program to Flash complete #0 1 FMC_MPDAT2 register has been written, and not program to Flash complete #1 D3 ISP DATA 3 Flag (Read Only) This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete. 7 1 read-only 0 FMC_MPDAT3 register is empty, or program to Flash complete #0 1 FMC_MPDAT3 register has been written, and not program to Flash complete #1 ISPFF ISP Fail Flag (Read Only) This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions: APROM writes to itself if APUEN is set to 0. LDROM writes to itself if LDUEN is set to 0. CONFIG is erased/programmed if CFGUEN is set to 0. Erase or Program command at brown-out detected Destination address is illegal, such as over an available range. Invalid ISP commands The base and size of new XOM regions is wrong, overlap or writed twice The input setting of XOM page erase function is wrong The active XOM regions is accessed (except for chip erase, page erase, checksum and read CID/DID) The XOM setting page is accessed (except for chip erase, word program and read) Violate the load code read protection Checksum or Flash All One Verification is not executed in their valid range Bank erase is not executed in APROM 2 1 read-only MPBUSY ISP Multi-word Program Busy Flag (Read Only) Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished. This bit is the mirror of ISPGO(FMC_ISPTRG[0]). 0 1 read-only 0 ISP Multi-Word program operation is finished #0 1 ISP Multi-Word program operation is progressed #1 PPGO ISP Multi-program Status (Read Only) 1 1 read-only 0 ISP multi-word program operation is not active #0 1 ISP multi-word program operation is in progress #1 XOMR0STS FMC_XOMR0STS XOM Region 0 Status Register 0xD0 -1 read-only n 0x0 0x0 BASE XOM Region 0 Base Address (Page-aligned) BASE is the base address of XOM Region 0. 8 24 read-only SIZE XOM Region 0 Size (Page-aligned) SIZE is the page number of XOM Region 0. 0 8 read-only XOMR1STS FMC_XOMR1STS XOM Region 1 Status Register 0xD4 -1 read-only n 0x0 0x0 BASE XOM Region 1 Base Address (Page-aligned) BASE is the base address of XOM Region 1. 8 24 read-only SIZE XOM Region 1 Size (Page-aligned) SIZE is the page number of XOM Region 1. 0 8 read-only XOMR2STS FMC_XOMR2STS XOM Region 2 Status Register 0xD8 -1 read-only n 0x0 0x0 BASE XOM Region 2 Base Address (Page-aligned) BASE is the base address of XOM Region 2. 8 24 read-only SIZE XOM Region 2 Size (Page-aligned) SIZE is the page number of XOM Region 2. 0 8 read-only XOMR3STS FMC_XOMR3STS XOM Region 3 Status Register 0xDC -1 read-only n 0x0 0x0 BASE XOM Region 3 Base Address (Page-aligned) BASE is the base address of XOM Region 3. 8 24 read-only SIZE XOM Region 3 Size (Page-aligned) SIZE is the page number of XOM Region 3. 0 8 read-only XOMSTS FMC_XOMSTS XOM Status Register 0xE0 -1 read-only n 0x0 0x0 XOMPEF XOM Page Erase Function Fail XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again. 4 1 read-only 0 Sucess #0 1 Fail #1 XOMR0ON XOM Region 0 On XOM Region 0 active status. 0 1 read-only 0 No active #0 1 XOM region 0 is active #1 XOMR1ON XOM Region 1 On XOM Region 1 active status. 1 1 read-only 0 No active #0 1 XOM region 1 is active #1 XOMR2ON XOM Region 2 On XOM Region 2 active status. 2 1 read-only 0 No active #0 1 XOM region 2 is active #1 XOMR3ON XOM Region 3 On XOM Region 3 active status. 3 1 read-only 0 No active #0 1 XOM region 3 is active #1 GPIO GPIO Register Map GPIO 0x0 0x0 0x2C registers n 0x100 0x2C registers n 0x130 0x4 registers n 0x140 0x2C registers n 0x170 0x4 registers n 0x180 0x2C registers n 0x1B0 0x4 registers n 0x1C0 0x2C registers n 0x1F0 0x4 registers n 0x200 0x2C registers n 0x230 0x4 registers n 0x30 0x4 registers n 0x40 0x2C registers n 0x440 0x4 registers n 0x450 0x20 registers n 0x490 0x4 registers n 0x498 0x8 registers n 0x70 0x4 registers n 0x80 0x2C registers n 0x800 0x1B4 registers n 0x9C0 0x34 registers n 0xA00 0x20 registers n 0xB0 0x4 registers n 0xC0 0x2C registers n 0xF0 0x4 registers n DBCTL GPIO_DBCTL Interrupt De-bounce Control Register 0x440 -1 read-write n 0x0 0x0 DBCLKSEL De-bounce Sampling Cycle Selection 0 4 read-write 0 Sample interrupt input once per 1 clocks #0000 1 Sample interrupt input once per 2 clocks #0001 2 Sample interrupt input once per 4 clocks #0010 3 Sample interrupt input once per 8 clocks #0011 4 Sample interrupt input once per 16 clocks #0100 5 Sample interrupt input once per 32 clocks #0101 6 Sample interrupt input once per 64 clocks #0110 7 Sample interrupt input once per 128 clocks #0111 8 Sample interrupt input once per 256 clocks #1000 9 Sample interrupt input once per 2*256 clocks #1001 10 Sample interrupt input once per 4*256 clocks #1010 11 Sample interrupt input once per 8*256 clocks #1011 12 Sample interrupt input once per 16*256 clocks #1100 13 Sample interrupt input once per 32*256 clocks #1101 14 Sample interrupt input once per 64*256 clocks #1110 15 Sample interrupt input once per 128*256 clocks #1111 DBCLKSRC De-bounce Counter Clock Source Selection 4 1 read-write 0 De-bounce counter clock source is the HCLK #0 1 De-bounce counter clock source is the internal low speed RC oscillator (LIRC) #1 ICLKON Interrupt Clock on Mode Note 1: It is recommended to disable this bit to save system power if no special application concern. Note 2:The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 5 1 read-write 0 Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1. If corresponding RHIEN or FLIEN not set to 1, the clock of IO detect circuit is stopped and INTSRC flag cannot be clear also #0 1 All I/O pins edge detection circuit is always active after reset #1 INT0_INNF INT0_INNF INTn Input Noise Filter Register 0x450 -1 read-write n 0x0 0x0 NFCNT Noise Filter Count The register bits control the filter counter to count from 0 to NFCNT. 8 3 read-write NFEN Noise Filter Enable 0 1 read-write 0 Noise Filter function Disabled #0 1 Noise Filter function Enabled #1 NFSEL Noise Filter Clock Selection 4 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 INT1_INNF INT1_INNF INTn Input Noise Filter Register 0x454 -1 read-write n 0x0 0x0 INT2_INNF INT2_INNF INTn Input Noise Filter Register 0x458 -1 read-write n 0x0 0x0 INT3_INNF INT3_INNF INTn Input Noise Filter Register 0x45C -1 read-write n 0x0 0x0 INT4_INNF INT4_INNF INTn Input Noise Filter Register 0x460 -1 read-write n 0x0 0x0 INT5_INNF INT5_INNF INTn Input Noise Filter Register 0x464 -1 read-write n 0x0 0x0 INT6_INNF INT6_INNF INTn Input Noise Filter Register 0x468 -1 read-write n 0x0 0x0 INT7_INNF INT7_INNF INTn Input Noise Filter Register 0x46C -1 read-write n 0x0 0x0 INT_EDETCTL INT_EDETCTL INT Edge Detect Control Register 0x490 -1 read-write n 0x0 0x0 EDETCTL0 INTn Edge Detect Control Bits 0 2 read-write 0 Not detect #00 1 INTn low to high detection Enable #01 2 INTn high to low detection Enable #10 3 INTn both low to high and high to low detection Enable #11 EDETCTL1 INTn Edge Detect Control Bits 2 2 read-write 0 Not detect #00 1 INTn low to high detection Enable #01 2 INTn high to low detection Enable #10 3 INTn both low to high and high to low detection Enable #11 EDETCTL2 INTn Edge Detect Control Bits 4 2 read-write 0 Not detect #00 1 INTn low to high detection Enable #01 2 INTn high to low detection Enable #10 3 INTn both low to high and high to low detection Enable #11 EDETCTL3 INTn Edge Detect Control Bits 6 2 read-write 0 Not detect #00 1 INTn low to high detection Enable #01 2 INTn high to low detection Enable #10 3 INTn both low to high and high to low detection Enable #11 EDETCTL4 INTn Edge Detect Control Bits 8 2 read-write 0 Not detect #00 1 INTn low to high detection Enable #01 2 INTn high to low detection Enable #10 3 INTn both low to high and high to low detection Enable #11 EDETCTL5 INTn Edge Detect Control Bits 10 2 read-write 0 Not detect #00 1 INTn low to high detection Enable #01 2 INTn high to low detection Enable #10 3 INTn both low to high and high to low detection Enable #11 EDETCTL6 INTn Edge Detect Control Bits 12 2 read-write 0 Not detect #00 1 INTn low to high detection Enable #01 2 INTn high to low detection Enable #10 3 INTn both low to high and high to low detection Enable #11 EDETCTL7 INTn Edge Detect Control Bits 14 2 read-write 0 Not detect #00 1 INTn low to high detection Enable #01 2 INTn high to low detection Enable #10 3 INTn both low to high and high to low detection Enable #11 Reseved Reseved 16 16 read-write INT_EDINTEN INT_EDINTEN INT Edge Detect Interrupt Enable Control Register 0x498 -1 read-write n 0x0 0x0 EDIEN0 INTn Edge Detect Interrupt Enable Bit 0 1 read-write 0 INTx Edge Detect Interrupt Disable #0 1 INTx Edge Detect Interrupt Enable #1 EDIEN1 INTn Edge Detect Interrupt Enable Bit 1 1 read-write 0 INTx Edge Detect Interrupt Disable #0 1 INTx Edge Detect Interrupt Enable #1 EDIEN2 INTn Edge Detect Interrupt Enable Bit 2 1 read-write 0 INTx Edge Detect Interrupt Disable #0 1 INTx Edge Detect Interrupt Enable #1 EDIEN3 INTn Edge Detect Interrupt Enable Bit 3 1 read-write 0 INTx Edge Detect Interrupt Disable #0 1 INTx Edge Detect Interrupt Enable #1 EDIEN4 INTn Edge Detect Interrupt Enable Bit 4 1 read-write 0 INTx Edge Detect Interrupt Disable #0 1 INTx Edge Detect Interrupt Enable #1 EDIEN5 INTn Edge Detect Interrupt Enable Bit 5 1 read-write 0 INTx Edge Detect Interrupt Disable #0 1 INTx Edge Detect Interrupt Enable #1 EDIEN6 INTn Edge Detect Interrupt Enable Bit 6 1 read-write 0 INTx Edge Detect Interrupt Disable #0 1 INTx Edge Detect Interrupt Enable #1 EDIEN7 INTn Edge Detect Interrupt Enable Bit 7 1 read-write 0 INTx Edge Detect Interrupt Disable #0 1 INTx Edge Detect Interrupt Enable #1 Reseved Reseved 8 24 read-write INT_EDSTS INT_EDSTS INT Edge Detect Interrupt Flag Register 0x49C -1 read-write n 0x0 0x0 EDIF0 INTn Edge Detect Interrupt Flag Note: This bit is cleared by writing 1 to it. 0 1 read-write 0 No Edge Detection happened #0 1 Rising Edge or Falling edge has been detected #1 EDIF1 INTn Edge Detect Interrupt Flag Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 No Edge Detection happened #0 1 Rising Edge or Falling edge has been detected #1 EDIF2 INTn Edge Detect Interrupt Flag Note: This bit is cleared by writing 1 to it. 2 1 read-write 0 No Edge Detection happened #0 1 Rising Edge or Falling edge has been detected #1 EDIF3 INTn Edge Detect Interrupt Flag Note: This bit is cleared by writing 1 to it. 3 1 read-write 0 No Edge Detection happened #0 1 Rising Edge or Falling edge has been detected #1 EDIF4 INTn Edge Detect Interrupt Flag Note: This bit is cleared by writing 1 to it. 4 1 read-write 0 No Edge Detection happened #0 1 Rising Edge or Falling edge has been detected #1 EDIF5 INTn Edge Detect Interrupt Flag Note: This bit is cleared by writing 1 to it. 5 1 read-write 0 No Edge Detection happened #0 1 Rising Edge or Falling edge has been detected #1 EDIF6 INTn Edge Detect Interrupt Flag Note: This bit is cleared by writing 1 to it. 6 1 read-write 0 No Edge Detection happened #0 1 Rising Edge or Falling edge has been detected #1 EDIF7 INTn Edge Detect Interrupt Flag Note: This bit is cleared by writing 1 to it. 7 1 read-write 0 No Edge Detection happened #0 1 Rising Edge or Falling edge has been detected #1 Reseved Reseved 8 24 read-write PA0_PDIO PA0_PDIO GPIO PA.n Pin Data Input/Output Register 0x800 -1 read-write n 0x0 0x0 PDIO GPIO Px.n Pin Data Input/Output Writing this bit can control one GPIO pin output value. Read this register to get GPIO pin status. For example, writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]), reading PA0_PDIO will return the value of PIN (PA_PIN[0]). Note 1: The writing operation will not be affected by register DATMSK (Px_DATMSK[n]). Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 0 1 read-write 0 Corresponding GPIO pin set to low #0 1 Corresponding GPIO pin set to high #1 PA10_PDIO PA10_PDIO GPIO PA.n Pin Data Input/Output Register 0x828 -1 read-write n 0x0 0x0 PA11_PDIO PA11_PDIO GPIO PA.n Pin Data Input/Output Register 0x82C -1 read-write n 0x0 0x0 PA12_PDIO PA12_PDIO GPIO PA.n Pin Data Input/Output Register 0x830 -1 read-write n 0x0 0x0 PA13_PDIO PA13_PDIO GPIO PA.n Pin Data Input/Output Register 0x834 -1 read-write n 0x0 0x0 PA14_PDIO PA14_PDIO GPIO PA.n Pin Data Input/Output Register 0x838 -1 read-write n 0x0 0x0 PA15_PDIO PA15_PDIO GPIO PA.n Pin Data Input/Output Register 0x83C -1 read-write n 0x0 0x0 PA1_PDIO PA1_PDIO GPIO PA.n Pin Data Input/Output Register 0x804 -1 read-write n 0x0 0x0 PA2_PDIO PA2_PDIO GPIO PA.n Pin Data Input/Output Register 0x808 -1 read-write n 0x0 0x0 PA3_PDIO PA3_PDIO GPIO PA.n Pin Data Input/Output Register 0x80C -1 read-write n 0x0 0x0 PA4_PDIO PA4_PDIO GPIO PA.n Pin Data Input/Output Register 0x810 -1 read-write n 0x0 0x0 PA5_PDIO PA5_PDIO GPIO PA.n Pin Data Input/Output Register 0x814 -1 read-write n 0x0 0x0 PA6_PDIO PA6_PDIO GPIO PA.n Pin Data Input/Output Register 0x818 -1 read-write n 0x0 0x0 PA7_PDIO PA7_PDIO GPIO PA.n Pin Data Input/Output Register 0x81C -1 read-write n 0x0 0x0 PA8_PDIO PA8_PDIO GPIO PA.n Pin Data Input/Output Register 0x820 -1 read-write n 0x0 0x0 PA9_PDIO PA9_PDIO GPIO PA.n Pin Data Input/Output Register 0x824 -1 read-write n 0x0 0x0 PA_DATMSK PA_DATMSK PA Data Output Write Mask 0xC -1 read-write n 0x0 0x0 DATMSK0 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 0 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK1 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 1 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK10 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 10 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK11 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 11 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK12 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 12 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK13 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 13 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK14 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 14 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK15 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 15 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK2 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 2 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK3 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 3 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK4 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 4 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK5 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 5 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK6 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 6 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK7 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 7 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK8 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 8 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK9 Port A-I Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 9 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 PA_DBEN PA_DBEN PA De-Bounce Enable Control Register 0x14 -1 read-write n 0x0 0x0 DBEN0 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 0 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN1 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 1 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN10 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 10 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN11 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 11 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN12 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 12 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN13 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 13 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN14 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 14 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN15 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 15 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN2 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 2 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN3 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 3 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN4 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 4 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN5 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 5 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN6 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 6 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN7 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 7 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN8 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 8 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN9 Port A-I Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 9 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 PA_DINOFF PA_DINOFF PA Digital Input Path Disable Control 0x4 -1 read-write n 0x0 0x0 DINOFF0 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 16 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF1 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 17 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF10 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 26 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF11 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 27 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF12 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 28 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF13 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 29 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF14 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 30 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF15 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 31 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF2 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 18 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF3 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 19 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF4 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 20 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF5 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 21 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF6 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 22 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF7 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 23 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF8 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 24 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF9 Port A-I Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 25 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 PA_DOUT PA_DOUT PA Data Output Value 0x8 -1 read-write n 0x0 0x0 DOUT0 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 0 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT1 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 1 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT10 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 10 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT11 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 11 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT12 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 12 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT13 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 13 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT14 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 14 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT15 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 15 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT2 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 2 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT3 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 3 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT4 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 4 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT5 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 5 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT6 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 6 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT7 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 7 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT8 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 8 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT9 Port A-I Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 9 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 PA_INTEN PA_INTEN PA Interrupt Enable Control Register 0x1C -1 read-write n 0x0 0x0 FLIEN0 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 0 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN1 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 1 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN10 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 10 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN11 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 11 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN12 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 12 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN13 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 13 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN14 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 14 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN15 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 15 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN2 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 2 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN3 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 3 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN4 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 4 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN5 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 5 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN6 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 6 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN7 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 7 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN8 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 8 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN9 Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 9 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 RHIEN0 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 16 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN1 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 17 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN10 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 26 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN11 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 27 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN12 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 28 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN13 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 29 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN14 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 30 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN15 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 31 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN2 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 18 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN3 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 19 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN4 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 20 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN5 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 21 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN6 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 22 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN7 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 23 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN8 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 24 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN9 Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 25 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 PA_INTSRC PA_INTSRC PA Interrupt Source Flag 0x20 -1 read-write n 0x0 0x0 INTSRC0 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 0 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC1 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 1 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC10 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 10 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC11 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 11 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC12 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 12 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC13 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 13 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC14 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 14 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC15 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 15 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC2 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 2 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC3 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 3 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC4 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 4 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC5 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 5 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC6 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 6 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC7 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 7 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC8 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 8 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC9 Port A-I Pin[n] Interrupt Source Flag Write Operation : Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 9 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 PA_INTTYPE PA_INTTYPE PA Interrupt Trigger Type Control 0x18 -1 read-write n 0x0 0x0 TYPE0 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 0 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE1 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 1 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE10 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 10 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE11 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 11 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE12 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 12 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE13 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 13 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE14 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 14 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE15 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 15 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE2 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 2 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE3 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 3 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE4 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 4 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE5 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 5 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE6 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 6 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE7 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 7 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE8 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 8 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE9 Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 9 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 PA_MODE PA_MODE PA I/O Mode Control 0x0 -1 read-write n 0x0 0x0 MODE0 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 0 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE1 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 2 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE10 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 20 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE11 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 22 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE12 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 24 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE13 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 26 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE14 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 28 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE15 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 30 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE2 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 4 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE3 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 6 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE4 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 8 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE5 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 10 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE6 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 12 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE7 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 14 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE8 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 16 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE9 Port A-I I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available 18 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 PA_PIN PA_PIN PA Pin Value 0x10 -1 read-only n 0x0 0x0 PIN0 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 0 1 read-only PIN1 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 1 1 read-only PIN10 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 10 1 read-only PIN11 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 11 1 read-only PIN12 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 12 1 read-only PIN13 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 13 1 read-only PIN14 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 14 1 read-only PIN15 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 15 1 read-only PIN2 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 2 1 read-only PIN3 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 3 1 read-only PIN4 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 4 1 read-only PIN5 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 5 1 read-only PIN6 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 6 1 read-only PIN7 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 7 1 read-only PIN8 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 8 1 read-only PIN9 Port A-I Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 9 1 read-only PA_PUSEL PA_PUSEL PA Pull-up Selection Register 0x30 -1 read-write n 0x0 0x0 PUSEL0 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 0 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL1 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 2 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL10 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 20 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL11 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 22 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL12 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 24 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL13 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 26 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL14 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 28 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL15 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 30 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL2 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 4 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL3 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 6 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL4 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 8 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL5 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 10 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL6 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 12 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL7 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 14 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL8 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 16 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PUSEL9 Port A-I Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: Basically, the pull-up control has following behavior limitation The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 18 1 read-write 0 Px.n pull-up disable #0 1 Px.n pull-up enable #1 PA_SLEWCTL PA_SLEWCTL PA High Slew Rate Control Register 0x28 -1 read-write n 0x0 0x0 HSREN0 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 0 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 HSREN1 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 2 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 HSREN10 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 20 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 HSREN11 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 22 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 HSREN12 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 24 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 HSREN13 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 26 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 HSREN14 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 28 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 HSREN15 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 30 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 HSREN2 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 4 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 HSREN3 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 6 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 HSREN4 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 8 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 HSREN5 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 10 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 HSREN6 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 12 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 HSREN7 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 14 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 HSREN8 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 16 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 HSREN9 Port A-I Pin[n] High Slew Rate Control Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 18 2 read-write 0 Px.n output with normal slew rate mode #00 1 Px.n output with high slew rate mode #01 2 Reserved. #10 3 Reserved. #11 PA_SMTEN PA_SMTEN PA Input Schmitt Trigger Enable Register 0x24 -1 read-write n 0x0 0x0 SMTEN0 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 0 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN1 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 1 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN10 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 10 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN11 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 11 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN12 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 12 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN13 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 13 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN14 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 14 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN15 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 15 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN2 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 2 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN3 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 3 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN4 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 4 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN5 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 5 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN6 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 6 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN7 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 7 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN8 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 8 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN9 Port A-I Pin[n] Input Schmitt Trigger Enable Bit Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available. 9 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 PB0_PDIO PB0_PDIO GPIO PB.n Pin Data Input/Output Register 0x840 -1 read-write n 0x0 0x0 PB10_PDIO PB10_PDIO GPIO PB.n Pin Data Input/Output Register 0x868 -1 read-write n 0x0 0x0 PB11_PDIO PB11_PDIO GPIO PB.n Pin Data Input/Output Register 0x86C -1 read-write n 0x0 0x0 PB12_PDIO PB12_PDIO GPIO PB.n Pin Data Input/Output Register 0x870 -1 read-write n 0x0 0x0 PB13_PDIO PB13_PDIO GPIO PB.n Pin Data Input/Output Register 0x874 -1 read-write n 0x0 0x0 PB14_PDIO PB14_PDIO GPIO PB.n Pin Data Input/Output Register 0x878 -1 read-write n 0x0 0x0 PB15_PDIO PB15_PDIO GPIO PB.n Pin Data Input/Output Register 0x87C -1 read-write n 0x0 0x0 PB1_PDIO PB1_PDIO GPIO PB.n Pin Data Input/Output Register 0x844 -1 read-write n 0x0 0x0 PB2_PDIO PB2_PDIO GPIO PB.n Pin Data Input/Output Register 0x848 -1 read-write n 0x0 0x0 PB3_PDIO PB3_PDIO GPIO PB.n Pin Data Input/Output Register 0x84C -1 read-write n 0x0 0x0 PB4_PDIO PB4_PDIO GPIO PB.n Pin Data Input/Output Register 0x850 -1 read-write n 0x0 0x0 PB5_PDIO PB5_PDIO GPIO PB.n Pin Data Input/Output Register 0x854 -1 read-write n 0x0 0x0 PB6_PDIO PB6_PDIO GPIO PB.n Pin Data Input/Output Register 0x858 -1 read-write n 0x0 0x0 PB7_PDIO PB7_PDIO GPIO PB.n Pin Data Input/Output Register 0x85C -1 read-write n 0x0 0x0 PB8_PDIO PB8_PDIO GPIO PB.n Pin Data Input/Output Register 0x860 -1 read-write n 0x0 0x0 PB9_PDIO PB9_PDIO GPIO PB.n Pin Data Input/Output Register 0x864 -1 read-write n 0x0 0x0 PB_DATMSK PB_DATMSK PB Data Output Write Mask 0x4C -1 read-write n 0x0 0x0 PB_DBEN PB_DBEN PB De-Bounce Enable Control Register 0x54 -1 read-write n 0x0 0x0 PB_DINOFF PB_DINOFF PB Digital Input Path Disable Control 0x44 -1 read-write n 0x0 0x0 PB_DOUT PB_DOUT PB Data Output Value 0x48 -1 read-write n 0x0 0x0 PB_INTEN PB_INTEN PB Interrupt Enable Control Register 0x5C -1 read-write n 0x0 0x0 PB_INTSRC PB_INTSRC PB Interrupt Source Flag 0x60 -1 read-write n 0x0 0x0 PB_INTTYPE PB_INTTYPE PB Interrupt Trigger Type Control 0x58 -1 read-write n 0x0 0x0 PB_MODE PB_MODE PB I/O Mode Control 0x40 -1 read-write n 0x0 0x0 PB_PIN PB_PIN PB Pin Value 0x50 -1 read-write n 0x0 0x0 PB_PUSEL PB_PUSEL PB Pull-up Selection Register 0x70 -1 read-write n 0x0 0x0 PB_SLEWCTL PB_SLEWCTL PB High Slew Rate Control Register 0x68 -1 read-write n 0x0 0x0 PB_SMTEN PB_SMTEN PB Input Schmitt Trigger Enable Register 0x64 -1 read-write n 0x0 0x0 PC0_PDIO PC0_PDIO GPIO PC.n Pin Data Input/Output Register 0x880 -1 read-write n 0x0 0x0 PC10_PDIO PC10_PDIO GPIO PC.n Pin Data Input/Output Register 0x8A8 -1 read-write n 0x0 0x0 PC11_PDIO PC11_PDIO GPIO PC.n Pin Data Input/Output Register 0x8AC -1 read-write n 0x0 0x0 PC12_PDIO PC12_PDIO GPIO PC.n Pin Data Input/Output Register 0x8B0 -1 read-write n 0x0 0x0 PC13_PDIO PC13_PDIO GPIO PC.n Pin Data Input/Output Register 0x8B4 -1 read-write n 0x0 0x0 PC14_PDIO PC14_PDIO GPIO PC.n Pin Data Input/Output Register 0x8B8 -1 read-write n 0x0 0x0 PC15_PDIO PC15_PDIO GPIO PC.n Pin Data Input/Output Register 0x8BC -1 read-write n 0x0 0x0 PC1_PDIO PC1_PDIO GPIO PC.n Pin Data Input/Output Register 0x884 -1 read-write n 0x0 0x0 PC2_PDIO PC2_PDIO GPIO PC.n Pin Data Input/Output Register 0x888 -1 read-write n 0x0 0x0 PC3_PDIO PC3_PDIO GPIO PC.n Pin Data Input/Output Register 0x88C -1 read-write n 0x0 0x0 PC4_PDIO PC4_PDIO GPIO PC.n Pin Data Input/Output Register 0x890 -1 read-write n 0x0 0x0 PC5_PDIO PC5_PDIO GPIO PC.n Pin Data Input/Output Register 0x894 -1 read-write n 0x0 0x0 PC6_PDIO PC6_PDIO GPIO PC.n Pin Data Input/Output Register 0x898 -1 read-write n 0x0 0x0 PC7_PDIO PC7_PDIO GPIO PC.n Pin Data Input/Output Register 0x89C -1 read-write n 0x0 0x0 PC8_PDIO PC8_PDIO GPIO PC.n Pin Data Input/Output Register 0x8A0 -1 read-write n 0x0 0x0 PC9_PDIO PC9_PDIO GPIO PC.n Pin Data Input/Output Register 0x8A4 -1 read-write n 0x0 0x0 PC_DATMSK PC_DATMSK PC Data Output Write Mask 0x8C -1 read-write n 0x0 0x0 PC_DBEN PC_DBEN PC De-Bounce Enable Control Register 0x94 -1 read-write n 0x0 0x0 PC_DINOFF PC_DINOFF PC Digital Input Path Disable Control 0x84 -1 read-write n 0x0 0x0 PC_DOUT PC_DOUT PC Data Output Value 0x88 -1 read-write n 0x0 0x0 PC_INTEN PC_INTEN PC Interrupt Enable Control Register 0x9C -1 read-write n 0x0 0x0 PC_INTSRC PC_INTSRC PC Interrupt Source Flag 0xA0 -1 read-write n 0x0 0x0 PC_INTTYPE PC_INTTYPE PC Interrupt Trigger Type Control 0x98 -1 read-write n 0x0 0x0 PC_MODE PC_MODE PC I/O Mode Control 0x80 -1 read-write n 0x0 0x0 PC_PIN PC_PIN PC Pin Value 0x90 -1 read-write n 0x0 0x0 PC_PUSEL PC_PUSEL PC Pull-up Selection Register 0xB0 -1 read-write n 0x0 0x0 PC_SLEWCTL PC_SLEWCTL PC High Slew Rate Control Register 0xA8 -1 read-write n 0x0 0x0 PC_SMTEN PC_SMTEN PC Input Schmitt Trigger Enable Register 0xA4 -1 read-write n 0x0 0x0 PD0_PDIO PD0_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C0 -1 read-write n 0x0 0x0 PD10_PDIO PD10_PDIO GPIO PD.n Pin Data Input/Output Register 0x8E8 -1 read-write n 0x0 0x0 PD11_PDIO PD11_PDIO GPIO PD.n Pin Data Input/Output Register 0x8EC -1 read-write n 0x0 0x0 PD12_PDIO PD12_PDIO GPIO PD.n Pin Data Input/Output Register 0x8F0 -1 read-write n 0x0 0x0 PD13_PDIO PD13_PDIO GPIO PD.n Pin Data Input/Output Register 0x8F4 -1 read-write n 0x0 0x0 PD14_PDIO PD14_PDIO GPIO PD.n Pin Data Input/Output Register 0x8F8 -1 read-write n 0x0 0x0 PD15_PDIO PD15_PDIO GPIO PD.n Pin Data Input/Output Register 0x8FC -1 read-write n 0x0 0x0 PD1_PDIO PD1_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C4 -1 read-write n 0x0 0x0 PD2_PDIO PD2_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C8 -1 read-write n 0x0 0x0 PD3_PDIO PD3_PDIO GPIO PD.n Pin Data Input/Output Register 0x8CC -1 read-write n 0x0 0x0 PD4_PDIO PD4_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D0 -1 read-write n 0x0 0x0 PD5_PDIO PD5_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D4 -1 read-write n 0x0 0x0 PD6_PDIO PD6_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D8 -1 read-write n 0x0 0x0 PD7_PDIO PD7_PDIO GPIO PD.n Pin Data Input/Output Register 0x8DC -1 read-write n 0x0 0x0 PD8_PDIO PD8_PDIO GPIO PD.n Pin Data Input/Output Register 0x8E0 -1 read-write n 0x0 0x0 PD9_PDIO PD9_PDIO GPIO PD.n Pin Data Input/Output Register 0x8E4 -1 read-write n 0x0 0x0 PD_DATMSK PD_DATMSK PD Data Output Write Mask 0xCC -1 read-write n 0x0 0x0 PD_DBEN PD_DBEN PD De-Bounce Enable Control Register 0xD4 -1 read-write n 0x0 0x0 PD_DINOFF PD_DINOFF PD Digital Input Path Disable Control 0xC4 -1 read-write n 0x0 0x0 PD_DOUT PD_DOUT PD Data Output Value 0xC8 -1 read-write n 0x0 0x0 PD_INTEN PD_INTEN PD Interrupt Enable Control Register 0xDC -1 read-write n 0x0 0x0 PD_INTSRC PD_INTSRC PD Interrupt Source Flag 0xE0 -1 read-write n 0x0 0x0 PD_INTTYPE PD_INTTYPE PD Interrupt Trigger Type Control 0xD8 -1 read-write n 0x0 0x0 PD_MODE PD_MODE PD I/O Mode Control 0xC0 -1 read-write n 0x0 0x0 PD_PIN PD_PIN PD Pin Value 0xD0 -1 read-write n 0x0 0x0 PD_PUSEL PD_PUSEL PD Pull-up Selection Register 0xF0 -1 read-write n 0x0 0x0 PD_SLEWCTL PD_SLEWCTL PD High Slew Rate Control Register 0xE8 -1 read-write n 0x0 0x0 PD_SMTEN PD_SMTEN PD Input Schmitt Trigger Enable Register 0xE4 -1 read-write n 0x0 0x0 PE0_PDIO PE0_PDIO GPIO PE.n Pin Data Input/Output Register 0x900 -1 read-write n 0x0 0x0 PE10_PDIO PE10_PDIO GPIO PE.n Pin Data Input/Output Register 0x928 -1 read-write n 0x0 0x0 PE11_PDIO PE11_PDIO GPIO PE.n Pin Data Input/Output Register 0x92C -1 read-write n 0x0 0x0 PE12_PDIO PE12_PDIO GPIO PE.n Pin Data Input/Output Register 0x930 -1 read-write n 0x0 0x0 PE13_PDIO PE13_PDIO GPIO PE.n Pin Data Input/Output Register 0x934 -1 read-write n 0x0 0x0 PE14_PDIO PE14_PDIO GPIO PE.n Pin Data Input/Output Register 0x938 -1 read-write n 0x0 0x0 PE15_PDIO PE15_PDIO GPIO PE.n Pin Data Input/Output Register 0x93C -1 read-write n 0x0 0x0 PE1_PDIO PE1_PDIO GPIO PE.n Pin Data Input/Output Register 0x904 -1 read-write n 0x0 0x0 PE2_PDIO PE2_PDIO GPIO PE.n Pin Data Input/Output Register 0x908 -1 read-write n 0x0 0x0 PE3_PDIO PE3_PDIO GPIO PE.n Pin Data Input/Output Register 0x90C -1 read-write n 0x0 0x0 PE4_PDIO PE4_PDIO GPIO PE.n Pin Data Input/Output Register 0x910 -1 read-write n 0x0 0x0 PE5_PDIO PE5_PDIO GPIO PE.n Pin Data Input/Output Register 0x914 -1 read-write n 0x0 0x0 PE6_PDIO PE6_PDIO GPIO PE.n Pin Data Input/Output Register 0x918 -1 read-write n 0x0 0x0 PE7_PDIO PE7_PDIO GPIO PE.n Pin Data Input/Output Register 0x91C -1 read-write n 0x0 0x0 PE8_PDIO PE8_PDIO GPIO PE.n Pin Data Input/Output Register 0x920 -1 read-write n 0x0 0x0 PE9_PDIO PE9_PDIO GPIO PE.n Pin Data Input/Output Register 0x924 -1 read-write n 0x0 0x0 PE_DATMSK PE_DATMSK PE Data Output Write Mask 0x10C -1 read-write n 0x0 0x0 PE_DBEN PE_DBEN PE De-Bounce Enable Control Register 0x114 -1 read-write n 0x0 0x0 PE_DINOFF PE_DINOFF PE Digital Input Path Disable Control 0x104 -1 read-write n 0x0 0x0 PE_DOUT PE_DOUT PE Data Output Value 0x108 -1 read-write n 0x0 0x0 PE_INTEN PE_INTEN PE Interrupt Enable Control Register 0x11C -1 read-write n 0x0 0x0 PE_INTSRC PE_INTSRC PE Interrupt Source Flag 0x120 -1 read-write n 0x0 0x0 PE_INTTYPE PE_INTTYPE PE Interrupt Trigger Type Control 0x118 -1 read-write n 0x0 0x0 PE_MODE PE_MODE PE I/O Mode Control 0x100 -1 read-write n 0x0 0x0 PE_PIN PE_PIN PE Pin Value 0x110 -1 read-write n 0x0 0x0 PE_PUSEL PE_PUSEL PE Pull-up Selection Register 0x130 -1 read-write n 0x0 0x0 PE_SLEWCTL PE_SLEWCTL PE High Slew Rate Control Register 0x128 -1 read-write n 0x0 0x0 PE_SMTEN PE_SMTEN PE Input Schmitt Trigger Enable Register 0x124 -1 read-write n 0x0 0x0 PF0_PDIO PF0_PDIO GPIO PF.n Pin Data Input/Output Register 0x940 -1 read-write n 0x0 0x0 PF10_PDIO PF10_PDIO GPIO PF.n Pin Data Input/Output Register 0x968 -1 read-write n 0x0 0x0 PF11_PDIO PF11_PDIO GPIO PF.n Pin Data Input/Output Register 0x96C -1 read-write n 0x0 0x0 PF12_PDIO PF12_PDIO GPIO PF.n Pin Data Input/Output Register 0x970 -1 read-write n 0x0 0x0 PF13_PDIO PF13_PDIO GPIO PF.n Pin Data Input/Output Register 0x974 -1 read-write n 0x0 0x0 PF14_PDIO PF14_PDIO GPIO PF.n Pin Data Input/Output Register 0x978 -1 read-write n 0x0 0x0 PF15_PDIO PF15_PDIO GPIO PF.n Pin Data Input/Output Register 0x97C -1 read-write n 0x0 0x0 PF1_PDIO PF1_PDIO GPIO PF.n Pin Data Input/Output Register 0x944 -1 read-write n 0x0 0x0 PF2_PDIO PF2_PDIO GPIO PF.n Pin Data Input/Output Register 0x948 -1 read-write n 0x0 0x0 PF3_PDIO PF3_PDIO GPIO PF.n Pin Data Input/Output Register 0x94C -1 read-write n 0x0 0x0 PF4_PDIO PF4_PDIO GPIO PF.n Pin Data Input/Output Register 0x950 -1 read-write n 0x0 0x0 PF5_PDIO PF5_PDIO GPIO PF.n Pin Data Input/Output Register 0x954 -1 read-write n 0x0 0x0 PF6_PDIO PF6_PDIO GPIO PF.n Pin Data Input/Output Register 0x958 -1 read-write n 0x0 0x0 PF7_PDIO PF7_PDIO GPIO PF.n Pin Data Input/Output Register 0x95C -1 read-write n 0x0 0x0 PF8_PDIO PF8_PDIO GPIO PF.n Pin Data Input/Output Register 0x960 -1 read-write n 0x0 0x0 PF9_PDIO PF9_PDIO GPIO PF.n Pin Data Input/Output Register 0x964 -1 read-write n 0x0 0x0 PF_DATMSK PF_DATMSK PF Data Output Write Mask 0x14C -1 read-write n 0x0 0x0 PF_DBEN PF_DBEN PF De-Bounce Enable Control Register 0x154 -1 read-write n 0x0 0x0 PF_DINOFF PF_DINOFF PF Digital Input Path Disable Control 0x144 -1 read-write n 0x0 0x0 PF_DOUT PF_DOUT PF Data Output Value 0x148 -1 read-write n 0x0 0x0 PF_INTEN PF_INTEN PF Interrupt Enable Control Register 0x15C -1 read-write n 0x0 0x0 PF_INTSRC PF_INTSRC PF Interrupt Source Flag 0x160 -1 read-write n 0x0 0x0 PF_INTTYPE PF_INTTYPE PF Interrupt Trigger Type Control 0x158 -1 read-write n 0x0 0x0 PF_MODE PF_MODE PF I/O Mode Control 0x140 -1 read-write n 0x0 0x0 PF_PIN PF_PIN PF Pin Value 0x150 -1 read-write n 0x0 0x0 PF_PUSEL PF_PUSEL PF Pull-up Selection Register 0x170 -1 read-write n 0x0 0x0 PF_SLEWCTL PF_SLEWCTL PF High Slew Rate Control Register 0x168 -1 read-write n 0x0 0x0 PF_SMTEN PF_SMTEN PF Input Schmitt Trigger Enable Register 0x164 -1 read-write n 0x0 0x0 PG0_PDIO PG0_PDIO GPIO PG.n Pin Data Input/Output Register 0x980 -1 read-write n 0x0 0x0 PG10_PDIO PG10_PDIO GPIO PG.n Pin Data Input/Output Register 0x9A8 -1 read-write n 0x0 0x0 PG11_PDIO PG11_PDIO GPIO PG.n Pin Data Input/Output Register 0x9AC -1 read-write n 0x0 0x0 PG12_PDIO PG12_PDIO GPIO PG.n Pin Data Input/Output Register 0x9B0 -1 read-write n 0x0 0x0 PG1_PDIO PG1_PDIO GPIO PG.n Pin Data Input/Output Register 0x984 -1 read-write n 0x0 0x0 PG2_PDIO PG2_PDIO GPIO PG.n Pin Data Input/Output Register 0x988 -1 read-write n 0x0 0x0 PG3_PDIO PG3_PDIO GPIO PG.n Pin Data Input/Output Register 0x98C -1 read-write n 0x0 0x0 PG4_PDIO PG4_PDIO GPIO PG.n Pin Data Input/Output Register 0x990 -1 read-write n 0x0 0x0 PG5_PDIO PG5_PDIO GPIO PG.n Pin Data Input/Output Register 0x994 -1 read-write n 0x0 0x0 PG6_PDIO PG6_PDIO GPIO PG.n Pin Data Input/Output Register 0x998 -1 read-write n 0x0 0x0 PG7_PDIO PG7_PDIO GPIO PG.n Pin Data Input/Output Register 0x99C -1 read-write n 0x0 0x0 PG8_PDIO PG8_PDIO GPIO PG.n Pin Data Input/Output Register 0x9A0 -1 read-write n 0x0 0x0 PG9_PDIO PG9_PDIO GPIO PG.n Pin Data Input/Output Register 0x9A4 -1 read-write n 0x0 0x0 PG_DATMSK PG_DATMSK PG Data Output Write Mask 0x18C -1 read-write n 0x0 0x0 PG_DBEN PG_DBEN PG De-Bounce Enable Control Register 0x194 -1 read-write n 0x0 0x0 PG_DINOFF PG_DINOFF PG Digital Input Path Disable Control 0x184 -1 read-write n 0x0 0x0 PG_DOUT PG_DOUT PG Data Output Value 0x188 -1 read-write n 0x0 0x0 PG_INTEN PG_INTEN PG Interrupt Enable Control Register 0x19C -1 read-write n 0x0 0x0 PG_INTSRC PG_INTSRC PG Interrupt Source Flag 0x1A0 -1 read-write n 0x0 0x0 PG_INTTYPE PG_INTTYPE PG Interrupt Trigger Type Control 0x198 -1 read-write n 0x0 0x0 PG_MODE PG_MODE PG I/O Mode Control 0x180 -1 read-write n 0x0 0x0 PG_PIN PG_PIN PG Pin Value 0x190 -1 read-write n 0x0 0x0 PG_PUSEL PG_PUSEL PG Pull-up Selection Register 0x1B0 -1 read-write n 0x0 0x0 PG_SLEWCTL PG_SLEWCTL PG High Slew Rate Control Register 0x1A8 -1 read-write n 0x0 0x0 PG_SMTEN PG_SMTEN PG Input Schmitt Trigger Enable Register 0x1A4 -1 read-write n 0x0 0x0 PH0_PDIO PH0_PDIO GPIO PH.n Pin Data Input/Output Register 0x9C0 -1 read-write n 0x0 0x0 PH10_PDIO PH10_PDIO GPIO PH.n Pin Data Input/Output Register 0x9E8 -1 read-write n 0x0 0x0 PH11_PDIO PH11_PDIO GPIO PH.n Pin Data Input/Output Register 0x9EC -1 read-write n 0x0 0x0 PH12_PDIO PH12_PDIO GPIO PH.n Pin Data Input/Output Register 0x9F0 -1 read-write n 0x0 0x0 PH1_PDIO PH1_PDIO GPIO PH.n Pin Data Input/Output Register 0x9C4 -1 read-write n 0x0 0x0 PH2_PDIO PH2_PDIO GPIO PH.n Pin Data Input/Output Register 0x9C8 -1 read-write n 0x0 0x0 PH3_PDIO PH3_PDIO GPIO PH.n Pin Data Input/Output Register 0x9CC -1 read-write n 0x0 0x0 PH4_PDIO PH4_PDIO GPIO PH.n Pin Data Input/Output Register 0x9D0 -1 read-write n 0x0 0x0 PH5_PDIO PH5_PDIO GPIO PH.n Pin Data Input/Output Register 0x9D4 -1 read-write n 0x0 0x0 PH6_PDIO PH6_PDIO GPIO PH.n Pin Data Input/Output Register 0x9D8 -1 read-write n 0x0 0x0 PH7_PDIO PH7_PDIO GPIO PH.n Pin Data Input/Output Register 0x9DC -1 read-write n 0x0 0x0 PH8_PDIO PH8_PDIO GPIO PH.n Pin Data Input/Output Register 0x9E0 -1 read-write n 0x0 0x0 PH9_PDIO PH9_PDIO GPIO PH.n Pin Data Input/Output Register 0x9E4 -1 read-write n 0x0 0x0 PH_DATMSK PH_DATMSK PH Data Output Write Mask 0x1CC -1 read-write n 0x0 0x0 PH_DBEN PH_DBEN PH De-Bounce Enable Control Register 0x1D4 -1 read-write n 0x0 0x0 PH_DINOFF PH_DINOFF PH Digital Input Path Disable Control 0x1C4 -1 read-write n 0x0 0x0 PH_DOUT PH_DOUT PH Data Output Value 0x1C8 -1 read-write n 0x0 0x0 PH_INTEN PH_INTEN PH Interrupt Enable Control Register 0x1DC -1 read-write n 0x0 0x0 PH_INTSRC PH_INTSRC PH Interrupt Source Flag 0x1E0 -1 read-write n 0x0 0x0 PH_INTTYPE PH_INTTYPE PH Interrupt Trigger Type Control 0x1D8 -1 read-write n 0x0 0x0 PH_MODE PH_MODE PH I/O Mode Control 0x1C0 -1 read-write n 0x0 0x0 PH_PIN PH_PIN PH Pin Value 0x1D0 -1 read-write n 0x0 0x0 PH_PUSEL PH_PUSEL PH Pull-up Selection Register 0x1F0 -1 read-write n 0x0 0x0 PH_SLEWCTL PH_SLEWCTL PH High Slew Rate Control Register 0x1E8 -1 read-write n 0x0 0x0 PH_SMTEN PH_SMTEN PH Input Schmitt Trigger Enable Register 0x1E4 -1 read-write n 0x0 0x0 PI0_PDIO PI0_PDIO GPIO PI.n Pin Data Input/Output Register 0xA00 -1 read-write n 0x0 0x0 PI1_PDIO PI1_PDIO GPIO PI.n Pin Data Input/Output Register 0xA04 -1 read-write n 0x0 0x0 PI2_PDIO PI2_PDIO GPIO PI.n Pin Data Input/Output Register 0xA08 -1 read-write n 0x0 0x0 PI3_PDIO PI3_PDIO GPIO PI.n Pin Data Input/Output Register 0xA0C -1 read-write n 0x0 0x0 PI4_PDIO PI4_PDIO GPIO PI.n Pin Data Input/Output Register 0xA10 -1 read-write n 0x0 0x0 PI5_PDIO PI5_PDIO GPIO PI.n Pin Data Input/Output Register 0xA14 -1 read-write n 0x0 0x0 PI6_PDIO PI6_PDIO GPIO PI.n Pin Data Input/Output Register 0xA18 -1 read-write n 0x0 0x0 PI7_PDIO PI7_PDIO GPIO PI.n Pin Data Input/Output Register 0xA1C -1 read-write n 0x0 0x0 PI_DATMSK PI_DATMSK PI Data Output Write Mask 0x20C -1 read-write n 0x0 0x0 PI_DBEN PI_DBEN PI De-Bounce Enable Control Register 0x214 -1 read-write n 0x0 0x0 PI_DINOFF PI_DINOFF PI Digital Input Path Disable Control 0x204 -1 read-write n 0x0 0x0 PI_DOUT PI_DOUT PI Data Output Value 0x208 -1 read-write n 0x0 0x0 PI_INTEN PI_INTEN PI Interrupt Enable Control Register 0x21C -1 read-write n 0x0 0x0 PI_INTSRC PI_INTSRC PI Interrupt Source Flag 0x220 -1 read-write n 0x0 0x0 PI_INTTYPE PI_INTTYPE PI Interrupt Trigger Type Control 0x218 -1 read-write n 0x0 0x0 PI_MODE PI_MODE PI I/O Mode Control 0x200 -1 read-write n 0x0 0x0 PI_PIN PI_PIN PI Pin Value 0x210 -1 read-write n 0x0 0x0 PI_PUSEL PI_PUSEL PI Pull-up Selection Register 0x230 -1 read-write n 0x0 0x0 PI_SLEWCTL PI_SLEWCTL PI High Slew Rate Control Register 0x228 -1 read-write n 0x0 0x0 PI_SMTEN PI_SMTEN PI Input Schmitt Trigger Enable Register 0x224 -1 read-write n 0x0 0x0 I2C0 I2C Register Map I2C 0x0 0x0 0x34 registers n 0x3C 0x30 registers n I2C_ADDR0 I2C_ADDR0 I2C Slave Address Register0 0x4 -1 read-write n 0x0 0x0 ADDR I2C Address The content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched. Note: When software set 10'h000, the address can not be used. 1 10 read-write GC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 I2C_ADDR1 I2C_ADDR1 I2C Slave Address Register1 0x18 -1 read-write n 0x0 0x0 I2C_ADDR2 I2C_ADDR2 I2C Slave Address Register2 0x1C -1 read-write n 0x0 0x0 I2C_ADDR3 I2C_ADDR3 I2C Slave Address Register3 0x20 -1 read-write n 0x0 0x0 I2C_ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register0 0x24 -1 read-write n 0x0 0x0 ADDRMSK I2C Address Mask I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. Note: The wake-up function can not use address mask. 1 10 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 I2C_ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register1 0x28 -1 read-write n 0x0 0x0 I2C_ADDRMSK2 I2C_ADDRMSK2 I2C Slave Address Mask Register2 0x2C -1 read-write n 0x0 0x0 I2C_ADDRMSK3 I2C_ADDRMSK3 I2C Slave Address Mask Register3 0x30 -1 read-write n 0x0 0x0 I2C_BUSCTL I2C_BUSCTL I2C Bus Management Control Register 0x50 -1 read-write n 0x0 0x0 ACKM9SI Acknowledge Manual Enable Extra SI Interrupt 11 1 read-write 0 There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1 #0 1 There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1 #1 ACKMEN Acknowledge Control by Manual In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. 0 1 read-write 0 Slave byte control Disabled #0 1 Slave byte control Enabled. The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse #1 ALERTEN Bus Management Alert Enable Bit 4 1 read-write 0 Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled. BM_ALERT pin not supported #0 1 Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled. BM_ALERT pin supported #1 BCDIEN Packet Error Checking Byte Count Done Interrupt Enable Bit 12 1 read-write 0 Byte count done interrupt Disabled #0 1 Byte count done interrupt Enabled #1 BMDEN Bus Management Device Default Address Enable Bit 2 1 read-write 0 Device default address Disable. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed #0 1 Device default address Enabled. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed #1 BMHEN Bus Management Host Enable Bit 3 1 read-write 0 Host function Disabled #0 1 Host function Enabled #1 BUSEN BUS Enable Bit Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. 7 1 read-write 0 The system management function Disabled #0 1 The system management function Enabled #1 PECCLR PEC Clear at Repeat Start The calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation. 10 1 read-write 0 PEC calculation is cleared by 'Repeat Start' function Disabled #0 1 PEC calculation is cleared by 'Repeat Start' function Enabled #1 PECDIEN Packet Error Checking Byte Transfer Done Interrupt Enable Bit 13 1 read-write 0 PEC transfer done interrupt Disabled #0 1 PEC transfer done interrupt Enabled #1 PECEN Packet Error Checking Calculation Enable Bit Note: When I2C enter powerdown mode, the bit should be enabled after wake-up if needed PEC calculation. 1 1 read-write 0 Packet Error Checking Calculation Disabled #0 1 Packet Error Checking Calculation Enabled #1 PECTXEN Packet Error Checking Byte Transmission/Reception 8 1 read-write 0 No PEC transfer #0 1 PEC transmission is requested #1 SCTLOEN Suspend or Control Pin Output Enable Bit 6 1 read-write 0 The SUSCON pin in input #0 1 The output enable is active on the SUSCON pin #1 SCTLOSTS Suspend/Control Data Output Status 5 1 read-write 0 The output of SUSCON pin is low #0 1 The output of SUSCON pin is high #1 TIDLE Timer Check in Idle State The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled. Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state. 9 1 read-write 0 BUSTOUT is used to calculate the clock low period in bus active #0 1 BUSTOUT is used to calculate the IDLE period in bus Idle #1 I2C_BUSSTS I2C_BUSSTS I2C Bus Management Status Register 0x58 -1 read-write n 0x0 0x0 ALERT SMBus Alert Status Note: 1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit. 3 1 read-write 0 SMBALERT pin state is low. No SMBALERT event #0 1 SMBALERT pin state is high. There is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1 #1 BCDONE Byte Count Transmission/Receive Done Note: Software can write 1 to clear this bit. 1 1 read-write 0 Byte count transmission/ receive is not finished when the PECEN is set #0 1 Byte count transmission/ receive is finished when the PECEN is set #1 BUSTO Bus Time-out Status In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. Note: Software can write 1 to clear this bit. 5 1 read-write 0 There is no any time-out or external clock time-out #0 1 A time-out or external clock time-out occurred #1 BUSY Bus Busy Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 0 1 read-write 0 Bus is IDLE (both SCLK and SDA High) #0 1 Bus is busy #1 CLKTO Clock Low Cumulate Time-out Status Note: Software can write 1 to clear this bit. 6 1 read-write 0 Cumulative clock low is no any time-out #0 1 Cumulative clock low time-out occurred #1 PECDONE PEC Byte Transmission/Receive Done Note: Software can write 1 to clear this bit. 7 1 read-write 0 PEC transmission/ receive is not finished when the PECEN is set #0 1 PEC transmission/ receive is finished when the PECEN is set #1 PECERR PEC Error in Reception Note: Software can write 1 to clear this bit. 2 1 read-write 0 PEC value equal the received PEC data packet #0 1 PEC value doesn't match the receive PEC data packet #1 SCTLDIN Bus Suspend or Control Signal Input Status 4 1 read-write 0 The input status of SUSCON pin is 0 #0 1 The input status of SUSCON pin is 1 #1 I2C_BUSTCTL I2C_BUSTCTL I2C Bus Management Timer Control Register 0x54 -1 read-write n 0x0 0x0 BUSTOEN Bus Time Out Enable Bit 0 1 read-write 0 Bus clock low time-out detection Disabled #0 1 Bus clock low time-out detection Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1) #1 BUSTOIEN Time-out Interrupt Enable Bit 2 1 read-write 0 SCLK low time-out interrupt Disabled. Bus IDLE time-out interrupt Disabled #0 1 SCLK low time-out interrupt Enabled. Bus IDLE time-out interrupt Enabled #1 CLKTOEN Cumulative Clock Low Time Out Enable Bit For Master, it calculates the period from START to ACK For Slave, it calculates the period from START to STOP 1 1 read-write 0 Cumulative clock low time-out detection Disabled #0 1 Cumulative clock low time-out detection Enabled #1 CLKTOIEN Extended Clock Time Out Interrupt Enable Bit 3 1 read-write 0 Clock time out interrupt Disabled #0 1 Clock time out interrupt Enabled #1 TORSTEN Time Out Reset Enable Bit 4 1 read-write 0 I2C state machine reset Disabled #0 1 I2C state machine reset Enabled. (The clock and data bus will be released to high) #1 I2C_BUSTOUT I2C_BUSTOUT I2C Bus Management Timer Register 0x64 -1 read-write n 0x0 0x0 BUSTO Bus Management Time-out Value Indicates the bus time-out value in bus is IDLE or SCLK low. Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first when the BUSEN(I2C_BUSCTL[7]) is set. 0 8 read-write I2C_CLKDIV I2C_CLKDIV I2C Clock Divided Register 0x10 -1 read-write n 0x0 0x0 DIVIDER I2C Clock Divided Note: The minimum value of I2C_CLKDIV is 4. 0 10 read-write NFCNT Noise Filter Counter The register bits control the input filter width. 0 : filter width 3*PCLK 1 : filter width 4*PCLK N : filter width (3+N)*PCKL Note: Filter width Min :3*PCLK, Max : 18*PCLK 12 4 read-write I2C_CLKTOUT I2C_CLKTOUT I2C Bus Management Clock Low Timer Register 0x68 -1 read-write n 0x0 0x0 CLKTO Bus Clock Low Timer The field is used to configure the cumulative clock extension time-out. Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and cleared to 0 first when the BUSEN is set. 0 8 read-write I2C_CTL0 I2C_CTL0 I2C Control Register 0 0x0 -1 read-write n 0x0 0x0 AA Assert Acknowledge Control 2 1 read-write I2CEN I2C Controller Enable Bit 6 1 read-write 0 I2C controller Disabled #0 1 I2C controller Enabled #1 INTEN Enable Interrupt 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 SI I2C Interrupt Flag When a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit. For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. 3 1 read-write STA I2C START Control Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically. 4 1 read-write I2C_CTL1 I2C_CTL1 I2C Control Register 1 0x44 -1 read-write n 0x0 0x0 ADDR10EN Address 10-bit Function Enable Bit 9 1 read-write 0 Address match 10-bit function Disabled #0 1 Address match 10-bit function Enabled #1 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the I2C request to PDMA #1 PDMASTR PDMA Stretch Bit 8 1 read-write 0 I2C send STOP automatically after PDMA transfer done. (only master TX) #0 1 I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX) #1 RXPDMAEN PDMA Receive Channel Available 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN PDMA Transmit Channel Available 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 I2C_DAT I2C_DAT I2C Data Register 0x8 -1 read-write n 0x0 0x0 DAT I2C Data Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port. 0 8 read-write I2C_PKTCRC I2C_PKTCRC I2C Packet Error Checking Byte Value Register 0x60 -1 read-only n 0x0 0x0 PECCRC Packet Error Checking Byte Value 0 8 read-only I2C_PKTSIZE I2C_PKTSIZE I2C Packet Error Checking Byte Number Register 0x5C -1 read-write n 0x0 0x0 PLDSIZE Transfer Byte Number The transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes. Note: The byte number counting includes address, command code, and data frame. 0 9 read-write I2C_STATUS0 I2C_STATUS0 I2C Status Register 0 0xC -1 read-only n 0x0 0x0 STATUS I2C Status 0 8 read-only I2C_STATUS1 I2C_STATUS1 I2C Status Register 1 0x48 -1 read-write n 0x0 0x0 ADMAT0 I2C Address 0 Match Status When address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 0 1 read-write ADMAT1 I2C Address 1 Match Status When address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 1 1 read-write ADMAT2 I2C Address 2 Match Status When address 2 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 2 1 read-write ADMAT3 I2C Address 3 Match Status When address 3 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 3 1 read-write ONBUSY On Bus Busy (Read Only) Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected. 8 1 read-only 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 I2C_TMCTL I2C_TMCTL I2C Timing Configure Control Register 0x4C -1 read-write n 0x0 0x0 HTCTL Hold Time Configure Control This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. 16 9 read-write STCTL Setup Time Configure Control This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode. Note: Setup time setting should not make SCL output less than three PCLKs. 0 9 read-write I2C_TOCTL I2C_TOCTL I2C Time-out Control Register 0x14 -1 read-write n 0x0 0x0 TOCDIV4 Time-out Counter Input Clock Divided by 4 When enabled, the time-out period is extended 4 times. 1 1 read-write 0 Time-out period is extend 4 times Disabled #0 1 Time-out period is extend 4 times Enabled #1 TOCEN Time-out Counter Enable Bit When enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. 2 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOIF Time-out Flag This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1. Note: Software can write 1 to clear this bit. 0 1 read-write I2C_WKCTL I2C_WKCTL I2C Wake-up Control Register 0x3C -1 read-write n 0x0 0x0 NHDBUSEN I2C No Hold BUS Enable Bit Note: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. 7 1 read-write 0 I2C hold bus after wake-up #0 1 I2C don't hold bus after wake-up #1 WKEN I2C Wake-up Enable Bit 0 1 read-write 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 I2C_WKSTS I2C_WKSTS I2C Wake-up Status Register 0x40 -1 read-write n 0x0 0x0 WKAKDONE Wakeup Address Frame Acknowledge Bit Done Note: This bit can't release WKIF. Software can write 1 to clear this bit. 1 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WKIF I2C Wake-up Flag When chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write WRSTSWK Read/Write Status Bit in Address Wakeup Frame Note: This bit will be cleared when software can write 1 to WKAKDONE bit. 2 1 read-write 0 Write command be record on the address match wakeup frame #0 1 Read command be record on the address match wakeup frame #1 I2C1 I2C Register Map I2C 0x0 0x0 0x34 registers n 0x3C 0x30 registers n I2C_ADDR0 I2C_ADDR0 I2C Slave Address Register0 0x4 -1 read-write n 0x0 0x0 ADDR I2C Address The content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched. Note: When software set 10'h000, the address can not be used. 1 10 read-write GC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 I2C_ADDR1 I2C_ADDR1 I2C Slave Address Register1 0x18 -1 read-write n 0x0 0x0 I2C_ADDR2 I2C_ADDR2 I2C Slave Address Register2 0x1C -1 read-write n 0x0 0x0 I2C_ADDR3 I2C_ADDR3 I2C Slave Address Register3 0x20 -1 read-write n 0x0 0x0 I2C_ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register0 0x24 -1 read-write n 0x0 0x0 ADDRMSK I2C Address Mask I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. Note: The wake-up function can not use address mask. 1 10 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 I2C_ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register1 0x28 -1 read-write n 0x0 0x0 I2C_ADDRMSK2 I2C_ADDRMSK2 I2C Slave Address Mask Register2 0x2C -1 read-write n 0x0 0x0 I2C_ADDRMSK3 I2C_ADDRMSK3 I2C Slave Address Mask Register3 0x30 -1 read-write n 0x0 0x0 I2C_BUSCTL I2C_BUSCTL I2C Bus Management Control Register 0x50 -1 read-write n 0x0 0x0 ACKM9SI Acknowledge Manual Enable Extra SI Interrupt 11 1 read-write 0 There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1 #0 1 There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1 #1 ACKMEN Acknowledge Control by Manual In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. 0 1 read-write 0 Slave byte control Disabled #0 1 Slave byte control Enabled. The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse #1 ALERTEN Bus Management Alert Enable Bit 4 1 read-write 0 Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled. BM_ALERT pin not supported #0 1 Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled. BM_ALERT pin supported #1 BCDIEN Packet Error Checking Byte Count Done Interrupt Enable Bit 12 1 read-write 0 Byte count done interrupt Disabled #0 1 Byte count done interrupt Enabled #1 BMDEN Bus Management Device Default Address Enable Bit 2 1 read-write 0 Device default address Disable. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed #0 1 Device default address Enabled. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed #1 BMHEN Bus Management Host Enable Bit 3 1 read-write 0 Host function Disabled #0 1 Host function Enabled #1 BUSEN BUS Enable Bit Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. 7 1 read-write 0 The system management function Disabled #0 1 The system management function Enabled #1 PECCLR PEC Clear at Repeat Start The calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation. 10 1 read-write 0 PEC calculation is cleared by 'Repeat Start' function Disabled #0 1 PEC calculation is cleared by 'Repeat Start' function Enabled #1 PECDIEN Packet Error Checking Byte Transfer Done Interrupt Enable Bit 13 1 read-write 0 PEC transfer done interrupt Disabled #0 1 PEC transfer done interrupt Enabled #1 PECEN Packet Error Checking Calculation Enable Bit Note: When I2C enter powerdown mode, the bit should be enabled after wake-up if needed PEC calculation. 1 1 read-write 0 Packet Error Checking Calculation Disabled #0 1 Packet Error Checking Calculation Enabled #1 PECTXEN Packet Error Checking Byte Transmission/Reception 8 1 read-write 0 No PEC transfer #0 1 PEC transmission is requested #1 SCTLOEN Suspend or Control Pin Output Enable Bit 6 1 read-write 0 The SUSCON pin in input #0 1 The output enable is active on the SUSCON pin #1 SCTLOSTS Suspend/Control Data Output Status 5 1 read-write 0 The output of SUSCON pin is low #0 1 The output of SUSCON pin is high #1 TIDLE Timer Check in Idle State The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled. Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state. 9 1 read-write 0 BUSTOUT is used to calculate the clock low period in bus active #0 1 BUSTOUT is used to calculate the IDLE period in bus Idle #1 I2C_BUSSTS I2C_BUSSTS I2C Bus Management Status Register 0x58 -1 read-write n 0x0 0x0 ALERT SMBus Alert Status Note: 1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit. 3 1 read-write 0 SMBALERT pin state is low. No SMBALERT event #0 1 SMBALERT pin state is high. There is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1 #1 BCDONE Byte Count Transmission/Receive Done Note: Software can write 1 to clear this bit. 1 1 read-write 0 Byte count transmission/ receive is not finished when the PECEN is set #0 1 Byte count transmission/ receive is finished when the PECEN is set #1 BUSTO Bus Time-out Status In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. Note: Software can write 1 to clear this bit. 5 1 read-write 0 There is no any time-out or external clock time-out #0 1 A time-out or external clock time-out occurred #1 BUSY Bus Busy Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 0 1 read-write 0 Bus is IDLE (both SCLK and SDA High) #0 1 Bus is busy #1 CLKTO Clock Low Cumulate Time-out Status Note: Software can write 1 to clear this bit. 6 1 read-write 0 Cumulative clock low is no any time-out #0 1 Cumulative clock low time-out occurred #1 PECDONE PEC Byte Transmission/Receive Done Note: Software can write 1 to clear this bit. 7 1 read-write 0 PEC transmission/ receive is not finished when the PECEN is set #0 1 PEC transmission/ receive is finished when the PECEN is set #1 PECERR PEC Error in Reception Note: Software can write 1 to clear this bit. 2 1 read-write 0 PEC value equal the received PEC data packet #0 1 PEC value doesn't match the receive PEC data packet #1 SCTLDIN Bus Suspend or Control Signal Input Status 4 1 read-write 0 The input status of SUSCON pin is 0 #0 1 The input status of SUSCON pin is 1 #1 I2C_BUSTCTL I2C_BUSTCTL I2C Bus Management Timer Control Register 0x54 -1 read-write n 0x0 0x0 BUSTOEN Bus Time Out Enable Bit 0 1 read-write 0 Bus clock low time-out detection Disabled #0 1 Bus clock low time-out detection Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1) #1 BUSTOIEN Time-out Interrupt Enable Bit 2 1 read-write 0 SCLK low time-out interrupt Disabled. Bus IDLE time-out interrupt Disabled #0 1 SCLK low time-out interrupt Enabled. Bus IDLE time-out interrupt Enabled #1 CLKTOEN Cumulative Clock Low Time Out Enable Bit For Master, it calculates the period from START to ACK For Slave, it calculates the period from START to STOP 1 1 read-write 0 Cumulative clock low time-out detection Disabled #0 1 Cumulative clock low time-out detection Enabled #1 CLKTOIEN Extended Clock Time Out Interrupt Enable Bit 3 1 read-write 0 Clock time out interrupt Disabled #0 1 Clock time out interrupt Enabled #1 TORSTEN Time Out Reset Enable Bit 4 1 read-write 0 I2C state machine reset Disabled #0 1 I2C state machine reset Enabled. (The clock and data bus will be released to high) #1 I2C_BUSTOUT I2C_BUSTOUT I2C Bus Management Timer Register 0x64 -1 read-write n 0x0 0x0 BUSTO Bus Management Time-out Value Indicates the bus time-out value in bus is IDLE or SCLK low. Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first when the BUSEN(I2C_BUSCTL[7]) is set. 0 8 read-write I2C_CLKDIV I2C_CLKDIV I2C Clock Divided Register 0x10 -1 read-write n 0x0 0x0 DIVIDER I2C Clock Divided Note: The minimum value of I2C_CLKDIV is 4. 0 10 read-write NFCNT Noise Filter Counter The register bits control the input filter width. 0 : filter width 3*PCLK 1 : filter width 4*PCLK N : filter width (3+N)*PCKL Note: Filter width Min :3*PCLK, Max : 18*PCLK 12 4 read-write I2C_CLKTOUT I2C_CLKTOUT I2C Bus Management Clock Low Timer Register 0x68 -1 read-write n 0x0 0x0 CLKTO Bus Clock Low Timer The field is used to configure the cumulative clock extension time-out. Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and cleared to 0 first when the BUSEN is set. 0 8 read-write I2C_CTL0 I2C_CTL0 I2C Control Register 0 0x0 -1 read-write n 0x0 0x0 AA Assert Acknowledge Control 2 1 read-write I2CEN I2C Controller Enable Bit 6 1 read-write 0 I2C controller Disabled #0 1 I2C controller Enabled #1 INTEN Enable Interrupt 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 SI I2C Interrupt Flag When a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit. For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. 3 1 read-write STA I2C START Control Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically. 4 1 read-write I2C_CTL1 I2C_CTL1 I2C Control Register 1 0x44 -1 read-write n 0x0 0x0 ADDR10EN Address 10-bit Function Enable Bit 9 1 read-write 0 Address match 10-bit function Disabled #0 1 Address match 10-bit function Enabled #1 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the I2C request to PDMA #1 PDMASTR PDMA Stretch Bit 8 1 read-write 0 I2C send STOP automatically after PDMA transfer done. (only master TX) #0 1 I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX) #1 RXPDMAEN PDMA Receive Channel Available 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN PDMA Transmit Channel Available 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 I2C_DAT I2C_DAT I2C Data Register 0x8 -1 read-write n 0x0 0x0 DAT I2C Data Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port. 0 8 read-write I2C_PKTCRC I2C_PKTCRC I2C Packet Error Checking Byte Value Register 0x60 -1 read-only n 0x0 0x0 PECCRC Packet Error Checking Byte Value 0 8 read-only I2C_PKTSIZE I2C_PKTSIZE I2C Packet Error Checking Byte Number Register 0x5C -1 read-write n 0x0 0x0 PLDSIZE Transfer Byte Number The transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes. Note: The byte number counting includes address, command code, and data frame. 0 9 read-write I2C_STATUS0 I2C_STATUS0 I2C Status Register 0 0xC -1 read-only n 0x0 0x0 STATUS I2C Status 0 8 read-only I2C_STATUS1 I2C_STATUS1 I2C Status Register 1 0x48 -1 read-write n 0x0 0x0 ADMAT0 I2C Address 0 Match Status When address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 0 1 read-write ADMAT1 I2C Address 1 Match Status When address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 1 1 read-write ADMAT2 I2C Address 2 Match Status When address 2 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 2 1 read-write ADMAT3 I2C Address 3 Match Status When address 3 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 3 1 read-write ONBUSY On Bus Busy (Read Only) Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected. 8 1 read-only 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 I2C_TMCTL I2C_TMCTL I2C Timing Configure Control Register 0x4C -1 read-write n 0x0 0x0 HTCTL Hold Time Configure Control This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. 16 9 read-write STCTL Setup Time Configure Control This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode. Note: Setup time setting should not make SCL output less than three PCLKs. 0 9 read-write I2C_TOCTL I2C_TOCTL I2C Time-out Control Register 0x14 -1 read-write n 0x0 0x0 TOCDIV4 Time-out Counter Input Clock Divided by 4 When enabled, the time-out period is extended 4 times. 1 1 read-write 0 Time-out period is extend 4 times Disabled #0 1 Time-out period is extend 4 times Enabled #1 TOCEN Time-out Counter Enable Bit When enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. 2 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOIF Time-out Flag This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1. Note: Software can write 1 to clear this bit. 0 1 read-write I2C_WKCTL I2C_WKCTL I2C Wake-up Control Register 0x3C -1 read-write n 0x0 0x0 NHDBUSEN I2C No Hold BUS Enable Bit Note: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. 7 1 read-write 0 I2C hold bus after wake-up #0 1 I2C don't hold bus after wake-up #1 WKEN I2C Wake-up Enable Bit 0 1 read-write 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 I2C_WKSTS I2C_WKSTS I2C Wake-up Status Register 0x40 -1 read-write n 0x0 0x0 WKAKDONE Wakeup Address Frame Acknowledge Bit Done Note: This bit can't release WKIF. Software can write 1 to clear this bit. 1 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WKIF I2C Wake-up Flag When chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write WRSTSWK Read/Write Status Bit in Address Wakeup Frame Note: This bit will be cleared when software can write 1 to WKAKDONE bit. 2 1 read-write 0 Write command be record on the address match wakeup frame #0 1 Read command be record on the address match wakeup frame #1 NMI NMI Register Map NMI 0x0 0x0 0x8 registers n NMIEN NMIEN NMI Source Interrupt Enable Register 0x0 -1 read-write n 0x0 0x0 BODOUT BOD NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 BOD NMI source Disabled #0 1 BOD NMI source Enabled #1 CLKFAIL Clock Fail Detected NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 Clock fail detected interrupt NMI source Disabled #0 1 Clock fail detected interrupt NMI source Enabled #1 EINT0 External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 8 1 read-write 0 External interrupt from PA.6 or PB.5 pin NMI source Disabled #0 1 External interrupt from PA.6 or PB.5 pin NMI source Enabled #1 EINT1 External Interrupt From PA.7, PB.4 or PD.15 NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 9 1 read-write 0 External interrupt from PA.7, PB.4 or PD.15 pin NMI source Disabled #0 1 External interrupt from PA.7, PB.4 or PD.15 pin NMI source Enabled #1 EINT2 External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 10 1 read-write 0 External interrupt from PB.3 or PC.6 pin NMI source Disabled #0 1 External interrupt from PB.3 or PC.6 pin NMI source Enabled #1 EINT3 External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 11 1 read-write 0 External interrupt from PB.2 or PC.7 pin NMI source Disabled #0 1 External interrupt from PB.2 or PC.7 pin NMI source Enabled #1 EINT4 External Interrupt From PA.8, PB.6 or PF.15 Pin NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 12 1 read-write 0 External interrupt from PA.8, PB.6 or PF.15 pin NMI source Disabled #0 1 External interrupt from PA.8, PB.6 or PF.15 pin NMI source Enabled #1 EINT5 External Interrupt From PB.7, PD.12 or PF.14 Pin NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 13 1 read-write 0 External interrupt from PB.7, PD.12 or PF.14 pin NMI source Disabled #0 1 External interrupt from PB.7, PD.12 or PF.14 pin NMI source Enabled #1 IRC_INT IRC TRIM NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 IRC TRIM NMI source Disabled #0 1 IRC TRIM NMI source Enabled #1 PWRWU_INT Power-down Mode Wake-up NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 Power-down mode wake-up NMI source Disabled #0 1 Power-down mode wake-up NMI source Enabled #1 RTC_INT RTC NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 RTC NMI source Disabled #0 1 RTC NMI source Enabled #1 SRAM_PERR SRAM ParityCheck Error NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 SRAM parity check error NMI source Disabled #0 1 SRAM parity check error NMI source Enabled #1 UART0_INT UART0 NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 14 1 read-write 0 UART0 NMI source Disabled #0 1 UART0 NMI source Enabled #1 UART1_INT UART1 NMI Source Enable (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 15 1 read-write 0 UART1 NMI source Disabled #0 1 UART1 NMI source Enabled #1 NMISTS NMISTS NMI Source Interrupt Status Register 0x4 -1 read-only n 0x0 0x0 BODOUT BOD Interrupt Flag (Read Only) 0 1 read-only 0 BOD interrupt is deasserted #0 1 BOD interrupt is asserted #1 CLKFAIL Clock Fail Detected Interrupt Flag (Read Only) 4 1 read-only 0 Clock fail detected interrupt is deasserted #0 1 Clock fail detected interrupt is asserted #1 EINT0 External Interrupt From PA.6 or PB.5 Pin Interrupt Flag (Read Only) 8 1 read-only 0 External Interrupt from PA.6 or PB.5 interrupt is deasserted #0 1 External Interrupt from PA.6 or PB.5 interrupt is asserted #1 EINT1 External Interrupt From PA.7, PB.4 or PD.15 Pin Interrupt Flag (Read Only) 9 1 read-only 0 External Interrupt from PA.7, PB.4 or PD.15 interrupt is deasserted #0 1 External Interrupt from PA.7, PB.4 or PD.15 interrupt is asserted #1 EINT2 External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only) 10 1 read-only 0 External Interrupt from PB.3 or PC.6 interrupt is deasserted #0 1 External Interrupt from PB.3 or PC.6 interrupt is asserted #1 EINT3 External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only) 11 1 read-only 0 External Interrupt from PB.2 or PC.7 interrupt is deasserted #0 1 External Interrupt from PB.2 or PC.7 interrupt is asserted #1 EINT4 External Interrupt From PA.8, PB.6 or PF.15 Pin Interrupt Flag (Read Only) 12 1 read-only 0 External Interrupt from PA.8, PB.6 or PF.15 interrupt is deasserted #0 1 External Interrupt from PA.8, PB.6 or PF.15 interrupt is asserted #1 EINT5 External Interrupt From PB.7, PD.12 or PF.14 Pin Interrupt Flag (Read Only) 13 1 read-only 0 External Interrupt from PB.7, PD.12 or PF.14 interrupt is deasserted #0 1 External Interrupt from PB.7, PD.12 or PF.14 interrupt is asserted #1 IRC_INT IRC TRIM Interrupt Flag (Read Only) 1 1 read-only 0 HIRC TRIM interrupt is deasserted #0 1 HIRC TRIM interrupt is asserted #1 PWRWU_INT Power-down Mode Wake-up Interrupt Flag (Read Only) 2 1 read-only 0 Power-down mode wake-up interrupt is deasserted #0 1 Power-down mode wake-up interrupt is asserted #1 RTC_INT RTC Interrupt Flag (Read Only) 6 1 read-only 0 RTC interrupt is deasserted #0 1 RTC interrupt is asserted #1 SRAM_PERR SRAM ParityCheck Error Interrupt Flag (Read Only) 3 1 read-only 0 SRAM parity check error interrupt is deasserted #0 1 SRAM parity check error interrupt is asserted #1 UART0_INT UART0 Interrupt Flag (Read Only) 14 1 read-only 0 UART0 interrupt is deasserted #0 1 UART0 interrupt is asserted #1 UART1_INT UART1 Interrupt Flag (Read Only) 15 1 read-only 0 UART1 interrupt is deasserted #0 1 UART1 interrupt is asserted #1 NVIC NVIC Register Map NVIC 0x0 0x0 0x10 registers n 0x100 0x10 registers n 0x180 0x10 registers n 0x200 0x10 registers n 0x300 0x74 registers n 0x80 0x10 registers n 0xE00 0x4 registers n IABR0 NVIC_IABR0 IRQ0 ~ IRQ111 Active Bit Register 0x200 -1 read-write n 0x0 0x0 ACTIVE Interrupt Active Flags The NVIC_IABR0-NVIC_IABR0 registers indicate which interrupts are active. 0 32 read-write 0 interrupt not active 0 1 interrupt active 1 IABR1 NVIC_IABR1 IRQ0 ~ IRQ111 Active Bit Register 0x204 -1 read-write n 0x0 0x0 ACTIVE Interrupt Active Flags The NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active. 0 32 read-write 0 interrupt not active 0 1 interrupt active 1 IABR2 NVIC_IABR2 IRQ0 ~ IRQ111 Active Bit Register 0x208 -1 read-write n 0x0 0x0 ACTIVE Interrupt Active Flags The NVIC_IABR0-NVIC_IABR2 registers indicate which interrupts are active. 0 32 read-write 0 interrupt not active 0 1 interrupt active 1 IABR3 NVIC_IABR3 IRQ0 ~ IRQ111 Active Bit Register 0x20C -1 read-write n 0x0 0x0 ACTIVE Interrupt Active Flags The NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active. 0 32 read-write 0 interrupt not active 0 1 interrupt active 1 ICER0 NVIC_ICER0 IRQ0 ~ IRQ111 Clear-enable Control Register 0x80 -1 read-write n 0x0 0x0 CALENA Interrupt Clear Enable Bit The NVIC_ICER0-NVIC_ICER0 registers disable interrupts, and show which interrupts are enabled. Write Operation: 0 32 read-write 0 No effect. Interrupt Disabled 0 1 Interrupt Disabled. Interrupt Enabled 1 ICER1 NVIC_ICER1 IRQ0 ~ IRQ111 Clear-enable Control Register 0x84 -1 read-write n 0x0 0x0 CALENA Interrupt Clear Enable Bit The NVIC_ICER0-NVIC_ICER1 registers disable interrupts, and show which interrupts are enabled. Write Operation: 0 32 read-write 0 No effect. Interrupt Disabled 0 1 Interrupt Disabled. Interrupt Enabled 1 ICER2 NVIC_ICER2 IRQ0 ~ IRQ111 Clear-enable Control Register 0x88 -1 read-write n 0x0 0x0 CALENA Interrupt Clear Enable Bit The NVIC_ICER0-NVIC_ICER2 registers disable interrupts, and show which interrupts are enabled. Write Operation: 0 32 read-write 0 No effect. Interrupt Disabled 0 1 Interrupt Disabled. Interrupt Enabled 1 ICER3 NVIC_ICER3 IRQ0 ~ IRQ111 Clear-enable Control Register 0x8C -1 read-write n 0x0 0x0 CALENA Interrupt Clear Enable Bit The NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled. Write Operation: 0 32 read-write 0 No effect. Interrupt Disabled 0 1 Interrupt Disabled. Interrupt Enabled 1 ICPR0 NVIC_ICPR0 IRQ0 ~ IRQ111 Clear-pending Control Register 0x180 -1 read-write n 0x0 0x0 CALPEND Interrupt Clear-pending The NVIC_ICPR0-NVIC_ICPR0 registers remove the pending state from interrupts, and show which interrupts are pending Write Operation: 0 32 read-write 0 No effect. Interrupt is not pending 0 1 Removes pending state an interrupt. Interrupt is pending 1 ICPR1 NVIC_ICPR1 IRQ0 ~ IRQ111 Clear-pending Control Register 0x184 -1 read-write n 0x0 0x0 CALPEND Interrupt Clear-pending The NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts, and show which interrupts are pending Write Operation: 0 32 read-write 0 No effect. Interrupt is not pending 0 1 Removes pending state an interrupt. Interrupt is pending 1 ICPR2 NVIC_ICPR2 IRQ0 ~ IRQ111 Clear-pending Control Register 0x188 -1 read-write n 0x0 0x0 CALPEND Interrupt Clear-pending The NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts, and show which interrupts are pending Write Operation: 0 32 read-write 0 No effect. Interrupt is not pending 0 1 Removes pending state an interrupt. Interrupt is pending 1 ICPR3 NVIC_ICPR3 IRQ0 ~ IRQ111 Clear-pending Control Register 0x18C -1 read-write n 0x0 0x0 CALPEND Interrupt Clear-pending The NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending Write Operation: 0 32 read-write 0 No effect. Interrupt is not pending 0 1 Removes pending state an interrupt. Interrupt is pending 1 IPR0 NVIC_IPR0 IRQ0 ~ IRQ111 Priority Control Register 0x300 -1 read-write n 0x0 0x0 PRI_4n_0 Priority of IRQ_4n+0 '0' denotes the highest priority and '15' denotes the lowest priority 4 4 read-write PRI_4n_1 Priority of IRQ_4n+1 '0' denotes the highest priority and '15' denotes the lowest priority 12 4 read-write PRI_4n_2 Priority of IRQ_4n+2 '0' denotes the highest priority and '15' denotes the lowest priority 20 4 read-write PRI_4n_3 Priority of IRQ_4n+3 '0' denotes the highest priority and '15' denotes the lowest priority 28 4 read-write IPR1 NVIC_IPR1 IRQ0 ~ IRQ111 Priority Control Register 0x304 -1 read-write n 0x0 0x0 IPR10 NVIC_IPR10 IRQ0 ~ IRQ111 Priority Control Register 0x328 -1 read-write n 0x0 0x0 IPR11 NVIC_IPR11 IRQ0 ~ IRQ111 Priority Control Register 0x32C -1 read-write n 0x0 0x0 IPR12 NVIC_IPR12 IRQ0 ~ IRQ111 Priority Control Register 0x330 -1 read-write n 0x0 0x0 IPR13 NVIC_IPR13 IRQ0 ~ IRQ111 Priority Control Register 0x334 -1 read-write n 0x0 0x0 IPR14 NVIC_IPR14 IRQ0 ~ IRQ111 Priority Control Register 0x338 -1 read-write n 0x0 0x0 IPR15 NVIC_IPR15 IRQ0 ~ IRQ111 Priority Control Register 0x33C -1 read-write n 0x0 0x0 IPR16 NVIC_IPR16 IRQ0 ~ IRQ111 Priority Control Register 0x340 -1 read-write n 0x0 0x0 IPR17 NVIC_IPR17 IRQ0 ~ IRQ111 Priority Control Register 0x344 -1 read-write n 0x0 0x0 IPR18 NVIC_IPR18 IRQ0 ~ IRQ111 Priority Control Register 0x348 -1 read-write n 0x0 0x0 IPR19 NVIC_IPR19 IRQ0 ~ IRQ111 Priority Control Register 0x34C -1 read-write n 0x0 0x0 IPR2 NVIC_IPR2 IRQ0 ~ IRQ111 Priority Control Register 0x308 -1 read-write n 0x0 0x0 IPR20 NVIC_IPR20 IRQ0 ~ IRQ111 Priority Control Register 0x350 -1 read-write n 0x0 0x0 IPR21 NVIC_IPR21 IRQ0 ~ IRQ111 Priority Control Register 0x354 -1 read-write n 0x0 0x0 IPR22 NVIC_IPR22 IRQ0 ~ IRQ111 Priority Control Register 0x358 -1 read-write n 0x0 0x0 IPR23 NVIC_IPR23 IRQ0 ~ IRQ111 Priority Control Register 0x35C -1 read-write n 0x0 0x0 IPR24 NVIC_IPR24 IRQ0 ~ IRQ111 Priority Control Register 0x360 -1 read-write n 0x0 0x0 IPR25 NVIC_IPR25 IRQ0 ~ IRQ111 Priority Control Register 0x364 -1 read-write n 0x0 0x0 IPR26 NVIC_IPR26 IRQ0 ~ IRQ111 Priority Control Register 0x368 -1 read-write n 0x0 0x0 IPR27 NVIC_IPR27 IRQ0 ~ IRQ111 Priority Control Register 0x36C -1 read-write n 0x0 0x0 IPR28 NVIC_IPR28 IRQ0 ~ IRQ111 Priority Control Register 0x370 -1 read-write n 0x0 0x0 IPR3 NVIC_IPR3 IRQ0 ~ IRQ111 Priority Control Register 0x30C -1 read-write n 0x0 0x0 IPR4 NVIC_IPR4 IRQ0 ~ IRQ111 Priority Control Register 0x310 -1 read-write n 0x0 0x0 IPR5 NVIC_IPR5 IRQ0 ~ IRQ111 Priority Control Register 0x314 -1 read-write n 0x0 0x0 IPR6 NVIC_IPR6 IRQ0 ~ IRQ111 Priority Control Register 0x318 -1 read-write n 0x0 0x0 IPR7 NVIC_IPR7 IRQ0 ~ IRQ111 Priority Control Register 0x31C -1 read-write n 0x0 0x0 IPR8 NVIC_IPR8 IRQ0 ~ IRQ111 Priority Control Register 0x320 -1 read-write n 0x0 0x0 IPR9 NVIC_IPR9 IRQ0 ~ IRQ111 Priority Control Register 0x324 -1 read-write n 0x0 0x0 ISER0 NVIC_ISER0 IRQ0 ~ IRQ111 Set-enable Control Register 0x0 -1 read-write n 0x0 0x0 SETENA Interrupt Set Enable Bit The NVIC_ISER0-NVIC_ISER0 registers enable interrupts, and show which interrupts are enabled Write Operation: 0 32 read-write 0 No effect. Interrupt Disabled 0 1 Interrupt Enabled 1 ISER1 NVIC_ISER1 IRQ0 ~ IRQ111 Set-enable Control Register 0x4 -1 read-write n 0x0 0x0 SETENA Interrupt Set Enable Bit The NVIC_ISER0-NVIC_ISER1 registers enable interrupts, and show which interrupts are enabled Write Operation: 0 32 read-write 0 No effect. Interrupt Disabled 0 1 Interrupt Enabled 1 ISER2 NVIC_ISER2 IRQ0 ~ IRQ111 Set-enable Control Register 0x8 -1 read-write n 0x0 0x0 SETENA Interrupt Set Enable Bit The NVIC_ISER0-NVIC_ISER2 registers enable interrupts, and show which interrupts are enabled Write Operation: 0 32 read-write 0 No effect. Interrupt Disabled 0 1 Interrupt Enabled 1 ISER3 NVIC_ISER3 IRQ0 ~ IRQ111 Set-enable Control Register 0xC -1 read-write n 0x0 0x0 SETENA Interrupt Set Enable Bit The NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled Write Operation: 0 32 read-write 0 No effect. Interrupt Disabled 0 1 Interrupt Enabled 1 ISPR0 NVIC_ISPR0 IRQ0 ~ IRQ111 Set-pending Control Register 0x100 -1 read-write n 0x0 0x0 SETPEND Interrupt Set-pending The NVIC_ISPR0-NVIC_ISPR0 registers force interrupts into the pending state, and show which interrupts are pending Write Operation: 0 32 read-write 0 No effect. Interrupt is not pending 0 1 Changes interrupt state to pending. Interrupt is pending 1 ISPR1 NVIC_ISPR1 IRQ0 ~ IRQ111 Set-pending Control Register 0x104 -1 read-write n 0x0 0x0 SETPEND Interrupt Set-pending The NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state, and show which interrupts are pending Write Operation: 0 32 read-write 0 No effect. Interrupt is not pending 0 1 Changes interrupt state to pending. Interrupt is pending 1 ISPR2 NVIC_ISPR2 IRQ0 ~ IRQ111 Set-pending Control Register 0x108 -1 read-write n 0x0 0x0 SETPEND Interrupt Set-pending The NVIC_ISPR0-NVIC_ISPR2 registers force interrupts into the pending state, and show which interrupts are pending Write Operation: 0 32 read-write 0 No effect. Interrupt is not pending 0 1 Changes interrupt state to pending. Interrupt is pending 1 ISPR3 NVIC_ISPR3 IRQ0 ~ IRQ111 Set-pending Control Register 0x10C -1 read-write n 0x0 0x0 SETPEND Interrupt Set-pending The NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending Write Operation: 0 32 read-write 0 No effect. Interrupt is not pending 0 1 Changes interrupt state to pending. Interrupt is pending 1 STIR STIR Software Trigger Interrupt Registers 0xE00 -1 read-write n 0x0 0x0 INTID Interrupt ID Write to the STIR To Generate An Interrupt from Software When the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR Interrupt ID of the interrupt to trigger, in the range 0-63. For example, a value of 0x03 specifies interrupt IRQ3. 0 9 read-write PDMA PDMA Register Map PDMA 0x0 0x0 0x60 registers n 0x100 0x18 registers n 0x400 0x44 registers n 0x460 0x4 registers n 0x480 0x8 registers n ABTSTS PDMA_ABTSTS PDMA Channel Read/Write Target Abort Flag Register 0x420 -1 read-write n 0x0 0x0 ABTIF0 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request. 0 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF1 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request. 1 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF2 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request. 2 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF3 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request. 3 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF4 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request. 4 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF5 PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request. 5 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ALIGN PDMA_ALIGN PDMA Transfer Alignment Status Register 0x428 -1 read-write n 0x0 0x0 ALIGN0 Transfer Alignment Flag Note: Source address and destination address should be alignment. 0 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN1 Transfer Alignment Flag Note: Source address and destination address should be alignment. 1 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN2 Transfer Alignment Flag Note: Source address and destination address should be alignment. 2 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN3 Transfer Alignment Flag Note: Source address and destination address should be alignment. 3 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN4 Transfer Alignment Flag Note: Source address and destination address should be alignment. 4 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 ALIGN5 Transfer Alignment Flag Note: Source address and destination address should be alignment. 5 1 read-write 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 CHCTL PDMA_CHCTL PDMA Channel Control Register 0x400 -1 read-write n 0x0 0x0 CHEN0 PDMA Channel Enable Bits Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 0 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN1 PDMA Channel Enable Bits Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 1 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN2 PDMA Channel Enable Bits Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 2 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN3 PDMA Channel Enable Bits Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 3 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN4 PDMA Channel Enable Bits Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 4 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN5 PDMA Channel Enable Bits Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 5 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHRST PDMA_CHRST PDMA Channel Reset Register 0x460 -1 read-write n 0x0 0x0 CHnRST Channel n Reset 0 6 read-write 0 corresponding channel n is not reset 0 1 corresponding channel n is reset 1 CURSCAT0 PDMA_CURSCAT0 Current Scatter-gather Descriptor Table Address of PDMA Channel n 0x100 -1 read-only n 0x0 0x0 CURADDR PDMA Current Description Address (Read Only) This field indicates a 32-bit current external description address of PDMA controller. Note: This field is read only and used for Scatter-Gather mode only to indicate the current external description address. 0 32 read-only CURSCAT1 PDMA_CURSCAT1 Current Scatter-gather Descriptor Table Address of PDMA Channel n 0x104 -1 read-write n 0x0 0x0 CURSCAT2 PDMA_CURSCAT2 Current Scatter-gather Descriptor Table Address of PDMA Channel n 0x108 -1 read-write n 0x0 0x0 CURSCAT3 PDMA_CURSCAT3 Current Scatter-gather Descriptor Table Address of PDMA Channel n 0x10C -1 read-write n 0x0 0x0 CURSCAT4 PDMA_CURSCAT4 Current Scatter-gather Descriptor Table Address of PDMA Channel n 0x110 -1 read-write n 0x0 0x0 CURSCAT5 PDMA_CURSCAT5 Current Scatter-gather Descriptor Table Address of PDMA Channel n 0x114 -1 read-write n 0x0 0x0 DSCT0_CTL PDMA_DSCT0_CTL Descriptor Table Control Register of PDMA Channel n 0x0 -1 read-write n 0x0 0x0 BURSIZE Burst Size Note: This field is only useful in burst transfer type. 4 3 read-write 0 128 Transfers #000 1 64 Transfers #001 2 32 Transfers #010 3 16 Transfers #011 4 8 Transfers #100 5 4 Transfers #101 6 2 Transfers #110 7 1 Transfers #111 DAINC Destination Address Increment This field is used to set the destination address increment size. Note: The fixed address function is not supported in memory to memory transfer type. 10 2 read-write 3 No increment (fixed address) #11 OPMODE PDMA Operation Mode Selection Note: Before filling new transfer task in the Descriptor Table, user must check the PDMA_INTSTS[1] to make sure the current task is complete. 0 2 read-write 0 Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically #00 1 Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[1] will be asserted #01 2 Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register PDMA controller will ignore this task, then load the next task to execute #10 3 Reserved. #11 SAINC Source Address Increment This field is used to set the source address increment size. Note: The fixed address function is not supported in memory to memory transfer type. 8 2 read-write 3 No increment (fixed address) #11 TBINTDIS Table Interrupt Disable Bit This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task. Note: This function only for scatter-gather mode. 7 1 read-write 0 Table interrupt Enabled #0 1 Table interrupt Disabled #1 TXCNT Transfer Count The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 65536, every transfer may be byte, half-word or word that is dependent on TXWIDTH field. Note: When PDMA finishes each transfer data, this field will be decrease immediately. 16 16 read-write TXTYPE Transfer Type 2 1 read-write 0 Burst transfer type #0 1 Single transfer type #1 TXWIDTH Transfer Width Selection This field is used for transfer width. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection 12 2 read-write 0 One byte (8 bit) is transferred for every operation #00 1 One half-word (16 bit) is transferred for every operation #01 2 One word (32-bit) is transferred for every operation #10 3 Reserved. #11 DSCT0_DA PDMA_DSCT0_DA Destination Address Register of PDMA Channel n 0x8 -1 read-write n 0x0 0x0 DA PDMA Transfer Destination Address This field indicates a 32-bit destination address of PDMA controller. 0 32 read-write DSCT0_NEXT PDMA_DSCT0_NEXT Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n 0xC -1 read-write n 0x0 0x0 EXENEXT PDMA Execution Next Descriptor Table Offset This field indicates the offset of next descriptor table address of current execution descriptor table in system memory. Note: write operation is useless in this field. 16 16 read-write NEXT PDMA Next Descriptor Table Offset This field indicates the offset of the next descriptor table address in system memory. Write Operation: If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100. Read Operation: When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory. When operating in scatter-gather mode, the last two bits NEXT[1:0] will become scatter-gather mode control indicator as below. Note 1: The descriptor table address must be word boundary. Note 2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. 0 16 read-write 0 Idle mode 0 1 operating in the basic mode (final scatter-gather table) 1 2 loading scatter-gather table from SRAM 2 3 operating in the scatter-gather mode 3 DSCT0_SA PDMA_DSCT0_SA Source Address Register of PDMA Channel n 0x4 -1 read-write n 0x0 0x0 SA PDMA Transfer Source Address This field indicates a 32-bit source address of PDMA controller. 0 32 read-write DSCT1_CTL PDMA_DSCT1_CTL Descriptor Table Control Register of PDMA Channel n 0x10 -1 read-write n 0x0 0x0 DSCT1_DA PDMA_DSCT1_DA Destination Address Register of PDMA Channel n 0x18 -1 read-write n 0x0 0x0 DSCT1_NEXT PDMA_DSCT1_NEXT Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n 0x1C -1 read-write n 0x0 0x0 DSCT1_SA PDMA_DSCT1_SA Source Address Register of PDMA Channel n 0x14 -1 read-write n 0x0 0x0 DSCT2_CTL PDMA_DSCT2_CTL Descriptor Table Control Register of PDMA Channel n 0x20 -1 read-write n 0x0 0x0 DSCT2_DA PDMA_DSCT2_DA Destination Address Register of PDMA Channel n 0x28 -1 read-write n 0x0 0x0 DSCT2_NEXT PDMA_DSCT2_NEXT Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n 0x2C -1 read-write n 0x0 0x0 DSCT2_SA PDMA_DSCT2_SA Source Address Register of PDMA Channel n 0x24 -1 read-write n 0x0 0x0 DSCT3_CTL PDMA_DSCT3_CTL Descriptor Table Control Register of PDMA Channel n 0x30 -1 read-write n 0x0 0x0 DSCT3_DA PDMA_DSCT3_DA Destination Address Register of PDMA Channel n 0x38 -1 read-write n 0x0 0x0 DSCT3_NEXT PDMA_DSCT3_NEXT Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n 0x3C -1 read-write n 0x0 0x0 DSCT3_SA PDMA_DSCT3_SA Source Address Register of PDMA Channel n 0x34 -1 read-write n 0x0 0x0 DSCT4_CTL PDMA_DSCT4_CTL Descriptor Table Control Register of PDMA Channel n 0x40 -1 read-write n 0x0 0x0 DSCT4_DA PDMA_DSCT4_DA Destination Address Register of PDMA Channel n 0x48 -1 read-write n 0x0 0x0 DSCT4_NEXT PDMA_DSCT4_NEXT Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n 0x4C -1 read-write n 0x0 0x0 DSCT4_SA PDMA_DSCT4_SA Source Address Register of PDMA Channel n 0x44 -1 read-write n 0x0 0x0 DSCT5_CTL PDMA_DSCT5_CTL Descriptor Table Control Register of PDMA Channel n 0x50 -1 read-write n 0x0 0x0 DSCT5_DA PDMA_DSCT5_DA Destination Address Register of PDMA Channel n 0x58 -1 read-write n 0x0 0x0 DSCT5_NEXT PDMA_DSCT5_NEXT Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n 0x5C -1 read-write n 0x0 0x0 DSCT5_SA PDMA_DSCT5_SA Source Address Register of PDMA Channel n 0x54 -1 read-write n 0x0 0x0 INTEN PDMA_INTEN PDMA Interrupt Enable Register 0x418 -1 read-write n 0x0 0x0 INTEN0 PDMA Interrupt Enable Bits This field is used to enable PDMA channel[n] interrupt. 0 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled.Note: The interrupt flag is time-out, abort, transfer done and align #1 INTEN1 PDMA Interrupt Enable Bits This field is used to enable PDMA channel[n] interrupt. 1 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled.Note: The interrupt flag is time-out, abort, transfer done and align #1 INTEN2 PDMA Interrupt Enable Bits This field is used to enable PDMA channel[n] interrupt. 2 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled.Note: The interrupt flag is time-out, abort, transfer done and align #1 INTEN3 PDMA Interrupt Enable Bits This field is used to enable PDMA channel[n] interrupt. 3 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled.Note: The interrupt flag is time-out, abort, transfer done and align #1 INTEN4 PDMA Interrupt Enable Bits This field is used to enable PDMA channel[n] interrupt. 4 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled.Note: The interrupt flag is time-out, abort, transfer done and align #1 INTEN5 PDMA Interrupt Enable Bits This field is used to enable PDMA channel[n] interrupt. 5 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled.Note: The interrupt flag is time-out, abort, transfer done and align #1 INTSTS PDMA_INTSTS PDMA Interrupt Status Register 0x41C -1 read-write n 0x0 0x0 ABTIF PDMA Read/Write Target Abort Interrupt Flag (Read Only) This bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error. 0 1 read-only 0 No AHB bus ERROR response received #0 1 AHB bus ERROR response received #1 ALIGNF Transfer Alignment Interrupt Flag (Read Only) 2 1 read-only 0 PDMA channel source address and destination address both follow transfer width setting #0 1 PDMA channel source address or destination address is not follow transfer width setting #1 REQTOF0 Request Time-out Flag for Channel 0 This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits. Note: Please disable time-out function before clearing this bit. 8 1 read-write 0 No request time-out #0 1 Peripheral request time-out #1 REQTOF1 Request Time-out Flag for Channel 1 This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits. Note: Please disable time-out function before clearing this bit. 9 1 read-write 0 No request time-out #0 1 Peripheral request time-out #1 TDIF Transfer Done Interrupt Flag (Read Only) This bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer. 1 1 read-only 0 Not finished yet #0 1 PDMA channel has finished transmission #1 PAUSE PDMA_PAUSE PDMA Transfer Pause Control Register 0x404 -1 write-only n 0x0 0x0 PAUSE0 PDMA Channel n Transfer Pause Control (Write Only) 0 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE1 PDMA Channel n Transfer Pause Control (Write Only) 1 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE2 PDMA Channel n Transfer Pause Control (Write Only) 2 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE3 PDMA Channel n Transfer Pause Control (Write Only) 3 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE4 PDMA Channel n Transfer Pause Control (Write Only) 4 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE5 PDMA Channel n Transfer Pause Control (Write Only) 5 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PRICLR PDMA_PRICLR PDMA Fixed Priority Clear Register 0x414 -1 write-only n 0x0 0x0 FPRICLR0 PDMA Fixed Priority Clear Bits (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority. 0 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR1 PDMA Fixed Priority Clear Bits (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority. 1 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR2 PDMA Fixed Priority Clear Bits (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority. 2 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR3 PDMA Fixed Priority Clear Bits (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority. 3 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR4 PDMA Fixed Priority Clear Bits (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority. 4 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR5 PDMA Fixed Priority Clear Bits (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority. 5 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 PRISET PDMA_PRISET PDMA Fixed Priority Setting Register 0x410 -1 read-write n 0x0 0x0 FPRISET0 PDMA Fixed Priority Setting Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field is only set to fixed priority to clear fixed priority use PDMA_PRICLR register. 0 1 read-write 0 No effect. Corresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel. Corresponding PDMA channel is fixed priority #1 FPRISET1 PDMA Fixed Priority Setting Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field is only set to fixed priority to clear fixed priority use PDMA_PRICLR register. 1 1 read-write 0 No effect. Corresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel. Corresponding PDMA channel is fixed priority #1 FPRISET2 PDMA Fixed Priority Setting Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field is only set to fixed priority to clear fixed priority use PDMA_PRICLR register. 2 1 read-write 0 No effect. Corresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel. Corresponding PDMA channel is fixed priority #1 FPRISET3 PDMA Fixed Priority Setting Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field is only set to fixed priority to clear fixed priority use PDMA_PRICLR register. 3 1 read-write 0 No effect. Corresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel. Corresponding PDMA channel is fixed priority #1 FPRISET4 PDMA Fixed Priority Setting Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field is only set to fixed priority to clear fixed priority use PDMA_PRICLR register. 4 1 read-write 0 No effect. Corresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel. Corresponding PDMA channel is fixed priority #1 FPRISET5 PDMA Fixed Priority Setting Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field is only set to fixed priority to clear fixed priority use PDMA_PRICLR register. 5 1 read-write 0 No effect. Corresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel. Corresponding PDMA channel is fixed priority #1 REQSEL0_3 PDMA_REQSEL0_3 PDMA Request Source Select Register 0 0x480 -1 read-write n 0x0 0x0 REQSRC0 Channel 0 Request Source Selection This filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0. Note 1: A peripheral cannot be assigned to two channels at the same time. Note 2: This field is useless when transfer between memory and memory. 0 6 read-write 0 Disable PDMA peripheral request 0 1 Channel connects to UART0_TX 1 10 Channel connects to UART4_RX 10 11 Channel connects to UART5_TX 11 12 Channel connects to UART5_RX 12 13 Channel connects to SPI0_TX 13 14 Channel connects to SPI0_RX 14 15 Channel connects to SPI1_TX 15 16 Channel connects to SPI1_RX 16 17 Channel connects to EPWM0_P1_RX 17 18 Channel connects to EPWM0_P2_RX 18 19 Channel connects to EPWM0_P3_RX 19 2 Channel connects to UART0_RX 2 20 Channel connects to EPWM1_P1_RX 20 21 Channel connects to EPWM1_P2_RX 21 22 Channel connects to EPWM1_P3_RX 22 23 Channel connects to I2C0_TX 23 24 Channel connects to I2C0_RX 24 25 Channel connects to I2C1_TX 25 26 Channel connects to I2C1_RX 26 27 Channel connects to TMR0 27 28 Channel connects to TMR1 28 29 Channel connects to TMR2 29 3 Channel connects to UART1_TX 3 30 Channel connects to TMR3 30 31 Channel connects to EADC0_RX 31 32 Channel connects to DAC0_TX 32 33 Channel connects to EPWM0_CH0_TX 33 34 Channel connects to EPWM0_CH1_TX 34 35 Channel connects to EPWM0_CH2_TX 35 36 Channel connects to EPWM0_CH3_TX 36 37 Channel connects to EPWM0_CH4_TX 37 38 Channel connects to EPWM0_CH5_TX 38 39 Channel connects to EPWM1_CH0_TX 39 4 Channel connects to UART1_RX 4 40 Channel connects to EPWM1_CH1_TX 40 41 Channel connects to EPWM1_CH2_TX 41 42 Channel connects to EPWM1_CH3_TX 42 43 Channel connects to EPWM1_CH4_TX 43 44 Channel connects to EPWM1_CH5_TX 44 45 Channel connects to ACMP0 45 46 Channel connects to ACMP1 46 47 Reserved. 47 48 Reserved. 48 49 Reserved. 49 5 Channel connects to UART2_TX 5 50 Reserved. 50 6 Channel connects to UART2_RX 6 7 Channel connects to UART3_TX 7 8 Channel connects to UART3_RX 8 9 Channel connects to UART4_TX 9 REQSRC1 Channel 1 Request Source Selection This filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 8 6 read-write REQSRC2 Channel 2 Request Source Selection This filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 16 6 read-write REQSRC3 Channel 3 Request Source Selection This filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 24 6 read-write REQSEL4_5 PDMA_REQSEL4_5 PDMA Request Source Select Register 1 0x484 -1 read-write n 0x0 0x0 REQSRC4 Channel 4 Request Source Selection This filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 0 6 read-write REQSRC5 Channel 5 Request Source Selection This filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 8 6 read-write SCATBA PDMA_SCATBA PDMA Scatter-gather Descriptor Table Base Address Register 0x43C -1 read-write n 0x0 0x0 SCATBA PDMA Scatter-gather Descriptor Table Address In Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is Note: Only useful in Scatter-Gather mode. 16 16 read-write SWREQ PDMA_SWREQ PDMA Software Request Register 0x408 -1 write-only n 0x0 0x0 SWREQ0 PDMA Software Request (Write Only) Set this bit to 1 to generate a software request to PDMA [n]. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored. 0 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ1 PDMA Software Request (Write Only) Set this bit to 1 to generate a software request to PDMA [n]. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored. 1 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ2 PDMA Software Request (Write Only) Set this bit to 1 to generate a software request to PDMA [n]. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored. 2 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ3 PDMA Software Request (Write Only) Set this bit to 1 to generate a software request to PDMA [n]. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored. 3 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ4 PDMA Software Request (Write Only) Set this bit to 1 to generate a software request to PDMA [n]. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored. 4 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ5 PDMA Software Request (Write Only) Set this bit to 1 to generate a software request to PDMA [n]. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored. 5 1 write-only 0 No effect #0 1 Generate a software request #1 TACTSTS PDMA_TACTSTS PDMA Transfer Active Flag Register 0x42C -1 read-only n 0x0 0x0 TXACTF0 Transfer on Active Flag (Read Only) This bit indicates which PDMA channel is in active. 0 1 read-only 0 PDMA channel is finished #0 1 PDMA channel is active #1 TXACTF1 Transfer on Active Flag (Read Only) This bit indicates which PDMA channel is in active. 1 1 read-only 0 PDMA channel is finished #0 1 PDMA channel is active #1 TXACTF2 Transfer on Active Flag (Read Only) This bit indicates which PDMA channel is in active. 2 1 read-only 0 PDMA channel is finished #0 1 PDMA channel is active #1 TXACTF3 Transfer on Active Flag (Read Only) This bit indicates which PDMA channel is in active. 3 1 read-only 0 PDMA channel is finished #0 1 PDMA channel is active #1 TXACTF4 Transfer on Active Flag (Read Only) This bit indicates which PDMA channel is in active. 4 1 read-only 0 PDMA channel is finished #0 1 PDMA channel is active #1 TXACTF5 Transfer on Active Flag (Read Only) This bit indicates which PDMA channel is in active. 5 1 read-only 0 PDMA channel is finished #0 1 PDMA channel is active #1 TDSTS PDMA_TDSTS PDMA Channel Transfer Done Flag Register 0x424 -1 read-write n 0x0 0x0 TDIF0 Transfer Done Flag This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 0 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF1 Transfer Done Flag This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 1 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF2 Transfer Done Flag This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 2 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF3 Transfer Done Flag This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 3 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF4 Transfer Done Flag This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 4 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF5 Transfer Done Flag This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 5 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TOC0_1 PDMA_TOC0_1 PDMA Time-out Counter Ch1 and Ch0 Register 0x440 -1 read-write n 0x0 0x0 TOC0 Time-out Counter for Channel 0 This controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock. 0 16 read-write TOC1 Time-out Counter for Channel 1 This controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[6:4]) clock. 16 16 read-write TOUTEN PDMA_TOUTEN PDMA Time-out Enable Register 0x434 -1 read-write n 0x0 0x0 TOUTEN0 PDMA Time-out Enable Bits 0 1 read-write 0 PDMA Channel n time-out function Disabled #0 1 PDMA Channel n time-out function Enabled #1 TOUTEN1 PDMA Time-out Enable Bits 1 1 read-write 0 PDMA Channel n time-out function Disabled #0 1 PDMA Channel n time-out function Enabled #1 TOUTIEN PDMA_TOUTIEN PDMA Time-out Interrupt Enable Register 0x438 -1 read-write n 0x0 0x0 TOUTIEN0 PDMA Time-out Interrupt Enable Bits 0 1 read-write 0 PDMA Channel n time-out interrupt Disabled #0 1 PDMA Channel n time-out interrupt Enabled #1 TOUTIEN1 PDMA Time-out Interrupt Enable Bits 1 1 read-write 0 PDMA Channel n time-out interrupt Disabled #0 1 PDMA Channel n time-out interrupt Enabled #1 TOUTPSC PDMA_TOUTPSC PDMA Time-out Prescaler Register 0x430 -1 read-write n 0x0 0x0 TOUTPSC0 PDMA Channel 0 Time-out Clock Source Prescaler Bits 0 3 read-write 0 PDMA channel 0 time-out clock source is HCLK/28 #000 1 PDMA channel 0 time-out clock source is HCLK/29 #001 2 PDMA channel 0 time-out clock source is HCLK/210 #010 3 PDMA channel 0 time-out clock source is HCLK/211 #011 4 PDMA channel 0 time-out clock source is HCLK/212 #100 5 PDMA channel 0 time-out clock source is HCLK/213 #101 6 PDMA channel 0 time-out clock source is HCLK/214 #110 7 PDMA channel 0 time-out clock source is HCLK/215 #111 TOUTPSC1 PDMA Channel 1 Time-out Clock Source Prescaler Bits 4 3 read-write 0 PDMA channel 1 time-out clock source is HCLK/28 #000 1 PDMA channel 1 time-out clock source is HCLK/29 #001 2 PDMA channel 1 time-out clock source is HCLK/210 #010 3 PDMA channel 1 time-out clock source is HCLK/211 #011 4 PDMA channel 1 time-out clock source is HCLK/212 #100 5 PDMA channel 1 time-out clock source is HCLK/213 #101 6 PDMA channel 1 time-out clock source is HCLK/214 #110 7 PDMA channel 1 time-out clock source is HCLK/215 #111 TRGSTS PDMA_TRGSTS PDMA Channel Request Status Register 0x40C -1 read-only n 0x0 0x0 REQSTS0 PDMA Channel Request Status (Read Only) This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 0 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS1 PDMA Channel Request Status (Read Only) This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 1 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS2 PDMA Channel Request Status (Read Only) This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 2 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS3 PDMA Channel Request Status (Read Only) This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 3 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS4 PDMA Channel Request Status (Read Only) This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 4 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS5 PDMA Channel Request Status (Read Only) This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 5 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 PRNG PRNG Register Map PRNG 0x0 0x0 0x30 registers n CTL PRNG_CTL PRNG Control Register 0x8 -1 read-write n 0x0 0x0 BUSY PRNG Busy (Read Only) 8 1 read-only 0 PRNG engine is idle #0 1 PRNG engine is generating PRNG_KEYx #1 KEYSZ PRNG Generate Key Size 2 2 read-write 0 64 bits #00 1 128 bits #01 2 192 bits #10 3 256 bits #11 SEEDRLD Reload New Seed for PRNG Engine 1 1 read-write 0 Generating key based on the current seed #0 1 Reload new seed #1 START Start PRNG Engine 0 1 read-write 0 Stop PRNG engine #0 1 Generate a new key and store the new key to the register PRNG_KEYx, which will be cleared when the new key is generated #1 INTEN PRNG_INTEN PRNG Interrupt Enable Control Register 0x0 -1 read-write n 0x0 0x0 PRNGIEN PRNG Interrupt Enable Bit 16 1 read-write 0 PRNG interrupt Disabled #0 1 PRNG interrupt Enabled #1 INTSTS PRNG_INTSTS PRNG Interrupt Flag 0x4 -1 read-write n 0x0 0x0 PRNGIF PRNG Finish Interrupt Flag Note: This bit is cleared by writing 1, and it has no effect by writing 0. 16 1 read-write 0 No PRNG interrupt #0 1 PRNG key generation done interrupt #1 KEY0 PRNG_KEY0 PRNG Generated Key0 0x10 -1 read-only n 0x0 0x0 KEY Store PRNG Generated Key (Read Only) The bits store the key that is generated by PRNG. 0 32 read-only KEY1 PRNG_KEY1 PRNG Generated Key1 0x14 -1 read-write n 0x0 0x0 KEY2 PRNG_KEY2 PRNG Generated Key2 0x18 -1 read-write n 0x0 0x0 KEY3 PRNG_KEY3 PRNG Generated Key3 0x1C -1 read-write n 0x0 0x0 KEY4 PRNG_KEY4 PRNG Generated Key4 0x20 -1 read-write n 0x0 0x0 KEY5 PRNG_KEY5 PRNG Generated Key5 0x24 -1 read-write n 0x0 0x0 KEY6 PRNG_KEY6 PRNG Generated Key6 0x28 -1 read-write n 0x0 0x0 KEY7 PRNG_KEY7 PRNG Generated Key7 0x2C -1 read-write n 0x0 0x0 SEED PRNG_SEED Seed for PRNG 0xC -1 write-only n 0x0 0x0 SEED Seed for PRNG (Write Only) The bits store the seed for PRNG engine. 0 32 write-only RTC RTC Register Map RTC 0x0 0x0 0x4 registers n 0x100 0x4 registers n 0x110 0x4 registers n 0x8 0x34 registers n CAL RTC_CAL RTC Calendar Loading Register 0x10 -1 read-write n 0x0 0x0 DAY 1-Day Calendar Digit (0~9) 0 4 read-write MON 1-Month Calendar Digit (0~9) 8 4 read-write TENDAY 10-Day Calendar Digit (0~3) 4 2 read-write TENMON 10-Month Calendar Digit (0~1) 12 1 read-write TENYEAR 10-Year Calendar Digit (0~9) 20 4 read-write YEAR 1-Year Calendar Digit (0~9) 16 4 read-write CALM RTC_CALM RTC Calendar Alarm Register 0x20 -1 read-write n 0x0 0x0 DAY 1-Day Calendar Digit of Alarm Setting (0~9) 0 4 read-write MON 1-Month Calendar Digit of Alarm Setting (0~9) 8 4 read-write TENDAY 10-Day Calendar Digit of Alarm Setting (0~3) 4 2 read-write TENMON 10-Month Calendar Digit of Alarm Setting (0~1) 12 1 read-write TENYEAR 10-Year Calendar Digit of Alarm Setting (0~9) 20 4 read-write YEAR 1-Year Calendar Digit of Alarm Setting (0~9) 16 4 read-write CAMSK RTC_CAMSK RTC Calendar Alarm Mask Register 0x38 -1 read-write n 0x0 0x0 MDAY Mask 1-Day Calendar Digit of Alarm Setting (0~9) 0 1 read-write MMON Mask 1-Month Calendar Digit of Alarm Setting (0~9) 2 1 read-write MTENDAY Mask 10-Day Calendar Digit of Alarm Setting (0~3) 1 1 read-write MTENMON Mask 10-Month Calendar Digit of Alarm Setting (0~1) 3 1 read-write MTENYEAR Mask 10-Year Calendar Digit of Alarm Setting (0~9) 5 1 read-write MYEAR Mask 1-Year Calendar Digit of Alarm Setting (0~9) 4 1 read-write CLKFMT RTC_CLKFMT RTC Time Scale Selection Register 0x14 -1 read-write n 0x0 0x0 DYNCOMPEN Dynamic Compensation Enable Bit 16 1 read-write 0 Dynamic Compensation Disabled #0 1 Dynamic Compensation Enabled #1 _24HEN 24-hour / 12-hour Time Scale Selection Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale 0 1 read-write 0 12-hour time scale with AM and PM indication selected #0 1 24-hour time scale selected #1 DSTCTL RTC_DSTCTL RTC Daylight Saving Time Control Register 0x110 -1 read-write n 0x0 0x0 ADDHR Add 1 Hour 0 1 read-write 0 No effect #0 1 Indicates RTC hour digit has been added one hour for summer time change #1 DSBAK Daylight Saving Back 2 1 read-write 0 Daylight Saving Change is not performed #0 1 Daylight Saving Change is performed #1 SUBHR Subtract 1 Hour 1 1 read-write 0 No effect #0 1 Indicates RTC hour digit has been subtracted one hour for winter time change #1 FREQADJ RTC_FREQADJ RTC Frequency Compensation Register 0x8 -1 read-write n 0x0 0x0 FCRBUSY Frequency Compensation Register Write Operation Busy (Read Only) Note: This bit is only used when DYNCOMPEN(RTC_CLKFMT[16]) is enabled. 31 1 read-only 0 The new register write operation is acceptable #0 1 The last write operation is in progress and new register write operation prohibited #1 FRACTION Fraction Part Note: Digit in FCR must be expressed as hexadecimal number. 0 6 read-write INTEGER Integer Part 8 5 read-write 0 Integer part of detected value is 32752 #00000 1 Integer part of detected value is 32753 #00001 2 Integer part of detected value is 32754 #00010 3 Integer part of detected value is 32755 #00011 4 Integer part of detected value is 32756 #00100 5 Integer part of detected value is 32757 #00101 6 Integer part of detected value is 32758 #00110 7 Integer part of detected value is 32759 #00111 8 Integer part of detected value is 32760 #01000 9 Integer part of detected value is 32761 #01001 10 Integer part of detected value is 32762 #01010 11 Integer part of detected value is 32763 #01011 12 Integer part of detected value is 32764 #01100 13 Integer part of detected value is 32765 #01101 14 Integer part of detected value is 32766 #01110 15 Integer part of detected value is 32767 #01111 16 Integer part of detected value is 32768 #10000 17 Integer part of detected value is 32769 #10001 18 Integer part of detected value is 32770 #10010 19 Integer part of detected value is 32771 #10011 20 Integer part of detected value is 32772 #10100 21 Integer part of detected value is 32773 #10101 22 Integer part of detected value is 32774 #10110 23 Integer part of detected value is 32775 #10111 24 Integer part of detected value is 32776 #11000 25 Integer part of detected value is 32777 #11001 26 Integer part of detected value is 32778 #11010 27 Integer part of detected value is 32779 #11011 28 Integer part of detected value is 32780 #11100 29 Integer part of detected value is 32781 #11101 30 Integer part of detected value is 32782 #11110 31 Integer part of detected value is 32783 #11111 INIT RTC_INIT RTC Initiation Register 0x0 -1 read-write n 0x0 0x0 ACTIVE RTC Active Status (Read Only) 0 1 read-only 0 RTC is at reset state #0 1 RTC is at normal active state #1 INIT RTC Initiation (Write Only) When RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leave reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. The INIT is a write-only field and read value will be always 0. 1 31 write-only INTEN RTC_INTEN RTC Interrupt Enable Register 0x28 -1 read-write n 0x0 0x0 ALMIEN Alarm Interrupt Enable Bit Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated. 0 1 read-write 0 RTC Alarm interrupt Disabled #0 1 RTC Alarm interrupt Enabled #1 TICKIEN Time Tick Interrupt Enable Bit Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated. 1 1 read-write 0 RTC Time Tick interrupt Disabled #0 1 RTC Time Tick interrupt Enabled #1 INTSTS RTC_INTSTS RTC Interrupt Status Register 0x2C -1 read-write n 0x0 0x0 ALMIF RTC Alarm Interrupt Flag Note: Write 1 to clear this bit. 0 1 read-write 0 Alarm condition is not matched #0 1 Alarm condition is matched #1 TICKIF RTC Time Tick Interrupt Flag Note: Write 1 to clear this bit. 1 1 read-write 0 Tick condition did not occur #0 1 Tick condition occurred #1 LEAPYEAR RTC_LEAPYEAR RTC Leap Year Indicator Register 0x24 -1 read-only n 0x0 0x0 LEAPYEAR Leap Year Indication (Read Only) 0 1 read-only 0 This year is not a leap year #0 1 This year is leap year #1 LXTCTL RTC_LXTCTL RTC 32.768 kHz Oscillator Control Register 0x100 -1 read-write n 0x0 0x0 GAIN Oscillator Gain Option User can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption. 1 3 read-write 0 L0 mode (ESR=35K CL =25pF) #000 1 L1 mode (ESR=35K CL =25pF) #001 2 L2 mode (ESR=35K CL =25pF) #010 3 L3 mode (ESR=70K CL =25pF) #011 4 L4 mode (ESR=70K CL =25pF) #100 5 L5 mode (ESR=70K CL =25pF) #101 6 L6 mode (ESR=90K CL =25pF) #110 7 L7 mode (ESR=90K CL =25pF) #111 RTCCKSEL RTC Clock Source Selection 7 1 read-write 0 Clock source from 32 kHz crystal or external XI_32K input #0 1 Clock source from internal low speed RC oscillator (LIRC38K) #1 TALM RTC_TALM RTC Time Alarm Register 0x1C -1 read-write n 0x0 0x0 HR 1-Hour Time Digit of Alarm Setting (0~9) 16 4 read-write MIN 1-Min Time Digit of Alarm Setting (0~9) 8 4 read-write SEC 1-Sec Time Digit of Alarm Setting (0~9) 0 4 read-write TENHR 10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) 20 2 read-write TENMIN 10-Min Time Digit of Alarm Setting (0~5) 12 3 read-write TENSEC 10-Sec Time Digit of Alarm Setting (0~5) 4 3 read-write TAMSK RTC_TAMSK RTC Time Alarm Mask Register 0x34 -1 read-write n 0x0 0x0 MHR Mask 1-Hour Time Digit of Alarm Setting (0~9) 4 1 read-write MMIN Mask 1-Min Time Digit of Alarm Setting (0~9) 2 1 read-write MSEC Mask 1-Sec Time Digit of Alarm Setting (0~9) 0 1 read-write MTENHR Mask 10-Hour Time Digit of Alarm Setting (0~2) 5 1 read-write MTENMIN Mask 10-Min Time Digit of Alarm Setting (0~5) 3 1 read-write MTENSEC Mask 10-Sec Time Digit of Alarm Setting (0~5) 1 1 read-write TICK RTC_TICK RTC Time Tick Register 0x30 -1 read-write n 0x0 0x0 TICK Time Tick Register These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. 0 3 read-write 0 Time tick is 1 second #000 1 Time tick is 1/2 second #001 2 Time tick is 1/4 second #010 3 Time tick is 1/8 second #011 4 Time tick is 1/16 second #100 5 Time tick is 1/32 second #101 6 Time tick is 1/64 second #110 7 Time tick is 1/128 second #111 TIME RTC_TIME RTC Time Loading Register 0xC -1 read-write n 0x0 0x0 HR 1-Hour Time Digit (0~9) 16 4 read-write MIN 1-Min Time Digit (0~9) 8 4 read-write SEC 1-Sec Time Digit (0~9) 0 4 read-write TENHR 10-Hour Time Digit (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) 20 2 read-write TENMIN 10-Min Time Digit (0~5) 12 3 read-write TENSEC 10-Sec Time Digit (0~5) 4 3 read-write WEEKDAY RTC_WEEKDAY RTC Day of the Week Register 0x18 -1 read-write n 0x0 0x0 WEEKDAY Day of the Week Register 0 3 read-write 0 Sunday #000 1 Monday #001 2 Tuesday #010 3 Wednesday #011 4 Thursday #100 5 Friday #101 6 Saturday #110 7 Reserved. #111 SCS SYST_SCR Register Map SYST_SCR 0x0 0x10 0xC registers n 0xD04 0x4 registers n 0xD0C 0x8 registers n 0xD18 0xC registers n AIRCR AIRCR Application Interrupt and Reset Control Register 0xD0C -1 read-write n 0x0 0x0 ENDIANNESS Data Endianness 15 1 read-write 0 Little-endian #0 1 Big-endian #1 PRIGROUP Interrupt Priority Grouping This field determines the Split Of Group priority from subpriority, 8 3 read-write SYSRESETREQ System Reset Request Writing This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested This bit is write only and self-cleared as part of the reset sequence. 2 1 read-write VECTCLRACTIVE Exception Active Status Clear Bit Setting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions This bit is write only and can only be written when the core is halted. Note: It is the debugger's responsibility to re-initialize the stack. 1 1 read-write VECTORKEY Register Access Key When writing this register, this field should be 0x05FA, otherwise the write action will be unpredictable. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status. 16 16 read-write VECTRESET Reserved. 0 1 read-write ICSR ICSR Interrupt Control and State Register 0xD04 -1 read-write n 0x0 0x0 ISRPENDING Interrupt Pending Flag, Excluding NMI and Faults (Read Only) 22 1 read-only 0 Interrupt not pending #0 1 Interrupt pending #1 ISRPREEMPT Interrupt Preempt Bit (Read Only) If set, a pending exception will be serviced on exit from the debug halt state. 23 1 read-only NMIPENDSET NMI Set-pending Bit Write Operation: Note: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 31 1 read-write 0 No effect. NMI exception is not pending #0 1 Change NMI exception state to pending. NMI exception is pending #1 PENDSTRTC_CAL SysTick Exception Clear-pending Bit Write Operation: Note: This is a write only bit. To clear the PENDST bit, you must 'write 0 to PENDSTSET and write 1 to PENDSTRTC_CAL' at the same time. 25 1 read-write 0 No effect #0 1 Remove the pending state from the SysTick exception #1 PENDSTSET SysTick Exception Set-pending Bit Write Operation: 26 1 read-write 0 No effect. SysTick exception is not pending #0 1 Change SysTick exception state to pending. SysTick exception is pending #1 PENDSVRTC_CAL PendSV Clear-pending Bit Write Operation: Note: This is a write only bit. To clear the PENDSV bit, you must 'write 0 to PENDSVSET and write 1 to PENDSVRTC_CAL' at the same time. 27 1 read-write 0 No effect #0 1 Remove the pending state from the PendSV exception #1 PENDSVSET PendSV Set-pending Bit Write Operation: Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending. 28 1 read-write 0 No effect. PendSV exception is not pending #0 1 Change PendSV exception state to pending. PendSV exception is pending #1 RETTOBASE Preempted Active Exceptions Indicator Indicates whether there are Preempted Active Exceptions 11 1 read-write 0 There are preempted active exceptions to execute #0 1 There are no active exceptions, or the currently-executing exception is the only active exception #1 VECTACTIVE Number of the Current Active Exception 0 7 read-write 0 Thread mode 0 VECTPENDING Number of the Highest Pended Exception Indicates the Exception Number of the Highest Priority Pending Enabled Exception The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register. 12 6 read-write 0 No pending exceptions 0 SCR SCR System Control Register 0xD10 -1 read-write n 0x0 0x0 SEVONPEND Send Event on Pending When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. 4 1 read-write 0 Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded #0 1 Enabled events and all interrupts, including disabled interrupts, can wake up the processor #1 SLEEPDEEP Processor Deep Sleep and Sleep Mode Selection Control whether the Processor uses Sleep Or Deep Sleep as its Low Power Mode. 2 1 read-write 0 Sleep #0 1 Deep sleep #1 SLEEPONEXIT Sleep-on-exit Enable Control This bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 1 1 read-write 0 Do not sleep when returning to Thread mode #0 1 Enter sleep, or deep sleep, on return from an ISR to Thread mode #1 SHPR1 SHPR1 System Handler Priority Register 1 0xD18 -1 read-write n 0x0 0x0 PRI_4 Priority of system handler 4, MemManage 4 4 read-write PRI_5 Priority of system handler 5, BusFault 12 4 read-write PRI_6 Priority of system handler 6, UsageFault 20 4 read-write SHPR2 SHPR2 System Handler Priority Register 2 0xD1C -1 read-write n 0x0 0x0 PRI_11 Priority of System Handler 11 - SVCall '0' denotes the highest priority and '3' denotes the lowest priority. 28 4 read-write SHPR3 SHPR3 System Handler Priority Register 3 0xD20 -1 read-write n 0x0 0x0 PRI_14 Priority of System Handler 14 - PendSV '0' denotes the highest priority and '3' denotes the lowest priority. 20 4 read-write PRI_15 Priority of System Handler 15 - SysTick '0' denotes the highest priority and '3' denotes the lowest priority. 28 4 read-write SYST_CTRL SYST_CTRL SysTick Control and Status Register 0x10 -1 read-write n 0x0 0x0 CLKSRC System Tick Clock Source Selection 2 1 read-write 0 Clock source is the (optional) external reference clock #0 1 Core clock used for SysTick #1 COUNTFLAG System Tick Counter Flag Returns 1 if timer counted to 0 since last time this register was read. COUNTFLAG is set by a count transition from 1 to 0. COUNTFLAG is cleared on read or by a write to the Current Value register. 16 1 read-write ENABLE System Tick Counter Enabled 0 1 read-write 0 Counter Disabled #0 1 Counter will operate in a multi-shot manner #1 TICKINT System Tick Interrupt Enabled 1 1 read-write 0 Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended #1 SYST_LOAD SYST_LOAD SysTick Reload Value Register 0x14 -1 read-write n 0x0 0x0 RELOAD System Tick Reload Value Value to load into the Current Value register when the counter reaches 0. 0 24 read-write SYST_VAL SYST_VAL SysTick Current Value Register 0x18 -1 read-write n 0x0 0x0 CURRENT System Tick Current Value Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. 0 24 read-write SPI0 SPI Register Map SPI 0x0 0x0 0x1C registers n 0x20 0x4 registers n 0x30 0x4 registers n 0x60 0xC registers n SPIx_CLKDIV SPIx_CLKDIV SPI Clock Divider Register 0x4 -1 read-write n 0x0 0x0 DIVIDER Clock Divider The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation. where is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. Note 1: Not supported in I2S mode. Note 2: The time interval must be larger than or equal to 8 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register. 0 9 read-write SPIx_CTL SPIx_CTL SPI Control Register 0x0 -1 read-write n 0x0 0x0 CLKPOL Clock Polarity 3 1 read-write 0 SPI bus clock is idle low #0 1 SPI bus clock is idle high #1 DATDIR Data Port Direction Control This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer 20 1 read-write 0 SPI data is input direction #0 1 SPI data is output direction #1 DWIDTH Data Width This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 4 bits and can up to 32 bits. Note: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically. 8 5 read-write HALFDPX SPI Half-duplex Transfer Enable Bit This bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. 14 1 read-write 0 SPI operates in full-duplex transfer #0 1 SPI operates in half-duplex transfer #1 LSB Send LSB First 13 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX) #1 REORDER Byte Reorder Function Enable Bit Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 19 1 read-write 0 Byte Reorder function Disabled #0 1 Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV #1 RXNEG Receive on Negative Edge 1 1 read-write 0 Received data input signal is latched on the rising edge of SPI bus clock #0 1 Received data input signal is latched on the falling edge of SPI bus clock #1 RXONLY Receive-only Mode Enable Bit This bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. 15 1 read-write 0 Receive-only mode Disabled #0 1 Receive-only mode Enabled #1 SLAVE Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SPIEN SPI Transfer Control Enable Bit In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1. Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. 0 1 read-write 0 Transfer control Disabled #0 1 Transfer control Enabled #1 SUSPITV Suspend Interval The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation. (SUSPITV + 0.5) * period of SPICLK clock cycle Example: Note: Master Mode only. 4 4 read-write TXNEG Transmit on Negative Edge 2 1 read-write 0 Transmitted data output signal is changed on the rising edge of SPI bus clock #0 1 Transmitted data output signal is changed on the falling edge of SPI bus clock #1 UNITIEN Unit Transfer Interrupt Enable Bit 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 SPIx_FIFOCTL SPIx_FIFOCTL SPI FIFO Control Register 0x10 -1 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear Note: The RX shift register will not be cleared. 8 1 read-write 0 No effect #0 1 Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 RXOVIEN Receive FIFO Overrun Interrupt Enable Bit 5 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RXRST Receive Reset 0 1 read-write 0 No effect #0 1 Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 RXTH Receive FIFO Threshold If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 4~16 bits of data length. 24 3 read-write RXTHIEN Receive FIFO Threshold Interrupt Enable Bit 2 1 read-write 0 RX FIFO threshold interrupt Disabled #0 1 RX FIFO threshold interrupt Enabled #1 RXTOIEN Slave Receive Time-out Interrupt Enable Bit 4 1 read-write 0 Receive time-out interrupt Disabled #0 1 Receive time-out interrupt Enabled #1 SLVBERX RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error Note: SPI Slave Mode only. 10 1 read-write 0 Uncompleted RX data will be dropped from RX FIFO when bit count error event happen in SPI slave mode #0 1 Uncompleted RX data will be written into RX FIFO when bit count error event happen in SPI slave mode. User can read SLVBENUM (SPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened #1 TXFBCLR Transmit FIFO Buffer Clear Note: The TX shift register will not be cleared. 9 1 read-write 0 No effect #0 1 Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 TXRST Transmit Reset Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. 1 1 read-write 0 No effect #0 1 Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 TXTH Transmit FIFO Threshold If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 4~16 bits of data length. 28 3 read-write TXTHIEN Transmit FIFO Threshold Interrupt Enable Bit 3 1 read-write 0 TX FIFO threshold interrupt Disabled #0 1 TX FIFO threshold interrupt Enabled #1 TXUFIEN TX Underflow Interrupt Enable Bit When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt. 7 1 read-write 0 Slave TX underflow interrupt Disabled #0 1 Slave TX underflow interrupt Enabled #1 TXUFPOL TX Underflow Data Polarity Note 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. Note 2: This bit should be set as 0 in I2S mode. Note 3: When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. 6 1 read-write 0 The SPI data out is keep 0 if there is TX underflow event in Slave mode #0 1 The SPI data out is keep 1 if there is TX underflow event in Slave mode #1 SPIx_I2SCLK SPIx_I2SCLK I2S Clock Divider Control Register 0x64 -1 read-write n 0x0 0x0 BCLKDIV Bit Clock Divider The I2S controller will generate bit clock in Master mode. The clock frequency of bit clock, fBCLK, is determined by the following expression: where is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. Note: The time interval must be larger than or equal to 8 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register. 8 10 read-write I2SMODE I2S Clock Divider Number Selection for I2S Mode and SPI Mode User sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) are set. I2SMODE needs to be set before I2SEN (SPIx_I2SCTL[0]) or SPIEN (SPIx_CTL[0]) is enabled. 24 1 read-write 0 The frequency of peripheral clock sets to SPI mode #0 1 The frequency of peripheral clock sets to I2S mode #1 I2SSLAVE I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode User sets I2SSLAVE to set frequency of peripheral clock of I2S master mode and I2S slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set. I2SSLAVE needs to be set before I2SEN (SPIx_I2SCTL[0]) is enabled. 25 1 read-write 0 The frequency of peripheral clock sets to I2S master mode #0 1 The frequency of peripheral clock sets to I2S slave mode #1 MCLKDIV Master Clock Divider If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions: where is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate. 0 7 read-write SPIx_I2SCTL SPIx_I2SCTL I2S Control Register 0x60 -1 read-write n 0x0 0x0 FORMAT Data Format Selection 28 2 read-write 0 I2S data format #00 1 MSB justified data format #01 2 PCM mode A #10 3 PCM mode B #11 I2SEN I2S Controller Enable Bit Note 1: If enabling this bit, I2Sx_BCLK will start to output in Master mode. Note 2: Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. 0 1 read-write 0 I2S mode Disabled #0 1 I2S mode Enabled #1 LZCEN Left Channel Zero Cross Detection Enable Bit If this bit is set to 1, when sign bits of the current left channel TX data and the next left channel TX data change or next TX shift data bits are all 0 then I2S TX output data of the left channel is 0 and LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 17 1 read-write 0 Left channel zero cross detection Disabled #0 1 Left channel zero cross detection Enabled #1 LZCIEN Left Channel Zero Cross Interrupt Enable Bit Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs. 25 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 MCLKEN Master Clock Enable Bit If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. 15 1 read-write 0 Master clock Disabled #0 1 Master clock Enabled #1 MONO Monaural Data 6 1 read-write 0 Data is stereo format #0 1 Data is monaural format #1 MUTE Transmit Mute Enable Bit 3 1 read-write 0 Transmit data is shifted from buffer #0 1 Transmit channel zero #1 ORDER Stereo Data Order in FIFO 7 1 read-write 0 Left channel data at high byte #0 1 Left channel data at low byte #1 RXEN Receive Enable Bit 2 1 read-write 0 Data receive Disabled #0 1 Data receive Enabled #1 RXLCH Receive Left Channel Enable Bit 23 1 read-write 0 Receive right channel data in Mono mode #0 1 Receive left channel data in Mono mode #1 RZCEN Right Channel Zero Cross Detection Enable Bit If this bit is set to 1, when sign bits of the current right channel TX data and the next right channel TX data change or next TX shift data bits are all 0 then I2S TX output data of the right channel is 0 and RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 16 1 read-write 0 Right channel zero cross detection Disabled #0 1 Right channel zero cross detection Enabled #1 RZCIEN Right Channel Zero Cross Interrupt Enable Bit Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs. 24 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 SLAVE Slave Mode I2S can operate as master or slave. For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. 8 1 read-write 0 Master mode #0 1 Slave mode #1 SLVERRIEN Bit Number Error Interrupt Enable Bit for Slave Mode Interrupt occurs if this bit is set to 1 and bit number error event occurs. 31 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 TXEN Transmit Enable Bit 1 1 read-write 0 Data transmit Disabled #0 1 Data transmit Enabled #1 WDWIDTH Word Width 4 2 read-write 0 data size is 8-bit #00 1 data size is 16-bit #01 2 data size is 24-bit #10 3 data size is 32-bit #11 SPIx_I2SSTS SPIx_I2SSTS I2S Status Register 0x68 -1 read-write n 0x0 0x0 I2SENSTS I2S Enable Status (Read Only) Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. 15 1 read-only 0 SPI/I2S control logic Disabled #0 1 SPI/I2S control logic Enabled #1 LZCIF Left Channel Zero Cross Interrupt Flag 21 1 read-write 0 No zero cross event occurred on left channel #0 1 Zero cross event occurred on left channel #1 RIGHT Right Channel (Read Only) This bit indicates the current transmit data is belong to which channel. 4 1 read-only 0 Left channel #0 1 Right channel #1 RXCNT Receive FIFO Data Count (Read Only) This bit field indicates the valid data count of receive FIFO buffer. 24 3 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. Note: This bit will be cleared by writing 1 to it. 11 1 read-write RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag Note: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 RZCIF Right Channel Zero Cross Interrupt Flag 20 1 read-write 0 No zero cross event occurred on right channel #0 1 Zero cross event occurred on right channel #1 SLVERRIF Bit Number Error Interrupt Flag for Slave Mode Note: This bit will be cleared by writing 1 to it. 22 1 read-write 0 No bit number error event occurred #0 1 Bit number error event occurred #1 TXCNT Transmit FIFO Data Count (Read Only) This bit field indicates the valid data count of transmit FIFO buffer. 28 3 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only) Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF Transmit FIFO Underflow Interrupt Flag When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1. Note: This bit will be cleared by writing 1 to it. 19 1 read-write SPIx_PDMACTL SPIx_PDMACTL SPI PDMA Control Register 0xC -1 read-write n 0x0 0x0 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0 #1 RXPDMAEN Receive PDMA Enable Bit 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit Note1: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously. Note2: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, TX PDMA function cannot be disabled prior to RX PDMA function. User can disable RX PDMA function firstly or disable both functions simultaneously. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPIx_RX SPIx_RX SPI Data Receive Register 0x30 -1 read-only n 0x0 0x0 RX Data Receive Register (Read Only) There are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. 0 32 read-only SPIx_SSCTL SPIx_SSCTL SPI Slave Select Control Register 0x8 -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit Note: Master Mode only. 3 1 read-write 0 Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]) #0 1 Automatic slave selection function Enabled #1 SLV3WIRE Slave 3-wire Mode Enable Bit In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIx_CLK, SPIx_MISO and SPIx_MOSI pins. Note 1: The value of this register equals to control register SLAVE (SPIx_I2SCTL[8]) when I2S mode is enabled. Note 2: SPI Slave Mode only. 4 1 read-write 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit 8 1 read-write 0 Slave mode bit count error interrupt Disabled #0 1 Slave mode bit count error interrupt Enabled #1 SLVURIEN Slave Mode TX Under Run Interrupt Enable Bit 9 1 read-write 0 Slave mode TX under run interrupt Disabled #0 1 Slave mode TX under run interrupt Enabled #1 SS Slave Selection Control If AUTOSS bit is cleared to 0, Note: Master Mode only. Note: It is Master Only. Note: It is Master Only. 0 1 read-write 0 set the SPIx_SS line to inactive state. Keep the SPIx_SS line at inactive state #0 1 set the SPIx_SS line to active state. SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]) #1 SSACTIEN Slave Select Active Interrupt Enable Bit 12 1 read-write 0 Slave select active interrupt Disabled #0 1 Slave select active interrupt Enabled #1 SSACTPOL Slave Selection Active Polarity This bit defines the active polarity of slave selection signal (SPIx_SS). 2 1 read-write 0 The slave selection signal SPIx_SS is active low #0 1 The slave selection signal SPIx_SS is active high #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit 13 1 read-write 0 Slave select inactive interrupt Disabled #0 1 Slave select inactive interrupt Enabled #1 SPIx_STATUS SPIx_STATUS SPI Status Register 0x14 -1 read-write n 0x0 0x0 BUSY Busy Status (Read Only) Note: By applications, this SPI bus flag should be used with other status registers in SPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF. Therefore the SPI transfer done events of TX/RX operations can be obtained at correct timing point. 0 1 read-only 0 SPI controller is in idle state #0 1 SPI controller is in busy state #1 RXCNT Receive FIFO Data Count (Read Only) This bit field indicates the valid data count of receive FIFO buffer. 24 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. Note: This bit will be cleared by writing 1 to it. 11 1 read-write 0 No FIFO is overrun #0 1 Receive FIFO is overrun #1 RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag Note: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 SLVBEIF Slave Mode Bit Count Error Interrupt Flag In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it. 6 1 read-write 0 No Slave mode bit count error event #0 1 Slave mode bit count error event occurred #1 SLVURIF Slave Mode TX Under Run Interrupt Flag In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. Note: This bit will be cleared by writing 1 to it. 7 1 read-write 0 No Slave TX under run event #0 1 Slave TX under run event occurred #1 SPIENSTS SPI Enable Status (Read Only) Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. 15 1 read-only 0 SPI controller Disabled #0 1 SPI controller Enabled #1 SSACTIF Slave Select Active Interrupt Flag Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 2 1 read-write 0 Slave select active interrupt was cleared or not occurred #0 1 Slave select active interrupt event occurred #1 SSINAIF Slave Select Inactive Interrupt Flag Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 3 1 read-write 0 Slave select inactive interrupt was cleared or not occurred #0 1 Slave select inactive interrupt event occurred #1 SSLINE Slave Select Line Bus Status (Read Only) Note: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 4 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXCNT Transmit FIFO Data Count (Read Only) This bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only) Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF TX Underflow Interrupt Flag When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. Note 1: This bit will be cleared by writing 1 to it. Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 19 1 read-write 0 No effect #0 1 No data in Transmit FIFO and TX shift register when the slave selection signal is active #1 UNITIF Unit Transfer Interrupt Flag Note: This bit will be cleared by writing 1 to it. 1 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 SPIx_STATUS2 SPIx_STATUS2 SPI Status2 Register 0x18 -1 read-only n 0x0 0x0 SLVBENUM Effective Bit Number of Uncompleted RX Data This status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI slave mode. This status register will be fixed to 0x0 when SLVBERX (SPIx_FIFOCTL[10]) is disabled. Note 1: This register will be cleared to 0x0 when user write 0x1 to SLVBEIF (SPIx_STATUS[6]). Note 2: SPI Slave Mode only. 24 6 read-only SPIx_TX SPIx_TX SPI Data Transmit Register 0x20 -1 write-only n 0x0 0x0 TX Data Transmit Register The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode. In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer. In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 0 32 write-only SPI1 SPI Register Map SPI 0x0 0x0 0x1C registers n 0x20 0x4 registers n 0x30 0x4 registers n 0x60 0xC registers n SPIx_CLKDIV SPIx_CLKDIV SPI Clock Divider Register 0x4 -1 read-write n 0x0 0x0 DIVIDER Clock Divider The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation. where is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. Note 1: Not supported in I2S mode. Note 2: The time interval must be larger than or equal to 8 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register. 0 9 read-write SPIx_CTL SPIx_CTL SPI Control Register 0x0 -1 read-write n 0x0 0x0 CLKPOL Clock Polarity 3 1 read-write 0 SPI bus clock is idle low #0 1 SPI bus clock is idle high #1 DATDIR Data Port Direction Control This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer 20 1 read-write 0 SPI data is input direction #0 1 SPI data is output direction #1 DWIDTH Data Width This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 4 bits and can up to 32 bits. Note: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically. 8 5 read-write HALFDPX SPI Half-duplex Transfer Enable Bit This bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. 14 1 read-write 0 SPI operates in full-duplex transfer #0 1 SPI operates in half-duplex transfer #1 LSB Send LSB First 13 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX) #1 REORDER Byte Reorder Function Enable Bit Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 19 1 read-write 0 Byte Reorder function Disabled #0 1 Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV #1 RXNEG Receive on Negative Edge 1 1 read-write 0 Received data input signal is latched on the rising edge of SPI bus clock #0 1 Received data input signal is latched on the falling edge of SPI bus clock #1 RXONLY Receive-only Mode Enable Bit This bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. 15 1 read-write 0 Receive-only mode Disabled #0 1 Receive-only mode Enabled #1 SLAVE Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SPIEN SPI Transfer Control Enable Bit In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1. Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. 0 1 read-write 0 Transfer control Disabled #0 1 Transfer control Enabled #1 SUSPITV Suspend Interval The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation. (SUSPITV + 0.5) * period of SPICLK clock cycle Example: Note: Master Mode only. 4 4 read-write TXNEG Transmit on Negative Edge 2 1 read-write 0 Transmitted data output signal is changed on the rising edge of SPI bus clock #0 1 Transmitted data output signal is changed on the falling edge of SPI bus clock #1 UNITIEN Unit Transfer Interrupt Enable Bit 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 SPIx_FIFOCTL SPIx_FIFOCTL SPI FIFO Control Register 0x10 -1 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear Note: The RX shift register will not be cleared. 8 1 read-write 0 No effect #0 1 Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 RXOVIEN Receive FIFO Overrun Interrupt Enable Bit 5 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RXRST Receive Reset 0 1 read-write 0 No effect #0 1 Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 RXTH Receive FIFO Threshold If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 4~16 bits of data length. 24 3 read-write RXTHIEN Receive FIFO Threshold Interrupt Enable Bit 2 1 read-write 0 RX FIFO threshold interrupt Disabled #0 1 RX FIFO threshold interrupt Enabled #1 RXTOIEN Slave Receive Time-out Interrupt Enable Bit 4 1 read-write 0 Receive time-out interrupt Disabled #0 1 Receive time-out interrupt Enabled #1 SLVBERX RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error Note: SPI Slave Mode only. 10 1 read-write 0 Uncompleted RX data will be dropped from RX FIFO when bit count error event happen in SPI slave mode #0 1 Uncompleted RX data will be written into RX FIFO when bit count error event happen in SPI slave mode. User can read SLVBENUM (SPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened #1 TXFBCLR Transmit FIFO Buffer Clear Note: The TX shift register will not be cleared. 9 1 read-write 0 No effect #0 1 Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 TXRST Transmit Reset Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. 1 1 read-write 0 No effect #0 1 Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 TXTH Transmit FIFO Threshold If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 4~16 bits of data length. 28 3 read-write TXTHIEN Transmit FIFO Threshold Interrupt Enable Bit 3 1 read-write 0 TX FIFO threshold interrupt Disabled #0 1 TX FIFO threshold interrupt Enabled #1 TXUFIEN TX Underflow Interrupt Enable Bit When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt. 7 1 read-write 0 Slave TX underflow interrupt Disabled #0 1 Slave TX underflow interrupt Enabled #1 TXUFPOL TX Underflow Data Polarity Note 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. Note 2: This bit should be set as 0 in I2S mode. Note 3: When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. 6 1 read-write 0 The SPI data out is keep 0 if there is TX underflow event in Slave mode #0 1 The SPI data out is keep 1 if there is TX underflow event in Slave mode #1 SPIx_I2SCLK SPIx_I2SCLK I2S Clock Divider Control Register 0x64 -1 read-write n 0x0 0x0 BCLKDIV Bit Clock Divider The I2S controller will generate bit clock in Master mode. The clock frequency of bit clock, fBCLK, is determined by the following expression: where is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. Note: The time interval must be larger than or equal to 8 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register. 8 10 read-write I2SMODE I2S Clock Divider Number Selection for I2S Mode and SPI Mode User sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) are set. I2SMODE needs to be set before I2SEN (SPIx_I2SCTL[0]) or SPIEN (SPIx_CTL[0]) is enabled. 24 1 read-write 0 The frequency of peripheral clock sets to SPI mode #0 1 The frequency of peripheral clock sets to I2S mode #1 I2SSLAVE I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode User sets I2SSLAVE to set frequency of peripheral clock of I2S master mode and I2S slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set. I2SSLAVE needs to be set before I2SEN (SPIx_I2SCTL[0]) is enabled. 25 1 read-write 0 The frequency of peripheral clock sets to I2S master mode #0 1 The frequency of peripheral clock sets to I2S slave mode #1 MCLKDIV Master Clock Divider If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions: where is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate. 0 7 read-write SPIx_I2SCTL SPIx_I2SCTL I2S Control Register 0x60 -1 read-write n 0x0 0x0 FORMAT Data Format Selection 28 2 read-write 0 I2S data format #00 1 MSB justified data format #01 2 PCM mode A #10 3 PCM mode B #11 I2SEN I2S Controller Enable Bit Note 1: If enabling this bit, I2Sx_BCLK will start to output in Master mode. Note 2: Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. 0 1 read-write 0 I2S mode Disabled #0 1 I2S mode Enabled #1 LZCEN Left Channel Zero Cross Detection Enable Bit If this bit is set to 1, when sign bits of the current left channel TX data and the next left channel TX data change or next TX shift data bits are all 0 then I2S TX output data of the left channel is 0 and LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 17 1 read-write 0 Left channel zero cross detection Disabled #0 1 Left channel zero cross detection Enabled #1 LZCIEN Left Channel Zero Cross Interrupt Enable Bit Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs. 25 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 MCLKEN Master Clock Enable Bit If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. 15 1 read-write 0 Master clock Disabled #0 1 Master clock Enabled #1 MONO Monaural Data 6 1 read-write 0 Data is stereo format #0 1 Data is monaural format #1 MUTE Transmit Mute Enable Bit 3 1 read-write 0 Transmit data is shifted from buffer #0 1 Transmit channel zero #1 ORDER Stereo Data Order in FIFO 7 1 read-write 0 Left channel data at high byte #0 1 Left channel data at low byte #1 RXEN Receive Enable Bit 2 1 read-write 0 Data receive Disabled #0 1 Data receive Enabled #1 RXLCH Receive Left Channel Enable Bit 23 1 read-write 0 Receive right channel data in Mono mode #0 1 Receive left channel data in Mono mode #1 RZCEN Right Channel Zero Cross Detection Enable Bit If this bit is set to 1, when sign bits of the current right channel TX data and the next right channel TX data change or next TX shift data bits are all 0 then I2S TX output data of the right channel is 0 and RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 16 1 read-write 0 Right channel zero cross detection Disabled #0 1 Right channel zero cross detection Enabled #1 RZCIEN Right Channel Zero Cross Interrupt Enable Bit Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs. 24 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 SLAVE Slave Mode I2S can operate as master or slave. For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. 8 1 read-write 0 Master mode #0 1 Slave mode #1 SLVERRIEN Bit Number Error Interrupt Enable Bit for Slave Mode Interrupt occurs if this bit is set to 1 and bit number error event occurs. 31 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 TXEN Transmit Enable Bit 1 1 read-write 0 Data transmit Disabled #0 1 Data transmit Enabled #1 WDWIDTH Word Width 4 2 read-write 0 data size is 8-bit #00 1 data size is 16-bit #01 2 data size is 24-bit #10 3 data size is 32-bit #11 SPIx_I2SSTS SPIx_I2SSTS I2S Status Register 0x68 -1 read-write n 0x0 0x0 I2SENSTS I2S Enable Status (Read Only) Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. 15 1 read-only 0 SPI/I2S control logic Disabled #0 1 SPI/I2S control logic Enabled #1 LZCIF Left Channel Zero Cross Interrupt Flag 21 1 read-write 0 No zero cross event occurred on left channel #0 1 Zero cross event occurred on left channel #1 RIGHT Right Channel (Read Only) This bit indicates the current transmit data is belong to which channel. 4 1 read-only 0 Left channel #0 1 Right channel #1 RXCNT Receive FIFO Data Count (Read Only) This bit field indicates the valid data count of receive FIFO buffer. 24 3 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. Note: This bit will be cleared by writing 1 to it. 11 1 read-write RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag Note: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 RZCIF Right Channel Zero Cross Interrupt Flag 20 1 read-write 0 No zero cross event occurred on right channel #0 1 Zero cross event occurred on right channel #1 SLVERRIF Bit Number Error Interrupt Flag for Slave Mode Note: This bit will be cleared by writing 1 to it. 22 1 read-write 0 No bit number error event occurred #0 1 Bit number error event occurred #1 TXCNT Transmit FIFO Data Count (Read Only) This bit field indicates the valid data count of transmit FIFO buffer. 28 3 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only) Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF Transmit FIFO Underflow Interrupt Flag When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1. Note: This bit will be cleared by writing 1 to it. 19 1 read-write SPIx_PDMACTL SPIx_PDMACTL SPI PDMA Control Register 0xC -1 read-write n 0x0 0x0 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0 #1 RXPDMAEN Receive PDMA Enable Bit 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit Note1: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously. Note2: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, TX PDMA function cannot be disabled prior to RX PDMA function. User can disable RX PDMA function firstly or disable both functions simultaneously. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPIx_RX SPIx_RX SPI Data Receive Register 0x30 -1 read-only n 0x0 0x0 RX Data Receive Register (Read Only) There are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. 0 32 read-only SPIx_SSCTL SPIx_SSCTL SPI Slave Select Control Register 0x8 -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit Note: Master Mode only. 3 1 read-write 0 Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]) #0 1 Automatic slave selection function Enabled #1 SLV3WIRE Slave 3-wire Mode Enable Bit In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIx_CLK, SPIx_MISO and SPIx_MOSI pins. Note 1: The value of this register equals to control register SLAVE (SPIx_I2SCTL[8]) when I2S mode is enabled. Note 2: SPI Slave Mode only. 4 1 read-write 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit 8 1 read-write 0 Slave mode bit count error interrupt Disabled #0 1 Slave mode bit count error interrupt Enabled #1 SLVURIEN Slave Mode TX Under Run Interrupt Enable Bit 9 1 read-write 0 Slave mode TX under run interrupt Disabled #0 1 Slave mode TX under run interrupt Enabled #1 SS Slave Selection Control If AUTOSS bit is cleared to 0, Note: Master Mode only. Note: It is Master Only. Note: It is Master Only. 0 1 read-write 0 set the SPIx_SS line to inactive state. Keep the SPIx_SS line at inactive state #0 1 set the SPIx_SS line to active state. SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]) #1 SSACTIEN Slave Select Active Interrupt Enable Bit 12 1 read-write 0 Slave select active interrupt Disabled #0 1 Slave select active interrupt Enabled #1 SSACTPOL Slave Selection Active Polarity This bit defines the active polarity of slave selection signal (SPIx_SS). 2 1 read-write 0 The slave selection signal SPIx_SS is active low #0 1 The slave selection signal SPIx_SS is active high #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit 13 1 read-write 0 Slave select inactive interrupt Disabled #0 1 Slave select inactive interrupt Enabled #1 SPIx_STATUS SPIx_STATUS SPI Status Register 0x14 -1 read-write n 0x0 0x0 BUSY Busy Status (Read Only) Note: By applications, this SPI bus flag should be used with other status registers in SPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF. Therefore the SPI transfer done events of TX/RX operations can be obtained at correct timing point. 0 1 read-only 0 SPI controller is in idle state #0 1 SPI controller is in busy state #1 RXCNT Receive FIFO Data Count (Read Only) This bit field indicates the valid data count of receive FIFO buffer. 24 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. Note: This bit will be cleared by writing 1 to it. 11 1 read-write 0 No FIFO is overrun #0 1 Receive FIFO is overrun #1 RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag Note: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 SLVBEIF Slave Mode Bit Count Error Interrupt Flag In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it. 6 1 read-write 0 No Slave mode bit count error event #0 1 Slave mode bit count error event occurred #1 SLVURIF Slave Mode TX Under Run Interrupt Flag In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. Note: This bit will be cleared by writing 1 to it. 7 1 read-write 0 No Slave TX under run event #0 1 Slave TX under run event occurred #1 SPIENSTS SPI Enable Status (Read Only) Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. 15 1 read-only 0 SPI controller Disabled #0 1 SPI controller Enabled #1 SSACTIF Slave Select Active Interrupt Flag Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 2 1 read-write 0 Slave select active interrupt was cleared or not occurred #0 1 Slave select active interrupt event occurred #1 SSINAIF Slave Select Inactive Interrupt Flag Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 3 1 read-write 0 Slave select inactive interrupt was cleared or not occurred #0 1 Slave select inactive interrupt event occurred #1 SSLINE Slave Select Line Bus Status (Read Only) Note: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 4 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXCNT Transmit FIFO Data Count (Read Only) This bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only) Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF TX Underflow Interrupt Flag When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. Note 1: This bit will be cleared by writing 1 to it. Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 19 1 read-write 0 No effect #0 1 No data in Transmit FIFO and TX shift register when the slave selection signal is active #1 UNITIF Unit Transfer Interrupt Flag Note: This bit will be cleared by writing 1 to it. 1 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 SPIx_STATUS2 SPIx_STATUS2 SPI Status2 Register 0x18 -1 read-only n 0x0 0x0 SLVBENUM Effective Bit Number of Uncompleted RX Data This status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI slave mode. This status register will be fixed to 0x0 when SLVBERX (SPIx_FIFOCTL[10]) is disabled. Note 1: This register will be cleared to 0x0 when user write 0x1 to SLVBEIF (SPIx_STATUS[6]). Note 2: SPI Slave Mode only. 24 6 read-only SPIx_TX SPIx_TX SPI Data Transmit Register 0x20 -1 write-only n 0x0 0x0 TX Data Transmit Register The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode. In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer. In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 0 32 write-only SYS SYS Register Map SYS 0x0 0x0 0x14 registers n 0x100 0x4 registers n 0x18 0x8 registers n 0x1EC 0x4 registers n 0x1F8 0x8 registers n 0x28 0x4 registers n 0x30 0x44 registers n 0x400 0x4 registers n 0x80 0x24 registers n 0xB0 0x4 registers n 0xC0 0xC registers n 0xD0 0x8 registers n 0xF0 0xC registers n AHBMCTL SYS_AHBMCTL AHB Bus Matrix Priority Control Register 0x400 -1 read-write n 0x0 0x0 INTACTEN Highest AHB Bus Priority of Cortex-M4 Core Enable Bit (Write Protect) Enable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Round-robin mode #0 1 Cortex-M4 CPU with highest bus priority when interrupt occurred #1 BODCTL SYS_BODCTL Brown-out Detector Control Register 0x18 -1 read-write n 0x0 0x0 BODDGSEL Brown-out Detector Output De-glitch Time Select (Write Protect) Note: These bits are write protected. Refer to the SYS_REGLCTL register. 8 3 read-write 0 BOD output is sampled by RC10K clock #000 1 4 system clock (HCLK) #001 2 8 system clock (HCLK) #010 3 16 system clock (HCLK) #011 4 32 system clock (HCLK) #100 5 64 system clock (HCLK) #101 6 128 system clock (HCLK) #110 7 256 system clock (HCLK) #111 BODEN Brown-out Detector Enable Bit (Write Protect) The default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]). Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Brown-out Detector function Disabled #0 1 Brown-out Detector function Enabled #1 BODIF Brown-out Detector Interrupt Flag Note: Write 1 to clear this bit to 0. 4 1 read-write 0 Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting #0 1 When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled #1 BODLPM Brown-out Detector Low Power Mode (Write Protect) Note 1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. Note 3:BOD enable stable time is 50us, period enable time need larger than it 5 1 read-write 0 BOD operate in normal mode (default) #0 1 BOD Low Power mode Enabled #1 BODOUT Brown-out Detector Output Status It means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled, this bit always responds 0. 6 1 read-write 0 Brown-out Detector output status is 0 #0 1 Brown-out Detector output status is 1 #1 BODRSTEN Brown-out Reset Enable Bit (Write Protect) The default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit. Note 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will be kept till to the BODEN is set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 Brown-out 'INTERRUPT' function Enabled #0 1 Brown-out 'RESET' function Enabled #1 BODVL Brown-out Detector Threshold Voltage Selection (Write Protect) The default value is set by Flash controller user configuration register CBOV (CONFIG0 [22:21]). Note: This bit is write protected. Refer to the SYS_REGLCTL register. 16 2 read-write 0 Brown-Out Detector threshold voltage is 2.4V #00 1 Brown-Out Detector threshold voltage is 2.7V #01 2 Brown-Out Detector threshold voltage is 3.7V #10 3 Brown-Out Detector threshold voltage is 4.4V #11 LVRDGSEL LVR Output De-glitch Time Select (Write Protect) Note: These bits are write protected. Refer to the SYS_REGLCTL register. 12 3 read-write 0 Without de-glitch function #000 1 4 system clock (HCLK) #001 2 8 system clock (HCLK) #010 3 16 system clock (HCLK) #011 4 32 system clock (HCLK) #100 5 64 system clock (HCLK) #101 6 128 system clock (HCLK) #110 7 256 system clock (HCLK) #111 LVREN Low Voltage Reset Enable Bit (Write Protect) The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. Note 1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Low Voltage Reset function Disabled #0 1 Low Voltage Reset function Enabled #1 GPA_MFOS SYS_GPA_MFOS GPIOA Multiple Function Output Select Register 0x80 -1 read-write n 0x0 0x0 MFOS0 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 0 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 MFOS1 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 1 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 MFOS10 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 10 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 MFOS11 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 11 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 MFOS12 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 12 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 MFOS13 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 13 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 MFOS14 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 14 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 MFOS15 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 15 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 MFOS2 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 2 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 MFOS3 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 3 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 MFOS4 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 4 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 MFOS5 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 5 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 MFOS6 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 6 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 MFOS7 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 7 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 MFOS8 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 8 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 MFOS9 GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available. 9 1 read-write 0 Multiple function pin output mode type is Push-pull mode #0 1 Multiple function pin output mode type is Open-drain mode #1 GPA_MFPH SYS_GPA_MFPH GPIOA High Byte Multiple Function Control Register 0x34 -1 read-write n 0x0 0x0 PA10MFP PA.10 Multi-function Pin Selection 8 4 read-write PA11MFP PA.11 Multi-function Pin Selection 12 4 read-write PA12MFP PA.12 Multi-function Pin Selection 16 4 read-write PA13MFP PA.13 Multi-function Pin Selection 20 4 read-write PA14MFP PA.14 Multi-function Pin Selection 24 4 read-write PA15MFP PA.15 Multi-function Pin Selection 28 4 read-write PA8MFP PA.8 Multi-function Pin Selection 0 4 read-write PA9MFP PA.9 Multi-function Pin Selection 4 4 read-write GPA_MFPL SYS_GPA_MFPL GPIOA Low Byte Multiple Function Control Register 0x30 -1 read-write n 0x0 0x0 PA0MFP PA.0 Multi-function Pin Selection 0 4 read-write PA1MFP PA.1 Multi-function Pin Selection 4 4 read-write PA2MFP PA.2 Multi-function Pin Selection 8 4 read-write PA3MFP PA.3 Multi-function Pin Selection 12 4 read-write PA4MFP PA.4 Multi-function Pin Selection 16 4 read-write PA5MFP PA.5 Multi-function Pin Selection 20 4 read-write PA6MFP PA.6 Multi-function Pin Selection 24 4 read-write PA7MFP PA.7 Multi-function Pin Selection 28 4 read-write GPB_MFOS SYS_GPB_MFOS GPIOB Multiple Function Output Select Register 0x84 -1 read-write n 0x0 0x0 GPB_MFPH SYS_GPB_MFPH GPIOB High Byte Multiple Function Control Register 0x3C -1 read-write n 0x0 0x0 PB10MFP PB.10 Multi-function Pin Selection 8 4 read-write PB11MFP PB.11 Multi-function Pin Selection 12 4 read-write PB12MFP PB.12 Multi-function Pin Selection 16 4 read-write PB13MFP PB.13 Multi-function Pin Selection 20 4 read-write PB14MFP PB.14 Multi-function Pin Selection 24 4 read-write PB15MFP PB.15 Multi-function Pin Selection 28 4 read-write PB8MFP PB.8 Multi-function Pin Selection 0 4 read-write PB9MFP PB.9 Multi-function Pin Selection 4 4 read-write GPB_MFPL SYS_GPB_MFPL GPIOB Low Byte Multiple Function Control Register 0x38 -1 read-write n 0x0 0x0 PB0MFP PB.0 Multi-function Pin Selection 0 4 read-write PB1MFP PB.1 Multi-function Pin Selection 4 4 read-write PB2MFP PB.2 Multi-function Pin Selection 8 4 read-write PB3MFP PB.3 Multi-function Pin Selection 12 4 read-write PB4MFP PB.4 Multi-function Pin Selection 16 4 read-write PB5MFP PB.5 Multi-function Pin Selection 20 4 read-write PB6MFP PB.6 Multi-function Pin Selection 24 4 read-write PB7MFP PB.7 Multi-function Pin Selection 28 4 read-write GPC_MFOS SYS_GPC_MFOS GPIOC Multiple Function Output Select Register 0x88 -1 read-write n 0x0 0x0 GPC_MFPH SYS_GPC_MFPH GPIOC High Byte Multiple Function Control Register 0x44 -1 read-write n 0x0 0x0 PC10MFP PC.10 Multi-function Pin Selection 8 4 read-write PC11MFP PC.11 Multi-function Pin Selection 12 4 read-write PC12MFP PC.12 Multi-function Pin Selection 16 4 read-write PC13MFP PC.13 Multi-function Pin Selection 20 4 read-write PC14MFP PC.14 Multi-function Pin Selection 24 4 read-write PC8MFP PC.8 Multi-function Pin Selection 0 4 read-write PC9MFP PC.9 Multi-function Pin Selection 4 4 read-write GPC_MFPL SYS_GPC_MFPL GPIOC Low Byte Multiple Function Control Register 0x40 -1 read-write n 0x0 0x0 PC0MFP PC.0 Multi-function Pin Selection 0 4 read-write PC1MFP PC.1 Multi-function Pin Selection 4 4 read-write PC2MFP PC.2 Multi-function Pin Selection 8 4 read-write PC3MFP PC.3 Multi-function Pin Selection 12 4 read-write PC4MFP PC.4 Multi-function Pin Selection 16 4 read-write PC5MFP PC.5 Multi-function Pin Selection 20 4 read-write PC6MFP PC.6 Multi-function Pin Selection 24 4 read-write PC7MFP PC.7 Multi-function Pin Selection 28 4 read-write GPD_MFOS SYS_GPD_MFOS GPIOD Multiple Function Output Select Register 0x8C -1 read-write n 0x0 0x0 GPD_MFPH SYS_GPD_MFPH GPIOD High Byte Multiple Function Control Register 0x4C -1 read-write n 0x0 0x0 PD10MFP PD.10 Multi-function Pin Selection 8 4 read-write PD11MFP PD.11 Multi-function Pin Selection 12 4 read-write PD12MFP PD.12 Multi-function Pin Selection 16 4 read-write PD13MFP PD.13 Multi-function Pin Selection 20 4 read-write PD14MFP PD.14 Multi-function Pin Selection 24 4 read-write PD15MFP PD.15 Multi-function Pin Selection 28 4 read-write PD8MFP PD.8 Multi-function Pin Selection 0 4 read-write PD9MFP PD.9 Multi-function Pin Selection 4 4 read-write GPD_MFPL SYS_GPD_MFPL GPIOD Low Byte Multiple Function Control Register 0x48 -1 read-write n 0x0 0x0 PD0MFP PD.0 Multi-function Pin Selection 0 4 read-write PD1MFP PD.1 Multi-function Pin Selection 4 4 read-write PD2MFP PD.2 Multi-function Pin Selection 8 4 read-write PD3MFP PD.3 Multi-function Pin Selection 12 4 read-write PD4MFP PD.4 Multi-function Pin Selection 16 4 read-write PD5MFP PD.5 Multi-function Pin Selection 20 4 read-write PD6MFP PD.6 Multi-function Pin Selection 24 4 read-write PD7MFP PD.7 Multi-function Pin Selection 28 4 read-write GPE_MFOS SYS_GPE_MFOS GPIOE Multiple Function Output Select Register 0x90 -1 read-write n 0x0 0x0 GPE_MFPH SYS_GPE_MFPH GPIOE High Byte Multiple Function Control Register 0x54 -1 read-write n 0x0 0x0 PE10MFP PE.10 Multi-function Pin Selection 8 4 read-write PE11MFP PE.11 Multi-function Pin Selection 12 4 read-write PE12MFP PE.12 Multi-function Pin Selection 16 4 read-write PE13MFP PE.13 Multi-function Pin Selection 20 4 read-write PE14MFP PE.14 Multi-function Pin Selection 24 4 read-write PE15MFP PE.15 Multi-function Pin Selection 28 4 read-write PE8MFP PE.8 Multi-function Pin Selection 0 4 read-write PE9MFP PE.9 Multi-function Pin Selection 4 4 read-write GPE_MFPL SYS_GPE_MFPL GPIOE Low Byte Multiple Function Control Register 0x50 -1 read-write n 0x0 0x0 PE0MFP PE.0 Multi-function Pin Selection 0 4 read-write PE1MFP PE.1 Multi-function Pin Selection 4 4 read-write PE2MFP PE.2 Multi-function Pin Selection 8 4 read-write PE3MFP PE.3 Multi-function Pin Selection 12 4 read-write PE4MFP PE.4 Multi-function Pin Selection 16 4 read-write PE5MFP PE.5 Multi-function Pin Selection 20 4 read-write PE6MFP PE.6 Multi-function Pin Selection 24 4 read-write PE7MFP PE.7 Multi-function Pin Selection 28 4 read-write GPF_MFOS SYS_GPF_MFOS GPIOF Multiple Function Output Select Register 0x94 -1 read-write n 0x0 0x0 GPF_MFPH SYS_GPF_MFPH GPIOF High Byte Multiple Function Control Register 0x5C -1 read-write n 0x0 0x0 PF10MFP PF.10 Multi-function Pin Selection 8 4 read-write PF11MFP PF.11 Multi-function Pin Selection 12 4 read-write PF12MFP PF.12 Multi-function Pin Selection 16 4 read-write PF13MFP PF.13 Multi-function Pin Selection 20 4 read-write PF14MFP PF.14 Multi-function Pin Selection 24 4 read-write PF15MFP PF.15 Multi-function Pin Selection 28 4 read-write PF8MFP PF.8 Multi-function Pin Selection 0 4 read-write PF9MFP PF.9 Multi-function Pin Selection 4 4 read-write GPF_MFPL SYS_GPF_MFPL GPIOF Low Byte Multiple Function Control Register 0x58 -1 read-write n 0x0 0x0 PF0MFP PF.0 Multi-function Pin Selection 0 4 read-write PF1MFP PF.1 Multi-function Pin Selection 4 4 read-write PF2MFP PF.2 Multi-function Pin Selection 8 4 read-write PF3MFP PF.3 Multi-function Pin Selection 12 4 read-write PF4MFP PF.4 Multi-function Pin Selection 16 4 read-write PF5MFP PF.5 Multi-function Pin Selection 20 4 read-write PF6MFP PF.6 Multi-function Pin Selection 24 4 read-write PF7MFP PF.7 Multi-function Pin Selection 28 4 read-write GPG_MFOS SYS_GPG_MFOS GPIOG Multiple Function Output Select Register 0x98 -1 read-write n 0x0 0x0 GPG_MFPH SYS_GPG_MFPH GPIOG High Byte Multiple Function Control Register 0x64 -1 read-write n 0x0 0x0 PG10MFP PG.10 Multi-function Pin Selection 8 4 read-write PG11MFP PG.11 Multi-function Pin Selection 12 4 read-write PG12MFP PG.12 Multi-function Pin Selection 16 4 read-write PG13MFP PG.13 Multi-function Pin Selection 20 4 read-write PG14MFP PG.14 Multi-function Pin Selection 24 4 read-write PG15MFP PG.15 Multi-function Pin Selection 28 4 read-write PG8MFP PG.8 Multi-function Pin Selection 0 4 read-write PG9MFP PG.9 Multi-function Pin Selection 4 4 read-write GPG_MFPL SYS_GPG_MFPL GPIOG Low Byte Multiple Function Control Register 0x60 -1 read-write n 0x0 0x0 PG2MFP PG.2 Multi-function Pin Selection 8 4 read-write PG3MFP PG.3 Multi-function Pin Selection 12 4 read-write PG4MFP PG.4 Multi-function Pin Selection 16 4 read-write GPH_MFOS SYS_GPH_MFOS GPIOH Multiple Function Output Select Register 0x9C -1 read-write n 0x0 0x0 GPH_MFPH SYS_GPH_MFPH GPIOH High Byte Multiple Function Control Register 0x6C -1 read-write n 0x0 0x0 PH10MFP PH.10 Multi-function Pin Selection 8 4 read-write PH11MFP PH.11 Multi-function Pin Selection 12 4 read-write PH8MFP PH.8 Multi-function Pin Selection 0 4 read-write PH9MFP PH.9 Multi-function Pin Selection 4 4 read-write GPH_MFPL SYS_GPH_MFPL GPIOH Low Byte Multiple Function Control Register 0x68 -1 read-write n 0x0 0x0 PH4MFP PH.4 Multi-function Pin Selection 16 4 read-write PH5MFP PH.5 Multi-function Pin Selection 20 4 read-write PH6MFP PH.6 Multi-function Pin Selection 24 4 read-write PH7MFP PH.7 Multi-function Pin Selection 28 4 read-write GPI_MFOS SYS_GPI_MFOS GPIOI Multiple Function Output Select Register 0xA0 -1 read-write n 0x0 0x0 GPI_MFPL SYS_GPI_MFPL GPIOI Low Byte Multiple Function Control Register 0x70 -1 read-write n 0x0 0x0 PI0MFP PI.0 Multi-function Pin Selection 0 4 read-write PI1MFP PI.1 Multi-function Pin Selection 4 4 read-write PI2MFP PI.2 Multi-function Pin Selection 8 4 read-write PI3MFP PI.3 Multi-function Pin Selection 12 4 read-write PI4MFP PI.4 Multi-function Pin Selection 16 4 read-write PI5MFP PI.5 Multi-function Pin Selection 20 4 read-write IPRST0 SYS_IPRST0 Peripheral Reset Control Register 0 0x8 -1 read-write n 0x0 0x0 CHIPRST Chip One-shot Reset (Write Protect) Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload. About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 7.2.2 Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Chip normal operation #0 1 Chip one-shot reset #1 CPURST Processor Core One-shot Reset (Write Protect) Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Processor core normal operation #0 1 Processor core one-shot reset #1 CRCRST CRC Calculation Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 CRC calculation controller normal operation #0 1 CRC calculation controller reset #1 PDMARST PDMA Controller Reset (Write Protect) Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 PDMA controller normal operation #0 1 PDMA controller reset #1 IPRST1 SYS_IPRST1 Peripheral Reset Control Register 1 0xC -1 read-write n 0x0 0x0 ACMP01RST Analog Comparator 0/1 Controller Reset 7 1 read-write 0 Analog Comparator 0/1 controller normal operation #0 1 Analog Comparator 0/1 controller reset #1 EADCRST EADC Controller Reset 28 1 read-write 0 EADC controller normal operation #0 1 EADC controller reset #1 GPIORST GPIO Controller Reset 1 1 read-write 0 GPIO controller normal operation #0 1 GPIO controller reset #1 I2C0RST I2C0 Controller Reset 8 1 read-write 0 I2C0 controller normal operation #0 1 I2C0 controller reset #1 I2C1RST I2C1 Controller Reset 9 1 read-write 0 I2C1 controller normal operation #0 1 I2C1 controller reset #1 SPI0RST SPI0 Controller Reset 13 1 read-write 0 SPI0 controller normal operation #0 1 SPI0 controller reset #1 SPI1RST SPI1 Controller Reset 14 1 read-write 0 SPI1 controller normal operation #0 1 SPI1 controller reset #1 TMR0RST Timer0 Controller Reset 2 1 read-write 0 Timer0 controller normal operation #0 1 Timer0 controller reset #1 TMR1RST Timer1 Controller Reset 3 1 read-write 0 Timer1 controller normal operation #0 1 Timer1 controller reset #1 TMR2RST Timer2 Controller Reset 4 1 read-write 0 Timer2 controller normal operation #0 1 Timer2 controller reset #1 TMR3RST Timer3 Controller Reset 5 1 read-write 0 Timer3 controller normal operation #0 1 Timer3 controller reset #1 UART0RST UART0 Controller Reset 16 1 read-write 0 UART0 controller normal operation #0 1 UART0 controller reset #1 UART1RST UART1 Controller Reset 17 1 read-write 0 UART1 controller normal operation #0 1 UART1 controller reset #1 UART2RST UART2 Controller Reset 18 1 read-write 0 UART2 controller normal operation #0 1 UART2 controller reset #1 UART3RST UART3 Controller Reset 19 1 read-write 0 UART3 controller normal operation #0 1 UART3 controller reset #1 UART4RST UART4 Controller Reset 20 1 read-write 0 UART4 controller normal operation #0 1 UART4 controller reset #1 UART5RST UART5 Controller Reset 21 1 read-write 0 UART5 controller normal operation #0 1 UART5 controller reset #1 IPRST2 SYS_IPRST2 Peripheral Reset Control Register 2 0x10 -1 read-write n 0x0 0x0 BPWM0RST BPWM0 Controller Reset 18 1 read-write 0 BPWM0 controller normal operation #0 1 BPWM0 controller reset #1 BPWM1RST BPWM1 Controller Reset 19 1 read-write 0 BPWM1 controller normal operation #0 1 BPWM1 controller reset #1 CIR0RST CIR0 Controller Reset 15 1 read-write 0 CIR0 controller normal operation #0 1 CIR0 controller reset #1 DACRST DAC Controller Reset 12 1 read-write 0 DAC controller normal operation #0 1 DAC controller reset #1 EPWM0RST EPWM0 Controller Reset 16 1 read-write 0 EPWM0 controller normal operation #0 1 EPWM0 controller reset #1 EPWM1RST EPWM1 Controller Reset 17 1 read-write 0 EPWM1 controller normal operation #0 1 EPWM1 controller reset #1 PRNGRST PRNG Controller Reset 24 1 read-write 0 PRNG controller normal operation #0 1 PRNG controller reset #1 IRCTCTL SYS_IRCTCTL HIRC Trim Control Register 0xF0 -1 read-write n 0x0 0x0 BOUNDARY Boundary Selection Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. This field shows the update value range. If the difference between the current trim value and the new update trim value is smaller than BOUNDARY value, then the trim value will be update to RC or it will keep the current trim value. Note 1: When the RC clock shift over 0.25% due to temperature condition in lock state, rc_trim circuit will increase or decrease at least 2 to trim value. Note 2: Only when the difference of the current frequency count and the target frequency count is smaller than 0.25% in unlock state, rc_trim circuit will increase or decrease 1 to trim value. Note: This field is effective only when the BOUNDEN(SYS_IRCTCTL[9]) is enabled. 16 5 read-write BOUNDEN Boundary Enable Bit 9 1 read-write 0 Boundary function Disabled #0 1 Boundary function Enabled #1 CESTOPEN Clock Error Stop Enable Bit 8 1 read-write 0 The trim operation keeps going if clock is inaccurate #0 1 The trim operation is stopped if clock is inaccurate #1 FREQSEL Trim Frequency Selection This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim. During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. Note: Only when the LXT and HIRC is stable, then the FREQSEL setting will be load to HIRC auto trim circuit. 0 2 read-write 0 Disable HIRC auto trim function #00 1 Enable HIRC auto trim function and trim HIRC to 48 MHz #01 2 Reserved. #10 3 Reserved. #11 LOOPSEL Trim Calculation Loop Selection This field defines that trim value calculation is based on how many reference clocks. Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 4 2 read-write 0 Trim value calculation is based on average difference in 4 clocks of reference clock #00 1 Trim value calculation is based on average difference in 8 clocks of reference clock #01 2 Trim value calculation is based on average difference in 16 clocks of reference clock #10 3 Trim value calculation is based on average difference in 32 clocks of reference clock #11 REFCKSEL Reference Clock Selection Note: The HIRC trim reference clock is 20 kHz in test mode. 10 1 read-write 0 HIRC trim reference clock is from LXT (32.768 kHz) #0 1 Reserved. #1 RETRYCNT Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. Once the HIRC is locked, the internal trim value update counter will be reset. If the trim value update counter reaches this limitation value and the frequency of HIRC is still not locked, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 6 2 read-write 0 Trim retry count limitation is 64 loops #00 1 Trim retry count limitation is 128 loops #01 2 Trim retry count limitation is 256 loops #10 3 Trim retry count limitation is 512 loops #11 IRCTIEN SYS_IRCTIEN HIRC Trim Interrupt Enable Register 0xF4 -1 read-write n 0x0 0x0 CLKEIEN Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccurate during auto trim operation. If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccurate. 2 1 read-write 0 Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU #0 1 Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU #1 TFAILIEN Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]). If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 1 1 read-write 0 Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU #0 1 Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU #1 IRCTISTS SYS_IRCTISTS HIRC Trim Interrupt Status Register 0xF8 -1 read-write n 0x0 0x0 CLKERRIF Clock Error Interrupt Status When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccurate. Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1. If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccurate. Write 1 to clear this to 0. 2 1 read-write 0 Clock frequency is accurate #0 1 Clock frequency is inaccurate #1 FREQLOCK HIRC Frequency Lock Status This bit indicates the HIRC frequency is locked. This is a status bit and does not trigger any interrupt Write 1 to clear this to 0. This bit will be set automatically, if the frequency is locked and the RC_TRIM is enabled. 0 1 read-write 0 The internal high-speed oscillator frequency is not locked at 48 MHz yet #0 1 The internal high-speed oscillator frequency is locked at 48 MHz #1 OVBDIF Over Boundary Status When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. Note 1: Write 1 to clear this flag. 3 1 read-write 0 Over boundary coundition did not occur #0 1 Over boundary coundition occurred #1 TFAILIF Trim Failure Interrupt Status This bit indicates that HIRC trim value update limitation count is reached and the HIRC clock frequency is still not locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically. If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0. 1 1 read-write 0 Trim value update limitation count is not reached #0 1 Trim value update limitation count is reached and HIRC frequency is still not locked #1 IVSCTL SYS_IVSCTL Internal Voltage Source Control Register 0x1C -1 read-write n 0x0 0x0 VTEMPEN Temperature Sensor Enable Bit This bit is used to enable/disable temperature sensor function. 0 1 read-write 0 Temperature sensor function Disabled (default) #0 1 Temperature sensor function Enabled #1 MODCTL SYS_MODCTL Modulation Control Register 0xB0 -1 read-write n 0x0 0x0 MODEN Modulation Function Enable Bit This bit enables modulation funcion by modulating with EPWM0 channel output and UART0(UART0_TXD) output. 0 1 read-write 0 Modulation Function Disabled #0 1 Modulation Function Enabled #1 MODH Modulation at Data High Select modulation pulse(EPWM0) at high or low of UART0_TXD. 0: Modulation pulse at UART0_TXD low. 1: Modulation pulse at UART0_TXD high. 1 1 read-write MODPWMSEL EPWM0 Channel Select for Modulation Select the EPWM0 channel to modulate with the UART0_TXD. 0000: EPWM0 Channel 0 modulate with UART0_TXD. 0001: EPWM0 Channel 1 modulate with UART0_TXD. 0010: EPWM0 Channel 2 modulate with UART0_TXD. 0011: EPWM0 Channel 3 modulete with UART0_TXD. 0100: EPWM0 Channel 4 modulete with UART0_TXD. 0101: EPWM0 Channel 5 modulete with UART0_TXD. 0110: Reserved. 0111: Reserved. 1000: Reserved. 1001: Reserved. 1010: Reserved. 1011: Reserved. 1100: Reserved. 1101: Reserved. 1110: Reserved. 1111: Reserved. Note: This bis is valid while MODEN (SYS_MODCTL[0]) is set to 1. 4 4 read-write PDID SYS_PDID Part Device Identification Number Register 0x0 -1 read-only n 0x0 0x0 PDID Part Device Identification Number (Read Only) This register reflects device part number code. Software can read this register to identify which device is used. 0 32 read-only PLCTL SYS_PLCTL Power Level Control Register 0x1F8 -1 read-write n 0x0 0x0 LVSPRD LDO Voltage Scaling Period(Write Protect) The LVSPRD value is the period of each LDO voltage rising step. 24 8 read-write LVSSTEP LDO Voltage Scaling Step(Write Protect) The LVSSTEP value is LDO voltage rising step. 16 5 read-write PLSEL Power Level Select(Write Protect) These bits indicate the status of power level. Note: Refer to section 6.2.5 for Power Modes and Power Level Transition. 0 2 read-write 0 Power level is PL0 #00 1 Power level is PL1 #01 PLSTS SYS_PLSTS Power Level Status Register 0x1FC -1 read-only n 0x0 0x0 PLCBUSY Power Level Change Busy Bit (Read Only) This bit is set by hardware when power level is changing. After power level change is completed, this bit will be cleared automatically by hardware. 0 1 read-only 0 Core voltage change is completed #0 1 Core voltage change is ongoing #1 PLSTATUS Power Level Status (Read Only) This bit indicates the status of power level. 8 2 read-only 0 Power level is PL0 #00 1 Power level is PL1 #01 PORDISAN SYS_PORDISAN Analog POR Disable Control Register 0x1EC -1 read-write n 0x0 0x0 POROFFAN Power-on Reset Enable Bit (Write Protect) After powered on, user can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field. The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 16 read-write REGLCTL SYS_REGLCTL Register Lock Control Register 0x100 -1 read-write n 0x0 0x0 REGLCTL Register Lock Control Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. REGLCTL[0] Register Lock Control Disable Index (Read Only) 0 8 read-write 0 Write-protection Enabled for writing protected registers. Any write to the protected register is ignored 0 1 Write-protection Disabled for writing protected registers 1 RSTSTS SYS_RSTSTS System Reset Status Register 0x4 -1 read-write n 0x0 0x0 BODRF BOD Reset Flag The BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 4 1 read-write 0 No reset from BOD #0 1 The BOD had issued the reset signal to reset the system #1 CPULKRF CPU Lockup Reset Flag Note 1: Write 1 to clear this bit to 0. Note 2: When CPU lockup happened under ICE is connected, this flag will set to 1 but chip will not reset. 8 1 read-write 0 No reset from CPU lockup happened #0 1 The Cortex-M4 lockup happened and chip is reset #1 CPURF CPU Reset Flag The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC). Note: Write 1 to clear this bit to 0. 7 1 read-write 0 No reset from CPU #0 1 The Cortex-M4 Core and FMC are reset by software setting CPURST to 1 #1 HRESETRF HRESET Reset Flag The HRESET reset flag is set by the 'Reset Signal' from the HRESET. Note: Write 1 to clear this bit to 0. 6 1 read-write 0 No reset from HRESET #0 1 Reset from HRESET #1 LVRF LVR Reset Flag The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 3 1 read-write 0 No reset from LVR #0 1 LVR controller had issued the reset signal to reset the system #1 PINRF NRESET Pin Reset Flag The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 1 1 read-write 0 No reset from nRESET pin #0 1 Pin nRESET had issued the reset signal to reset the system #1 PORF POR Reset Flag The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 0 1 read-write 0 No reset from POR or CHIPRST #0 1 Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system #1 SYSRF System Reset Flag The system reset flag is set by the 'Reset Signal' from the Cortex-M4 Core to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 5 1 read-write 0 No reset from Cortex-M4 #0 1 The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core #1 WDTRF WDT Reset Flag The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. Note 1: Write 1 to clear this bit to 0. Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. 2 1 read-write 0 No reset from watchdog timer or window watchdog timer #0 1 The watchdog timer or window watchdog timer had issued the reset signal to reset the system #1 SRAM_BISTCTL SYS_SRAM_BISTCTL System SRAM BIST Test Control Register 0xD0 -1 read-write n 0x0 0x0 CRBIST CACHE BIST Enable Bit (Write Protect) This bit enables BIST test for CACHE RAM Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 system CACHE BIST Disabled #0 1 system CACHE BIST Enabled #1 PDMABIST PDMA BIST Enable Bit (Write Protect) This bit enables BIST test for PDMA RAM Note: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 system PDMA BIST Disabled #0 1 system PDMA BIST Enabled #1 SRBIST0 SRAM Bank0 BIST Enable Bit (Write Protect) This bit enables BIST test for SRAM bank0. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 system SRAM bank0 BIST Disabled #0 1 system SRAM bank0 BIST Enabled #1 SRBIST1 SRAM Bank1 BIST Enable Bit (Write Protect) This bit enables BIST test for SRAM bank1. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 system SRAM bank1 BIST Disabled #0 1 system SRAM bank1 BIST Enabled #1 SRAM_BISTSTS SYS_SRAM_BISTSTS System SRAM BIST Test Status Register 0xD4 -1 read-only n 0x0 0x0 CRBEND CACHE SRAM BIST Test Finish 18 1 read-only 0 System CACHE RAM BIST is active #0 1 System CACHE RAM BIST test finish #1 CRBISTEF CACHE SRAM BIST Fail Flag 2 1 read-only 0 System CACHE RAM BIST test pass #0 1 System CACHE RAM BIST test fail #1 PDMABEF PDMA SRAM BIST Fail Flag 7 1 read-only 0 PDMA SRAM BIST test pass #0 1 PDMA SRAM BIST test fail #1 PDMABEND PDMA SRAM BIST Test Finish 23 1 read-only 0 PDMA SRAM BIST is active #0 1 PDMA SRAM BIST test finish #1 SRBEND0 1st SRAM BIST Test Finish 16 1 read-only 0 1st system SRAM BIST active #0 1 1st system SRAM BIST finish #1 SRBEND1 2nd SRAM BIST Test Finish 17 1 read-only 0 2nd system SRAM BIST is active #0 1 2nd system SRAM BIST finish #1 SRBISTEF0 1st System SRAM BIST Fail Flag 0 1 read-only 0 1st system SRAM BIST test pass #0 1 1st system SRAM BIST test fail #1 SRBISTEF1 2nd System SRAM BIST Fail Flag 1 1 read-only 0 2nd system SRAM BIST test pass #0 1 2nd system SRAM BIST test fail #1 SRAM_ERRADDR SYS_SRAM_ERRADDR System SRAM Parity Check Error Address Register 0xC8 -1 read-only n 0x0 0x0 ERRADDR System SRAM Parity Error Address This register shows system SRAM parity error byte address. 0 32 read-only SRAM_INTCTL SYS_SRAM_INTCTL System SRAM Interrupt Enable Control Register 0xC0 -1 read-write n 0x0 0x0 PERRIEN SRAM Parity Check Error Interrupt Enable Bit 0 1 read-write 0 SRAM parity check error interrupt Disabled #0 1 SRAM parity check error interrupt Enabled #1 SRAM_STATUS SYS_SRAM_STATUS System SRAM Parity Error Status Register 0xC4 -1 read-write n 0x0 0x0 PERRIF SRAM Parity Check Error Flag This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0. 0 1 read-write 0 No System SRAM parity error #0 1 System SRAM parity error occur #1 VREFCTL SYS_VREFCTL VREF Control Register 0x28 -1 read-write n 0x0 0x0 PRELOADEN Pre-load Function Enable Bit (Write Protect) This bit should be enabled and keep during Tstable when VREFCTL(SYS_VREFCTL[4:0]) change setting(except set to 00000). Tstable depends on different situations has different requirement, please refer to Datasheet. Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 VREF Pre-load function Disabled. (Default) #0 1 VREF Pre-load function Enabled #1 VBGFEN Chip Internal Voltage Band-gap Force Enable Bit(Write Only) Note: If user want to read the value of this bit, please read bit[25]. 24 1 write-only 0 Chip internal voltage band-gap controlled by ADC/ACMP if source selected #0 1 Chip internal voltage band-gap force enable #1 VREFCTL VREF Control Bits (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 5 read-write 0 VREF is from external pin #00000 2 VREF is from internal reference voltage 2.048V #00010 6 VREF is from internal reference voltage 2.56V #00110 10 VREF is from internal reference voltage 3.072V #01010 14 VREF is from internal reference voltage 4.096V #01110 TMR01 TIMER Register Map TIMER 0x0 0x0 0x20 registers n 0x100 0x20 registers n 0x140 0x38 registers n 0x40 0x38 registers n TIMER0_CAP TIMER0_CAP Timer0 Capture Data Register 0x10 -1 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register When CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. Note: User must consider the Timer will keep register TIMERx_CAP unchanged and drop the new capture value, if the CPU does not clear the CAPIF status. 0 24 read-only TIMER0_CMP TIMER0_CMP Timer0 Comparator Register 0x4 -1 read-write n 0x0 0x0 CMPDAT Timer Comparator Value CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. 0 24 read-write TIMER0_CNT TIMER0_CNT Timer0 Data Register 0xC -1 read-write n 0x0 0x0 CNT Timer Data Register Read operation. Read this register to get CNT value. For example: If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value. If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value. Write operation. Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. 0 24 read-write RSTACT Timer Data Register Reset Active (Read Only) This bit indicates if the counter reset operation active. When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically. 31 1 read-only 0 Reset operation is done #0 1 Reset operation triggered by writing TIMERx_CNT is in progress #1 TIMER0_CTL TIMER0_CTL Timer0 Control Register 0x0 -1 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only) This bit indicates the 24-bit up counter status. Note: This bit may active when CNT 0 transition to CNT 1. 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CAPSRC Capture Pin Source Selection 22 1 read-write 0 Capture Function source is from TMx_EXT (x= 0~3) pin #0 1 Capture Function source is from internal ACMP output signal , internal clock (LIRC, HIRC), or external clock (HXT, LXT) #1 CNTEN Timer Counting Enable Bit Note 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 EXTCNTEN Event Counter Mode Enable Bit This bit is for external counting pin function enabled. Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. 24 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 FUNCSEL Function Selection Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. 15 1 read-write 0 Timer controller is used as timer function #0 1 Timer controller is used as PWM function #1 ICEDEBUG ICE Debug Mode Acknowledge Disable Bit (Write Protect) TIMER counter will keep going no matter CPU is held by ICE or not. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN Timer Interrupt Enable Bit Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer time-out interrupt Disabled #0 1 Timer time-out interrupt Enabled #1 INTRGEN Inter-timer Trigger Mode Enable Bit Setting this bit will enable the inter-timer trigger capture function. The Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function. Note: For Timer1/3, this bit is ineffective and the read back value is always 0. 19 1 read-write 0 Inter-Timer Trigger Capture mode Disabled #0 1 Inter-Timer Trigger Capture mode Enabled #1 OPMODE Timer Counting Mode Select 27 2 read-write 0 The timer controller is operated in One-shot mode #00 1 The timer controller is operated in Periodic mode #01 2 The timer controller is operated in Toggle-output mode #10 3 The timer controller is operated in Continuous Counting mode #11 PERIOSEL Periodic Mode Behavior Selection Enable Bit If updated CMPDAT value CNT, CNT will be reset to default value. 20 1 read-write 0 The behavior selection in periodic mode is Disabled #0 1 The behavior selection in periodic mode is Enabled #1 PSC Prescale Counter Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. 0 8 read-write TGLPINSEL Toggle-output Pin Select 21 1 read-write 0 Toggle mode output to TMx (Timer Event Counter Pin) #0 1 Toggle mode output to TMx_EXT (Timer External Capture Pin) #1 WKEN Wake-up Function Enable Bit If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. 23 1 read-write 0 Wake-up function Disabled if timer interrupt signal generated #0 1 Wake-up function Enabled if timer interrupt signal generated #1 TIMER0_EINTSTS TIMER0_EINTSTS Timer0 External Interrupt Status Register 0x18 -1 read-write n 0x0 0x0 CAPIF Timer External Capture Interrupt Flag This bit indicates the timer external capture interrupt flag status. Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 0 1 read-write 0 TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt did not occur #0 1 TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt occurred #1 TIMER0_EXTCTL TIMER0_EXTCTL Timer0 External Control Register 0x14 -1 read-write n 0x0 0x0 CAPDBEN Timer External Capture Pin De-bounce Enable Bit Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. 6 1 read-write 0 TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled #0 1 TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled #1 CAPDIVSCL Timer Capture Source Divider Scale This bits indicate the divide scale for capture source divider Note: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source. 28 4 read-write 0 Capture source/1 #0000 1 Capture source/2 #0001 2 Capture source/4 #0010 3 Capture source/8 #0011 4 Capture source/16 #0100 5 Capture source/32 #0101 6 Capture source/64 #0110 7 Capture source/128 #0111 8 Capture source/256 #1000 CAPEDGE Timer External Capture Pin Edge Detect When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. Note: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL (TIMERx_EXTCTL[10:8]) to select capture source. 12 3 read-write 0 Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin #000 1 Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin #001 2 Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer #010 3 Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer #011 6 First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin #110 7 First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin #111 CAPEN Timer Capture Enable Bit This bit enables the capture input function. Note: When CAPEN is 1, user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source. 3 1 read-write 0 Capture source Disabled #0 1 Capture source Enabled #1 CAPFUNCS Capture Function Selection 4 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 CAPIEN Timer External Capture Interrupt Enable Bit 5 1 read-write 0 TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Disabled #0 1 TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Enabled #1 CNTDBEN Timer Counter Pin De-bounce Enable Bit Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. 7 1 read-write 0 TMx (x= 0~3) pin de-bounce Disabled #0 1 TMx (x= 0~3) pin de-bounce Enabled #1 CNTPHASE Timer External Count Phase 0 1 read-write 0 A falling edge of external counting pin will be counted #0 1 A rising edge of external counting pin will be counted #1 INTERCAPSEL Internal Capture Source Select Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. 8 3 read-write 0 Capture Function source is from internal ACMP0 output signal #000 1 Capture Function source is from internal ACMP1 output signal #001 2 Capture Function source is from HXT #010 3 Capture Function source is from LXT #011 4 Capture Function source is from HIRC #100 5 Capture Function source is from LIRC #101 6 Reserved. #110 7 Reserved. #111 TIMER0_INTSTS TIMER0_INTSTS Timer0 Interrupt Status Register 0x8 -1 read-write n 0x0 0x0 TIF Timer Interrupt Flag This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. Note: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT value matches the CMPDAT value #1 TWKF Timer Wake-up Flag This bit indicates the interrupt wake-up flag status of timer. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated #1 TIMER0_PWMCLKPSC TIMER0_PWMCLKPSC Timer0 PWM Counter Clock Pre-scale Register 0x44 -1 read-write n 0x0 0x0 CLKPSC PWM Counter Clock Pre-scale The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0, then there is no scaling in PWM counter clock source. 0 8 read-write TIMER0_PWMCMPBUF TIMER0_PWMCMPBUF Timer0 PWM Comparator Buffer Register 0x74 -1 read-only n 0x0 0x0 CMPBUF PWM Comparator Buffer Register (Read Only) Used as CMP active register. 0 16 read-only TIMER0_PWMCMPDAT TIMER0_PWMCMPDAT Timer0 PWM Comparator Register 0x50 -1 read-write n 0x0 0x0 CMP PWM Comparator Register PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger EADC, PDMA, and DAC start convert. 0 16 read-write TIMER0_PWMCNT TIMER0_PWMCNT Timer0 PWM Counter Register 0x54 -1 read-only n 0x0 0x0 CNT PWM Counter Value Register (Read Only) User can monitor CNT to know the current counter value in 16-bit period counter. 0 16 read-only TIMER0_PWMCNTCLR TIMER0_PWMCNTCLR Timer0 PWM Clear Counter Register 0x48 -1 read-write n 0x0 0x0 CNTCLR Clear PWM Counter Control Bit It is automatically cleared by hardware. Note: Timer peripheral clock source should be set as PCLK to ensure that this bit can be automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x0000 in up count type #1 TIMER0_PWMCTL TIMER0_PWMCTL Timer0 PWM Control Register 0x40 -1 read-write n 0x0 0x0 CNTEN PWM Counter Enable Bit 0 1 read-write 0 PWM counter and clock prescale Stop Running #0 1 PWM counter and clock prescale Start Running #1 CNTMODE PWM Counter Mode 3 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 DBGHALT ICE Debug Mode Counter Halt (Write Protect) If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. Note: This bit is write protected. Refer to SYS_REGLCTL control register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable Bit (Write Protect) PWM output pin will keep output no matter ICE debug mode acknowledged or not. Note: This bit is write protected. Refer to SYS_REGLCTL control register. 31 1 read-write 0 ICE debug mode acknowledgement effects PWM output #0 1 ICE debug mode acknowledgement disabled #1 PWMINTWKEN PWM Interrupt Wake-up Enable Bit If PWM interrupt occurs when chip is in Power-down mode, PWMINTWKEN can determine whether chip wake-up occurs or not. 12 1 read-write 0 PWM interrupt wake-up Disabled #0 1 PWM interrupt wake-up Enabled #1 TIMER0_PWMINTEN0 TIMER0_PWMINTEN0 Timer0 PWM Interrupt Enable Register 0 0x60 -1 read-write n 0x0 0x0 CMPUIEN PWM Compare Up Count Interrupt Enable Bit 2 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 PIEN PWM Period Point Interrupt Enable Bit 1 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 TIMER0_PWMINTSTS0 TIMER0_PWMINTSTS0 Timer0 PWM Interrupt Status Register 0 0x64 -1 read-write n 0x0 0x0 CMPUIF PWM Compare Up Count Interrupt Flag This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP. Note 1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type. Note 2: This bit is cleared by writing 1 to it. 2 1 read-write PIF PWM Period Point Interrupt Flag This bit is set by hardware when TIMERx_PWM counter reaches PERIOD. Note: This bit is cleared by writing 1 to it. 1 1 read-write TIMER0_PWMPBUF TIMER0_PWMPBUF Timer0 PWM Period Buffer Register 0x70 -1 read-only n 0x0 0x0 PBUF PWM Period Buffer Register (Read Only) Used as PERIOD active register. 0 16 read-only TIMER0_PWMPERIOD TIMER0_PWMPERIOD Timer0 PWM Period Register 0x4C -1 read-write n 0x0 0x0 PERIOD PWM Period Register In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. In up count type: 0 16 read-write TIMER0_PWMPOCTL TIMER0_PWMPOCTL Timer0 PWM Pin Output Control Register 0x5C -1 read-write n 0x0 0x0 POEN PWMx Output Pin Enable Bit Note: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin. 0 1 read-write 0 PWMx_OUT pin at tri-state mode #0 1 PWMx_OUT pin in output mode #1 POSEL PWM Output Pin Select 8 1 read-write 0 PWMx_OUT pin is TMx #0 1 PWMx_OUT pin is TMx_EXT #1 TIMER0_PWMPOLCTL TIMER0_PWMPOLCTL Timer0 PWM Pin Output Polar Control Register 0x58 -1 read-write n 0x0 0x0 PINV PWMx Output Pin Polar Control Bit The bit is used to control polarity state of PWMx_OUT pin. Note: Sets POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin. 0 1 read-write 0 PWMx_OUT pin polar inverse Disabled #0 1 PWMx_OUT polar inverse Enabled #1 TIMER0_PWMSTATUS TIMER0_PWMSTATUS Timer0 PWM Status Register 0x6C -1 read-write n 0x0 0x0 CNTMAXF PWM Counter Equal to 0xFFFF Flag Note: This bit is cleared by writing 1 to it. 0 1 read-write 0 The PWM counter value never reached its maximum value 0xFFFF #0 1 The PWM counter value has reached its maximum value #1 DACTRGF Trigger DAC Start Conversion Flag Note: This bit is cleared by writing 1 to it. 17 1 read-write 0 PWM counter event trigger DAC start conversion has not occurred #0 1 PWM counter event trigger DAC start conversion has occurred #1 EADCTRGF Trigger EADC Start Conversion Flag Note: This bit is cleared by writing 1 to it. 16 1 read-write 0 PWM counter event trigger EADC start conversion is not occurred #0 1 PWM counter event trigger EADC start conversion has occurred #1 PDMATRGF Trigger PDMA Start Conversion Flag Note: This bit is cleared by writing 1 to it. 18 1 read-write 0 PWM counter event trigger PDMA start conversion has not occurred #0 1 PWM counter event trigger PDMA start conversion has occurred #1 PWMINTWKF PWM Interrupt Wake-up Flag Note: This bit is cleared by writing 1 to it. 8 1 read-write 0 PWM interrupt wake-up has not occurred #0 1 PWM interrupt wake-up has occurred #1 TIMER0_PWMTRGCTL TIMER0_PWMTRGCTL Timer0 PWM Trigger Control Register 0x68 -1 read-write n 0x0 0x0 PWMTRGDAC PWM Counter Event Trigger DAC Conversion Enable Bit If this bit is set to 1, PWM can trigger DAC conversion. Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source. 8 1 read-write 0 PWM trigger DAC Disabled #0 1 PWM trigger DAC Enabled #1 PWMTRGEADC PWM Counter Event Trigger EADC Conversion Enable Bit Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source. 7 1 read-write 0 PWM counter event trigger EADC conversion Disabled #0 1 PWM counter event trigger EADC conversion Enabled #1 PWMTRGPDMA PWM Counter Event Trigger PDMA Conversion Enable Bit If this bit is set to 1, PWM can trigger PDMA conversion. Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source. 9 1 read-write 0 PWM trigger PDMA Disabled #0 1 PWM trigger PDMA Enabled #1 TRGSEL PWM Counter Event Source Select to Trigger Conversion 0 2 read-write 0 Trigger conversion at period point (PIF) #00 1 Trigger conversion at compare up count point (CMPUIF) #01 2 Trigger conversion at period or compare up count point (PIF or CMPUIF) #10 3 Reserved. #11 TIMER0_TRGCTL TIMER0_TRGCTL Timer0 Trigger Control Register 0x1C -1 read-write n 0x0 0x0 TRGDAC Trigger DAC Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC. 3 1 read-write 0 Timer interrupt trigger DAC Disabled #0 1 Timer interrupt trigger DAC Enabled #1 TRGEADC Trigger EADC Enable Bit If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. 2 1 read-write 0 Timer interrupt trigger EADC Disabled #0 1 Timer interrupt trigger EADC Enabled #1 TRGPDMA Trigger PDMA Enable Bit If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. 4 1 read-write 0 Timer interrupt trigger PDMA Disabled #0 1 Timer interrupt trigger PDMA Enabled #1 TRGPWM Trigger EPWM/BPWM Enable Bit If this bit is set to 1, each timer time-out event or capture event can be as EPWM/BPWM counter clock source. 1 1 read-write 0 Timer interrupt trigger EPWM/BPWM Disabled #0 1 Timer interrupt trigger EPWM/BPWM Enabled #1 TRGSSEL Trigger Source Select Bit This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal. 0 1 read-write 0 Time-out interrupt signal is used to internal trigger EPWM, PDMA, DAC, and EADC #0 1 Capture interrupt signal is used to internal trigger EPWM, PDMA, DAC, and EADC #1 TIMER1_CAP TIMER1_CAP Timer1 Capture Data Register 0x110 -1 read-write n 0x0 0x0 TIMER1_CMP TIMER1_CMP Timer1 Comparator Register 0x104 -1 read-write n 0x0 0x0 TIMER1_CNT TIMER1_CNT Timer1 Data Register 0x10C -1 read-write n 0x0 0x0 TIMER1_CTL TIMER1_CTL Timer1 Control Register 0x100 -1 read-write n 0x0 0x0 TIMER1_EINTSTS TIMER1_EINTSTS Timer1 External Interrupt Status Register 0x118 -1 read-write n 0x0 0x0 TIMER1_EXTCTL TIMER1_EXTCTL Timer1 External Control Register 0x114 -1 read-write n 0x0 0x0 TIMER1_INTSTS TIMER1_INTSTS Timer1 Interrupt Status Register 0x108 -1 read-write n 0x0 0x0 TIMER1_PWMCLKPSC TIMER1_PWMCLKPSC Timer1 PWM Counter Clock Pre-scale Register 0x144 -1 read-write n 0x0 0x0 TIMER1_PWMCMPBUF TIMER1_PWMCMPBUF Timer1 PWM Comparator Buffer Register 0x174 -1 read-write n 0x0 0x0 TIMER1_PWMCMPDAT TIMER1_PWMCMPDAT Timer1 PWM Comparator Register 0x150 -1 read-write n 0x0 0x0 TIMER1_PWMCNT TIMER1_PWMCNT Timer1 PWM Counter Register 0x154 -1 read-write n 0x0 0x0 TIMER1_PWMCNTCLR TIMER1_PWMCNTCLR Timer1 PWM Clear Counter Register 0x148 -1 read-write n 0x0 0x0 TIMER1_PWMCTL TIMER1_PWMCTL Timer1 PWM Control Register 0x140 -1 read-write n 0x0 0x0 TIMER1_PWMINTEN0 TIMER1_PWMINTEN0 Timer1 PWM Interrupt Enable Register 0 0x160 -1 read-write n 0x0 0x0 TIMER1_PWMINTSTS0 TIMER1_PWMINTSTS0 Timer1 PWM Interrupt Status Register 0 0x164 -1 read-write n 0x0 0x0 TIMER1_PWMPBUF TIMER1_PWMPBUF Timer1 PWM Period Buffer Register 0x170 -1 read-write n 0x0 0x0 TIMER1_PWMPERIOD TIMER1_PWMPERIOD Timer1 PWM Period Register 0x14C -1 read-write n 0x0 0x0 TIMER1_PWMPOCTL TIMER1_PWMPOCTL Timer1 PWM Pin Output Control Register 0x15C -1 read-write n 0x0 0x0 TIMER1_PWMPOLCTL TIMER1_PWMPOLCTL Timer1 PWM Pin Output Polar Control Register 0x158 -1 read-write n 0x0 0x0 TIMER1_PWMSTATUS TIMER1_PWMSTATUS Timer1 PWM Status Register 0x16C -1 read-write n 0x0 0x0 TIMER1_PWMTRGCTL TIMER1_PWMTRGCTL Timer1 PWM Trigger Control Register 0x168 -1 read-write n 0x0 0x0 TIMER1_TRGCTL TIMER1_TRGCTL Timer1 Trigger Control Register 0x11C -1 read-write n 0x0 0x0 TMR23 TIMER Register Map TIMER 0x0 0x0 0x20 registers n 0x100 0x20 registers n 0x140 0x38 registers n 0x40 0x38 registers n TIMER2_CAP TIMER2_CAP Timer2 Capture Data Register 0x10 -1 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register When CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. Note: User must consider the Timer will keep register TIMERx_CAP unchanged and drop the new capture value, if the CPU does not clear the CAPIF status. 0 24 read-only TIMER2_CMP TIMER2_CMP Timer2 Comparator Register 0x4 -1 read-write n 0x0 0x0 CMPDAT Timer Comparator Value CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. 0 24 read-write TIMER2_CNT TIMER2_CNT Timer2 Data Register 0xC -1 read-write n 0x0 0x0 CNT Timer Data Register Read operation. Read this register to get CNT value. For example: If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value. If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value. Write operation. Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. 0 24 read-write RSTACT Timer Data Register Reset Active (Read Only) This bit indicates if the counter reset operation active. When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically. 31 1 read-only 0 Reset operation is done #0 1 Reset operation triggered by writing TIMERx_CNT is in progress #1 TIMER2_CTL TIMER2_CTL Timer2 Control Register 0x0 -1 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only) This bit indicates the 24-bit up counter status. Note: This bit may active when CNT 0 transition to CNT 1. 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CAPSRC Capture Pin Source Selection 22 1 read-write 0 Capture Function source is from TMx_EXT (x= 0~3) pin #0 1 Capture Function source is from internal ACMP output signal , internal clock (LIRC, HIRC), or external clock (HXT, LXT) #1 CNTEN Timer Counting Enable Bit Note 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 EXTCNTEN Event Counter Mode Enable Bit This bit is for external counting pin function enabled. Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. 24 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 FUNCSEL Function Selection Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. 15 1 read-write 0 Timer controller is used as timer function #0 1 Timer controller is used as PWM function #1 ICEDEBUG ICE Debug Mode Acknowledge Disable Bit (Write Protect) TIMER counter will keep going no matter CPU is held by ICE or not. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN Timer Interrupt Enable Bit Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer time-out interrupt Disabled #0 1 Timer time-out interrupt Enabled #1 INTRGEN Inter-timer Trigger Mode Enable Bit Setting this bit will enable the inter-timer trigger capture function. The Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function. Note: For Timer1/3, this bit is ineffective and the read back value is always 0. 19 1 read-write 0 Inter-Timer Trigger Capture mode Disabled #0 1 Inter-Timer Trigger Capture mode Enabled #1 OPMODE Timer Counting Mode Select 27 2 read-write 0 The timer controller is operated in One-shot mode #00 1 The timer controller is operated in Periodic mode #01 2 The timer controller is operated in Toggle-output mode #10 3 The timer controller is operated in Continuous Counting mode #11 PERIOSEL Periodic Mode Behavior Selection Enable Bit If updated CMPDAT value CNT, CNT will be reset to default value. 20 1 read-write 0 The behavior selection in periodic mode is Disabled #0 1 The behavior selection in periodic mode is Enabled #1 PSC Prescale Counter Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. 0 8 read-write TGLPINSEL Toggle-output Pin Select 21 1 read-write 0 Toggle mode output to TMx (Timer Event Counter Pin) #0 1 Toggle mode output to TMx_EXT (Timer External Capture Pin) #1 WKEN Wake-up Function Enable Bit If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. 23 1 read-write 0 Wake-up function Disabled if timer interrupt signal generated #0 1 Wake-up function Enabled if timer interrupt signal generated #1 TIMER2_EINTSTS TIMER2_EINTSTS Timer2 External Interrupt Status Register 0x18 -1 read-write n 0x0 0x0 CAPIF Timer External Capture Interrupt Flag This bit indicates the timer external capture interrupt flag status. Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 0 1 read-write 0 TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt did not occur #0 1 TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt occurred #1 TIMER2_EXTCTL TIMER2_EXTCTL Timer2 External Control Register 0x14 -1 read-write n 0x0 0x0 CAPDBEN Timer External Capture Pin De-bounce Enable Bit Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. 6 1 read-write 0 TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled #0 1 TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled #1 CAPDIVSCL Timer Capture Source Divider Scale This bits indicate the divide scale for capture source divider Note: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source. 28 4 read-write 0 Capture source/1 #0000 1 Capture source/2 #0001 2 Capture source/4 #0010 3 Capture source/8 #0011 4 Capture source/16 #0100 5 Capture source/32 #0101 6 Capture source/64 #0110 7 Capture source/128 #0111 8 Capture source/256 #1000 CAPEDGE Timer External Capture Pin Edge Detect When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. Note: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL (TIMERx_EXTCTL[10:8]) to select capture source. 12 3 read-write 0 Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin #000 1 Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin #001 2 Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer #010 3 Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer #011 6 First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin #110 7 First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin #111 CAPEN Timer Capture Enable Bit This bit enables the capture input function. Note: When CAPEN is 1, user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source. 3 1 read-write 0 Capture source Disabled #0 1 Capture source Enabled #1 CAPFUNCS Capture Function Selection 4 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 CAPIEN Timer External Capture Interrupt Enable Bit 5 1 read-write 0 TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Disabled #0 1 TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Enabled #1 CNTDBEN Timer Counter Pin De-bounce Enable Bit Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. 7 1 read-write 0 TMx (x= 0~3) pin de-bounce Disabled #0 1 TMx (x= 0~3) pin de-bounce Enabled #1 CNTPHASE Timer External Count Phase 0 1 read-write 0 A falling edge of external counting pin will be counted #0 1 A rising edge of external counting pin will be counted #1 INTERCAPSEL Internal Capture Source Select Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. 8 3 read-write 0 Capture Function source is from internal ACMP0 output signal #000 1 Capture Function source is from internal ACMP1 output signal #001 2 Capture Function source is from HXT #010 3 Capture Function source is from LXT #011 4 Capture Function source is from HIRC #100 5 Capture Function source is from LIRC #101 6 Reserved. #110 7 Reserved. #111 TIMER2_INTSTS TIMER2_INTSTS Timer2 Interrupt Status Register 0x8 -1 read-write n 0x0 0x0 TIF Timer Interrupt Flag This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. Note: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT value matches the CMPDAT value #1 TWKF Timer Wake-up Flag This bit indicates the interrupt wake-up flag status of timer. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated #1 TIMER2_PWMCLKPSC TIMER2_PWMCLKPSC Timer2 PWM Counter Clock Pre-scale Register 0x44 -1 read-write n 0x0 0x0 CLKPSC PWM Counter Clock Pre-scale The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0, then there is no scaling in PWM counter clock source. 0 8 read-write TIMER2_PWMCMPBUF TIMER2_PWMCMPBUF Timer2 PWM Comparator Buffer Register 0x74 -1 read-only n 0x0 0x0 CMPBUF PWM Comparator Buffer Register (Read Only) Used as CMP active register. 0 16 read-only TIMER2_PWMCMPDAT TIMER2_PWMCMPDAT Timer2 PWM Comparator Register 0x50 -1 read-write n 0x0 0x0 CMP PWM Comparator Register PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger EADC, PDMA, and DAC start convert. 0 16 read-write TIMER2_PWMCNT TIMER2_PWMCNT Timer2 PWM Counter Register 0x54 -1 read-only n 0x0 0x0 CNT PWM Counter Value Register (Read Only) User can monitor CNT to know the current counter value in 16-bit period counter. 0 16 read-only TIMER2_PWMCNTCLR TIMER2_PWMCNTCLR Timer2 PWM Clear Counter Register 0x48 -1 read-write n 0x0 0x0 CNTCLR Clear PWM Counter Control Bit It is automatically cleared by hardware. Note: Timer peripheral clock source should be set as PCLK to ensure that this bit can be automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x0000 in up count type #1 TIMER2_PWMCTL TIMER2_PWMCTL Timer2 PWM Control Register 0x40 -1 read-write n 0x0 0x0 CNTEN PWM Counter Enable Bit 0 1 read-write 0 PWM counter and clock prescale Stop Running #0 1 PWM counter and clock prescale Start Running #1 CNTMODE PWM Counter Mode 3 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 DBGHALT ICE Debug Mode Counter Halt (Write Protect) If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. Note: This bit is write protected. Refer to SYS_REGLCTL control register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable Bit (Write Protect) PWM output pin will keep output no matter ICE debug mode acknowledged or not. Note: This bit is write protected. Refer to SYS_REGLCTL control register. 31 1 read-write 0 ICE debug mode acknowledgement effects PWM output #0 1 ICE debug mode acknowledgement disabled #1 PWMINTWKEN PWM Interrupt Wake-up Enable Bit If PWM interrupt occurs when chip is in Power-down mode, PWMINTWKEN can determine whether chip wake-up occurs or not. 12 1 read-write 0 PWM interrupt wake-up Disabled #0 1 PWM interrupt wake-up Enabled #1 TIMER2_PWMINTEN0 TIMER2_PWMINTEN0 Timer2 PWM Interrupt Enable Register 0 0x60 -1 read-write n 0x0 0x0 CMPUIEN PWM Compare Up Count Interrupt Enable Bit 2 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 PIEN PWM Period Point Interrupt Enable Bit 1 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 TIMER2_PWMINTSTS0 TIMER2_PWMINTSTS0 Timer2 PWM Interrupt Status Register 0 0x64 -1 read-write n 0x0 0x0 CMPUIF PWM Compare Up Count Interrupt Flag This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP. Note 1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type. Note 2: This bit is cleared by writing 1 to it. 2 1 read-write PIF PWM Period Point Interrupt Flag This bit is set by hardware when TIMERx_PWM counter reaches PERIOD. Note: This bit is cleared by writing 1 to it. 1 1 read-write TIMER2_PWMPBUF TIMER2_PWMPBUF Timer2 PWM Period Buffer Register 0x70 -1 read-only n 0x0 0x0 PBUF PWM Period Buffer Register (Read Only) Used as PERIOD active register. 0 16 read-only TIMER2_PWMPERIOD TIMER2_PWMPERIOD Timer2 PWM Period Register 0x4C -1 read-write n 0x0 0x0 PERIOD PWM Period Register In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. In up count type: 0 16 read-write TIMER2_PWMPOCTL TIMER2_PWMPOCTL Timer2 PWM Pin Output Control Register 0x5C -1 read-write n 0x0 0x0 POEN PWMx Output Pin Enable Bit Note: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin. 0 1 read-write 0 PWMx_OUT pin at tri-state mode #0 1 PWMx_OUT pin in output mode #1 POSEL PWM Output Pin Select 8 1 read-write 0 PWMx_OUT pin is TMx #0 1 PWMx_OUT pin is TMx_EXT #1 TIMER2_PWMPOLCTL TIMER2_PWMPOLCTL Timer2 PWM Pin Output Polar Control Register 0x58 -1 read-write n 0x0 0x0 PINV PWMx Output Pin Polar Control Bit The bit is used to control polarity state of PWMx_OUT pin. Note: Sets POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin. 0 1 read-write 0 PWMx_OUT pin polar inverse Disabled #0 1 PWMx_OUT polar inverse Enabled #1 TIMER2_PWMSTATUS TIMER2_PWMSTATUS Timer2 PWM Status Register 0x6C -1 read-write n 0x0 0x0 CNTMAXF PWM Counter Equal to 0xFFFF Flag Note: This bit is cleared by writing 1 to it. 0 1 read-write 0 The PWM counter value never reached its maximum value 0xFFFF #0 1 The PWM counter value has reached its maximum value #1 DACTRGF Trigger DAC Start Conversion Flag Note: This bit is cleared by writing 1 to it. 17 1 read-write 0 PWM counter event trigger DAC start conversion has not occurred #0 1 PWM counter event trigger DAC start conversion has occurred #1 EADCTRGF Trigger EADC Start Conversion Flag Note: This bit is cleared by writing 1 to it. 16 1 read-write 0 PWM counter event trigger EADC start conversion is not occurred #0 1 PWM counter event trigger EADC start conversion has occurred #1 PDMATRGF Trigger PDMA Start Conversion Flag Note: This bit is cleared by writing 1 to it. 18 1 read-write 0 PWM counter event trigger PDMA start conversion has not occurred #0 1 PWM counter event trigger PDMA start conversion has occurred #1 PWMINTWKF PWM Interrupt Wake-up Flag Note: This bit is cleared by writing 1 to it. 8 1 read-write 0 PWM interrupt wake-up has not occurred #0 1 PWM interrupt wake-up has occurred #1 TIMER2_PWMTRGCTL TIMER2_PWMTRGCTL Timer2 PWM Trigger Control Register 0x68 -1 read-write n 0x0 0x0 PWMTRGDAC PWM Counter Event Trigger DAC Conversion Enable Bit If this bit is set to 1, PWM can trigger DAC conversion. Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source. 8 1 read-write 0 PWM trigger DAC Disabled #0 1 PWM trigger DAC Enabled #1 PWMTRGEADC PWM Counter Event Trigger EADC Conversion Enable Bit Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source. 7 1 read-write 0 PWM counter event trigger EADC conversion Disabled #0 1 PWM counter event trigger EADC conversion Enabled #1 PWMTRGPDMA PWM Counter Event Trigger PDMA Conversion Enable Bit If this bit is set to 1, PWM can trigger PDMA conversion. Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source. 9 1 read-write 0 PWM trigger PDMA Disabled #0 1 PWM trigger PDMA Enabled #1 TRGSEL PWM Counter Event Source Select to Trigger Conversion 0 2 read-write 0 Trigger conversion at period point (PIF) #00 1 Trigger conversion at compare up count point (CMPUIF) #01 2 Trigger conversion at period or compare up count point (PIF or CMPUIF) #10 3 Reserved. #11 TIMER2_TRGCTL TIMER2_TRGCTL Timer2 Trigger Control Register 0x1C -1 read-write n 0x0 0x0 TRGDAC Trigger DAC Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC. 3 1 read-write 0 Timer interrupt trigger DAC Disabled #0 1 Timer interrupt trigger DAC Enabled #1 TRGEADC Trigger EADC Enable Bit If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. 2 1 read-write 0 Timer interrupt trigger EADC Disabled #0 1 Timer interrupt trigger EADC Enabled #1 TRGPDMA Trigger PDMA Enable Bit If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. 4 1 read-write 0 Timer interrupt trigger PDMA Disabled #0 1 Timer interrupt trigger PDMA Enabled #1 TRGPWM Trigger EPWM/BPWM Enable Bit If this bit is set to 1, each timer time-out event or capture event can be as EPWM/BPWM counter clock source. 1 1 read-write 0 Timer interrupt trigger EPWM/BPWM Disabled #0 1 Timer interrupt trigger EPWM/BPWM Enabled #1 TRGSSEL Trigger Source Select Bit This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal. 0 1 read-write 0 Time-out interrupt signal is used to internal trigger EPWM, PDMA, DAC, and EADC #0 1 Capture interrupt signal is used to internal trigger EPWM, PDMA, DAC, and EADC #1 TIMER3_CAP TIMER3_CAP Timer3 Capture Data Register 0x110 -1 read-write n 0x0 0x0 TIMER3_CMP TIMER3_CMP Timer3 Comparator Register 0x104 -1 read-write n 0x0 0x0 TIMER3_CNT TIMER3_CNT Timer3 Data Register 0x10C -1 read-write n 0x0 0x0 TIMER3_CTL TIMER3_CTL Timer3 Control Register 0x100 -1 read-write n 0x0 0x0 TIMER3_EINTSTS TIMER3_EINTSTS Timer3 External Interrupt Status Register 0x118 -1 read-write n 0x0 0x0 TIMER3_EXTCTL TIMER3_EXTCTL Timer3 External Control Register 0x114 -1 read-write n 0x0 0x0 TIMER3_INTSTS TIMER3_INTSTS Timer3 Interrupt Status Register 0x108 -1 read-write n 0x0 0x0 TIMER3_PWMCLKPSC TIMER3_PWMCLKPSC Timer3 PWM Counter Clock Pre-scale Register 0x144 -1 read-write n 0x0 0x0 TIMER3_PWMCMPBUF TIMER3_PWMCMPBUF Timer3 PWM Comparator Buffer Register 0x174 -1 read-write n 0x0 0x0 TIMER3_PWMCMPDAT TIMER3_PWMCMPDAT Timer3 PWM Comparator Register 0x150 -1 read-write n 0x0 0x0 TIMER3_PWMCNT TIMER3_PWMCNT Timer3 PWM Counter Register 0x154 -1 read-write n 0x0 0x0 TIMER3_PWMCNTCLR TIMER3_PWMCNTCLR Timer3 PWM Clear Counter Register 0x148 -1 read-write n 0x0 0x0 TIMER3_PWMCTL TIMER3_PWMCTL Timer3 PWM Control Register 0x140 -1 read-write n 0x0 0x0 TIMER3_PWMINTEN0 TIMER3_PWMINTEN0 Timer3 PWM Interrupt Enable Register 0 0x160 -1 read-write n 0x0 0x0 TIMER3_PWMINTSTS0 TIMER3_PWMINTSTS0 Timer3 PWM Interrupt Status Register 0 0x164 -1 read-write n 0x0 0x0 TIMER3_PWMPBUF TIMER3_PWMPBUF Timer3 PWM Period Buffer Register 0x170 -1 read-write n 0x0 0x0 TIMER3_PWMPERIOD TIMER3_PWMPERIOD Timer3 PWM Period Register 0x14C -1 read-write n 0x0 0x0 TIMER3_PWMPOCTL TIMER3_PWMPOCTL Timer3 PWM Pin Output Control Register 0x15C -1 read-write n 0x0 0x0 TIMER3_PWMPOLCTL TIMER3_PWMPOLCTL Timer3 PWM Pin Output Polar Control Register 0x158 -1 read-write n 0x0 0x0 TIMER3_PWMSTATUS TIMER3_PWMSTATUS Timer3 PWM Status Register 0x16C -1 read-write n 0x0 0x0 TIMER3_PWMTRGCTL TIMER3_PWMTRGCTL Timer3 PWM Trigger Control Register 0x168 -1 read-write n 0x0 0x0 TIMER3_TRGCTL TIMER3_TRGCTL Timer3 Trigger Control Register 0x11C -1 read-write n 0x0 0x0 UART0 UART Register Map UART 0x0 0x0 0x4C registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length Note : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from START bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from START bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from START bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from START bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit Note : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF (UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit This bit is used to enable RS-485 Address Detection mode. Note: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value This field contains the RS-485 address match values. Note: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length This field indicates a 4-bit LIN TX break field count. Note 1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit Note: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD) Note: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) Note: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0 This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.144. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1 This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.144. Note: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.144. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1 This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.144. 24 4 read-write UART_BRCOMP UART_BRCOMP UART Baud Rate Compensation Register 0x3C -1 read-write n 0x0 0x0 BRCOMP Baud Rate Compensation Patten These 9-bits are used to define the relative bit is compensated or not. BRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8]). 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 -1 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer Write Operation: By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read Operation: By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY PARITY Bit Receive/Transmit Buffer Write Operation: By writing to this bit, the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. Read Operation: If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the PARITY bit can be read by this bit. Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Incoming Data Wake-up Compensation Register 0x48 -1 read-write n 0x0 0x0 STCOMP START Bit Compensation Value These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode. Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Note: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit The receiver is disabled or not (set 1 to disable receiver). Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) to be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) to be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag This bit is set to logic '1' when auto-baud rate detect function is finished. Note: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. Note: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. Note 2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits). Note: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0). Note: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'. Note: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only) This bit initiate RX FIFO empty or not. Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only) This bit initiates RX FIFO full or not. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only) This bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag This bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only) This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one. The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only) This bit indicates TX FIFO empty or not. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only) This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only) This bit indicates TX FIFO full or not. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. Note: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only) This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only) This bit indicates TX and RX are active or inactive. Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 -1 read-write n 0x0 0x0 DGE Deglitch Enable Bit Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic. 6 1 read-write 0 Deglitch Disabled #0 1 Deglitch Enabled #1 FUNCSEL Function Select 0 3 read-write 0 UART function #000 1 LIN function #001 2 IrDA function #010 3 RS-485 function #011 4 UART Single-wire function #100 TXRXDIS TX and RX Disable Bit Setting this bit can disable TX and RX. Note: The TX and RX will not be disabled immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 -1 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit Note: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit This bit can enable or disable RX PDMA service. Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 SWBEIEN Single-wire Bit Error Detection Interrupt Enable Bit Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT (UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF (UART_INTSTS[16]) is set. Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART Single-wire mode. 16 1 read-write 0 Single-wire Bit Error Detect Inerrupt Disabled #0 1 Single-wire Bit Error Detect Inerrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only) This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only) This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared if both of RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF (UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF (UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF (UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag Note: This bit is cleared when SLVHDETF (UART_LINSTS[0]), BRKDETF (UART_LINSTS[8]), BITEF (UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF (UART_LINSTS[1]) all are cleared and software writing '1' to LINIF (UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only) This bit is set if LINIEN (UART_INTEN[8]) and LINIF (UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and MODEMIF (UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated. #1 RDAIF Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the RX FIFO equals the RFITL then the RDAIF (UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. Note: This bit is read only and will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL (UART_FIFO[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only) This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 SWBEIF Single-wire Bit Error Detection Interrupt Flag This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode. Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART Single-wire mode. Note 2: This bit can be cleared by writing '1' to it. 16 1 read-write 0 No single-wire bit error detection interrupt flag is generated #0 1 Single-wire bit error detection interrupt flag is generated #1 SWBEINT Single-wire Bit Error Detect Interrupt Indicator (Read Only) This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1. 24 1 read-only 0 No Single-wire Bit Error Detection Interrupt generated #0 1 Single-wire Bit Error Detection Interrupt generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only) This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. Note: This bit is read only and will be cleared when writing data into UART_DAT (TX FIFO is not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only) This bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-write 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF (UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only) This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF (UART_WKSTS[0]) is set to 1. Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only) This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINCTL UART_LINCTL UART LIN Control Register 0x34 -1 read-write n 0x0 0x0 BITERREN Bit Error Detect Enable Bit 12 1 read-write 0 Bit error detection function Disabled #0 1 Bit error detection function Enabled #1 BRKDETEN LIN Break Detection Enable Bit 10 1 read-write 0 LIN break detection Disabled #0 1 LIN break detection Enabled #1 BRKFL LIN Break Field Length This field indicates a 4-bit LIN TX break field count. Note 1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]). User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]). Note 2: This break field length is BRKFL + 1. 16 4 read-write BSL LIN Break/Sync Delimiter Length Note: This bit used for LIN master to sending header field. 20 2 read-write 0 The LIN break/sync delimiter length is 1-bit time #00 1 The LIN break/sync delimiter length is 2-bit time #01 2 The LIN break/sync delimiter length is 3-bit time #10 3 The LIN break/sync delimiter length is 4-bit time #11 HSEL LIN Header Select 22 2 read-write 0 The LIN header includes 'break field' #00 1 The LIN header includes 'break field' and 'sync field' #01 2 The LIN header includes 'break field', 'sync field' and 'frame ID field' #10 3 Reserved. #11 IDPEN LIN ID Parity Enable Bit 9 1 read-write 0 LIN frame ID parity Disabled #0 1 LIN frame ID parity Enabled #1 LINRXOFF LIN Receiver Disable Bit 11 1 read-write 0 LIN receiver Enabled #0 1 LIN receiver Disabled #1 MUTE LIN Mute Mode Enable Bit Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.14.5.10 (LIN slave mode). 4 1 read-write 0 LIN mute mode Disabled #0 1 LIN mute mode Enabled #1 PID LIN PID Bits If the parity generated by hardware, user fill ID0~ID5 (PID[29:24]), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field. Note 1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first). Note 2: This field can be used for LIN master mode or slave mode. 24 8 read-write SENDH LIN TX Send Header Enable Bit The LIN TX header can be 'break field' or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]). Note 1: This bit is shadow bit of LINTXEN (UART_ALTCTL[7]) user can read/write it by setting LINTXEN (UART_ALTCTL[7]) or SENDH (UART_LINCTL[8]). Note 2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 8 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 SLVAREN LIN Slave Automatic Resynchronization Mode Enable Bit Note 2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1). Note 3: The control and interactions of this field are explained in 6.14.5.10 (Slave mode with automatic resynchronization). 2 1 read-write 0 LIN automatic resynchronization Disabled #0 1 LIN automatic resynchronization Enabled #1 SLVDUEN LIN Slave Divider Update Method Enable Bit Note 2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) Note 3: The control and interactions of this field are explained in 6.14.5.10 (Slave mode with automatic resynchronization). 3 1 read-write 0 UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time) #0 1 UART_BAUD is updated at the next received character. User must set the bit before checksum reception #1 SLVEN LIN Slave Mode Enable Bit 0 1 read-write 0 LIN slave mode Disabled #0 1 LIN slave mode Enabled #1 SLVHDEN LIN Slave Header Detection Enable Bit 1 1 read-write 0 LIN slave header detection Disabled #0 1 LIN slave header detection Enabled #1 UART_LINE UART_LINE UART Line Control Register 0xC -1 read-write n 0x0 0x0 BCB Break Control Bit Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit Note: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE PARITY Bit Enable Bit Note: PARITY bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 PARITY bit generated Disabled #0 1 PARITY bit generated Enabled #1 PSS PARITY Bit Source Selection The PARITY bit can be selected to be generated and checked automatically or by software. Note 1: This bit has effect only when PBE (UART_LINE[3]) is set. Note 2: If PSS is 0, the PARITY bit is transmitted and checked automatically. If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (UART_DAT[8]) and the PARITY bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 PARITY bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 PARITY bit generated and checked by software #1 RXDINV RX Data Inverted Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection This field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_LINSTS UART_LINSTS UART LIN Status Register 0x38 -1 read-write n 0x0 0x0 BITEF Bit Error Detect Status Flag At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. 9 1 read-write 0 Bit error not detected #0 1 Bit error detected #1 BRKDETF LIN Break Detection Flag This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. 8 1 read-write 0 LIN break not detected #0 1 LIN break detected #1 SLVHDETF LIN Slave Header Detection Flag This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it. Note 3: When enable ID parity check IDPEN (UART_LINCTL[9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not. 0 1 read-write 0 LIN header not detected #0 1 LIN header detected (break + sync + frame ID) #1 SLVHEF LIN Slave Header Error Flag This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', 'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', 'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'. 1 1 read-write 0 LIN header error not detected #0 1 LIN header error detected #1 SLVIDPEF LIN Slave ID Parity Error Flag This bit is set by hardware when receipted frame ID parity is not correct. 2 1 read-write 0 No active #0 1 Receipted frame ID parity is not correct #1 SLVSYNCF LIN Slave Sync Field This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. Note 2: This bit can be cleared by writing 1 to it. Note 3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. 3 1 read-write 0 The current character is not at LIN sync state #0 1 The current character is at LIN sync state #1 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. Note 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. Note 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. Note 3: Single-wire mode supports this feature. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level This bit defines the active level state of nRTS pin output. Note 1: Refer to Figure 6.1413 and Figure 6.1414 for UART function mode. Note 2: Refer to Figure 6.1424 and Figure 6.1425 for RS-485 function mode. Note 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only) This bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level This bit defines the active level state of nCTS pin input. Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only) This bit mirror from nCTS pin input of voltage logic status. Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 -1 read-write n 0x0 0x0 DLY TX Delay Time Value This field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 -1 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit Note:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode. 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit Note:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit Note 1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. Note 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit Note 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode. Note 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 -1 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag This bit is set if chip wake-up from power-down state by nCTS wake-up. Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag This bit is set if chip wake-up from power-down state by data wake-up. Note 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up. Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out #1 UART1 UART Register Map UART 0x0 0x0 0x4C registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length Note : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from START bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from START bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from START bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from START bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit Note : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF (UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit This bit is used to enable RS-485 Address Detection mode. Note: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value This field contains the RS-485 address match values. Note: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length This field indicates a 4-bit LIN TX break field count. Note 1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit Note: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD) Note: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) Note: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0 This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.144. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1 This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.144. Note: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.144. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1 This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.144. 24 4 read-write UART_BRCOMP UART_BRCOMP UART Baud Rate Compensation Register 0x3C -1 read-write n 0x0 0x0 BRCOMP Baud Rate Compensation Patten These 9-bits are used to define the relative bit is compensated or not. BRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8]). 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 -1 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer Write Operation: By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read Operation: By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY PARITY Bit Receive/Transmit Buffer Write Operation: By writing to this bit, the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. Read Operation: If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the PARITY bit can be read by this bit. Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Incoming Data Wake-up Compensation Register 0x48 -1 read-write n 0x0 0x0 STCOMP START Bit Compensation Value These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode. Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Note: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit The receiver is disabled or not (set 1 to disable receiver). Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) to be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) to be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag This bit is set to logic '1' when auto-baud rate detect function is finished. Note: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. Note: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. Note 2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits). Note: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0). Note: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'. Note: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only) This bit initiate RX FIFO empty or not. Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only) This bit initiates RX FIFO full or not. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only) This bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag This bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only) This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one. The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only) This bit indicates TX FIFO empty or not. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only) This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only) This bit indicates TX FIFO full or not. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. Note: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only) This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only) This bit indicates TX and RX are active or inactive. Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 -1 read-write n 0x0 0x0 DGE Deglitch Enable Bit Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic. 6 1 read-write 0 Deglitch Disabled #0 1 Deglitch Enabled #1 FUNCSEL Function Select 0 3 read-write 0 UART function #000 1 LIN function #001 2 IrDA function #010 3 RS-485 function #011 4 UART Single-wire function #100 TXRXDIS TX and RX Disable Bit Setting this bit can disable TX and RX. Note: The TX and RX will not be disabled immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 -1 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit Note: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit This bit can enable or disable RX PDMA service. Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 SWBEIEN Single-wire Bit Error Detection Interrupt Enable Bit Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT (UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF (UART_INTSTS[16]) is set. Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART Single-wire mode. 16 1 read-write 0 Single-wire Bit Error Detect Inerrupt Disabled #0 1 Single-wire Bit Error Detect Inerrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only) This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only) This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared if both of RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF (UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF (UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF (UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag Note: This bit is cleared when SLVHDETF (UART_LINSTS[0]), BRKDETF (UART_LINSTS[8]), BITEF (UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF (UART_LINSTS[1]) all are cleared and software writing '1' to LINIF (UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only) This bit is set if LINIEN (UART_INTEN[8]) and LINIF (UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and MODEMIF (UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the RX FIFO equals the RFITL then the RDAIF (UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. Note: This bit is read only and will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL (UART_FIFO[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only) This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 SWBEIF Single-wire Bit Error Detection Interrupt Flag This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode. Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART Single-wire mode. Note 2: This bit can be cleared by writing '1' to it. 16 1 read-write 0 No single-wire bit error detection interrupt flag is generated #0 1 Single-wire bit error detection interrupt flag is generated #1 SWBEINT Single-wire Bit Error Detect Interrupt Indicator (Read Only) This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1. 24 1 read-only 0 No Single-wire Bit Error Detection Interrupt generated #0 1 Single-wire Bit Error Detection Interrupt generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only) This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. Note: This bit is read only and will be cleared when writing data into UART_DAT (TX FIFO is not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only) This bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-write 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF (UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only) This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF (UART_WKSTS[0]) is set to 1. Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only) This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINCTL UART_LINCTL UART LIN Control Register 0x34 -1 read-write n 0x0 0x0 BITERREN Bit Error Detect Enable Bit 12 1 read-write 0 Bit error detection function Disabled #0 1 Bit error detection function Enabled #1 BRKDETEN LIN Break Detection Enable Bit 10 1 read-write 0 LIN break detection Disabled #0 1 LIN break detection Enabled #1 BRKFL LIN Break Field Length This field indicates a 4-bit LIN TX break field count. Note 1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]). User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]). Note 2: This break field length is BRKFL + 1. 16 4 read-write BSL LIN Break/Sync Delimiter Length Note: This bit used for LIN master to sending header field. 20 2 read-write 0 The LIN break/sync delimiter length is 1-bit time #00 1 The LIN break/sync delimiter length is 2-bit time #01 2 The LIN break/sync delimiter length is 3-bit time #10 3 The LIN break/sync delimiter length is 4-bit time #11 HSEL LIN Header Select 22 2 read-write 0 The LIN header includes 'break field' #00 1 The LIN header includes 'break field' and 'sync field' #01 2 The LIN header includes 'break field', 'sync field' and 'frame ID field' #10 3 Reserved. #11 IDPEN LIN ID Parity Enable Bit 9 1 read-write 0 LIN frame ID parity Disabled #0 1 LIN frame ID parity Enabled #1 LINRXOFF LIN Receiver Disable Bit 11 1 read-write 0 LIN receiver Enabled #0 1 LIN receiver Disabled #1 MUTE LIN Mute Mode Enable Bit Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.14.5.10 (LIN slave mode). 4 1 read-write 0 LIN mute mode Disabled #0 1 LIN mute mode Enabled #1 PID LIN PID Bits If the parity generated by hardware, user fill ID0~ID5 (PID[29:24]), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field. Note 1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first). Note 2: This field can be used for LIN master mode or slave mode. 24 8 read-write SENDH LIN TX Send Header Enable Bit The LIN TX header can be 'break field' or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]). Note 1: This bit is shadow bit of LINTXEN (UART_ALTCTL[7]) user can read/write it by setting LINTXEN (UART_ALTCTL[7]) or SENDH (UART_LINCTL[8]). Note 2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 8 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 SLVAREN LIN Slave Automatic Resynchronization Mode Enable Bit Note 2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1). Note 3: The control and interactions of this field are explained in 6.14.5.10 (Slave mode with automatic resynchronization). 2 1 read-write 0 LIN automatic resynchronization Disabled #0 1 LIN automatic resynchronization Enabled #1 SLVDUEN LIN Slave Divider Update Method Enable Bit Note 2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) Note 3: The control and interactions of this field are explained in 6.14.5.10 (Slave mode with automatic resynchronization). 3 1 read-write 0 UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time) #0 1 UART_BAUD is updated at the next received character. User must set the bit before checksum reception #1 SLVEN LIN Slave Mode Enable Bit 0 1 read-write 0 LIN slave mode Disabled #0 1 LIN slave mode Enabled #1 SLVHDEN LIN Slave Header Detection Enable Bit 1 1 read-write 0 LIN slave header detection Disabled #0 1 LIN slave header detection Enabled #1 UART_LINE UART_LINE UART Line Control Register 0xC -1 read-write n 0x0 0x0 BCB Break Control Bit Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit Note: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE PARITY Bit Enable Bit Note: PARITY bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 PARITY bit generated Disabled #0 1 PARITY bit generated Enabled #1 PSS PARITY Bit Source Selection The PARITY bit can be selected to be generated and checked automatically or by software. Note 1: This bit has effect only when PBE (UART_LINE[3]) is set. Note 2: If PSS is 0, the PARITY bit is transmitted and checked automatically. If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (UART_DAT[8]) and the PARITY bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 PARITY bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 PARITY bit generated and checked by software #1 RXDINV RX Data Inverted Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection This field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_LINSTS UART_LINSTS UART LIN Status Register 0x38 -1 read-write n 0x0 0x0 BITEF Bit Error Detect Status Flag At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. 9 1 read-write 0 Bit error not detected #0 1 Bit error detected #1 BRKDETF LIN Break Detection Flag This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. 8 1 read-write 0 LIN break not detected #0 1 LIN break detected #1 SLVHDETF LIN Slave Header Detection Flag This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it. Note 3: When enable ID parity check IDPEN (UART_LINCTL[9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not. 0 1 read-write 0 LIN header not detected #0 1 LIN header detected (break + sync + frame ID) #1 SLVHEF LIN Slave Header Error Flag This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', 'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', 'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'. 1 1 read-write 0 LIN header error not detected #0 1 LIN header error detected #1 SLVIDPEF LIN Slave ID Parity Error Flag This bit is set by hardware when receipted frame ID parity is not correct. 2 1 read-write 0 No active #0 1 Receipted frame ID parity is not correct #1 SLVSYNCF LIN Slave Sync Field This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. Note 2: This bit can be cleared by writing 1 to it. Note 3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. 3 1 read-write 0 The current character is not at LIN sync state #0 1 The current character is at LIN sync state #1 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. Note 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. Note 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. Note 3: Single-wire mode supports this feature. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level This bit defines the active level state of nRTS pin output. Note 1: Refer to Figure 6.1413 and Figure 6.1414 for UART function mode. Note 2: Refer to Figure 6.1424 and Figure 6.1425 for RS-485 function mode. Note 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only) This bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level This bit defines the active level state of nCTS pin input. Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only) This bit mirror from nCTS pin input of voltage logic status. Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 -1 read-write n 0x0 0x0 DLY TX Delay Time Value This field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 -1 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit Note:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode. 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit Note:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit Note 1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. Note 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit Note 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode. Note 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 -1 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag This bit is set if chip wake-up from power-down state by nCTS wake-up. Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag This bit is set if chip wake-up from power-down state by data wake-up. Note 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up. Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out #1 UART2 UART Register Map UART 0x0 0x0 0x34 registers n 0x40 0xC registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length Note : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from START bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from START bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from START bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from START bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit Note : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF (UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit This bit is used to enable RS-485 Address Detection mode. Note: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value This field contains the RS-485 address match values. Note: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length This field indicates a 4-bit LIN TX break field count. Note 1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit Note: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD) Note: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) Note: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0 This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.144. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1 This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.144. Note: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.144. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1 This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.144. 24 4 read-write UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 -1 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer Write Operation: By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read Operation: By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY PARITY Bit Receive/Transmit Buffer Write Operation: By writing to this bit, the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. Read Operation: If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the PARITY bit can be read by this bit. Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Incoming Data Wake-up Compensation Register 0x48 -1 read-write n 0x0 0x0 STCOMP START Bit Compensation Value These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode. Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Note: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit The receiver is disabled or not (set 1 to disable receiver). Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) to be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) to be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag This bit is set to logic '1' when auto-baud rate detect function is finished. Note: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. Note: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. Note 2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits). Note: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0). Note: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'. Note: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only) This bit initiate RX FIFO empty or not. Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only) This bit initiates RX FIFO full or not. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only) This bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag This bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only) This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one. The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only) This bit indicates TX FIFO empty or not. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only) This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only) This bit indicates TX FIFO full or not. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. Note: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only) This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only) This bit indicates TX and RX are active or inactive. Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 -1 read-write n 0x0 0x0 DGE Deglitch Enable Bit Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic. 6 1 read-write 0 Deglitch Disabled #0 1 Deglitch Enabled #1 FUNCSEL Function Select 0 3 read-write 0 UART function #000 1 LIN function #001 2 IrDA function #010 3 RS-485 function #011 4 UART Single-wire function #100 TXRXDIS TX and RX Disable Bit Setting this bit can disable TX and RX. Note: The TX and RX will not be disabled immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 -1 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit Note: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit This bit can enable or disable RX PDMA service. Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 SWBEIEN Single-wire Bit Error Detection Interrupt Enable Bit Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT (UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF (UART_INTSTS[16]) is set. Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART Single-wire mode. 16 1 read-write 0 Single-wire Bit Error Detect Inerrupt Disabled #0 1 Single-wire Bit Error Detect Inerrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only) This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only) This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared if both of RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF (UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF (UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF (UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag Note: This bit is cleared when SLVHDETF (UART_LINSTS[0]), BRKDETF (UART_LINSTS[8]), BITEF (UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF (UART_LINSTS[1]) all are cleared and software writing '1' to LINIF (UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only) This bit is set if LINIEN (UART_INTEN[8]) and LINIF (UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and MODEMIF (UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the RX FIFO equals the RFITL then the RDAIF (UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. Note: This bit is read only and will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL (UART_FIFO[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only) This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 SWBEIF Single-wire Bit Error Detection Interrupt Flag This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode. Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART Single-wire mode. Note 2: This bit can be cleared by writing '1' to it. 16 1 read-write 0 No single-wire bit error detection interrupt flag is generated #0 1 Single-wire bit error detection interrupt flag is generated #1 SWBEINT Single-wire Bit Error Detect Interrupt Indicator (Read Only) This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1. 24 1 read-only 0 No Single-wire Bit Error Detection Interrupt generated #0 1 Single-wire Bit Error Detection Interrupt generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only) This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. Note: This bit is read only and will be cleared when writing data into UART_DAT (TX FIFO is not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only) This bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-write 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF (UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only) This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF (UART_WKSTS[0]) is set to 1. Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only) This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINE UART_LINE UART Line Control Register 0xC -1 read-write n 0x0 0x0 BCB Break Control Bit Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit Note: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE PARITY Bit Enable Bit Note: PARITY bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 PARITY bit generated Disabled #0 1 PARITY bit generated Enabled #1 PSS PARITY Bit Source Selection The PARITY bit can be selected to be generated and checked automatically or by software. Note 1: This bit has effect only when PBE (UART_LINE[3]) is set. Note 2: If PSS is 0, the PARITY bit is transmitted and checked automatically. If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (UART_DAT[8]) and the PARITY bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 PARITY bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 PARITY bit generated and checked by software #1 RXDINV RX Data Inverted Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection This field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. Note 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. Note 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. Note 3: Single-wire mode supports this feature. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level This bit defines the active level state of nRTS pin output. Note 1: Refer to Figure 6.1413 and Figure 6.1414 for UART function mode. Note 2: Refer to Figure 6.1424 and Figure 6.1425 for RS-485 function mode. Note 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only) This bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level This bit defines the active level state of nCTS pin input. Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only) This bit mirror from nCTS pin input of voltage logic status. Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 -1 read-write n 0x0 0x0 DLY TX Delay Time Value This field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 -1 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit Note:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode. 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit Note:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit Note 1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. Note 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit Note 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode. Note 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 -1 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag This bit is set if chip wake-up from power-down state by nCTS wake-up. Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag This bit is set if chip wake-up from power-down state by data wake-up. Note 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up. Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out #1 UART3 UART Register Map UART 0x0 0x0 0x34 registers n 0x40 0xC registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length Note : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from START bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from START bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from START bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from START bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit Note : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF (UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit This bit is used to enable RS-485 Address Detection mode. Note: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value This field contains the RS-485 address match values. Note: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length This field indicates a 4-bit LIN TX break field count. Note 1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit Note: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD) Note: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) Note: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0 This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.144. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1 This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.144. Note: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.144. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1 This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.144. 24 4 read-write UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 -1 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer Write Operation: By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read Operation: By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY PARITY Bit Receive/Transmit Buffer Write Operation: By writing to this bit, the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. Read Operation: If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the PARITY bit can be read by this bit. Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Incoming Data Wake-up Compensation Register 0x48 -1 read-write n 0x0 0x0 STCOMP START Bit Compensation Value These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode. Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Note: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit The receiver is disabled or not (set 1 to disable receiver). Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) to be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) to be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag This bit is set to logic '1' when auto-baud rate detect function is finished. Note: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. Note: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. Note 2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits). Note: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0). Note: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'. Note: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only) This bit initiate RX FIFO empty or not. Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only) This bit initiates RX FIFO full or not. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only) This bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag This bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only) This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one. The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only) This bit indicates TX FIFO empty or not. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only) This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only) This bit indicates TX FIFO full or not. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. Note: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only) This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only) This bit indicates TX and RX are active or inactive. Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 -1 read-write n 0x0 0x0 DGE Deglitch Enable Bit Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic. 6 1 read-write 0 Deglitch Disabled #0 1 Deglitch Enabled #1 FUNCSEL Function Select 0 3 read-write 0 UART function #000 1 LIN function #001 2 IrDA function #010 3 RS-485 function #011 4 UART Single-wire function #100 TXRXDIS TX and RX Disable Bit Setting this bit can disable TX and RX. Note: The TX and RX will not be disabled immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 -1 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit Note: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit This bit can enable or disable RX PDMA service. Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 SWBEIEN Single-wire Bit Error Detection Interrupt Enable Bit Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT (UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF (UART_INTSTS[16]) is set. Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART Single-wire mode. 16 1 read-write 0 Single-wire Bit Error Detect Inerrupt Disabled #0 1 Single-wire Bit Error Detect Inerrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only) This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only) This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared if both of RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF (UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF (UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF (UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag Note: This bit is cleared when SLVHDETF (UART_LINSTS[0]), BRKDETF (UART_LINSTS[8]), BITEF (UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF (UART_LINSTS[1]) all are cleared and software writing '1' to LINIF (UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only) This bit is set if LINIEN (UART_INTEN[8]) and LINIF (UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and MODEMIF (UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the RX FIFO equals the RFITL then the RDAIF (UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. Note: This bit is read only and will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL (UART_FIFO[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only) This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 SWBEIF Single-wire Bit Error Detection Interrupt Flag This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode. Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART Single-wire mode. Note 2: This bit can be cleared by writing '1' to it. 16 1 read-write 0 No single-wire bit error detection interrupt flag is generated #0 1 Single-wire bit error detection interrupt flag is generated #1 SWBEINT Single-wire Bit Error Detect Interrupt Indicator (Read Only) This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1. 24 1 read-only 0 No Single-wire Bit Error Detection Interrupt generated #0 1 Single-wire Bit Error Detection Interrupt generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only) This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. Note: This bit is read only and will be cleared when writing data into UART_DAT (TX FIFO is not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only) This bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-write 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF (UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only) This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF (UART_WKSTS[0]) is set to 1. Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only) This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINE UART_LINE UART Line Control Register 0xC -1 read-write n 0x0 0x0 BCB Break Control Bit Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit Note: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE PARITY Bit Enable Bit Note: PARITY bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 PARITY bit generated Disabled #0 1 PARITY bit generated Enabled #1 PSS PARITY Bit Source Selection The PARITY bit can be selected to be generated and checked automatically or by software. Note 1: This bit has effect only when PBE (UART_LINE[3]) is set. Note 2: If PSS is 0, the PARITY bit is transmitted and checked automatically. If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (UART_DAT[8]) and the PARITY bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 PARITY bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 PARITY bit generated and checked by software #1 RXDINV RX Data Inverted Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection This field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. Note 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. Note 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. Note 3: Single-wire mode supports this feature. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level This bit defines the active level state of nRTS pin output. Note 1: Refer to Figure 6.1413 and Figure 6.1414 for UART function mode. Note 2: Refer to Figure 6.1424 and Figure 6.1425 for RS-485 function mode. Note 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only) This bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level This bit defines the active level state of nCTS pin input. Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only) This bit mirror from nCTS pin input of voltage logic status. Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 -1 read-write n 0x0 0x0 DLY TX Delay Time Value This field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 -1 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit Note:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode. 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit Note:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit Note 1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. Note 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit Note 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode. Note 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 -1 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag This bit is set if chip wake-up from power-down state by nCTS wake-up. Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag This bit is set if chip wake-up from power-down state by data wake-up. Note 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up. Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out #1 UART4 UART Register Map UART 0x0 0x0 0x34 registers n 0x40 0xC registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length Note : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from START bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from START bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from START bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from START bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit Note : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF (UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit This bit is used to enable RS-485 Address Detection mode. Note: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value This field contains the RS-485 address match values. Note: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length This field indicates a 4-bit LIN TX break field count. Note 1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit Note: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD) Note: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) Note: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0 This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.144. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1 This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.144. Note: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.144. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1 This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.144. 24 4 read-write UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 -1 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer Write Operation: By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read Operation: By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY PARITY Bit Receive/Transmit Buffer Write Operation: By writing to this bit, the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. Read Operation: If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the PARITY bit can be read by this bit. Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Incoming Data Wake-up Compensation Register 0x48 -1 read-write n 0x0 0x0 STCOMP START Bit Compensation Value These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode. Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Note: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit The receiver is disabled or not (set 1 to disable receiver). Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) to be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) to be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag This bit is set to logic '1' when auto-baud rate detect function is finished. Note: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. Note: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. Note 2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits). Note: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0). Note: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'. Note: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only) This bit initiate RX FIFO empty or not. Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only) This bit initiates RX FIFO full or not. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only) This bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag This bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only) This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one. The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only) This bit indicates TX FIFO empty or not. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only) This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only) This bit indicates TX FIFO full or not. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. Note: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only) This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only) This bit indicates TX and RX are active or inactive. Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 -1 read-write n 0x0 0x0 DGE Deglitch Enable Bit Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic. 6 1 read-write 0 Deglitch Disabled #0 1 Deglitch Enabled #1 FUNCSEL Function Select 0 3 read-write 0 UART function #000 1 LIN function #001 2 IrDA function #010 3 RS-485 function #011 4 UART Single-wire function #100 TXRXDIS TX and RX Disable Bit Setting this bit can disable TX and RX. Note: The TX and RX will not be disabled immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 -1 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit Note: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit This bit can enable or disable RX PDMA service. Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 SWBEIEN Single-wire Bit Error Detection Interrupt Enable Bit Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT (UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF (UART_INTSTS[16]) is set. Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART Single-wire mode. 16 1 read-write 0 Single-wire Bit Error Detect Inerrupt Disabled #0 1 Single-wire Bit Error Detect Inerrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only) This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only) This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared if both of RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF (UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF (UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF (UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag Note: This bit is cleared when SLVHDETF (UART_LINSTS[0]), BRKDETF (UART_LINSTS[8]), BITEF (UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF (UART_LINSTS[1]) all are cleared and software writing '1' to LINIF (UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only) This bit is set if LINIEN (UART_INTEN[8]) and LINIF (UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and MODEMIF (UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the RX FIFO equals the RFITL then the RDAIF (UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. Note: This bit is read only and will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL (UART_FIFO[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only) This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 SWBEIF Single-wire Bit Error Detection Interrupt Flag This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode. Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART Single-wire mode. Note 2: This bit can be cleared by writing '1' to it. 16 1 read-write 0 No single-wire bit error detection interrupt flag is generated #0 1 Single-wire bit error detection interrupt flag is generated #1 SWBEINT Single-wire Bit Error Detect Interrupt Indicator (Read Only) This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1. 24 1 read-only 0 No Single-wire Bit Error Detection Interrupt generated #0 1 Single-wire Bit Error Detection Interrupt generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only) This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. Note: This bit is read only and will be cleared when writing data into UART_DAT (TX FIFO is not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only) This bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-write 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF (UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only) This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF (UART_WKSTS[0]) is set to 1. Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only) This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINE UART_LINE UART Line Control Register 0xC -1 read-write n 0x0 0x0 BCB Break Control Bit Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit Note: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE PARITY Bit Enable Bit Note: PARITY bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 PARITY bit generated Disabled #0 1 PARITY bit generated Enabled #1 PSS PARITY Bit Source Selection The PARITY bit can be selected to be generated and checked automatically or by software. Note 1: This bit has effect only when PBE (UART_LINE[3]) is set. Note 2: If PSS is 0, the PARITY bit is transmitted and checked automatically. If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (UART_DAT[8]) and the PARITY bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 PARITY bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 PARITY bit generated and checked by software #1 RXDINV RX Data Inverted Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection This field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. Note 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. Note 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. Note 3: Single-wire mode supports this feature. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level This bit defines the active level state of nRTS pin output. Note 1: Refer to Figure 6.1413 and Figure 6.1414 for UART function mode. Note 2: Refer to Figure 6.1424 and Figure 6.1425 for RS-485 function mode. Note 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only) This bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level This bit defines the active level state of nCTS pin input. Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only) This bit mirror from nCTS pin input of voltage logic status. Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 -1 read-write n 0x0 0x0 DLY TX Delay Time Value This field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 -1 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit Note:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode. 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit Note:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit Note 1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. Note 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit Note 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode. Note 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 -1 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag This bit is set if chip wake-up from power-down state by nCTS wake-up. Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag This bit is set if chip wake-up from power-down state by data wake-up. Note 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up. Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out #1 UART5 UART Register Map UART 0x0 0x0 0x34 registers n 0x40 0xC registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length Note : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from START bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from START bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from START bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from START bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit Note : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF (UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit This bit is used to enable RS-485 Address Detection mode. Note: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value This field contains the RS-485 address match values. Note: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length This field indicates a 4-bit LIN TX break field count. Note 1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit Note: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD) Note: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) Note: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0 This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.144. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1 This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.144. Note: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.144. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1 This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.144. 24 4 read-write UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 -1 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer Write Operation: By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read Operation: By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY PARITY Bit Receive/Transmit Buffer Write Operation: By writing to this bit, the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. Read Operation: If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the PARITY bit can be read by this bit. Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Incoming Data Wake-up Compensation Register 0x48 -1 read-write n 0x0 0x0 STCOMP START Bit Compensation Value These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode. Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Note: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit The receiver is disabled or not (set 1 to disable receiver). Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) to be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) to be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag This bit is set to logic '1' when auto-baud rate detect function is finished. Note: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. Note: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. Note 2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits). Note: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0). Note: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'. Note: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only) This bit initiate RX FIFO empty or not. Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only) This bit initiates RX FIFO full or not. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only) This bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag This bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only) This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one. The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only) This bit indicates TX FIFO empty or not. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only) This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only) This bit indicates TX FIFO full or not. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. Note: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only) This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only) This bit indicates TX and RX are active or inactive. Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 -1 read-write n 0x0 0x0 DGE Deglitch Enable Bit Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic. 6 1 read-write 0 Deglitch Disabled #0 1 Deglitch Enabled #1 FUNCSEL Function Select 0 3 read-write 0 UART function #000 1 LIN function #001 2 IrDA function #010 3 RS-485 function #011 4 UART Single-wire function #100 TXRXDIS TX and RX Disable Bit Setting this bit can disable TX and RX. Note: The TX and RX will not be disabled immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 -1 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit Note: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit This bit can enable or disable RX PDMA service. Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 SWBEIEN Single-wire Bit Error Detection Interrupt Enable Bit Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT (UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF (UART_INTSTS[16]) is set. Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART Single-wire mode. 16 1 read-write 0 Single-wire Bit Error Detect Inerrupt Disabled #0 1 Single-wire Bit Error Detect Inerrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only) This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only) This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared if both of RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF (UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF (UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF (UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag Note: This bit is cleared when SLVHDETF (UART_LINSTS[0]), BRKDETF (UART_LINSTS[8]), BITEF (UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF (UART_LINSTS[1]) all are cleared and software writing '1' to LINIF (UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only) This bit is set if LINIEN (UART_INTEN[8]) and LINIF (UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and MODEMIF (UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the RX FIFO equals the RFITL then the RDAIF (UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. Note: This bit is read only and will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL (UART_FIFO[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only) This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 SWBEIF Single-wire Bit Error Detection Interrupt Flag This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode. Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART Single-wire mode. Note 2: This bit can be cleared by writing '1' to it. 16 1 read-write 0 No single-wire bit error detection interrupt flag is generated #0 1 Single-wire bit error detection interrupt flag is generated #1 SWBEINT Single-wire Bit Error Detect Interrupt Indicator (Read Only) This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1. 24 1 read-only 0 No Single-wire Bit Error Detection Interrupt generated #0 1 Single-wire Bit Error Detection Interrupt generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only) This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. Note: This bit is read only and will be cleared when writing data into UART_DAT (TX FIFO is not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only) This bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-write 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF (UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only) This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF (UART_WKSTS[0]) is set to 1. Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only) This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINE UART_LINE UART Line Control Register 0xC -1 read-write n 0x0 0x0 BCB Break Control Bit Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit Note: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE PARITY Bit Enable Bit Note: PARITY bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 PARITY bit generated Disabled #0 1 PARITY bit generated Enabled #1 PSS PARITY Bit Source Selection The PARITY bit can be selected to be generated and checked automatically or by software. Note 1: This bit has effect only when PBE (UART_LINE[3]) is set. Note 2: If PSS is 0, the PARITY bit is transmitted and checked automatically. If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (UART_DAT[8]) and the PARITY bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 PARITY bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 PARITY bit generated and checked by software #1 RXDINV RX Data Inverted Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is set as UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection This field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. Note 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. Note 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. Note 3: Single-wire mode supports this feature. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level This bit defines the active level state of nRTS pin output. Note 1: Refer to Figure 6.1413 and Figure 6.1414 for UART function mode. Note 2: Refer to Figure 6.1424 and Figure 6.1425 for RS-485 function mode. Note 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only) This bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level This bit defines the active level state of nCTS pin input. Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then wait for TXRXACT (UART_FIFOSTS[31]) to be cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1. Note: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only) This bit mirror from nCTS pin input of voltage logic status. Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 -1 read-write n 0x0 0x0 DLY TX Delay Time Value This field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 -1 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit Note:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode. 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit Note:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit Note 1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. Note 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit Note 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode. Note 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 -1 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag This bit is set if chip wake-up from power-down state by nCTS wake-up. Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag This bit is set if chip wake-up from power-down state by data wake-up. Note 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up. Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'. Note 2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out #1 WDT WDT Register Map WDT 0x0 0x0 0xC registers n ALTCTL WDT_ALTCTL WDT Alternative Control Register 0x4 -1 read-write n 0x0 0x0 RSTDSEL WDT Reset Delay Selection (Write Protect) When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened. User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period. Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: This register will be reset to 0 if WDT time-out reset happened. 0 2 read-write 0 WDT Reset Delay Period is 1026 * WDT_CLK #00 1 WDT Reset Delay Period is 130 * WDT_CLK #01 2 WDT Reset Delay Period is 18 * WDT_CLK #10 3 WDT Reset Delay Period is 3 * WDT_CLK #11 CTL WDT_CTL WDT Control Register 0x0 -1 read-write n 0x0 0x0 ICEDEBUG ICE Debug Mode Acknowledge Disable Bit (Write Protect) WDT up counter will keep going no matter CPU is held by ICE or not. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement affects WDT counting #0 1 ICE debug mode acknowledgement Disabled #1 IF WDT Time-out Interrupt Flag This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval Note: This bit is cleared by writing 1 to it. 3 1 read-write 0 WDT time-out interrupt did not occur #0 1 WDT time-out interrupt occurred #1 INTEN WDT Time-out Interrupt Enable Bit (Write Protect) If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 WDT time-out interrupt Disabled #0 1 WDT time-out interrupt Enabled #1 RSTCNT Reset WDT Up Counter (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: This bit will be automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Reset the internal 20-bit WDT up counter value #1 RSTEN WDT Time-out Reset Enable Bit (Write Protect) Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 WDT time-out reset function Disabled #0 1 WDT time-out reset function Enabled #1 RSTF WDT Time-out Reset Flag This bit indicates the system has been reset by WDT time-out reset or not. Note: This bit is cleared by writing 1 to it. 2 1 read-write 0 WDT time-out reset did not occur #0 1 WDT time-out reset occurred #1 SYNC WDT Enable Control SYNC Flag Indicator (Read Only) If user executes enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not. Note: Performing enable or disable WDTEN bit needs 2 * WDT_CLK period to become active. 30 1 read-only 0 Set WDTEN bit is completed #0 1 Set WDTEN bit is synchronizing and not become active yet #1 TOUTSEL WDT Time-out Interval Selection (Write Protect) These three bits select the time-out interval period for the WDT. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 8 4 read-write 0 24 * WDT_CLK #0000 1 26 * WDT_CLK #0001 2 28 * WDT_CLK #0010 3 210 * WDT_CLK #0011 4 212 * WDT_CLK #0100 5 214 * WDT_CLK #0101 6 216 * WDT_CLK #0110 7 218 * WDT_CLK #0111 8 220 * WDT_CLK #1000 WDTEN WDT Enable Bit (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111, this bit is forced as 1 and user cannot change this bit to 0. 7 1 read-write 0 WDT Disabled (This action will reset the internal up counter value) #0 1 WDT Enabled #1 WKEN WDT Time-out Wake-up Function Control (Write Protect) If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Chip can be woken up by WDT time-out interrupt signal generated only if WDT clock source is selected to 38.4 kHz internal low speed RC oscillator (LIRC) or LXT. 4 1 read-write 0 Wake-up trigger event Disabled if WDT time-out interrupt signal generated #0 1 Wake-up trigger event Enabled if WDT time-out interrupt signal generated #1 WKF WDT Time-out Wake-up Flag (Write Protect) This bit indicates the interrupt wake-up flag status of WDT Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: This bit is cleared by writing 1 to it. 5 1 read-write 0 WDT does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated #1 RSTCNT WDT_RSTCNT WDT Reset Counter Register 0x8 -1 write-only n 0x0 0x0 RSTCNT WDT Reset Counter Register Writing 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0. Note 1: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active. Note 2: RSTCNT (WDT_CTL[0]) bit is a write protected bit. RSTCNT (WDT_RSTCNT[31:0]) bits are not write protected. 0 32 write-only WWDT WWDT Register Map WWDT 0x0 0x0 0x10 registers n CNT WWDT_CNT WWDT Counter Value Register 0xC -1 read-only n 0x0 0x0 CNTDAT WWDT Counter Value CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. 0 6 read-only CTL WWDT_CTL WWDT Control Register 0x4 -1 read-write n 0x0 0x0 CMPDAT WWDT Window Compare Set this register to adjust the valid reload window. Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately. 16 6 read-write ICEDEBUG ICE Debug Mode Acknowledge Disable Bit Note: WWDT down counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects WWDT counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN WWDT Interrupt Enable Bit If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU. 1 1 read-write 0 WWDT counter compare match interrupt Disabled #0 1 WWDT counter compare match interrupt Enabled #1 PSCSEL WWDT Counter Prescale Period Selection 8 4 read-write 0 Pre-scale is 1 Max time-out period is 1 * 64 * WWDT_CLK #0000 1 Pre-scale is 2 Max time-out period is 2 * 64 * WWDT_CLK #0001 2 Pre-scale is 4 Max time-out period is 4 * 64 * WWDT_CLK #0010 3 Pre-scale is 8 Max time-out period is 8 * 64 * WWDT_CLK #0011 4 Pre-scale is 16 Max time-out period is 16 * 64 * WWDT_CLK #0100 5 Pre-scale is 32 Max time-out period is 32 * 64 * WWDT_CLK #0101 6 Pre-scale is 64 Max time-out period is 64 * 64 * WWDT_CLK #0110 7 Pre-scale is 128 Max time-out period is 128 * 64 * WWDT_CLK #0111 8 Pre-scale is 192 Max time-out period is 192 * 64 * WWDT_CLK #1000 9 Pre-scale is 256 Max time-out period is 256 * 64 * WWDT_CLK #1001 10 Pre-scale is 384 Max time-out period is 384 * 64 * WWDT_CLK #1010 11 Pre-scale is 512 Max time-out period is 512 * 64 * WWDT_CLK #1011 12 Pre-scale is 768 Max time-out period is 768 * 64 * WWDT_CLK #1100 13 Pre-scale is 1024 Max time-out period is 1024 * 64 * WWDT_CLK #1101 14 Pre-scale is 1536 Max time-out period is 1536 * 64 * WWDT_CLK #1110 15 Pre-scale is 2048 Max time-out period is 2048 * 64 * WWDT_CLK #1111 WWDTEN WWDT Enable Bit 0 1 read-write 0 WWDT counter is stopped #0 1 WWDT counter starts counting #1 RLDCNT WWDT_RLDCNT WWDT Reload Counter Register 0x0 -1 write-only n 0x0 0x0 RLDCNT WWDT Reload Counter Register Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]). If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated immediately. 0 32 write-only STATUS WWDT_STATUS WWDT Status Register 0x8 -1 read-write n 0x0 0x0 WWDTIF WWDT Compare Match Interrupt Flag This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]). Note: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 WWDT counter value matches CMPDAT #1 WWDTRF WWDT Timer-out Reset Flag This bit indicates the system has been reset by WWDT time-out reset or not. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 WWDT time-out reset did not occur #0 1 WWDT time-out reset occurred #1