nuvoTon
MINI51DE_v1
2024.04.28
MINI51DE_v1 SVD file
8
32
ACMP
ACMP Register Map
ACMP
0x0
0x0
0x10
registers
n
CR0
ACMP_CR0
Analog Comparator 0 Control Register
0x0
read-write
n
0x0
0x0
ACMPEN
Analog Comparator 0 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after this bit is set.
0
1
read-write
0
Analog Comparator 0 Disabled
#0
1
Analog Comparator 1 Enabled
#1
ACMPIE
Analog Comparator 0 Interrupt Enable Control\n
1
1
read-write
0
Interrupt function Disabled
#0
1
Interrupt function Enabled
#1
CPP0SEL
Analog Comparator 0 Positive Input Selection\n
29
2
read-write
0
CPP0 is from P1.5 pin
#00
1
CPP0 is from P1.0 pin
#01
2
CPP0 is from P1.2 pin
#10
3
CPP0 is from P1.3 pin
#11
FALLING
Analog Comparator 0 Falling Edge Trigger Enable Control\nNote: The bit is only effective while analog comparator 0 triggers PWM or Timer.
9
1
read-write
0
Analog comparator 0 falling edge trigger Disabled
#0
1
Analog comparator 0 falling edge trigger PWM or Timer Enabled
#1
HYSEN
Analog Comparator 0 Hysteresis Enable Control\n
2
1
read-write
0
Hysteresis function Disabled
#0
1
Hysteresis function Enabled
#1
NEGSEL
Analog Comparator 0 Negative Input Selection\n
4
1
read-write
0
The source of the negative comparator input is from CPN0 pin
#0
1
The source of the negative comparator input is from internal band-gap voltage or comparator reference voltage
#1
RISING
Analog Comparator 0 Rising Edge Trigger Enable Control\nNote: The bit is only effective while analog comparator 0 triggers PWM or Timer.
8
1
read-write
0
Analog comparator 0 rising edge trigger Disabled
#0
1
Analog comparator 0 rising edge trigger PWM or Timer Enabled
#1
CR1
ACMP_CR1
Analog Comparator 1 Control Register
0x4
read-write
n
0x0
0x0
ACMPEN
Analog Comparator 1 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after this bit is set.
0
1
read-write
0
Analog Comparator 1 Disabled
#0
1
Analog Comparator 1 Enabled
#1
ACMPIE
Analog Comparator 1 Interrupt Enable Control\n
1
1
read-write
0
Interrupt function Disabled
#0
1
Interrupt function Enabled
#1
CPP1SEL
Analog Comparator 1 Positive Input Selection\n
29
2
read-write
0
CPP1 is from P3.1 pin
#00
1
CPP1 is from P3.2 pin
#01
2
CPP1 is from P3.4 pin
#10
3
CPP1 is from P3.5 pin
#11
FALLING
Analog Comparator 1 Falling Edge Trigger Enable Control\nNote: The bit is only effective while analog comparator 1 triggers PWM or Timer.
9
1
read-write
0
Analog comparator 1 falling edge trigger Disabled
#0
1
Analog comparator 1 falling edge trigger PWM or Timer Enabled
#1
HYSEN
Analog Comparator 1 Hysteresis Enable Control\n
2
1
read-write
0
Hysteresis function Disabled
#0
1
Hysteresis function Enabled
#1
NEGSEL
Analog Comparator 1 Negative Input Selection\n
4
1
read-write
0
The source of the negative comparator input is from CPN1 pin
#0
1
The source of the negative comparator input is from internal band-gap voltage or comparator reference voltage
#1
RISING
Analog Comparator 1 Rising Edge Trigger Enable Control\nNote: The bit is only effective while analog comparator 1 triggers PWM or Timer.
8
1
read-write
0
Analog comparator 1 rising edge trigger Disabled
#0
1
Analog comparator 1 rising edge trigger PWM or Timer Enabled
#1
RVCR
ACMP_RVCR
Analog Comparator Reference Voltage Control Register
0xC
read-write
n
0x0
0x0
CRVS
Comparator Reference Voltage Setting\n
0
4
read-write
OUT_SEL
CRV Module Output Selection\n
7
1
read-write
0
Band-gap voltage
#0
1
Internal comparator reference voltage
#1
SR01
ACMP_SR01
Analog Comparator 0/1 Status Register
0x8
read-write
n
0x0
0x0
ACMPF0
Analog Comparator 0 Flag\nNote: Software can write 1 to clear this bit to 0.
0
1
read-write
0
Analog comparator 0 output does not change
#0
1
Analog comparator 0 output changed
#1
ACMPF1
Analog Comparator 1 Flag\nNote: Software can write 1 to clear this bit to 0.
1
1
read-write
0
Analog comparator 1 output does not change
#0
1
Analog comparator 1 output changed
#1
ACMPO0
Analog Comparator 0 Output\n
2
1
read-write
0
Analog comparator 0 outputs 0
#0
1
Analog comparator 0 outputs 1
#1
ACMPO1
Analog Comparator 1 Output\n
3
1
read-write
0
Analog comparator 1 outputs 0
#0
1
Analog comparator 1 outputs 1
#1
ADC
ADC Register Map
ADC
0x0
0x0
0x4
registers
n
0x20
0x14
registers
n
0x44
0x8
registers
n
ADCHER
ADCHER
ADC Channel Enable Control Register
0x24
read-write
n
0x0
0x0
CHEN0
Analog Input Channel 0 Enable Control\nNote: If software enables more than one channel, the channel with the smallest number will be selected and the other enabled channels will be ignored.
0
1
read-write
0
Channel 0 Disabled
#0
1
Channel 0 Enabled
#1
CHEN1
Analog Input Channel 1 Enable Control\n
1
1
read-write
0
Channel 1 Disabled
#0
1
Channel 1 Enabled
#1
CHEN2
Analog Input Channel 2 Enable Control\n
2
1
read-write
0
Channel 2 Disabled
#0
1
Channel 2 Enabled
#1
CHEN3
Analog Input Channel 3 Enable Control\n
3
1
read-write
0
Channel 3 Disabled
#0
1
Channel 3 Enabled
#1
CHEN4
Analog Input Channel 4 Enable Control\n
4
1
read-write
0
Channel 4 Disabled
#0
1
Channel 4 Enabled
#1
CHEN5
Analog Input Channel 5 Enable Control\n
5
1
read-write
0
Channel 5 Disabled
#0
1
Channel 5 Enabled
#1
CHEN6
Analog Input Channel 6 Enable Control\n
6
1
read-write
0
Channel 6 Disabled
#0
1
Channel 6 Enabled
#1
CHEN7
Analog Input Channel 7 Enable Control\n
7
1
read-write
0
Channel 7 Disabled
#0
1
Channel 7 Enabled
#1
PRESEL
Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7, the ADC clock rate needs to be limited to lower than 300 kHz.
8
1
read-write
0
External analog input
#0
1
Internal band-gap voltage (VBG)
#1
ADCMPR0
ADCMPR0
ADC Compare Register 0
0x28
read-write
n
0x0
0x0
CMPCH
Compare Channel Selection\n
3
3
read-write
0
Channel 0 conversion result is selected to be compared
#000
1
Channel 1 conversion result is selected to be compared
#001
2
Channel 2 conversion result is selected to be compared
#010
3
Channel 3 conversion result is selected to be compared
#011
4
Channel 4 conversion result is selected to be compared
#100
5
Channel 5 conversion result is selected to be compared
#101
6
Channel 6 conversion result is selected to be compared
#110
7
Channel 7 conversion result is selected to be compared
#111
CMPCOND
Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
2
1
read-write
0
Set the compare condition as that when a 10-bit A/D conversion result is less than the 10-bit CMPD (ADCMPRx[25:16]), the internal match counter will increase one
#0
1
Set the compare condition as that when a 10-bit A/D conversion result is greater or equal to the 10-bit CMPD (ADCMPRx[25:16]), the internal match counter will increase one
#1
CMPD
Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel.
16
10
read-write
CMPEN
Compare Enable Control\nSet 1 to this bit to enable comparing CMPD[9:0] with specified channel conversion results when converted data is loaded into the ADDR register.\n
0
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
CMPIE
Compare Interrupt Enable Control\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.\n
1
1
read-write
0
Compare function interrupt Disabled
#0
1
Compare function interrupt Enabled
#1
CMPMATCNT
Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND, the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
8
4
read-write
ADCMPR1
ADCMPR1
ADC Compare Register 1
0x2C
read-write
n
0x0
0x0
ADCR
ADCR
ADC Control Register
0x20
read-write
n
0x0
0x0
ADEN
A/D Converter Enable Control\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
0
1
read-write
0
A/D Converter Disabled
#0
1
A/D Converter Enabled
#1
ADIE
A/D Interrupt Enable Control\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.\n
1
1
read-write
0
A/D interrupt function Disabled
#0
1
A/D interrupt function Enabled
#1
ADST
A/D Conversion Start\nADST bit can be set to 1 from three sources: software or PWM trigger and external pin STADC. ADST will be cleared to 0 by hardware automatically after conversion complete.\n
11
1
read-write
0
Conversion stopped and A/D converter entered idle state
#0
1
Conversion start
#1
TRGCOND
External Trigger Condition\nThis bit decides whether the external pin STADC trigger event is falling or raising edge. The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigger.\n
6
1
read-write
0
Falling edge
#0
1
Raising edge
#1
TRGEN
External Trigger Enable Control\nEnable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source.\n
8
1
read-write
0
External trigger Disabled
#0
1
External trigger Enabled
#1
TRGS
Hardware Trigger Source\nNote: Software should disable TRGEN and ADST before change TRGS.
4
2
read-write
0
A/D conversion is started by external STADC pin
#00
3
A/D conversion is started by PWM trigger
#11
ADDR
ADDR
ADC Data Register
0x0
read-only
n
0x0
0x0
OVERRUN
Over Run Flag\nIf converted data in RSLT[9:0] has not been read before the new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after the ADDR register is read.
16
1
read-only
0
Data in RSLT (ADDR[9:0])is recent conversion result
#0
1
Data in RSLT (ADDR[9:0])overwrote
#1
RSLT
A/D Conversion Result\nThis field contains conversion result of ADC.
0
10
read-only
VALID
Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADDR register is read.
17
1
read-only
0
Data in RSLT (ADDR[9:0]) bits not valid
#0
1
Data in RSLT (ADDR[9:0]) bits valid
#1
ADSAMP
ADSAMP
ADC Sampling Time Counter Register
0x48
read-write
n
0x0
0x0
ADSAMPCNT
ADC Sampling Counter\nIf the ADC input is unstable, user can set this register to increase the sampling time to get a stable ADC input signal. The default sampling time is 1 ADC clock. The additional clock number will be inserted to lengthen the sampling clock.\n
0
4
read-write
0
0 additional ADC sample clock
#0000
1
1 additional ADC sample clock
#0001
2
2 additional ADC sample clock
#0010
3
4 additional ADC sample clock
#0011
4
8 additional ADC sample clock
#0100
5
16 additional ADC sample clock
#0101
6
32 additional ADC sample clock
#0110
7
64 additional ADC sample clock
#0111
8
128 additional ADC sample clock
#1000
9
256 additional ADC sample clock
#1001
10
512 additional ADC sample clock
#1010
11
1024 additional ADC sample clock
#1011
12
1024 additional ADC sample clock
#1100
13
1024 additional ADC sample clock
#1101
14
1024 additional ADC sample clock
#1110
15
1024 additional ADC sample clock
#1111
ADSR
ADSR
ADC Status Register
0x30
read-write
n
0x0
0x0
ADF
A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. ADF is set to 1 When A/D conversion ends.\nSoftware can write 1 to clear this bit to 0.
0
1
read-write
BUSY
BUSY/IDLE (Read Only)\nThis bit is mirror of as ADST bit in ADCR\n
3
1
read-only
0
A/D converter is in idle state
#0
1
A/D converter is busy at conversion
#1
CHANNEL
Current Conversion Channel (Read Only)\n
4
3
read-only
CMPF0
Compare Flag 0\nWhen the selected channel A/D conversion result meets the setting condition in ADCMPR0, this bit is set to 1. Software can write 1 to clear this bit to 0.\n
1
1
read-write
0
Conversion result in ADDR does not meet the ADCMPR0 setting
#0
1
Conversion result in ADDR meets the ADCMPR0 setting
#1
CMPF1
Compare Flag 1\nWhen the selected channel A/D conversion result meets the setting condition in ADCMPR1, this bit is set to 1. Software can write 1 to clear this bit to 0.\n
2
1
read-write
0
Conversion result in ADDR does not meet the ADCMPR1 setting
#0
1
Conversion result in ADDR meets the ADCMPR1 setting
#1
OVERRUN
Overrun Flag (Read Only)\nIt is a mirror to OVERRUN (ADSR[16]) bit in ADDR register.
16
1
read-only
VALID
Data Valid Flag (Read Only)\nIt is a mirror of VALID (ADDR[17]) bit in ADDR register.
8
1
read-only
ADTDCR
ADTDCR
ADC Trigger Delay Control Register
0x44
read-write
n
0x0
0x0
PTDT
PWM Trigger Delay Timer\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * PTDT) * system clock.
0
8
read-write
CLK
CLK Register Map
CLK
0x0
0x0
0x20
registers
n
0x24
0x4
registers
n
AHBCLK
AHBCLK
AHB Devices Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
ISP_EN
Flash ISP Controller Clock Enable Control\n
2
1
read-write
0
Flash ISP peripheral clock Disabled
#0
1
Flash ISP peripheral clock Enabled
#1
APBCLK
APBCLK
APB Devices Clock Enable Control Register
0x8
-1
read-write
n
0x0
0x0
ACMP_EN
Analog Comparator Clock Enable Control\n
30
1
read-write
0
Analog Comparator clock Disabled
#0
1
Analog Comparator clock Enabled
#1
ADC_EN
Analog-digital-converter (ADC) Clock Enable Control\n
28
1
read-write
0
ADC peripheral clock Disabled
#0
1
ADC peripheral clock Enabled
#1
FDIV_EN
Frequency Divider Output Clock Enable Control\n
6
1
read-write
0
FDIV clock Disabled
#0
1
FDIV clock Enabled
#1
I2C_EN
I2C Clock Enable Control\n
8
1
read-write
0
I2C clock Disabled
#0
1
I2C clock Enabled
#1
PWM01_EN
PWM_01 Clock Enable Control\n
20
1
read-write
0
PWM01 clock Disabled
#0
1
PWM01 clock Enabled
#1
PWM23_EN
PWM_23 Clock Enable Control\n
21
1
read-write
0
PWM23 clock Disabled
#0
1
PWM23 clock Enabled
#1
PWM45_EN
PWM_45 Clock Enable Control\n
22
1
read-write
0
PWM45 clock Disabled
#0
1
PWM45 clock Enabled
#1
SPI_EN
SPI Peripheral Clock Enable Control\n
12
1
read-write
0
SPI peripheral clock Disabled
#0
1
SPI peripheral clock Enabled
#1
TMR0_EN
Timer0 Clock Enable Control\n
2
1
read-write
0
Timer0 clock Disabled
#0
1
Timer0 clock Enabled
#1
TMR1_EN
Timer1 Clock Enable Control\n
3
1
read-write
0
Timer1 clock Disabled
#0
1
Timer1 clock Enabled
#1
UART_EN
UART Clock Enable Control\n
16
1
read-write
0
UART clock Disabled
#0
1
UART clock Enabled
#1
WDT_EN
Watchdog Timer Clock Enable Control (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA + 0x100.
0
1
read-write
0
Watchdog Timer clock Disabled
#0
1
Watchdog Timer clock Enabled
#1
CLKDIV
CLKDIV
Clock Divider Number Register
0x18
read-write
n
0x0
0x0
ADC_N
ADC Peripheral Clock Divide Number From ADC Peripheral Clock Source\n
16
8
read-write
HCLK_N
HCLK Clock Divide Number From HCLK Clock Source\n
0
4
read-write
UART_N
UART Clock Divide Number From UART Clock Source\n
8
4
read-write
CLKSEL0
CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLK_S
HCLK Clock Source Selection (Write Protect)\nNote1: Before clock switching, the related clock sources (both pre-select and new-select) must be turn-on and stable.\nNote2: These bits are protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA + 0x100.\nNote3: To set PWRCON[1:0], select HXT or LXT crystal clock.
0
3
read-write
0
Clock source is from HXT or LXT
#000
1
Reserved
#001
2
Reserved
#010
3
Clock source is from LIRC
#011
7
Clock source is from HIRC
#111
STCLK_S
Cortex-M0 SysTick Clock Source Selection From Reference Clock (Write Protect)\nNote3: To set PWRCON[1:0], select HXT or LXT crystal clock.
3
3
read-write
0
Clock source is from HXT or LXT
#000
1
Reserved
#001
2
Clock source is from HXT/2 or LXT/2
#010
3
Clock source is from HCLK/2
#011
7
Clock source is from HIRC /2
#111
CLKSEL1
CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
ADC_S
ADC Peripheral Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
2
2
read-write
0
Clock source is from HXT or LXT
#00
1
Reserved
#01
2
Clock source is from HCLK
#10
3
Clock source is from HIRC
#11
SPI_S
SPI Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
4
1
read-write
0
Clock source is from HXT or LXT
#0
1
Clock source is from HCLK
#1
TMR0_S
TIMER0 Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
8
3
read-write
0
Clock source is from HXT or LXT
#000
1
Clock source is from LIRC
#001
2
Clock source is from HCLK
#010
3
Clock source is from external trigger
#011
7
Clock source is from HIRC
#111
TMR1_S
TIMER1 Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
12
3
read-write
0
Clock source is from HXT or LXT
#000
1
Clock source is from LIRC
#001
2
Clock source is from HCLK
#010
3
Clock source is from external trigger
#011
7
Clock source is from HIRC
#111
UART_S
UART Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
24
2
read-write
0
Clock source is from HXT or LXT
#00
1
Reserved
#01
2
Clock source is from HIRC
#10
3
Clock source is from HIRC
#11
WDT_S
WDT CLK Clock Source Selection (Write Protect)\nNote1: These bits are the protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA + 0x100.\nNote2: To set PWRCON[1:0], select HXT or LXT crystal clock.
0
2
read-write
0
Clock source is from HXT or LXT
#00
1
Reserved
#01
2
Clock source is from HCLK/2048 clock
#10
3
Clock source is from LIRC
#11
CLKSEL2
CLKSEL2
Clock Source Select Control Register 2
0x1C
-1
read-write
n
0x0
0x0
FRQDIV_S
Clock Divider Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
2
2
read-write
0
Clock source is from HXT or LXT
#00
1
Reserved
#01
2
Clock source is from HCLK
#10
3
Clock source is from HIRC
#11
CLKSTATUS
CLKSTATUS
Clock Status Monitor Register
0xC
-1
read-write
n
0x0
0x0
CLK_SW_FAIL
Clock Switch Fail Flag\nNote1: This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote2: This bit is read only. After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLK_SE_FAIL will be cleared automatically by hardware.
7
1
read-write
0
Clock switching success
#0
1
Clock switching failed
#1
OSC10K_STB
LIRC Clock Source Stable Flag (Read Only)\n
3
1
read-only
0
LIRC clock is not stable or disabled
#0
1
LIRC clock is stable
#1
OSC22M_STB
HIRC Clock Source Stable Flag (Read Only)\n
4
1
read-only
0
HIRC clock is not stable or disabled
#0
1
HIRC clock is stable
#1
XTL_STB
HXT Or LXT Clock Source Stable Flag
0
1
read-write
0
HXT or LXT clock is not stable or disabled
#0
1
HXT or LXT clock is stable
#1
FRQDIV
FRQDIV
Frequency Divider Control Register
0x24
read-write
n
0x0
0x0
DIVIDER1
Frequency Divider 1 Enable Control\n
5
1
read-write
0
Divider output frequency is depended on FSEL value
#0
1
Divider output frequency is the same as input clock frequency
#1
DIVIDER_EN
Frequency Divider Enable Control\n
4
1
read-write
0
Frequency Divider Disabled
#0
1
Frequency Divider Enabled
#1
FSEL
Divider Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0].
0
4
read-write
PWRCON
PWRCON
System Power-down Control Register
0x0
-1
read-write
n
0x0
0x0
OSC10K_EN
10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Control (Write Protect)\n
3
1
read-write
0
10 kHz internal low speed RC oscillator (LIRC) Disabled
#0
1
10 kHz internal low speed RC oscillator (LIRC) Enabled
#1
OSC22M_EN
22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Control (Write Protect)\nNote: The default of OSC22M_EN bit is 1.
2
1
read-write
0
22.1184 MHz internal high speed RC oscillator (HIRC) Disabled
#0
1
22.1184 MHz internal high speed RC oscillator (HIRC) Enabled
#1
PD_32K
Enable LXT In Power-down Mode\nThis bit controls the crystal oscillator active or not in Power-down mode.\n
9
1
read-write
0
No effect to Power-down mode
#0
1
If XTLCLK_EN[1:0] = 10, LXT is still active in Power-down mode
#1
PD_WU_DLY
Wake-up Delay Counter Enable Control (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz external high speed crystal (HXT), 4096 clock cycles for 32.768 kHz external low speed crystal (LXT), and 16 clock cycles when chip works at 22.1184 MHz internal high speed RC oscillator (HIRC).\n
4
1
read-write
0
Clock cycles delay Disabled
#0
1
Clock cycles delay Enabled
#1
PD_WU_INT_EN
Power-down Mode Wake-up Interrupt Enable Control (Write Protect)\nNote: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
5
1
read-write
0
Disabled
#0
1
Enabled
#1
PD_WU_STS
Power-down Mode Wake-up Interrupt Status
Set by Power-down wake-up event , which indicates that resume from Power-down mode
The flag is set if the GPIO, UART, WDT, I2C, ACMP, Timer or BOD wake-up occurred.
Note: This bit works only if PD_WU_INT_EN (PWRCON[5]) set to 1. Write 1 to clear the bit to 0.
6
1
read-write
PWR_DOWN_EN
System Power-down Enable Bit (Write Protect)\nWhen chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next Power-down.\nIn Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT), 32.768 kHz external low speed crystal oscillator (LXT), and the 22.1184 MHz internal high speed oscillator (HIRC) will be disabled in this mode, and 10 kHz internal low speed RC oscillator (LIRC) are not controlled by Power-down mode.\nIn Power-down mode, the system clock is disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from 10 kHz internal low speed oscillator.\n
7
1
read-write
0
Chip operating normally or chip in Idle mode because of WFI command
#0
1
Chip enters Power-down mode instantly or waits CPU sleep command WFI
#1
XTLCLK_EN
External Crystal HXT Or LXT Enable Control (Write Protect)
The default clock source is from HIRC. These two bits are default set to 00 and the XTAL1 and XTAL2 pins are GPIO.
Note: To enable the external XTAL function, the P5_ALT[1:0] and P5_MFP[1:0] bits must also be set in P5_MFP.
0
2
read-write
0
XTAL1 and XTAL2 are GPIO, disable both LXT HXT (default)
#00
1
HXT Enabled
#01
2
LXT Enabled
#10
3
XTAL1 is external clock input pin, XTAL2 is GPIO
#11
FMC
FMC Register Map
FMC
0x0
0x0
0x18
registers
n
0x40
0x4
registers
n
DFBA
DFBA
Data Flash Start Address
0x14
-1
read-only
n
0x0
0x0
DFBA
Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash start address is defined by user. Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0.
0
32
read-only
ISPADR
ISPADR
ISP Address Register
0x4
read-write
n
0x0
0x0
ISPADR
ISP Address\nThe NuMicro Mini51TM series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation.
0
32
read-write
ISPCMD
ISPCMD
ISP Command Register
0xC
read-write
n
0x0
0x0
ISPCMD
ISP Command \nISP commands are shown below:\n
0
6
read-write
0
Read
0x00
4
Read Unique ID
0x04
11
Read Company ID (0xDA)
0x0b
33
Program
0x21
34
Page Erase
0x22
46
Set Vector Page Re-Map
0x2e
ISPCON
ISPCON
ISP Control Register
0x0
read-write
n
0x0
0x0
APUEN
APROM Update Enable Control (Write Protect)\n
3
1
read-write
0
APROM cannot be updated when chip runs in APROM
#0
1
APROM can be updated when chip runs in APROM
#1
BS
Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.\n
1
1
read-write
0
Boot from APROM
#0
1
Boot from LDROM
#1
CFGUEN
CONFIG Update Enable Control (Write Protect)\nWriting this bit to 1 enables software to update CONFIG value by ISP register control procedure regardless of program code is running in APROM or LDROM.\n
4
1
read-write
0
ISP update User Configuration Disabled
#0
1
ISP update User Configuration Enabled
#1
ISPEN
ISP Enable Control (Write Protect)\nSet this bit to enable ISP function.\n
0
1
read-write
0
ISP function Disabled
#0
1
ISP function Enabled
#1
ISPFF
ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(3) User Configuration is erased/programmed when CFGUEN is 0.\n(4) Destination address is illegal, such as over an available range.\nNote: Write 1 to clear this bit to 0.
6
1
read-write
LDUEN
LDROM Update Enable Control (Write Protect)\n
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated when the MCU runs in APROM
#1
ISPDAT
ISPDAT
ISP Data Register
0x8
read-write
n
0x0
0x0
ISPDAT
ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
0
32
read-write
ISPSTA
ISPSTA
ISP Status Register
0x40
read-write
n
0x0
0x0
CBS
Config Boot Selection (Read Only)\nThis is a mirror of CBS in CONFIG0.
1
2
read-only
ISPFF
ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(3) User Configuration is erased/programmed when CFGUEN is 0.\n(4) Destination address is illegal, such as over an available range.\nWrite 1 to clear.\nNote: This bit functions the same as ISPCON bit 6.
6
1
read-write
ISPGO
ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same with ISPTRG bit 0.
0
1
read-only
0
ISP operation is finished
#0
1
ISP operation is progressed
#1
VECMAP
Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}.
9
12
read-only
ISPTRG
ISPTRG
ISP Trigger Register
0x10
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n
0
1
read-write
0
ISP operation is finished
#0
1
ISP operation is progressed
#1
GCR
GCR Register Map
GCR
0x0
0x0
0x10
registers
n
0x100
0x4
registers
n
0x18
0x4
registers
n
0x30
0x18
registers
n
0x80
0xC
registers
n
BODCR
BODCR
Brown-out Detector Control Register
0x18
read-write
n
0x0
0x0
BOD_INTF
Brown-out Detector Interrupt Flag\n
4
1
read-write
0
Brown-out Detector does not detect any voltage dropped at AVDD down through or up through the voltage of BOD_VL setting
#0
1
When Brown-out Detector detects the AVDD is dropped through the voltage of BOD_VL setting or the AVDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled
#1
BOD_LPM
Brown-out Detector Low Power Mode (Write Protect)\nThe BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1uA but slow the BOD response.
5
1
read-write
0
BOD operate in normal mode (default)
#0
1
Enable the BOD low power mode
#1
BOD_OUT
Brown-out Detector Output State\n
6
1
read-write
0
Brown-out Detector status output is 0, the detected voltage is higher than BOD_VL setting
#0
1
Brown-out Detector status output is 1, the detected voltage is lower than BOD_VL setting
#1
BOD_RSTEN
Brown-out Reset Enable Control (Initiated And Write-protected Bit)\nThe default value is set by flash controller user configuration register config0 bit[20].\nWhen the BOD_EN is enabled and the interrupt is asserted, the interrupt will be kept till the BOD_EN is set to 0. The interrupt for CPU can be blocked by disabling the NVIC in CPU for BOD interrupt or disable the interrupt source by disabling the BOD_EN and then re-enabling the BOD_EN function if the BOD function is required.
3
1
read-write
0
Brown-out INTERRUPT function Enabled when the Brown-out Detector function is enable and the detected voltage is lower than the threshold, then assert a signal to interrupt the Cortex-M0 CPU
#0
1
Brown-out RESET function Enabled when the Brown-out Detector function is enable and the detected voltage is lower than the threshold then assert a signal to reset the chip
#1
BOD_VL
Brown-out Detector Threshold Voltage Selection (Initiated Write-protected Bit)
1
2
read-write
BOD_VL_EXT
Brown-out Detector Selection Extension (Initiated Write-protected Bit)
0
1
read-write
0
Brown-out detector threshold voltage is selected by the table defined in BOD_VL
#0
1
Brown-out detector threshold voltage is selected by the table defined below
#1
IPRSTC1
IPRSTC1
Peripheral Reset Control Resister 1
0x8
read-write
n
0x0
0x0
CHIP_RST
CHIP One-shot Reset (Write Protect)\nSetting this bit will reset the CHIP, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is the same as the POR reset, and all the chip module is reset and the chip settings from flash are also reloaded.\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA + 0x100.
0
1
read-write
0
Chip normal operation
#0
1
CHIP one-shot reset
#1
CPU_RST
CPU Kernel Reset\nSetting this bit will reset the CPU kernel, and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA + 0x100.
1
1
read-write
0
CPU normal operation
#0
1
Reset CPU Kernel
#1
IPRSTC2
IPRSTC2
Peripheral Reset Control Resister 2
0xC
read-write
n
0x0
0x0
ACMP_RST
ACMP Controller Reset\n
22
1
read-write
0
ACMP module normal operation
#0
1
ACMP module reset
#1
ADC_RST
ADC Controller Reset\n
28
1
read-write
0
ADC module normal operation
#0
1
ADC module reset
#1
GPIO_RST
GPIO (P0~P5) Controller Reset\n
1
1
read-write
0
GPIO module normal operation
#0
1
GPIO module reset
#1
I2C_RST
I2C Controller Reset\n
8
1
read-write
0
I2C module normal operation
#0
1
I2C module reset
#1
PWM_RST
PWM Controller Reset\n
20
1
read-write
0
PWM module normal operation
#0
1
PWM module reset
#1
SPI_RST
SPI Controller Reset\n
12
1
read-write
0
SPI module normal operation
#0
1
SPI module reset
#1
TMR0_RST
Timer0 Controller Reset\n
2
1
read-write
0
Timer0 module normal operation
#0
1
Timer0 module reset
#1
TMR1_RST
Timer1 Controller Reset\n
3
1
read-write
0
Timer1 module normal operation
#0
1
Timer1 module reset
#1
UART_RST
UART Controller Reset\n
16
1
read-write
0
UART module normal operation
#0
1
UART module reset
#1
IRCTRIMCTL
IRCTRIMCTL
HIRC Trim Control Register
0x80
read-write
n
0x0
0x0
TRIM_LOOP
Trim Calculation Loop\nThis field defines that trim value calculation is based on how many LXT clocks in.\nFor example, if TRIM_LOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT clock.\n
4
2
read-write
0
Trim value calculation is based on average difference in 4 LXT clocks
#00
1
Trim value calculation is based on average difference in 8 LXT clocks
#01
2
Trim value calculation is based on average difference in 16 LXT clocks
#10
3
Trim value calculation is based on average difference in 32 LXT clocks
#11
TRIM_RETRY_CNT
Trim Value Update Limitation Count\n
6
2
read-write
TRIM_SEL
Trim Frequency Selection\nThis bit is to enable the HIRC auto trim.\nWhen setting this bit to 1, the HIRC auto trim function will trim HIRC to 22.1184 MHz automatically based on the LXT reference clock.\nDuring auto trim operation, if LXT clock error is detected or trim retry limitation count reached, this field will be cleared to 0 automatically.\n
0
1
read-write
0
HIRC auto trim function Disabled
#0
1
HIRC auto trim function Enabled and HIRC trimmed to 22.1184 MHz
#1
IRCTRIMIEN
IRCTRIMIEN
HIRC Trim Interrupt Enable Control Register
0x84
read-write
n
0x0
0x0
TRIM_FAIL_IEN
Trim Failure Interrupt Enable Control\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count is reached and HIRC frequency is still not locked on target frequency set by TRIM_SEL.\nIf this bit is high and TRIM_FAIL_INT is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count is reached.\n
1
1
read-write
0
TRIM_FAIL_INT status Disabled to trigger an interrupt to CPU
#0
1
TRIM_FAIL_INT status Enabled to trigger an interrupt to CPU
#1
_32K_ERR_IEN
LXT Clock Error Interrupt Enable Control\nThis bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation.\nIf this bit is high, and 32K_ERR_INT is set during auto trim operation, an interrupt will be triggered to notify the LXT clock frequency is inaccurate.\n
2
1
read-write
0
32K_ERR_INT status Disabled to trigger an interrupt to CPU
#0
1
32K_ERR_INT status Enabled to trigger an interrupt to CPU
#1
IRCTRIMINT
IRCTRIMINT
HIRC Trim Interrupt Status Register
0x88
read-write
n
0x0
0x0
FREQ_LOCK
HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency locked in 22.1184 MHz.\nThis is a read only status bit and doesn't trigger any interrupt.
0
1
read-write
TRIM_FAIL_INT
Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 0 by hardware automatically.\nIf this bit is set and TRIM_FAIL_IEN is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Software can write 1 to clear this bit to 0.\n
1
1
read-write
0
Trim value update limitation count is not reached
#0
1
Trim value update limitation count is reached and HIRC frequency is still not locked
#1
_32K_ERR_INT
LXT Clock Error Interrupt Status\nThis bit indicates that LXT clock frequency is inaccuracy. Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 0 by hardware automatically.\nIf this bit is set and 32K_ERR_IEN is high, an interrupt will be triggered to notify the LXT clock frequency is inaccuracy. Software can write 1 to clear this bit to 0.\n
2
1
read-write
0
LXT clock frequency is accuracy
#0
1
LXT clock frequency is inaccuracy
#1
P0_MFP
P0_MFP
P0 Multiple Function and Input Type Control Register
0x30
read-write
n
0x0
0x0
P0_ALT0
P0.0 Alternate Function Selection\n
8
1
read-write
P0_ALT1
P0.1 Alternate Function Selection\n
9
1
read-write
P0_ALT4
P0.4 Alternate Function Selection\n
12
1
read-write
P0_ALT5
P0.5 Alternate Function Selection\n
13
1
read-write
P0_ALT6
P0.6 Alternate Function Selection\n
14
1
read-write
P0_ALT7
P0.7 Alternate Function Selection\n
15
1
read-write
P0_MFP
P0 Multiple Function Selection\nThe pin function of P0 depends on P0_MFP and P0_ALT.\nRefer to P0_ALT Description for details.
0
8
read-write
P0_TYPE
P0[7:0] TTL Or Schmitt Trigger Function Enable Control\n
16
8
read-write
0
P0[7:0]Select I/O input as TTL function
0
1
P0[7:0] Select I/O input as Schmitt Trigger function
1
P1_MFP
P1_MFP
P1 Multiple Function and Input Type Control Register
0x34
read-write
n
0x0
0x0
P1_ALT0
P1.0 Alternate Function Selection\n
8
1
read-write
P1_ALT2
P1.2 Alternate Function Selection\n
10
1
read-write
P1_ALT3
P1.3 Alternate Function Selection\n
11
1
read-write
P1_ALT4
P1.4 Alternate Function Selection\n
12
1
read-write
P1_ALT5
P1.5 Alternate Function Selection\n
13
1
read-write
P1_MFP
P1 Multiple Function Selection\nThe pin function of P1 depends on P1_MFP and P1_ALT.\nRefer to P1_ALT Description for details.
0
8
read-write
P1_TYPE
P1[7:0] TTL Or Schmitt Trigger Function Enable Control\n
16
8
read-write
0
P1[7:0]Select I/O input as TTL function
0
1
P1[7:0] Select I/O input as Schmitt Trigger function
1
P2_MFP
P2_MFP
P2 Multiple Function and Input Type Control Register
0x38
read-write
n
0x0
0x0
P2_ALT2
P2.2 Alternate Function Selection\n
10
1
read-write
P2_ALT3
P2.3 Alternate Function Selection\n
11
1
read-write
P2_ALT4
P2.4 Alternate Function Selection\n
12
1
read-write
P2_ALT5
P2.5 Alternate Function Selection\n
13
1
read-write
P2_ALT6
P2.6 Alternate Function Selection\n
14
1
read-write
P2_MFP
P2 Multiple Function Selection\nThe pin function of P2 depends on P2_MFP and P2_ALT.\nRefer to P2_ALT Description for details.
0
8
read-write
P2_TYPE
P2[7:0] TTL Or Schmitt Trigger Function Enable Control\n
16
8
read-write
0
P2[7:0]Select I/O input as TTL function
0
1
P2[7:0] Select I/O input as Schmitt Trigger function
1
P3_MFP
P3_MFP
P3 Multiple Function and Input Type Control Register
0x3C
read-write
n
0x0
0x0
P32CPP1
P3.2 Alternate Function Selection Extension\n
24
1
read-write
0
P3.2 is set by P3_ALT[2] and P3_MFP[2]
#0
1
P3.2 is set to CPP1 of ACMP1
#1
P3_ALT0
P3.0 Alternate Function Selection\n
8
1
read-write
P3_ALT1
P3.1 Alternate Function Selection\n
9
1
read-write
P3_ALT2
P3.2 Alternate Function Selection\n
10
1
read-write
P3_ALT4
P3.4 Alternate Function Selection\n
12
1
read-write
P3_ALT5
P3.5 Alternate Function Selection\n
13
1
read-write
P3_ALT6
P3.6 Alternate Function Selection\n
14
1
read-write
P3_MFP
P3 Multiple Function Selection\nThe pin function of P3 depends on P3_MFP and P3_ALT.\nRefer to P3_ALT Description for details.
0
8
read-write
P3_TYPE
P3[7:0] TTL Or Schmitt Trigger Function Enable Control\n
16
8
read-write
0
P3[7:0]Select I/O input as TTL function
0
1
P3[7:0] Select I/O input as Schmitt Trigger function
1
P4_MFP
P4_MFP
P4 Multiple Function and Input Type Control Register
0x40
-1
read-write
n
0x0
0x0
P4_ALT6
P4.6 Alternate Function Selection\n
14
1
read-write
P4_ALT7
P4.7 Alternate Function Selection\n
15
1
read-write
P4_MFP
P4 Multiple Function Selection\nThe pin function of P4 depends on P4_MFP and P4_ALT.\nRefer to P4_ALT Description for details.
0
8
read-write
P4_TYPE
P4[7:0] TTL Or Schmitt Trigger Function Enable Control\n
16
8
read-write
0
P4[7:0]Select I/O input as TTL function
0
1
P4[7:0] Select I/O input as Schmitt Trigger function
1
P5_MFP
P5_MFP
P5 Multiple Function and Input Type Control Register
0x44
read-write
n
0x0
0x0
P5_ALT0
P5.0 Alternate Function Selection\n
8
1
read-write
P5_ALT1
P5.1 Alternate Function Selection\n
9
1
read-write
P5_ALT2
P5.2 Alternate Function Selection\n
10
1
read-write
P5_ALT3
P5.3 Alternate Function Selection\n
11
1
read-write
P5_ALT4
P5.4 Alternate Function Selection\n
12
1
read-write
P5_ALT5
P5.5 Alternate Function Selection\n
13
1
read-write
P5_MFP
P5 Multiple Function Selection\nThe pin function of P5 depends on P5_MFP and P5_ALT.\nRefer to P5_ALT Description for details.
0
8
read-write
P5_TYPE
P5[7:0] TTL Or Schmitt Trigger Function Enable Control\n
16
8
read-write
0
P5[7:0]Select I/O input as TTL function
0
1
P5[7:0] Select I/O input as Schmitt Trigger function
1
PDID
PDID
Part Device Identification Number Register
0x0
read-only
n
0x0
0x0
PDID
Product Device Identification Number
This register reflects the device part number code. Software can read this register to identify which device is used.
For example, the MINI51LDE PDID code is 0x20205100 .
0
32
read-only
REGWRPROT
REGWRPROT
Register Write-protection Control Register
0x100
read-write
n
0x0
0x0
REGPROTDIS
Register Write-protection Disable Index (Read Only)\n
0
1
read-only
0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
#0
1
Write-protection Disabled for writing protected registers
#1
REGWRPROT
Register Write-protection Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write.
0
8
write-only
RSTSRC
RSTSRC
System Reset Source Register
0x4
read-write
n
0x0
0x0
RSTS_BOD
Brown-out Detector Reset Flag
The RSTS_BOD flag is set by the reset signal from the Brown-out Detector to indicate the previous reset source.
Note: Software can write 1 to clear this bit to 0.
4
1
read-write
0
No reset from BOD
#0
1
The BOD had issued the reset signal to reset the system
#1
RSTS_CPU
CPU Reset Flag\nThe RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC).\nNote: Software can write 1 to clear this bit to 0.
7
1
read-write
0
No reset from CPU
#0
1
Cortex-M0 core and FMC are reset by software setting CPU_RST to 1
#1
RSTS_MCU
MCU Reset Flag
The RSTS_MCU flag is set by the reset signal from the Cortex-M0 core to indicate the previous reset source.
Note: Software can write 1 to clear this bit to 0.
5
1
read-write
0
No reset from Cortex-M0
#0
1
The Cortex-M0 had issued the reset signal to reset the system by writing 1 to bit SYSRESETREQ (AIRCR[2]), Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core
#1
RSTS_POR
Power-on Reset Flag
The RSTS_POR flag is set by the reset signal , which is from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]), to indicate the previous reset source.
Note: Software can write 1 to clear this bit to 0.
0
1
read-write
0
No reset from POR or CHIP_RST
#0
1
Power-on-Reset (POR) or CHIP_RST had issued the reset signal to reset the system
#1
RSTS_RESET
Reset Pin Reset Flag
The RSTS_RESET flag is set by the reset signal from the /RESET pin to indicate the previous reset source.
Note: Software can write 1 to clear this bit to 0.
1
1
read-write
0
No reset from pin /RESET pin
#0
1
The /RESET pin had issued the reset signal to reset the system
#1
RSTS_WDT
Watchdog Reset Flag
The RSTS_WDT flag is set by the reset signal from the Watchdog timer to indicate the previous reset source.
Note: Software can write 1 to clear this bit to 0.
2
1
read-write
0
No reset from Watchdog timer
#0
1
The Watchdog timer had issued the reset signal to reset the system
#1
GP
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
0x100
0x24
registers
n
0x140
0x24
registers
n
0x180
0x4
registers
n
0x200
0x8
registers
n
0x210
0x14
registers
n
0x228
0x10
registers
n
0x248
0x14
registers
n
0x260
0xC
registers
n
0x270
0xC
registers
n
0x298
0x20
registers
n
0x40
0x24
registers
n
0x80
0x24
registers
n
0xC0
0x24
registers
n
DBNCECON
DBNCECON
Interrupt De-bounce Control
0x180
-1
read-write
n
0x0
0x0
DBCLKSEL
De-bounce Sampling Cycle Selection\n
0
4
read-write
DBCLKSRC
De-bounce Counter Clock Source Selection\n
4
1
read-write
0
De-bounce counter clock source is the HCLK
#0
1
De-bounce counter clock source is the 10 kHz internal low speed oscillator
#1
ICLK_ON
Interrupt Clock On Mode\nNote: It is recommended to turn off this bit to save system power if no special application concern.
5
1
read-write
0
Edge detection circuit is active only if I/O pin corresponding Px_IEN bit is set to 1
#0
1
All I/O pins edge detection circuit is always active after reset
#1
P00_PDIO
P00_PDIO
GPIO P0.0 Pin Data Input/Output
0x200
-1
read-write
n
0x0
0x0
P_PDIO
GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n].
0
1
read-write
0
Corresponding GPIO pin set to low.\nCorresponding GPIO pin status is low
#0
1
Corresponding GPIO pin set to high.\nCorresponding GPIO pin status is high
#1
P01_PDIO
P01_PDIO
GPIO P0.1 Pin Data Input/Output
0x204
read-write
n
0x0
0x0
P04_PDIO
P04_PDIO
GPIO P0.4 Pin Data Input/Output
0x210
read-write
n
0x0
0x0
P05_PDIO
P05_PDIO
GPIO P0.5 Pin Data Input/Output
0x214
read-write
n
0x0
0x0
P06_PDIO
P06_PDIO
GPIO P0.6 Pin Data Input/Output
0x218
read-write
n
0x0
0x0
P07_PDIO
P07_PDIO
GPIO P0.7 Pin Data Input/Output
0x21C
read-write
n
0x0
0x0
P0_DBEN
P0_DBEN
P0 De-bounce Enable Control
0x14
read-write
n
0x0
0x0
DBEN
Port 0-5 Pin [N] Input Signal De-bounce Enable Control\nDBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\nNote2: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system woken up caused by the Px.n de-bounce function.\nNote3:\nP0_DBEN[3:2] are reserved.\nP1_DBEN[7:6], [1] are reserved.\nP2_DBEN[7], [1:0] are reserved.\nP3_DBEN[7], [3] are reserved.\nP4_DBEN[5:0] are reserved.\nP5_DBEN[7:6] are reserved.
0
8
read-write
0
Px.n de-bounce function Disabled
0
1
Px.n de-bounce function Enabled
1
P0_DMASK
P0_DMASK
P0 Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK
Port 0-5 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding Px_DOUT[n] bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote2: This function only protects the corresponding Px_DOUT[n] bit, and will not protect the corresponding Pxn_PDIO bit.\nNote3:\nP0_DMASK[3:2] are reserved.\nP1_DMASK[7:6], [1] are reserved.\nP2_DMASK[7], [1:0] are reserved.\nP3_DMASK[7], [3] are reserved.\nP4_DMASK[5:0] are reserved.\nP5_DMASK[7:6] are reserved.
0
8
read-write
0
Corresponding Px_DOUT[n] bit can be updated
0
1
Corresponding Px_DOUT[n] bit is protected
1
P0_DOUT
P0_DOUT
P0 Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT
Port 0-5 Pin [N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output and Quasi-bidirectional mode.\nNote2:\nP0_DOUT[3:2] are reserved.\nP1_DOUT[7:6], [1] are reserved.\nP2_DOUT[7], [1:0] are reserved.\nP3_DOUT[7], [3] are reserved.\nP4_DOUT[5:0] are reserved.\nP5_DOUT[7:6] are reserved.
0
8
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
1
P0_IEN
P0_IEN
P0 Interrupt Enable Control
0x1C
read-write
n
0x0
0x0
IF_EN
Port 0-5 Pin [N] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EB[n] bit to 1:\nIf the interrupt is level trigger (IMD[n] is 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge mode trigger (IMD[n] is 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nP0_IEN[19:18], [3:2] are reserved.\nP1_IEN[23:22], [17], [7:6], [1] are reserved.\nP2_IEN[23], [17:16], [7], [1:0] are reserved.\nP3_IEN[23], [19], [7], [3] are reserved.\nP4_IEN[21:16], [5:0] are reserved.\nP5_IEN[23:22], [7:6] are reserved.
0
1
read-write
0
Px.n low level or high to low interrupt Disabled
#0
1
Px.n low level or high to low interrupt Enabled
#1
IR_EN
Port 0-5 Pin [N] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger (IMD[n] is 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (IMD[n] is 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
16
8
read-write
0
Px.n level high or low to high interrupt Disabled
0
1
Px.n level high or low to high interrupt Enabled
1
P0_IMD
P0_IMD
P0 Interrupt Mode Control
0x18
read-write
n
0x0
0x0
IMD
Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control\nIMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nP0_IMD[3:2] are reserved.\nP1_IMD[7:6], [1] are reserved.\nP2_IMD[7], [1:0] are reserved.\nP3_IMD[7], [3] are reserved.\nP4_IMD[5:0] are reserved.\nP5_IMD[7:6] are reserved.
0
8
read-write
0
Edge trigger interrupt
0
1
Level trigger interrupt
1
P0_ISRC
P0_ISRC
P0 Interrupt Source Flag
0x20
read-write
n
0x0
0x0
ISRC
Port 0-5 Pin [N] Interrupt Source Flag\nWrite :\nNote2:\nP0_ISRC[3:2] are reserved.\nP1_ISRC[7:6], [1] are reserved.\nP2_ISRC[7], [1:0] are reserved.\nP3_ISRC[7], [3] are reserved.\nP4_ISRC[5:0] are reserved.\nP5_ISRC[7:6] are reserved.
0
8
read-write
0
No action.\nNo interrupt at Px.n
0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
1
P0_OFFD
P0_OFFD
P0 Digital Input Path Disable Control
0x4
read-write
n
0x0
0x0
OFFD
Port 0-5 Pin [N] Digital Input Path Disable Control\n
16
8
read-write
0
Px.n digital input path Enabled
0
1
Px.n digital input path Disabled (digital input tied to low)
1
P0_PIN
P0_PIN
P0 Pin Value
0x10
read-only
n
0x0
0x0
PIN
Port 0-5 Pin [N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note2:
P0_PIN[3:2] are reserved.
P1_PIN[7:6], [1] are reserved.
P2_PIN[7], [1:0] are reserved.
P3_PIN[7], [3] are reserved.
P4_PIN[5:0] are reserved.
P5_PIN[7:6] are reserved.
0
8
read-only
P0_PMD
P0_PMD
P0 I/O Mode Control
0x0
read-write
n
0x0
0x0
PMD0
Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
0
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
PMD1
Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
2
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
PMD2
Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
4
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
PMD3
Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
6
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
PMD4
Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
8
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
PMD5
Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
10
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
PMD6
Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
12
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
PMD7
Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
14
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
P10_PDIO
P10_PDIO
GPIO P1.0 Pin Data Input/Output
0x220
read-write
n
0x0
0x0
P12_PDIO
P12_PDIO
GPIO P1.2 Pin Data Input/Output
0x228
read-write
n
0x0
0x0
P13_PDIO
P13_PDIO
GPIO P1.3 Pin Data Input/Output
0x22C
read-write
n
0x0
0x0
P14_PDIO
P14_PDIO
GPIO P1.4 Pin Data Input/Output
0x230
read-write
n
0x0
0x0
P15_PDIO
P15_PDIO
GPIO P1.5 Pin Data Input/Output
0x234
read-write
n
0x0
0x0
P1_DBEN
P1_DBEN
P1 De-bounce Enable Control
0x54
read-write
n
0x0
0x0
P1_DMASK
P1_DMASK
P1 Data Output Write Mask
0x4C
read-write
n
0x0
0x0
P1_DOUT
P1_DOUT
P1 Data Output Value
0x48
read-write
n
0x0
0x0
P1_IEN
P1_IEN
P1 Interrupt Enable Control
0x5C
read-write
n
0x0
0x0
P1_IMD
P1_IMD
P1 Interrupt Mode Control
0x58
read-write
n
0x0
0x0
P1_ISRC
P1_ISRC
P1 Interrupt Source Flag
0x60
read-write
n
0x0
0x0
P1_OFFD
P1_OFFD
P1 Digital Input Path Disable Control
0x44
read-write
n
0x0
0x0
P1_PIN
P1_PIN
P1 Pin Value
0x50
read-write
n
0x0
0x0
P1_PMD
P1_PMD
P1 I/O Mode Control
0x40
read-write
n
0x0
0x0
P22_PDIO
P22_PDIO
GPIO P2.2 Pin Data Input/Output
0x248
read-write
n
0x0
0x0
P23_PDIO
P23_PDIO
GPIO P2.3 Pin Data Input/Output
0x24C
read-write
n
0x0
0x0
P24_PDIO
P24_PDIO
GPIO P2.4 Pin Data Input/Output
0x250
read-write
n
0x0
0x0
P25_PDIO
P25_PDIO
GPIO P2.5 Pin Data Input/Output
0x254
read-write
n
0x0
0x0
P26_PDIO
P26_PDIO
GPIO P2.6 Pin Data Input/Output
0x258
read-write
n
0x0
0x0
P2_DBEN
P2_DBEN
P2 De-bounce Enable Control
0x94
read-write
n
0x0
0x0
P2_DMASK
P2_DMASK
P2 Data Output Write Mask
0x8C
read-write
n
0x0
0x0
P2_DOUT
P2_DOUT
P2 Data Output Value
0x88
read-write
n
0x0
0x0
P2_IEN
P2_IEN
P2 Interrupt Enable Control
0x9C
read-write
n
0x0
0x0
P2_IMD
P2_IMD
P2 Interrupt Mode Control
0x98
read-write
n
0x0
0x0
P2_ISRC
P2_ISRC
P2 Interrupt Source Flag
0xA0
read-write
n
0x0
0x0
P2_OFFD
P2_OFFD
P2 Digital Input Path Disable Control
0x84
read-write
n
0x0
0x0
P2_PIN
P2_PIN
P2 Pin Value
0x90
read-write
n
0x0
0x0
P2_PMD
P2_PMD
P2 I/O Mode Control
0x80
read-write
n
0x0
0x0
P30_PDIO
P30_PDIO
GPIO P3.0 Pin Data Input/Output
0x260
read-write
n
0x0
0x0
P31_PDIO
P31_PDIO
GPIO P3.1 Pin Data Input/Output
0x264
read-write
n
0x0
0x0
P32_PDIO
P32_PDIO
GPIO P3.2 Pin Data Input/Output
0x268
read-write
n
0x0
0x0
P34_PDIO
P34_PDIO
GPIO P3.4 Pin Data Input/Output
0x270
read-write
n
0x0
0x0
P35_PDIO
P35_PDIO
GPIO P3.5 Pin Data Input/Output
0x274
read-write
n
0x0
0x0
P36_PDIO
P36_PDIO
GPIO P3.6 Pin Data Input/Output
0x278
read-write
n
0x0
0x0
P3_DBEN
P3_DBEN
P3 De-bounce Enable Control
0xD4
read-write
n
0x0
0x0
P3_DMASK
P3_DMASK
P3 Data Output Write Mask
0xCC
read-write
n
0x0
0x0
P3_DOUT
P3_DOUT
P3 Data Output Value
0xC8
read-write
n
0x0
0x0
P3_IEN
P3_IEN
P3 Interrupt Enable Control
0xDC
read-write
n
0x0
0x0
P3_IMD
P3_IMD
P3 Interrupt Mode Control
0xD8
read-write
n
0x0
0x0
P3_ISRC
P3_ISRC
P3 Interrupt Source Flag
0xE0
read-write
n
0x0
0x0
P3_OFFD
P3_OFFD
P3 Digital Input Path Disable Control
0xC4
read-write
n
0x0
0x0
P3_PIN
P3_PIN
P3 Pin Value
0xD0
read-write
n
0x0
0x0
P3_PMD
P3_PMD
P3 I/O Mode Control
0xC0
read-write
n
0x0
0x0
P46_PDIO
P46_PDIO
GPIO P4.6 Pin Data Input/Output
0x298
read-write
n
0x0
0x0
P47_PDIO
P47_PDIO
GPIO P4.7 Pin Data Input/Output
0x29C
read-write
n
0x0
0x0
P4_DBEN
P4_DBEN
P4 De-bounce Enable Control
0x114
read-write
n
0x0
0x0
P4_DMASK
P4_DMASK
P4 Data Output Write Mask
0x10C
read-write
n
0x0
0x0
P4_DOUT
P4_DOUT
P4 Data Output Value
0x108
read-write
n
0x0
0x0
P4_IEN
P4_IEN
P4 Interrupt Enable Control
0x11C
read-write
n
0x0
0x0
P4_IMD
P4_IMD
P4 Interrupt Mode Control
0x118
read-write
n
0x0
0x0
P4_ISRC
P4_ISRC
P4 Interrupt Source Flag
0x120
read-write
n
0x0
0x0
P4_OFFD
P4_OFFD
P4 Digital Input Path Disable Control
0x104
read-write
n
0x0
0x0
P4_PIN
P4_PIN
P4 Pin Value
0x110
read-write
n
0x0
0x0
P4_PMD
P4_PMD
P4 I/O Mode Control
0x100
read-write
n
0x0
0x0
P50_PDIO
P50_PDIO
GPIO P5.0 Pin Data Input/Output
0x2A0
read-write
n
0x0
0x0
P51_PDIO
P51_PDIO
GPIO P5.1 Pin Data Input/Output
0x2A4
read-write
n
0x0
0x0
P52_PDIO
P52_PDIO
GPIO P5.2 Pin Data Input/Output
0x2A8
read-write
n
0x0
0x0
P53_PDIO
P53_PDIO
GPIO P5.3 Pin Data Input/Output
0x2AC
read-write
n
0x0
0x0
P54_PDIO
P54_PDIO
GPIO P5.4 Pin Data Input/Output
0x2B0
read-write
n
0x0
0x0
P55_PDIO
P55_PDIO
GPIO P5.5 Pin Data Input/Output
0x2B4
read-write
n
0x0
0x0
P5_DBEN
P5_DBEN
P5 De-bounce Enable Control
0x154
read-write
n
0x0
0x0
P5_DMASK
P5_DMASK
P5 Data Output Write Mask
0x14C
read-write
n
0x0
0x0
P5_DOUT
P5_DOUT
P5 Data Output Value
0x148
read-write
n
0x0
0x0
P5_IEN
P5_IEN
P5 Interrupt Enable Control
0x15C
read-write
n
0x0
0x0
P5_IMD
P5_IMD
P5 Interrupt Mode Control
0x158
read-write
n
0x0
0x0
P5_ISRC
P5_ISRC
P5 Interrupt Source Flag
0x160
read-write
n
0x0
0x0
P5_OFFD
P5_OFFD
P5 Digital Input Path Disable Control
0x144
read-write
n
0x0
0x0
P5_PIN
P5_PIN
P5 Pin Value
0x150
read-write
n
0x0
0x0
P5_PMD
P5_PMD
P5 I/O Mode Control
0x140
read-write
n
0x0
0x0
I2C
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2CADDR0
I2CADDR0
I2C Slave Address Register 0
I2CADRR0
0x4
read-write
n
0x0
0x0
GC
General Call Function\n
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2CADDR
I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
I2CADDR1
I2CADDR1
I2C Slave Address Register 1
0x18
read-write
n
0x0
0x0
I2CADDR2
I2CADDR2
I2C Slave Address Register 2
0x1C
read-write
n
0x0
0x0
I2CADDR3
I2CADDR3
I2C Slave Address Register 3
0x20
read-write
n
0x0
0x0
I2CADM0
I2CADM0
I2C Slave Address Mask Register 0
0x24
read-write
n
0x0
0x0
I2CADM
I2C Address Mask Bits\n
1
7
read-write
0
I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register)
0
1
I2C address mask Enabled (the received corresponding address bit is Don't care )
1
I2CADM1
I2CADM1
I2C Slave Address Mask Register 1
0x28
read-write
n
0x0
0x0
I2CADM2
I2CADM2
I2C Slave Address Mask Register 2
0x2C
read-write
n
0x0
0x0
I2CADM3
I2CADM3
I2C Slave Address Mask Register 3
0x30
read-write
n
0x0
0x0
I2CADRR0
I2CADRR0
I2C Slave Address Register 0
0x4
read-write
n
0x0
0x0
I2CCON2
I2CCON2
I2C Control Register 2
0x3C
read-write
n
0x0
0x0
NOSTRETCH
NO STRETCH The I2C BUS\n
2
1
read-write
0
The I2C SCL bus is stretched by hardware if the SI is not cleared in master mode
#0
1
The I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode
#1
OVER_INTEN
I2C OVER RUN Interrupt Control Bit
Setting OVER_INTEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received FIFO.
3
1
read-write
0
Disabled
#0
1
Enabled
#1
TWOFF_EN
TWO LEVEL FIFO Enable Control\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
UNDER_INTEN
I2C UNDER RUN Interrupt Control Bit\nSetting UNDER_INTEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted FIFO.\n
4
1
read-write
0
Disabled
#0
1
Enabled
#1
WAKEUPEN
Wake-up Enable Control
The system can be wake-up by I2C bus when the system is set into power mode and the received data matched one of the addresses in Address Register.
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2CDAT
I2CDAT
I2C DATA Register
0x8
read-write
n
0x0
0x0
I2CDAT
I2C Data Bits\nBit [7:0] is located with the 8-bit transferred data of the I2C serial port.
0
8
read-write
I2CLK
I2CLK
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
I2CLK
I2C Clock Divided Bits\nNote: The minimum value of I2CLK is 4.
0
8
read-write
I2CON
I2CON
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control Bit\n
2
1
read-write
EI
Interrupt Enable Control\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
ENS1
I2C Controller Enable Control\n
6
1
read-write
0
I2C Controller Disabled
#0
1
I2C Controller Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON[7]) is set, the I2C interrupt is requested. SI must be cleared by software. Software can write 1 to clear this bit.
3
1
read-write
STA
I2C START Control Bit\nSetting STA to logic 1 to enter Master mode. I2C hardware sends a START or repeats the START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control Bit
In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the Slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2CSTATUS
I2CSTATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
I2CSTATUS
I2C Status Bits\n
0
8
read-only
I2CSTATUS2
I2CSTATUS2
I2C Status Register 2
0x40
read-write
n
0x0
0x0
EMPTY
I2C TWO LEVEL FIFO EMPTY\n
2
1
read-write
FULL
I2C TWO LEVEL FIFO FULL\n
1
1
read-write
OVERUN
I2C OVER RUN Status Bit
3
1
read-write
UNDERUN
I2C UNDER RUN Status Bit
4
1
read-write
WAKEUPIF
I2C Wake-up Interrupt Flag\nWhen chip is woken up from Power-Down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
I2CTOC
I2CTOC
I2C Time-out Counter Register
0x14
read-write
n
0x0
0x0
DIV4
Time-out Counter Input Clock Divided By 4
Note: When enabled, the time-out period is extended 4 times.
1
1
read-write
0
Time-out counter input clock divided by 4 Disabled
#0
1
Time-out counter input clock divided by 4 Enabled
#1
ENTI
Time-out Counter Enable Control\nNote: When the 14-bit time-out counter is enabled, it will start counting when SI is clear. Setting 1to the SI flag will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TIF
Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nNote: Software can write 1 to clear this bit.
0
1
read-write
INT
INT Register Map
INT
0x0
0x0
0x88
registers
n
IRQ0_SRC
IRQ0_SRC
IRQ0 (BOD) Interrupt Source Identity
0x0
read-only
n
0x0
0x0
INT_SRC
Interrupt Source\nDefine the interrupt sources for interrupt event.
0
3
read-only
IRQ10_SRC
IRQ10_SRC
Reserved
0x28
read-write
n
0x0
0x0
IRQ11_SRC
IRQ11_SRC
Reserved
0x2C
read-write
n
0x0
0x0
IRQ12_SRC
IRQ12_SRC
IRQ12 (UART) Interrupt Source Identity
0x30
read-write
n
0x0
0x0
IRQ13_SRC
IRQ13_SRC
Reserved
0x34
read-write
n
0x0
0x0
IRQ14_SRC
IRQ14_SRC
IRQ14 (SPI) Interrupt Source Identity
0x38
read-write
n
0x0
0x0
IRQ15_SRC
IRQ15_SRC
Reserved
0x3C
read-write
n
0x0
0x0
IRQ16_SRC
IRQ16_SRC
IRQ16 (GP5) Interrupt Source Identity
0x40
read-write
n
0x0
0x0
IRQ17_SRC
IRQ17_SRC
IRQ17 (HIRC Trim) Interrupt Source Identity
0x44
read-write
n
0x0
0x0
IRQ18_SRC
IRQ18_SRC
IRQ18 (I2C) Interrupt Source Identity
0x48
read-write
n
0x0
0x0
IRQ19_SRC
IRQ19_SRC
Reserved
0x4C
read-write
n
0x0
0x0
IRQ1_SRC
IRQ1_SRC
IRQ1 (WDT) Interrupt Source Identity
0x4
read-write
n
0x0
0x0
IRQ20_SRC
IRQ20_SRC
Reserved
0x50
read-write
n
0x0
0x0
IRQ21_SRC
IRQ21_SRC
Reserved
0x54
read-write
n
0x0
0x0
IRQ22_SRC
IRQ22_SRC
Reserved
0x58
read-write
n
0x0
0x0
IRQ23_SRC
IRQ23_SRC
Reserved
0x5C
read-write
n
0x0
0x0
IRQ24_SRC
IRQ24_SRC
Reserved
0x60
read-write
n
0x0
0x0
IRQ25_SRC
IRQ25_SRC
IRQ25 (ACMP) Interrupt Source Identity
0x64
read-write
n
0x0
0x0
IRQ26_SRC
IRQ26_SRC
Reserved
0x68
read-write
n
0x0
0x0
IRQ27_SRC
IRQ27_SRC
Reserved
0x6C
read-write
n
0x0
0x0
IRQ28_SRC
IRQ28_SRC
IRQ28 (PWRWU) Interrupt Source Identity
0x70
read-write
n
0x0
0x0
IRQ29_SRC
IRQ29_SRC
IRQ29 (ADC) Interrupt Source Identity
0x74
read-write
n
0x0
0x0
IRQ2_SRC
IRQ2_SRC
IRQ2 (EINT0) Interrupt Source Identity
0x8
read-write
n
0x0
0x0
IRQ30_SRC
IRQ30_SRC
Reserved
0x78
read-write
n
0x0
0x0
IRQ31_SRC
IRQ31_SRC
Reserved
0x7C
read-write
n
0x0
0x0
IRQ3_SRC
IRQ3_SRC
IRQ3 (EINT1) Interrupt Source Identity
0xC
read-write
n
0x0
0x0
IRQ4_SRC
IRQ4_SRC
IRQ4 (GP0/1) Interrupt Source Identity
0x10
read-write
n
0x0
0x0
IRQ5_SRC
IRQ5_SRC
IRQ5 (GP2/3/4) Interrupt Source Identity
0x14
read-write
n
0x0
0x0
IRQ6_SRC
IRQ6_SRC
IRQ6 (PWM) Interrupt Source Identity
0x18
read-write
n
0x0
0x0
IRQ7_SRC
IRQ7_SRC
IRQ7 (BRAKE) Interrupt Source Identity
0x1C
read-write
n
0x0
0x0
IRQ8_SRC
IRQ8_SRC
IRQ8 (TMR0) Interrupt Source Identity
0x20
read-write
n
0x0
0x0
IRQ9_SRC
IRQ9_SRC
IRQ9 (TMR1) Interrupt Source Identity
0x24
read-write
n
0x0
0x0
MCU_IRQ
MCU_IRQ
MCU IRQ Number Identity Register
0x84
read-write
n
0x0
0x0
MCU_IRQ
MCU IRQ Source\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. This modes to generate interrupt to Cortex-M0 - the normal mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0, setting MCU_IRQ[n] to 1 will generate an interrupt to Cortex-M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting MCU_IRQ[n] 0 has no effect.
0
32
read-write
NMI_CON
NMI_CON
NMI Source Interrupt Select Control Register
0x80
read-write
n
0x0
0x0
NMI_SEL
NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL.
0
5
read-write
NMI_SEL_EN
NMI Interrupt Enable Control (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
8
1
read-write
0
NMI interrupt Disabled
#0
1
NMI interrupt Enabled
#1
PWM
PWM Register Map
PWM
0x0
0x0
0x3C
registers
n
0x54
0x34
registers
n
CMR0
CMR0
PWM Comparator Register 0
0x24
read-write
n
0x0
0x0
CMRn
PWM Comparator Bits\nNote: Any write to CMRn will take effect in next PWM cycle.
0
16
read-write
CMR1
CMR1
PWM Comparator Register 1
0x28
read-write
n
0x0
0x0
CMR2
CMR2
PWM Comparator Register 2
0x2C
read-write
n
0x0
0x0
CMR3
CMR3
PWM Comparator Register 3
0x30
read-write
n
0x0
0x0
CMR4
CMR4
PWM Comparator Register 4
0x34
read-write
n
0x0
0x0
CMR5
CMR5
PWM Comparator Register 5
0x38
read-write
n
0x0
0x0
CNR0
CNR0
PWM Counter Register 0
0xC
read-write
n
0x0
0x0
CNRn
PWM Counter/Timer Loaded Value\nNote: Any write to CNRn will take effect in next PWM cycle.
0
16
read-write
CNR1
CNR1
PWM Counter Register 1
0x10
read-write
n
0x0
0x0
CNR2
CNR2
PWM Counter Register 2
0x14
read-write
n
0x0
0x0
CNR3
CNR3
PWM Counter Register 3
0x18
read-write
n
0x0
0x0
CNR4
CNR4
PWM Counter Register 4
0x1C
read-write
n
0x0
0x0
CNR5
CNR5
PWM Counter Register 5
0x20
read-write
n
0x0
0x0
CSR
CSR
PWM Clock Select Register
0x4
read-write
n
0x0
0x0
CSR0
Timer 0 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
0
3
read-write
CSR1
Timer 1 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
4
3
read-write
CSR2
Timer 2 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
8
3
read-write
CSR3
Timer 3 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
12
3
read-write
CSR4
Timer 4 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
16
3
read-write
CSR5
Timer 5 Clock Source Selection\nSelect clock input for PWM timer.\n
20
3
read-write
0
Input Clock Divided by 2
#000
1
Input Clock Divided by 4
#001
2
Input Clock Divided by 8
#010
3
Input Clock Divided by 16
#011
4
Input Clock Divided by 1
#100
INTACCUCTL
INTACCUCTL
Period Interrupt Accumulation Control Register
0x84
-1
read-write
n
0x0
0x0
INTACCUEN0
Interrupt Accumulation Function Enable Control\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
PERIODCNT
Interrupt Accumulation Bits\nWhen INTACCUEN0 is set, PERIODCNT will decrease when every PWMPIF0 flag is set and when PERIODCNT reach to zero, the PWM0 interrupt will occurred and PERIODCNT will reload itself.
4
4
read-write
PCR
PCR
PWM Control Register
0x8
read-write
n
0x0
0x0
CH0EN
PWM-timer 0 Enable/Disable Start Run\n
0
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CH0INV
PWM-timer 0 Output Inverter Enable Control\n
2
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH0MOD
PWM-timer 0 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR0 and CMR0 cleared.
3
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH1EN
PWM-timer 1 Enable/Disable Start Run\n
4
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CH1INV
PWM-timer 1 Output Inverter ON/OFF\n
6
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
CH1MOD
PWM-timer 1 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR1 and CMR1 cleared.
7
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH2EN
PWM-timer 2 Enable/Disable Start Run\n
8
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CH2INV
PWM-timer 2 Output Inverter Enable Control\n
10
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH2MOD
PWM-timer 2 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR2 and CMR2 cleared.
11
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH3EN
PWM-timer 3 Enable/Disable Start Run\n
12
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CH3INV
PWM-timer 3 Output Inverter Enable Control\n
14
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH3MOD
PWM-timer 3 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR3 and CMR3 cleared.
15
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH4EN
PWM-timer 4 Enable/Disable Start Run\n
16
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CH4INV
PWM-timer 4 Output Inverter Enable Control\n
18
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH4MOD
PWM-timer 4 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR4 and CMR4 cleared.
19
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH5EN
PWM-timer 5 Enable/Disable Start Run\n
20
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CH5INV
PWM-timer 5 Output Inverter Enable Control\n
22
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH5MOD
PWM-timer 5 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR5 and CMR5 cleared.
23
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CLRPWM
Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware.
27
1
read-write
0
Do not clear PWM counter
#0
1
All 16-bit PWM counters cleared to 0x0000
#1
DB_MODE
PWM Debug Mode Configuration Bit (Available In DEBUG Mode Only)\n
1
1
read-write
0
Safe mode: The timer is frozen and PWM outputs are shut down Safe state for the inverter. The timer can still be re-started from where it stops
#0
1
Normal mode: The timer continues to operate normally May be dangerous in some cases since a constant duty cycle is applied to the inverter (no more interrupts serviced)
#1
DZEN01
Dead-zone 0 Generator Enable Control (PWM0 And PWM1 Pair For PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group.
24
1
read-write
0
Disabled
#0
1
Enabled
#1
DZEN23
Dead-zone 2 Generator Enable Control (PWM2 And PWM3 Pair For PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group.
25
1
read-write
0
Disabled
#0
1
Enabled
#1
DZEN45
Dead-zone 4 Generator Enable Control (PWM4 And PWM5 Pair For PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM4 and PWM5 becomes a complementary pair for PWM group.
26
1
read-write
0
Disabled
#0
1
Enabled
#1
GRP
Group Bit\n
30
1
read-write
0
The signals timing of all PWM channels are independent
#0
1
Unify the signals timing of PWM0, PWM2 and PWM4 in the same phase which is controlled by PWM0 and also unify the signals timing of PWM1, PWM3 and PWM5 in the same phase which is controlled by PWM1
#1
PWMMOD
PWM Operating Mode Selection\n
28
2
read-write
0
Independent mode
#00
1
Complementary mode
#01
2
Synchronized mode
#10
3
Reserved
#11
PWMTYPE
PWM Aligned Type Selection Bit\n
31
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
PDZIR
PDZIR
PWM Dead-zone Interval Register
0x64
read-write
n
0x0
0x0
DZI01
Dead-zone Interval Register For Pair Of Channel0 And Channel1 (PWM0 And PWM1 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
0
8
read-write
DZI23
Dead-zone Interval Register For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
8
8
read-write
DZI45
Dead-zone Interval Register For Pair Of Channel4 And Channel5 (PWM4 And PWM5 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
16
8
read-write
PFBCON
PFBCON
PWM Fault Brake Control Register
0x60
read-write
n
0x0
0x0
BKEN0
Enable BKP0 Pin Trigger Fault Brake Function 0\n
0
1
read-write
0
Disabling BKP0 pin can trigger brake function 0 (EINT0 or CPO1)
#0
1
Enabling a falling at BKP0 pin can trigger brake function 0
#1
BKEN1
Enable BKP1 Pin Trigger Fault Brake Function 1\n
1
1
read-write
0
Disabling BKP1 pin can trigger brake function 1 (EINT1 or CPO0)
#0
1
Enabling a falling at BKP1 pin can trigger brake function 1
#1
BKF
PWM Fault Brake Event Flag (Write 1 Clear)\nSoftware can write 1 to clear this bit and must clear this bit before restart PWM counter.
7
1
read-write
0
PWM output initial state when fault brake conditions asserted
#0
1
PWM output fault brake state when fault brake conditions asserted
#1
CPO0BKEN
BKP1 Fault Brake Function Source Selection\n
2
1
read-write
0
EINT1 as one brake source in BKP1
#0
1
CPO0 as one brake source in BKP1
#1
CPO1BKEN
BKP0 Fault Brake Function Source Selection\n
3
1
read-write
0
EINT0 as one brake source in BKP0
#0
1
CPO1 as one brake source in BKP0
#1
D6BKO6
D6 Brake Output Select Bit\n
30
1
read-write
0
D6 output low when fault brake conditions asserted
#0
1
D6 output high when fault brake conditions asserted
#1
D7BKO7
D7 Brake Output Select Bit\n
31
1
read-write
0
D7 output low when fault brake conditions asserted
#0
1
D7 output high when fault brake conditions asserted
#1
PWMBKO0
PWM Channel 0 Brake Output Select Bit\n
24
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
PWMBKO1
PWM Channel 1 Brake Output Select Bit\n
25
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
PWMBKO2
PWM Channel 2 Brake Output Select Bit\n
26
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
PWMBKO3
PWM Channel 3 Brake Output Select Bit\n
27
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
PWMBKO4
PWM Channel 4 Brake Output Select Bit\n
28
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
PWMBKO5
PWM Channel 5 Brake Output Select Bit\n
29
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
PHCHG
PHCHG
Phase Change Register
0x78
-1
read-write
n
0x0
0x0
ACCNT0
Hardware Auto Clear CE0 When ACMP0 Trigger It\n
14
1
read-write
0
Enabled
#0
1
Disabled
#1
ACCNT1
Hardware Auto Clear CE1 When ACMP1 Trigger It\n
15
1
read-write
0
Enabled
#0
1
Disabled
#1
CE0
ACMP0 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set.
31
1
read-write
0
Disabled
#0
1
Enabled
#1
CE1
ACMP1 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set.
23
1
read-write
0
Disabled
#0
1
Enabled
#1
CH01TOFF0
Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application
Note: Only for PWM0, PWM1, PWM2, PWM3.
24
1
read-write
0
Disabled
#0
1
Enabled
#1
CH01TOFF1
Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application
Note: only for PWM0,PWM1,PWM2,PWM3.
16
1
read-write
0
Disabled
#0
1
Enabled
#1
CH11TOFF0
Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application
Note: Only for PWM0, PWM1, PWM2, PWM3.
25
1
read-write
0
Disabled
#0
1
Enabled
#1
CH11TOFF1
Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application
Note: Only for PWM0, PWM1, PWM2, PWM3.
17
1
read-write
0
Disabled
#0
1
Enabled
#1
CH21TOFF0
Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application
Note: Only for PWM0, PWM1, PWM2, PWM3.
26
1
read-write
0
Disabled
#0
1
Enabled
#1
CH21TOFF1
Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application
Note: Only for PWM0, PWM1, PWM2, PWM3.
18
1
read-write
0
Disabled
#0
1
Enabled
#1
CH31TOFF0
Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application
Note: Only for PWM0, PWM1, PWM2, PWM3.
27
1
read-write
0
Disabled
#0
1
Enabled
#1
CH31TOFF1
Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application
Note: Only for PWM0, PWM1, PWM2, PWM3.
19
1
read-write
0
Disabled
#0
1
Enabled
#1
CMP0SEL
CMP0SEL\nSelect the positive input source of ACMP0.\n
28
2
read-write
0
Select P1.5 as the input of ACMP0
#00
1
Select P1.0 as the input of ACMP0
#01
2
Select P1.2 as the input of ACMP0
#10
3
Select P1.3 as the input of ACMP0
#11
CMP1SEL
CMP1SEL\nSelect the positive input source of ACMP1.\n
20
2
read-write
0
Select P3.1 as the input of ACMP1
#00
1
Select P3.2 as the input of ACMP1
#01
2
Select P3.3 as the input of ACMP1
#10
3
Select P3.4 as the input of ACMP1
#11
D0
D0: When PWM0 Is Zero, Channel 0's Output Waveform Is D0\n
0
1
read-write
0
Output low
#0
1
Output high
#1
D1
D1: When PWM1 Is Zero, Channel 1's Output Waveform Is D1\n
1
1
read-write
0
Output low
#0
1
Output high
#1
D2
D2: When PWM2 Is Zero, Channel 2's Output Waveform Is D2\n
2
1
read-write
0
Output low
#0
1
Output high
#1
D3
D3: When PWM3 Is Zero, Channel 3's Output Waveform Is D3\n
3
1
read-write
0
Output low
#0
1
Output high
#1
D4
D4: When PWM4 Is Zero, Channel 4's Output Waveform Is D4\n
4
1
read-write
0
Output low
#0
1
Output high
#1
D5
D5: When PWM5 Is Zero, Channel 5's Output Waveform Is D5\n
5
1
read-write
0
Output low
#0
1
Output high
#1
D6
D6: When MASK6 Is 1, Channel 6's Output Waveform Is D6\n
6
1
read-write
0
Output low
#0
1
Output high
#1
D7
D7: When MASK7 Is 1, Channel 7's Output Waveform Is D7\n
7
1
read-write
0
Output low
#0
1
Output high
#1
PWM0
PWM Channel 0 Output Enable Control\n
8
1
read-write
0
Output D0 specified in bit 0 of PHCHG register
#0
1
Output the original channel 0 waveform
#1
PWM1
PWM Channel 1 Output Enable Control\n
9
1
read-write
0
Output D1 specified in bit 1 of PHCHG register
#0
1
Output the original channel 1 waveform
#1
PWM2
PWM Channel 2 Output Enable Control\n
10
1
read-write
0
Output D2 specified in bit 2 of PHCHG register
#0
1
Output the original channel 2 waveform
#1
PWM3
PWM Channel 3 Output Enable Control\n
11
1
read-write
0
Output D3 specified in bit 3 of PHCHG register
#0
1
Output the original channel 3 waveform
#1
PWM4
PWM Channel 4 Output Enable Control\n
12
1
read-write
0
Output D4 specified in bit 4 of PHCHG register
#0
1
Output the original channel 4 waveform
#1
PWM5
PWM Channel 5 Output Enable Control\n
13
1
read-write
0
Output D5 specified in bit 5 of PHCHG register
#0
1
Output the original channel 5 waveform
#1
T0
Timer0 Trigger PWM Function Enable Control\nWhen this bit is set, timer0 time-out event will update PHCHG with PHCHG_NXT register.
30
1
read-write
0
Disabled
#0
1
Enabled
#1
T1
Timer1 Trigger PWM Function Enable Control\nWhen this bit is set, timer1 time-out event will update PHCHG with PHCHG_NXT register.
22
1
read-write
0
Disabled
#0
1
Enabled
#1
PHCHGMASK
PHCHGMASK
Phase Change MASK Register
0x80
read-write
n
0x0
0x0
CMPMASK0
MASK For ACMP0
Note: Register CMP0CR is describe in Comparator Controller chapter
8
1
read-write
0
The input of ACMP is controlled by CMP0CR
#0
1
The input of ACMP is controlled by CMP0SEL of PHCHG register
#1
CMPMASK1
MASK For ACMP1\nNote: Register CMP1CR is describe in Comparator Controller chapter
9
1
read-write
0
The input of ACMP is controlled by CMP1CR
#0
1
The input of ACMP is controlled by CMP1SEL of PHCHG register
#1
MASK6
MASK For D6
6
1
read-write
0
Original GPIO P0.1
#0
1
D6
#1
MASK7
MASK For D7
7
1
read-write
0
Original GPIO P0.0
#0
1
D7
#1
PHCHGNXT
PHCHGNXT
Next Phase Change Register
0x7C
-1
read-write
n
0x0
0x0
ACCNT0
Hardware Auto Clear CE0 When ACMP0 Trigger It\n
14
1
read-write
0
Enabled
#0
1
Disabled
#1
ACCNT1
Hardware Auto Clear CE1 When ACMP1 Trigger It\n
15
1
read-write
0
Enabled
#0
1
Disabled
#1
CE0
ACMP0 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set.
31
1
read-write
0
Disabled
#0
1
Enabled
#1
CE1
ACMP1 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set.
23
1
read-write
0
Disabled
#0
1
Enabled
#1
CH01TOFF0
Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application
Note: Only for PWM0, PWM1, PWM2, PWM3.
24
1
read-write
0
Disabled
#0
1
Enabled
#1
CH01TOFF1
Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application
Note: only for PWM0,PWM1,PWM2,PWM3.
16
1
read-write
0
Disabled
#0
1
Enabled
#1
CH11TOFF0
Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application
Note: Only for PWM0, PWM1, PWM2, PWM3.
25
1
read-write
0
Disabled
#0
1
Enabled
#1
CH11TOFF1
Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application
Note: Only for PWM0, PWM1, PWM2, PWM3.
17
1
read-write
0
Disabled
#0
1
Enabled
#1
CH21TOFF0
Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application
Note: Only for PWM0, PWM1, PWM2, PWM3.
26
1
read-write
0
Disabled
#0
1
Enabled
#1
CH21TOFF1
Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application
Note: Only for PWM0, PWM1, PWM2, PWM3.
18
1
read-write
0
Disabled
#0
1
Enabled
#1
CH31TOFF0
Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application
Note: Only for PWM0, PWM1, PWM2, PWM3.
27
1
read-write
0
Disabled
#0
1
Enabled
#1
CH31TOFF1
Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application
Note: Only for PWM0, PWM1, PWM2, PWM3.
19
1
read-write
0
Disabled
#0
1
Enabled
#1
CMP0SEL
CMP0SEL\nSelect the positive input source of ACMP0.\n
28
2
read-write
0
Select P1.5 as the input of ACMP0
#00
1
Select P1.0 as the input of ACMP0
#01
2
Select P1.2 as the input of ACMP0
#10
3
Select P1.3 as the input of ACMP0
#11
CMP1SEL
CMP1SEL\nSelect the positive input source of ACMP1.\n
20
2
read-write
0
Select P3.1 as the input of ACMP1
#00
1
Select P3.2 as the input of ACMP1
#01
2
Select P3.3 as the input of ACMP1
#10
3
Select P3.4 as the input of ACMP1
#11
D0
D0: When PWM0 Is Zero, Channel 0's Output Waveform Is D0\n
0
1
read-write
0
Output low
#0
1
Output high
#1
D1
D1: When PWM1 Is Zero, Channel 1's Output Waveform Is D1\n
1
1
read-write
0
Output low
#0
1
Output high
#1
D2
D2: When PWM2 Is Zero, Channel 2's Output Waveform Is D2\n
2
1
read-write
0
Output low
#0
1
Output high
#1
D3
D3: When PWM3 Is Zero, Channel 3's Output Waveform Is D3\n
3
1
read-write
0
Output low
#0
1
Output high
#1
D4
D4: When PWM4 Is Zero, Channel 4's Output Waveform Is D4\n
4
1
read-write
0
Output low
#0
1
Output high
#1
D5
D5: When PWM5 Is Zero, Channel 5's Output Waveform Is D5\n
5
1
read-write
0
Output low
#0
1
Output high
#1
D6
D6: When MASK6 Is 1, Channel 6's Output Waveform Is D6\n
6
1
read-write
0
Output low
#0
1
Output high
#1
D7
D7: When MASK7 Is 1, Channel 7's Output Waveform Is D7\n
7
1
read-write
0
Output low
#0
1
Output high
#1
PWM0
PWM Channel 0 Output Enable Control\n
8
1
read-write
0
Output D0 specified in bit 0 of PHCHG register
#0
1
Output the original channel 0 waveform
#1
PWM1
PWM Channel 1 Output Enable Control\n
9
1
read-write
0
Output D1 specified in bit 1 of PHCHG register
#0
1
Output the original channel 1 waveform
#1
PWM2
PWM Channel 2 Output Enable Control\n
10
1
read-write
0
Output D2 specified in bit 2 of PHCHG register
#0
1
Output the original channel 2 waveform
#1
PWM3
PWM Channel 3 Output Enable Control\n
11
1
read-write
0
Output D3 specified in bit 3 of PHCHG register
#0
1
Output the original channel 3 waveform
#1
PWM4
PWM Channel 4 Output Enable Control\n
12
1
read-write
0
Output D4 specified in bit 4 of PHCHG register
#0
1
Output the original channel 4 waveform
#1
PWM5
PWM Channel 5 Output Enable Control\n
13
1
read-write
0
Output D5 specified in bit 5 of PHCHG register
#0
1
Output the original channel 5 waveform
#1
T0
Timer0 Trigger PWM Function Enable Control\nWhen this bit is set, timer0 time-out event will update PHCHG with PHCHG_NXT register.
30
1
read-write
0
Disabled
#0
1
Enabled
#1
T1
Timer1 Trigger PWM Function Enable Control\nWhen this bit is set, timer1 time-out event will update PHCHG with PHCHG_NXT register.
22
1
read-write
0
Disabled
#0
1
Enabled
#1
PIER
PIER
PWM Interrupt Enable Control Register
0x54
read-write
n
0x0
0x0
BRKIE
Fault Brake0 And 1 Interrupt Enable Control\n
16
1
read-write
0
Disabling flags BKF0 and BKF1 to trigger PWM interrupt
#0
1
Enabling flags BKF0 and BKF1 can trigger PWM interrupt
#1
INT_TYPE
PWM Interrupt Type Selection Bit\nNote: This bit is effective when PWM in central align mode only.
17
1
read-write
0
PWMPIFn will be set if PWM counter underflows
#0
1
PWMPIFn will be set if PWM counter matches CNRn register
#1
PWMDIE0
PWM Channel 0 Duty Interrupt Enable Control\n
8
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE1
PWM Channel 1 Duty Interrupt Enable Control\n
9
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE2
PWM Channel 2 Duty Interrupt Enable Control\n
10
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE3
PWM Channel 3 Duty Interrupt Enable Control\n
11
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE4
PWM Channel 4 Duty Interrupt Enable Control\n
12
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE5
PWM Channel 5 Duty Interrupt Enable Control\n
13
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMPIE0
PWM Channel 0 Period Interrupt Enable Control\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMPIE1
PWM Channel 1 Period Interrupt Enable Control\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMPIE2
PWM Channel 2 Period Interrupt Enable Control\n
2
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMPIE3
PWM Channel 3 Period Interrupt Enable Control\n
3
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMPIE4
PWM Channel 4 Period Interrupt Enable Control\n
4
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMPIE5
PWM Channel 5 Period Interrupt Enable Control\n
5
1
read-write
0
Disabled
#0
1
Enabled
#1
PIIR
PIIR
PWM Interrupt Indication Register
0x58
read-write
n
0x0
0x0
BKF0
PWM Brake0 Flag\nNote: Software can write 1 to clear this bit.
16
1
read-write
0
PWM Brake does not recognize a falling signal at BKP0
#0
1
When PWM Brake detects a falling signal at pin BKP0, this flag will be set to high
#1
BKF1
PWM Brake1 Flag\nNote: Software can write 1 to clear this bit.
17
1
read-write
0
PWM Brake does not recognize a falling signal at BKP1
#0
1
When PWM Brake detects a falling signal at pin BKP1, this flag will be set to high
#1
PWMDIF0
PWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when a channel 0 PWM counter reaches CMR0 in down-count direction. \nNote: Software can write 1 to clear this bit.
8
1
read-write
PWMDIF1
PWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when a channel 1 PWM counter reaches CMR1 in down-count direction. \nNote: Software can write 1 to clear this bit.
9
1
read-write
PWMDIF2
PWM Channel 2 Duty Interrupt Flag\nFlag is set by hardware when a channel 2 PWM counter reaches CMR2 in down-count direction. \nNote: Software can write 1 to clear this bit.
10
1
read-write
PWMDIF3
PWM Channel 3 Duty Interrupt Flag\nFlag is set by hardware when a channel 3 PWM counter reaches CMR3 in down-count direction. \nNote: Software can write 1 to clear this bit.
11
1
read-write
PWMDIF4
PWM Channel 4 Duty Interrupt Flag\nFlag is set by hardware when a channel 4 PWM counter reaches CMR4 in down-count direction. \nNote: Software can write 1 to clear this bit.
12
1
read-write
PWMDIF5
PWM Channel 5 Duty Interrupt Flag\nFlag is set by hardware when a channel 5 PWM counter reaches CMR5 in down-count direction. \nNote: Software can write 1 to clear this bit.
13
1
read-write
PWMPIF0
PWM Channel 0 Period Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
0
1
read-write
PWMPIF1
PWM Channel 1 Period Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
1
1
read-write
PWMPIF2
PWM Channel 2 Period Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
2
1
read-write
PWMPIF3
PWM Channel 3 Period Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
3
1
read-write
PWMPIF4
PWM Channel 4 Period Interrupt Flag\nFlag is set by hardware when PWM4 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
4
1
read-write
PWMPIF5
PWM Channel 5 Period Interrupt Flag\nFlag is set by hardware when PWM5 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
5
1
read-write
PPR
PPR
PWM Pre-scale Register
0x0
read-write
n
0x0
0x0
CP01
Clock Prescaler 0 For PWM Counter 0 And 1
Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter.
0
8
read-write
CP23
Clock Prescaler 2 For PWM Counter 2 And 3\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter.\n
8
8
read-write
CP45
Clock Prescaler 4 For PWM Counter 4 And 5\nClock input is divided by (CP45 + 1) before it is fed to the corresponding PWM counter.\n
16
8
read-write
PWMPOE
PWMPOE
PWM Output Enable for Channel 0~5
0x5C
read-write
n
0x0
0x0
PWM0
PWM Channel 0 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
0
1
read-write
0
PWM channel 0 output to pin Disabled
#0
1
PWM channel 0 output to pin Enabled
#1
PWM1
PWM Channel 1 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
1
1
read-write
0
PWM channel 1 output to pin Disabled
#0
1
PWM channel 1 output to pin Enabled
#1
PWM2
PWM Channel 2 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
2
1
read-write
0
PWM channel 2 output to pin Disabled
#0
1
PWM channel 2 output to pin Enabled
#1
PWM3
PWM Channel 3 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
3
1
read-write
0
PWM channel 3 output to pin Disabled
#0
1
PWM channel 3 output to pin Enabled
#1
PWM4
PWM Channel 4 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
4
1
read-write
0
PWM channel 4 output to pin Disabled
#0
1
PWM channel 4 output to pin Enabled
#1
PWM5
PWM Channel 5 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
5
1
read-write
0
PWM channel 5 output to pin Disabled
#0
1
PWM channel 5 output to pin Enabled
#1
TRGCON0
TRGCON0
PWM Trigger Control Register 0
0x68
read-write
n
0x0
0x0
CM0TRGFEN
Enable PWM Trigger ADC Function While Channel0's Counter Matching CMR0 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
CM0TRGREN
Enable PWM Trigger ADC Function While Channel0's Counter Matching CMR0 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CM1TRGFEN
Enable PWM Trigger ADC Function While Channel1's Counter Matching CMR1 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
10
1
read-write
0
Disabled
#0
1
Enabled
#1
CM1TRGREN
Enable PWM Trigger ADC Function While Channel1's Counter Matching CMR1 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
8
1
read-write
0
Disabled
#0
1
Enabled
#1
CM2TRGFEN
Enable PWM Trigger ADC Function While Channel2's Counter Matching CMR2 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
18
1
read-write
0
Disabled
#0
1
Enabled
#1
CM2TRGREN
Enable PWM Trigger ADC Function While Channel2's Counter Matching CMR2 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
16
1
read-write
0
Disabled
#0
1
Enabled
#1
CM3TRGFEN
Enable PWM Trigger ADC Function While Channel3's Counter Matching CMR3 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
26
1
read-write
0
Disabled
#0
1
Enabled
#1
CM3TRGREN
Enable PWM Trigger ADC Function While Channel3's Counter Matching CMR3 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
24
1
read-write
0
Disabled
#0
1
Enabled
#1
CNT0TRGEN
Enable PWM Trigger ADC Function While Channel0's Counter Matching CNR0\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
CNT1TRGEN
Enable PWM Trigger ADC Function While Channel1's Counter Matching CNR1\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
9
1
read-write
0
Disabled
#0
1
Enabled
#1
CNT2TRGEN
Enable PWM Trigger ADC Function While Channel2's Counter Matching CNR2\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
17
1
read-write
0
Disabled
#0
1
Enabled
#1
CNT3TRGEN
Enable PWM Trigger ADC Function While Channel3's Counter Matching CNR3\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
25
1
read-write
0
Disabled
#0
1
Enabled
#1
P0TRGEN
Enable PWM Trigger ADC Function While Channel0's Counter Matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode.
3
1
read-write
0
Disabled
#0
1
Enabled
#1
P1TRGEN
Enable PWM Trigger ADC Function While Channel1's Counter Matching 0 \nNote: This bit is valid for both center aligned mode and edged aligned mode.
11
1
read-write
0
Disabled
#0
1
Enabled
#1
P2TRGEN
Enable PWM Trigger ADC Function While Channel2's Counter Matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode.
19
1
read-write
0
Disabled
#0
1
Enabled
#1
P3TRGEN
Enable PWM Trigger ADC Function While Channel3's Counter Matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode.
27
1
read-write
0
Disabled
#0
1
Enabled
#1
TRGCON1
TRGCON1
PWM Trigger Control Register 1
0x6C
read-write
n
0x0
0x0
CM4TRGFEN
Enable PWM Trigger ADC Function While Channel4's Counter Matching CMR4 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
CM4TRGREN
Enable PWM Trigger ADC Function While Channel4's Counter Matching CMR4 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CM5TRGFEN
Enable PWM Trigger ADC Function While Channel5's Counter Matching CMR5 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
10
1
read-write
0
Disabled
#0
1
Enabled
#1
CM5TRGREN
Enable PWM Trigger ADC Function While Channel5's Counter Matching CMR5 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
8
1
read-write
0
Disabled
#0
1
Enabled
#1
CNT4TRGEN
Enable PWM Trigger ADC Function While Channel4's Counter Matching CNR4\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
CNT5TRGEN
Enable PWM Trigger ADC Function While Channel5's Counter Matching CNR5\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
9
1
read-write
0
Disabled
#0
1
Enabled
#1
P4TRGEN
Enable PWM Trigger ADC Function While Channel4's Counter Matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode.
3
1
read-write
0
Disabled
#0
1
Enabled
#1
P5TRGEN
Enable PWM Trigger ADC Function While Channel5's Counter Matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode.
11
1
read-write
0
Disabled
#0
1
Enabled
#1
TRGSTS0
TRGSTS0
PWM Trigger Status Register 0
0x70
read-write
n
0x0
0x0
CMR0FLAG_F
ADC Trigger Flag By Counting Down To CMR\nNote: Software can write 1 to clear this bit.
2
1
read-write
CMR0FLAG_R
ADC Trigger Flag By Counting Up To CMR\nNote: Software can write 1 to clear this bit.
0
1
read-write
CMR1FLAG_F
ADC Trigger Flag By Counting Down To CMR\nNote: Software can write 1 to clear this bit.
10
1
read-write
CMR1FLAG_R
ADC Trigger Flag By Counting Up To CMR\nNote: Software can write 1 to clear this bit.
8
1
read-write
CMR2FLAG_F
ADC Trigger Flag By Counting Down To CMR\nNote: Software can write 1 to clear this bit.
18
1
read-write
CMR2FLAG_R
ADC Trigger Flag By Counting Up To CMR \nNote: Software can write 1 to clear this bit.
16
1
read-write
CMR3FLAG_F
When Counter Counting Down To CMR, This Bit Will Be Set For Trigger ADC\nNote: Software can write 1 to clear this bit.
26
1
read-write
CMR3FLAG_R
When Counter Counting Up To CMR, This Bit Will Be Set For Trigger ADC\nNote: Software can write 1 to clear this bit.
24
1
read-write
CNT0FLAG
ADC Trigger Flag By Counting To CNR
Note: Software can write 1 to clear this bit.
1
1
read-write
CNT1FLAG
ADC Trigger Flag By Counting To CNR
Note: Software can write 1 to clear this bit.
9
1
read-write
CNT2FLAG
ADC Trigger Flag By Counting To CNR
Note: Software can write 1 to clear this bit.
17
1
read-write
CNT3FLAG
When Counter Counting To CNR, This Bit Will Be Set For Trigger ADC\nNote: Software can write 1 to clear this bit.
25
1
read-write
PERID0FLAG
ADC Trigger Flag By Period \nNote: Software can write 1 to clear this bit.
3
1
read-write
PERID1FLAG
ADC Trigger Flag By Period \nNote: Software can write 1 to clear this bit.
11
1
read-write
PERID2FLAG
ADC Trigger Flag By Period \nNote: Software can write 1 to clear this bit.
19
1
read-write
PERID3FLAG
When Counter Counting To Period, This Bit Will Be Set For Trigger ADC \nNote: Software can write 1 to clear this bit.
27
1
read-write
TRGSTS1
TRGSTS1
PWM Trigger Status Register 1
0x74
read-write
n
0x0
0x0
CMR4FLAG_F
ADC Trigger Flag By Counting Down To CMR\nNote: Software can write 1 to clear this bit.
2
1
read-write
CMR4FLAG_R
ADC Trigger Flag By Counting Up To CMR\nNote: Software can write 1 to clear this bit.
0
1
read-write
CMR5FLAG_F
ADC Trigger Flag By Counting Down To CMR\nNote: Software can write 1 to clear this bit.
10
1
read-write
CMR5FLAG_R
ADC Trigger Flag By Counting Up To CMR\nNote: Software can write 1 to clear this bit.
8
1
read-write
CNT4FLAG
ADC Trigger Flag By Counting To CNR\nNote: Software can write 1 to clear this bit.
1
1
read-write
CNT5FLAG
ADC Trigger Flag By Counting To CNR\nNote: Software can write 1 to clear this bit.
9
1
read-write
PERID4FLAG
ADC Trigger Flag By Period \nNote: Software can write 1 to clear this bit.
3
1
read-write
PERID5FLAG
ADC Trigger Flag By Period \nNote: Software can write 1 to clear this bit.
11
1
read-write
SCS
SCS Register Map
SCS
0x0
0x10
0xC
registers
n
0x100
0x4
registers
n
0x180
0x4
registers
n
0x200
0x4
registers
n
0x280
0x4
registers
n
0x400
0x20
registers
n
0xD00
0x8
registers
n
0xD0C
0x8
registers
n
0xD1C
0x8
registers
n
AIRCR
AIRCR
Application Interrupt and Reset Control Register
0xD0C
-1
read-write
n
0x0
0x0
SYSRESETREQ
System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence.
2
1
read-write
VECTCLRACTIVE
Exception Active Status Clear Bit\nReserved for debug use. When writing to the register, user must write 0 to this bit, otherwise behavior is unpredictable.
1
1
read-write
VECTORKEY
Register Access Key\nWrite:\nWhen writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.\nRead:\nRead as 0xFA05.
16
16
read-write
CPUID
CPUID
CPUID Register
0xD00
-1
read-only
n
0x0
0x0
IMPLEMENTER
Implementer Code\n
24
8
read-only
PART
Architecture Of The Processor\nRead as 0xC for ARMv6-M parts.
16
4
read-only
PARTNO
Part Number Of The Processor\nRead as 0xC20.
4
12
read-only
REVISION
Revision Number\nRead as 0x0.
0
4
read-only
ICSR
ICSR
Interrupt Control State Register
0xD04
read-write
n
0x0
0x0
ISRPENDING
Interrupt Pending Flag, Excluding NMI And Faults\nThis bit is read only.
22
1
read-write
0
Interrupt not pending
#0
1
Interrupt pending
#1
ISRPREEMPT
Interrupt Preemption Bit\nIf set, a pending exception will be serviced on exit from the debug halt state.\nThis bit is read only.
23
1
read-write
NMIPENDSET
NMI Set-pending Bit\nWrite:\nNote: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
31
1
read-write
0
No effect.\nNMI exception not pending
#0
1
Changes NMI exception state to pending.\nNMI exception pending
#1
PENDSTCLR
SysTick Exception Clear-pending Bit
Write:
Note: This bit is write-only. When you want to clear PENDST bit, you must write 0 to PENDSTSET and write 1 to PENDSTCLR at the same time.
25
1
read-write
0
No effect
#0
1
Removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick Exception Set-pending Bit\nWrite:\n
26
1
read-write
0
No effect.\nSysTick exception is not pending
#0
1
Changes SysTick exception state to pending.\nSysTick exception is pending
#1
PENDSVCLR
PendSV Clear-pending Bit
Write:
Note: This bit is write-only. To clear the PENDSV bit, you must write 0 to PENDSVSET and write 1 to PENDSVCLR at the same time.
27
1
read-write
0
No effect
#0
1
Removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV Set-pending Bit\nWrite:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
No effect.\nPendSV exception is not pending
#0
1
Changes PendSV exception state to pending.\nPendSV exception is pending
#1
VECTACTIVE
Contains The Active Exception Number\nThis bit is read only.
0
9
read-write
0
Thread mode
0
VECTPENDING
Exception Number Of The Highest Priority Pending Enabled Exception\nThis bit is read only.
12
9
read-write
0
No pending exceptions
0
NVIC_ICER
NVIC_ICER
IRQ0 ~ IRQ31 Clear-enable Control Register
0x180
read-write
n
0x0
0x0
CLRENA
Interrupt Disable Control\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite:\nRead value indicates the current enable status.
0
32
read-write
0
No effect.\nAssociated interrupt status Disabled
0
1
Write 1 to disable associated interrupt.\nAssociated interrupt status Enabled
1
NVIC_ICPR
NVIC_ICPR
IRQ0 ~ IRQ31 Clear-pending Control Register
0x280
read-write
n
0x0
0x0
CLRPEND
Clear Interrupt Pending Bits\nWrite:\nRead value indicates the current pending status.
0
32
read-write
0
No effect.\nAssociated interrupt in not in pending status
0
1
Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status
1
NVIC_IPR0
NVIC_IPR0
IRQ0 ~ IRQ3 Interrupt Priority Control Register
0x400
read-write
n
0x0
0x0
PRI_0
Priority Of IRQ0\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_1
Priority Of IRQ1\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_2
Priority Of IRQ2\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_3
Priority Of IRQ3\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR1
NVIC_IPR1
IRQ4 ~ IRQ7 Interrupt Priority Control Register
0x404
read-write
n
0x0
0x0
PRI_4
Priority Of IRQ4\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_5
Priority Of IRQ5\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_6
Priority Of IRQ6\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_7
Priority Of IRQ7\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR2
NVIC_IPR2
IRQ8 ~ IRQ11 Interrupt Priority Control Register
0x408
read-write
n
0x0
0x0
PRI_10
Priority Of IRQ10\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_11
Priority Of IRQ11\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
PRI_8
Priority Of IRQ8\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_9
Priority Of IRQ9\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
NVIC_IPR3
NVIC_IPR3
IRQ12 ~ IRQ15 Interrupt Priority Control Register
0x40C
read-write
n
0x0
0x0
PRI_12
Priority Of IRQ12\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_13
Priority Of IRQ13\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_14
Priority Of IRQ14\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_15
Priority Of IRQ15\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR4
NVIC_IPR4
IRQ16 ~ IRQ19 Interrupt Priority Control Register
0x410
read-write
n
0x0
0x0
PRI_16
Priority Of IRQ16\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_17
Priority Of IRQ17\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_18
Priority Of IRQ18\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_19
Priority Of IRQ19\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR5
NVIC_IPR5
IRQ20 ~ IRQ23 Interrupt Priority Control Register
0x414
read-write
n
0x0
0x0
PRI_20
Priority Of IRQ20\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_21
Priority Of IRQ21\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_22
Priority Of IRQ22\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_23
Priority Of IRQ23\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR6
NVIC_IPR6
IRQ24 ~ IRQ27 Interrupt Priority Control Register
0x418
read-write
n
0x0
0x0
PRI_24
Priority Of IRQ24\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_25
Priority Of IRQ25\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_26
Priority Of IRQ26\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_27
Priority Of IRQ27\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR7
NVIC_IPR7
IRQ28 ~ IRQ31 Interrupt Priority Control Register
0x41C
read-write
n
0x0
0x0
PRI_28
Priority Of IRQ28\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_29
Priority Of IRQ29\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_30
Priority Of IRQ30\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_31
Priority Of IRQ31\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_ISER
NVIC_ISER
IRQ0 ~ IRQ31 Set-enable Control Register
0x100
read-write
n
0x0
0x0
SETENA
Interrupt Enable Control\nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite:\nRead value indicates the current enable status.
0
32
read-write
0
No effect.\nAssociated interrupt status Disabled
0
1
Write 1 to enable associated interrupt.\nAssociated interrupt status Enabled
1
NVIC_ISPR
NVIC_ISPR
IRQ0 ~ IRQ31 Set-pending Control Register
0x200
read-write
n
0x0
0x0
SETPEND
Set Interrupt Pending Bits\nWrite:\nRead value indicates the current pending status.
0
32
read-write
0
No effect.\nAssociated interrupt in not in pending status
0
1
Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status
1
SCR
SCR
System Control Register
0xD10
read-write
n
0x0
0x0
SEVONPEND
Send Event On Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded
#0
1
Enabled events and all interrupts, including disabled interrupts, can wake-up the processor
#1
SLEEPDEEP
Processor Deep Sleep And Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode:\n
2
1
read-write
0
Sleep mode
#0
1
Deep Sleep mode
#1
SLEEPONEXIT
Sleep-on-exit Enable\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
0
Do not sleep when returning to Thread mode
#0
1
Enter Sleep, or Deep Sleep, on return from ISR to Thread mode
#1
SHPR2
SHPR2
System Handler Priority Register 2
0xD1C
read-write
n
0x0
0x0
PRI_11
Priority Of System Handler 11 - SVCall\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
SHPR3
SHPR3
System Handler Priority Register 3
0xD20
read-write
n
0x0
0x0
PRI_14
Priority Of System Handler 14 - PendSV\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_15
Priority Of System Handler 15 - SysTick\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
SYST_CSR
SYST_CSR
SysTick Control and Status Register
0x10
read-write
n
0x0
0x0
CLKSRC
System Tick Clock Source Selection\n
2
1
read-write
0
Clock source is optional, refer to STCLK_S
#0
1
Core clock used for SysTick timer
#1
COUNTFLAG
System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-write
ENABLE
System Tick Counter Enable Control\n
0
1
read-write
0
Counter Disabled
#0
1
Counter Enabled and will operate in a multi-shot manner
#1
TICKINT
System Tick Interrupt Enabled\n
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to 0 has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended
#1
SYST_CVR
SYST_CVR
SysTick Current Value Register
0x18
read-write
n
0x0
0x0
CURRENT
System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value Register).
0
24
read-write
SYST_RVR
SYST_RVR
SysTick Reload Value Register
0x14
read-write
n
0x0
0x0
RELOAD
System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0.
0
24
read-write
SPI
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x3C
0xC
registers
n
CNTRL
SPI_CNTRL
SPI Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity\n
11
1
read-write
0
SPICLK idle low
#0
1
SPICLK idle high
#1
FIFO
FIFO Mode Enable Control
Note 1: Before enabling FIFO mode, the other related settings should be set in advance.
Note 2: In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data into the 4-depth transmit FIFO. When all data stored at transmit FIFO buffer are transferred, the GO_BUSY bit will back to 0.
21
1
read-write
0
FIFO Mode Disabled
#0
1
FIFO Mode Enabled
#1
GO_BUSY
SPI Transfer Control Bit And Busy Status\nIf FIFO mode is enabled, this bit will be controlled by hardware and is Read only.\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote 1: When FIFO mode is disabled, all configurations should be ready before writing 1 to the GO_BUSY bit.\nNote 2: In SPI Slave mode, if FIFO mode is disabled and the SPI bus clock is kept at idle state during a data transfer, the GO_BUSY bit will not be cleared to 0 when slave select signal goes to inactive state.
0
1
read-write
0
Writing 0 to this bit to stop data transfer if SPI is transferring
#0
1
In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Unit-transfer Interrupt Enable Control\n
17
1
read-write
0
SPI unit-transfer interrupt Disabled
#0
1
SPI unit-transfer interrupt Enabled
#1
IF
Unit-transfer Interrupt Flag
Note 1: This bit will be cleared by writing 1 to itself.
Note 2: It's a mutual mirror bit of SPI_STATUS[16].
16
1
read-write
0
The transfer does not finish yet
#0
1
The SPI controller has finished one unit transfer
#1
LSB
LSB First\n
10
1
read-write
0
The MSB is transmitted/received first
#0
1
The LSB is transmitted/received first
#1
REORDER
Byte Reorder Function\nNote: This setting is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.
19
1
read-write
0
Byte reorder function Disabled
#0
1
Byte reorder function Enabled
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CNTRL[24].
24
1
read-only
0
The receive FIFO buffer is not empty
#0
1
The receive FIFO buffer is empty
#1
RX_FULL
Receive FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[25]
25
1
read-only
0
The receive FIFO buffer is not full
#0
1
The receive FIFO buffer is full
#1
RX_NEG
Receive On Negative Edge\n
1
1
read-write
0
The received data input signal latched on the Rising edge of SPICLK
#0
1
The received data input signal latched on the Falling edge of SPICLK
#1
SLAVE
Slave Mode Control\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)
The four bits provide configurable suspend interval between two successive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation:
(SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle
Example:
12
4
read-write
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits are transmitted in one transmit/receive. The minimum bit length is 8 bits and can up to 32 bits.\n
3
5
read-write
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STAUTS[26].
26
1
read-only
0
The transmit FIFO buffer is not empty
#0
1
The transmit FIFO buffer is empty
#1
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[27].
27
1
read-only
0
The transmit FIFO buffer is not full
#0
1
The transmit FIFO buffer is full
#1
TX_NEG
Transmit On Negative Edge\n
2
1
read-write
0
The transmitted data output signal is driven on the Rising edge of SPICLK
#0
1
The transmitted data output signal is driven on the Falling edge of SPICLK
#1
CNTRL2
SPI_CNTRL2
SPI Control and Status Register 2
0x3C
read-write
n
0x0
0x0
BCn
Clock Configuration Backward Compatible Option\nNote: Refer to the description of SPI_DIVIDER register for details.
31
1
read-write
0
The clock configuration is backward compatible
#0
1
The clock configuration is not backward compatible
#1
NOSLVSEL
Slave 3-wire Mode Enable Control (Slave Only)
The SPI controller work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI
Note: In Slave 3-wire mode, the SS_LTRIG bit (SPI_SSR[4]) shall be set as 1.
8
1
read-write
0
The controller is 4-wire bi-direction interface
#0
1
The controller is 3-wire bi-direction interface in Slave mode. The controller will be ready to transmit/receive data after the GO_BUSY bit is set to 1
#1
SLV_ABORT
Slave 3-wire Mode Abort Control Bit (Slave Only)\nIn normal operation, there is an interrupt event when the number of received bits meets the requirement which defined in TX_BIT_LEN.\nIf the number of received bits is less than the requirement and there is no more bus clock input over one transfer time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a unit transfer interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
9
1
read-write
0
No force the transfer done when the NOSLVSEL bit is set to 1
#0
1
Force the transfer done when the NOSLVSEL bit is set to 1
#1
SLV_START_INTSTS
Slave 3-wire Mode Start Interrupt Status (Slave Only)
This bit dedicates if a transaction has started in slave 3-wire mode.
Note 1: It will be cleared automatically when a transaction is done or by writing 1 to this bit.
Note 2: It is a mutual mirror bit of SPI_STATUS[11].
11
1
read-write
0
Slave does not detect any SPI bus clock transfer since the SSTA_INTEN bit was set to 1
#0
1
The transfer has started in slave 3-wire mode.
#1
SSTA_INTEN
Slave 3-wire Mode Start Interrupt Enable Control (Slave Only)\nIt is used to enable interrupt when the transfer has started in slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, user can set the SLV_ABORT bit to force the transfer done.\nNote: It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared to 0.
10
1
read-write
0
Transaction start interrupt Disabled
#0
1
Transaction start interrupt Enabled
#1
SS_INT_OPT
Slave Select Inactive Interrupt Option (Slave Only)\nNote: This setting is only available if the SPI controller is configured as level trigger in slave device.
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
DIVIDER
SPI_DIVIDER
SPI Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider Bits (Master Only)\nThe value in this field is the frequency divider to determine the SPI peripheral clock frequency fspi, and the SPI master's bus clock frequency on the SPICLK output pin. The frequency is obtained according to the following equation:\nIf the bit of BCn, SPI_CNTRL2[31], is set to 0.\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source which is defined in the CLKSEL1 register.
0
8
read-write
FIFO_CTL
SPI_FIFO_CTL
SPI FIFO Control Register
0x40
-1
read-write
n
0x0
0x0
RXOV_INTEN
Receive FIFO Overrun Interrupt Enable Control\n
6
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RX_CLR
Clear Receive FIFO Buffer\nNote: This bit will be cleared to 0 by hardware after software sets it to 1 and the receive FIFO is cleared.
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer
#1
RX_INTEN
Receive Threshold Interrupt Enable Control\n
2
1
read-write
0
Receive threshold interrupt Disabled
#0
1
Receive threshold interrupt Enabled
#1
RX_THRESHOLD
Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
24
2
read-write
TIMEOUT_INTEN
Receive FIFO Time-out Interrupt Enable Control\n
21
1
read-write
0
Time-out interrupt Disabled
#0
1
Time-out interrupt Enabled
#1
TX_CLR
Clear Transmit FIFO Buffer\nNote: This bit will be cleared to 0 by hardware after software sets it to 1 and the transmit FIFO is cleared.
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer
#1
TX_INTEN
Transmit Threshold Interrupt Enable Control\n
3
1
read-write
0
Transmit threshold interrupt Disabled
#0
1
Transmit threshold interrupt Enabled
#1
TX_THRESHOLD
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
28
2
read-write
RX
SPI_RX
SPI Data Receive Register
0x10
read-only
n
0x0
0x0
RX
Data Receive Bits (Read Only)\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, bit RX [7:0] holds the received data. The values of the other bits are unknown.
0
32
read-only
SSR
SPI_SSR
SPI Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit (Master Only)\n
3
1
read-write
0
SPISS pin signal will be asserted/de-asserted by setting /clearing SSR bit
#0
1
SPISS pin signal will be generated automatically, which means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Flag (Read Only, Slave Only)
When the SS_LTRIG bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not.
5
1
read-only
0
The transaction number or the transferred bit length of one transaction does not meet the specified requirements
#0
1
The transaction number and the transferred bit length met the specified requirements which defined in TX_BIT_LEN
#1
SSR
Slave Select Control Bit (Master Only)\nIf AUTOSS bit is 0,\n
0
1
read-write
0
Set the SPISS line to inactive state.\nKeep the SPISS line at inactive state
#0
1
Set the proper SPISS line to active state.\nSelect the SPISS line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time. The active state of SPISS is specified in SS_LVL bit
#1
SS_LTRIG
Slave Select Level Trigger Enable Bit (Slave Only)\n
4
1
read-write
0
The input slave select signal is edge-trigger
#0
1
The input slave select signal is level-trigger
#1
SS_LVL
Slave Select Active Level (Slave Only)\nIt defines the active status of slave select signal (SPISS).\nIf SS_LTRIG bit is 1:\n
2
1
read-write
0
The slave select signal SPISS is active at Low-level.\nThe slave select signal SPISS is active at Falling-edge
#0
1
The slave select signal SPISS is active at High-level.\nThe slave select signal SPISS is active at Rising-edge
#1
STATUS
SPI_STATUS
SPI Status Register
0x44
-1
read-write
n
0x0
0x0
IF
SPI Unit-transfer Interrupt Flag\nNote 1: This bit will be cleared by writing 1 to itself.\nNote 2: It's a mutual mirror bit of SPI_CNTRL[16].
16
1
read-write
0
The transfer does not finish yet
#0
1
The SPI controller has finished one unit transfer
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CNTRL[24].
24
1
read-only
0
The receive FIFO buffer is not empty
#0
1
The receive FIFO buffer is empty
#1
RX_FIFO_COUNT
Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer.
12
4
read-only
RX_FULL
Receive FIFO Buffer Full Indicator (Read Only) \nNote: It's a mutual mirror bit of SPI_CNTRL[25].
25
1
read-only
0
The receive FIFO buffer is not full
#0
1
The receive FIFO buffer is full
#1
RX_INTSTS
Receive FIFO Threshold Interrupt Status (Read Only)\n
0
1
read-only
0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
#1
RX_OVERRUN
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
0
No overrun in receive FIFO
#0
1
Overrun in receive FIFO
#1
SLV_START_INTSTS
Slave Start Interrupt Status (Slave Only)\nIt is used to dedicate that the transfer has started in slave 3-wire mode. \nNote 1: It will be cleared as transfer done or by writing one to this bit.\nNote 2: It's a mutual mirror bit of SPI_CNTRL2[11].
11
1
read-write
0
Slave does not detect any SPI bus clock transfer since the SSTA_INTEN bit was set to 1
#0
1
The transfer has started in slave 3-wire mode
#1
TIMEOUT
Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
20
1
read-write
0
No receive FIFO time-out event
#0
1
The receive FIFO buffer is not empty and it does not be read over 64 SPI clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only) \nNote: It's a mutual mirror bit of SPI_CNTRL[26].
26
1
read-only
0
The transmit FIFO buffer is not empty
#0
1
The transmit FIFO buffer is empty
#1
TX_FIFO_COUNT
Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer.
28
4
read-only
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CNTRL[27].
27
1
read-only
0
The transmit FIFO buffer is not full
#0
1
The transmit FIFO buffer is full
#1
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (Read Only)\n
4
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
#1
TX
SPI_TX
SPI Data Transmit Register
0x20
write-only
n
0x0
0x0
TX
Data Transmit Bits (Write Only)\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bit TX [7:0] will be transmitted in next transfer.
0
32
write-only
TMR
TMR Register Map
TMR
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TCAP0
TCAP0
Timer0 Capture Data Register
0x10
read-only
n
0x0
0x0
TCAP
Timer Capture Data Register\nWhen TEXIF flag is set to 1, the current TDR value will be auto-loaded into this TCAP filed immediately.
0
24
read-only
TCAP1
TCAP1
Timer1 Capture Data Register
0x30
read-write
n
0x0
0x0
TCMPR0
TCMPR0
Timer0 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.
0
24
read-write
TCMPR1
TCMPR1
Timer1 Compare Register
0x24
read-write
n
0x0
0x0
TCSR0
TCSR0
Timer0 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CACT
Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CAP_SRC
Capture Pin Source Selection\n
19
1
read-write
0
Capture Function source is from TxEX pin
#0
1
Capture Function source is from ACMPx output signal
#1
CEN
Timer Enable Control\n
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
CRST
Timer Reset\n
26
1
read-write
0
No effect
#0
1
Reset 8-bit prescale counter, 24-bit up counter value and CEN bit if CACT is 1
#1
CTB
Counter Mode Enable Control\nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 6.12.5.3 for detail description.\n
24
1
read-write
0
External event counter mode Disabled
#0
1
External event counter mode Enabled
#1
DBGACK_TMR
ICE Debug Mode Acknowledge Disable Control (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
IE
Interrupt Enable Control\nIf this bit is enabled, when the timer interrupt flag (TIF) is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer Interrupt function Disabled
#0
1
Timer Interrupt function Enabled
#1
MODE
Timer Operating Mode\n
27
2
read-write
PERIODIC_SEL
Periodic Mode Behavior Selection\n
17
1
read-write
0
In One-shot or Periodic mode, when write new TCMP, timer counter will reset
#0
1
In One-shot or Periodic mode, when write new TCMP if new TCMP TDR(current counter) , timer counter keep counting and will not reset. If new TCMP = TDR(current counter) , timer counter will reset
#1
PRESCALE
Prescale Counter\n
0
8
read-write
TDR_EN
Data Load Enable Control\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n
16
1
read-write
0
Timer Data Register update Disabled
#0
1
Timer Data Register update Enabled while Timer counter is active
#1
TOUT_PIN
Toggle Out Pin Selection\nWhen Timer is set to toggle mode,\n
18
1
read-write
0
Time0/1 toggle output pin is T0/T1 pin
#0
1
Time0/1 toggle output pin is T0EX/T1EX pin
#1
WAKE_EN
Wake-up Enable Control\nWhen WAKE_EN (UA_IER[6]) is set and the TIF or TEXIF (TEXISR[0]) is set, the timer controller will generator a wake-up trigger event to CPU.\n
23
1
read-write
0
Wake-up trigger event Disabled
#0
1
Wake-up trigger event Enabled
#1
TCSR1
TCSR1
Timer1 Control and Status Register
0x20
read-write
n
0x0
0x0
TDR0
TDR0
Timer0 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register\nIf TDR_EN (TCSRx[16]) is set to 1, TDR register value will be updated continuously to monitor 24-bit up counter value.
0
24
read-only
TDR1
TDR1
Timer1 Data Register
0x2C
read-write
n
0x0
0x0
TEXCON0
TEXCON0
Timer0 External Control Register
0x14
read-write
n
0x0
0x0
CAP_MODE
Capture Mode Selection\n
8
1
read-write
0
Timer counter reset function or free-counting mode of timer capture function
#0
1
Trigger-counting mode of timer capture function
#1
RSTCAPSEL
Timer External Reset Counter / Timer External Capture Mode Selection\n
4
1
read-write
0
Transition on TxEX (x = 0~1) pin is using to save the TDR value into TCAP value if TEXIF flag is set to 1
#0
1
Transition on TxEX (x = 0~1) pin is using to reset the 24-bit up counter
#1
TCDB
Timer External Counter Input Pin De-bounce Enable Control\n
7
1
read-write
0
Tx (x = 0~1) pin de-bounce Disabled
#0
1
Tx (x = 0~1) pin de-bounce Enabled
#1
TEXDB
Timer External Capture Input Pin De-bounce Enable Control\n
6
1
read-write
0
TxEX (x = 0~1) pin de-bounce Disabled
#0
1
TxEX (x = 0~1) pin de-bounce Enabled
#1
TEXEN
Timer External Pin Function Enable Control\n
3
1
read-write
0
RSTCAPSEL function of TxEX (x = 0~1) pin will be ignored
#0
1
RSTCAPSEL function of TxEX (x = 0~1) pin is active
#1
TEXIEN
Timer External Capture Interrupt Enable Control\nIf TEXIEN enabled, Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1.
5
1
read-write
0
TxEX (x = 0~1) pin detection Interrupt Disabled
#0
1
TxEX (x = 0~1) pin detection Interrupt Enabled
#1
TEX_EDGE
Timer External Pin Edge Detection\n
1
2
read-write
0
A 1 to 0 transition on TxEX (x = 0~1) will be detected
#00
1
A 0 to 1 transition on TxEX (x = 0~1) will be detected
#01
2
Either 1 to 0 or 0 to 1 transition on TxEX (x = 0~1) will be detected
#10
3
Reserved
#11
TX_PHASE
Timer External Count Pin Phase Detect Selection\n
0
1
read-write
0
A falling edge of Tx (x = 0~1) pin will be counted
#0
1
A rising edge of Tx (x = 0~1) pin will be counted
#1
TEXCON1
TEXCON1
Timer1 External Control Register
0x34
read-write
n
0x0
0x0
TEXISR0
TEXISR0
Timer0 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
TEXIF
Timer External Interrupt Flag\nThis bit indicates the external capture interrupt flag status\nNote: This bit is cleared by writing 1 to it
0
1
read-write
0
TxEX (x = 0, 1) pin interrupt did not occur
#0
1
TxEX (x = 0, 1) pin interrupt occurred
#1
TEXISR1
TEXISR1
Timer1 External Interrupt Status Register
0x38
read-write
n
0x0
0x0
TISR0
TISR0
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
TDR value matches the TCMP value
#1
TWF
Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of Time.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated
#1
TISR1
TISR1
Timer1 Interrupt Status Register
0x28
read-write
n
0x0
0x0
UART
UART Register Map
UART
0x0
0x0
0x30
registers
n
UA_ALT_CSR
UA_ALT_CSR
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address Match Value\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: This bit cannot be active with RS485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation Mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation Mode (AAD) Enabled
#1
RS485_ADD_EN
RS-485 Address Detection Enable Control\nThis bit is used to enable RS-485 Address Detection mode.\nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
RS-485 address detection mode Disabled
#0
1
RS-485 address detection mode Enabled
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD) Control\nNote: This bit cannot be active with RS485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Address Detection Operation Mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation Mode (AAD) Enabled
#1
RS485_NMM
RS-485 Normal Multi-drop Operation Mode (NMM) Control\nNote: This bit cannot be active with RS485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation Mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation Mode (NMM) Enabled
#1
UA_BAUD
UA_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BRD
Baud Rate Divider\nThe field indicates the baud rate divider.
0
16
read-write
DIVIDER_X
Divider X\n
24
4
read-write
DIV_X_EN
Divider X Enable Control\nNote: When in IrDA mode, this bit must be disabled.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
#1
DIV_X_ONE
Divider X Equal 1
Refer to section UART Controller Baud Rate Generator for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 8)
#1
UA_FCR
UA_FCR
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (RDA_INT) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL then the RDA_IF will be set (if RDA_IEN in UA_IER register is enable, an interrupt will generated).\n
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RFR
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles.
1
1
read-write
0
No effect
#0
1
The RX internal state machine and pointers reset
#1
RTS_TRI_LEV
RTS Trigger Level (For Auto-flow Control Use)\nNote: This field is used for RTS auto-flow control.
16
4
read-write
0
RTS Trigger Level is 1 byte
#0000
1
RTS Trigger Level is 4 bytes
#0001
2
RTS Trigger Level is 8 bytes
#0010
3
RTS Trigger Level is 14 bytes
#0011
RX_DIS
Receiver Disable Control
The receiver is disabled or not (setting 1 to disable the receiver).
Note1: This field is only used for RS-485 Normal Multi-drop mode. It should be programmed firstly to avoid receiving unknown data before RS-485_NMM (UA_ALT_CSR [8]) is programmed.
Note2: After RS-485 receives an address byte in RS-485 Normal Multi-drop mode, this bit (RX_DIS) will be cleared to 0 by hardware.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
TFR
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles.
2
1
read-write
0
No effect
#0
1
The TX internal state machine and pointers reset
#1
UA_FSR
UA_FSR
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
BIF
Break Interrupt Flag (Read Only)
This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
Note: This bit is read only, but software can write 1 to clear it.
6
1
read-only
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit follows the last data bit or parity bit is detected as as logic 0).
Note: This bit is read only, but can be cleared by writing '1' to it .
5
1
read-only
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit .
4
1
read-only
0
No parity error is generated
#0
1
Parity error is generated.Note: This bit is read only, but can be cleared by writing '1' to it
#1
RS_485_ADD_DETF
RS-485 Address Byte Detection Flag \nNote1: This field is used for RS-485 function mode.\nNote2: This bit is cleared by writing 1 to it.
3
1
read-write
RX_EMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RX_FULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RX_OVER_IF
RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 16 bytes, this bit will be set.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RX_POINTER
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15. When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 15.
8
6
read-only
TE_FLAG
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TX_EMPTY
Transmitter FIFO Empty (Read Only)
This bit indicates TX FIFO is empty or not.
Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TX_FULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TX_OVER_IF
TX Overflow Error Interrupt Flag\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is cleared by writing 1 to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TX_POINTER
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15. When the using level of TX FIFO Buffer equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 15.
16
6
read-only
UA_FUN_SEL
UA_FUN_SEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Selection\n
0
2
read-write
0
UART function mode
#00
1
Reserved
#01
2
IrDA function mode
#10
3
RS-485 function mode
#11
UA_IER
UA_IER
UART Interrupt Enable Control Register
0x4
read-write
n
0x0
0x0
AUTO_CTS_EN
CTS Auto Flow Control Enable Control\nNote: When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
CTS auto flow control Disabled
#0
1
CTS auto flow control Enabled
#1
AUTO_RTS_EN
RTS Auto Flow Control Enable Control\nNote: When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will de-assert RTS signal.
12
1
read-write
0
RTS auto flow control Disabled
#0
1
RTS auto flow control Enabled
#1
BUF_ERR_IEN
Buffer Error Interrupt Enable Control\n
5
1
read-write
0
INT_BUF_ERR Masked Disabled
#0
1
INT_BUF_ERR Enabled
#1
MODEM_IEN
Modem Status Interrupt Enable Control\n
3
1
read-write
0
MODEM_INT Masked off
#0
1
MODEM_INT Enabled
#1
RDA_IEN
Receive Data Available Interrupt Enable Control\n
0
1
read-write
0
RDA_INT Masked off
#0
1
RDA_INT Enabled
#1
RLS_IEN
Receive Line Status Interrupt Enable Control\n
2
1
read-write
0
RLS_INT Masked off
#0
1
RLS_INT Enabled
#1
RTO_IEN
RX Time-out Interrupt Enable Control\n
4
1
read-write
0
TOUT_INT Masked off
#0
1
TOUT_INT Enabled
#1
THRE_IEN
Transmit Holding Register Empty Interrupt Enable Control\n
1
1
read-write
0
THRE_INT Masked off
#0
1
THRE_INT Enabled
#1
TIME_OUT_EN
Time-out Counter Enable Control\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
WAKE_EN
Wake-up CPU Function Enable Control
Note: when the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode.
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART Wake-up function Enabled
#1
UA_IRCR
UA_IRCR
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
INV_RX
INV_RX\n
6
1
read-write
0
No inversion
#0
1
Inverse RX input signal
#1
INV_TX
INV_TX\n
5
1
read-write
0
No inversion
#0
1
Inverse TX output signal
#1
TX_SELECT
TX_SELECT\n
1
1
read-write
0
IrDA receiver Enabled
#0
1
IrDA transmitter Enabled
#1
UA_ISR
UA_ISR
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUF_ERR_IF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX/RX FIFO overflow flag (TX_OVER_IF or RX_OVER_IF) is set. \nWhen BUF_ERR_IF is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TX_OVER_IF and RX_OVER_IF are cleared.
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUF_ERR_INT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
buffer error interrupt is generated
#1
MODEM_IF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEM_INT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDA_IF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDA_INT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLS_IF
Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF, FEF, PEF and RS485_ADD_DETF are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLS_INT
Receive Line Status Interrupt (Read Only)
This bit is set if RLS_IEN and RLS_IF are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER [1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
1
1
read-only
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THRE_INT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TOUT_IF
Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RTO_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
4
1
read-only
0
No Time-out interrupt flag is generated
#0
1
Time-out interrupt flag is generated
#1
TOUT_INT
Time-out Interrupt Indicator (Read Only)\nThis bit is set if RTO_IEN and TOUT_IF are both set to 1.\n
12
1
read-only
0
No Time-out interrupt is generated
#0
1
Time-out interrupt is generated
#1
UA_LCR
UA_LCR
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.\n
6
1
read-write
0
Break control Disabled
#0
1
Break control Enabled
#1
EPE
Even Parity Enable Control\nThis bit has effect only when PBE (UA_LCR[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number Of STOP Bit
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-, 7- and 8-bti word length, 2 STOP bit is generated in the transmitted data
#1
PBE
Parity Bit Enable Control\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable Control\n
5
1
read-write
0
Stick parity Disabled
#0
1
If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
0
Word length is 5-bit
#00
1
Word length is 6-bit
#01
2
Word length is 7-bit
#10
3
Word length is 8-bit
#11
UA_MCR
UA_MCR
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
LEV_RTS
RTS Pin Active Level
This bit defines the active level state of RTS pin output.
Note1: Refer to and UART function mode.
Note2: Refer to and for RS-485 function mode.
9
1
read-write
0
RTS pin output is high level active
#0
1
RTS pin output is low level active
#1
RTSn
RTS (Request-to-send) Signal Control\nThis bit is direct control internal RTS signal active or not, and then drive the RTS pin output with LEV_RTS bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control (AUTO_RTS_EN) is enabled in UART function mode.\nNote2: This RTS signal control bit is not effective when RS-485 auto direction mode (RS485_AUD) is enabled in RS-485 function mode.
1
1
read-write
0
RTS signal is active
#0
1
RTS signal is inactive
#1
RTS_ST
RTS Pin State (Read Only)\nThis bit mirror from RTS pin output of voltage logic status.\n
13
1
read-only
0
RTS pin output is low level voltage logic state
#0
1
RTS pin output is high level voltage logic state
#1
UA_MSR
UA_MSR
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTS_ST
CTS Pin Status (Read Only)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected.
4
1
read-only
0
CTS pin input is low level voltage logic state
#0
1
CTS pin input is high level voltage logic state
#1
DCTSF
Detect CTS State Change Flag\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
CTS input has not change state
#0
1
CTS input has change state
#1
LEV_CTS
CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to
8
1
read-write
0
CTS pin input is high level active
#0
1
CTS pin input is low level active
#1
UA_RBR
UA_RBR
UART Receive Buffer Register
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Bits (Read Only)\nBy reading this register, the UART Controller will return an 8-bit data received from RX pin (LSB first).
0
8
read-only
UA_THR
UA_THR
UART Transmit Holding Register
UA_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Bits\nBy writing to this register, the UART sends out an 8-bit data through the TX pin (LSB first).
0
8
write-only
UA_TOR
UA_TOR
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value\nThis field is used to program the transfer delay time between the last stop bit and next start bit.
8
8
read-write
TOIC
Time-out Interrupt Comparator\n
0
8
read-write
WDT
WDT Register Map
WDT
0x0
0x0
0x4
registers
n
WTCR
WTCR
Watchdog Timer Control Register
0x0
-1
read-write
n
0x0
0x0
DBGACK_WDT
ICE Debug Mode Acknowledge Disable Control (Write Protect)\nWDT up counter will keep going no matter CPU is hanging by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects WDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
WTE
Watchdog Timer Enable Control (Write Protect)\n
7
1
read-write
0
WDT Disabled. (This action will reset the internal up counter value.)
#0
1
WDT Enabled
#1
WTIE
Watchdog Timer Time-out Interrupt Enable Control (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.\n
6
1
read-write
0
WDT time-out interrupt Disabled
#0
1
WDT time-out interrupt Enabled
#1
WTIF
Watchdog Timer Time-out Interrupt Flag\nThis bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it.
3
1
read-write
0
WDT time-out interrupt did not occur
#0
1
WDT time-out interrupt occurred
#1
WTIS
Watchdog Timer Interval Selection\nThese three bits select the time-out interval for the Watchdog Timer.\n
8
3
read-write
0
24 * TWDT
#000
1
26 * TWDT
#001
2
28 * TWDT
#010
3
210 * TWDT
#011
4
212 * TWDT
#100
5
214 * TWDT
#101
6
216 * TWDT
#110
7
218 * TWDT
#111
WTR
Reset Watchdog Timer Up Counter (Write Protect)\nNote: This bit will be automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Reset the internal 18-bit WDT up counter value
#1
WTRE
Watchdog Timer Time-out Reset Enable Control (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period (1024 * TWDT) expires.\n
1
1
read-write
0
WDT time-out reset function Disabled
#0
1
WDT time-out reset function Enabled
#1
WTRF
Watchdog Timer Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
2
1
read-write
0
WDT time-out reset did not occur
#0
1
WDT time-out reset occurred
#1
WTWKE
Watchdog Timer Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1, while WTIF is generated to 1 and WTIE enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
4
1
read-write
0
Wake-up trigger event Disabled if WDT time-out interrupt signal generated
#0
1
Wake-up trigger event Enabled if WDT time-out interrupt signal generated
#1
WTWKF
Watchdog Timer Time-out Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of WDT.\nNote: This bit is cleared by writing 1 to it.
5
1
read-write
0
WDT does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated
#1