nuvoTon MINI51XAE_v1 2024.04.27 MINI51XAE_v1 SVD file 8 32 ACMP ACMP Register Map ACMP 0x0 0x0 0x10 registers n CTL0 ACMP_CTL0 Analog Comparator 0 Control Register 0x0 read-write n 0x0 0x0 ACMPEN Analog Comparator 0 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after this bit is set. 0 1 read-write 0 Analog Comparator 0 Disabled #0 1 Analog Comparator 1 Enabled #1 ACMPIE Analog Comparator 0 Interrupt Enable Control 1 1 read-write 0 Interrupt function Disabled #0 1 Interrupt function Enabled #1 FTRGEN Analog Comparator 0 Falling Edge Trigger Enable\nNote: The bit is only effective while analog comparator 0 triggers PWM or Timer. 9 1 read-write 0 Analog comparator 0 falling edge trigger PWM or Timer enabled #0 1 Analog comparator 0 falling edge trigger disabled #1 HYSSEL Analog Comparator 0 Hysteresis Selection 2 2 read-write 0 CMP0 Hysteresis Disabled #00 1 CMP0 Hysteresis typical range is 15mV #01 2 CMP0 Hysteresis typical range is 90mV #10 3 Same as 00 #11 NEGSEL Analog Comparator 0 Negative Input Selection 4 1 read-write 0 The source of the negative comparator input is from CPN0 pin #0 1 The source of the negative comparator input is from internal band-gap voltage or comparator reference voltage #1 POSSEL Analog Comparator 0 Positive Input Selection 29 2 read-write 0 CPP0 is from P1.5 pin #00 1 CPP0 is from P1.0 pin #01 2 CPP0 is from P1.2 pin #10 3 CPP0 is from P1.3 pin #11 RTRGEN Analog Comparator 0 Rising Edge Trigger Enable\nNote: The bit is only effective while analog comparator 0 triggers PWM or Timer. 8 1 read-write 0 Analog comparator 0 rising edge trigger PWM or Timer enabled #0 1 Analog comparator 0 rising edge trigger disabled #1 SMPTSEL Analog Comparator 0 Speed Mode Selection 12 1 read-write 0 Slow mode #0 1 Fast mode #1 CTL1 ACMP_CTL1 Analog Comparator 1 Control Register 0x4 read-write n 0x0 0x0 ACMPEN Analog Comparator 1 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after this bit is set.. 0 1 read-write 0 Analog Comparator 1 Disabled #0 1 Analog Comparator 1 Enabled #1 ACMPIE Analog Comparator 1 Interrupt Enable Control 1 1 read-write 0 Interrupt function Disabled #0 1 Interrupt function Enabled #1 FTRGEN Analog Comparator 1 Falling Edge Trigger Enable\nNote: The bit is only effective while analog comparator 1 triggers PWM or Timer. 9 1 read-write 0 Analog comparator 1 falling edge trigger PWM or Timer enabled #0 1 Analog comparator 1 falling edge trigger disabled #1 HYSSEL Analog Comparator 1 Hysteresis Selction 2 2 read-write 0 CMP0 Hysteresis Disabled #00 1 CMP0 Hysteresis typical range is 15mV #01 2 CMP0 Hysteresis typical range is 90mV #10 3 Same as 00 #11 NEGSEL Analog Comparator 1 Negative Input Selection 4 1 read-write 0 The source of the negative comparator input is from CPN1 pin #0 1 The source of the negative comparator input is from internal band-gap voltage or comparator reference voltage #1 POSSEL Comparator 1 Positive Input Selection 29 2 read-write 0 CPP1 is from P3.1 pin #00 1 CPP1 is from P3.2 pin #01 2 CPP1 is from P3.4 pin #10 3 CPP1 is from P3.5 pin #11 RTRGEN Analog Comparator 1 Rising Edge Trigger Enable\nNote: The bit is only effective while analog comparator 1 triggers PWM or Timer. 8 1 read-write 0 Analog comparator 1 rising edge trigger PWM or Timer enabled #0 1 Analog comparator 1 rising edge trigger disabled #1 SMPTSEL Analog Comparator 1 Speed Mode Selection 12 1 read-write 0 Slow mode #0 1 Fast mode #1 STATUS ACMP_STATUS Analog Comparator 0/1 Status Register 0x8 read-write n 0x0 0x0 ACMPIF0 Analog Comparator 0 Flag\nNote: Software can write 1 to clear this bit to zero. 0 1 read-write 0 Analog comparator 0 output does not change #0 1 Analog comparator 0 output changed #1 ACMPIF1 Analog Comparator 1 Flag\nNote: Software can write 1 to clear this bit to zero. 1 1 read-write 0 Analog comparator 1 output does not change #0 1 Analog comparator 1 output changed #1 ACMPO0 Analog Comparator 0 Output 2 1 read-write 0 Analog comparator 0 outputs 0 #0 1 Analog comparator 0 outputs 1 #1 ACMPO1 Analog Comparator 1 Output 3 1 read-write 0 Analog comparator 1 outputs 0 #0 1 Analog comparator 1 outputs 1 #1 VREF ACMP_VREF Analog Comparator Reference Voltage Control Register 0xC read-write n 0x0 0x0 CRVCTL Internal Reference Selection 0 4 read-write IREFSEL CRV Module Output Selection 7 1 read-write 0 Band-gap voltage #0 1 Internal comparator reference voltage #1 ADC ADC Register Map ADC 0x0 0x0 0x4 registers n 0x20 0x14 registers n 0x44 0x14 registers n CHEN ADC_CHEN ADC Channel Enable Register 0x24 read-write n 0x0 0x0 BGEN Band-Gap Voltage Measurement\nNote: User can set BGEN high to use ADC to measure Band-Gap voltage directly to instead of enabling PRESET and CHEN7. 13 1 read-write 0 Disabled #0 1 Enabled #1 CH7SEL Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7, the ADC clock rate needs to be limited to lower than 300 kHz. 8 1 read-write 0 External analog input #0 1 Internal band-gap voltage (VBG) #1 CHEN0 Analog Input Channel 0 Enable\nNote: If software enables more than one channel, the channel with the smallest number will be selected and the other enabled channels will be ignored. 0 1 read-write 0 Channel 0 Disabled #0 1 Channel 0 Enabled #1 CHEN1 Analog Input Channel 1 Enable 1 1 read-write 0 Channel 1 Disabled #0 1 Channel 1 Enabled #1 CHEN10 Analog Input Channel 10 Enable 11 1 read-write 0 Disabled #0 1 Enabled #1 CHEN11 Analog Input Channel 11 Enable 12 1 read-write 0 Disabled #0 1 Enabled #1 CHEN2 Analog Input Channel 2 Enable 2 1 read-write 0 Channel 2 Disabled #0 1 Channel 2 Enabled #1 CHEN3 Analog Input Channel 3 Enable 3 1 read-write 0 Channel 3 Disabled #0 1 Channel 3 Enabled #1 CHEN4 Analog Input Channel 4 Enable 4 1 read-write 0 Channel 4 Disabled #0 1 Channel 4 Enabled #1 CHEN5 Analog Input Channel 5 Enable 5 1 read-write 0 Channel 5 Disabled #0 1 Channel 5 Enabled #1 CHEN6 Analog Input Channel 6 Enable 6 1 read-write 0 Channel 6 Disabled #0 1 Channel 6 Enabled #1 CHEN7 Analog Input Channel 7 Enable 7 1 read-write 0 Channel 7 Disabled #0 1 Channel 7 Enabled #1 CHEN8 Analog Input Channel 8 Enable 9 1 read-write 0 Disabled #0 1 Enabled #1 CHEN9 Analog Input Channel 9 Enable 10 1 read-write 0 Disabled #0 1 Enabled #1 CMP0 ADC_CMP0 ADC Compare Register 0 0x28 read-write n 0x0 0x0 ADCMPEN Compare Enable\nSet 1 to this bit to enable comparing CMPDAT[9:0] with specified channel conversion results when converted data is loaded into the ADC_DAT register. 0 1 read-write 0 Compare function Disabled #0 1 Compare function Enabled #1 ADCMPIE Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT, ADCMPFx bit will be asserted, in the meanwhile, if CMPCOND is set to 1, a compare interrupt request is generated. 1 1 read-write 0 Compare function interrupt Disabled #0 1 Compare function interrupt Enabled #1 CMPCH Compare Channel Selection 3 4 read-write 0 Channel 0 conversion result is selected to be compared #0000 1 Channel 1 conversion result is selected to be compared #0001 2 Channel 2 conversion result is selected to be compared #0010 3 Channel 3 conversion result is selected to be compared #0011 4 Channel 4 conversion result is selected to be compared #0100 5 Channel 5 conversion result is selected to be compared #0101 6 Channel 6 conversion result is selected to be compared #0110 7 Channel 7 conversion result is selected to be compared #0111 8 Channel 8 conversion result is selected to be compared #1000 9 Channel 9 conversion result is selected to be compared #1001 10 Channel 10 conversion result is selected to be compared #1010 11 Channel 11 conversion result is selected to be compared #1011 12 band-gap voltage result is selected to be compared #1100 CMPCOND Compare Condition\nNote: When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFx bit will be set. 2 1 read-write 0 Set the compare condition as that when a 10-bit A/D conversion result is less than the 10-bit CMPDAT (ADCMPRx[25:16]), the internal match counter will increase one #0 1 Set the compare condition as that when a 10-bit A/D conversion result is greater or equal to the 10-bit CMPDAT (ADCMPRx[25:16]), the internal match counter will increase one #1 CMPDAT Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel. 16 10 read-write CMPMCNT Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFx bit will be set. 8 4 read-write CMP1 ADC_CMP1 ADC Compare Register 1 0x2C read-write n 0x0 0x0 CTL ADC_CTL ADC Control Register 0x20 read-write n 0x0 0x0 ADCEN A/D Converter Enable\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption. 0 1 read-write 0 A/D Converter Disabled #0 1 A/D Converter Enabled #1 ADCIEN A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADCIEN bit is set to 1. 1 1 read-write 0 A/D interrupt function Disabled #0 1 A/D interrupt function Enabled #1 HWTRGCOND External Trigger Condition\nThis bit decides whether the external pin STADC trigger event is falling or raising edge. The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigger. 6 1 read-write 0 Falling edge #0 1 Raising edge #1 HWTRGEN External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled, the SWTRG bit can be set to 1 by the selected hardware trigger source. 8 1 read-write 0 External trigger Disabled #0 1 External trigger Enabled #1 HWTRGSEL Hardware Trigger Source\nNote: Software should disable HWTRGEN and SWTRG before change HWTRGSEL. 4 2 read-write 0 A/D conversion is started by external STADC pin #00 3 A/D conversion is started by PWM trigger #11 SWTRG A/D Conversion Start\nSWTRG bit can be set to 1 from two sources: software and external pin STADC. SWTRG will be cleared to 0 by hardware automatically after conversion complete. 11 1 read-write 0 Conversion stopped and A/D converter entered idle state #0 1 Conversion start #1 VREFSEL Reference Voltage Selection Signal 12 1 read-write 0 Connect VDD5V to internal reference #0 1 Connect VREF (AIN0) pin to internal reference #1 DAT ADC_DAT ADC Data Register 0x0 read-only n 0x0 0x0 OV Over Run Flag\nIf converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after the ADC_DAT register is read. 16 1 read-only 0 Data in RESULT[9:0] is recent conversion result #0 1 Data in RESULT[9:0] overwrote #1 RESULT A/D Conversion Result\nThis field contains conversion result of ADC. 0 10 read-only VALID Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read. 17 1 read-only 0 Data in RESULT[9:0] bits not valid #0 1 Data in RESULT[9:0] bits valid #1 EXTSMPT ADC_EXTSMPT ADC Sampling Time Counter Register 0x48 read-write n 0x0 0x0 EXTSMPT ADC Sampling Counter\nADC sampling counters are 6 ADC clock is suggestion. 0 4 read-write 0 6 ADC Clock #0000 1 7 ADC Clock #0001 2 8 ADC Clock #0010 3 10 ADC Clock #0011 4 14 ADC Clock #0100 5 22 ADC Clock #0101 6 38 ADC Clock #0110 7 70 ADC Clock #0111 8 1346 ADC Clock #1000 9 262 ADC Clock #1001 10 518 ADC Clock #1010 11 1030 ADC Clock #1011 12 1030 ADC Clock #1100 13 1030 ADC Clock #1101 14 1030 ADC Clock #1110 15 1030 ADC Clock #1111 SEQCTL ADC_SEQCTL ADC PWM Sequential Mode Control Register 0x4C read-write n 0x0 0x0 MODESEL ADC Sequential Mode Selection 2 2 read-write 0 Issue ADC_INT after Channel 0 then Channel 1 conversion finishes when SEQEN =1 #00 1 Issue ADC_INT after Channel 1 then Channel 2 conversion finishes when SEQEN =1 #01 2 Issue ADC_INT after Channel 0 then Channel 2 conversion finishes when SEQEN =1 #10 3 Reserved #11 SEQEN ADC Sequential Mode Enable\nWhen ADC sequential mode is enabled, two of three ADC channels from 0 to 2 will automatically convert analog data in the sequence of channel [0, 1] or channel[1, 2] or channel[0, 2] defined by SEQ_MODE[1:0]. 0 1 read-write 0 ADC sequential mode Disabled #0 1 ADC sequential mode Enabled #1 SEQTYPE ADC Sequential Mode Type 1 1 read-write 0 ADC delay time is only inserted before the first conversion. The second conversion starts immediately after the first conversion is completed. (for 2/3-shunt type) #0 1 ADC delay time is inserted before each conversion. (for 1-shunt type) #1 TRG1SRC ADC Sequential Mode Trigger1 Source 10 2 read-write 0 PWM0 #00 1 PWM2 #01 2 PWM4 #10 3 Reserved #11 TRG1TYPE ADC Sequential Mode Trigger1 Type 8 2 read-write 0 Rising of the selected PWM #00 1 Center of the selected PWM #01 2 Falling of the selected PWM #10 3 Period of the selected PWM #11 TRG2SRC ADC Sequential Mode Trigger2 Source 18 2 read-write 0 PWM0 #00 1 PWM2 #01 2 PWM4 #10 3 Reserved #11 TRG2TYPE ADC Sequential Mode Trigger2 Type 16 2 read-write 0 Rising of the selected PWM #00 1 Center of the selected PWM #01 2 Falling of the selected PWM #10 3 Period of the selected PWM #11 SEQDAT0 ADC_SEQDAT0 ADC PWM Sequential Mode Result Register 0 0x50 read-only n 0x0 0x0 OV Over Run Flag\nIf converted data in RESULT [9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after the ADC_DAT register is read. 16 1 read-only 0 Data in RESULT [9:0] is recent conversion result #0 1 Data in RESULT [9:0] overwritten #1 RESULT A/D PWM Sequential Mode Conversion Result\nThis field contains conversion result of ADC. 0 10 read-only VALID Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read. 17 1 read-only 0 Data in RESULT [9:0] bits not valid #0 1 Data in RESULT. ADC_TRGDLY [9:0] bits valid #1 SEQDAT1 ADC_SEQDAT1 ADC PWM Sequential Mode Result Register 1 0x54 read-write n 0x0 0x0 STATUS ADC_STATUS ADC Status Register 0x30 read-write n 0x0 0x0 ADCMPF0 Compare Flag 0\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP0, this bit is set to 1. Software can write 1 to clear this bit to zero. 1 1 read-write 0 Conversion result in ADC_DAT does not meet the ADC_CMP0 setting #0 1 Conversion result in ADC_DAT meets the ADC_CMP0 setting #1 ADCMPF1 Compare Flag 1\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP1, this bit is set to 1. Software can write 1 to clear this bit to zero. 2 1 read-write 0 Conversion result in ADC_DAT does not meet the ADC_CMP1 setting #0 1 Conversion result in ADC_DAT meets the ADC_CMP1 setting #1 ADIF A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. ADIF is set to 1 When A/D conversion ends.\nSoftware can write 1 to clear this bit to zero. 0 1 read-write BUSY BUSY/IDLE (Read Only)\nThis bit is mirror of as SWTRG bit in ADC_CTL 3 1 read-only 0 A/D converter is in idle state #0 1 A/D converter is busy at conversion #1 CHANNEL Current Conversion Channel (Read Only) 4 3 read-only OV OV Flag (Read Only)\nIt is a mirror to OV bit in ADC_DAT register. 16 1 read-only VALID Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in ADC_DAT register. 8 1 read-only TRGDLY ADC_TRGDLY ADC Trigger Delay Control Register 0x44 read-write n 0x0 0x0 DELAY PWM Trigger Delay Timer\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * DELAY) * system clock. 0 8 read-write CLK CLK Register Map CLK 0x0 0x0 0x20 registers n 0x24 0x4 registers n AHBCLK CLK_AHBCLK AHB Devices Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 HDIVEN Divider Clock Enable Control 4 1 read-write 0 Divider clock Disabled #0 1 Divider clock Enabled #1 ISPCKEN Flash ISP Controller Clock Enable Control 2 1 read-write 0 Flash ISP peripheral clock Disabled #0 1 Flash ISP peripheral clock Enabled #1 APBCLK CLK_APBCLK APB Devices Clock Enable Control Register 0x8 -1 read-write n 0x0 0x0 ACMPCKEN Analog Comparator Clock Enable Control 30 1 read-write 0 Analog Comparator clock Disabled #0 1 Analog Comparator clock Enabled #1 ADCCKEN Analog-Digital-Converter (ADC) Clock Enable Control 28 1 read-write 0 ADC peripheral clock Disabled #0 1 ADC peripheral clock Enabled #1 CLKOCKEN Frequency Divider Output Clock Enable Control 6 1 read-write 0 FDIV clock Disabled #0 1 FDIV clock Enabled #1 I2CCKEN I2C Clock Enable Control 8 1 read-write 0 I2C clock Disabled #0 1 I2C clock Enabled #1 PWMCH01CKEN PWM_01 Clock Enable Control 20 1 read-write 0 PWM01 clock Disabled #0 1 PWM01 clock Enabled #1 PWMCH23CKEN PWM_23 Clock Enable Control 21 1 read-write 0 PWM23 clock Disabled #0 1 PWM23 clock Enabled #1 PWMCH45CKEN PWM_45 Clock Enable Control 22 1 read-write 0 PWM45 clock Disabled #0 1 PWM45 clock Enabled #1 SPICKEN SPI Peripheral Clock Enable Control 12 1 read-write 0 SPI peripheral clock Disabled #0 1 SPI peripheral clock Enabled #1 TMR0CKEN Timer0 Clock Enable Control 2 1 read-write 0 Timer0 clock Disabled #0 1 Timer0 clock Enabled #1 TMR1CKEN Timer1 Clock Enable Control 3 1 read-write 0 Timer1 clock Disabled #0 1 Timer1 clock Enabled #1 UART0CKEN UART0 Clock Enable Control 16 1 read-write 0 UART0 clock Disabled #0 1 UART0 clock Enabled #1 UART1CKEN UART1 Clock Enable Control 17 1 read-write 0 UART1 clock Disabled #0 1 UART1 clock Enabled #1 WDTCKEN Watchdog Timer Clock Enable Control (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address SYS_BA + 0x100. 0 1 read-write 0 Watchdog Timer clock Disabled #0 1 Watchdog Timer clock Enabled #1 CLKDIV CLK_CLKDIV Clock Divider Number Register 0x18 read-write n 0x0 0x0 ADCDIV ADC Peripheral Clock Divide Number From ADC Peripheral Clock Source 16 8 read-write HCLKDIV HCLK Clock Divide Number From HCLK Clock Source 0 4 read-write UART0DIV UART0 Clock Divide Number From UART0 Clock Source 8 4 read-write UART1DIV UART1 Clock Divide Number From UART1 Clock Source 12 4 read-write CLKOCTL CLK_CLKOCTL Frequency Divider Control Register 0x24 read-write n 0x0 0x0 CLKOEN Frequency Divider Enable Control 4 1 read-write 0 Frequency Divider Disabled #0 1 Frequency Divider Enabled #1 DIV1EN Frequency Divider 1 Enable Control 5 1 read-write 0 Divider output frequency is depended on FSEL value #0 1 Divider output frequency is the same as input clock frequency #1 FSEL Divider Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0]. 0 4 read-write CLKSEL0 CLK_CLKSEL0 Clock Source Select Control Register 0 0x10 -1 read-write n 0x0 0x0 HCLKSEL HCLK Clock Source Selection (Write Protect)\nNote1: Before clock switching, the related clock sources (both pre-select and new-select) must be turn-on and stable.\nNote2: These bits are protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address SYS_BA + 0x100.\nNote3: To set CLK_PWRCTL[1:0] to select HXT or LXT crystal clock. 0 3 read-write 0 Clock source is from HXT or LXT #000 1 Reserved #001 2 Reserved #010 3 Clock source is from LIRC #011 7 Clock source is from HIRC #111 STCLKSEL Cortex-M0 SysTick Clock Source Selection From Reference Clock (Write Protect)\nNote3: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. 3 3 read-write 0 Clock source is from HXT or LXT #000 1 Reserved #001 2 Clock source is from HXT/2 or LXT/2 #010 3 Clock source is from HCLK/2 #011 7 Clock source is from HIRC /2 #111 CLKSEL1 CLK_CLKSEL1 Clock Source Select Control Register 1 0x14 -1 read-write n 0x0 0x0 ADCSEL ADC Peripheral Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. 2 2 read-write 0 Clock source is from HXT or LXT #00 1 Reserved #01 2 Clock source is from HCLK #10 3 Clock source is from HIRC #11 SPISEL SPI Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. 4 1 read-write 0 Clock source is from HXT or LXT #0 1 Clock source is from HCLK #1 TMR0SEL TIMER0 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. 8 3 read-write 0 Clock source is from HXT or LXT #000 1 Clock source is from LIRC #001 2 Clock source is from HCLK #010 3 Clock source is from external trigger #011 7 Clock source is from HIRC #111 TMR1SEL TIMER1 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. 12 3 read-write 0 Clock source is from HXT or LXT #000 1 Clock source is from LIRC #001 2 Clock source is from HCLK #010 3 Clock source is from external trigger #011 7 Clock source is from HIRC #111 UART0SEL UART0 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. 24 2 read-write 0 Clock source is from HXT or LXT #00 1 Reserved #01 2 Clock source is from HIRC #10 3 Clock source is from HIRC #11 UART1SEL UART1 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. 26 2 read-write 0 Clock source from HXT or LXT crystal clock #00 1 Reserved #01 2 Clock source from HIRC oscillator clock #10 3 Reserved #11 WDTSEL WDT CLK Clock Source Selection (Write Protect)\nNote1: These bits are the protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address SYS_BA + 0x100.\nNote2: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. 0 2 read-write 0 Clock source is from HXT or LXT #00 1 Reserved #01 2 Clock source is from HCLK/2048 clock #10 3 Clock source is from LIRC #11 CLKSEL2 CLK_CLKSEL2 Clock Source Select Control Register 2 0x1C -1 read-write n 0x0 0x0 FDIVSEL Clock Divider Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. 2 2 read-write 0 Clock source is from HXT or LXT #00 1 Reserved #01 2 Clock source is from HCLK #10 3 Clock source is from HIRC #11 PWRCTL CLK_PWRCTL System Power-down Control Register 0x0 -1 read-write n 0x0 0x0 HIRCEN 44.2368 MHz Internal High Speed RC Oscillator (HIRC) Enable Control (Write Protect)\nNote: The default of HIRCEN bit is 1. 2 1 read-write 0 44.2368 MHz internal high speed RC oscillator (HIRC) Disabled #0 1 44.2368 MHz internal high speed RC oscillator (HIRC) Enabled #1 HXTGAIN HXT Gain Selection 10 2 read-write 0 Full gain for the frequency up to 24MHz #00 1 3/4 gain for the frequency up to 16MHz #01 2 1/2 gain for the frequency up to 12MHz #10 3 1/4 gain for the frequency up to 4MHz #11 LIRCEN 10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Control (Write Protest) 3 1 read-write 0 10 kHz internal low speed RC oscillator (LIRC) Disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) Enabled #1 PDEN System Power-Down Enable Bit (Write Protect)\nWhen chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next Power-down.\nIn Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT), 32.768 kHz external low speed crystal oscillator (LXT), and the 22.1184 MHz internal high speed oscillator (HIRC) will be disabled in this mode, and 10 kHz internal low speed RC oscillator (LIRC) are not controlled by Power-down mode.\nIn Power-down mode, the system clock is disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from 10 kHz internal low speed oscillator. 7 1 read-write 0 Chip operating normally or chip in Idle mode because of WFI command #0 1 Chip enters Power-down mode instantly or waits CPU sleep command WFI #1 PDLXT Enable LXT In Power-Down Mode\nThis bit controls the crystal oscillator active or not in Power-down mode. 9 1 read-write 0 No effect to Power-down mode #0 1 If XTLEN[1:0] = 10, LXT is still active in Power-down mode #1 PDWKDLY Wake-Up Delay Counter Enable Control (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz external high speed crystal (HXT), 4096 clock cycles for 32.768 kHz external low speed crystal (LXT), and 16 clock cycles when chip works at 22.1184 MHz internal high speed RC oscillator (HIRC). 4 1 read-write 0 Clock cycles delay Disabled #0 1 Clock cycles delay Enabled #1 PDWKIEN Power-Down Mode Wake-Up Interrupt Enable Control (Write Protect)\nNote: The interrupt will occur when both PDWKIF and PDWKIEN are high. 5 1 read-write 0 Disabled #0 1 Enabled #1 PDWKIF Power-Down Mode Wake-Up Interrupt Status Set by Power-down wake-up event , which indicates that resume from Power-down mode The flag is set if the GPIO, UART, WDT, ACMP, Timer or BOD wake-up occurred. Note: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. Write 1 to clear the bit to 0. 6 1 read-write XTLEN External HXT Or LXT Crystal Oscillator Enable Control (Write Protect) The default clock source is from HIRC. These two bits are default set to 00 and the XTAL1 and XTAL2 pins are GPIO. Note: To enable external XTAL function, P5_ALT[1:0] and P5_MFP[1:0] bits must also be set in P5_MFP. 0 2 read-write 0 XTAL1 and XTAL2 are GPIO, disable both LXT HXT (default) #00 1 HXT Enabled #01 2 LXT Enabled #10 3 XTAL1 is external clock input pin, XTAL2 is GPIO #11 STATUS CLK_STATUS Clock Status Monitor Register 0xC -1 read-write n 0x0 0x0 CLKSFAIL Clock Switch Fail Flag\nNote1: This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote2: This bit is read only. After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware. 7 1 read-write 0 Clock switching success #0 1 Clock switching failed #1 HIRCSTB HIRC Clock Source Stable Flag (Read Only) 4 1 read-only 0 HIRC clock is not stable or disabled #0 1 HIRC clock is stable #1 LIRCSTB LIRC Clock Source Stable Flag (Read Only) 3 1 read-only 0 LIRC clock is not stable or disabled #0 1 LIRC clock is stable #1 XTLSTB HXT Or LXT Clock Source Stable Flag 0 1 read-write 0 HXT or LXT clock is not stable or disabled #0 1 HXT or LXT clock is stable #1 FMC FMC Register Map FMC 0x0 0x0 0x18 registers n 0x40 0x4 registers n DFBA FMC_DFBA Data Flash Start Address 0x14 -1 read-only n 0x0 0x0 DFBA Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nThe data flash start address is defined by user. Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0. 0 32 read-only ISPADDR FMC_ISPADDR ISP Address Register 0x4 read-write n 0x0 0x0 ISPADR ISP Address\nThe NuMicroTM MINI51X series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation. 0 32 read-write ISPCMD FMC_ISPCMD ISP Command Register 0xC read-write n 0x0 0x0 CMD ISP Command \nISP commands are shown below: 0 6 read-write 0 Read 0x00 4 Read Unique ID 0x04 11 Read Company ID (0xDA) 0x0b 33 Program 0x21 34 Page Erase 0x22 46 Set Vector Page Re-Map 0x2e ISPCTL FMC_ISPCTL ISP Control Register 0x0 read-write n 0x0 0x0 APUEN APROM Update Enable Control (Write Protect) 3 1 read-write 0 APROM cannot be updated when chip runs in APROM #0 1 APROM can be updated when chip runs in APROM #1 BS Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (CPURF is 1) or system reset (SYSRF) is happened. 1 1 read-write 0 Boot from APROM #0 1 Boot from LDROM #1 CFGUEN CONFIG Update Enable Control (Write Protect)\nWriting this bit to 1 enables software to update CONFIG value by ISP register control procedure regardless of program code is running in APROM or LDROM. 4 1 read-write 0 ISP update User Configuration Disabled #0 1 ISP update User Configuration Enabled #1 ISPEN ISP Enable Control (Write Protect)\nSet this bit to enable ISP function. 0 1 read-write 0 ISP function Disabled #0 1 ISP function Enabled #1 ISPFF ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself. \n(3) Destination address is illegal, such as over an available range.\nNote: Write 1 to clear this bit to 0. 6 1 read-write LDUEN LDROM Update Enable Control (Write Protect) 5 1 read-write 0 LDROM cannot be updated #0 1 LDROM can be updated when the MCU runs in APROM #1 ISPDAT FMC_ISPDAT ISP Data Register 0x8 read-write n 0x0 0x0 ISPDAT ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation. 0 32 read-write ISPSTS FMC_ISPSTS ISP Status Register 0x40 read-write n 0x0 0x0 CBS Config Boot Selection (Read Only)\nThis is a mirror of CBS in CONFIG0. 1 2 read-only ISPBUSY ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same with FMC_ISPTRG bit 0. 0 1 read-only 0 ISP operation is finished #0 1 ISP operation is progressed #1 ISPFF ISP Fail Flag (Write-Protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Destination address is illegal, such as over an available range.\nWrite 1 to clear.\nNote: This bit functions the same as FMC_ISPCTL bit 6. 6 1 read-write VECMAP Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}. 9 12 read-only ISPTRG FMC_ISPTRG ISP Trigger Register 0x10 read-write n 0x0 0x0 ISPGO ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 0 1 read-write 0 ISP operation is finished #0 1 ISP operation is progressed #1 GP GPIO Register Map GPIO 0x0 0x0 0x24 registers n 0x100 0x24 registers n 0x140 0x24 registers n 0x180 0x4 registers n 0x200 0x8 registers n 0x210 0x14 registers n 0x228 0x14 registers n 0x248 0x24 registers n 0x270 0x10 registers n 0x298 0x20 registers n 0x40 0x24 registers n 0x80 0x24 registers n 0xC0 0x24 registers n DBNCECON DBNCECON Interrupt De-bounce Control 0x180 -1 read-write n 0x0 0x0 DBCLKSEL De-Bounce Sampling Cycle Selection 0 4 read-write 0 Sample interrupt input once per 1 clock #0000 1 Sample interrupt input once per 2 clocks #0001 2 Sample interrupt input once per 4 clocks #0010 3 Sample interrupt input once per 8 clocks #0011 4 Sample interrupt input once per 16 clocks #0100 5 Sample interrupt input once per 32 clocks #0101 6 Sample interrupt input once per 64 clocks #0110 7 Sample interrupt input once per 128 clocks #0111 8 Sample interrupt input once per 256 clocks #1000 9 Sample interrupt input once per 512 clocks #1001 10 Sample interrupt input once per 1024 clocks #1010 11 Sample interrupt input once per 2048 clocks #1011 12 Sample interrupt input once per 4096 clocks #1100 13 Sample interrupt input once per 8192 clocks #1101 14 Sample interrupt input once per 16384 clocks #1110 15 Sample interrupt input once per 32768 clocks #1111 DBCLKSRC De-Bounce Counter Clock Source Selection 4 1 read-write 0 De-bounce counter clock source is the HCLK #0 1 De-bounce counter clock source is the 10 kHz internal low speed oscillator #1 ICLKON Interrupt Clock On Mode\nNote: It is recommended to turn off this bit to save system power if no special application concern. 5 1 read-write 0 Edge detection circuit is active only if I/O pin corresponding Px_INTEN bit is set to 1 #0 1 All I/O pins edge detection circuit is always active after reset #1 P00_PDIO P00_PDIO GPIO P0.0 Pin Data Input/Output 0x200 -1 read-write n 0x0 0x0 PDIO GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nFor example, writing P01_PDIO will reflect the written value to bit P0_DOUT[1], reading P01_PDIO will return the value of P0_PIN[1].\nNote: The writing operation will not be affected by register Px_DATMSK[n]. 0 1 read-write 0 Corresponding GPIO pin set to low.\nCorresponding GPIO pin status is low #0 1 Corresponding GPIO pin set to high.\nCorresponding GPIO pin status is high #1 P01_PDIO P01_PDIO GPIO P0.1 Pin Data Input/Output 0x204 read-write n 0x0 0x0 P04_PDIO P04_PDIO GPIO P0.4 Pin Data Input/Output 0x210 read-write n 0x0 0x0 P05_PDIO P05_PDIO GPIO P0.5 Pin Data Input/Output 0x214 read-write n 0x0 0x0 P06_PDIO P06_PDIO GPIO P0.6 Pin Data Input/Output 0x218 read-write n 0x0 0x0 P07_PDIO P07_PDIO GPIO P0.7 Pin Data Input/Output 0x21C read-write n 0x0 0x0 P0_DATMSK P0_DATMSK P0 Data Output Write Mask 0xC read-write n 0x0 0x0 DATMSK Port 0-5 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DATMSK[n] bit is set to 1, the corresponding Px_DOUT[n] bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote2: This function only protects the corresponding Px_DOUT[n] bit, and will not protect the corresponding Pxn_PDIO bit. 0 8 read-write 0 Corresponding Px_DOUT[n] bit can be updated 0 1 Corresponding Px_DOUT[n] bit is protected 1 P0_DBEN P0_DBEN P0 De-bounce Enable Control 0x14 read-write n 0x0 0x0 DBEN Port 0-5 Pin [N] Input Signal De-Bounce Enable Control\nDBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\nNote2: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function. 0 8 read-write 0 Px.n de-bounce function Disabled 0 1 Px.n de-bounce function Enabled 1 P0_DINOFF P0_DINOFF P0 Digital Input Path Disable Control 0x4 read-write n 0x0 0x0 DINOFF Port 0-5 Pin [N] Digital Input Path Disable Control 16 8 read-write 0 Px.n digital input path Enabled 0 1 Px.n digital input path Disabled (digital input tied to low) 1 P0_DOUT P0_DOUT P0 Data Output Value 0x8 -1 read-write n 0x0 0x0 DOUT Port 0-5 Pin [N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output and Quasi-bidirectional mode. 0 8 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode 0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode 1 P0_INTEN P0_INTEN P0 Interrupt Enable Control 0x1C read-write n 0x0 0x0 FLIEN Port 0-5 Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFLIEN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN[n] bit to 1:\nIf the interrupt is level trigger (INTTYPE[n] is 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge mode trigger (INTTYPE[n] is 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 0 1 read-write 0 Px.n low level or high to low interrupt Disabled #0 1 Px.n low level or high to low interrupt Enabled #1 RHIEN Port 0-5 Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRHIEN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN[n] bit to 1:\nIf the interrupt is level trigger (INTTYPE[n] is 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (INTTYPE[n] is 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 16 8 read-write 0 Px.n level high or low to high interrupt Disabled 0 1 Px.n level high or low to high interrupt Enabled 1 P0_INTSRC P0_INTSRC P0 Interrupt Source Flag 0x20 read-write n 0x0 0x0 INTSRC Port 0-5 Pin [N] Interrupt Source Flag\nWrite : 0 8 read-write 0 No action.\nNo interrupt at Px.n 0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt 1 P0_INTTYPE P0_INTTYPE P0 Interrupt Mode Control 0x18 read-write n 0x0 0x0 INTTYPE Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control\nINTTYPE[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 0 8 read-write 0 Edge trigger interrupt 0 1 Level trigger interrupt 1 P0_MODE P0_MODE P0 I/O Mode Control 0x0 read-write n 0x0 0x0 MODE0 Port 0-5 I/O Pin [N] Mode Control 0 2 read-write MODE1 Port 0-5 I/O Pin [N] Mode Control 2 2 read-write MODE2 Port 0-5 I/O Pin [N] Mode Control 4 2 read-write MODE3 Port 0-5 I/O Pin [N] Mode Control 6 2 read-write MODE4 Port 0-5 I/O Pin [N] Mode Control 8 2 read-write MODE5 Port 0-5 I/O Pin [N] Mode Control 10 2 read-write MODE6 Port 0-5 I/O Pin [N] Mode Control 12 2 read-write MODE7 Port 0-5 I/O Pin [N] Mode Control 14 2 read-write P0_PIN P0_PIN P0 Pin Value 0x10 read-only n 0x0 0x0 PIN Port 0-5 Pin [N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. 0 8 read-only P10_PDIO P10_PDIO GPIO P1.0 Pin Data Input/Output 0x220 read-write n 0x0 0x0 P12_PDIO P12_PDIO GPIO P1.2 Pin Data Input/Output 0x228 read-write n 0x0 0x0 P13_PDIO P13_PDIO GPIO P1.3 Pin Data Input/Output 0x22C read-write n 0x0 0x0 P14_PDIO P14_PDIO GPIO P1.4 Pin Data Input/Output 0x230 read-write n 0x0 0x0 P15_PDIO P15_PDIO GPIO P1.5 Pin Data Input/Output 0x234 read-write n 0x0 0x0 P16_PDIO P16_PDIO GPIO P1.6 Pin Data Input/Output 0x238 read-write n 0x0 0x0 P1_DATMSK P1_DATMSK P1 Data Output Write Mask 0x4C read-write n 0x0 0x0 P1_DBEN P1_DBEN P1 De-bounce Enable Control 0x54 read-write n 0x0 0x0 P1_DINOFF P1_DINOFF P1 Digital Input Path Disable Control 0x44 read-write n 0x0 0x0 P1_DOUT P1_DOUT P1 Data Output Value 0x48 read-write n 0x0 0x0 P1_INTEN P1_INTEN P1 Interrupt Enable Control 0x5C read-write n 0x0 0x0 P1_INTSRC P1_INTSRC P1 Interrupt Source Flag 0x60 read-write n 0x0 0x0 P1_INTTYPE P1_INTTYPE P1 Interrupt Mode Control 0x58 read-write n 0x0 0x0 P1_MODE P1_MODE P1 I/O Mode Control 0x40 read-write n 0x0 0x0 P1_PIN P1_PIN P1 Pin Value 0x50 read-write n 0x0 0x0 P22_PDIO P22_PDIO GPIO P2.2 Pin Data Input/Output 0x248 read-write n 0x0 0x0 P23_PDIO P23_PDIO GPIO P2.3 Pin Data Input/Output 0x24C read-write n 0x0 0x0 P24_PDIO P24_PDIO GPIO P2.4 Pin Data Input/Output 0x250 read-write n 0x0 0x0 P25_PDIO P25_PDIO GPIO P2.5 Pin Data Input/Output 0x254 read-write n 0x0 0x0 P26_PDIO P26_PDIO GPIO P2.6 Pin Data Input/Output 0x258 read-write n 0x0 0x0 P27_PDIO P27_PDIO GPIO P2.7 Pin Data Input/Output 0x25C read-write n 0x0 0x0 P2_DATMSK P2_DATMSK P2 Data Output Write Mask 0x8C read-write n 0x0 0x0 P2_DBEN P2_DBEN P2 De-bounce Enable Control 0x94 read-write n 0x0 0x0 P2_DINOFF P2_DINOFF P2 Digital Input Path Disable Control 0x84 read-write n 0x0 0x0 P2_DOUT P2_DOUT P2 Data Output Value 0x88 read-write n 0x0 0x0 P2_INTEN P2_INTEN P2 Interrupt Enable Control 0x9C read-write n 0x0 0x0 P2_INTSRC P2_INTSRC P2 Interrupt Source Flag 0xA0 read-write n 0x0 0x0 P2_INTTYPE P2_INTTYPE P2 Interrupt Mode Control 0x98 read-write n 0x0 0x0 P2_MODE P2_MODE P2 I/O Mode Control 0x80 read-write n 0x0 0x0 P2_PIN P2_PIN P2 Pin Value 0x90 read-write n 0x0 0x0 P30_PDIO P30_PDIO GPIO P3.0 Pin Data Input/Output 0x260 read-write n 0x0 0x0 P31_PDIO P31_PDIO GPIO P3.1 Pin Data Input/Output 0x264 read-write n 0x0 0x0 P32_PDIO P32_PDIO GPIO P3.2 Pin Data Input/Output 0x268 read-write n 0x0 0x0 P34_PDIO P34_PDIO GPIO P3.4 Pin Data Input/Output 0x270 read-write n 0x0 0x0 P35_PDIO P35_PDIO GPIO P3.5 Pin Data Input/Output 0x274 read-write n 0x0 0x0 P36_PDIO P36_PDIO GPIO P3.6 Pin Data Input/Output 0x278 read-write n 0x0 0x0 P37_PDIO P37_PDIO GPIO P3.7 Pin Data Input/Output 0x27C read-write n 0x0 0x0 P3_DATMSK P3_DATMSK P3 Data Output Write Mask 0xCC read-write n 0x0 0x0 P3_DBEN P3_DBEN P3 De-bounce Enable Control 0xD4 read-write n 0x0 0x0 P3_DINOFF P3_DINOFF P3 Digital Input Path Disable Control 0xC4 read-write n 0x0 0x0 P3_DOUT P3_DOUT P3 Data Output Value 0xC8 read-write n 0x0 0x0 P3_INTEN P3_INTEN P3 Interrupt Enable Control 0xDC read-write n 0x0 0x0 P3_INTSRC P3_INTSRC P3 Interrupt Source Flag 0xE0 read-write n 0x0 0x0 P3_INTTYPE P3_INTTYPE P3 Interrupt Mode Control 0xD8 read-write n 0x0 0x0 P3_MODE P3_MODE P3 I/O Mode Control 0xC0 read-write n 0x0 0x0 P3_PIN P3_PIN P3 Pin Value 0xD0 read-write n 0x0 0x0 P46_PDIO P46_PDIO GPIO P4.6 Pin Data Input/Output 0x298 read-write n 0x0 0x0 P47_PDIO P47_PDIO GPIO P4.7 Pin Data Input/Output 0x29C read-write n 0x0 0x0 P4_DATMSK P4_DATMSK P4 Data Output Write Mask 0x10C read-write n 0x0 0x0 P4_DBEN P4_DBEN P4 De-bounce Enable Control 0x114 read-write n 0x0 0x0 P4_DINOFF P4_DINOFF P4 Digital Input Path Disable Control 0x104 read-write n 0x0 0x0 P4_DOUT P4_DOUT P4 Data Output Value 0x108 read-write n 0x0 0x0 P4_INTEN P4_INTEN P4 Interrupt Enable Control 0x11C read-write n 0x0 0x0 P4_INTSRC P4_INTSRC P4 Interrupt Source Flag 0x120 read-write n 0x0 0x0 P4_INTTYPE P4_INTTYPE P4 Interrupt Mode Control 0x118 read-write n 0x0 0x0 P4_MODE P4_MODE P4 I/O Mode Control 0x100 read-write n 0x0 0x0 P4_PIN P4_PIN P4 Pin Value 0x110 read-write n 0x0 0x0 P50_PDIO P50_PDIO GPIO P5.0 Pin Data Input/Output 0x2A0 read-write n 0x0 0x0 P51_PDIO P51_PDIO GPIO P5.1 Pin Data Input/Output 0x2A4 read-write n 0x0 0x0 P52_PDIO P52_PDIO GPIO P5.2 Pin Data Input/Output 0x2A8 read-write n 0x0 0x0 P53_PDIO P53_PDIO GPIO P5.3 Pin Data Input/Output 0x2AC read-write n 0x0 0x0 P54_PDIO P54_PDIO GPIO P5.4 Pin Data Input/Output 0x2B0 read-write n 0x0 0x0 P55_PDIO P55_PDIO GPIO P5.5 Pin Data Input/Output 0x2B4 read-write n 0x0 0x0 P5_DATMSK P5_DATMSK P5 Data Output Write Mask 0x14C read-write n 0x0 0x0 P5_DBEN P5_DBEN P5 De-bounce Enable Control 0x154 read-write n 0x0 0x0 P5_DINOFF P5_DINOFF P5 Digital Input Path Disable Control 0x144 read-write n 0x0 0x0 P5_DOUT P5_DOUT P5 Data Output Value 0x148 read-write n 0x0 0x0 P5_INTEN P5_INTEN P5 Interrupt Enable Control 0x15C read-write n 0x0 0x0 P5_INTSRC P5_INTSRC P5 Interrupt Source Flag 0x160 read-write n 0x0 0x0 P5_INTTYPE P5_INTTYPE P5 Interrupt Mode Control 0x158 read-write n 0x0 0x0 P5_MODE P5_MODE P5 I/O Mode Control 0x140 read-write n 0x0 0x0 P5_PIN P5_PIN P5 Pin Value 0x150 read-write n 0x0 0x0 HDIV HDIV Register Map HDIV 0x0 0x0 0x14 registers n DIVIDEND HDIV_DIVIDEND Dividend Source Register 0x0 read-write n 0x0 0x0 DIVIDEND Dividend Source\nThis register is given the dividend of divider before calculation starting. 0 32 read-write DIVISOR HDIV_DIVISOR Divisor Source Resister 0x4 -1 read-write n 0x0 0x0 DIVISOR Divisor Source\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written, hardware divider will start calculate. 0 16 read-write QUOTIENT HDIV_QUOTIENT Quotient Result Resister 0x8 read-write n 0x0 0x0 QUOTIENT Quotient Result\nThis register holds the quotient result of divider after calculation complete. 0 32 read-write REM HDIV_REM Remainder Result Register 0xC read-write n 0x0 0x0 REM Remainder Result\nThe remainder of hardware divider is 16-bit sign integer (REM[15:0]) with sign extension (REM[31:16]) to 32-bit integer. 0 32 read-write STATUS HDIV_STATUS Divider Status Register 0x10 -1 read-only n 0x0 0x0 DIVBYZERO Divisor Zero Warning\nNote: The DIVBYZERO flag is used to indicate divide-by-zero situation and updated whenever HDIV_DIVISOR is written. This register is read only. 1 1 read-only 0 The divisor is not 0 #0 1 The divisor is 0 #1 I2C I2C Register Map I2C 0x0 0x0 0x30 registers n 0x3C 0x8 registers n ADDR0 I2C_ADDR0 I2C Slave Address Register 0 0x4 read-write n 0x0 0x0 ADDR I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched. 1 7 read-write GC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 ADDR1 I2C_ADDR1 I2C Slave Address Register 1 0x18 read-write n 0x0 0x0 ADDR2 I2C_ADDR2 I2C Slave Address Register 2 0x1C read-write n 0x0 0x0 ADDR3 I2C_ADDR3 I2C Slave Address Register 3 0x20 read-write n 0x0 0x0 ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register 0 0x24 read-write n 0x0 0x0 ADDRMSK I2C Address Mask Register 1 7 read-write 0 I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register) 0 1 I2C address mask Enabled (the received corresponding address bit is Don't care ) 1 ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register 1 0x28 read-write n 0x0 0x0 ADDRMSK2 I2C_ADDRMSK2 I2C Slave Address Mask Register 2 0x2C read-write n 0x0 0x0 ADDRMSK3 I2C_ADDRMSK3 I2C Slave Address Mask Register 3 0x30 read-write n 0x0 0x0 CLKDIV I2C_CLKDIV I2C Clock Divided Register 0x10 read-write n 0x0 0x0 DIVIDER I2C Clock Divided Register\nNote: The minimum value of DIVIDER is 4. 0 8 read-write CTL I2C_CTL I2C Control Register 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control Bit 2 1 read-write I2CEN I2C Controller Enable Bit 6 1 read-write 0 I2C Controller Disabled #0 1 I2C Controller Enabled #1 INTEN Enable Interrupt 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL[7]) is set, the I2C interrupt is requested. SI must be cleared by software. Software can write 1 to clear this bit. 3 1 read-write STA I2C START Control Bit\nSetting STA to logic 1 to enter Master mode. I2C hardware sends a START or repeats the START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control Bit In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the Slave receiver mode to receive data from the master transmit device. 4 1 read-write CTL1 I2C_CTL1 I2C Control Register 1 0x3C read-write n 0x0 0x0 FIFOEN FIFO Mode Enable 1 1 read-write 0 Disabled #0 1 Enabled #1 NSTRETCH NO STRETCH The I2C BUS 2 1 read-write 0 The I2C SCL bus is stretched by hardware if the SI is not cleared in master mode #0 1 The I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode #1 OVIEN I2C OVER RUN Interrupt Control Bit Setting OVIEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received FIFO. 3 1 read-write 0 Disabled #0 1 Enabled #1 URIEN I2C UNDER RUN Interrupt Control Bit\nSetting URIEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted FIFO. 4 1 read-write 0 Disabled #0 1 Enabled #1 WKEN Wake-Up Enable\nThe system can be wake up by I2C bus when the system is set into power mode and the received data matched one of the addresses in Address Register. 0 1 read-write 0 I2C wake up function Disabled #0 1 I2C wake up function Enabled #1 DAT I2C_DAT I2C Data Register 0x8 read-write n 0x0 0x0 DAT I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of the I2C serial port. 0 8 read-write STATUS I2C_STATUS I2C Status Register 0xC -1 read-only n 0x0 0x0 STATUS I2C Status Register 0 8 read-only STATUS1 I2C_STATUS1 I2C Status Register 1 0x40 read-write n 0x0 0x0 EMPTY I2C TWO LEVEL FIFO EMPTY 2 1 read-write FULL I2C TWO LEVEL FIFO FULL 1 1 read-write OVIF I2C OVER RUN Status Bit 3 1 read-write URIF I2C UNDER RUN Status Bit 4 1 read-write WKIF I2C Wake-Up Interrupt Flag\nWhen chip is woken up from Power-Down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write TOCTL I2C_TOCTL I2C Time-Out Counter Register 0x14 read-write n 0x0 0x0 TOCDIV4 Time-Out Counter Input Clock Divided By 4 Note: When enabled, the time-out period is extended 4 times. 1 1 read-write 0 Time-out counter input clock divided by 4 Disabled #0 1 Time-out counter input clock divided by 4 Enabled #1 TOCEN Time-Out Counter Enabled\nNote: When the 14-bit time-out counter is enabled, it will start counting when SI is clear. Setting 1to the SI flag will reset counter and re-start up counting after SI is cleared. 2 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOIF Time-Out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit. 0 1 read-write INT INT Register Map INT 0x0 0x0 0x28 registers n 0x0 0x28 registers n 0x30 0xC registers n 0x40 0xC registers n 0x64 0x4 registers n 0x70 0x8 registers n 0x80 0x8 registers n IRQ0SRC IRQ0SRC IRQ0 (BOD) Interrupt Source Identity 0x0 read-only n 0x0 0x0 INT_SRC Interrupt Source 0 3 read-only IRQ12SRC IRQ12SRC IRQ12 (BOD) Interrupt Source Identity 0x30 read-write n 0x0 0x0 IRQ13SRC IRQ13SRC IRQ13 (BOD) Interrupt Source Identity 0x34 read-write n 0x0 0x0 IRQ14SRC IRQ14SRC IRQ14 (BOD) Interrupt Source Identity 0x38 read-write n 0x0 0x0 IRQ16SRC IRQ16SRC IRQ16 (BOD) Interrupt Source Identity 0x40 read-write n 0x0 0x0 IRQ17SRC IRQ17SRC IRQ17 (BOD) Interrupt Source Identity 0x44 read-write n 0x0 0x0 IRQ18SRC IRQ18SRC IRQ18 (BOD) Interrupt Source Identity 0x48 read-write n 0x0 0x0 IRQ1SRC IRQ1SRC IRQ1 (BOD) Interrupt Source Identity 0x4 read-write n 0x0 0x0 IRQ25SRC IRQ25SRC IRQ25 (BOD) Interrupt Source Identity 0x64 read-write n 0x0 0x0 IRQ28SRC IRQ28SRC IRQ28 (BOD) Interrupt Source Identity 0x70 read-write n 0x0 0x0 IRQ29SRC IRQ29SRC IRQ29 (BOD) Interrupt Source Identity 0x74 read-write n 0x0 0x0 IRQ2SRC IRQ2SRC IRQ2 (BOD) Interrupt Source Identity 0x8 read-write n 0x0 0x0 IRQ3SRC IRQ3SRC IRQ3 (BOD) Interrupt Source Identity 0xC read-write n 0x0 0x0 IRQ4SRC IRQ4SRC IRQ4 (BOD) Interrupt Source Identity 0x10 read-write n 0x0 0x0 IRQ5SRC IRQ5SRC IRQ5 (BOD) Interrupt Source Identity 0x14 read-write n 0x0 0x0 IRQ6SRC IRQ6SRC IRQ6 (BOD) Interrupt Source Identity 0x18 read-write n 0x0 0x0 IRQ7SRC IRQ7SRC IRQ7 (BOD) Interrupt Source Identity 0x1C read-write n 0x0 0x0 IRQ8SRC IRQ8SRC IRQ8 (BOD) Interrupt Source Identity 0x20 read-write n 0x0 0x0 IRQ9SRC IRQ9SRC IRQ9 (BOD) Interrupt Source Identity 0x24 read-write n 0x0 0x0 IRQSTS IRQSTS MCU IRQ Number Identity Register 0x84 read-write n 0x0 0x0 IRQ MCU IRQ Source Register\nThe IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. There are two modes to generate interrupt to Cortex-M0 - the normal mode and test mode.\nThe IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0.\nWhen the IRQ[n] is 0, setting IRQ[n] to 1 will generate an interrupt to Cortex-M0 NVIC[n].\nWhen the IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting IRQ[n] 0 has no effect. 0 32 read-write NMICTL NMICTL NMI Source Interrupt Select Control Register 0x80 read-write n 0x0 0x0 NMISELEN NMI Interrupt Enable Control (Write Protected)\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address SYS_BA+0x100. 8 1 read-write 0 NMI interrupt Disabled #0 1 NMI interrupt Enabled #1 NMTSEL NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMTSEL. 0 5 read-write PWM PWM Register Map PWM 0x0 0x0 0x3C registers n 0x54 0x34 registers n ADCTCTL0 PWM_ADCTCTL0 PWM Trigger Control Register 0 0x68 read-write n 0x0 0x0 CDTRGEN0 PWM Channel 0 Compare Down Count Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode. 2 1 read-write 0 Disabled #0 1 Enabled #1 CDTRGEN1 PWM Channel 1 Compare Down Count Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode. 10 1 read-write 0 Disabled #0 1 Enabled #1 CDTRGEN2 PWM Channel 2 Compare Down Count Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode. 18 1 read-write 0 Disabled #0 1 Enabled #1 CDTRGEN3 PWM Channel 3 Compare Down Count Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode. 26 1 read-write 0 Disabled #0 1 Enabled #1 CPTRGEN0 PWM Channel 0 Center Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. 1 1 read-write 0 Disabled #0 1 Enabled #1 CPTRGEN1 Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. 9 1 read-write 1 Enabled #1 CPTRGEN2 PWM Channel 2 Center Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. 17 1 read-write 0 Disabled #0 1 Enabled #1 CPTRGEN3 PWM Channel 3 Center Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. 25 1 read-write 0 Disabled #0 1 Enabled #1 CUTRGEN0 PWM Channel 0 Compare Up Count Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. 0 1 read-write 0 Disabled #0 1 Enabled #1 CUTRGEN1 PWM Channel 1 Compare Up Count Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. 8 1 read-write 0 Disabled #0 1 Enabled #1 CUTRGEN2 PWM Channel 2 Compare Up Count Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. 16 1 read-write 0 Disabled #0 1 Enabled #1 CUTRGEN3 PWM Channel 3 Compare Up Count Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. 24 1 read-write 0 Disabled #0 1 Enabled #1 ZPTRGEN0 PWM Channel 0 Zero Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode. 3 1 read-write 0 Disabled #0 1 Enabled #1 ZPTRGEN1 PWM Channel 1 Zero Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode. 11 1 read-write 0 Disabled #0 1 Enabled #1 ZPTRGEN2 PWM Channel 2 Zero Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode. 19 1 read-write 0 Disabled #0 1 Enabled #1 ZPTRGEN3 PWM Channel 3 Zero Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode. 27 1 read-write 0 Disabled #0 1 Enabled #1 ADCTCTL1 PWM_ADCTCTL1 PWM Trigger Control Register 1 0x6C read-write n 0x0 0x0 CDTRGEN4 PWM Channel 4 Compare Down Count Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode. 2 1 read-write 0 Disabled #0 1 Enabled #1 CDTRGEN5 PWM Channel 5 Compare Down Count Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode. 10 1 read-write 0 Disabled #0 1 Enabled #1 CPTRGEN4 PWM Channel 4 Center Point Trigger ADC Enable Bit\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. 1 1 read-write 0 Disabled #0 1 Enabled #1 CPTRGEN5 PWM Channel 5 Center Point Trigger ADC Enable Bit\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. 9 1 read-write 0 Disabled #0 1 Enabled #1 CUTRGEN4 PWM Channel 4 Compare Up Count Point Trigger ADC Enable Bit\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. 0 1 read-write 0 Disabled #0 1 Enabled #1 CUTRGEN5 PWM Channel 5 Compare Up Count Point Trigger ADC Enable Bit\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. 8 1 read-write 0 Disabled #0 1 Enabled #1 ZPTRGEN4 PWM Channel 4 Zero Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode. 3 1 read-write 0 Disabled #0 1 Enabled #1 ZPTRGEN5 PWM Channel 5 Zero Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode. 11 1 read-write 0 Disabled #0 1 Enabled #1 ADCTSTS0 PWM_ADCTSTS0 PWM Trigger Status Register 0 0x70 read-write n 0x0 0x0 CDTRGF0 PWM Channel 0 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 2 1 read-write CDTRGF1 PWM Channel 1 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 10 1 read-write CDTRGF2 PWM Channel 2 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 18 1 read-write CDTRGF3 PWM Channel 3 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 26 1 read-write CPTRGF0 PWM Channel 0 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 1 1 read-write CPTRGF1 PWM Channel 1 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 9 1 read-write CPTRGF2 PWM Channel 2 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 17 1 read-write CPTRGF3 PWM Channel 3 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 25 1 read-write CUTRGF0 PWM Channel 0 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 0 1 read-write CUTRGF1 PWM Channel 1 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 8 1 read-write CUTRGF2 PWM Channel 3 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 16 1 read-write CUTRGF3 PWM Channel 3 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 24 1 read-write ZPTRGF0 PWM Channel 0 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 3 1 read-write ZPTRGF1 PWM Channel 1 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 11 1 read-write ZPTRGF2 PWM Channel 2 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 19 1 read-write ZPTRGF3 PWM Channel 3 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 27 1 read-write ADCTSTS1 PWM_ADCTSTS1 PWM Trigger Status Register 1 0x74 read-write n 0x0 0x0 CDTRGF4 PWM Channel 4 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 2 1 read-write CDTRGF5 PWM Channel 5 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 10 1 read-write CPTRGF4 PWM Channel 4 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 1 1 read-write CPTRGF5 PWM Channel 5 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 9 1 read-write CUTRGF4 PWM Channel 4 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 0 1 read-write CUTRGF5 PWM Channel 5 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 8 1 read-write ZPTRGF4 PWM Channel 4 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 3 1 read-write ZPTRGF5 PWM Channel 5 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit. 11 1 read-write BRKCTL PWM_BRKCTL PWM Fault Brake Control Register 0x60 read-write n 0x0 0x0 BKOD0 PWM Channel 0 Brake Output Select Register 24 1 read-write 0 PWM output low when fault brake conditions asserted #0 1 PWM output high when fault brake conditions asserted #1 BKOD1 PWM Channel 1 Brake Output Select Register 25 1 read-write 0 PWM output low when fault brake conditions asserted #0 1 PWM output high when fault brake conditions asserted #1 BKOD2 PWM Channel 2 Brake Output Select Register 26 1 read-write 0 PWM output low when fault brake conditions asserted #0 1 PWM output high when fault brake conditions asserted #1 BKOD3 PWM Channel 3 Brake Output Select Register 27 1 read-write 0 PWM output low when fault brake conditions asserted #0 1 PWM output high when fault brake conditions asserted #1 BKOD4 PWM Channel 4 Brake Output Select Register 28 1 read-write 0 PWM output low when fault brake conditions asserted #0 1 PWM output high when fault brake conditions asserted #1 BKOD5 PWM Channel 5 Brake Output Select Register 29 1 read-write 0 PWM output low when fault brake conditions asserted #0 1 PWM output high when fault brake conditions asserted #1 BRK0EN Enable BKP0 Pin Trigger Fault Brake Function 0 0 1 read-write 0 Disabling BKP0 pin can trigger brake function 0 (EINT0 or CPO1) #0 1 Enabling a falling at BKP0 pin can trigger brake function 0 #1 BRK0SEL BKP1 Fault Brake Function Source Selection 2 1 read-write 0 EINT1 as one brake source in BKP1 #0 1 CPO0 as one brake source in BKP1 #1 BRK1EN Enable BKP1 Pin Trigger Fault Brake Function 1 1 1 read-write 0 Disabling BKP1 pin can trigger brake function 1 (EINT1 or CPO0) #0 1 Enabling a falling at BKP1 pin can trigger brake function 1 #1 BRK1SEL BKP0 Fault Brake Function Source Selection 3 1 read-write 0 EINT0 as one brake source in BKP0 #0 1 CPO1 as one brake source in BKP0 #1 BRKACT PWM Brake Type 8 1 read-write 0 PWM counter stop when brake is asserted #0 1 PWM counter keep going when brake is asserted #1 BRKSTS PWM Fault Brake Event Flag (Write 1 Clear)\nSoftware can write 1 to clear this bit and must clear this bit before restart PWM counter. 7 1 read-write 0 PWM output initial state when fault brake conditions asserted #0 1 PWM output fault brake state when fault brake conditions asserted #1 D6BKOD D6 Brake Output Select Register 30 1 read-write 0 D6 output low when fault brake conditions asserted #0 1 D6 output high when fault brake conditions asserted #1 D7BKOD D7 Brake Output Select Register 31 1 read-write 0 D7 output low when fault brake conditions asserted #0 1 D7 output high when fault brake conditions asserted #1 SWBRK Software Brake 9 1 read-write 0 Disable PWM Software brake and back to normal PWM function #0 1 Assert PWM Brake immediately #1 CLKDIV PWM_CLKDIV PWM Clock Select Register 0x4 read-write n 0x0 0x0 CLKDIV0 Timer 0 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CLKDIV5.) 0 3 read-write CLKDIV1 Timer 1 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CLKDIV5.) 4 3 read-write CLKDIV2 Timer 2 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CLKDIV5.) 8 3 read-write CLKDIV3 Timer 3 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CLKDIV5.) 12 3 read-write CLKDIV4 Timer 4 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CLKDIV5.) 16 3 read-write CLKDIV5 Timer 5 Clock Source Selection\nSelect clock input for PWM timer. 20 3 read-write 0 2 clock input/CLKPSC45/2 #000 1 4 clock input/CLKPSC45/4 #001 3 8 clock input/CLKPSC45/8 #011 4 16 clock input/CLKPSC45/16 #100 5 1 clock input/CLKPSC45/1 #101 6 Clock input #110 7 Reserved #111 CLKPSC PWM_CLKPSC PWM Pre-scale Register 0x0 read-write n 0x0 0x0 CLKPSC01 Clock Prescaler 0 For PWM Counter 0 And 1 Clock input is divided by (CLKPSC01 + 1) before it is fed to the corresponding PWM counter. 0 8 read-write CLKPSC23 Clock Prescaler 2 For PWM Counter 2 And 3\nClock input is divided by (CLKPSC23 + 1) before it is fed to the corresponding PWM counter. 8 8 read-write CLKPSC45 Clock Prescaler 4 For PWM Counter 4 And 5\nClock input is divided by (CLKPSC45 + 1) before it is fed to the corresponding PWM counter. 16 8 read-write CMPDAT0 PWM_CMPDAT0 PWM Comparator Register 0 0x24 read-write n 0x0 0x0 CMP PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned mode:\nNote: Any write to CMP will take effect in next PWM cycle. 0 16 read-write CMPD PWM Comparator Register For Down Counter In Center-Aligned Asymmetric Mode\nOthers: PWM output is always high 16 16 read-write CMPDAT1 PWM_CMPDAT1 PWM Comparator Register 1 0x28 read-write n 0x0 0x0 CMPDAT2 PWM_CMPDAT2 PWM Comparator Register 2 0x2C read-write n 0x0 0x0 CMPDAT3 PWM_CMPDAT3 PWM Comparator Register 3 0x30 read-write n 0x0 0x0 CMPDAT4 PWM_CMPDAT4 PWM Comparator Register 4 0x34 read-write n 0x0 0x0 CMPDAT5 PWM_CMPDAT5 PWM Comparator Register 5 0x38 read-write n 0x0 0x0 CTL PWM_CTL PWM Control Register 0x8 read-write n 0x0 0x0 ASYMEN Asymmetric Mode In Center-Aligned Type 21 1 read-write 0 symmetric mode in center-aligned type #0 1 asymmetric mode in center-aligned type #1 CNTCLR Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware. 27 1 read-write 0 Do not clear PWM counter #0 1 All 16-bit PWM counters cleared to 0x0000 #1 CNTEN0 PWM-Timer 0 Enable/Disable Start Run 0 1 read-write 0 Corresponding PWM-timer running Stopped #0 1 Corresponding PWM-timer start run Enabled #1 CNTEN1 PWM-Timer 1 Enable/Disable Start Run 4 1 read-write 0 Corresponding PWM-timer running Stopped #0 1 Corresponding PWM-timer start run Enabled #1 CNTEN2 PWM-Timer 2 Enable/Disable Start Run 8 1 read-write 0 Corresponding PWM-timer running Stopped #0 1 Corresponding PWM-timer start run Enabled #1 CNTEN3 PWM-Timer 3 Enable/Disable Start Run 12 1 read-write 0 Corresponding PWM-timer running Stopped #0 1 Corresponding PWM-timer start run Enabled #1 CNTEN4 PWM-Timer 4 Enable/Disable Start Run 16 1 read-write 0 Corresponding PWM-timer running Stopped #0 1 Corresponding PWM-timer start run Enabled #1 CNTEN5 PWM-Timer 5 Enable/Disable Start Run 20 1 read-write 0 Corresponding PWM-timer running Stopped #0 1 Corresponding PWM-timer start run Enabled #1 CNTMODE0 PWM-Timer 0 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD0 and PWM_CMPDAT0 cleared. 3 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CNTMODE1 PWM-Timer 1 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD1 and PWM_CMPDAT1 cleared. 7 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CNTMODE2 PWM-Timer 2 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD2 and PWM_CMPDAT2 cleared. 11 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CNTMODE3 PWM-Timer 3 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD3 and PWM_CMPDAT3 cleared. 15 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CNTMODE4 PWM-Timer 4 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD4 and PWM_CMPDAT4 cleared. 19 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CNTMODE5 PWM-Timer 5 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD5 and PWM_CMPDAT5 cleared. 23 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CNTTYPE PWM Aligned Type Selection Bit 31 1 read-write 0 Edge-aligned type #0 1 Center-aligned type #1 DBGTRIOFF PWM Debug Mode Configuration Bit (Available In DEBUG Mode Only) 1 1 read-write 0 Safe mode: The timer is frozen and PWM outputs are shut down Safe state for the inverter. The timer can still be re-started from where it stops #0 1 Normal mode: The timer continues to operate normally May be dangerous in some cases since a constant duty cycle is applied to the inverter (no more interrupts serviced) #1 DTCNT01 Dead-Zone 0 Generator Enable/Disable (PWM0 And PWM1 Pair For PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group. 24 1 read-write 0 Disabled #0 1 Enabled #1 DTCNT23 Dead-Zone 2 Generator Enable/Disable (PWM2 And PWM3 Pair For PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group. 25 1 read-write 0 Disabled #0 1 Enabled #1 DTCNT45 Dead-Zone 4 Generator Enable/Disable (PWM4 And PWM5 Pair For PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM4 and PWM5 becomes a complementary pair for PWM group. 26 1 read-write 0 Disabled #0 1 Enabled #1 GROUPEN Group Bit 30 1 read-write 0 The signals timing of all PWM channels are independent #0 1 Unify the signals timing of PWM0, PWM2 and PWM4 in the same phase which is controlled by PWM0 and also unify the signals timing of PWM1, PWM3 and PWM5 in the same phase which is controlled by PWM1 #1 HCUPDT Half Cycle Update Enable For Center-Aligned Type 5 1 read-write 0 disable half cycle update PERIOD CMP #0 1 enable half cycle update PERIOD CMP #1 MODE PWM Operating Mode Selection 28 2 read-write 0 Independent mode #00 1 Complementary mode #01 2 Synchronized mode #10 3 Reserved #11 PINV0 PWM-Timer 0 Output Inverter Enabled/Disabled 2 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 PINV1 PWM-Timer 1 Output Inverter Enabled/Disabled 6 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 PINV2 PWM-Timer 2 Output Inverter Enabled/Disabled 10 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 PINV3 PWM-Timer 3 Output Inverter Enabled/Disabled 14 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 PINV4 PWM-Timer 4 Output Inverter Enabled/Disabled 18 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 PINV5 PWM-Timer 5 Output Inverter Enabled/Disabled 22 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 DTCTL PWM_DTCTL PWM Dead-zone Interval Register 0x64 read-write n 0x0 0x0 DTCNT01 Dead-Zone Interval Register For Pair Of Channel0 And Channel1 (PWM0 And PWM1 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CLKDIV bits. 0 8 read-write DTCNT23 Dead-Zone Interval Register For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CLKDIV bits. 8 8 read-write DTCNT45 Dead-Zone Interval Register For Pair Of Channel4 And Channel5 (PWM4 And PWM5 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CLKDIV bits. 16 8 read-write IFA PWM_IFA Period Interrupt Accumulation Control Register 0x84 -1 read-write n 0x0 0x0 IFAEN Interrupt Accumulation Enable 0 1 read-write 0 Disabled #0 1 Enabled #1 IFCNT Interrupt Accumulation Count\nWhen IFCNT is set, IFCNT will decrease when every ZIF0 flag is set and when IFCNT reach to zero, the PWM0 interrupt will occurred and IFCNT will reload itself. 4 4 read-write INTEN PWM_INTEN PWM Interrupt Enable Register 0x54 read-write n 0x0 0x0 BRKIEN Enable Fault Brake0 And 1 Interrupt 16 1 read-write 0 Disabling flags BRKIF0 and BRKIF1 to trigger PWM interrupt #0 1 Enabling flags BRKIF0 and BRKIF1 can trigger PWM interrupt #1 CMPDIEN0 PWM Channel 0 Duty Interrupt Enable 8 1 read-write 0 Disabled #0 1 Enabled #1 CMPDIEN1 PWM Channel 1 Duty Interrupt Enable 9 1 read-write 0 Disabled #0 1 Enabled #1 CMPDIEN2 PWM Channel 2 Duty Interrupt Enable 10 1 read-write 0 Disabled #0 1 Enabled #1 CMPDIEN3 PWM Channel 3 Duty Interrupt Enable 11 1 read-write 0 Disabled #0 1 Enabled #1 CMPDIEN4 PWM Channel 4 Duty Interrupt Enable 12 1 read-write 0 Disabled #0 1 Enabled #1 CMPDIEN5 PWM Channel 5 Duty Interrupt Enable 13 1 read-write 0 Disabled. Rising for edge aligned mode. Falling for center aligned mode #0 1 Enabled #1 CMPUIEN0 PWM Channel 0 Rising Interrupt Enable 24 1 read-write 0 Disabled #0 1 Enabled #1 CMPUIEN1 PWM Channel 1 Rising Interrupt Enable 25 1 read-write 0 Disabled #0 1 Enabled #1 CMPUIEN2 PWM Channel 2 Rising Interrupt Enable 26 1 read-write 0 Disabled #0 1 Enabled #1 CMPUIEN3 PWM Channel 3 Rising Interrupt Enable 27 1 read-write 0 Disabled #0 1 Enabled #1 CMPUIEN4 PWM Channel 4 Rising Interrupt Enable 28 1 read-write 0 Disabled #0 1 Enabled #1 CMPUIEN5 PWM Channel 5 Rising Interrupt Enable 29 1 read-write 0 Disabled #0 1 Enabled #1 PIEN0 PWM Channel 0 Central Interrupt Enable 18 1 read-write 0 Disabled #0 1 Enabled #1 PIEN1 PWM Channel 1 Central Interrupt Enable 19 1 read-write 0 Disabled #0 1 Enabled #1 PIEN2 PWM Channel 2 Central Interrupt Enable 20 1 read-write 0 Disabled #0 1 Enabled #1 PIEN3 PWM Channel 3 Central Interrupt Enable 21 1 read-write 0 Disabled #0 1 Enabled #1 PIEN4 PWM Channel 4 Central Interrupt Enable 22 1 read-write 0 Disabled #0 1 Enabled #1 PIEN5 PWM Channel 5 Central Interrupt Enable 23 1 read-write 0 Disabled #0 1 Enabled #1 PINTTYPE PWM Period Interrupt Type Selection\nNote: This bit is effective when PWM in central align mode only. 17 1 read-write 0 ZIFn will be set if PWM counter underflows #0 1 ZIFn will be set if PWM counter matches PERIODn register #1 ZIEN0 PWM Channel 0 Period Interrupt Enable 0 1 read-write 0 Disabled #0 1 Enabled #1 ZIEN1 PWM Channel 1 Period Interrupt Enable 1 1 read-write 0 Disabled #0 1 Enabled #1 ZIEN2 PWM Channel 2 Period Interrupt Enable 2 1 read-write 0 Disabled #0 1 Enabled #1 ZIEN3 PWM Channel 3 Period Interrupt Enable 3 1 read-write 0 Disabled #0 1 Enabled #1 ZIEN4 PWM Channel 4 Period Interrupt Enable 4 1 read-write 0 Disabled #0 1 Enabled #1 ZIEN5 PWM Channel 5 Period Interrupt Enable 5 1 read-write 0 Disabled #0 1 Enabled #1 INTSTS PWM_INTSTS PWM Interrupt Indication Register 0x58 read-write n 0x0 0x0 BRKIF0 PWM Brake0 Flag\nNote: Software can write 1 to clear this bit. 16 1 read-write 0 PWM Brake does not recognize a falling signal at BKP0 #0 1 When PWM Brake detects a falling signal at pin BKP0, this flag will be set to high #1 BRKIF1 PWM Brake1 Flag\nNote: Software can write 1 to clear this bit. 17 1 read-write 0 PWM Brake does not recognize a falling signal at BKP1 #0 1 When PWM Brake detects a falling signal at pin BKP1, this flag will be set to high #1 CMPDIF0 PWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when a channel 0 PWM counter reaches PWM_CMPDAT0 in down-count direction. \nNote: Software can write 1 to clear this bit. 8 1 read-write CMPDIF1 PWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when a channel 1 PWM counter reaches PWM_CMPDAT1 in down-count direction. \nNote: Software can write 1 to clear this bit. 9 1 read-write CMPDIF2 PWM Channel 2 Duty Interrupt Flag\nFlag is set by hardware when a channel 2 PWM counter reaches PWM_CMPDAT2 in down-count direction. \nNote: Software can write 1 to clear this bit. 10 1 read-write CMPDIF3 PWM Channel 3 Duty Interrupt Flag\nFlag is set by hardware when a channel 3 PWM counter reaches PWM_CMPDAT3 in down-count direction. \nNote: Software can write 1 to clear this bit. 11 1 read-write CMPDIF4 PWM Channel 4 Duty Interrupt Flag\nFlag is set by hardware when a channel 4 PWM counter reaches PWM_CMPDAT4 in down-count direction. \nNote: Software can write 1 to clear this bit. 12 1 read-write CMPDIF5 PWM Channel 5 Duty Interrupt Flag\nFlag is set by hardware when a channel 5 PWM counter reaches PWM_CMPDAT5 in down-count direction. \nNote: Software can write 1 to clear this bit. 13 1 read-write CMPUIF0 PWM Channel 1 Rise Interrupt Flag\nFlag is set by hardware when a channel 0 PWM rise counter reaches PWM_CMPDAT0. Software can write 1 to clear this bit. 24 1 read-write CMPUIF1 PWM Channel 1 Rise Interrupt Flag\nFlag is set by hardware when a channel 1 PWM rise counter reaches PWM_CMPDAT1. Software can write 1 to clear this bit. 25 1 read-write CMPUIF2 PWM Channel 2 Rise Interrupt Flag\nFlag is set by hardware when a channel 2 PWM rise counter reaches PWM_CMPDAT2. Software can write 1 to clear this bit. 26 1 read-write CMPUIF3 PWM Channel 3 Rise Interrupt Flag\nFlag is set by hardware when a channel 3 PWM rise counter reaches PWM_CMPDAT3. Software can write 1 to clear this bit. 27 1 read-write CMPUIF4 PWM Channel 4 Rise Interrupt Flag\nFlag is set by hardware when a channel 4 PWM rise counter reaches PWM_CMPDAT4. Software can write 1 to clear this bit. 28 1 read-write CMPUIF5 PWM Channel 5 Rise Interrupt Flag\nFlag is set by hardware when a channel 5 PWM rise counter reaches \nPWM_CNT0\n5. Software can write 1 to clear this bit. 29 1 read-write PIF0 PWM Channel 0 Center Interrupt Flag\nFlag is set by hardware when a channel 0 PWM rise counter reaches CNT0. Software can write 1 to clear this bit. 18 1 read-write PIF1 PWM Channel 1 Center Interrupt Flag\nFlag is set by hardware when a channel 1 PWM rise counter reaches CNT1. Software can write 1 to clear this bit. 19 1 read-write PIF2 PWM Channel 2 Center Interrupt Flag\nFlag is set by hardware when a channel 2 PWM rise counter reaches CNT2. Software can write 1 to clear this bit. 20 1 read-write PIF3 PWM Channel 3 Center Interrupt Flag\nFlag is set by hardware when a channel 3 PWM rise counter reaches CNT3. Software can write 1 to clear this bit. 21 1 read-write PIF4 PWM Channel 4 Center Interrupt Flag\nFlag is set by hardware when a channel 4 PWM rise counter reaches CNT4. Software can write 1 to clear this bit. 22 1 read-write PIF5 PWM Channel 5 Center Interrupt Flag\nFlag is set by hardware when a channel 5 PWM rise counter reaches CNT5. Software can write 1 to clear this bit. 23 1 read-write ZIF0 PWM Channel 0 Period Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches zero. \nNote: Software can write 1 to clear this bit. 0 1 read-write ZIF1 PWM Channel 1 Period Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches zero. \nNote: Software can write 1 to clear this bit. 1 1 read-write ZIF2 PWM Channel 2 Period Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches zero. \nNote: Software can write 1 to clear this bit. 2 1 read-write ZIF3 PWM Channel 3 Period Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches zero. \nNote: Software can write 1 to clear this bit. 3 1 read-write ZIF4 PWM Channel 4 Period Interrupt Flag\nFlag is set by hardware when PWM4 down counter reaches zero. \nNote: Software can write 1 to clear this bit. 4 1 read-write ZIF5 PWM Channel 5 Period Interrupt Flag\nFlag is set by hardware when PWM5 down counter reaches zero. \nNote: Software can write 1 to clear this bit. 5 1 read-write PERIOD0 PWM_PERIOD0 PWM Counter Register 0 0xC read-write n 0x0 0x0 PERIOD PWM Counter/Timer Loaded Value\nPERIOD determines the PWM period.\nEdge-aligned mode:\nNote: Any write to PERIOD will take effect in next PWM cycle. 0 16 read-write PERIOD1 PWM_PERIOD1 PWM Counter Register 1 0x10 read-write n 0x0 0x0 PERIOD2 PWM_PERIOD2 PWM Counter Register 2 0x14 read-write n 0x0 0x0 PERIOD3 PWM_PERIOD3 PWM Counter Register 3 0x18 read-write n 0x0 0x0 PERIOD4 PWM_PERIOD4 PWM Counter Register 4 0x1C read-write n 0x0 0x0 PERIOD5 PWM_PERIOD5 PWM Counter Register 5 0x20 read-write n 0x0 0x0 PHCHG PWM_PHCHG Phase Changed Register 0x78 -1 read-write n 0x0 0x0 A0POSSEL A0POSSEL\nSelect the positive input source of ACMP0. 28 2 read-write 0 Select P1.5 as the input of ACMP0 #00 1 Select P1.0 as the input of ACMP0 #01 2 Select P1.2 as the input of ACMP0 #10 3 Select P1.3 as the input of ACMP0 #11 A1POSSEL A1POSSEL\nSelect the positive input source of ACMP1. 20 2 read-write 0 Select P3.1 as the input of ACMP1 #00 1 Select P3.2 as the input of ACMP1 #01 2 Select P3.3 as the input of ACMP1 #10 3 Select P3.4 as the input of ACMP1 #11 ACMP0TEN Enable ACMP0 Trigger Function\nNote: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set. 31 1 read-write 0 Disabled #0 1 Enabled #1 ACMP1TEN Enable ACMP1 Trigger Function\nNote: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set. 23 1 read-write 0 Disabled #0 1 Enabled #1 AUTOCLR0 Hardware Auto Clear ACMP0TEN When ACMP0 Trigger It 14 1 read-write 0 Enabled #0 1 Disabled #1 AUTOCLR1 Hardware Auto Clear ACMP1TEN When ACMP1 Trigger It 15 1 read-write 0 Enabled #0 1 Disabled #1 MSKDAT0 MSKDAT0: When MSKEN0 Is Zero, Channel 0's Output Waveform Is MSKDAT0 0 1 read-write 0 Output low #0 1 Output high #1 MSKDAT1 MSKDAT1: When MSKEN1is Zero, Channel 1's Output Waveform Is MSKDAT1 1 1 read-write 0 Output low #0 1 Output high #1 MSKDAT2 MSKDAT2: When MSKEN2 Is Zero, Channel 2's Output Waveform Is MSKDAT2 2 1 read-write 0 Output low #0 1 Output high #1 MSKDAT3 MSKDAT3: When MSKEN3 Is Zero, Channel 3's Output Waveform Is MSKDAT3 3 1 read-write 0 Output low #0 1 Output high #1 MSKDAT4 MSKDAT4: When MSKEN4is Zero, Channel 4's Output Waveform Is MSKDAT4 4 1 read-write 0 Output low #0 1 Output high #1 MSKDAT5 MSKDAT5: When MSKEN5 Is Zero, Channel 5's Output Waveform Is MSKDAT5 5 1 read-write 0 Output low #0 1 Output high #1 MSKDAT6 MSKDAT6: When MSKEN6 Is 1, Channel 6's Output Waveform Is MSKDAT6 6 1 read-write 0 Output low #0 1 Output high #1 MSKDAT7 MSKDAT7: When MSKEN7 Is 1, Channel 7's Output Waveform Is MSKDAT7 7 1 read-write 0 Output low #0 1 Output high #1 MSKEN0 MSKEN Channel 0 Output Enable Control 8 1 read-write 0 Output MSKDAT0 specified in bit 0 of PWM_PHCHG register #0 1 Output the original channel 0 waveform #1 MSKEN1 MSKEN Channel 1 Output Enable Control 9 1 read-write 0 Output MSKDAT1 specified in bit 1 of PWM_PHCHG register #0 1 Output the original channel 1 waveform #1 MSKEN2 MSKEN Channel 2 Output Enable Control 10 1 read-write 0 Output MSKDAT2 specified in bit 2 of PWM_PHCHG register #0 1 Output the original channel 2 waveform #1 MSKEN3 MSKEN Channel 3 Output Enable Control 11 1 read-write 0 Output MSKDAT3 specified in bit 3 of PWM_PHCHG register #0 1 Output the original channel 3 waveform #1 MSKEN4 MSKEN Channel 4 Output Enable Control 12 1 read-write 0 Output MSKDAT4 specified in bit 4 of PWM_PHCHG register #0 1 Output the original channel 4 waveform #1 MSKEN5 MSKEN Channel 5 Output Enable Control 13 1 read-write 0 Output MSKDAT5 specified in bit 5 of PWM_PHCHG register #0 1 Output the original channel 5 waveform #1 OFFEN00 Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. 24 1 read-write 0 Disabled #0 1 Enabled #1 OFFEN01 Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. 16 1 read-write 0 Disabled #0 1 Enabled #1 OFFEN10 Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. 25 1 read-write 0 Disabled #0 1 Enabled #1 OFFEN11 Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. 17 1 read-write 0 Disabled #0 1 Enabled #1 OFFEN20 Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. 26 1 read-write 0 Disabled #0 1 Enabled #1 OFFEN21 Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. 18 1 read-write 0 Disabled #0 1 Enabled #1 OFFEN30 Setting This Bit Will Force MSKEN3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. 27 1 read-write 0 Disabled #0 1 Enabled #1 OFFEN31 Setting This Bit Will Force MSKEN3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. 19 1 read-write 0 Disabled #0 1 Enabled #1 T0 Enable Timer0 Trigger PWM Function\nWhen this bit is set, timer0 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register. 30 1 read-write 0 Disabled #0 1 Enabled #1 TMR1TEN Enable Timer1 Trigger PWM Function\nWhen this bit is set, timer1 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register. 22 1 read-write 0 Disabled #0 1 Enabled #1 PHCHGMSK PWM_PHCHGMSK Phase Change MASK Register 0x80 read-write n 0x0 0x0 MASKEND6 MASK For D6 6 1 read-write 0 Original GPIO P0.1 #0 1 D6 #1 MASKEND7 MASK For D7 7 1 read-write 0 Original GPIO P0.0 #0 1 D7 #1 POSCTL0 ACMP0 Positive Input Selection Control Note: Register CMP0CR is describe in Comparator Controller chapter 8 1 read-write 0 The input of ACMP0 is controlled by CMP0CR #0 1 The input of ACMP0 is controlled by A0POSSEL of PWM_PHCHG register #1 POSCTL1 ACMP1 Positive Input Selection Control\nNote: Register CMP1CR is describe in Comparator Controller chapter 9 1 read-write 0 The input of ACMP1 is controlled by CMP1CR #0 1 The input of ACMP1 is controlled by A1POSSEL of PWM_PHCHG register #1 PHCHGNXT PWM_PHCHGNXT Next Phase Change Register 0x7C -1 read-write n 0x0 0x0 A0POSSEL A0POSSEL\nSelect the positive input source of ACMP0. 28 2 read-write 0 Select P1.5 as the input of ACMP0 #00 1 Select P1.0 as the input of ACMP0 #01 2 Select P1.2 as the input of ACMP0 #10 3 Select P1.3 as the input of ACMP0 #11 A1POSSEL A1POSSEL\nSelect the positive input source of ACMP1. 20 2 read-write 0 Select P3.1 as the input of ACMP1 #00 1 Select P3.2 as the input of ACMP1 #01 2 Select P3.3 as the input of ACMP1 #10 3 Select P3.4 as the input of ACMP1 #11 ACMP0TEN Enable ACMP0 Trigger Function\nNote: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set. 31 1 read-write 0 Disabled #0 1 Enabled #1 ACMP1TEN Enable ACMP1 Trigger Function\nNote: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set. 23 1 read-write 0 Disabled #0 1 Enabled #1 AUTOCLR0 Hardware Auto Clear ACMP0TEN When ACMP0 Trigger It 14 1 read-write 0 Enabled #0 1 Disabled #1 AUTOCLR1 Hardware Auto Clear ACMP1TEN When ACMP1 Trigger It 15 1 read-write 0 Enabled #0 1 Disabled #1 MSKDAT0 MSKDAT0: When MSKEN0 Is Zero, Channel 0's Output Waveform Is MSKDAT0 0 1 read-write 0 Output low #0 1 Output high #1 MSKDAT1 MSKDAT1: When MSKEN1is Zero, Channel 1's Output Waveform Is MSKDAT1 1 1 read-write 0 Output low #0 1 Output high #1 MSKDAT2 MSKDAT2: When MSKEN2 Is Zero, Channel 2's Output Waveform Is MSKDAT2 2 1 read-write 0 Output low #0 1 Output high #1 MSKDAT3 MSKDAT3: When MSKEN3 Is Zero, Channel 3's Output Waveform Is MSKDAT3 3 1 read-write 0 Output low #0 1 Output high #1 MSKDAT4 MSKDAT4: When MSKEN4is Zero, Channel 4's Output Waveform Is MSKDAT4 4 1 read-write 0 Output low #0 1 Output high #1 MSKDAT5 MSKDAT5: When MSKEN5 Is Zero, Channel 5's Output Waveform Is MSKDAT5 5 1 read-write 0 Output low #0 1 Output high #1 MSKDAT6 MSKDAT6: When MSKEN6 Is 1, Channel 6's Output Waveform Is MSKDAT6 6 1 read-write 0 Output low #0 1 Output high #1 MSKDAT7 MSKDAT7: When MSKEN7 Is 1, Channel 7's Output Waveform Is MSKDAT7 7 1 read-write 0 Output low #0 1 Output high #1 MSKEN0 MSKEN Channel 0 Output Enable Control 8 1 read-write 0 Output MSKDAT0 specified in bit 0 of PWM_PHCHG register #0 1 Output the original channel 0 waveform #1 MSKEN1 MSKEN Channel 1 Output Enable Control 9 1 read-write 0 Output MSKDAT1 specified in bit 1 of PWM_PHCHG register #0 1 Output the original channel 1 waveform #1 MSKEN2 MSKEN Channel 2 Output Enable Control 10 1 read-write 0 Output MSKDAT2 specified in bit 2 of PWM_PHCHG register #0 1 Output the original channel 2 waveform #1 MSKEN3 MSKEN Channel 3 Output Enable Control 11 1 read-write 0 Output MSKDAT3 specified in bit 3 of PWM_PHCHG register #0 1 Output the original channel 3 waveform #1 MSKEN4 MSKEN Channel 4 Output Enable Control 12 1 read-write 0 Output MSKDAT4 specified in bit 4 of PWM_PHCHG register #0 1 Output the original channel 4 waveform #1 MSKEN5 MSKEN Channel 5 Output Enable Control 13 1 read-write 0 Output MSKDAT5 specified in bit 5 of PWM_PHCHG register #0 1 Output the original channel 5 waveform #1 OFFEN00 Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. 24 1 read-write 0 Disabled #0 1 Enabled #1 OFFEN01 Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. 16 1 read-write 0 Disabled #0 1 Enabled #1 OFFEN10 Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. 25 1 read-write 0 Disabled #0 1 Enabled #1 OFFEN11 Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. 17 1 read-write 0 Disabled #0 1 Enabled #1 OFFEN20 Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.. 26 1 read-write 0 Disabled #0 1 Enabled #1 OFFEN21 Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. 18 1 read-write 0 Disabled #0 1 Enabled #1 OFFEN30 Setting This Bit Will Force MSKEN3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. 27 1 read-write 0 Disabled #0 1 Enabled #1 OFFEN31 Setting This Bit Will Force MSKEN3to Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. 19 1 read-write 0 Disabled #0 1 Enabled #1 TMR0TEN Enable Timer0 Trigger PWM Function\nWhen this bit is set, timer0 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register. 30 1 read-write 0 Disabled #0 1 Enabled #1 TMR1TEN Enable Timer1 Trigger PWM Function\nWhen this bit is set, timer1 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register. 22 1 read-write 0 Disabled #0 1 Enabled #1 POEN PWM_POEN PWM Output Enable for Channel 0~5 0x5C read-write n 0x0 0x0 POEN0 PWM Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function. 0 1 read-write 0 PWM channel 0 output to pin Disabled #0 1 PWM channel 0 output to pin Enabled #1 POEN1 PWM Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function. 1 1 read-write 0 PWM channel 1 output to pin Disabled #0 1 PWM channel 1 output to pin Enabled #1 POEN2 PWM Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function. 2 1 read-write 0 PWM channel 2 output to pin Disabled #0 1 PWM channel 2 output to pin Enabled #1 POEN3 PWM Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function. 3 1 read-write 0 PWM channel 3 output to pin Disabled #0 1 PWM channel 3 output to pin Enabled #1 POEN4 PWM Channel 4 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function. 4 1 read-write 0 PWM channel 4 output to pin Disabled #0 1 PWM channel 4 output to pin Enabled #1 POEN5 PWM Channel 5 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function. 5 1 read-write 0 PWM channel 5 output to pin Disabled #0 1 PWM channel 5 output to pin Enabled #1 SCS SCS Register Map SCS 0x0 0x10 0xC registers n 0x100 0x4 registers n 0x180 0x4 registers n 0x200 0x4 registers n 0x280 0x4 registers n 0x400 0x20 registers n 0xD00 0x8 registers n 0xD0C 0x8 registers n 0xD1C 0x8 registers n AIRCR AIRCR Application Interrupt and Reset Control Register 0xD0C -1 read-write n 0x0 0x0 SYSRESETREQ System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence. 2 1 read-write VECTCLRACTIVE Exception Active Status Clear Bit\nReserved for debug use. When writing to the register, user must write 0 to this bit, otherwise behavior is unpredictable. 1 1 read-write VECTORKEY Register Access Key\nWrite:\nWhen writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.\nRead:\nRead as 0xFA05. 16 16 read-write CPUID CPUID CPUID Register 0xD00 -1 read-only n 0x0 0x0 IMPLEMENTER Implementer Code 24 8 read-only PART Architecture Of The Processor\nRead as 0xC for ARMv6-M parts. 16 4 read-only PARTNO Part Number Of The Processor\nRead as 0xC20. 4 12 read-only REVISION Revision Number\nRead as 0x0. 0 4 read-only ICSR ICSR Interrupt Control State Register 0xD04 read-write n 0x0 0x0 ISRPENDING Interrupt Pending Flag, Excluding NMI And Faults\nThis bit is read only. 22 1 read-write 0 Interrupt not pending #0 1 Interrupt pending #1 ISRPREEMPT Interrupt Preemption Bit\nIf set, a pending exception will be serviced on exit from the debug halt state.\nThis bit is read only. 23 1 read-write NMIPENDSET NMI Set-Pending Bit\nWrite:\nNote: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 31 1 read-write 0 No effect.\nNMI exception not pending #0 1 Changes NMI exception state to pending.\nNMI exception pending #1 PENDSTCLR SysTick Exception Clear-Pending Bit Write: Note: This bit is write-only. When you want to clear PENDST bit, you must write 0 to PENDSTSET and write 1 to PENDSTCLR at the same time. 25 1 read-write 0 No effect #0 1 Removes the pending state from the SysTick exception #1 PENDSTSET SysTick Exception Set-Pending Bit\nWrite: 26 1 read-write 0 No effect.\nSysTick exception is not pending #0 1 Changes SysTick exception state to pending.\nSysTick exception is pending #1 PENDSVCLR PendSV Clear-Pending Bit Write: Note: This bit is write-only. To clear the PENDSV bit, you must write 0 to PENDSVSET and write 1 to PENDSVCLR at the same time. 27 1 read-write 0 No effect #0 1 Removes the pending state from the PendSV exception #1 PENDSVSET PendSV Set-Pending Bit\nWrite:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending. 28 1 read-write 0 No effect.\nPendSV exception is not pending #0 1 Changes PendSV exception state to pending.\nPendSV exception is pending #1 VECTACTIVE Contains The Active Exception Number\nThis bit is read only. 0 9 read-write 0 Thread mode 0 VECTPENDING Exception Number Of The Highest Priority Pending Enabled Exception\nThis bit is read only. 12 9 read-write 0 No pending exceptions 0 NVIC_ICER NVIC_ICER IRQ0 ~ IRQ31 Clear-Enable Control Register 0x180 read-write n 0x0 0x0 CLRENA Interrupt Disable Register\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite:\nRead value indicates the current enable status. 0 32 read-write 0 No effect.\nAssociated interrupt status is Disabled 0 1 Write 1 to disable associated interrupt.\nAssociated interrupt status is Enabled 1 NVIC_ICPR NVIC_ICPR IRQ0 ~ IRQ31 Clear-Pending Control Register 0x280 read-write n 0x0 0x0 CLRPEND Clear Interrupt Pending Register\nWrite:\nRead value indicates the current pending status. 0 32 read-write 0 No effect.\nAssociated interrupt in not in pending status 0 1 Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status 1 NVIC_IPR0 NVIC_IPR0 IRQ0 ~ IRQ3 Interrupt Priority Control Register 0x400 read-write n 0x0 0x0 PRI_0 Priority Of IRQ0\n0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_1 Priority Of IRQ1\n0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_2 Priority Of IRQ2\n0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_3 Priority Of IRQ3\n0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR1 NVIC_IPR1 IRQ4 ~ IRQ7 Interrupt Priority Control Register 0x404 read-write n 0x0 0x0 PRI_4 Priority Of IRQ4\n0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_5 Priority Of IRQ5\n0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_6 Priority Of IRQ6\n0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_7 Priority Of IRQ7\n0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR2 NVIC_IPR2 IRQ8 ~ IRQ11 Interrupt Priority Control Register 0x408 read-write n 0x0 0x0 PRI_10 Priority Of IRQ10\n0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_11 Priority Of IRQ11\n0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write PRI_8 Priority Of IRQ8\n0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_9 Priority Of IRQ9\n0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write NVIC_IPR3 NVIC_IPR3 IRQ12 ~ IRQ15 Interrupt Priority Control Register 0x40C read-write n 0x0 0x0 PRI_12 Priority Of IRQ12\n0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_13 Priority Of IRQ13\n0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_14 Priority Of IRQ14\n0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_15 Priority Of IRQ15\n0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR4 NVIC_IPR4 IRQ16 ~ IRQ19 Interrupt Priority Control Register 0x410 read-write n 0x0 0x0 PRI_16 Priority Of IRQ16\n0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_17 Priority Of IRQ17\n0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_18 Priority Of IRQ18\n0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_19 Priority Of IRQ19\n0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR5 NVIC_IPR5 IRQ20 ~ IRQ23 Interrupt Priority Control Register 0x414 read-write n 0x0 0x0 PRI_20 Priority Of IRQ20\n0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_21 Priority Of IRQ21\n0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_22 Priority Of IRQ22\n0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_23 Priority Of IRQ23\n0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR6 NVIC_IPR6 IRQ24 ~ IRQ27 Interrupt Priority Control Register 0x418 read-write n 0x0 0x0 PRI_24 Priority Of IRQ24\n0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_25 Priority Of IRQ25\n0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_26 Priority Of IRQ26\n0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_27 Priority Of IRQ27\n0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR7 NVIC_IPR7 IRQ28 ~ IRQ31 Interrupt Priority Control Register 0x41C read-write n 0x0 0x0 PRI_28 Priority Of IRQ28\n0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_29 Priority Of IRQ29\n0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_30 Priority Of IRQ30\n0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_31 Priority Of IRQ31\n0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_ISER NVIC_ISER IRQ0 ~ IRQ31 Set-Enable Control Register 0x100 read-write n 0x0 0x0 SETENA Interrupt Enable Register \nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite:\nRead value indicates the current enable status. 0 32 read-write 0 No effect.\nAssociated interrupt status is Disabled 0 1 Write 1 to enable associated interrupt.\nAssociated interrupt status is Enabled 1 NVIC_ISPR NVIC_ISPR IRQ0 ~ IRQ31 Set-Pending Control Register 0x200 read-write n 0x0 0x0 SETPEND Set Interrupt Pending Register\nWrite:\nRead value indicates the current pending status. 0 32 read-write 0 No effect.\nAssociated interrupt in not in pending status 0 1 Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status 1 SCR SCR System Control Register 0xD10 read-write n 0x0 0x0 SEVONPEND Send Event On Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event. 4 1 read-write 0 Only enabled interrupts or events can wake up the processor, disabled interrupts are excluded #0 1 Enabled events and all interrupts, including disabled interrupts, can wake-up the processor #1 SLEEPDEEP Processor Deep Sleep And Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode: 2 1 read-write 0 Sleep mode #0 1 Deep Sleep mode #1 SLEEPONEXIT Sleep-On-Exit Enable\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 1 1 read-write 0 Do not sleep when returning to Thread mode #0 1 Enter Sleep, or Deep Sleep, on return from ISR to Thread mode #1 SHPR2 SHPR2 System Handler Priority Register 2 0xD1C read-write n 0x0 0x0 PRI_11 Priority Of System Handler 11 - SVCall\n0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write SHPR3 SHPR3 System Handler Priority Register 3 0xD20 read-write n 0x0 0x0 PRI_14 Priority Of System Handler 14 - PendSV\n0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_15 Priority Of System Handler 15 - SysTick\n0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write SYST_CSR SYST_CSR SysTick Control and Status Register 0x10 read-write n 0x0 0x0 CLKSRC System Tick Clock Source Selection 2 1 read-write 0 Clock source is optional, refer to STCLK_S #0 1 Core clock used for SysTick timer #1 COUNTFLAG System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register. 16 1 read-write ENABLE System Tick Counter Enabled 0 1 read-write 0 Counter Disabled #0 1 Counter Enabled and will operate in a multi-shot manner #1 TICKINT System Tick Interrupt Enabled 1 1 read-write 0 Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to 0 has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended #1 SYST_CVR SYST_CVR SysTick Current Value Register 0x18 read-write n 0x0 0x0 CURRENT System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value Register). 0 24 read-write SYST_RVR SYST_RVR SysTick Reload Value Register 0x14 read-write n 0x0 0x0 RELOAD System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0. 0 24 read-write SPI SPI Register Map SPI 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x3C 0xC registers n CLKDIV SPI_CLKDIV SPI Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider Register (Master Only)\nThe value in this field is the frequency divider to determine the SPI peripheral clock frequency fspi, and the SPI master's bus clock frequency on the SPICLK output pin. The frequency is obtained according to the following equation:\nIf the bit of DIVMOD, SPI_SLVCTL[31], is set to 0.\n\nelse if DIVMOD is set to 1,\n\nwhere \n is the SPI peripheral clock source which is defined in the CLKSEL1 register. 0 8 read-write CTL SPI_CTL SPI Control and Status Register 0x0 -1 read-write n 0x0 0x0 CLKPOL Clock Polarity 11 1 read-write 0 SPICLK idle low #0 1 SPICLK idle high #1 DWIDTH Transmit Bit Length\nThis field specifies how many bits are transmitted in one transmit/receive. The minimum bit length is 8 bits and can up to 32 bits. 3 5 read-write FIFOEN FIFO Mode Enable Control Note 1: Before enabling FIFO mode, the other related settings should be set in advance. Note 2: In Master mode, if the FIFO mode is enabled, the SPIEN bit will be set to 1 automatically after writing data into the 4-depth transmit FIFO. When all data stored at transmit FIFO buffer are transferred, the SPIEN bit will back to 0. 21 1 read-write 0 FIFO Mode Disabled #0 1 FIFO Mode Enabled #1 LSB LSB First 10 1 read-write 0 The MSB is transmitted/received first #0 1 The LSB is transmitted/received first #1 REORDER Byte Reorder Function\nNote: This setting is only available if DWIDTH is defined as 16, 24, and 32 bits. 19 1 read-write 0 Byte reorder function Disabled #0 1 Byte reorder function Enabled #1 RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CTL[24]. 24 1 read-only 0 The receive FIFO buffer is not empty #0 1 The receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[25] 25 1 read-only 0 The receive FIFO buffer is not full #0 1 The receive FIFO buffer is full #1 RXNEG Receive On Negative Edge 1 1 read-write 0 The received data input signal latched on the Rising edge of SPICLK #0 1 The received data input signal latched on the Falling edge of SPICLK #1 SLAVE Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SPIEN SPI Transfer Control Bit And Busy Status\nIf FIFO mode is enabled, this bit will be controlled by hardware and its Read only.\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote 1: When FIFO mode is disabled, all configurations should be ready before writing 1 to the SPIEN bit.\nNote 2: In SPI Slave mode, if FIFO mode is disabled and the SPI bus clock is kept at idle state during a data transfer, the SPIEN bit will not be cleared to 0 when slave select signal goes to inactive state. 0 1 read-write 0 Writing 0 to this bit to stop data transfer if SPI is transferring #0 1 In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master #1 SUSPITV Suspend Interval (Master Only) The four bits provide configurable suspend interval between two successive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation: (SUSPITV + 0.5) * period of SPICLK clock cycle Example: 12 4 read-write TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STAUTS[26]. 26 1 read-only 0 The transmit FIFO buffer is not empty #0 1 The transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[27]. 27 1 read-only 0 The transmit FIFO buffer is not full #0 1 The transmit FIFO buffer is full #1 TXNEG Transmit On Negative Edge 2 1 read-write 0 The transmitted data output signal is driven on the Rising edge of SPICLK #0 1 The transmitted data output signal is driven on the Falling edge of SPICLK #1 UNITIEN Unit-Transfer Interrupt Enable Control 17 1 read-write 0 SPI unit-transfer interrupt Disabled #0 1 SPI unit-transfer interrupt Enabled #1 UNITIF Unit-Transfer Interrupt Flag\nNote 1: This bit will be cleared by writing 1 to itself.\nNote 2: . It's a mutual mirror bit of SPI_STATUS[16]. 16 1 read-write 0 The transfer does not finish yet #0 1 The SPI controller has finished one unit transfer #1 FIFOCTL SPI_FIFOCTL SPI FIFO Control Register 0x40 -1 read-write n 0x0 0x0 RXOVIEN Receive FIFO Overrun Interrupt Enable Control 6 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RXRST Clear Receive FIFO Buffer\nNote: This bit will be cleared to 0 by hardware after software sets it to 1 and the receive FIFO is cleared. 0 1 read-write 0 No effect #0 1 Clear receive FIFO buffer #1 RXTH Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. 24 2 read-write RXTHIEN Receive Threshold Interrupt Enable Control 2 1 read-write 0 Receive threshold interrupt Disabled #0 1 Receive threshold interrupt Enabled #1 RXTOIEN Receive FIFO Time-Out Interrupt Enable Control 21 1 read-write 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 TXRST Clear Transmit FIFO Buffer\nNote: This bit will be cleared to 0 by hardware after software sets it to 1 and the transmit FIFO is cleared. 1 1 read-write 0 No effect #0 1 Clear transmit FIFO buffer #1 TXTH Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. 28 2 read-write TXTHIEN Transmit Threshold Interrupt Enable 3 1 read-write 0 Transmit threshold interrupt Disabled #0 1 Transmit threshold interrupt Enabled #1 RX SPI_RX SPI Data Receive Register 0x10 read-only n 0x0 0x0 RX Data Receive Register (Read Only)\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CTL register.\nFor example, if DWIDTH is set to 0x08, bit RX0[7:0] holds the received data. The values of the other bits are unknown. The Data Receive Registers are read-only registers. 0 32 read-only SLVCTL SPI_SLVCTL SPI Slave Mode Control Register 0x3C read-write n 0x0 0x0 DIVMOD Clock Configuration Backward Compatible Option\nNote: Refer to the description of SPI_CLKDIV register for details. 31 1 read-write 0 The clock configuration is backward compatible #0 1 The clock configuration is not backward compatible #1 SLV3WIRE Slave 3-Wire Mode Enable Bit (Slave Only)\nThe SPI controller work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SSLTEN bit (SPI_SSCTL[4]) shall be set as 1. 8 1 read-write 0 The controller is 4-wire bi-direction interface #0 1 The controller is 3-wire bi-direction interface in Slave mode. The controller will be ready to transmit/receive data after the SPIEN bit is set to 1 #1 SLVABT Slave 3-Wire Mode Abort Control Bit (Slave Only)\nIn normal operation, there is an interrupt event when the number of received bits meets the requirement which defined in DWIDTH.\nIf the number of received bits is less than the requirement and there is no more bus clock input over one transfer time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a unit transfer interrupt event.\nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software. 9 1 read-write 0 No force the transfer done when the SLV3WIRE bit is set to 1 #0 1 Force the transfer done when the SLV3WIRE bit is set to 1 #1 SLVSTIEN Slave 3-Wire Mode Start Interrupt Enable (Slave Only)\nIt is used to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, user can set the SLV3WIRE bit to force the transfer done.\nNote 1: It will be cleared to 0 as the current transfer is done or the SLVSTIF bit is cleared to 0. 10 1 read-write 0 Transaction start interrupt Disabled #0 1 Transaction start interrupt Enabled #1 SLVSTIF Slave 3-Wire Mode Start Interrupt Status (Slave Only) This bit dedicates if a transaction has started in Slave 3-wire mode. Note 1: It will be cleared automatically when a transaction is done or by writing 1 to this bit. Note 2: It is a mutual mirror bit of SPI_STATUS[11]. 11 1 read-write 0 Slave does not detect any SPI bus clock transfer since the SLVSTIEN bit was set to 1 #0 1 The transfer has started in Slave 3-wire mode #1 SSINAIEN Slave Select Inactive Interrupt Option (Slave Only)\nNote: This setting is only available if the SPI controller is configured as level trigger in slave device. 16 1 read-write 0 As the slave select signal goes to inactive level, the UNITIF bit will NOT be set to 1 #0 1 As the slave select signal goes to inactive level, the UNITIF bit will be set to 1 #1 SSCTL SPI_SSCTL SPI Slave Select Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit (Master Only) 3 1 read-write 0 SPISS pin signal will be asserted/de-asserted by setting /clearing SS bit #0 1 SPISS pin signal will be generated automatically, which means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting SPIEN, and will be de-asserted after each transmit/receive is finished #1 LTF Level Trigger Flag (Read Only, Slave Only)\nWhen the SSLTEN bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not. 5 1 read-only 0 The transaction number or the transferred bit length of one transaction does not meet the specified requirements #0 1 The transaction number and the transferred bit length met the specified requirements which defined in DWIDTH #1 SS Slave Select Control Bits (Master Only)\nIf AUTOSS bit is 0, 0 1 read-write 0 Set the SPISS line to inactive state.\nKeep the SPISS line at inactive state #0 1 Set the proper SPISS line to active state.\nSelect the SPISS line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time. The active state of SPISS is specified in SSACTPOL bit #1 SSACTPOL Slave Select Active Level (Slave Only)\nIt defines the active status of slave select signal (SPISS).\nIf SSLTEN bit is 1: 2 1 read-write 0 The slave select signal SPISS is active at low-level.\nThe slave select signal SPISS is active at Falling-edge #0 1 The slave select signal SPISS is active at high-level.\nThe slave select signal SPISS is active at Rising-edge #1 SSLTEN Slave Select Level Trigger Enable Bit (Slave Only) 4 1 read-write 0 The input slave select signal is edge-trigger #0 1 The input slave select signal is level-trigger #1 STATUS SPI_STATUS SPI Status Register 0x44 -1 read-write n 0x0 0x0 RXCNT Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer. 12 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CTL[24]. 24 1 read-only 0 The receive FIFO buffer is not empty #0 1 The receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) \nNote: It's a mutual mirror bit of SPI_CTL[25]. 25 1 read-only 0 The receive FIFO buffer is not full #0 1 The receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. 2 1 read-write 0 No overrun in receive FIFO #0 1 Overrun in receive FIFO #1 RXTHIF Receive FIFO Threshold Interrupt Status (Read Only) 0 1 read-only 0 The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 SLVSTIF Slave Start Interrupt Status (Slave Only)\nIt is used to dedicate that the transfer has started in slave 3-wire mode. \nNote 1: It will be cleared as transfer done or by writing one to this bit.\nNote 2: It's a mutual mirror bit of SPI_SLVCTL[11]. 11 1 read-write 0 Slave does not detect any SPI bus clock transfer since the SSTA_INTEN bit was set to 1 #0 1 The transfer has started in Slave 3-wire mode #1 SLVTOIF Time-Out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 20 1 read-write 0 No receive FIFO time-out event #0 1 The receive FIFO buffer is not empty and it does not be read over 64 SPI clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 TXCNT Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer. 28 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) \nNote: It's a mutual mirror bit of SPI_CTL[26]. 26 1 read-only 0 The transmit FIFO buffer is not empty #0 1 The transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CTL[27]. 27 1 read-only 0 The transmit FIFO buffer is not full #0 1 The transmit FIFO buffer is full #1 TXTHIF Transmit FIFO Threshold Interrupt Status (Read Only) 4 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 UNITIF SPI Unit-Transfer Interrupt Flag\nNote 1: This bit will be cleared by writing 1 to itself.\nNote 2: It's a mutual mirror bit of SPI_CTL[16]. 16 1 read-write 0 The transfer does not finish yet #0 1 The SPI controller has finished one unit transfer #1 TX SPI_TX SPI Data Transmit Register 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register.\nFor example, if DWIDTH is set to 0x08, the bit TX0[7:0] will be transmitted in next transfer. 0 32 write-only SYS SYS Register Map SYS 0x0 0x0 0x10 registers n 0x100 0x4 registers n 0x18 0x4 registers n 0x30 0x1C registers n 0x80 0xC registers n BODCTL SYS_BODCTL Brown-out Detector Control Register 0x18 read-write n 0x0 0x0 BODIF Brown-Out Detector Interrupt Flag 4 1 read-write 0 Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting #0 1 When Brown-out Detector detects the VDD is dropped through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled #1 BODLPM Brown-Out Detector Low Power Mode (Write-Protected)\nThe BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. 5 1 read-write 0 BOD operate in normal mode (default) #0 1 Enable the BOD low power mode #1 BODOUT Brown-Out Detector Output State 6 1 read-write 0 Brown-out Detector status output is 0, the detected voltage is higher than BODVL setting #0 1 Brown-out Detector status output is 1, the detected voltage is lower than BODVL setting #1 BODRSTEN Brown-Out Reset Enable (Initiated And Write-Protected Bit)\nThe default value is set by flash controller user configuration register config0 bit[20].\nWhen the BOREN is enabled and the interrupt is asserted, the interrupt will be kept till the BOREN is set to 0. The interrupt for CPU can be blocked by disabling the NVIC in CPU for BOD interrupt or disable the interrupt source by disabling the BOREN and then re-enabling the BOREN function if the BOD function is required. 3 1 read-write 0 Brown-out INTERRUPT function Enabled when the Brown-out Detector function is enable and the detected voltage is lower than the threshold, then assert a signal to interrupt the Cortex-M0 CPU #0 1 Brown-out RESET function Enabled when the Brown-out Detector function is enable and the detected voltage is lower than the threshold then assert a signal to reset the chip #1 BODVL1_0 Brown-Out Detector Threshold Voltage Selection (Initiated Write-Protected Bit) 1 2 read-write BODVL2 Brown-Out Detector Threshold Voltage Selection (Initiated Write-Protected Bit) The default value is set by flash controller user configuration register config0 bit[19]. 7 1 read-write BODVL_EXT Brown-Out Detector Selection Extension (Initiated Write-Protected Bit) 0 1 read-write 0 Brown-out detector threshold voltage is selected by the table defined in BODVL[1:0] #0 1 Brown-out detector threshold voltage is selected by BODVL[2:0] defined as below #1 BOREN Brown-Out Reset Enable\nThe bit will enable BOR reset function. When VDD5V lower than 1.7v BOR will reset whole chip.\n0: Disable\n1: Enable 8 1 read-write EINT0SEL SYS_EINT0SEL PIN selection 0x48 read-write n 0x0 0x0 SEL INT0 SEL GPB3 0 1 read-write 0 INT0 source is P3.2 #0 1 INT0 source is P1.3 #1 IPRST0 SYS_IPRST0 Peripheral Reset Control Resister 1 0x8 read-write n 0x0 0x0 CHIPRST CHIP One-Shot Reset (Write Protect)\nSetting this bit will reset the CHIP, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is the same as the POR reset, and all the chip module is reset and the chip settings from flash are also reload.\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGLCTL at address SYS_BA + 0x100. 0 1 read-write 0 Chip normal operation #0 1 CHIP one-shot reset #1 CPURST CPU Kernel One Shot Reset\nSetting this bit will reset the CPU kernel, and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGLCTL at address SYS_BA + 0x100. 1 1 read-write 0 Normal #0 1 Reset CPU #1 CPUWS CPU Wait-State Control For Flash Memory Access\n0: Insert one wait-state when access Flash\n1: Non-insert wait-state when access Flash\nNote: When HCLK frequency is faster than 44MHz, insert one wait state is necessary. 2 1 read-write IPRST1 SYS_IPRST1 Peripheral Reset Control Resister 2 0xC read-write n 0x0 0x0 ACMPRST ACMP Controller Reset 22 1 read-write 0 ACMP block normal operation #0 1 ACMP block reset #1 ADCRST ADC Controller Reset 28 1 read-write 0 ADC block normal operation #0 1 ADC block reset #1 GPIORST GPIO (P0~P5) Controller Reset 1 1 read-write 0 GPIO normal operation #0 1 GPIO reset #1 I2C_RST I2C Controller Reset 8 1 read-write 0 I2C normal operation #0 1 I2C block reset #1 PWMRST PWM Controller Reset 20 1 read-write 0 PWM block normal operation #0 1 PWM block reset #1 SPIRST SPI Controller Reset 12 1 read-write 0 SPI block normal operation #0 1 SPI block reset #1 TMR0RST Timer0 Controller Reset 2 1 read-write 0 Timer0 normal operation #0 1 Timer0 block reset #1 TMR1RST Timer1 Controller Reset 3 1 read-write 0 Timer1 normal operation #0 1 Timer1 block reset #1 UART0RST UART0 Controller Reset 16 1 read-write 0 UART0 normal operation #0 1 UART0 block reset #1 UART1RST UART1 Controller Reset 17 1 read-write 0 UART1 normal operation #0 1 UART1 block reset #1 IRCTCTL SYS_IRCTCTL HFIRC Trim Control Register 0x80 read-write n 0x0 0x0 FREQSEL Trim Frequency Selection\nThis bit is to enable the HFIRC auto trim.\nWhen setting this bit to 1, the HFIRC auto trim function will trim HFIRC to 22.1184 MHz automatically based on the LXT reference clock.\nDuring auto trim operation, if LXT clock error is detected or trim retry limitation count reached, this field will be cleared to 0 automatically. 0 1 read-write 0 HFIRC auto trim function Disabled #0 1 HFIRC auto trim function Enabled and HFIRC trimmed to 22.1184 MHz #1 LOOPSEL Trim Calculation Loop This field defines trim value calculation based on the number of LXT clock. For example, if LOOPSEL is set as 00 , auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT clock. This field also defines how many times the auto trim circuit will try to update the HFIRC trim value before the frequency of HFIRC is locked. Once the HFIRC is locked, the internal trim value update counter will be reset. If the trim value update counter reaches this limitation value and frequency of HFIRC is still not locked, the auto trim operation will be disabled and FREQSEL will be cleared to 0. 4 2 read-write 0 Trim value calculation is based on average difference in 4 LXT clock and trim retry count limitation is 64 #00 1 Trim value calculation is based on average difference in 8 LXT clock and trim retry count limitation is 128 #01 2 Trim value calculation is based on average difference in 16 LXT clock and trim retry count limitation is 256 #10 3 Trim value calculation is based on average difference in 32 LXT clock and trim retry count limitation is 512 #11 IRCTIEN SYS_IRCTIEN HFIRC Trim Interrupt Enable Register 0x84 read-write n 0x0 0x0 CLKEIEN LXT Clock Error Interrupt Enable\nThis bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation.\nIf this bit is high, and CLKERRIF is set during auto trim operation, an interrupt will be triggered to notify the LXT clock frequency is inaccurate. 2 1 read-write 0 CLKERRIF status Disabled to trigger an interrupt to CPU #0 1 CLKERRIF status Enabled to trigger an interrupt to CPU #1 TFAILIEN Trim Failure Interrupt Enable\nThis bit controls if an interrupt will be triggered while HFIRC trim value update limitation count is reached and HFIRC frequency is still not locked on target frequency set by FREQSEL.\nIf this bit is high and TFAILIF is set during auto trim operation, an interrupt will be triggered to notify that HFIRC trim value update limitation count is reached. 1 1 read-write 0 TFAILIF status Disabled to trigger an interrupt to CPU #0 1 TFAILIF status Enabled to trigger an interrupt to CPU #1 IRCTISTS SYS_IRCTISTS HFIRC Trim Interrupt Status Register 0x88 read-write n 0x0 0x0 CLKERRIF LXT Clock Error Interrupt Status\nThis bit indicates that LXT clock frequency is inaccuracy. Once this bit is set, the auto trim operation stopped and FREQSEL will be cleared to 0 by hardware automatically.\nIf this bit is set and CLKEIEN is high, an interrupt will be triggered to notify the LXT clock frequency is inaccuracy. Software can write 1 to clear this bit to zero. 2 1 read-write 0 LXT clock frequency is accuracy #0 1 LXT clock frequency is inaccuracy #1 FREQLOCK HFIRC Frequency Lock Status\nThis bit indicates the HFIRC frequency locked in 22.1184 MHz.\nThis is a read only status bit and doesn't trigger any interrupt. 0 1 read-write TFAILIF Trim Failure Interrupt Status\nThis bit indicates that HFIRC trim value update limitation count reached and HFIRC clock frequency still doesn't lock. Once this bit is set, the auto trim operation stopped and FREQSEL will be cleared to 0 by hardware automatically.\nIf this bit is set and TFAILIEN is high, an interrupt will be triggered to notify that HFIRC trim value update limitation count was reached. Software can write 1 to clear this bit to zero. 1 1 read-write 0 Trim value update limitation count is not reached #0 1 Trim value update limitation count is reached and HFIRC frequency is still not locked #1 P0_MFP SYS_P0_MFP P0 Multiple Function and Input Type Control Register 0x30 read-write n 0x0 0x0 ALT0 P0.0 Alternate Function Selection 8 1 read-write ALT1 P0.1 Alternate Function Selection 9 1 read-write ALT4 P0.4 Alternate Function Selection 12 1 read-write ALT5 P0.5 Alternate Function Selection 13 1 read-write ALT6 P0.6 Alternate Function Selection 14 1 read-write ALT7 P0.7 Alternate Function Selection 15 1 read-write HS P0[7:0] Slew Rate Control 24 8 read-write 0 P0[7:0] Low slew rate output, 16MHz available 0 1 P0[7:0] High slew rate output, 24MHz available 1 MFP P0 Multiple Function Selection\nThe pin function of P0 depends on P0_MFP and ALT.\nRefer to ALT Description for details. 0 8 read-write TYPE P0[7:0] Input Schmitt Trigger Function Enable 16 8 read-write 0 P0[7:0] I/O input Schmitt Trigger function Disabled 0 1 P0[7:0] I/O input Schmitt Trigger function Enabled 1 P1_MFP SYS_P1_MFP P1 Multiple Function and Input Type Control Register 0x34 read-write n 0x0 0x0 ALT0 P1.0 Alternate Function Selection 8 1 read-write ALT2 P1.2 Alternate Function Selection 10 1 read-write ALT3 P1.3 Alternate Function Selection 11 1 read-write ALT4 P1.4 Alternate Function Selection 12 1 read-write ALT5 P1.5 Alternate Function Selection 13 1 read-write ALT6 P1.6 Alternate Function Selection 14 1 read-write HS P1[7:0] Slew Rate Control 24 8 read-write 0 P1[7:0] Low slew rate output, 16MHz available 0 1 P1[7:0] High slew rate output, 24MHz available 1 MFP P1 Multiple Function Selection\nThe pin function of P1 depends on MFP and ALT.\nRefer to P1_ALT Description for details. 0 8 read-write TYPE P1[7:0] Input Schmitt Trigger Function Enable 16 8 read-write 0 P1[7:0] I/O input Schmitt Trigger function Disabled 0 1 P1[7:0] I/O input Schmitt Trigger function Enabled 1 P2_MFP SYS_P2_MFP P2 Multiple Function and Input Type Control Register 0x38 read-write n 0x0 0x0 ALT2 P2.2 Alternate Function Selection 10 1 read-write ALT3 P2.3 Alternate Function Selection 11 1 read-write ALT4 P2.4 Alternate Function Selection 12 1 read-write ALT5 P2.5 Alternate Function Selection 13 1 read-write ALT6 P2.6 Alternate Function Selection 14 1 read-write ALT7 P2.7 Alternate Function Selection 15 1 read-write HS P2[7:0] Slew Rate Control 24 8 read-write 0 P2[7:0] Low slew rate output, 16MHz available 0 1 P2[7:0] High slew rate output, 24MHz available 1 MFP P2 Multiple Function Selection\nThe pin function of P2 depends on P2_MFP and ALT.\nRefer to ALT Description for details. 0 8 read-write TYPE P2[7:0] Input Schmitt Trigger Function Enable 16 8 read-write 0 P2[7:0] I/O input Schmitt Trigger function Disabled 0 1 P2[7:0] I/O input Schmitt Trigger function Enabled 1 P3_MFP SYS_P3_MFP P3 Multiple Function and Input Type Control Register 0x3C read-write n 0x0 0x0 ALT0 P3.0 Alternate Function Selection 8 1 read-write ALT1 P3.1 Alternate Function Selection 9 1 read-write ALT2 P3.2 Alternate Function Selection 10 1 read-write ALT4 P3.4 Alternate Function Selection 12 1 read-write ALT5 P3.5 Alternate Function Selection 13 1 read-write ALT6 P3.6 Alternate Function Selection 14 1 read-write ALT7 P3.7 Alternate Function Selection 15 1 read-write HS P3[6:0] Slew Rate Control 25 7 read-write 0 P3[6:0] Low slew rate output, 16MHz available 0 1 P3[6:0] High slew rate output, 24MHz available 1 MFP P3 Multiple Function Selection\nThe pin function of P3 depends on MFP and ALT.\nRefer to ALT Description for details. 0 8 read-write P32CTL P3.2 Alternate Function Selection Extension 24 1 read-write 0 P3.2 is set by ALT[2] and MFP[2] #0 1 P3.2 is set to CPP1 of ACMP1 #1 TYPE P3[7:0] Input Schmitt Trigger Function Enable 16 8 read-write 0 P3[7:0] I/O input Schmitt Trigger function Disabled 0 1 P3[7:0] I/O input Schmitt Trigger function Enabled 1 P4_MFP SYS_P4_MFP P4 Multiple Function and Input Type Control Register 0x40 -1 read-write n 0x0 0x0 ALT6 P4.6 Alternate Function Selection 14 1 read-write ALT7 P4.7 Alternate Function Selection 15 1 read-write HS P4[7:0] Slew Rate Control 24 8 read-write 0 P4[7:0] Low slew rate output, 16MHz available 0 1 P4[7:0] High slew rate output, 24MHz available 1 MFP P4 Multiple Function Selection\nThe pin function of P4 depends on MFP and P4_ALT.\nRefer to ALT Description for details. 0 8 read-write TYPE P4[7:0] Input Schmitt Trigger Function Enable 16 8 read-write 0 P4[7:0] I/O input Schmitt Trigger function Disabled 0 1 P4[7:0] I/O input Schmitt Trigger function Enabled 1 P5_MFP SYS_P5_MFP P5 Multiple Function and Input Type Control Register 0x44 read-write n 0x0 0x0 ALT0 P5.0 Alternate Function Selection 8 1 read-write ALT1 P5.1 Alternate Function Selection 9 1 read-write ALT2 P5.2 Alternate Function Selection 10 1 read-write ALT3 P5.3 Alternate Function Selection 11 1 read-write ALT4 P5.4 Alternate Function Selection 12 1 read-write ALT5 P5.5 Alternate Function Selection 13 1 read-write HS P5[7:0] Slew Rate Control 24 8 read-write 0 P5[7:0] Low slew rate output, 16MHz available 0 1 P5[7:0] High slew rate output, 24MHz available 1 MFP P5 Multiple Function Selection\nThe pin function of P5 depends on MFP and ALT.\nRefer to ALT Description for details. 0 8 read-write TYPE P5[7:0] Input Schmitt Trigger Function Enable 16 8 read-write 0 P5[7:0] I/O input Schmitt Trigger function Disabled 0 1 P5[7:0] I/O input Schmitt Trigger function Enabled 1 PDID SYS_PDID Part Device Identification Number Register 0x0 read-only n 0x0 0x0 PDID Product Device Identification Number\nThis register reflects the device part number code. Software can read this register to identify which device is used. 0 32 read-only REGLCTL SYS_REGLCTL Register Write-Protection Control Register 0x100 read-write n 0x0 0x0 REGPROTDIS Register Write-Protection Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field. After this sequence is completed, the REGWRPROT bit will be set to 1 and write-protection registers can be normal write. 0 8 write-only REGWRPROT Register Write-Protection Disable Index (Read Only) 0 1 read-only 0 Write-protection Enabled for writing protected registers. Any write to the protected register is ignored #0 1 Write-protection Disabled for writing protected registers #1 RSTSTS SYS_RSTSTS System Reset Source Register 0x4 read-write n 0x0 0x0 BODRF Brown-Out Detector Reset Flag The BODRF flag is set by the reset signal from the Brown-out Detector to indicate the previous reset source. Note: Software can write 1 to clear this bit to zero. 4 1 read-write 0 No reset from BOD #0 1 The BOD had issued the reset signal to reset the system #1 CPURF CPU Reset Flag\nThe CPURF flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC).\nNote: Software can write 1 to clear this bit to zero. 7 1 read-write 0 No reset from CPU #0 1 Cortex-M0 core and FMC are reset by software setting CPURST to 1 #1 PINRF Reset Pin Reset Flag The PINRF flag is set by the reset signal from the /RESET pin to indicate the previous reset source. Note: Software can write 1 to clear this bit to zero. 1 1 read-write 0 No reset from pin /RESET pin #0 1 The /RESET pin had issued the reset signal to reset the system #1 PORF Power-On Reset Flag The PORF flag is set by the reset signal , which is from the Power-On Reset (POR) controller or bit CHIPRST (SYS_IPRST0[0]), to indicate the previous reset source. Note: Software can write 1 to clear this bit to zero. 0 1 read-write 0 No reset from POR or CHIPRST #0 1 The Power-on-Reset (POR) or CHIPRST had issued the reset signal to reset the system #1 SYSRF MCU Reset Flag The SYSRF flag is set by the reset signal from the Cortex-M0 core to indicate the previous reset source. Note: Software can write 1 to clear this bit to zero. 5 1 read-write 0 No reset from Cortex-M0 #0 1 The Cortex-M0 had issued the reset signal to reset the system by writing 1 to bit SYSRESETREQ (AIRCR[2]), Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core #1 WDTRF Watchdog Reset Flag The RSTS_WDT flag is set by the reset signal from the Watchdog timer to indicate the previous reset source. Note: Software can write 1 to clear this bit to zero. 2 1 read-write 0 No reset from Watchdog timer #0 1 The Watchdog timer had issued the reset signal to reset the system #1 TMR TMR Register Map TMR 0x0 0x0 0x1C registers n 0x20 0x1C registers n 0x40 0x10 registers n TIMER0_CAP TIMER0_CAP Timer0 Capture Data Register 0x10 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register\nWhen CAPIF flag is set to 1, the current CNT (TIMERx_CNT[23:0]) value will be auto-loaded into this TCAP filed immediately. 0 24 read-only TIMER0_CMP TIMER0_CMP Timer0 Compare Register 0x4 read-write n 0x0 0x0 CMPDAT Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When Timer is operating at Continuous Counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into CMPDAT field. But if Timer is operating at other modes except Periodic mode on M05xxDN/DE, the 24-bit up counter will restart counting and using newest CMPDAT value to be the timer compared value if software writes a new value into CMPDAT field. 0 24 read-write TIMER0_CNT TIMER0_CNT Timer0 Data Register 0xC read-only n 0x0 0x0 CNT Timer Data Register\nIf CNTDATEN is set to 1, CNT register value will be updated continuously to monitor 24-bit up counter value. 0 24 read-only TIMER0_CTL TIMER0_CTL Timer0 Control and Status Register 0x0 -1 read-write n 0x0 0x0 ACTSTS Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status. 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CAPPINSEL Capture Pin Source Selection 19 1 read-write 0 Capture Function source is from TxEX pin #0 1 Capture Function source is from ACMPx output signal #1 CMPCTL TIMERx_CMP Mode Control 17 1 read-write 0 In One-shot or Periodic mode, when write new CMPDAT, timer counter will reset #0 1 In One-shot or Periodic mode, when write new CMPDAT if new CMPDAT CNT (TIMERx_CNT[23:0])(current counter) , timer counter keep counting and will not reset. If new CMPDAT = CNT(current counter) , timer counter will reset #1 CNTDATEN Data Load Enable Control\nWhen CNTDATEN is set, CNT (TIMERx_CNT[23:0]) (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting. 16 1 read-write 0 Timer Data Register update Disabled #0 1 Timer Data Register update Enabled while Timer counter is active #1 CNTEN Timer Enable Control 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 EXTCNTEN Counter Mode Enable Control\nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 6.12.5.3 for detail description. 24 1 read-write 0 External event counter mode Disabled #0 1 External event counter mode Enabled #1 ICEDEBUG ICE Debug Mode Acknowledge Disable (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN Interrupt Enable Control\nIf this bit is enabled, when the timer interrupt flag (TIF) is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer Interrupt function Disabled #0 1 Timer Interrupt function Enabled #1 OPMODE Timer Operating Mode 27 2 read-write 0 The timer is operating in the One-shot OPMODE. The associated interrupt signal is generated once (if INTEN is enabled) and CNTEN is automatically cleared by hardware #00 1 The timer is operating in Periodic OPMODE. The associated interrupt signal is generated periodically (if INTEN is enabled) #01 2 The timer is operating in Toggle OPMODE. The interrupt signal is generated periodically (if INTEN is enabled). The associated signal (tout) is changing back and forth with 50% duty cycle #10 3 The timer is operating in Continuous Counting mode. The associated interrupt signal is generated when TIMERx_CNT = TIMERx_CMP (if INTEN is enabled). However, the 24-bit up-timer counts continuously. Please refer to 6.12.5.2 for detailed description about Continuous Counting mode operation #11 PSC Prescale Counter 0 8 read-write RSTCNT Timer Reset 26 1 read-write 0 No effect #0 1 Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit if ACTSTS is 1 #1 TGLPINSEL Toggle Out Pin Selection\nWhen Timer is set to toggle mode, 18 1 read-write 0 Time0/1 toggle output pin is T0/T1 pin #0 1 Time0/1 toggle output pin is T0EX/T1EX pin #1 WKEN Wake-Up Enable\nWhen WKEN is set and the TIF or CAPIF is set, the timer controller will generator a wake-up trigger event to CPU. 23 1 read-write 0 Wake-up trigger event Disabled #0 1 Wake-up trigger event Enabled #1 TIMER0_EINTSTS TIMER0_EINTSTS Timer0 External Interrupt Status Register 0x18 read-write n 0x0 0x0 CAPIF Timer External Interrupt Flag\nThis bit indicates the external capture interrupt flag status\nNote: This bit is cleared by writing 1 to it 0 1 read-write 0 TxEX (x = 0~1) pin interrupt did not occur #0 1 TxEX (x = 0~1) pin interrupt occurred #1 TIMER0_EXTCTL TIMER0_EXTCTL Timer0 External Control Register 0x14 read-write n 0x0 0x0 CAPDBEN Timer External Capture Input Pin De-Bounce Enable Control 6 1 read-write 0 TxEX (x = 0~1) pin de-bounce Disabled #0 1 TxEX (x = 0~1) pin de-bounce Enabled #1 CAPEDGE Timer External Pin Edge Detection 1 2 read-write 0 A 1 to 0 transition on TxEX (x = 0~1) will be detected #00 1 A 0 to 1 transition on TxEX (x = 0~1) will be detected #01 2 Either 1 to 0 or 0 to 1 transition on TxEX (x = 0~1) will be detected #10 3 Reserved #11 CAPEN Timer External Pin Function Enable 3 1 read-write 0 CAPFUNCS function of TxEX (x = 0~1) pin will be ignored #0 1 CAPFUNCS function of TxEX (x = 0~1) pin is active #1 CAPFUNCS Timer External Reset Counter / Timer External Capture Mode Selection 4 1 read-write 0 Transition on TxEX (x = 0~1) pin is using to save the CNT (TIMERx_CNT[23:0]) value into TCAP value if CAPIF flag is set to 1 #0 1 Transition on TxEX (x = 0~1) pin is using to reset the 24-bit up counter #1 CAPIEN Timer External Capture Interrupt Enable Control\nIf CAPIEN enabled, Timer will raise an external capture interrupt signal and inform to CPU while CAPIF flag is set to 1. 5 1 read-write 0 TxEX (x = 0~1) pin detection Interrupt Disabled #0 1 TxEX (x = 0~1) pin detection Interrupt Enabled #1 CAPMODE Capture Mode Selection 8 1 read-write 0 Timer counter reset function or free-counting mode of timer capture function #0 1 Trigger-counting mode of timer capture function #1 CNTPHASE Timer External Count Pin Phase Detect Selection 0 1 read-write 0 A falling edge of Tx (x = 0~1) pin will be counted #0 1 A rising edge of Tx (x = 0~1) pin will be counted #1 ECNTDBEN Timer External Counter Input Pin De-Bounce Enable Control 7 1 read-write 0 Tx (x = 0~1) pin de-bounce Disabled #0 1 Tx (x = 0~1) pin de-bounce Enabled #1 TIMER0_INTSTS TIMER0_INTSTS Timer0 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT value matches the CMPDAT value #1 TWKF Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Time.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated #1 TIMER1_CAP TIMER1_CAP Timer1 Capture Data Register 0x30 read-write n 0x0 0x0 TIMER1_CMP TIMER1_CMP Timer1 Compare Register 0x24 read-write n 0x0 0x0 TIMER1_CNT TIMER1_CNT Timer1 Data Register 0x2C read-write n 0x0 0x0 TIMER1_CTL TIMER1_CTL Timer1 Control and Status Register 0x20 read-write n 0x0 0x0 TIMER1_EINTSTS TIMER1_EINTSTS Timer1 External Interrupt Status Register 0x38 read-write n 0x0 0x0 TIMER1_EXTCTL TIMER1_EXTCTL Timer1 External Control Register 0x34 read-write n 0x0 0x0 TIMER1_INTSTS TIMER1_INTSTS Timer1 Interrupt Status Register 0x28 read-write n 0x0 0x0 TIMER_CCAP0 TIMER_CCAP0 Timer Continuous Capture Data Register 0 0x44 read-only n 0x0 0x0 CAPDAT Timer Continuous Capture Data Register X\nTIMER_CCAP0 store the timer count value of first rising edge.\nTIMER_CCAP1 store the timer count value of first falling edge.\nTIMER_CCAP2 store the timer count value of second rising edge. 0 24 read-only TIMER_CCAP1 TIMER_CCAP1 Timer Continuous Capture Data Register 1 0x48 read-write n 0x0 0x0 TIMER_CCAP2 TIMER_CCAP2 Timer Continuous Capture Data Register 2 0x4C read-write n 0x0 0x0 TIMER_CCAPCTL TIMER_CCAPCTL Timer Continuous Capture Control Register 0x40 read-write n 0x0 0x0 CAPCHSEL Capture Channel Selection\nSelect the input channel to be captured. 3 3 read-write 0 P0.0 #000 1 P0.4 #001 2 P0.5 #010 3 P0.6 #011 4 P0.7 #100 5 P5.2 #101 6 P3.0 #110 7 P3.1 #111 CAPF1F Capture Falling Edge 1 Flag\nFirst falling edge already captured, this bit will be set to 1.\nNote: This bit is cleared by H/W automatically when write CCAPEN to 1 or writing 1 to it 9 1 read-write 0 None #0 1 TIMER_CCAP1 data is ready for read #1 CAPF2F Capture Falling Edge 2 Flag\nSecond falling edge already captured, this bit will be set to 1.\nNote: This bit is cleared by H/W automatically when write CCAPEN to 1 or writing 1 to it 11 1 read-write 0 None #0 1 TIMER0_CAP or TIMER1_CAP data is ready for read #1 CAPR1F Capture Rising Edge 1 Flag\nFirst rising edge already captured, this bit will be set to 1.\nNote: This bit is cleared by H/W automatically when write CCAPEN to 1 or writing 1 to it 8 1 read-write 0 None #0 1 TIMER_CCAP0 data is ready for read #1 CAPR2F Capture Rising Edge 2 Flag\nSecond rising edge already captured, this bit will be set to 1.\nNote: This bit is cleared by H/W automatically when write CCAPEN to 1 or writing 1 to it 10 1 read-write 0 None #0 1 TIMER_CCAP2 data is ready for read #1 CCAPEN Continuous Capture Enable\nThis bit enables the advanced capture function.\nNote: This bit is cleared by H/W automatically when capture operation finish or writing 0 to it 0 1 read-write 0 Enable #0 1 Disable #1 INV Input Signal Inverse\nInvert the input signal which be captured. 1 1 read-write 0 None #0 1 Inverse #1 TMRSEL Capture Timer Selection\nSelect the timer to capture the input signal. 2 1 read-write 0 Timer 0 #0 1 Timer 1 #1 UART0 UART Register Map UART 0x0 0x0 0x30 registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ADDRDEN RS-485 Address Detection Enable Control\nThis bit is used to enable RS-485 Address Detection mode.\nNote: This field is used for RS-485 any operation mode. 15 1 read-write 0 RS-485 address detection mode Disabled #0 1 RS-485 address detection mode Enabled #1 ADDRMV Address Match Value Register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS485NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation Mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation Mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Mode (AUD) Control\nNote: It can be active with RS485ADD or RS485NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Mode (AUD) Disabled #0 1 RS-485 Auto Direction Mode (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-Drop Operation Mode (NMM) Control\nNote: It cannot be active with RS485AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation Mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation Mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divisor Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 Divider X Equal 1 UART Controller Baud Rate Generator Refer to section UART Controller Baud Rate Generator for more information. 28 1 read-write 0 Divider M = X (the equation of M = X+1, but EDIVM1[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 8) #1 BAUDM1 Divider X Enable\nRefer to the table below for more information.\nNote: When in IrDA mode, this bit must be disabled. 29 1 read-write 0 Divider X Disabled (the equation of M = 16) #0 1 Divider X Enabled (the equation of M = X+1, but EDIVM1 [27:24] must = 8) #1 BRD Baud Rate Divider\nThe field indicates the baud rate divider. 0 16 read-write EDIVM1 Divider X 24 4 read-write UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Receiving/Transmit Buffer\nWrite Operation:\nBy writing to this register, the UART sends out an 8-bit data through the TX pin (LSB first). \nBy reading this register, the UART Controller will return an 8-bit data received from RX pin (LSB first). 0 8 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt (RDAINT) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set (if RDAIEN in UART_INTEN register is enable, an interrupt will generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV RTS Trigger Level (for Auto-flow Control Use)\nNote: This field is used for RTS auto-flow control. 16 4 read-write 0 RTS Trigger Level is 1 byte #0000 1 RTS Trigger Level is 4 bytes #0001 2 RTS Trigger Level is 8 bytes #0010 3 RTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Register\nThe receiver is disabled or not (setting 1 to disable the receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles. 1 1 read-write 0 No effect #0 1 The RX internal state machine and pointers reset #1 TXRST TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles. 2 1 read-write 0 No effect #0 1 The TX internal state machine and pointers reset #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ADDRDETF RS-485 Address Byte Detection Flag \nNote1: This field is used for RS-485 function mode.\nNote2: This bit is cleared by writing 1 to it. 3 1 read-write BIF Break Interrupt Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). Note: This bit is read only, but software can write 1 to clear it. 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only)\nNote: This bit is read only, but can be cleared by writing '1' to it . 5 1 read-only 1 Framing error is generated #1 PEF Parity Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit . 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated.Note: This bit is read only, but can be cleared by writing '1' to it #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXOVIF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit is cleared by writing 1 to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select 0 2 read-write 0 UART function mode #00 1 Reserved #01 2 IrDA function mode #10 3 RS-485 function mode #11 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ATOCTSEN CTS Auto Flow Control Enable Control\nNote: When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 read-write 0 CTS auto flow control Disabled #0 1 CTS auto flow control Enabled #1 ATORTSEN RTS Auto Flow Control Enable Control\nNote: When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO [19:16]), the UART will de-assert RTS signal. 12 1 read-write 0 RTS auto flow control Disabled #0 1 RTS auto flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Control 5 1 read-write 0 BUFERRINT Masked Disabled #0 1 BUFERRINT Enabled #1 MODEMIEN Modem Status Interrupt Enable Control 3 1 read-write 0 MODEMINT Masked off #0 1 MODEMINT Enabled #1 RDAIEN Receive Data Available Interrupt Enable Control 0 1 read-write 0 RDAINT Masked off #0 1 RDAINT Enabled #1 RLSIEN Receive Line Status Interrupt Enable Control 2 1 read-write 0 RLSINT Masked off #0 1 RLSINT Enabled #1 RXTOIEN RX Time-Out Interrupt Enable Control 4 1 read-write 0 RXTOINT Masked off #0 1 RXTOINT Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Control 1 1 read-write 0 THREINT Masked off #0 1 THREINT Enabled #1 TOCNTEN Time-Out Counter Enable Control 11 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 WKCTSIEN Wake-Up CPU Function Enable Control Note: when the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode. 6 1 read-write 0 UART wake-up function Disabled #0 1 UART Wake-up function Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX/RX FIFO overflow flag (TXOVIF or RXOVIF) is set. \nWhen BUFERRIF is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TXOVIF and RXOVIF are cleared. 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and BUFERRIF are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 buffer error interrupt is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN and MODENIF are both set to 1. 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 MODENIF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF. 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 RDAIF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN and RDAIF are both set to 1.\nThis bit is set if RDAIEN and RDAIF are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF, FEF, PEF and ADDRDETF are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt (Read Only)\nThis bit is set if RLSIEN and RLSIF are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RXTOIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 RXTOINT Time-Out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN and RXTOIF are both set to 1. 12 1 read-only 0 No Time-out interrupt is generated #0 1 Time-out interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN [1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into DAT (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN and THREIF are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV RXINV 6 1 read-write 0 No inversion #0 1 Inverse RX input signal #1 TXEN TXEN 1 1 read-write 0 IrDA receiver Enabled #0 1 IrDA transmitter Enabled #1 TXINV TXINV 5 1 read-write 0 No inversion #0 1 Inverse TX output signal #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write 0 Break control Disabled #0 1 Break control Enabled #1 EPE Even Parity Enable Control\nThis bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number Of STOP Bit 2 1 read-write 0 One STOP bit is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-, 7- and 8-bti word length, 2 STOP bit is generated in the transmitted data #1 PBE Parity Bit Enable Control 3 1 read-write 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 SPE Stick Parity Enable Control 5 1 read-write 0 Stick parity Disabled #0 1 If PBE (UART_LINE[3]) and EBE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EBE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1 #1 WLS Word Length Selection 0 2 read-write 0 Word length is 5-bit #00 1 Word length is 6-bit #01 2 Word length is 7-bit #10 3 Word length is 8-bit #11 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS RTS (Request-To-Send) Signal Control\nThis bit is direct control internal RTS signal active or not, and then drive the RTS pin output with RTSACTLV bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control is enabled in UART function mode.\nNote2: This RTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 RTS signal is active #0 1 RTS signal is inactive #1 RTSACTLV RTS Pin Active Level\nThis bit defines the active level state of RTS pin output. 9 1 read-write 0 RTS pin output is high level active #0 1 RTS pin output is low level active #1 RTSSTS RTS Pin State (Read Only)\nThis bit mirror from RTS pin output of voltage logic status. 13 1 read-only 0 RTS pin output is low level voltage logic state #0 1 RTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 6.1410 8 1 read-write 0 CTS pin input is high level active #0 1 CTS pin input is low level active #1 CTSDETF Detect CTS State Change Flag\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 CTS input has not change state #0 1 CTS input has change state #1 CTSSTS CTS Pin Status (Read Only)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected. 4 1 read-only 0 CTS pin input is low level voltage logic state #0 1 CTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value\nThis field is used to program the transfer delay time between the last stop bit and next start bit. 8 8 read-write TOIC Time-Out Interrupt Comparator 0 8 read-write UART1 UART Register Map UART 0x0 0x0 0x30 registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ADDRDEN RS-485 Address Detection Enable Control\nThis bit is used to enable RS-485 Address Detection mode.\nNote: This field is used for RS-485 any operation mode. 15 1 read-write 0 RS-485 address detection mode Disabled #0 1 RS-485 address detection mode Enabled #1 ADDRMV Address Match Value Register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS485NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation Mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation Mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Mode (AUD) Control\nNote: It can be active with RS485ADD or RS485NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Mode (AUD) Disabled #0 1 RS-485 Auto Direction Mode (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-Drop Operation Mode (NMM) Control\nNote: It cannot be active with RS485AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation Mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation Mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divisor Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 Divider X Equal 1 UART Controller Baud Rate Generator Refer to section UART Controller Baud Rate Generator for more information. 28 1 read-write 0 Divider M = X (the equation of M = X+1, but EDIVM1[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 8) #1 BAUDM1 Divider X Enable\nRefer to the table below for more information.\nNote: When in IrDA mode, this bit must be disabled. 29 1 read-write 0 Divider X Disabled (the equation of M = 16) #0 1 Divider X Enabled (the equation of M = X+1, but EDIVM1 [27:24] must = 8) #1 BRD Baud Rate Divider\nThe field indicates the baud rate divider. 0 16 read-write EDIVM1 Divider X 24 4 read-write UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Receiving/Transmit Buffer\nWrite Operation:\nBy writing to this register, the UART sends out an 8-bit data through the TX pin (LSB first). \nBy reading this register, the UART Controller will return an 8-bit data received from RX pin (LSB first). 0 8 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt (RDAINT) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set (if RDAIEN in UART_INTEN register is enable, an interrupt will generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV RTS Trigger Level (for Auto-flow Control Use)\nNote: This field is used for RTS auto-flow control. 16 4 read-write 0 RTS Trigger Level is 1 byte #0000 1 RTS Trigger Level is 4 bytes #0001 2 RTS Trigger Level is 8 bytes #0010 3 RTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Register\nThe receiver is disabled or not (setting 1 to disable the receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles. 1 1 read-write 0 No effect #0 1 The RX internal state machine and pointers reset #1 TXRST TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles. 2 1 read-write 0 No effect #0 1 The TX internal state machine and pointers reset #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ADDRDETF RS-485 Address Byte Detection Flag \nNote1: This field is used for RS-485 function mode.\nNote2: This bit is cleared by writing 1 to it. 3 1 read-write BIF Break Interrupt Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). Note: This bit is read only, but software can write 1 to clear it. 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only)\nNote: This bit is read only, but can be cleared by writing '1' to it . 5 1 read-only 1 Framing error is generated #1 PEF Parity Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit . 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated.Note: This bit is read only, but can be cleared by writing '1' to it #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXOVIF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit is cleared by writing 1 to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select 0 2 read-write 0 UART function mode #00 1 Reserved #01 2 IrDA function mode #10 3 RS-485 function mode #11 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ATOCTSEN CTS Auto Flow Control Enable Control\nNote: When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 read-write 0 CTS auto flow control Disabled #0 1 CTS auto flow control Enabled #1 ATORTSEN RTS Auto Flow Control Enable Control\nNote: When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO [19:16]), the UART will de-assert RTS signal. 12 1 read-write 0 RTS auto flow control Disabled #0 1 RTS auto flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Control 5 1 read-write 0 BUFERRINT Masked Disabled #0 1 BUFERRINT Enabled #1 MODEMIEN Modem Status Interrupt Enable Control 3 1 read-write 0 MODEMINT Masked off #0 1 MODEMINT Enabled #1 RDAIEN Receive Data Available Interrupt Enable Control 0 1 read-write 0 RDAINT Masked off #0 1 RDAINT Enabled #1 RLSIEN Receive Line Status Interrupt Enable Control 2 1 read-write 0 RLSINT Masked off #0 1 RLSINT Enabled #1 RXTOIEN RX Time-Out Interrupt Enable Control 4 1 read-write 0 RXTOINT Masked off #0 1 RXTOINT Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Control 1 1 read-write 0 THREINT Masked off #0 1 THREINT Enabled #1 TOCNTEN Time-Out Counter Enable Control 11 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 WKCTSIEN Wake-Up CPU Function Enable Control Note: when the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode. 6 1 read-write 0 UART wake-up function Disabled #0 1 UART Wake-up function Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX/RX FIFO overflow flag (TXOVIF or RXOVIF) is set. \nWhen BUFERRIF is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TXOVIF and RXOVIF are cleared. 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and BUFERRIF are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 buffer error interrupt is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN and MODENIF are both set to 1. 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 MODENIF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF. 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 RDAIF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN and RDAIF are both set to 1.\nThis bit is set if RDAIEN and RDAIF are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF, FEF, PEF and ADDRDETF are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt (Read Only)\nThis bit is set if RLSIEN and RLSIF are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RXTOIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 RXTOINT Time-Out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN and RXTOIF are both set to 1. 12 1 read-only 0 No Time-out interrupt is generated #0 1 Time-out interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN [1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into DAT (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN and THREIF are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV RXINV 6 1 read-write 0 No inversion #0 1 Inverse RX input signal #1 TXEN TXEN 1 1 read-write 0 IrDA receiver Enabled #0 1 IrDA transmitter Enabled #1 TXINV TXINV 5 1 read-write 0 No inversion #0 1 Inverse TX output signal #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write 0 Break control Disabled #0 1 Break control Enabled #1 EPE Even Parity Enable Control\nThis bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number Of STOP Bit 2 1 read-write 0 One STOP bit is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-, 7- and 8-bti word length, 2 STOP bit is generated in the transmitted data #1 PBE Parity Bit Enable Control 3 1 read-write 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 SPE Stick Parity Enable Control 5 1 read-write 0 Stick parity Disabled #0 1 If PBE (UART_LINE[3]) and EBE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EBE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1 #1 WLS Word Length Selection 0 2 read-write 0 Word length is 5-bit #00 1 Word length is 6-bit #01 2 Word length is 7-bit #10 3 Word length is 8-bit #11 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS RTS (Request-To-Send) Signal Control\nThis bit is direct control internal RTS signal active or not, and then drive the RTS pin output with RTSACTLV bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control is enabled in UART function mode.\nNote2: This RTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 RTS signal is active #0 1 RTS signal is inactive #1 RTSACTLV RTS Pin Active Level\nThis bit defines the active level state of RTS pin output. 9 1 read-write 0 RTS pin output is high level active #0 1 RTS pin output is low level active #1 RTSSTS RTS Pin State (Read Only)\nThis bit mirror from RTS pin output of voltage logic status. 13 1 read-only 0 RTS pin output is low level voltage logic state #0 1 RTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 6.1410 8 1 read-write 0 CTS pin input is high level active #0 1 CTS pin input is low level active #1 CTSDETF Detect CTS State Change Flag\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 CTS input has not change state #0 1 CTS input has change state #1 CTSSTS CTS Pin Status (Read Only)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected. 4 1 read-only 0 CTS pin input is low level voltage logic state #0 1 CTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value\nThis field is used to program the transfer delay time between the last stop bit and next start bit. 8 8 read-write TOIC Time-Out Interrupt Comparator 0 8 read-write WDT WDT Register Map WDT 0x0 0x0 0x4 registers n CTL WDT_CTL Watchdog Timer Control Register 0x0 -1 read-write n 0x0 0x0 ICEDEBUG ICE Debug Mode Acknowledge Disable Control (Write Protect)\nWDT up counter will keep going no matter CPU is hanging by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects WDT counting #0 1 ICE debug mode acknowledgement Disabled #1 IF Watchdog Timer Time-Out Interrupt Flag\nThis bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it. 3 1 read-write 0 WDT time-out interrupt did not occur #0 1 WDT time-out interrupt occurred #1 INTEN Watchdog Timer Time-Out Interrupt Enable Control (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. 6 1 read-write 0 WDT time-out interrupt Disabled #0 1 WDT time-out interrupt Enabled #1 RSTCNT Reset Watchdog Timer Up Counter (Write Protect)\nNote: This bit will be automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Reset the internal 18-bit WDT up counter value #1 RSTEN Watchdog Timer Time-Out Reset Enable Control (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period (1024 * TWDT) expires. 1 1 read-write 0 WDT time-out reset function Disabled #0 1 WDT time-out reset function Enabled #1 RSTF Watchdog Timer Time-Out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it. 2 1 read-write 0 WDT time-out reset did not occur #0 1 WDT time-out reset occurred #1 TOUTSEL Watchdog Timer Interval Selection\nThese three bits select the time-out interval for the Watchdog Timer. 8 3 read-write 0 24 * TWDT #000 1 26 * TWDT #001 2 28 * TWDT #010 3 210 * TWDT #011 4 212 * TWDT #100 5 214 * TWDT #101 6 216 * TWDT #110 7 218 * TWDT #111 WDTEN Watchdog Timer Enable Control (Write Protect) 7 1 read-write 0 WDT Disabled. (This action will reset the internal up counter value.) #0 1 WDT Enabled #1 WKEN Watchdog Timer Time-Out Wake-Up Function Control (Write Protect)\nIf this bit is set to 1, while IF is generated to 1 and INTEN enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator. 4 1 read-write 0 Wake-up trigger event Disabled if WDT time-out interrupt signal generated #0 1 Wake-up trigger event Enabled if WDT time-out interrupt signal generated #1 WKF Watchdog Timer Time-Out Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of WDT.\nNote: This bit is cleared by writing 1 to it. 5 1 read-write 0 WDT does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated #1