nuvoTon
MINI58DE_v1
2024.05.02
MINI58DE_v1 SVD file
8
32
ACMP
ACMP Register Map
ACMP
0x0
0x0
0x10
registers
n
CTL0
ACMP_CTL0
Analog Comparator 0 Control Register
0x0
read-write
n
0x0
0x0
ACMPEN
Analog Comparator 0 Enable Bit\nNote: Analog comparator output needs to wait 2 us stable time after this bit is set.
0
1
read-write
0
Analog Comparator 0 Disabled
#0
1
Analog Comparator 1 Enabled
#1
ACMPIE
Analog Comparator 0 Interrupt Enable Bit\n
1
1
read-write
0
Interrupt function Disabled
#0
1
Interrupt function Enabled
#1
FILTSEL
Comparator Output Filter Count Selection\n
20
4
read-write
0
Filter function is Disabled
#0000
1
ACMP0 output is sampled 1 consecutive PCLK
#0001
2
ACMP0 output is sampled 2 consecutive PCLKs
#0010
3
ACMP0 output is sampled 4 consecutive PCLKs
#0011
4
ACMP0 output is sampled 8 consecutive PCLKs
#0100
5
ACMP0 output is sampled 16 consecutive PCLKs
#0101
6
ACMP0 output is sampled 32 consecutive PCLKs
#0110
7
ACMP0 output is sampled 64 consecutive PCLKs
#0111
8
ACMP0 output is sampled 128 consecutive PCLKs
#1000
9
ACMP0 output is sampled 256 consecutive PCLKs
#1001
10
ACMP0 output is sampled 512 consecutive PCLKs
#1010
FTRGEN
Analog Comparator 0 Falling Edge Trigger Enable\nNote: The bit is only effective while analog comparator 0 triggers PWM or Timer.
9
1
read-write
0
Analog comparator 0 falling edge trigger PWM or Timer enabled
#0
1
Analog comparator 0 falling edge trigger disabled
#1
HYSSEL
Analog Comparator 0 Hysteresis Select Bit\n
2
1
read-write
0
Hysteresis function Disabled
#0
1
Hysteresis function Enabled
#1
NEGSEL
Analog Comparator 0 Negative Input Select Bit\n
4
1
read-write
0
The source of the negative comparator input is from CPN0 pin
#0
1
The source of the negative comparator input is from internal band-gap voltage or comparator reference voltage
#1
POSSEL
Analog Comparator 0 Positive Input Selection\n
29
2
read-write
0
ACMP0_Px is from ACMP0_P0 (P1.5) pin
#00
1
ACMP0_Px is from ACMP0_P1 (P1.0) pin
#01
2
ACMP0_Px is from ACMP0_P2 (P1.2) pin
#10
3
ACMP0_Px is from ACMP0_P3 (P1.3) pin
#11
RTRGEN
Analog Comparator 0 Rising Edge Trigger Enable Bit\nNote: The bit is only effective while analog comparator 0 triggers PWM or Timer.
8
1
read-write
0
Analog comparator 0 rising edge trigger PWM or Timer enabled
#0
1
Analog comparator 0 rising edge trigger disabled
#1
CTL1
ACMP_CTL1
Analog Comparator 1 Control Register
0x4
read-write
n
0x0
0x0
ACMPEN
Analog Comparator 1 Enable Bit\nNote: Analog comparator output needs to wait 2 us stable time after this bit is set.
0
1
read-write
0
Analog Comparator 1 Disabled
#0
1
Analog Comparator 1 Enabled
#1
ACMPIE
Analog Comparator 1 Interrupt Enable Bit\n
1
1
read-write
0
Interrupt function Disabled
#0
1
Interrupt function Enabled
#1
FILTSEL
Comparator Output Filter Count Selection\n
20
4
read-write
0
Filter function is Disabled
#0000
1
ACMP1 output is sampled 1 consecutive PCLK
#0001
2
ACMP1 output is sampled 2 consecutive PCLKs
#0010
3
ACMP1 output is sampled 4 consecutive PCLKs
#0011
4
ACMP1 output is sampled 8 consecutive PCLKs
#0100
5
ACMP1 output is sampled 16 consecutive PCLKs
#0101
6
ACMP1 output is sampled 32 consecutive PCLKs
#0110
7
ACMP1 output is sampled 64 consecutive PCLKs
#0111
8
ACMP1 output is sampled 128 consecutive PCLKs
#1000
9
ACMP1 output is sampled 256 consecutive PCLKs
#1001
10
ACMP1 output is sampled 512 consecutive PCLKs
#1010
FTRGEN
Analog Comparator 1 Falling Edge Trigger Enable Bit\nNote: The bit is only effective while analog comparator 1 triggers PWM or Timer.
9
1
read-write
0
Analog comparator 1 falling edge trigger PWM or Timer Enabled
#0
1
Analog comparator 1 falling edge trigger Disabled
#1
HYSSEL
Analog Comparator 1 Hysteresis Select Bit\n
2
1
read-write
0
Hysteresis function Disabled
#0
1
Hysteresis function Enabled
#1
NEGSEL
Analog Comparator 1 Negative Input Select Bit\n
4
1
read-write
0
The source of the negative comparator input is from CPN1 pin
#0
1
The source of the negative comparator input is from internal band-gap voltage or comparator reference voltage
#1
POSSEL
Analog Comparator 1 Positive Input Selection\n
29
2
read-write
0
ACMP1_Px is from ACMP1_P0 (P3.1) pin
#00
1
ACMP1_Px is from ACMP1_P1 (P3.2) pin
#01
2
ACMP1_Px is from ACMP1_P2 (P3.4) pin
#10
3
ACMP1_Px is from ACMP1_P3 (P3.5) pin
#11
RTRGEN
Analog Comparator 1 Rising Edge Trigger Enable Bit\nNote: The bit is only effective while analog comparator 1 triggers PWM or Timer.
8
1
read-write
0
Analog comparator 1 rising edge trigger PWM or Timer Enabled
#0
1
Analog comparator 1 rising edge trigger Disabled
#1
STATUS
ACMP_STATUS
Analog Comparator 0/1 Status Register
0x8
read-write
n
0x0
0x0
ACMPIF0
Analog Comparator 0 Flag\nNote: This bit can be cleared to 0 by software writing 1.
0
1
read-write
0
Analog comparator 0 output does not change
#0
1
Analog comparator 0 output changed
#1
ACMPIF1
Analog Comparator 1 Flag\nNote: This bit can be cleared to 0 by software writing 1.
1
1
read-write
0
Analog comparator 1 output does not change
#0
1
Analog comparator 1 output changed
#1
ACMPO0
Analog Comparator 0 Output\n
2
1
read-write
0
Analog comparator 0 outputs 0
#0
1
Analog comparator 0 outputs 1
#1
ACMPO1
Analog Comparator 1 Output\n
3
1
read-write
0
Analog comparator 1 outputs 0
#0
1
Analog comparator 1 outputs 1
#1
VREF
ACMP_VREF
Analog Comparator Reference Voltage Control Register
0xC
read-write
n
0x0
0x0
CRVCTL
Comparator Reference Voltage Control\n
0
4
read-write
IREFSEL
CRV Internal Reference Selection\n
7
1
read-write
0
Band-gap voltage
#0
1
Internal comparator reference voltage
#1
ADC
ADC Register Map
ADC
0x0
0x0
0x4
registers
n
0x20
0x14
registers
n
0x44
0x14
registers
n
CHEN
ADC_CHEN
A/D Channel Enable Register
0x24
read-write
n
0x0
0x0
CH7SEL
Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7, the ADC clock rate needs to be limited to lower than 300 kHz.
8
1
read-write
0
External analog input
#0
1
Internal band-gap voltage (VBG)
#1
CHEN0
Analog Input Channel 0 Enable Bit\nNote: If software enables more than one channel, the channel with the smallest number will be selected and the other enabled channels will be ignored.
0
1
read-write
0
Channel 0 Disabled
#0
1
Channel 0 Enabled
#1
CHEN1
Analog Input Channel 1 Enable Bit\n
1
1
read-write
0
Channel 1 Disabled
#0
1
Channel 1 Enabled
#1
CHEN2
Analog Input Channel 2 Enable Bit\n
2
1
read-write
0
Channel 2 Disabled
#0
1
Channel 2 Enabled
#1
CHEN3
Analog Input Channel 3 Enable Bit\n
3
1
read-write
0
Channel 3 Disabled
#0
1
Channel 3 Enabled
#1
CHEN4
Analog Input Channel 4 Enable Bit\n
4
1
read-write
0
Channel 4 Disabled
#0
1
Channel 4 Enabled
#1
CHEN5
Analog Input Channel 5 Enable Bit\n
5
1
read-write
0
Channel 5 Disabled
#0
1
Channel 5 Enabled
#1
CHEN6
Analog Input Channel 6 Enable Bit\n
6
1
read-write
0
Channel 6 Disabled
#0
1
Channel 6 Enabled
#1
CHEN7
Analog Input Channel 7 Enable Bit\n
7
1
read-write
0
Channel 7 Disabled
#0
1
Channel 7 Enabled
#1
CMP0
ADC_CMP0
A/D Compare Register 0
0x28
read-write
n
0x0
0x0
ADCMPEN
A/D Compare Enable Bit\nSet 1 to this bit to enable comparing CMPDAT (ADC_CMPx[25:16]) with specified channel conversion results when converted data is loaded into the ADC_DAT register.\n
0
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
ADCMPIE
A/D Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT, ADCMPIE bit will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.\n
1
1
read-write
0
Compare function interrupt Disabled
#0
1
Compare function interrupt Enabled
#1
CMPCH
Compare Channel Selection\nSet this field to select which channel's result to be compared.\nNote: Valid setting of this field is channel 0~7.
3
3
read-write
CMPCOND
Compare Condition\nNote: When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx bit will be set.
2
1
read-write
0
Set the compare condition as that when a 10-bit A/D conversion result is less than the 10-bit CMPDAT (ADC_CMPx[25:16]), the internal match counter will increase one
#0
1
Set the compare condition as that when a 10-bit A/D conversion result is greater or equal to the 10-bit CMPDAT (ADC_CMPx[25:16]), the internal match counter will increase one
#1
CMPDAT
Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel.
16
10
read-write
CMPMCNT
Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx bit will be set.
8
4
read-write
CMP1
ADC_CMP1
A/D Compare Register 1
0x2C
read-write
n
0x0
0x0
CTL
ADC_CTL
A/D Control Register
0x20
read-write
n
0x0
0x0
ADCEN
A/D Converter Enable Bit\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
0
1
read-write
0
A/D Converter Disabled
#0
1
A/D Converter Enabled
#1
ADCIEN
A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADCIEN bit is set to 1.\n
1
1
read-write
0
A/D interrupt function Disabled
#0
1
A/D interrupt function Enabled
#1
HWTRGCOND
Hardware External Trigger Condition\nThis bit decides whether the external pin STADC trigger event is falling or raising edge. The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigger.\n
6
1
read-write
0
Falling edge
#0
1
Raising edge
#1
HWTRGEN
Hardware External Trigger Enable Bit\nEnable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled, the SWTRG bit can be set to 1 by the selected hardware trigger source.\n
8
1
read-write
0
External trigger Disabled
#0
1
External trigger Enabled
#1
HWTRGSEL
Hardware Trigger Source Select Bit\nNote: Software should disable TRGEN and SWTRG before change TRGS.
4
2
read-write
0
A/D conversion is started by external STADC pin
#00
3
A/D conversion is started by PWM trigger
#11
SWTRG
Software Trigger A/D Conversion Start\nSWTRG bit can be set to 1 from two sources: software and external pin STADC. SWTRG will be cleared to 0 by hardware automatically after conversion complete.\n
11
1
read-write
0
Conversion stopped and A/D converter entered idle state
#0
1
Conversion start
#1
DAT
ADC_DAT
A/D Data Register
0x0
read-only
n
0x0
0x0
OV
Over Run Flag\nIf converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after the ADC_DAT register is read.\n
16
1
read-only
0
Data in RESULT[9:0] is recent conversion result
#0
1
Data in RESULT[9:0] overwrote
#1
RESULT
A/D Conversion Result\nThis field contains conversion result of ADC.
0
10
read-only
VALID
Valid Flag \nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read.\n
17
1
read-only
0
Data in RESULT[9:0] bits not valid
#0
1
Data in RESULT[9:0] bits valid
#1
EXTSMPT
ADC_EXTSMPT
A/D Sampling Time Counter Register
0x48
read-write
n
0x0
0x0
EXTSMPT
Additional ADC Sample Clock\nIf the ADC input is unstable, user can set this register to increase the sampling time to get a stable ADC input signal. The default sampling time is 1 ADC clocks. The additional clock number will be inserted to lengthen the sampling clock.\n
0
4
read-write
0
Number of additional clock cycles is 0
0
1
Number of additional clock cycles is 1
1
10
Number of additional clock cycles is 512
10
11
Number of additional clock cycles is 1024
11
12
Number of additional clock cycles is 1024
12
13
Number of additional clock cycles is 1024
13
14
Number of additional clock cycles is 1024
14
15
Number of additional clock cycles is 1024
15
2
Number of additional clock cycles is 2
2
3
Number of additional clock cycles is 4
3
4
Number of additional clock cycles is 8
4
5
Number of additional clock cycles is 16
5
6
Number of additional clock cycles is 32
6
7
Number of additional clock cycles is 64
7
8
Number of additional clock cycles is 128
8
9
Number of additional clock cycles is 256
9
SEQCTL
ADC_SEQCTL
A/D PWM Sequential Mode Control Register
0x4C
read-write
n
0x0
0x0
MODESEL
ADC Sequential Mode Selection\n
2
2
read-write
0
Issue ADC_INT after Channel 0 then Channel 1 conversion finishes when SEQEN =1
#00
1
Issue ADC_INT after Channel 1 then Channel 2 conversion finishes when SEQEN =1
#01
2
Issue ADC_INT after Channel 0 then Channel 2 conversion finishes when SEQEN =1
#10
3
Reserved
#11
SEQEN
ADC Sequential Mode Enable Bit\nWhen ADC sequential mode is enabled, two of three ADC channels from 0 to 2 will automatically convert analog data in the sequence of channel [0, 1] or channel[1, 2] or channel[0, 2] defined by MODESEL (ADC_SEQCTL[3:2]).\n
0
1
read-write
0
ADC sequential mode Disabled
#0
1
ADC sequential mode Enabled
#1
SEQTYPE
ADC Sequential Mode Type\n
1
1
read-write
0
ADC delay time is only inserted before the first conversion. The second conversion starts immediately after the first conversion is completed. (for 2/3-shunt type)
#0
1
ADC delay time is inserted before each conversion. (for 1-shunt type)
#1
TRG1CTL
PWM Trigger Source Selection For TRG1CTL[3:2]
Note: PWM trigger source is valid for 1-shunt and 2/3-shunt type.
8
4
read-write
0
PWM Trigger source is PWM0.\nRising of the selected PWM
00
1
PWM Trigger source is PWM2.\nCenter of the selected PWM
01
10
PWM Trigger source is PWM4.\nFalling of the selected PWM
10
11
PWM Trigger source is reserved.\nPeriod of the selected PWM
11
TRG2CTL
PWM Trigger Source Selection For TRG2CTL[3:2]\nNote: PWM trigger source is valid for 1-shunt type.
16
4
read-write
0
PWM Trigger source is PWM0.\nRising of the selected PWM
00
1
PWM Trigger source is PWM2.\nCenter of the selected PWM
01
10
PWM Trigger source is PWM4.\nFalling of the selected PWM
10
11
PWM Trigger source is reserved.\nPeriod of the selected PWM
11
SEQDAT1
ADC_SEQDAT1
A/D PWM Sequential Mode First Result Register1
0x50
read-only
n
0x0
0x0
OV
Over Run Flag\nIf converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after the ADC_DAT register is read.\n
16
1
read-only
0
Data in RESULT[9:0] is recent conversion result
#0
1
Data in RESULT[9:0] overwritten
#1
RESULT
A/D PWM Sequential Mode Conversion Result\nThis field contains conversion result of ADC.
0
10
read-only
VALID
Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read.\n
17
1
read-only
0
Data in RESULT[9:0] bits not valid
#0
1
Data in RESULT[9:0] bits valid
#1
SEQDAT2
ADC_SEQDAT2
A/D PWM Sequential Mode Second Result Register1
0x54
read-write
n
0x0
0x0
STATUS
ADC_STATUS
A/D Status Register
0x30
read-write
n
0x0
0x0
ADCMPF0
A/D Compare Flag 0\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP0, this bit is set to 1.\nNote: This bit can be cleared to 0 by software writing 1.
1
1
read-write
0
Conversion result in ADC_DAT does not meet the ADC_CMP0 setting
#0
1
Conversion result in ADC_DAT meets the ADC_CMP0 setting
#1
ADCMPF1
A/D Compare Flag 1\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP1, this bit is set to 1.\nNote: This bit can be cleared to 0 by software writing 1.
2
1
read-write
0
Conversion result in ADC_DAT does not meet the ADC_CMP1 setting
#0
1
Conversion result in ADC_DAT meets the ADC_CMP1 setting
#1
ADIF
A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. ADIF is set to 1 When A/D conversion ends.\nNote: This bit can be cleared to 0 by software writing 1.
0
1
read-write
BUSY
BUSY/IDLE (Read Only)\nThis bit is mirror of as SWTRG bit in ADC_CTL\n
3
1
read-only
0
A/D converter is in idle state
#0
1
A/D converter is busy at conversion
#1
CHANNEL
Current Conversion Channel (Read Only)\n
4
3
read-only
OV
Overrun Flag (Read Only)\nIt is a mirror to OV bit in ADC_DAT register.
16
1
read-only
VALID
Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in ADC_DAT register.
8
1
read-only
TRGDLY
ADC_TRGDLY
A/D Trigger Delay Control Register
0x44
read-write
n
0x0
0x0
DELAY
PWM Trigger Delay Timer\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * DELAY) * system clock.
0
8
read-write
CLK
CLK Register Map
CLK
0x0
0x0
0x28
registers
n
AHBCLK
CLK_AHBCLK
AHB Devices Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
ISPCKEN
Flash ISP Controller Clock Enable Bit\n
2
1
read-write
0
Flash ISP peripheral clock Disabled
#0
1
Flash ISP peripheral clock Enabled
#1
APBCLK
CLK_APBCLK
APB Devices Clock Enable Control Register
0x8
-1
read-write
n
0x0
0x0
ACMPCKEN
Analog Comparator Clock Enable Bit\n
30
1
read-write
0
Analog Comparator clock Disabled
#0
1
Analog Comparator clock Enabled
#1
ADCCKEN
Analog-digital-converter (ADC) Clock Enable Bit\n
28
1
read-write
0
ADC peripheral clock Disabled
#0
1
ADC peripheral clock Enabled
#1
CLKOCKEN
Frequency Divider Output Clock Enable Bit\n
6
1
read-write
0
CLKO clock Disabled
#0
1
CLKO clock Enabled
#1
I2C0CKEN
I2C0 Clock Enable Bit\n
8
1
read-write
0
I2C0 clock Disabled
#0
1
I2C0 clock Enabled
#1
I2C1CKEN
I2C1 Clock Enable Bit\n
9
1
read-write
0
I2C1 clock Disabled
#0
1
I2C1 clock Enabled
#1
PWMCH01CKEN
PWM_01 Clock Enable Bit\n
20
1
read-write
0
PWM01 clock Disabled
#0
1
PWM01 clock Enabled
#1
PWMCH23CKEN
PWM_23 Clock Enable Bit\n
21
1
read-write
0
PWM23 clock Disabled
#0
1
PWM23 clock Enabled
#1
PWMCH45CKEN
PWM_45 Clock Enable Bit\n
22
1
read-write
0
PWM45 clock Disabled
#0
1
PWM45 clock Enabled
#1
SPICKEN
SPI Clock Enable Bit\n
12
1
read-write
0
SPI peripheral clock Disabled
#0
1
SPI peripheral clock Enabled
#1
TMR0CKEN
Timer0 Clock Enable Bit\n
2
1
read-write
0
Timer0 clock Disabled
#0
1
Timer0 clock Enabled
#1
TMR1CKEN
Timer1 Clock Enable Bit\n
3
1
read-write
0
Timer1 clock Disabled
#0
1
Timer1 clock Enabled
#1
UART0CKEN
UART0 Clock Enable Bit\n
16
1
read-write
0
UART0 clock Disabled
#0
1
UART0 clock Enabled
#1
UART1CKEN
UART1 Clock Enable Bit\n
17
1
read-write
0
UART1 clock Disabled
#0
1
UART1 clock Enabled
#1
WDTCKEN
Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address SYS_BA + 0x100.
0
1
read-write
0
Watchdog Timer clock Disabled
#0
1
Watchdog Timer clock Enabled
#1
CLKDIV
CLK_CLKDIV
Clock Divider Number Register
0x18
read-write
n
0x0
0x0
ADCDIV
ADC Peripheral Clock Divide Number From ADC Peripheral Clock Source\n
16
8
read-write
HCLKDIV
HCLK Clock Divide Number From HCLK Clock Source\n
0
4
read-write
UARTDIV
UART Clock Divide Number From UART Clock Source\n
8
4
read-write
CLKOCTL
CLK_CLKOCTL
Frequency Divider Control Register
0x24
read-write
n
0x0
0x0
CLKOEN
Frequency Divider Enable Bit\n
4
1
read-write
0
Frequency Divider Disabled
#0
1
Frequency Divider Enabled
#1
DIV1EN
Frequency Divider One Enable Bit\n
5
1
read-write
0
Divider output frequency is depended on FREQSEL value
#0
1
Divider output frequency is the same as input clock frequency
#1
FREQSEL
Divider Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL(CLK_CLKOCTL[3:0]).
0
4
read-write
CLKSEL0
CLK_CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLKSEL
HCLK Clock Source Selection (Write Protect)\nNote1: Before clock switching, the related clock sources (both pre-select and new-select) must be turn-on and stable.\nNote2: These bits are protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address SYS_BA + 0x100.\nNote3: To set CLK_PWRCTL[1:0] to select HXT or LXT crystal clock.
0
3
read-write
0
Clock source is from HXT or LXT
#000
1
Reserved
#001
2
Clock source is from PLL
#010
3
Clock source is from LIRC
#011
7
Clock source is from HIRC
#111
STCLKSEL
Cortex-M0 SysTick Clock Source Selection (Write Protect)\nNote3: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
3
3
read-write
0
Clock source is from HXT or LXT
#000
1
Reserved
#001
2
Clock source is from HXT/2 or LXT/2
#010
3
Clock source is from HCLK/2
#011
7
Clock source is from HIRC/2
#111
CLKSEL1
CLK_CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
ADCSEL
ADC Peripheral Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
2
2
read-write
0
Clock source is from HXT or LXT
#00
1
Clock source is from PLL
#01
2
Clock source is from HCLK
#10
3
Clock source is from HIRC
#11
PWMCH01SEL
PWM0 And PWM1 Clock Source Selection\nPWM0 and PWM1 use the same peripheral clock source. Both of them use the same prescaler.\n
28
2
read-write
0
Reserved
#00
1
Reserved
#01
2
Clock source is from HCLK
#10
3
Reserved
#11
PWMCH23SEL
PWM2 And PWM3 Clock Source Selection
PWM2 and PWM3 use the same peripheral clock source Both of them use the same prescaler.
30
2
read-write
0
Reserved
#00
1
Reserved
#01
2
Clock source is from HCLK
#10
3
Reserved
#11
SPISEL
SPI Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
4
2
read-write
0
Clock source is from HXT or LXT
#00
1
Clock source is from HCLK
#01
2
Clock source is from PLL
#10
3
Reserved
#11
TMR0SEL
TIMER0 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
8
3
read-write
0
Clock source is from HXT or LXT
#000
1
Clock source is from LIRC
#001
2
Clock source is from HCLK
#010
3
Clock source is from external trigger
#011
7
Clock source is from HIRC
#111
TMR1SEL
TIMER1 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
12
3
read-write
0
Clock source is from HXT or LXT
#000
1
Clock source is from LIRC
#001
2
Clock source is from HCLK
#010
3
Clock source is from external trigger
#011
7
Clock source is from HIRC
#111
UARTSEL
UART Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
24
2
read-write
0
Clock source is from HXT or LXT
#00
1
Clock source is from PLL
#01
2
Clock source is from HIRC
#10
3
Clock source is from HIRC
#11
WDTSEL
WDT CLK Clock Source Selection (Write Protect)\nNote1: These bits are the protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address SYS_BA + 0x100.\nNote2: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
0
2
read-write
0
Clock source is from HXT or LXT
#00
1
Reserved
#01
2
Clock source is from HCLK/2048 clock
#10
3
Clock source is from LIRC
#11
CLKSEL2
CLK_CLKSEL2
Clock Source Select Control Register 2
0x1C
-1
read-write
n
0x0
0x0
FREQSEL
Clock Divider Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
2
2
read-write
0
Clock source is from HXT or LXT
#00
1
Clock source is from LIRC
#01
2
Clock source is from HCLK
#10
3
Clock source is from HIRC
#11
PWMCH45SEL
PWM4 And PWM5 Clock Source Selection
PWM4 and PWM5 use the same peripheral clock source Both of them use the same prescaler.
4
2
read-write
0
Reserved
#00
1
Reserved
#01
2
Clock source is from HCLK
#10
3
Reserved
#11
WWDTSEL
Window Watchdog Timer Clock Source Selection\n
16
2
read-write
0
Reserved
#00
1
Reserved
#01
2
Clock source from HCLK/2048 clock
#10
3
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
#11
PLLCTL
CLK_PLLCTL
PLL Control Register
0x20
-1
read-write
n
0x0
0x0
BP
PLL Bypass Control\n
17
1
read-write
0
PLL is in Normal mode (default)
#0
1
PLL clock output is same as PLL source clock input
#1
FBDIV
PLL Feedback Divider Control\nRefer to the formulas below the table.
0
9
read-write
INDIV
PLL Input Divider Control\nRefer to the formulas below the table.
9
5
read-write
OE
PLL OE (FOUT Enable) Pin Control\n
18
1
read-write
0
PLL FOUT Enabled
#0
1
PLL FOUT is fixed low
#1
OUTDIV
PLL Output Divider Control\nRefer to the formulas below the table.
14
2
read-write
PD
Power-down Mode\nIf the PDEN bit is set to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode too.\n
16
1
read-write
0
PLL is in Normal mode
#0
1
PLL is in Power-down mode (default)
#1
PLLSRC
PLL Source Clock Selection\n
19
1
read-write
0
PLL source clock from HXT
#0
1
PLL source clock from HIRC
#1
PWRCTL
CLK_PWRCTL
System Power-down Control Register
0x0
-1
read-write
n
0x0
0x0
HIRCEN
HIRC Enable Bit (Write Protect)\nNote: The default of HIRCEN bit is 1.
2
1
read-write
0
22.1184 MHz internal high speed RC oscillator (HIRC) Disabled
#0
1
22.1184 MHz internal high speed RC oscillator (HIRC) Enabled
#1
LIRCEN
LIRC Enable Bit (Write Protect)\n
3
1
read-write
0
10 kHz internal low speed RC oscillator (LIRC) Disabled
#0
1
10 kHz internal low speed RC oscillator (LIRC) Enabled
#1
PDEN
System Power-down Enable Bit (Write Protect)\nWhen chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next Power-down.\nIn Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT), 32.768 kHz external low speed crystal oscillator (LXT), and the 22.1184 MHz internal high speed oscillator (HIRC) will be disabled in this mode, and 10 kHz internal low speed RC oscillator (LIRC) are not controlled by Power-down mode.\nIn Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from 10 kHz internal low speed oscillator.\n
7
1
read-write
0
Chip operating normally or chip in Idle mode because of WFI command
#0
1
Chip enters Power-down mode instantly or waits CPU sleep command WFI
#1
PDLXT
Enable LXT In Power-down Mode\nThis bit controls the crystal oscillator active or not in Power-down mode.\n
9
1
read-write
0
No effect to Power-down mode
#0
1
If XTLEN[1:0] = 10, LXT is still active in Power-down mode
#1
PDWKDLY
Wake-up Delay Counter Enable Bit (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz external high speed crystal (HXT), 4096 clock cycles for 32.768 kHz external low speed crystal (LXT), and 16 clock cycles when chip works at 22.1184 MHz internal high speed RC oscillator (HIRC).\n
4
1
read-write
0
Clock cycles delay Disabled
#0
1
Clock cycles delay Enabled
#1
PDWKIEN
Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote: The interrupt will occur when both PDWKIF and PDWKIEN are high.
5
1
read-write
0
Power-down mode wake-up interrupt Disabled
#0
1
Power-down mode wake-up interrupt Enabled
#1
PDWKIF
Power-down Mode Wake-up Interrupt Status
Set by Power-down wake-up event , which indicates that resume from Power-down mode
The flag is set if the GPIO, UART, WDT, ACMP, Timer or BOD wake-up occurred.
Note: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. Write 1 to clear the bit to 0.
6
1
read-write
XTLEN
External HXT Or LXT Crystal Oscillator Enable Bit (Write Protect)
The default clock source is from HIRC. These two bits are default set to 00 and the XT1_IN and XT1_OUT pins are GPIO.
Note: To enable external XTAL function, ALT[1:0] and MFP[1:0] bits must also be set in SYS_P5_MFP.
0
2
read-write
0
XT1_IN and XT1_OUT are GPIO, disable both LXT HXT (default)
#00
1
HXT Enabled
#01
2
LXT Enabled
#10
3
XT1_IN is external clock input pin, XT1_OUT is GPIO
#11
STATUS
CLK_STATUS
Clock Status Monitor Register
0xC
-1
read-write
n
0x0
0x0
CLKSFAIL
Clock Switch Fail Flag (Read Only)\nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote: This bit is read only. After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware.
7
1
read-only
0
Clock switching success
#0
1
Clock switching failure
#1
HIRCSTB
HIRC Clock Source Stable Flag (Read Only)\n
4
1
read-only
0
HIRC clock is not stable or disabled
#0
1
HIRC clock is stable and enabled
#1
LIRCSTB
LIRC Clock Source Stable Flag (Read Only)\n
3
1
read-only
0
LIRC clock is not stable or disabled
#0
1
LIRC clock is stable and enabled
#1
PLLSTB
Internal PLL Clock Source Stable Flag (Read Only)\n
2
1
read-only
0
Internal PLL clock is not stable or disabled
#0
1
Internal PLL clock is stable and enabled
#1
XTLSTB
HXT Or LXT Clock Source Stable Flag
0
1
read-write
0
HXT or LXT clock is not stable or disabled
#0
1
HXT or LXT clock is stable and enabled
#1
FMC
FMC Register Map
FMC
0x0
0x0
0x1C
registers
n
0x40
0x4
registers
n
DFBA
FMC_DFBA
Data Flash Base Address
0x14
read-only
n
0x0
0x0
DFBA
Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash is shared with APROM. the content of this register is loaded from CONFIG1\n
0
32
read-only
FATCTL
FMC_FATCTL
Flash Access Time Control Register
0x18
read-write
n
0x0
0x0
FOM
Frequency Optimization Mode (Write Protect)\nThe Mini58 series supports adjustable flash access timing to optimize the flash access cycles in different working frequency.\n
4
3
read-write
1
Frequency 24MHz
#001
ISPADDR
FMC_ISPADDR
ISP Address Register
0x4
read-write
n
0x0
0x0
ISPADDR
ISP Address\nThe Mini58 series is equipped with embedded flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. and ISPADR[8:0] must be kept all 0 for Vector Page Re-map Command\nFor CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation.
0
32
read-write
ISPCMD
FMC_ISPCMD
ISP Command Register
0xC
read-write
n
0x0
0x0
CMD
ISP CMD\nISP command table is shown below:\nThe other commands are invalid.
0
7
read-write
0
FLASH Read
0x00
4
Read Unique ID
0x04
11
Read Company ID
0x0b
12
Read Device ID
0x0c
13
Read CRC32 Checksum
0x0d
33
FLASH 32-bit Program
0x21
34
FLASH Page Erase
0x22
45
Run CRC32 Checksum Calculation
0x2d
46
Vector Remap
0x2e
ISPCTL
FMC_ISPCTL
ISP Control Register
0x0
read-write
n
0x0
0x0
APUEN
APROM Update Enable Bit (Write Protect)\n
3
1
read-write
0
APROM cannot be updated when the chip runs in APROM
#0
1
APROM can be updated when the chip runs in APROM
#1
BS
Boot Select (Write Protect)
Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened
1
1
read-write
0
Booting from APROM
#0
1
Booting from LDROM
#1
CFGUEN
CONFIG Update Enable Bit (Write Protect)\n
4
1
read-write
0
CONFIG cannot be updated
#0
1
CONFIG can be updated
#1
ISPEN
ISP Enable Bit (Write Protect)\nSet this bit to enable the ISP function.\n
0
1
read-write
0
ISP function Disabled
#0
1
ISP function Enabled
#1
ISPFF
ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) SPROM is erased/programmed if SPUEN is set to 0.\n(5) SPROM is programmed at SPROM secured mode.\n(6) Page Erase command at LOCK mode with ICE connection.\n(7) Erase or Program command at brown-out detected.\n(8) Destination address is illegal, such as over an available range.\n(9) Invalid ISP commands.
6
1
read-write
LDUEN
LDROM Update Enable (Write Protect)\nLDROM update enable bit.\n
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated
#1
SPUEN
SPROM Update Enable Bit (Write Protect)\n
2
1
read-write
0
SPROM cannot be updated
#0
1
SPROM can be updated
#1
ISPDAT
FMC_ISPDAT
ISP Data Register
0x8
read-write
n
0x0
0x0
ISPDAT
ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.\n
0
32
read-write
ISPSTS
FMC_ISPSTS
ISP Status Register
0x40
read-write
n
0x0
0x0
CBS
Boot Selection Of CONFIG (Read Only)
This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
1
2
read-only
0
LDROM with IAP mode
#00
1
LDROM without IAP mode
#01
2
APROM with IAP mode
#10
3
APROM without IAP mode
#11
ISPBUSY
ISP BUSY (Read Only)\n
0
1
read-only
0
ISP operation is finished
#0
1
ISP operation is busy
#1
ISPFF
ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) SPROM is erased/programmed if SPUEN is set to 0.\n(5) SPROM is programmed at SPROM secured mode.\n(6) Page Erase command at LOCK mode with ICE connection.\n(7) Erase or Program command at brown-out detected.\n(8) Destination address is illegal, such as over an available range.\n(9) Invalid ISP commands.
6
1
read-write
SCODE
Security Code Active Flag
This bit is set to 1 by hardware when detecting SPROM secured code is active at flash initialization, or software writes 1 to this bit to make secured code active this bit is only cleared by SPROM page erase operation.
31
1
read-write
0
SPROM secured code is inactive
#0
1
SPROM secured code is active
#1
VECMAP
Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}
9
12
read-only
ISPTRG
FMC_ISPTRG
ISP Trigger Control Register
0x10
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n
0
1
read-write
0
ISP operation is finished
#0
1
ISP is progressed
#1
GP
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
0x100
0x24
registers
n
0x140
0x24
registers
n
0x180
0x4
registers
n
0x200
0x8
registers
n
0x210
0x14
registers
n
0x228
0x10
registers
n
0x248
0x14
registers
n
0x260
0xC
registers
n
0x270
0xC
registers
n
0x298
0x20
registers
n
0x40
0x24
registers
n
0x80
0x24
registers
n
0xC0
0x24
registers
n
GPIO_DBCTL
GPIO_DBCTL
De-bounce Cycle Control
0x180
-1
read-write
n
0x0
0x0
DBCLKSEL
De-bounce Sampling Cycle Selection\n
0
4
read-write
0
Sample interrupt input once per 1 clock
#0000
1
Sample interrupt input once per 2 clocks
#0001
2
Sample interrupt input once per 4 clocks
#0010
3
Sample interrupt input once per 8 clocks
#0011
4
Sample interrupt input once per 16 clocks
#0100
5
Sample interrupt input once per 32 clocks
#0101
6
Sample interrupt input once per 64 clocks
#0110
7
Sample interrupt input once per 128 clocks
#0111
8
Sample interrupt input once per 256 clocks
#1000
9
Sample interrupt input once per 2*256 clocks
#1001
10
Sample interrupt input once per 4*256 clocks
#1010
11
Sample interrupt input once per 8*256 clocks
#1011
12
Sample interrupt input once per 16*256 clocks
#1100
13
Sample interrupt input once per 32*256 clocks
#1101
14
Sample interrupt input once per 64*256 clocks
#1110
15
Sample interrupt input once per 128*256 clocks
#1111
DBCLKSRC
De-bounce Counter Clock Source Selection\n
4
1
read-write
0
De-bounce counter clock source is HCLK
#0
1
De-bounce counter clock source is 10 kHz internal low speed RC oscillator (LIRC)
#1
ICLKON
Interrupt Clock On Mode\nNote: It is recommended to disable this bit to save system power if no special application concern.
5
1
read-write
0
Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1
#0
1
All I/O pins edge detection circuit is always active after reset
#1
P00_PDIO
P00_PDIO
GPIO P0.0 Pin Data Input/Output
0x200
-1
read-write
n
0x0
0x0
PDIO
GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n
0
1
read-write
0
Corresponding GPIO pin set to low
#0
1
Corresponding GPIO pin set to high
#1
P01_PDIO
P01_PDIO
GPIO P0.1 Pin Data Input/Output
0x204
read-write
n
0x0
0x0
P04_PDIO
P04_PDIO
GPIO P0.4 Pin Data Input/Output
0x210
read-write
n
0x0
0x0
P05_PDIO
P05_PDIO
GPIO P0.5 Pin Data Input/Output
0x214
read-write
n
0x0
0x0
P06_PDIO
P06_PDIO
GPIO P0.6 Pin Data Input/Output
0x218
read-write
n
0x0
0x0
P07_PDIO
P07_PDIO
GPIO P0.7 Pin Data Input/Output
0x21C
read-write
n
0x0
0x0
P0_DATMSK
P0_DATMSK
P0 Data Output Write Mask
0xC
read-write
n
0x0
0x0
DATMSK0
Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
0
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK1
Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
1
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK2
Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
2
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK3
Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
3
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK4
Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
4
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK5
Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
5
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK6
Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
6
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK7
Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
7
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
P0_DBEN
P0_DBEN
P0 De-bounce Enable Control
0x14
read-write
n
0x0
0x0
DBEN0
Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN1
Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
1
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN2
Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
2
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN3
Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
3
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN4
Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
4
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN5
Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
5
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN6
Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
6
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN7
Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
7
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
P0_DINOFF
P0_DINOFF
P0 Digital Input Path Disable Control
0x4
read-write
n
0x0
0x0
DINOFF0
Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
16
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF1
Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
17
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF2
Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
18
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF3
Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
19
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF4
Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
20
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF5
Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
21
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF6
Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
22
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF7
Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
23
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
P0_DOUT
P0_DOUT
P0 Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
0
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
1
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
2
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
3
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
4
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
5
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
6
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
7
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
P0_INTEN
P0_INTEN
P0 Interrupt Enable Control
0x1C
read-write
n
0x0
0x0
FLIEN0
Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
0
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN1
Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
1
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN2
Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
2
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN3
Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
3
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN4
Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
4
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN5
Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
5
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN6
Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
6
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN7
Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
7
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
RHIEN0
Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
16
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN1
Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
17
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN2
Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
18
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN3
Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
19
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN4
Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
20
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN5
Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
21
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN6
Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
22
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN7
Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
23
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
P0_INTSRC
P0_INTSRC
P0 Interrupt Source Flag
0x20
read-write
n
0x0
0x0
INTSRC0
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
0
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC1
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
1
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC10
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
10
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC11
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
11
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC12
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
12
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC13
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
13
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC14
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
14
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC15
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
15
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC2
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
2
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC3
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
3
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC4
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
4
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC5
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
5
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC6
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
6
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC7
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
7
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC8
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
8
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC9
Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
9
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
P0_INTTYPE
P0_INTTYPE
P0 Interrupt Mode Control
0x18
read-write
n
0x0
0x0
TYPE0
Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
0
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE1
Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
1
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE2
Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
2
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE3
Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
3
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE4
Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
4
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE5
Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
5
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE6
Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
6
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE7
Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
7
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
P0_MODE
P0_MODE
P0 I/O Mode Control
0x0
read-write
n
0x0
0x0
MODE0
Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
0
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE1
Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
2
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE2
Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
4
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE3
Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
6
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE4
Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
8
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE5
Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
10
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE6
Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
12
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE7
Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
14
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
P0_PIN
P0_PIN
P0 Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
0
1
read-only
PIN1
Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
1
1
read-only
PIN2
Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
2
1
read-only
PIN3
Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
3
1
read-only
PIN4
Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
4
1
read-only
PIN5
Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
5
1
read-only
PIN6
Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
6
1
read-only
PIN7
Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
7
1
read-only
P10_PDIO
P10_PDIO
GPIO P1.0 Pin Data Input/Output
0x220
read-write
n
0x0
0x0
P12_PDIO
P12_PDIO
GPIO P1.2 Pin Data Input/Output
0x228
read-write
n
0x0
0x0
P13_PDIO
P13_PDIO
GPIO P1.3 Pin Data Input/Output
0x22C
read-write
n
0x0
0x0
P14_PDIO
P14_PDIO
GPIO P1.4 Pin Data Input/Output
0x230
read-write
n
0x0
0x0
P15_PDIO
P15_PDIO
GPIO P1.5 Pin Data Input/Output
0x234
read-write
n
0x0
0x0
P1_DATMSK
P1_DATMSK
P1 Data Output Write Mask
0x4C
read-write
n
0x0
0x0
P1_DBEN
P1_DBEN
P1 De-bounce Enable Control
0x54
read-write
n
0x0
0x0
P1_DINOFF
P1_DINOFF
P1 Digital Input Path Disable Control
0x44
read-write
n
0x0
0x0
P1_DOUT
P1_DOUT
P1 Data Output Value
0x48
read-write
n
0x0
0x0
P1_INTEN
P1_INTEN
P1 Interrupt Enable Control
0x5C
read-write
n
0x0
0x0
P1_INTSRC
P1_INTSRC
P1 Interrupt Source Flag
0x60
read-write
n
0x0
0x0
P1_INTTYPE
P1_INTTYPE
P1 Interrupt Mode Control
0x58
read-write
n
0x0
0x0
P1_MODE
P1_MODE
P1 I/O Mode Control
0x40
read-write
n
0x0
0x0
P1_PIN
P1_PIN
P1 Pin Value
0x50
read-write
n
0x0
0x0
P22_PDIO
P22_PDIO
GPIO P2.2 Pin Data Input/Output
0x248
read-write
n
0x0
0x0
P23_PDIO
P23_PDIO
GPIO P2.3 Pin Data Input/Output
0x24C
read-write
n
0x0
0x0
P24_PDIO
P24_PDIO
GPIO P2.4 Pin Data Input/Output
0x250
read-write
n
0x0
0x0
P25_PDIO
P25_PDIO
GPIO P2.5 Pin Data Input/Output
0x254
read-write
n
0x0
0x0
P26_PDIO
P26_PDIO
GPIO P2.6 Pin Data Input/Output
0x258
read-write
n
0x0
0x0
P2_DATMSK
P2_DATMSK
P2 Data Output Write Mask
0x8C
read-write
n
0x0
0x0
P2_DBEN
P2_DBEN
P2 De-bounce Enable Control
0x94
read-write
n
0x0
0x0
P2_DINOFF
P2_DINOFF
P2 Digital Input Path Disable Control
0x84
read-write
n
0x0
0x0
P2_DOUT
P2_DOUT
P2 Data Output Value
0x88
read-write
n
0x0
0x0
P2_INTEN
P2_INTEN
P2 Interrupt Enable Control
0x9C
read-write
n
0x0
0x0
P2_INTSRC
P2_INTSRC
P2 Interrupt Source Flag
0xA0
read-write
n
0x0
0x0
P2_INTTYPE
P2_INTTYPE
P2 Interrupt Mode Control
0x98
read-write
n
0x0
0x0
P2_MODE
P2_MODE
P2 I/O Mode Control
0x80
read-write
n
0x0
0x0
P2_PIN
P2_PIN
P2 Pin Value
0x90
read-write
n
0x0
0x0
P30_PDIO
P30_PDIO
GPIO P3.0 Pin Data Input/Output
0x260
read-write
n
0x0
0x0
P31_PDIO
P31_PDIO
GPIO P3.1 Pin Data Input/Output
0x264
read-write
n
0x0
0x0
P32_PDIO
P32_PDIO
GPIO P3.2 Pin Data Input/Output
0x268
read-write
n
0x0
0x0
P34_PDIO
P34_PDIO
GPIO P3.4 Pin Data Input/Output
0x270
read-write
n
0x0
0x0
P35_PDIO
P35_PDIO
GPIO P3.5 Pin Data Input/Output
0x274
read-write
n
0x0
0x0
P36_PDIO
P36_PDIO
GPIO P3.6 Pin Data Input/Output
0x278
read-write
n
0x0
0x0
P3_DATMSK
P3_DATMSK
P3 Data Output Write Mask
0xCC
read-write
n
0x0
0x0
P3_DBEN
P3_DBEN
P3 De-bounce Enable Control
0xD4
read-write
n
0x0
0x0
P3_DINOFF
P3_DINOFF
P3 Digital Input Path Disable Control
0xC4
read-write
n
0x0
0x0
P3_DOUT
P3_DOUT
P3 Data Output Value
0xC8
read-write
n
0x0
0x0
P3_INTEN
P3_INTEN
P3 Interrupt Enable Control
0xDC
read-write
n
0x0
0x0
P3_INTSRC
P3_INTSRC
P3 Interrupt Source Flag
0xE0
read-write
n
0x0
0x0
P3_INTTYPE
P3_INTTYPE
P3 Interrupt Mode Control
0xD8
read-write
n
0x0
0x0
P3_MODE
P3_MODE
P3 I/O Mode Control
0xC0
read-write
n
0x0
0x0
P3_PIN
P3_PIN
P3 Pin Value
0xD0
read-write
n
0x0
0x0
P46_PDIO
P46_PDIO
GPIO P4.6 Pin Data Input/Output
0x298
read-write
n
0x0
0x0
P47_PDIO
P47_PDIO
GPIO P4.7 Pin Data Input/Output
0x29C
read-write
n
0x0
0x0
P4_DATMSK
P4_DATMSK
P4 Data Output Write Mask
0x10C
read-write
n
0x0
0x0
P4_DBEN
P4_DBEN
P4 De-bounce Enable Control
0x114
read-write
n
0x0
0x0
P4_DINOFF
P4_DINOFF
P4 Digital Input Path Disable Control
0x104
read-write
n
0x0
0x0
P4_DOUT
P4_DOUT
P4 Data Output Value
0x108
read-write
n
0x0
0x0
P4_INTEN
P4_INTEN
P4 Interrupt Enable Control
0x11C
read-write
n
0x0
0x0
P4_INTSRC
P4_INTSRC
P4 Interrupt Source Flag
0x120
read-write
n
0x0
0x0
P4_INTTYPE
P4_INTTYPE
P4 Interrupt Mode Control
0x118
read-write
n
0x0
0x0
P4_MODE
P4_MODE
P4 I/O Mode Control
0x100
read-write
n
0x0
0x0
P4_PIN
P4_PIN
P4 Pin Value
0x110
read-write
n
0x0
0x0
P50_PDIO
P50_PDIO
GPIO P5.0 Pin Data Input/Output
0x2A0
read-write
n
0x0
0x0
P51_PDIO
P51_PDIO
GPIO P5.1 Pin Data Input/Output
0x2A4
read-write
n
0x0
0x0
P52_PDIO
P52_PDIO
GPIO P5.2 Pin Data Input/Output
0x2A8
read-write
n
0x0
0x0
P53_PDIO
P53_PDIO
GPIO P5.3 Pin Data Input/Output
0x2AC
read-write
n
0x0
0x0
P54_PDIO
P54_PDIO
GPIO P5.4 Pin Data Input/Output
0x2B0
read-write
n
0x0
0x0
P55_PDIO
P55_PDIO
GPIO P5.5 Pin Data Input/Output
0x2B4
read-write
n
0x0
0x0
P5_DATMSK
P5_DATMSK
P5 Data Output Write Mask
0x14C
read-write
n
0x0
0x0
P5_DBEN
P5_DBEN
P5 De-bounce Enable Control
0x154
read-write
n
0x0
0x0
P5_DINOFF
P5_DINOFF
P5 Digital Input Path Disable Control
0x144
read-write
n
0x0
0x0
P5_DOUT
P5_DOUT
P5 Data Output Value
0x148
read-write
n
0x0
0x0
P5_INTEN
P5_INTEN
P5 Interrupt Enable Control
0x15C
read-write
n
0x0
0x0
P5_INTSRC
P5_INTSRC
P5 Interrupt Source Flag
0x160
read-write
n
0x0
0x0
P5_INTTYPE
P5_INTTYPE
P5 Interrupt Mode Control
0x158
read-write
n
0x0
0x0
P5_MODE
P5_MODE
P5 I/O Mode Control
0x140
read-write
n
0x0
0x0
P5_PIN
P5_PIN
P5 Pin Value
0x150
read-write
n
0x0
0x0
I2C0
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register 0
0x4
read-write
n
0x0
0x0
ADDR
I2C Address\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
GC
General Call Function Control\n
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register 1
0x18
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register 2
0x1C
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register 3
0x20
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register 0
0x24
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask Bits\n
1
7
read-write
0
I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register)
0
1
I2C address mask Enabled (the received corresponding address bit is Don't care )
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register 1
0x28
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register 2
0x2C
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register 3
0x30
read-write
n
0x0
0x0
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided Register\nNote: The minimum value of I2C_CLKDIV is 4.
0
8
read-write
I2C_CTL
I2C_CTL
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control Bit\n
2
1
read-write
I2CEN
I2C Controller Enable Bit\n
6
1
read-write
0
I2C Controller Disabled
#0
1
I2C Controller Enabled
#1
INTEN
Interrupt Enable Bit\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL[7]) is set, the I2C interrupt is requested. SI must be cleared by software. This bit can be cleared by software writing '1'.
3
1
read-write
STA
I2C START Control Bit\nSet STA to logic 1 to enter Master mode. I2C hardware sends a START or repeats the START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control Bit
In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the Slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2C_CTL1
I2C_CTL1
I2C Control Register 1
0x3C
read-write
n
0x0
0x0
NSTRETCH
No Stretch On The I2C Bus\n
2
1
read-write
0
The I2C SCL bus is stretched by hardware if the SI is not cleared in master mode
#0
1
The I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode
#1
OVIEN
I2C Overrun Interrupt Control\nSetting OVIEN to 1 will send a interrupt to system when the TWOLVFF bit is enabled and there is overrun event in received buffer.\n
3
1
read-write
0
Overrun Interrupt Disabled
#0
1
Overrun Interrupt Enabled
#1
TWOLVFIFO
Two-level Buffer Enable Bit\n
1
1
read-write
0
Two-level buffer Disabled
#0
1
Two-level buffer Enabled
#1
URIEN
I2C Under Run Interrupt Control\nSetting URIEN to 1 will send a interrupt to system when the TWOLVFF bit is enabled and there is under run event happened in transmitted buffer.\n
4
1
read-write
0
Under run Interrupt Disabled
#0
1
Under run Interrupt Enabled
#1
WKEN
Wake-up Enable Bit\nThe system can be woken up by I2C bus when the system is set into Power mode and the received data matched one of the addresses in Address Register.\nNote: Only I2C0 channel supports wake-up function. This bit is not valid on I2C1 channel.
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_DAT
I2C_DAT
I2C DATA Register
0x8
read-write
n
0x0
0x0
DAT
I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of the I2C serial port.
0
8
read-write
I2C_STATUS
I2C_STATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status Register\n
0
8
read-only
I2C_STATUS1
I2C_STATUS1
I2C Status Register 1
0x40
read-write
n
0x0
0x0
EMPTY
I2C Two-level Buffer Empty\n
2
1
read-write
FULL
I2C Two-level Buffer Full\n
1
1
read-write
OVIF
I2C Overrun Status\n
3
1
read-write
URIF
I2C Under Run Status\n
4
1
read-write
WKIF
I2C Wake-up Interrupt Flag
When chip is woken up from Power-down mode by I2C, this bit is set to 1. This bit can be cleared by software writing 1 .
Note: Only I2C0 channel supports wake-up function. This bit is not valid on I2C1 channel.
0
1
read-write
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
read-write
n
0x0
0x0
TOCEN
Time-out Counter Enable Bit\nNote: When the 14-bit time-out counter is enabled, it will start counting when SI is cleared. Setting 1 to the SI flag will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOCURIEN
Time-out Counter Input Clock Divided By 4
Note: When enabled, the time-out period is extended 4 times.
1
1
read-write
0
Time-out counter input clock divided by 4 Disabled
#0
1
Time-out counter input clock divided by 4 Enabled
#1
TOIF
Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: This bit can be cleared by software writing '1'.
0
1
read-write
I2C1
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register 0
0x4
read-write
n
0x0
0x0
ADDR
I2C Address\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
GC
General Call Function Control\n
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register 1
0x18
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register 2
0x1C
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register 3
0x20
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register 0
0x24
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask Bits\n
1
7
read-write
0
I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register)
0
1
I2C address mask Enabled (the received corresponding address bit is Don't care )
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register 1
0x28
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register 2
0x2C
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register 3
0x30
read-write
n
0x0
0x0
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided Register\nNote: The minimum value of I2C_CLKDIV is 4.
0
8
read-write
I2C_CTL
I2C_CTL
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control Bit\n
2
1
read-write
I2CEN
I2C Controller Enable Bit\n
6
1
read-write
0
I2C Controller Disabled
#0
1
I2C Controller Enabled
#1
INTEN
Interrupt Enable Bit\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL[7]) is set, the I2C interrupt is requested. SI must be cleared by software. This bit can be cleared by software writing '1'.
3
1
read-write
STA
I2C START Control Bit\nSet STA to logic 1 to enter Master mode. I2C hardware sends a START or repeats the START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control Bit
In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the Slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2C_CTL1
I2C_CTL1
I2C Control Register 1
0x3C
read-write
n
0x0
0x0
NSTRETCH
No Stretch On The I2C Bus\n
2
1
read-write
0
The I2C SCL bus is stretched by hardware if the SI is not cleared in master mode
#0
1
The I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode
#1
OVIEN
I2C Overrun Interrupt Control\nSetting OVIEN to 1 will send a interrupt to system when the TWOLVFF bit is enabled and there is overrun event in received buffer.\n
3
1
read-write
0
Overrun Interrupt Disabled
#0
1
Overrun Interrupt Enabled
#1
TWOLVFIFO
Two-level Buffer Enable Bit\n
1
1
read-write
0
Two-level buffer Disabled
#0
1
Two-level buffer Enabled
#1
URIEN
I2C Under Run Interrupt Control\nSetting URIEN to 1 will send a interrupt to system when the TWOLVFF bit is enabled and there is under run event happened in transmitted buffer.\n
4
1
read-write
0
Under run Interrupt Disabled
#0
1
Under run Interrupt Enabled
#1
WKEN
Wake-up Enable Bit\nThe system can be woken up by I2C bus when the system is set into Power mode and the received data matched one of the addresses in Address Register.\nNote: Only I2C0 channel supports wake-up function. This bit is not valid on I2C1 channel.
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_DAT
I2C_DAT
I2C DATA Register
0x8
read-write
n
0x0
0x0
DAT
I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of the I2C serial port.
0
8
read-write
I2C_STATUS
I2C_STATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status Register\n
0
8
read-only
I2C_STATUS1
I2C_STATUS1
I2C Status Register 1
0x40
read-write
n
0x0
0x0
EMPTY
I2C Two-level Buffer Empty\n
2
1
read-write
FULL
I2C Two-level Buffer Full\n
1
1
read-write
OVIF
I2C Overrun Status\n
3
1
read-write
URIF
I2C Under Run Status\n
4
1
read-write
WKIF
I2C Wake-up Interrupt Flag
When chip is woken up from Power-down mode by I2C, this bit is set to 1. This bit can be cleared by software writing 1 .
Note: Only I2C0 channel supports wake-up function. This bit is not valid on I2C1 channel.
0
1
read-write
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
read-write
n
0x0
0x0
TOCEN
Time-out Counter Enable Bit\nNote: When the 14-bit time-out counter is enabled, it will start counting when SI is cleared. Setting 1 to the SI flag will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOCURIEN
Time-out Counter Input Clock Divided By 4
Note: When enabled, the time-out period is extended 4 times.
1
1
read-write
0
Time-out counter input clock divided by 4 Disabled
#0
1
Time-out counter input clock divided by 4 Enabled
#1
TOIF
Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: This bit can be cleared by software writing '1'.
0
1
read-write
INT
INT Register Map
INT
0x0
0x0
0x88
registers
n
IRQ0_SRC
IRQ0_SRC
IRQ0 (BOD) Interrupt Source Identity
0x0
read-only
n
0x0
0x0
BOD_INT
IRQ0 Source Identity\n
0
1
read-only
0
IRQ0 source is not from BOD interrupt (BOD_INT)
#0
1
IRQ0 source is from BOD interrupt (BOD_INT)
#1
IRQ10_SRC
IRQ10_SRC
Reserved
0x28
read-write
n
0x0
0x0
IRQ11_SRC
IRQ11_SRC
Reserved
0x2C
read-write
n
0x0
0x0
IRQ12_SRC
IRQ12_SRC
IRQ12 (UART0) Interrupt Source Identity
0x30
read-only
n
0x0
0x0
UART0_INT
IRQ12 Source Identity\n
0
1
read-only
0
IRQ12 source is not from UART0 interrupt (UART0_INT)
#0
1
IRQ12 source is from UART0 interrupt (UART0_INT)
#1
IRQ13_SRC
IRQ13_SRC
IRQ13 (UART1) Interrupt Source Identity
0x34
read-only
n
0x0
0x0
UART1_INT
IRQ13 Source Identity\n
0
1
read-only
0
IRQ13 source is not from UART1 interrupt (UART1_INT)
#0
1
IRQ13 source is from UART1 interrupt (UART1_INT)
#1
IRQ14_SRC
IRQ14_SRC
IRQ14 (SPI) Interrupt Source Identity
0x38
read-only
n
0x0
0x0
SPI_INT
IRQ14 Source Identity\n
0
1
read-only
0
IRQ14 source is not from SPI interrupt (SPI_INT)
#0
1
IRQ14 source is from SPI interrupt (SPI_INT)
#1
IRQ15_SRC
IRQ15_SRC
Reserved
0x3C
read-write
n
0x0
0x0
IRQ16_SRC
IRQ16_SRC
IRQ16 (GP5) Interrupt Source Identity
0x40
read-only
n
0x0
0x0
GP5_INT
IRQ16 Source Identity\n
0
1
read-only
0
IRQ16 source is not from GP5 interrupt (GP5_INT)
#0
1
IRQ16 source is from GP5 interrupt (GP5_INT)
#1
IRQ17_SRC
IRQ17_SRC
IRQ17 (HIRC Trim) Interrupt Source Identity
0x44
read-only
n
0x0
0x0
HIRC_TRIM_INT
IRQ17 Source Identity\n
0
1
read-only
0
IRQ17 source is not from HIRC trim interrupt (HIRC_TRIM_INT)
#0
1
IRQ17 source is from HIRC trim interrupt (HIRC_TRIM_INT)
#1
IRQ18_SRC
IRQ18_SRC
IRQ18 (I2C0) Interrupt Source Identity
0x48
read-only
n
0x0
0x0
I2C0_INT
IRQ18 Source Identity\n
0
1
read-only
0
IRQ18 source is not from I2C0 interrupt (I2C0_INT)
#0
1
IRQ18 source is from I2C0 interrupt (I2C0_INT)
#1
IRQ19_SRC
IRQ19_SRC
IRQ19 (I2C1) Interrupt Source Identity
0x4C
read-only
n
0x0
0x0
I2C1_INT
IRQ19 Source Identity\n
0
1
read-only
0
IRQ19 source is not from I2C1 interrupt (I2C1_INT)
#0
1
IRQ19 source is from I2C1 interrupt (I2C1_INT)
#1
IRQ1_SRC
IRQ1_SRC
IRQ1 (WDT) Interrupt Source Identity
0x4
read-only
n
0x0
0x0
WDT_INT
IRQ1 Source Identity\n
0
1
read-only
0
IRQ1 source is not from watchdog interrupt (WDT _INT)
#0
1
IRQ1 source is from watchdog interrupt (WDT_INT)
#1
WWDT_INT
IRQ1 Source Identity\n
1
1
read-only
0
IRQ1 source is not from window watchdog interrupt (WWDT _INT)
#0
1
IRQ1 source is from window watchdog interrupt (WWDT_INT)
#1
IRQ20_SRC
IRQ20_SRC
Reserved
0x50
read-write
n
0x0
0x0
IRQ21_SRC
IRQ21_SRC
Reserved
0x54
read-write
n
0x0
0x0
IRQ22_SRC
IRQ22_SRC
Reserved
0x58
read-write
n
0x0
0x0
IRQ23_SRC
IRQ23_SRC
Reserved
0x5C
read-write
n
0x0
0x0
IRQ24_SRC
IRQ24_SRC
Reserved
0x60
read-write
n
0x0
0x0
IRQ25_SRC
IRQ25_SRC
IRQ25 (ACMP) Interrupt Source Identity
0x64
read-only
n
0x0
0x0
ACMP_INT
IRQ25 Source Identity\n
0
1
read-only
0
IRQ25 source is not from ACMP interrupt (ACMP_INT)
#0
1
IRQ25 source is from ACMP interrupt (ACMP_INT)
#1
IRQ26_SRC
IRQ26_SRC
Reserved
0x68
read-write
n
0x0
0x0
IRQ27_SRC
IRQ27_SRC
Reserved
0x6C
read-write
n
0x0
0x0
IRQ28_SRC
IRQ28_SRC
IRQ28 (PWRWU) Interrupt Source Identity
0x70
read-only
n
0x0
0x0
PWRWU_INT
IRQ28 Source Identity\n
0
1
read-only
0
IRQ28 source is not from PWRWU interrupt (PWRWU_INT)
#0
1
IRQ28 source is from PWREU interrupt (PWRWU_INT)
#1
IRQ29_SRC
IRQ29_SRC
IRQ29 (ADC) Interrupt Source Identity
0x74
read-only
n
0x0
0x0
ADC_INT
IRQ29 Source Identity \n
0
1
read-only
0
IRQ29 source is not from ADC interrupt (ADC_INT)
#0
1
IRQ29 source is from ADC interrupt (ADC_INT)
#1
IRQ2_SRC
IRQ2_SRC
IRQ2 (EINT0) Interrupt Source Identity
0x8
read-only
n
0x0
0x0
EINT0
IRQ2 Source Identity\n
0
1
read-only
0
IRQ2 source is not from external signal interrupt 0 from P3.2 (EINT0)
#0
1
IRQ2 source is from external signal interrupt 0 from P3.2 (EINT0)
#1
IRQ30_SRC
IRQ30_SRC
Reserved
0x78
read-write
n
0x0
0x0
IRQ31_SRC
IRQ31_SRC
Reserved
0x7C
read-write
n
0x0
0x0
IRQ3_SRC
IRQ3_SRC
IRQ3 (EINT1) Interrupt Source Identity
0xC
read-only
n
0x0
0x0
EINT1
IRQ3 Source Identity\n
0
1
read-only
0
IRQ3 source is not from external signal interrupt 1 from P5.2 (EINT1)
#0
1
IRQ3 source is from external signal interrupt 1 from P5.2 (EINT1)
#1
IRQ4_SRC
IRQ4_SRC
IRQ4 (GP0/1) Interrupt Source Identity
0x10
read-only
n
0x0
0x0
GP0_INT
IRQ4 Source Identity\n
0
1
read-only
0
IRQ4 source is not from GP0 interrupt (GP0_INT)
#0
1
IRQ4 source is from GP0 interrupt (GP0_INT)
#1
GP1_INT
IRQ4 Source Identity\n
1
1
read-only
0
IRQ4 source is not from GP1 interrupt (GP1_INT)
#0
1
IRQ4 source is from GP1 interrupt (GP1_INT)
#1
IRQ5_SRC
IRQ5_SRC
IRQ5 (GP2/3/4) Interrupt Source Identity
0x14
read-only
n
0x0
0x0
GP2_INT
IRQ5 Source Identity\n
0
1
read-only
0
IRQ5 source is not from GP2 interrupt (GP2_INT)
#0
1
IRQ5 source is from GP2 interrupt (GP2_INT)
#1
GP3_INT
IRQ5 Source Identity\n
1
1
read-only
0
IRQ5 source is not from GP3 interrupt (GP3_INT)
#0
1
IRQ5 source is from GP3 interrupt (GP3_INT)
#1
GP4_INT
IRQ5 Source Identity\n
2
1
read-only
0
IRQ5 source is not from GP4 interrupt (GP4_INT)
#0
1
IRQ5 source is from GP4 interrupt (GP4_INT)
#1
IRQ6_SRC
IRQ6_SRC
IRQ6 (PWM) Interrupt Source Identity
0x18
read-only
n
0x0
0x0
PWM_INT
IRQ6 Source Identity\n
0
1
read-only
0
IRQ6 source is not from PWM interrupt (PWM_INT)
#0
1
IRQ6 source is from PWM interrupt (PWM_INT)
#1
IRQ7_SRC
IRQ7_SRC
IRQ7 (BRAKE) Interrupt Source Identity
0x1C
read-only
n
0x0
0x0
BRAKE_INT
IRQ7 Source Identity \n
0
1
read-only
0
IRQ7 source is not from Brake interrupt (BRAKE_INT)
#0
1
IRQ7 source is from Brake interrupt (BRAKE_INT)
#1
IRQ8_SRC
IRQ8_SRC
IRQ8 (TMR0) Interrupt Source Identity
0x20
read-only
n
0x0
0x0
TMR0_INT
IRQ8 Source Identity \n
0
1
read-only
0
IRQ8 source is not from Timer0 interrupt (TMR0_INT)
#0
1
IRQ8 source is from Timer0 interrupt (TMR0_INT)
#1
IRQ9_SRC
IRQ9_SRC
IRQ9 (TMR1) Interrupt Source Identity
0x24
read-only
n
0x0
0x0
TMR1_INT
IRQ9 Source Identity \n
0
1
read-only
0
IRQ9 source is not from Timer1 interrupt (TMR1_INT)
#0
1
IRQ9 source is from Timer1 interrupt (TMR1_INT)
#1
MCU_IRQ
MCU_IRQ
MCU IRQ Number Identity Register
0x84
read-write
n
0x0
0x0
MCU_IRQ
MCU IRQ Source Bits\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. There are two modes to generate interrupt to Cortex-M0 - the normal mode and test mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0, setting MCU_IRQ[n] to 1 will generate an interrupt to Cortex-M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting MCU_IRQ[n] 0 has no effect.
0
32
read-write
NMI_CON
NMI_CON
NMI Source Interrupt Select Control Register
0x80
read-write
n
0x0
0x0
NMI_SEL
NMI Interrupt Source Select Bit\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL.
0
5
read-write
NMI_SEL_EN
NMI Interrupt Enable Bit (Write Protected)\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
8
1
read-write
0
NMI interrupt Disabled
#0
1
NMI interrupt Enabled
#1
PWM0
PWM0 Register Map
PWM0
0x0
0x0
0x3C
registers
n
0x54
0x3C
registers
n
PWM_ADCTCTL0
PWM_ADCTCTL0
PWM Trigger Control Register 0
0x68
read-write
n
0x0
0x0
CDTRGEN0
Channel 0 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel0's counter matching CMP0 in down-count direction\nNote: This bit is valid for both center-aligned type and edged-aligned type.
2
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CDTRGEN1
Channel 1 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel1's counter matching CMP1 in down-count direction\nNote: This bit is valid for both center-aligned type and edged-aligned type.
10
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CDTRGEN2
Channel 2 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel2's counter matching CMP2 in down-count direction\nNote: This bit is valid for both center-aligned type and edged-aligned type.
18
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CDTRGEN3
Channel 3 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel3's counter matching CMP3 in down-count direction\nNote: This bit is valid for both center-aligned type and edged aligned type.
26
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CPTRGEN0
Channel 0 Center Point Trigger ADC Enable Bit\nEnable PWM Trigger ADC Function While channel0's Counter Matching PERIOD0\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
1
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CPTRGEN1
Channel 1 Center Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel1's counter matching PERIOD1\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
9
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CPTRGEN2
Channel 2 Center Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel2's counter matching PERIOD2\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
17
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CPTRGEN3
Channel 3 Center Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel3's counter matching PERIOD3\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged aligned type, setting this bit is meaningless and will not take any effect.
25
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CUTRGEN0
Channel 0 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel0's counter matching CMP0 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
0
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CUTRGEN1
Channel 1 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel1's counter matching CMP1 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
8
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CUTRGEN2
Channel 2 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel2's counter matching CMP2 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
16
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CUTRGEN3
Channel 3 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel3's counter matching CMP3 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged aligned type, setting this bit is meaningless and will not take any effect.
24
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
ZPTRGEN0
Channel 0 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel0's counter matching 0\nNote: This bit is valid for both center-aligned type and edged-aligned type.
3
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
ZPTRGEN1
Channel 1 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function While channel1's Counter Matching 0 \nNote: This bit is valid for both center-aligned type and edged-aligned type.
11
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
ZPTRGEN2
Channel 2 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel2's counter matching 0\nNote: This bit is valid for both center-aligned type and edged-aligned type.
19
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
ZPTRGEN3
Channel 3 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel3's counter matching 0\nNote: This bit is valid for both center-aligned type and edged aligned type.
27
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
PWM_ADCTCTL1
PWM_ADCTCTL1
PWM Trigger Control Register 1
0x6C
read-write
n
0x0
0x0
CDTRGEN4
Channel 4 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel4's counter matching CMP4 in down-count direction\nNote: This bit is valid for both center-aligned type and edged-aligned type.
2
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CDTRGEN5
Channel 5 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel5's counter matching CMP5 in down-count direction\nNote: This bit is valid for both center-aligned type and edged-aligned type.
10
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CPTRGEN4
Channel 4 Center Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel4's counter matching PERIOD4\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
1
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CPTRGEN5
Channel 5 Center Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel5's counter matching PERIOD5\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
9
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CUTRGEN4
Channel 4 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel4's counter matching CMP4 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
0
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
CUTRGEN5
Channel 5 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel5's counter matching CMP5 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
8
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
ZPTRGEN4
Channel 4 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel4's counter matching 0\nNote: This bit is valid for both center-aligned type and edged-aligned type.
3
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
ZPTRGEN5
Channel 5 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel5's counter matching 0\nNote: This bit is valid for both center-aligned type and edged-aligned type.
11
1
read-write
0
PWM condition trigger ADC function Disabled
#0
1
PWM condition trigger ADC function Enabled
#1
PWM_ADCTSTS0
PWM_ADCTSTS0
PWM Trigger Status Register 0
0x70
read-write
n
0x0
0x0
CDTRGF0
Channel 0 Compare Down Trigger ADC Flag\nWhen the channel0's counter is counting down to CMP0, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
2
1
read-write
CDTRGF1
Channel 1 Compare Down Trigger ADC Flag\nWhen the channel1's counter is counting down to CMP1, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
10
1
read-write
CDTRGF2
Channel 2 Compare Down Trigger ADC Flag\nWhen the channel2's counter is counting down to CMP2, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
18
1
read-write
CDTRGF3
Channel 3 Compare Down Trigger ADC Flag\nWhen the channel3's counter is counting down to CMP3, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
26
1
read-write
CPTRGF0
Channel 0 Center Point Trigger ADC Flag\nWhen the channel0's counter is counting to PERIOD0, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
1
1
read-write
CPTRGF1
Channel 1 Center Point Trigger ADC Flag\nWhen the channel1's counter is counting to PERIOD1, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
9
1
read-write
CPTRGF2
Channel 2 Center Point Trigger ADC Flag\nWhen the channel2's counter is counting to PERIOD2, this bit will be set for trigger ADC. Note: This bit can be cleared by software writing 1.
17
1
read-write
CPTRGF3
Channel 3 Center Point Trigger ADC Flag\nWhen the channel3's counter is counting to PERIOD3, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
25
1
read-write
CUTRGF0
Channel 0 Compare Up Trigger ADC Flag\nWhen the channel0's counter is counting up to CMP0, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
0
1
read-write
CUTRGF1
Channel 1 Compare Up Trigger ADC Flag\nWhen the channel1's counter is counting up to CMP1, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
8
1
read-write
CUTRGF2
Channel 2 Compare Up Trigger ADC Flag\nWhen the channel2's counter is counting up to CMP2, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
16
1
read-write
CUTRGF3
Channel 3 Compare Up Trigger ADC Flag\nWhen the channel3's counter is counting up to CMP3, this bit will be set for trigger ADC.\nNote: This bit can be cleared by software writing 1.
24
1
read-write
ZPTRGF0
Channel 0 Zero Point Trigger ADC Flag\nWhen the channel0's counter is counting to zero point, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
3
1
read-write
ZPTRGF1
Channel 1 Zero Point Trigger ADC Flag\nWhen the channel1's counter is counting to zero point, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
11
1
read-write
ZPTRGF2
Channel 2 Zero Point Trigger ADC Enable Bit\nWhen the channel2's counter is counting to zero point, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
19
1
read-write
ZPTRGF3
Channel 3 Zero Point Trigger ADC Flag\nWhen the channel3's counter is counting to zero point, this bit will be set for trigger ADC.\nNote: This bit can be cleared by software writing 1.
27
1
read-write
PWM_ADCTSTS1
PWM_ADCTSTS1
PWM Trigger Status Register 1
0x74
read-write
n
0x0
0x0
CDTRGF4
Channel 4 Compare Down Trigger ADC Flag\nWhen the channel4's counter is counting down to CMP4, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
2
1
read-write
CDTRGF5
Channel 5 Compare Down Trigger ADC Flag\nWhen the channel5's counter is counting down to CMP5, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
10
1
read-write
CPTRGF4
Channel 4 Center Point Trigger ADC Flag\nWhen the channel4's counter is counting to PERIOD4, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
1
1
read-write
CPTRGF5
Channel 5 Center Point Trigger ADC Flag\nWhen the channel5's counter is counting to PERIOD5, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
9
1
read-write
CUTRGF4
Channel 4 Compare Up Trigger ADC Flag
When the channel4's counter is counting up to CMP4, this bit will be set for trigger ADC. Note: This bit can be cleared by software writing 1.
0
1
read-write
CUTRGF5
Channel 5 Compare Up Trigger ADC Flag\nWhen the channel5's counter is counting up to CMP5, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
8
1
read-write
ZPTRGF4
Channel 4 Zero Point Trigger ADC Flag\nWhen the channel4's counter is counting to zero point, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
3
1
read-write
ZPTRGF5
Channel 5 Zero Point Trigger ADC Flag\nWhen the channel5's counter is counting to zero point, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
11
1
read-write
PWM_BRKCTL
PWM_BRKCTL
PWM Fault Brake Control Register
0x60
read-write
n
0x0
0x0
BKOD0
PWM Brake Output Data Select Bits\n
24
1
read-write
0
PWM channel n output low when fault brake conditions asserted
#0
1
PWM channel n output high when fault brake conditions asserted
#1
BKOD1
PWM Brake Output Data Select Bits\n
25
1
read-write
0
PWM channel n output low when fault brake conditions asserted
#0
1
PWM channel n output high when fault brake conditions asserted
#1
BKOD2
PWM Brake Output Data Select Bits\n
26
1
read-write
0
PWM channel n output low when fault brake conditions asserted
#0
1
PWM channel n output high when fault brake conditions asserted
#1
BKOD3
PWM Brake Output Data Select Bits\n
27
1
read-write
0
PWM channel n output low when fault brake conditions asserted
#0
1
PWM channel n output high when fault brake conditions asserted
#1
BKOD4
PWM Brake Output Data Select Bits\n
28
1
read-write
0
PWM channel n output low when fault brake conditions asserted
#0
1
PWM channel n output high when fault brake conditions asserted
#1
BKOD5
PWM Brake Output Data Select Bits\n
29
1
read-write
0
PWM channel n output low when fault brake conditions asserted
#0
1
PWM channel n output high when fault brake conditions asserted
#1
BRK0EN
Enable BKP0 Pin Trigger Fault Brake Function 0\n
0
1
read-write
0
Disabling BKP0 pin can trigger brake function 0 (EINT0 or CPO1)
#0
1
Enabling a falling at BKP0 pin can trigger brake function 0
#1
BRK0SEL
BKP1 Fault Brake Function Source Select Bit\n
2
1
read-write
0
EINT1 as one brake source in BKP1
#0
1
CPO0 as one brake source in BKP1
#1
BRK1EN
Enable BKP1 Pin Trigger Fault Brake Function 1\n
1
1
read-write
0
Disabling BKP1 pin can trigger brake function 1 (EINT1 or CPO0)
#0
1
Enabling a falling at BKP1 pin can trigger brake function 1
#1
BRK1SEL
BKP0 Fault Brake Function Source Select Bit\n
3
1
read-write
0
EINT0 as one brake source in BKP0
#0
1
CPO1 as one brake source in BKP0
#1
BRKACT
PWM Brake Action Type\n
8
1
read-write
0
PWM counter stop when brake is asserted
#0
1
PWM counter keep going when brake is asserted
#1
BRKSTS
PWM Fault Brake Event Status Flag\nNote: This bit can be cleared by software writing 1 and must be cleared before restarting the PWM counter.
7
1
read-write
0
PWM output initial state when fault brake conditions asserted
#0
1
PWM output fault brake state when fault brake conditions asserted
#1
D6BKOD
Channel 6 Brake Output Data Select Bit\n
30
1
read-write
0
Channel 6 output low when fault brake conditions asserted
#0
1
Channel 6 output high when fault brake conditions asserted
#1
D7BKOD
Channel 7 Brake Output Data Select Bit\n
31
1
read-write
0
Channel 7 output low when fault brake conditions asserted
#0
1
Channel 7 output high when fault brake conditions asserted
#1
SWBRK
Software Brake\n
9
1
read-write
0
Disable PWM Software brake and back to normal PWM function
#0
1
Assert PWM Brake immediately
#1
PWM_CLKDIV
PWM_CLKDIV
PWM Clock Select Register
0x4
read-write
n
0x0
0x0
CLKDIV0
Counter 0 Clock Divider Selection\nSelect clock input for PWM counter.\n
0
3
read-write
0
Clock input / (CLKPSC01/2)
#000
1
Clock input / (CLKPSC01/4)
#001
2
Clock input / (CLKPSC01/8)
#010
3
Clock input / (CLKPSC01/16)
#011
4
Clock input / CLKPSC01
#100
CLKDIV1
Counter 1 Clock Divider Selection\nSelect clock input for PWM counter.\n
4
3
read-write
0
Clock input / (CLKPSC01/2)
#000
1
Clock input / (CLKPSC01/4)
#001
2
Clock input / (CLKPSC01/8)
#010
3
Clock input / (CLKPSC01/16)
#011
4
Clock input / CLKPSC01
#100
CLKDIV2
Counter 2 Clock Divider Selection\nSelect clock input for PWM counter.\n
8
3
read-write
0
Clock input / (CLKPSC23/2)
#000
1
Clock input / (CLKPSC23/4)
#001
2
Clock input / (CLKPSC23/8)
#010
3
Clock input / (CLKPSC23/16)
#011
4
Clock input / CLKPSC23
#100
CLKDIV3
Counter 3 Clock Divider Selection\nSelect clock input for PWM counter.\n
12
3
read-write
0
Clock input / (CLKPSC23/2)
#000
1
Clock input / (CLKPSC23/4)
#001
2
Clock input / (CLKPSC23/8)
#010
3
Clock input / (CLKPSC23/16)
#011
4
Clock input / CLKPSC23
#100
CLKDIV4
Counter 4 Clock Divider Selection\nSelect clock input for PWM counter.\n
16
3
read-write
0
Clock input / (CLKPSC45/2)
#000
1
Clock input / (CLKPSC45/4)
#001
2
Clock input / (CLKPSC45/8)
#010
3
Clock input / (CLKPSC45/16)
#011
4
Clock input / CLKPSC45
#100
CLKDIV5
Counter 5 Clock Divider Selection\nSelect clock input for PWM counter.\n
20
3
read-write
0
Clock input / (CLKPSC45/2)
#000
1
Clock input / (CLKPSC45/4)
#001
2
Clock input / (CLKPSC45/8)
#010
3
Clock input / (CLKPSC45/16)
#011
4
Clock input / CLKPSC45
#100
PWM_CLKPSC
PWM_CLKPSC
PWM Clock Pre-scale Register
0x0
read-write
n
0x0
0x0
CLKPSC01
Clock Prescaler 0 For PWM Counter 0 And 1\nClock input is divided by (CLKPSC01 + 1) before it is fed to the corresponding PWM counter.\n
0
8
read-write
CLKPSC23
Clock Prescaler 2 For PWM Counter 2 And 3\nClock input is divided by (CLKPSC23 + 1) before it is fed to the corresponding PWM counter.\n
8
8
read-write
CLKPSC45
Clock Prescaler 4 For PWM Counter 4 And 5\nClock input is divided by (CLKPSC45 + 1) before it is fed to the corresponding PWM counter.\n
16
8
read-write
PWM_CMPDAT0
PWM_CMPDAT0
PWM Comparator Register 0
0x24
read-write
n
0x0
0x0
CMPDn
PWM Comparator Register For Down Counter In Asymmetric Mode\nOthers: PWM output is always high.
16
16
read-write
CMPn
PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned type:\nNote: Any write to CMPn will take effect in the next PWM cycle.
0
16
read-write
PWM_CMPDAT1
PWM_CMPDAT1
PWM Comparator Register 1
0x28
read-write
n
0x0
0x0
PWM_CMPDAT2
PWM_CMPDAT2
PWM Comparator Register 2
0x2C
read-write
n
0x0
0x0
PWM_CMPDAT3
PWM_CMPDAT3
PWM Comparator Register 3
0x30
read-write
n
0x0
0x0
PWM_CMPDAT4
PWM_CMPDAT4
PWM Comparator Register 4
0x34
read-write
n
0x0
0x0
PWM_CMPDAT5
PWM_CMPDAT5
PWM Comparator Register 5
0x38
read-write
n
0x0
0x0
PWM_CTL
PWM_CTL
PWM Control Register
0x8
read-write
n
0x0
0x0
ASYMEN
Asymmetric Mode In Center-aligned Type \n
21
1
read-write
0
Symmetric mode in center-aligned type
#0
1
Asymmetric mode in center-aligned type
#1
CNTCLR
Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware.
27
1
read-write
0
Do not clear PWM counter
#0
1
All 16-bit PWM counters cleared to 0x0000
#1
CNTEN0
PWM Counter 0 Enable Start Run\n
0
1
read-write
0
Corresponding PWM counter running Stopped
#0
1
Corresponding PWM counter start run Enabled
#1
CNTEN1
PWM Counter 1 Enable/Disable Start Run\n
4
1
read-write
0
Corresponding PWM counter running Stopped
#0
1
Corresponding PWM counter start run Enabled
#1
CNTEN2
PWM Counter 2 Enable Start Run\n
8
1
read-write
0
Corresponding PWM counter running Stopped
#0
1
Corresponding PWM counter start run Enabled
#1
CNTEN3
PWM Counter 3 Enable Start Run\n
12
1
read-write
0
Corresponding PWM counter running Stopped
#0
1
Corresponding PWM counter start run Enabled
#1
CNTEN4
PWM Counter 4 Enable Start Run\n
16
1
read-write
0
Corresponding PWM counter running Stopped
#0
1
Corresponding PWM counter start run Enabled
#1
CNTEN5
PWM Counter 5 Enable Start Run\n
20
1
read-write
0
Corresponding PWM counter running Stopped
#0
1
Corresponding PWM counter start run Enabled
#1
CNTMODE0
PWM Counter 0 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PERIOD0 and CMP0 cleared.
3
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CNTMODE1
PWM Counter 1 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PERIOD1 and CMP1 cleared.
7
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CNTMODE2
PWM Counter 2 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PERIOD2 and CMP2 cleared.
11
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CNTMODE3
PWM Counter 3 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PERIOD3 and CMP3 cleared.
15
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CNTMODE4
PWM Counter 4 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PERIOD4 and CMP4 cleared.
19
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CNTMODE5
PWM Counter 5 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PERIOD5 and CMP5 cleared.
23
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CNTTYPE
PWM Counter-aligned Type Select Bit\n
31
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
DBGTRIOFF
Disable PWM Output Tri-state Under Debug Mode (Available In DEBUG Mode Only)\n
1
1
read-write
0
Safe mode: The counter is frozen and PWM outputs are shut down Safe state for the inverter. The counter can still be re-started from where it stops
#0
1
Normal mode: The counter continues to operate normally May be dangerous in some cases since a constant duty cycle is applied to the inverter (no more interrupts serviced)
#1
DTCNT01
Dead-time 0 Counter Enable Bit (PWM0_CH0 And PWM0_CH1 Pair For PWMA Group)\nNote: When the dead-time generator is enabled, the pair of PWM0_CH0 and PWM0_CH1 becomes a complementary pair for PWMA group.
24
1
read-write
0
Dead-time 0 generator Disabled
#0
1
Dead-time 0 generator Enabled
#1
DTCNT23
Dead-time 2 Counter Enable Bit (PWM0_CH2 And PWM0_CH3 Pair For PWMB Group)\nNote: When the dead-time generator is enabled, the pair of PWM0_CH2 and PWM0_CH3 becomes a complementary pair for PWMB group.
25
1
read-write
0
Dead-time 2 generator Disabled
#0
1
Dead-time 2 generator Enabled
#1
DTCNT45
Dead-time 4 Counter Enable Bit (PWM0_CH4 And PWM0_CH5 Pair For PWMC Group)\nNote: When the dead-time generator is enabled, the pair of PWM0_CH4 and PWM0_CH5 becomes a complementary pair for PWMC group.
26
1
read-write
0
Dead-time 4 generator Disabled
#0
1
Dead-time 4 generator Enabled
#1
GROUPEN
Group Function Enable Bit\n
30
1
read-write
0
The signals timing of all PWM channels are independent
#0
1
Unify the signals timing of PWM0_CH0, PWM0_CH2 and PWM0_CH4 in the same phase which is controlled by PWM0_CH0 and also unify the signals timing of PWM0_CH1, PWM0_CH3 and PWM0_CH5 in the same phase which is controlled by PWM0_CH1
#1
HCUPDT
Half Cycle Update Enable for Center-aligned Type\n
5
1
read-write
0
Disable half cycle update PERIOD CMP
#0
1
Enable half cycle update PERIOD CMP
#1
MODE
PWM Operating Mode Select Bit\n
28
2
read-write
0
Independent mode
#00
1
Complementary mode
#01
2
Synchronized mode
#10
3
Reserved
#11
PINV0
PWM0_CH0 Output Inverter Enable Bit\n
2
1
read-write
0
PWM0_CH0 output inverter Disabled
#0
1
PWM0_CH0 output inverter Enabled
#1
PINV1
PWM0_CH1 Output Inverter Enable Bit\n
6
1
read-write
0
PWM0_CH1 output inverter Disable
#0
1
PWM0_CH1 output inverter Enable
#1
PINV2
PWM0_CH2 Output Inverter Enable Bit\n
10
1
read-write
0
PWM0_CH2 output inverter Disabled
#0
1
PWM0_CH2 output inverter Enabled
#1
PINV3
PWM0_CH 3 Output Inverter Enable Bit\n
14
1
read-write
0
PWM0_CH3 output inverter Disabled
#0
1
PWM0_CH3 output inverter Enabled
#1
PINV4
PWM0_CH4 Output Inverter Enable Bit\n
18
1
read-write
0
PWM0_CH4 output inverter Disabled
#0
1
PWM0_CH4 output inverter Enabled
#1
PINV5
PWM0_CH5 Output Inverter Enable Bit\n
22
1
read-write
0
PWM0_CH5 output inverter Disabled
#0
1
PWM0_CH5 output inverter Enabled
#1
PWM_DTCTL
PWM_DTCTL
PWM Dead-time Control Register
0x64
read-write
n
0x0
0x0
DTI01
Dead-time Interval Register For Pair Of Channel0 And Channel1 (PWM0_CH0 And PWM0_CH1 Pair)\nThese 8 bits determine dead-time length.\nThe unit time of dead-time length is received from corresponding PWM_CLKDIV bits.
0
8
read-write
DTI23
Dead-time Interval Register For Pair Of Channel2 And Channel3 (PWM0_CH2 And PWM0_CH3 Pair)\nThese 8 bits determine dead-time length.\nThe unit time of dead-time length is received from corresponding PWM_CLKDIV bits.
8
8
read-write
DTI45
Dead-time Interval Register For Pair Of Channel4 And Channel5 (PWM0_CH4 And PWM0_CH5 Pair)\nThese 8 bits determine dead-time length.\nThe unit time of dead-time length is received from corresponding PWM_CLKDIV bits.
16
8
read-write
PWM_IFA
PWM_IFA
PWM Period Interrupt Accumulation Control Register
0x84
-1
read-write
n
0x0
0x0
IFAEN
Interrupt Accumulation Function Enable Bit\n
0
1
read-write
0
Interrupt accumulation function Disabled
#0
1
Interrupt accumulation function Enabled
#1
IFCNT
Interrupt Accumulation Counter \nWhen IFAEN is set, IFCNT will decrease when every ZIFn flag is set and when IFCNT reach to zero, the PWMn interrupt will occurred and IFCNT will reload itself.
4
4
read-write
PWM_INTEN
PWM_INTEN
PWM Interrupt Enable Register
0x54
read-write
n
0x0
0x0
BRKIEN
Fault Brake0 And Fault Brake1 Interrupt Enable Bit\n
16
1
read-write
0
BRKIF0 and BRKIF1 trigger PWM interrupt Disabled
#0
1
BRKIF0 and BRKIF1 trigger PWM interrupt Enabled
#1
CMPDIEN0
PWM Compare Down Interrupt Enable Bit\n
8
1
read-write
0
PWM0_CHn compare down interrupt Disabled
#0
1
PWM0_CHn compare down interrupt Enabled
#1
CMPDIEN1
PWM Compare Down Interrupt Enable Bit\n
9
1
read-write
0
PWM0_CHn compare down interrupt Disabled
#0
1
PWM0_CHn compare down interrupt Enabled
#1
CMPDIEN2
PWM Compare Down Interrupt Enable Bit\n
10
1
read-write
0
PWM0_CHn compare down interrupt Disabled
#0
1
PWM0_CHn compare down interrupt Enabled
#1
CMPDIEN3
PWM Compare Down Interrupt Enable Bit\n
11
1
read-write
0
PWM0_CHn compare down interrupt Disabled
#0
1
PWM0_CHn compare down interrupt Enabled
#1
CMPDIEN4
PWM Compare Down Interrupt Enable Bit\n
12
1
read-write
0
PWM0_CHn compare down interrupt Disabled
#0
1
PWM0_CHn compare down interrupt Enabled
#1
CMPDIEN5
PWM Compare Down Interrupt Enable Bit\n
13
1
read-write
0
PWM0_CHn compare down interrupt Disabled
#0
1
PWM0_CHn compare down interrupt Enabled
#1
CMPUIEN0
PWM Compare Up Interrupt Enable Bit\n
24
1
read-write
0
PWM0_CHn compare up interrupt Disabled
#0
1
PWM0_CHn compare up interrupt Enabled
#1
CMPUIEN1
PWM Compare Up Interrupt Enable Bit\n
25
1
read-write
0
PWM0_CHn compare up interrupt Disabled
#0
1
PWM0_CHn compare up interrupt Enabled
#1
CMPUIEN2
PWM Compare Up Interrupt Enable Bit\n
26
1
read-write
0
PWM0_CHn compare up interrupt Disabled
#0
1
PWM0_CHn compare up interrupt Enabled
#1
CMPUIEN3
PWM Compare Up Interrupt Enable Bit\n
27
1
read-write
0
PWM0_CHn compare up interrupt Disabled
#0
1
PWM0_CHn compare up interrupt Enabled
#1
CMPUIEN4
PWM Compare Up Interrupt Enable Bit\n
28
1
read-write
0
PWM0_CHn compare up interrupt Disabled
#0
1
PWM0_CHn compare up interrupt Enabled
#1
CMPUIEN5
PWM Compare Up Interrupt Enable Bit\n
29
1
read-write
0
PWM0_CHn compare up interrupt Disabled
#0
1
PWM0_CHn compare up interrupt Enabled
#1
PIEN0
PWM Period Interrupt Enable Bit\n
18
1
read-write
0
PWM0_CHn period interrupt Disabled
#0
1
PWM0_CHn period interrupt Enabled
#1
PIEN1
PWM Period Interrupt Enable Bit\n
19
1
read-write
0
PWM0_CHn period interrupt Disabled
#0
1
PWM0_CHn period interrupt Enabled
#1
PIEN2
PWM Period Interrupt Enable Bit\n
20
1
read-write
0
PWM0_CHn period interrupt Disabled
#0
1
PWM0_CHn period interrupt Enabled
#1
PIEN3
PWM Period Interrupt Enable Bit\n
21
1
read-write
0
PWM0_CHn period interrupt Disabled
#0
1
PWM0_CHn period interrupt Enabled
#1
PIEN4
PWM Period Interrupt Enable Bit\n
22
1
read-write
0
PWM0_CHn period interrupt Disabled
#0
1
PWM0_CHn period interrupt Enabled
#1
PIEN5
PWM Period Interrupt Enable Bit\n
23
1
read-write
0
PWM0_CHn period interrupt Disabled
#0
1
PWM0_CHn period interrupt Enabled
#1
PINTTYPE
PWM Interrupt Type Selection\nNote: This bit is effective when PWM is in center-aligned type only.
17
1
read-write
0
ZIFn will be set if PWM counter underflows
#0
1
ZIFn will be set if PWM counter matches PERIODn register
#1
ZIEN0
PWM Zero Point Interrupt Enable Bit\n
0
1
read-write
0
PWM0_CHn zero point interrupt Disabled
#0
1
PWM0_CHn zero point interrupt Enabled
#1
ZIEN1
PWM Zero Point Interrupt Enable Bit\n
1
1
read-write
0
PWM0_CHn zero point interrupt Disabled
#0
1
PWM0_CHn zero point interrupt Enabled
#1
ZIEN2
PWM Zero Point Interrupt Enable Bit\n
2
1
read-write
0
PWM0_CHn zero point interrupt Disabled
#0
1
PWM0_CHn zero point interrupt Enabled
#1
ZIEN3
PWM Zero Point Interrupt Enable Bit\n
3
1
read-write
0
PWM0_CHn zero point interrupt Disabled
#0
1
PWM0_CHn zero point interrupt Enabled
#1
ZIEN4
PWM Zero Point Interrupt Enable Bit\n
4
1
read-write
0
PWM0_CHn zero point interrupt Disabled
#0
1
PWM0_CHn zero point interrupt Enabled
#1
ZIEN5
PWM Zero Point Interrupt Enable Bit\n
5
1
read-write
0
PWM0_CHn zero point interrupt Disabled
#0
1
PWM0_CHn zero point interrupt Enabled
#1
PWM_INTSTS
PWM_INTSTS
PWM Interrupt Status Register
0x58
read-write
n
0x0
0x0
BRKIF0
PWM Brake0 Flag\nNote: This bit can be cleared by software writing 1.
16
1
read-write
0
PWM Brake does not recognize a falling signal at BKP0
#0
1
When PWM Brake detects a falling signal at pin BKP0 this flag will be set to high
#1
BRKIF1
PWM Brake1 Flag\nNote: This bit can be cleared by software writing 1.
17
1
read-write
0
PWM Brake does not recognize a falling signal at BKP1
#0
1
When PWM Brake detects a falling signal at pin BKP1 this flag will be set to high
#1
CMPDIF0
PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1.
8
1
read-write
CMPDIF1
PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1.
9
1
read-write
CMPDIF2
PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1.
10
1
read-write
CMPDIF3
PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1.
11
1
read-write
CMPDIF4
PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1.
12
1
read-write
CMPDIF5
PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1.
13
1
read-write
CMPUIF0
PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1.
24
1
read-write
CMPUIF1
PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1.
25
1
read-write
CMPUIF2
PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1.
26
1
read-write
CMPUIF3
PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1.
27
1
read-write
CMPUIF4
PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1.
28
1
read-write
CMPUIF5
PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1.
29
1
read-write
PIF0
PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1.
18
1
read-write
PIF1
PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1.
19
1
read-write
PIF2
PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1.
20
1
read-write
PIF3
PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1.
21
1
read-write
PIF4
PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1.
22
1
read-write
PIF5
PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1.
23
1
read-write
ZIF0
PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1.
0
1
read-write
ZIF1
PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1.
1
1
read-write
ZIF2
PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1.
2
1
read-write
ZIF3
PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1.
3
1
read-write
ZIF4
PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1.
4
1
read-write
ZIF5
PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1.
5
1
read-write
PWM_MSKALIGN
PWM_MSKALIGN
PWM Phase Change Mask Aligned Register
0x8C
-1
read-write
n
0x0
0x0
ALIGNn
PWM0_CHn Output Mask Aligned Enable Bit\n
16
6
read-write
0
PWM0_CHn output will mask immediately when mask function enabled
0
1
PWM0_CHn output will mask when output aligned to PWM period
1
MSKDAT0
PWM0_CHn Mask Data\nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
0
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT1
PWM0_CHn Mask Data\nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
1
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT2
PWM0_CHn Mask Data\nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
2
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT3
PWM0_CHn Mask Data\nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
3
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT4
PWM0_CHn Mask Data\nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
4
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT5
PWM0_CHn Mask Data\nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
5
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKEN0
PWM Output Mask Enable Bits\n
8
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
MSKEN1
PWM Output Mask Enable Bits\n
9
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
MSKEN2
PWM Output Mask Enable Bits\n
10
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
MSKEN3
PWM Output Mask Enable Bits\n
11
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
MSKEN4
PWM Output Mask Enable Bits\n
12
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
MSKEN5
PWM Output Mask Enable Bits\n
13
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
PWM_PCACTL
PWM_PCACTL
PWM Precise Center-aligned Type Control Register
0x88
read-write
n
0x0
0x0
PCAEN
PWM Precise Center-aligned Type Enable Bit\n
0
1
read-write
0
Precise center-aligned type Disabled
#0
1
Precise center-aligned type Enabled
#1
PWM_PERIOD0
PWM_PERIOD0
PWM Counter Period Register 0
0xC
read-write
n
0x0
0x0
PERIODn
PWM Counter Period Value\nPERIODn determines the PWM counter period.\nEdge-aligned type:\nNote: Any write to PERIODn will take effect in the next PWM cycle.
0
16
read-write
PWM_PERIOD1
PWM_PERIOD1
PWM Counter Period Register 1
0x10
read-write
n
0x0
0x0
PWM_PERIOD2
PWM_PERIOD2
PWM Counter Period Register 2
0x14
read-write
n
0x0
0x0
PWM_PERIOD3
PWM_PERIOD3
PWM Counter Period Register 3
0x18
read-write
n
0x0
0x0
PWM_PERIOD4
PWM_PERIOD4
PWM Counter Period Register 4
0x1C
read-write
n
0x0
0x0
PWM_PERIOD5
PWM_PERIOD5
PWM Counter Period Register 5
0x20
read-write
n
0x0
0x0
PWM_PHCHG
PWM_PHCHG
PWM Phase Changed Register
0x78
-1
read-write
n
0x0
0x0
A0POSSEL
ACMP0 Positive Input Source Select Bits\n
28
2
read-write
0
Select P1.5 as the input of ACMP0
#00
1
Select P1.0 as the input of ACMP0
#01
2
Select P1.2 as the input of ACMP0
#10
3
Select P1.3 as the input of ACMP0
#11
A1POSSEL
ACMP1 Positive Input Source Select Bits\n
20
2
read-write
0
Select P3.1 as the input of ACMP1
#00
1
Select P3.2 as the input of ACMP1
#01
2
Select P3.3 as the input of ACMP1
#10
3
Select P3.4 as the input of ACMP1
#11
ACMP0TEN
ACMP0 Trigger PWM Function Enable Bit\nNote: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set.
31
1
read-write
0
ACMP0 trigger PWM function Disabled
#0
1
ACMP0 trigger PWM function Enabled
#1
ACMP1TEN
ACMP1 Trigger Function Enable Bit\nNote: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set.
23
1
read-write
0
ACMP1 trigger PWM function Disabled
#0
1
ACMP1 trigger PWM function Enabled
#1
AOFFEN00
ACMP0 Trigger Channel 0 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
24
1
read-write
0
PWM0_CH0 one period cycle output low Disabled
#0
1
PWM0_CH0 one period cycle output low Enabled
#1
AOFFEN01
ACMP1 Trigger Channel 0 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
16
1
read-write
0
PWM0_CH0 one period cycle output low Disabled
#0
1
PWM0_CH0 one period cycle output low Enabled
#1
AOFFEN10
ACMP0 Trigger Channel 1 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
25
1
read-write
0
PWM0_CH1 one period cycle output low Disabled
#0
1
PWM0_CH1 one period cycle output low Enabled
#1
AOFFEN11
ACMP1 Trigger Channel 1 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
17
1
read-write
0
PWM0_CH1 one period cycle output low Disabled
#0
1
PWM0_CH1 one period cycle output low Enabled
#1
AOFFEN20
ACMP0 Trigger Channel 2 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
26
1
read-write
0
PWM0_CH2 one period cycle output low Disabled
#0
1
PWM0_CH2 one period cycle output low Enabled
#1
AOFFEN21
ACMP1 Trigger Channel 2 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~PWM0_CH 3.
18
1
read-write
0
PWM0_CH2 one period cycle output low Disabled
#0
1
PWM0_CH2 one period cycle output low Enabled
#1
AOFFEN30
ACMP0 Trigger Channel 3 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~ PWM0_CH3.
27
1
read-write
0
PWM0_CH3 one period cycle output low Disabled
#0
1
PWM0_CH3 one period cycle output low Enabled
#1
AOFFEN31
ACMP1 Trigger Channel 3 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
19
1
read-write
0
PWM0_CH3 one period cycle output low Disabled
#0
1
PWM0_CH3 one period cycle output low Enabled
#1
AUTOCLR0
Hardware Auto Clear ACMP0TEN\n
14
1
read-write
0
Hardware will auto clear ACMP0TEN when ACMP0 trigger PWM
#0
1
Hardware will not auto clear ACMP0TEN when ACMP0 trigger PWM
#1
AUTOCLR1
Hardware Auto Clear ACMP1TEN \n
15
1
read-write
0
Hardware will auto clear ACMP1TEN when ACMP1 trigger PWM
#0
1
Hardware will not auto clear ACMP1TEN when ACMP1 trigger PWM
#1
MSKDAT0
PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
0
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT1
PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
1
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT2
PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
2
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT3
PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
3
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT4
PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
4
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT5
PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
5
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT6
PWM0_CH6 (GPIO P0.1) Mask Data \nWhen MASKEND6 Is 1, channel 6's output level is MSKDAT6.\n
6
1
read-write
0
PWM0_CH6 output low level
#0
1
PWM0_CH6 output high level
#1
MSKDAT7
PWM0_CH7 (GPIO P0.0) Mask Data \nWhen MASKEND7 Is 1, channel 7's output level is MSKDAT7.\n
7
1
read-write
0
PWM0_CH7 output low level
#0
1
PWM0_CH7 output high level
#1
MSKEN0
PWMn Output Mask Enable Bits\n
8
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
MSKEN1
PWMn Output Mask Enable Bits\n
9
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
MSKEN2
PWMn Output Mask Enable Bits\n
10
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
MSKEN3
PWMn Output Mask Enable Bits\n
11
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
MSKEN4
PWMn Output Mask Enable Bits\n
12
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
MSKEN5
PWMn Output Mask Enable Bits\n
13
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
TMR0TEN
TIMER0 Trigger PWM Function Enable Bit\nWhen this bit is set, TIMER0 time-out event will update PWM_PHCHG with PHCHG_NXT register.\n
30
1
read-write
0
TIMER0 trigger PWM function Disabled
#0
1
TIMER0 trigger PWM function Enabled
#1
TMR1TEN
TIMER1 Trigger PWM Function Enable Bit\nWhen this bit is set, TIMER1 time-out event will update PWM_PHCHG with PHCHG_NXT register.\n
22
1
read-write
0
TIMER1 trigger PWM function Disabled
#0
1
TIMER1 trigger PWM function Enabled
#1
PWM_PHCHGMSK
PWM_PHCHGMSK
PWM Phase Change Mask Register
0x80
read-write
n
0x0
0x0
MASKEND6
PWM0_CH6 (GPIO P0.1) Output Mask Enable Bit\n
6
1
read-write
0
Output the original GPIO P0.1
#0
1
Output MSKDAT6 specified in bit 6 of PWM_PHCHG register
#1
MASKEND7
PWM0_CH7 (GPIO P0.0) Output Mask Enable Bit\n
7
1
read-write
0
Output the original GPIO P0.0
#0
1
Output MSKDAT7 specified in bit 7 of PWM_PHCHG register
#1
POSCTL0
Positive Input Control For ACMP0
Note: Register CMP0CR is described in Comparator Controller chapter.
8
1
read-write
0
The input of ACMP is controlled by CMP0CR
#0
1
The input of ACMP is controlled by CMP0SEL of PWM_PHCHG register
#1
POSCTL1
Positive Input Control For ACMP1\nNote: Register CMP1CR is described in Comparator Controller chapter.
9
1
read-write
0
The input of ACMP is controlled by CMP1CR
#0
1
The input of ACMP is controlled by CMP1SEL of PWM_PHCHG register
#1
PWM_PHCHGNXT
PWM_PHCHGNXT
PWM Next Phase Change Register
0x7C
-1
read-write
n
0x0
0x0
A0POSSEL
ACMP0 Positive Input Source Select Bits\n
28
2
read-write
0
Select P1.5 as the input of ACMP0
#00
1
Select P1.0 as the input of ACMP0
#01
2
Select P1.2 as the input of ACMP0
#10
3
Select P1.3 as the input of ACMP0
#11
A1POSSEL
ACMP1 Positive Input Source Select Bits\n
20
2
read-write
0
Select P3.1 as the input of ACMP1
#00
1
Select P3.2 as the input of ACMP1
#01
2
Select P3.3 as the input of ACMP1
#10
3
Select P3.4 as the input of ACMP1
#11
ACMP0TEN
ACMP0 Trigger Function Enable Bit\nNote: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set.
31
1
read-write
0
ACMP0 trigger PWM function Disabled
#0
1
ACMP0 trigger PWM function Enabled
#1
ACMP1TEN
ACMP1 Trigger Function Enable Bit\nNote: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set.
23
1
read-write
0
ACMP1 trigger PWM function Disabled
#0
1
ACMP1 trigger PWM function Enabled
#1
AOFFEN00
ACMP0 Trigger Channel 0 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
24
1
read-write
0
PWM0_CH0 one period cycle output low Disabled
#0
1
PWM0_CH0 one period cycle output low Enabled
#1
AOFFEN01
ACMP1 Trigger Channel 0 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
16
1
read-write
0
PWM0_CH0 one period cycle output low Disabled
#0
1
PWM0_CH0 one period cycle output low Enabled
#1
AOFFEN10
ACMP0 Trigger Channel 1 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
25
1
read-write
0
PWM0_CH1 one period cycle output low Disabled
#0
1
PWM0_CH1 one period cycle output low Enabled
#1
AOFFEN11
ACMP1 Trigger Channel 1 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
17
1
read-write
0
PWM0_CH1 one period cycle output low Disabled
#0
1
PWM0_CH1 one period cycle output low Enabled
#1
AOFFEN20
ACMP0 Trigger Channel 2 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
26
1
read-write
0
PWM0_CH2 one period cycle output low Disabled
#0
1
PWM0_CH2 one period cycle output low Enabled
#1
AOFFEN21
ACMP1 Trigger Channel 2 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
18
1
read-write
0
PWM0_CH2 one period cycle output low Disabled
#0
1
PWM0_CH2 one period cycle output low Enabled
#1
AOFFEN30
ACMP0 Trigger Channel 3 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
27
1
read-write
0
PWM0_CH3 one period cycle output low Disabled
#0
1
PWM0_CH3 one period cycle output low Enabled
#1
AOFFEN31
ACMP1 Trigger Channel 3 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
19
1
read-write
0
PWM0_CH3 one period cycle output low Disabled
#0
1
PWM0_CH3 one period cycle output low Enabled
#1
AUTOCLR0
Hardware Auto Clear ACMP0TEN\n
14
1
read-write
0
Hardware will auto clear ACMP0TEN when ACMP0 trigger PWM
#0
1
Hardware will not auto clear ACMP0TEN when ACMP0 trigger PWM
#1
AUTOCLR1
Hardware Auto Clear ACMP1TEN \n
15
1
read-write
0
Hardware will auto clear ACMP1TEN when ACMP1 trigger PWM
#0
1
Hardware will not auto clear ACMP1TEN when ACMP1 trigger PWM
#1
MSKDAT0
PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
0
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT1
PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
1
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT2
PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
2
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT3
PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
3
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT4
PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
4
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT5
PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
5
1
read-write
0
PWM0_CHn output low level
#0
1
PWM0_CHn output high level
#1
MSKDAT6
PWM0_CH6 (GPIO P0.1) Mask Data \nWhen MASKEND6 Is 1, channel 6's output level is MSKDAT6.\n
6
1
read-write
0
PWM0_CH6 output low level
#0
1
PWM0_CH6 output high level
#1
MSKDAT7
PWM0_CH7 (GPIO P0.0) Mask Data \nWhen MASKEND7 Is 1, channel 7's output level is MSKDAT7.\n
7
1
read-write
0
PWM0_CH7 output low level
#0
1
PWM0_CH7 output high level
#1
MSKEN0
PWM Output Mask Enable Bits\n
8
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
MSKEN1
PWM Output Mask Enable Bits\n
9
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
MSKEN2
PWM Output Mask Enable Bits\n
10
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
MSKEN3
PWM Output Mask Enable Bits\n
11
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
MSKEN4
PWM Output Mask Enable Bits\n
12
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
MSKEN5
PWM Output Mask Enable Bits\n
13
1
read-write
0
Output MSKDATn specified in bit n of PWM_PHCHG register
#0
1
Output the original channel n waveform
#1
TMR0TEN
TMR0 Trigger PWM Function Enable Bit\nWhen this bit is set, TMR0 time-out event will update PWM_PHCHG with PHCHG_NXT register.\n
30
1
read-write
0
TMR0 trigger PWM function Disabled
#0
1
TMR0 trigger PWM function Enabled
#1
TMR1TEN
TMR1 Trigger PWM Function Enable Bit\nWhen this bit is set, TMR1 time-out event will update PWM_PHCHG with PHCHG_NXT register.\n
22
1
read-write
0
TMR1 trigger PWM function Disabled
#0
1
TMR1 trigger PWM function Enabled
#1
PWM_POEN
PWM_POEN
PWM Output Enable Register
0x5C
read-write
n
0x0
0x0
POEN0
PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function.
0
1
read-write
0
PWM channel n output to pin Disabled
#0
1
PWM channel n output to pin Enabled
#1
POEN1
PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function.
1
1
read-write
0
PWM channel n output to pin Disabled
#0
1
PWM channel n output to pin Enabled
#1
POEN2
PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function.
2
1
read-write
0
PWM channel n output to pin Disabled
#0
1
PWM channel n output to pin Enabled
#1
POEN3
PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function.
3
1
read-write
0
PWM channel n output to pin Disabled
#0
1
PWM channel n output to pin Enabled
#1
POEN4
PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function.
4
1
read-write
0
PWM channel n output to pin Disabled
#0
1
PWM channel n output to pin Enabled
#1
POEN5
PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function.
5
1
read-write
0
PWM channel n output to pin Disabled
#0
1
PWM channel n output to pin Enabled
#1
SCS
SCS Register Map
SCS
0x0
0x10
0xC
registers
n
0x100
0x4
registers
n
0x180
0x4
registers
n
0x200
0x4
registers
n
0x280
0x4
registers
n
0x400
0x20
registers
n
0xD00
0x8
registers
n
0xD0C
0x8
registers
n
0xD1C
0x8
registers
n
AIRCR
SCS_AIRCR
Application Interrupt and Reset Control Register
0xD0C
-1
read-write
n
0x0
0x0
SYSRESETREQ
System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence.
2
1
read-write
VECTCLRACTIVE
Exception Active Status Clear Bit\nReserved for debug use. When writing to the register, user must write 0 to this bit, otherwise behavior is unpredictable.
1
1
read-write
VECTORKEY
Register Access Key\nWrite Operation:\nWhen writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.\nRead Operation:\nRead as 0xFA05.
16
16
read-write
CPUID
SCS_CPUID
CPUID Base Register
0xD00
-1
read-only
n
0x0
0x0
IMPLEMENTER
Implementer Code\n
24
8
read-only
PART
Architecture of the Processor\nRead as 0xC for ARMv6-M parts.
16
4
read-only
PARTNO
Part Number of the Processor\nRead as 0xC20.
4
12
read-only
REVISION
Revision Number\nRead as 0x0.
0
4
read-only
ICSR
SCS_ICSR
Interrupt Control State Register
0xD04
read-write
n
0x0
0x0
ISRPENDING
Interrupt Pending Flag, Excluding NMI and Faults\nNote: This bit is read only.
22
1
read-write
0
Interrupt not pending
#0
1
Interrupt pending
#1
ISRPREEMPT
Interrupt Preemption Bit\nIf set, a pending exception will be serviced on exit from the debug halt state.\nNote: This bit is read only.
23
1
read-write
NMIPENDSET
NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
31
1
read-write
0
No effect.\nNMI exception is not pending
#0
1
Changes NMI exception state to pending.\nNMI exception is pending
#1
PENDSTCLR
SysTick Exception Clear-pending Bit
Write Operation:
Note: This bit is write-only. When you want to clear PENDST bit, you must write 0 to PENDSTSET and write 1 to PENDSTCLR at the same time.
25
1
read-write
0
No effect
#0
1
Removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick Exception Set-pending Bit\nWrite Operation:\n
26
1
read-write
0
No effect.\nSysTick exception is not pending
#0
1
Changes SysTick exception state to pending.\nSysTick exception is pending
#1
PENDSVCLR
PendSV Clear-pending Bit
Write Operation:
Note: This bit is write-only. To clear the PENDSV bit, you must write 0 to PENDSVSET and write 1 to PENDSVCLR at the same time.
27
1
read-write
0
No effect
#0
1
Removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
No effect.\nPendSV exception is not pending
#0
1
Changes PendSV exception state to pending.\nPendSV exception is pending
#1
VECTACTIVE
Contains the Active Exception Number\nNote: These bits are read only.
0
9
read-write
0
Thread mode
0
VECTPENDING
Exception Number of the Highest Priority Pending Enabled Exception\nNote: These bits are read only.
12
9
read-write
0
No pending exceptions
0
NVIC_ICER
NVIC_ICER
IRQ0 ~ IRQ31 Clear-enable Control Register
0x180
read-write
n
0x0
0x0
CLRENA
Interrupt Disable Bits\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nNote: Read value indicates the current enable status.
0
32
read-write
0
No effect.\nAssociated interrupt status is Disabled
0
1
Write 1 to disable associated interrupt.\nAssociated interrupt status is Enabled
1
NVIC_ICPR
NVIC_ICPR
IRQ0 ~ IRQ31 Clear-pending Control Register
0x280
read-write
n
0x0
0x0
CLRPEND
Clear Interrupt Pending Bits\nWrite Operation:\nNote: Read value indicates the current pending status.
0
32
read-write
0
No effect.\nAssociated interrupt is not in pending status
0
1
Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status
1
NVIC_IPR0
NVIC_IPR0
IRQ0 ~ IRQ3 Interrupt Priority Control Register
0x400
read-write
n
0x0
0x0
PRI_0
Priority of IRQ0\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_1
Priority of IRQ1\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_2
Priority of IRQ2\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_3
Priority of IRQ3\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR1
NVIC_IPR1
IRQ4 ~ IRQ7 Interrupt Priority Control Register
0x404
read-write
n
0x0
0x0
PRI_4
Priority of IRQ4\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_5
Priority of IRQ5\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_6
Priority of IRQ6\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_7
Priority of IRQ7\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR2
NVIC_IPR2
IRQ8 ~ IRQ11 Interrupt Priority Control Register
0x408
read-write
n
0x0
0x0
PRI_10
Priority of IRQ10\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_11
Priority of IRQ11\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
PRI_8
Priority of IRQ8\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_9
Priority of IRQ9\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
NVIC_IPR3
NVIC_IPR3
IRQ12 ~ IRQ15 Interrupt Priority Control Register
0x40C
read-write
n
0x0
0x0
PRI_12
Priority of IRQ12\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_13
Priority of IRQ13\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_14
Priority of IRQ14\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_15
Priority of IRQ15\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR4
NVIC_IPR4
IRQ16 ~ IRQ19 Interrupt Priority Control Register
0x410
read-write
n
0x0
0x0
PRI_16
Priority of IRQ16\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_17
Priority of IRQ17\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_18
Priority of IRQ18\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_19
Priority of IRQ19\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR5
NVIC_IPR5
IRQ20 ~ IRQ23 Interrupt Priority Control Register
0x414
read-write
n
0x0
0x0
PRI_20
Priority of IRQ20\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_21
Priority of IRQ21\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_22
Priority of IRQ22\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_23
Priority of IRQ23\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR6
NVIC_IPR6
IRQ24 ~ IRQ27 Interrupt Priority Control Register
0x418
read-write
n
0x0
0x0
PRI_24
Priority of IRQ24\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_25
Priority of IRQ25\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_26
Priority of IRQ26\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_27
Priority of IRQ27\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR7
NVIC_IPR7
IRQ28 ~ IRQ31 Interrupt Priority Control Register
0x41C
read-write
n
0x0
0x0
PRI_28
Priority of IRQ28\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_29
Priority of IRQ29\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_30
Priority of IRQ30\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_31
Priority of IRQ31\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_ISER
NVIC_ISER
IRQ0 ~ IRQ31 Set-enable Control Register
0x100
read-write
n
0x0
0x0
SETENA
Interrupt Enable Bits\nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nNote: Read value indicates the current enable status.
0
32
read-write
0
No effect.\nAssociated interrupt status Disabled
0
1
Write 1 to enable associated interrupt.\nAssociated interrupt status Enabled
1
NVIC_ISPR
NVIC_ISPR
IRQ0 ~ IRQ31 Set-pending Control Register
0x200
read-write
n
0x0
0x0
SETPEND
Set Interrupt Pending Bits\nWrite Operation:\nNote: Read value indicates the current pending status.
0
32
read-write
0
No effect.\nAssociated interrupt in not in pending status
0
1
Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status
1
SCR
SCS_SCR
System Control Register
0xD10
read-write
n
0x0
0x0
SEVONPEND
Send Event On Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded
#0
1
Enabled events and all interrupts, including disabled interrupts, can wake-up the processor
#1
SLEEPDEEP
Processor Deep Sleep And Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode:\n
2
1
read-write
0
Sleep mode
#0
1
Deep Sleep mode
#1
SLEEPONEXIT
Sleep-on-exit Enable\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
0
Do not sleep when returning to Thread mode
#0
1
Enter Sleep, or Deep Sleep, on return from ISR to Thread mode
#1
SHPR2
SCS_SHPR2
System Handler Priority Register 2
0xD1C
read-write
n
0x0
0x0
PRI_11
Priority Of System Handler 11 - SVCall\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
SHPR3
SCS_SHPR3
System Handler Priority Register 3
0xD20
read-write
n
0x0
0x0
PRI_14
Priority of System Handler 14 - PendSV\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_15
Priority of System Handler 15 - SysTick\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
SYST_CSR
SYST_CSR
SysTick Control and Status Register
0x10
read-write
n
0x0
0x0
CLKSRC
System Tick Clock Source Select Bit\n
2
1
read-write
0
Clock source is optional, refer to STCLKSEL
#0
1
Core clock used for SysTick timer
#1
COUNTFLAG
System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-write
ENABLE
System Tick Counter Enable Bit\n
0
1
read-write
0
Counter Disabled
#0
1
Counter Enabled and will operate in a multi-shot manner
#1
TICKINT
System Tick Interrupt Enable Bit\n
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to 0 has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended
#1
SYST_CVR
SYST_CVR
SysTick Current Value Register
0x18
read-write
n
0x0
0x0
CURRENT
System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value Register).
0
24
read-write
SYST_RVR
SYST_RVR
SysTick Reload Value Register
0x14
read-write
n
0x0
0x0
RELOAD
System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0.
0
24
read-write
SPI
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x3C
0xC
registers
n
CLKDIV
SPI_CLKDIV
SPI Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register (Master Only)\nThe value in this field is the frequency divider to determine the SPI peripheral clock frequency fspi, and the SPI master's bus clock frequency on the SPI_CLK output pin. The frequency is obtained according to the following equation:\nIf the bit of DIVMOD, SPI_SLVCTL[31], is set to 0.\n\nelse if DIVMOD is set to 1,\n\nwhere \n is the SPI peripheral clock source which is defined in the CLK_CLKSEL1 register.
0
8
read-write
CTL
SPI_CTL
SPI Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity\n
11
1
read-write
0
SPI_CLK idle low
#0
1
SPI_CLK idle high
#1
DWIDTH
Transmit Bit Length\nThis field specifies how many bits are transmitted in one transmit/receive. The minimum bit length is 8 bits and can up to 32 bits.\n
3
5
read-write
FIFOEN
FIFO Mode Enable Bit\nNote 1: Before enabling FIFO mode, the other related settings should be set in advance.\nNote 2: In Master mode, if the FIFO mode is enabled, the SPIEN bit will be set to 1 automatically after writing data into the 4-layer depth transmit FIFO. When all data stored in transmit FIFO buffer are transferred, the SPIEN bit will back to 0.
21
1
read-write
0
FIFO Mode Disabled
#0
1
FIFO Mode Enabled
#1
LSB
LSB First\n
10
1
read-write
0
The MSB is transmitted/received first
#0
1
The LSB is transmitted/received first
#1
REORDER
Byte Reorder Function\nNote: This setting is only available if DWIDTH is defined as 16, 24, or 32 bits.
19
1
read-write
0
Byte reorder function Disabled
#0
1
Byte reorder function Enabled
#1
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[24].
24
1
read-only
0
The receive FIFO buffer is not empty
#0
1
The receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[25]
25
1
read-only
0
The receive FIFO buffer is not full
#0
1
The receive FIFO buffer is full
#1
RXNEG
Receive On Negative Edge\n
1
1
read-write
0
The received data input signal latched on the rising-edge of SPI_CLK
#0
1
The received data input signal latched on the falling-edge of SPI_CLK
#1
SLAVE
Slave Mode Control\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Control Bit And Busy Status\nIf FIFO mode is enabled, this bit will be controlled by hardware and it's read only.\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote 1: When FIFO mode is disabled, all configurations should be ready before writing 1 to the SPIEN bit.\nNote 2: In SPI Slave mode, if FIFO mode is disabled and the SPI bus clock is kept at idle state during a data transfer, the SPIEN bit will not be cleared to 0 when slave select signal goes to inactive state.
0
1
read-write
0
Writing 0 to this bit to stop data transfer if SPI is transferring
#0
1
In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
SUSPITV
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation:\n(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\nExample:\n
12
4
read-write
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STAUTS[26].
26
1
read-only
0
The transmit FIFO buffer is not empty
#0
1
The transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[27].
27
1
read-only
0
The transmit FIFO buffer is not full
#0
1
The transmit FIFO buffer is full
#1
TXNEG
Transmit On Negative Edge\n
2
1
read-write
0
The transmitted data output signal is driven on the rising-edge of SPI_CLK
#0
1
The transmitted data output signal is driven on the falling-edge of SPI_CLK
#1
UNITIEN
Unit-transfer Interrupt Enable Bit\n
17
1
read-write
0
SPI unit-transfer interrupt Disabled
#0
1
SPI unit-transfer interrupt Enabled
#1
UNITIF
Unit-transfer Interrupt Flag\nNote 1: This bit will be cleared by writing 1 to itself.\nNote 2: It's a mutual mirror bit of SPI_STATUS[16].
16
1
read-write
0
The transfer does not finish yet
#0
1
The SPI controller has finished one unit transfer
#1
FIFOCTL
SPI_FIFOCTL
SPI FIFO Control Register
0x40
-1
read-write
n
0x0
0x0
RXOVIEN
Receive FIFO Overrun Interrupt Enable Bit\n
6
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Clear Receive FIFO Buffer\nNote: This bit will be cleared to 0 by hardware after software sets it to 1 and the receive FIFO is cleared.
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer
#1
RXTH
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
24
2
read-write
RXTHIEN
Receive Threshold Interrupt Enable Bit\n
2
1
read-write
0
Receive threshold interrupt Disabled
#0
1
Receive threshold interrupt Enabled
#1
RXTOIEN
Receive FIFO Time-out Interrupt Enable Bit\n
21
1
read-write
0
Time-out interrupt Disabled
#0
1
Time-out interrupt Enabled
#1
TXRST
Clear Transmit FIFO Buffer\nNote: This bit will be cleared to 0 by hardware after software sets it to 1 and the transmit FIFO is cleared.
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer
#1
TXTH
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
28
2
read-write
TXTHIEN
Transmit Threshold Interrupt Enable Bit\n
3
1
read-write
0
Transmit threshold interrupt Disabled
#0
1
Transmit threshold interrupt Enabled
#1
RX
SPI_RX
SPI Data Receive Register
0x10
read-only
n
0x0
0x0
RX
Data Receive Register (Read Only)\nThe Data Receive Register holds the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field DWIDTH in the SPI_CTL register.\nFor example, if DWIDTH is set to 0x08, the bit field RX[7:0] holds the received data. The values of the other bits are unknown. The Data Receive Register is read-only register.
0
32
read-only
SLVCTL
SPI_SLVCTL
SPI Slave Control and Status Register
0x3C
read-write
n
0x0
0x0
DIVMOD
Clock Configuration Backward Compatible Option\nNote: Refer to the description of SPI_CLKDIV register for details.
31
1
read-write
0
The clock configuration is backward compatible
#0
1
The clock configuration is not backward compatible
#1
SLV3WIRE
Slave 3-wire Mode Enable Bit (Slave Only)\nThe SPI controller work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SSLTEN bit (SPI_SSCTL[4]) shall be set as 1.
8
1
read-write
0
The controller is 4-wire bi-direction interface in Slave mode
#0
1
The controller is 3-wire bi-direction interface in Slave mode. The controller will be ready to transmit/receive data after the SPIEN bit is set to 1
#1
SLVABT
Slave 3-wire Mode Abort Control Bit (Slave Only)\nIn normal operation, there is an interrupt event when the number of received bits meets the requirement which defined in DWIDTH.\nIf the number of received bits is less than the requirement and there is no more bus clock input over one transfer time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a unit transfer interrupt event.\nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
9
1
read-write
0
No force the transfer done when the SLV3WIRE bit is set to 1
#0
1
Force the transfer done when the SLV3WIRE bit is set to 1
#1
SLVSTIEN
Slave 3-wire Mode Start Interrupt Enable (Slave Only)\nIt is used to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, user can set the SLVABT bit to force the transfer done.\nNote: It will be cleared to 0 as the current transfer is done or the SLVSTIF bit is cleared to 0.
10
1
read-write
0
Transaction start interrupt Disabled
#0
1
Transaction start interrupt Enabled
#1
SLVSTIF
Slave 3-wire Mode Start Interrupt Status (Slave Only)
This bit dedicates if a transaction has started in Slave 3-wire mode.
Note 1: It will be cleared automatically when a transaction is done or by writing 1 to this bit.
Note 2: It is a mutual mirror bit of SPI_STATUS[11].
11
1
read-write
0
Slave does not detect any SPI bus clock transfer since the SLVSTIEN bit was set to 1
#0
1
The transfer has started in Slave 3-wire mode
#1
SSINAIEN
Slave Select Inactive Interrupt Option (Slave Only)\nNote: This setting is only available if the SPI controller is configured as level trigger in slave device.
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
SSCTL
SPI_SSCTL
SPI Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit (Master Only)\n
3
1
read-write
0
SPI_SS pin signal will be asserted/de-asserted by setting /clearing SS bit
#0
1
SPI_SS pin signal will be generated automatically by hardware, which means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting SPIEN, and will be de-asserted after each transmit/receive is finished
#1
LTF
Level Trigger Flag (Read Only, Slave Only)\nWhen the SSLTEN bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\n
5
1
read-only
0
The transaction number or the transferred bit length of one transaction does not meet the specified requirements
#0
1
The transaction number and the transferred bit length meet the specified requirements which defined in DWIDTH
#1
SS
Slave Select Control Bits (Master Only)\nIf AUTOSS bit is 0,\n
0
1
read-write
0
Set the SPI_SS line to inactive state.\nKeep the SPI_SS line at inactive state
#0
1
Set the SPI_SS line to active state.\nSelect the SPI_SS line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time. The active state of SPI_SS is specified in SSACTPOL bit
#1
SSACTPOL
Slave Select Active Level (Slave Only)\nIt defines the active status of slave select signal (SPI_SS).\nIf SSLTEN bit is 1:\n
2
1
read-write
0
The slave select signal SPI_SS is active at low-level.\nThe slave select signal SPI_SS is active at falling-edge
#0
1
The slave select signal SPI_SS is active at high-level.\nThe slave select signal SPI_SS is active at rising-edge
#1
SSLTEN
Slave Select Level Trigger Enable Bit (Slave Only)\n
4
1
read-write
0
The input slave select signal is edge-trigger
#0
1
The input slave select signal is level-trigger
#1
STATUS
SPI_STATUS
SPI Status Register
0x44
-1
read-write
n
0x0
0x0
RXCNT
Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer.
12
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CTL[24].
24
1
read-only
0
The receive FIFO buffer is not empty
#0
1
The receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only) \nNote: It's a mutual mirror bit of SPI_CTL[25].
25
1
read-only
0
The receive FIFO buffer is not full
#0
1
The receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
0
No overrun in receive FIFO
#0
1
Overrun in receive FIFO
#1
RXTHIF
Receive FIFO Threshold Interrupt Status (Read Only)\n
0
1
read-only
0
The valid data count within the receive FIFO buffer is less than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
SLVSTIF
Slave Start Interrupt Status (Slave Only)\nIt is used to dedicate that the transfer has started in slave 3-wire mode. \nNote 1: It will be cleared as transfer done or by writing one to this bit.\nNote 2: It's a mutual mirror bit of SPI_SLVCTL[11].
11
1
read-write
0
Slave does not detect any SPI bus clock transfer since the SLVSTIEN bit was set to 1. The transfer is not started
#0
1
The transfer has started in Slave 3-wire mode
#1
SLVTOIF
Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
20
1
read-write
0
No receive FIFO time-out event
#0
1
The receive FIFO buffer is not empty and it does not be read over 64 SPI clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TXCNT
Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only) \nNote: It's a mutual mirror bit of SPI_CTL[26].
26
1
read-only
0
The transmit FIFO buffer is not empty
#0
1
The transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CTL[27].
27
1
read-only
0
The transmit FIFO buffer is not full
#0
1
The transmit FIFO buffer is full
#1
TXTHIF
Transmit FIFO Threshold Interrupt Status (Read Only)\n
4
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
UNITIF
SPI Unit-transfer Interrupt Flag\nNote 1: This bit will be cleared by writing 1 to itself.\nNote 2: It's a mutual mirror bit of SPI_CTL[16].
16
1
read-write
0
The transfer does not finish yet
#0
1
The SPI controller has finished one unit transfer
#1
TX
SPI_TX
SPI Data Transmit Register
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe Data Transmit Register holds the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field DWIDTH in the SPI_CTL register.\nFor example, if DWIDTH is set to 0x08, the bit filed TX[7:0] will be transmitted in next transfer.
0
32
write-only
SYS
SYS Register Map
SYS
0x0
0x0
0x10
registers
n
0x100
0x4
registers
n
0x18
0x4
registers
n
0x30
0x18
registers
n
0x80
0xC
registers
n
BODCTL
SYS_BODCTL
Brown-out Detector Control Register
0x18
read-write
n
0x0
0x0
BODEN
Brown-out Detector Selection Extension (Initiated Write-protected Bit)
0
1
read-write
0
Brown-out detector threshold voltage is selected by the table defined in BODVL
#0
1
Brown-out detector threshold voltage is selected by the table defined as below
#1
BODIF
Brown-out Detector Interrupt Flag\n
4
1
read-write
0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting
#0
1
When Brown-out Detector detects the VDD is dropped through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled
#1
BODLPM
Brown-out Detector Low Power Mode (Write Protect)\nNote: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
5
1
read-write
0
BOD operate in normal mode (default)
#0
1
BOD Low Power mode Enabled
#1
BODOUT
Brown-out Detector Output Status\n
6
1
read-write
0
Brown-out Detector status output is 0, the detected voltage is higher than BODVL setting
#0
1
Brown-out Detector status output is 1, the detected voltage is lower than BODVL setting
#1
BODRSTEN
Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit.\nNote: When the BOD_EN is enabled and the interrupt is asserted, the interrupt will be kept till the BOD_EN is set to 0. The interrupt for CPU can be blocked by disabling the NVIC in CPU for BOD interrupt or disable the interrupt source by disabling the BOD_EN and then re-enabling the BOD_EN function if the BOD function is required.
3
1
read-write
0
Brown-out INTERRUPT function Enabled when the Brown-out Detector function is enable and the detected voltage is lower than the threshold, then assert a signal to interrupt the Cortex-M0 CPU
#0
1
Brown-out RESET function Enabled when the Brown-out Detector function is enable and the detected voltage is lower than the threshold then assert a signal to reset the chip
#1
BODVL
Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0[22:21]).\n
1
2
read-write
0
Reserved
#00
1
Brown-out Detector threshold voltage is 2.7V
#01
2
Brown-out Detector threshold voltage is 3.7V
#10
3
Brown-out Detector function Disabled
#11
IPRST0
SYS_IPRST0
Peripheral Reset Control Register 0
0x8
read-write
n
0x0
0x0
CHIPRST
CHIP One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is the same as the POR reset, all the chip controllers is reset and the chip settings from flash are also reload.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
Chip normal operation
#0
1
CHIP one-shot reset
#1
CPURST
Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller (FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
Processor core normal operation
#0
1
Processor core one-shot reset
#1
IPRST1
SYS_IPRST1
Peripheral Reset Control Register 1
0xC
read-write
n
0x0
0x0
ACMPRST
ACMP Controller Reset\n
22
1
read-write
0
ACMP controller normal operation
#0
1
ACMP controller reset
#1
ADCRST
ADC Controller Reset\n
28
1
read-write
0
ADC controller normal operation
#0
1
ADC controller reset
#1
GPIORST
GPIO (P0~P5) Controller Reset\n
1
1
read-write
0
GPIO controller normal operation
#0
1
GPIO controller reset
#1
I2C0RST
I2C0 Controller Reset\n
8
1
read-write
0
I2C0 controller normal operation
#0
1
I2C0 controller reset
#1
I2C1RST
I2C1 Controller Reset\n
9
1
read-write
0
I2C1 controller normal operation
#0
1
I2C1 controller reset
#1
PWM0RST
PWM0 Controller Reset\n
20
1
read-write
0
PWM0 controller normal operation
#0
1
PWM0 controller reset
#1
SPI0RST
SPI0 Controller Reset\n
12
1
read-write
0
SPI controller normal operation
#0
1
SPI controller reset
#1
TMR0RST
Timer0 Controller Reset\n
2
1
read-write
0
Timer0 controller normal operation
#0
1
Timer0 controller reset
#1
TMR1RST
Timer1 Controller Reset\n
3
1
read-write
0
Timer1 controller normal operation
#0
1
Timer1 controller reset
#1
UART0RST
UART0 Controller Reset\n
16
1
read-write
0
UART0 controller normal operation
#0
1
UART0 controller reset
#1
UART1RST
UART1 Controller Reset\n
17
1
read-write
0
UART1 controller normal operation
#0
1
UART1 controller reset
#1
IRCTCTL
SYS_IRCTCTL
HIRC Trim Control Register
0x80
read-write
n
0x0
0x0
FREQSEL
Trim Frequency Select Bit\nThis bit is to enable the HIRC auto trim.\nWhen setting this bit to 1, the HIRC auto trim function will trim HIRC to 22.1184 MHz automatically based on the LXT reference clock.\nDuring auto trim operation, if LXT clock error is detected or trim retry limitation count reached, this field will be cleared to 0 automatically.\n
0
1
read-write
0
HIRC auto trim function Disabled
#0
1
HIRC auto trim function Enabled and HIRC trimmed to 22.1184 MHz
#1
LOOPSEL
Trim Calculation Loop
This field defines trim value calculation based on the number of LXT clock.
For example, if LOOPSEL is set as 00 , auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT clocks.
This field also defines how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC is locked.
Once the HIRC is locked, the internal trim value update counter will be reset.
If the trim value update counter reaches this limitation value and frequency of HIRC is still not locked, the auto trim operation will be disabled and FREQSEL will be cleared to 0.
4
2
read-write
0
Trim value calculation is based on average difference in 4 LXT clock and trim retry count limitation is 64
#00
1
Trim value calculation is based on average difference in 8 LXT clock and trim retry count limitation is 128
#01
2
Trim value calculation is based on average difference in 16 LXT clock and trim retry count limitation is 256
#10
3
Trim value calculation is based on average difference in 32 LXT clock and trim retry count limitation is 512
#11
IRCTIEN
SYS_IRCTIEN
HIRC Trim Interrupt Enable Register
0x84
read-write
n
0x0
0x0
CLKEIEN
LXT Clock Error Interrupt Enable Bit\nThis bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation.\nIf this bit is high, and CLKERRIF (SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the LXT clock frequency is inaccurate.\n
2
1
read-write
0
CLKERRIF (SYS_IRCTISTS[2]) status Disabled to trigger an interrupt to CPU
#0
1
CLKERRIF (SYS_IRCTISTS[2]) status Enabled to trigger an interrupt to CPU
#1
TFAILIEN
Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count is reached and HIRC frequency is still not locked on target frequency set by FREQSEL (SYS_IRCTCTL[1:0]).\nIf this bit is high and TFAILIF (SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count is reached.\n
1
1
read-write
0
TFAILIF (SYS_IRCTISTS[1]) status Disabled to trigger an interrupt to CPU
#0
1
TFAILIF (SYS_IRCTISTS[1]) status Enabled to trigger an interrupt to CPU
#1
IRCTISTS
SYS_IRCTISTS
HIRC Trim Interrupt Status Register
0x88
read-write
n
0x0
0x0
CLKERRIF
LXT Clock Error Interrupt Status\nThis bit indicates that LXT clock frequency is inaccuracy. Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRCTCTL[0]) will be cleared to 0 by hardware automatically.\nIf this bit is set and CLKEIEN (SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the LXT clock frequency is inaccuracy. Software can write 1 to clear this bit to 0.\n
2
1
read-write
0
LXT clock frequency is accuracy
#0
1
LXT clock frequency is inaccuracy
#1
FREQLOCK
HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency locked in 22.1184 MHz.\nThis is a read only status bit and doesn't trigger any interrupt.
0
1
read-write
TFAILIF
Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRCTCTL[1:0]) will be cleared to 0 by hardware automatically.\nIf this bit is set and TFAILIEN (SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Software can write 1 to clear this bit to 0.\n
1
1
read-write
0
Trim value update limitation count is not reached
#0
1
Trim value update limitation count is reached and HIRC frequency is still not locked
#1
P0_MFP
SYS_P0_MFP
P0 Multiple Function and Input Type Control Register
0x30
read-write
n
0x0
0x0
ALT0
P0.0 Alternate Function Select Bit\nBits ALT[0] (SYS_P0_MFP[8]), and MFP[0] (SYS_P0_MFP[0]) determine the P0.0 function.\n
8
1
read-write
ALT1
P0.1 Alternate Function Select Bit\nBits ALT[1] (SYS_P0_MFP[9]), and MFP[1] (SYS_P0_MFP[1]) determine the P0.1 function.\n
9
1
read-write
ALT4
P0.4 Alternate Function Select Bit\nBits ALT[4] (SYS_P0_MFP[12]), and MFP[4] (SYS_P0_MFP[4]) determine the P0.4 function.\n
12
1
read-write
ALT5
P0.5 Alternate Function Select Bit\nBits ALT[5] (SYS_P0_MFP[13]), and MFP[5] (SYS_P0_MFP[5]) determine the P0.5 function.\n
13
1
read-write
ALT6
P0.6 Alternate Function Select Bit\nBits ALT[6] (SYS_P0_MFP[14]), and MFP[6] (SYS_P0_MFP[6]) determine the P0.6 function.\n
14
1
read-write
ALT7
P0.7 Alternate Function Select Bit\nBits ALT[7] (SYS_P0_MFP[15]), and MFP[7] (SYS_P0_MFP[7]) determine the P0.7 function.\n
15
1
read-write
MFP
P0 Multiple Function Select Bit\nThe pin function of P0 depends on MFP and ALT.\nRefer to ALT Description for details.
0
8
read-write
TYPE
P0[7:0] Input Schmitt Trigger Function Enable Bits\n
16
8
read-write
0
P0[7:0] I/O input Schmitt Trigger function Disabled
0
1
P0[7:0] I/O input Schmitt Trigger function Enabled
1
P1_MFP
SYS_P1_MFP
P1 Multiple Function and Input Type Control Register
0x34
read-write
n
0x0
0x0
ALT0
P1.0 Alternate Function Select Bit\nBits ALT[0] (SYS_P1_MFP[8]), and MFP[0] (SYS_P1_MFP[0]) determine the P1.0 function.\n
8
1
read-write
ALT2
P1.2 Alternate Function Select Bit\nBits P12EXT (SYS_P1_MFP[26]), ALT[2] (SYS_P1_MFP[10]), and MFP[2] (SYS_P1_MFP[2]) determine the P1.2 function.\n
10
1
read-write
ALT3
P1.3 Alternate Function Select Bit\nBits P13EXT (SYS_P1_MFP[27]), ALT[3] (SYS_P1_MFP[11]), and MFP[3] (SYS_P1_MFP[3]) determine the P1.3 function.\n
11
1
read-write
ALT4
P1.4 Alternate Function Select Bit\nBits P14EXT (SYS_P1_MFP[28]), ALT[4] (SYS_P1_MFP[12]), and MFP[4] (SYS_P1_MFP[4]) determine the P1.4 function.\n
12
1
read-write
ALT5
P1.5 Alternate Function Select Bit\nBits ALT[5] (SYS_P1_MFP[13]), and MFP[5] (SYS_P1_MFP[5]) determine the P1.5 function.\n
13
1
read-write
MFP
P1 Multiple Function Select Bit\nThe pin function of P1 depends on MFP and ALT.\nRefer to ALT Description for details.
0
8
read-write
P12EXT
P1.2 Alternate Function Selection Extension\nBits P12EXT (SYS_P1_MFP[26]), ALT[2] (SYS_P1_MFP[10]), and MFP[2] (SYS_P1_MFP[2]) determine the P1.2 function.\n
26
1
read-write
P13EXT
P1.3 Alternate Function Selection Extension\nBits P13EXT (SYS_P1_MFP[27]), ALT[3] (SYS_P1_MFP[11]), and MFP[3] (SYS_P1_MFP[3]) determine the P1.3 function.\n
27
1
read-write
P14EXT
P1.4 Alternate Function Selection Extension\nBits P14EXT (SYS_P1_MFP[28]), ALT[4] (SYS_P1_MFP[12]), and MFP[4] (SYS_P1_MFP[4]) determine the P1.4 function.\n
28
1
read-write
TYPE
P1[7:0] Input Schmitt Trigger Function Enable Bit\n
16
8
read-write
0
P1[7:0] I/O input Schmitt Trigger function Disabled
0
1
P1[7:0] I/O input Schmitt Trigger function Enabled
1
P2_MFP
SYS_P2_MFP
P2 Multiple Function and Input Type Control Register
0x38
read-write
n
0x0
0x0
ALT2
P2.2 Alternate Function Select Bit\nBits ALT[2] (SYS_P2_MFP[10]), and MFP[2] (SYS_P2_MFP[2]) determine the P2.2 function.\n
10
1
read-write
ALT3
P2.3 Alternate Function Select Bit\nBits ALT[3] (SYS_P2_MFP[11]), and MFP[3] (SYS_P2_MFP[3]) determine the P2.3 function.\n
11
1
read-write
ALT4
P2.4 Alternate Function Select Bit\nBits ALT[4] (SYS_P2_MFP[12]), and MFP[4] (SYS_P2_MFP[4]) determine the P2.4 function.\n
12
1
read-write
ALT5
P2.5 Alternate Function Select Bit\nBits ALT[5] (SYS_P2_MFP[13]), and MFP[5] (SYS_P2_MFP[5]) determine the P2.5 function.\n
13
1
read-write
ALT6
P2.6 Alternate Function Select Bit\nBits ALT[6] (SYS_P2_MFP[14]), and MFP[6] (SYS_P2_MFP[6]) determine the P2.6 function.\n
14
1
read-write
MFP
P2 Multiple Function Select Bit\nThe pin function of P2 depends on MFP and ALT.\nRefer to ALT Description for details.
0
8
read-write
TYPE
P2[7:0] Input Schmitt Trigger Function Enable Bits\n
16
8
read-write
0
P2[7:0] I/O input Schmitt Trigger function Disabled
0
1
P2[7:0] I/O input Schmitt Trigger function Enabled
1
P3_MFP
SYS_P3_MFP
P3 Multiple Function and Input Type Control Register
0x3C
read-write
n
0x0
0x0
ALT0
P3.0 Alternate Function Select Bit\nBits ALT[0] (SYS_P3_MFP[8]), and MFP[0] (SYS_P3_MFP[0]) determine the P3.0 function.\n
8
1
read-write
ALT1
P3.1 Alternate Function Select Bit\nThe pin function of P3.1 depends on P3_MFP[1] and P3_ALT[1].\nBits ALT[1] (SYS_P3_MFP[9]), and MFP[1] (SYS_P3_MFP[1]) determine the P3.1 function.\n
9
1
read-write
ALT2
P3.2 Alternate Function Select Bit\nBits P32EXT (SYS_P3_MFP[26]), ALT[2] (SYS_P3_MFP[10]), and MFP[2] (SYS_P3_MFP[2]) determine the P3.2 function.\n
10
1
read-write
ALT4
P3.4 Alternate Function Select Bit\nBits ALT[4] (SYS_P3_MFP[12]), and MFP[4] (SYS_P3_MFP[4]) determine the P3.4 function.\n
12
1
read-write
ALT5
P3.5 Alternate Function Select Bit\nBits ALT[5] (SYS_P3_MFP[13]), and MFP[5] (SYS_P3_MFP[5]) determine the P3.5 function.\n
13
1
read-write
ALT6
P3.6 Alternate Function Select Bit\nBits ALT[6] (SYS_P3_MFP[14]), and MFP[6] (SYS_P3_MFP[6]) determine the P3.6 function.\n
14
1
read-write
MFP
P3 Multiple Function Select Bits\nThe pin function of P3 depends on MFP and ALT.\nRefer to ALT Description for details.
0
8
read-write
P32EXT
P3.2 Alternate Function Selection Extension\nBits P32EXT (SYS_P3_MFP[26]), ALT[2] (SYS_P3_MFP[10]), and MFP[2] (SYS_P3_MFP[2]) determine the P3.2 function.\n
26
1
read-write
TYPE
P3[7:0] Input Schmitt Trigger Function Enable Bits\n
16
8
read-write
0
P3[7:0] I/O input Schmitt Trigger function Disabled
0
1
P3[7:0] I/O input Schmitt Trigger function Enabled
1
P4_MFP
SYS_P4_MFP
P4 Multiple Function and Input Type Control Register
0x40
-1
read-write
n
0x0
0x0
ALT6
P4.6 Alternate Function Select Bit\nBits ALT[6] (SYS_P4_MFP[14]), and MFP[6] (SYS_P4_MFP[6]) determine the P4.6 function.\n
14
1
read-write
ALT7
P4.7 Alternate Function Select Bit\nBits ALT[7] (SYS_P4_MFP[15]), and MFP[7] (SYS_P4_MFP[7]) determine the P4.7 function.\n
15
1
read-write
MFP
P4 Multiple Function Select Bits\nThe pin function of P4 depends on MFP and ALT.\nRefer to ALT Description for details.
0
8
read-write
TYPE
P4[7:0] Input Schmitt Trigger Function Enable Bits\n
16
8
read-write
0
P4[7:0] I/O input Schmitt Trigger function Disabled
0
1
P4[7:0] I/O input Schmitt Trigger function Enabled
1
P5_MFP
SYS_P5_MFP
P5 Multiple Function and Input Type Control Register
0x44
read-write
n
0x0
0x0
ALT0
P5.0 Alternate Function Select Bit\nThe pin function of P5.0 depends on MFP[0] and ALT[0].\nBits ALT[0] (SYS_P5_MFP[8]), and MFP[0] (SYS_P5_MFP[0]) determine the P5.0 function.\nNote: To enable external XTAL function, the CLK_PWRCTL bit [1:0] (XTLEN), external HXT or LXT crystal oscillator control register must also be set.
8
1
read-write
ALT1
P5.1 Alternate Function Select Bit\nBits ALT[1] (SYS_P5_MFP[9]), and MFP[1] (SYS_P5_MFP[1]) determine the P5.1 function.\nNote: To enable external XTAL function, the CLK_PWRCTL bit [1:0] (XTLEN), external HXT or LXT crystal oscillator control register must also be set.
9
1
read-write
ALT2
P5.2 Alternate Function Select Bit\nBits ALT[2] (SYS_P5_MFP[10]), and MFP[2] (SYS_P5_MFP[2]) determine the P5.2 function.\n
10
1
read-write
ALT3
P5.3 Alternate Function Select Bit\nBits ALT[3] (SYS_P5_MFP[11]), and MFP[3] (SYS_P5_MFP[3]) determine the P5.3 function.\n
11
1
read-write
ALT4
P5.4 Alternate Function Select Bit\nBits ALT[4] (SYS_P5_MFP[12]), and MFP[4] (SYS_P5_MFP[4]) determine the P5.4 function.\n
12
1
read-write
ALT5
P5.5 Alternate Function Select Bit\nBits ALT[5] (SYS_P5_MFP[13]), and MFP[5] (SYS_P5_MFP[5]) determine the P5.5 function.\n
13
1
read-write
MFP
P5 Multiple Function Select Bits\nThe pin function of P5 depends on MFP and ALT.\nRefer to ALT Description for details.
0
8
read-write
TYPE
P5[7:0] Input Schmitt Trigger Function Enable Bits\n
16
8
read-write
0
P5[7:0] I/O input Schmitt Trigger function Disabled
0
1
P5[7:0] I/O input Schmitt Trigger function Enabled
1
PDID
SYS_PDID
Part Device Identification Number Register
0x0
read-only
n
0x0
0x0
PDID
Product Device Identification Number (Read Only)
This register reflects the device part number code. Software can read this register to identify which device is used.
For example, the MINI58LDE PDID code is 0x00A05800 .
0
32
read-only
REGLCTL
SYS_REGLCTL
Register Write-protection Control Register
0x100
read-write
n
0x0
0x0
REGLCTL
Register Write-protection Code
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field. After this sequence is completed, the REGLCTL bit 0 will be set to 1 and write-protection registers can be normal write.
Register Write-protection Disable Index
Please refer to 6.2.6 Register Protection.Note: The bits which are write-protected will be noted as (Write Protect) beside the description.
0
8
read-write
0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
0
1
Write-protection Disabled for writing protected registers
1
RSTSTS
SYS_RSTSTS
System Reset Status Register
0x4
read-write
n
0x0
0x0
BODRF
BOD Reset Flag
The BOD reset flag is set by the Reset Signal from the Brown-out Detector to indicate the previous reset source.
Note: Software can write 1 to clear this bit to zero.
4
1
read-write
0
No reset from BOD
#0
1
The BOD had issued the reset signal to reset the system
#1
CPULKRF
The Cortex-M0 LOCKUP Flag\nNote: Software can write 1 to clear this bit to zero.
8
1
read-write
0
No reset from Cortex-M0 LOCKUP happened
#0
1
The Cortex-M0 LOCKUP happened and chip is reset
#1
CPURF
CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC).\nNote: Software can write 1 to clear this bit to zero.
7
1
read-write
0
No reset from CPU
#0
1
The Cortex-M0 Core and FMC are reset by software setting CPURST to 1
#1
PINRF
NRESET Pin Reset Flag
The nRESET pin reset flag is set by the Reset Signal from the nRESET pin to indicate the previous reset source.
Note: Software can write 1 to clear this bit to zero.
1
1
read-write
0
No reset from nRESET pin
#0
1
Pin nRESET had issued the reset signal to reset the system
#1
PORF
POR Reset Flag
The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
Note: Software can write 1 to clear this bit to zero.
0
1
read-write
0
No reset from POR or CHIPRST
#0
1
Power-on-Reset (POR) or CHIPRST had issued the reset signal to reset the system
#1
SYSRF
System Reset Flag
The system reset flag is set by the Reset Signal from the Cortex-M0 Core to indicate the previous reset source.
Note: Software can write 1 to clear this bit to zero.
5
1
read-write
0
No reset from Cortex-M0
#0
1
The Cortex-M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ (SCS_AIRCR[2]), Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core
#1
WDTRF
WDT Reset Flag
The WDT reset flag is set by the Reset Signal from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
Note: Software can write 1 to clear this bit to zero.
2
1
read-write
0
No reset from watchdog timer or window watchdog timer
#0
1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
#1
TMR
TMR Register Map
TMR
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TIMER0_CAP
TIMER0_CAP
Timer0 Capture Data Register
0x10
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
0
24
read-only
TIMER0_CMP
TIMER0_CMP
Timer0 Compare Register
0x4
read-write
n
0x0
0x0
CMPDAT
Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into the CMPDAT field.
0
24
read-write
TIMER0_CNT
TIMER0_CNT
Timer0 Data Register
0xC
read-only
n
0x0
0x0
CNT
Timer Data Register\nIf EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24- bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24- bit event input counter value.
0
24
read-only
TIMER0_CTL
TIMER0_CTL
Timer0 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CAPSRC
Capture Pin Source Select Bit\n
19
1
read-write
0
Capture Function source is from TMx_EXT (x= 0~1) pin
#0
1
Capture Function source is from internal ACMP output signal. User can set CAPSRCMP (TIMERx_EXTCTL[9]) to decide which ACMP output signal as timer capture source
#1
CMPCTL
Timer Compared Mode Select Bit
If updated CMPDAT value CNT, CNT will be reset to default value.
17
1
read-write
0
The behavior selection in one-shot or periodic mode Disabled
#0
1
The behavior selection in one-shot or periodic mode Enabled
#1
CNTEN
Timer Counting Enable Bit\n
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Event Counter Mode Enable Bit\nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source.
24
1
read-write
0
Event counter mode Disabled
#0
1
Event counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal will be generated and inform CPU.
29
1
read-write
0
Timer Interrupt Disabled
#0
1
Timer Interrupt Enabled
#1
OPMODE
Timer Counting Mode Selection\n
27
2
read-write
0
The Timer controller is operated in one-shot mode
#00
1
The Timer controller is operated in periodic mode
#01
2
The Timer controller is operated in toggle-output mode
#10
3
The Timer controller is operated in continuous counting mode
#11
PSC
Prescale Counter\n
0
8
read-write
RSTCNT
Timer Counter Reset\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n
26
1
read-write
0
No effect
#0
1
Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit
#1
TGLPINSEL
Toggle-output Pin Select Bit\n
18
1
read-write
0
Toggle mode output to TMx (Timer Event Counter Pin)
#0
1
Toggle mode output to TMx_EXT (Timer External Capture Pin)
#1
WKEN
Wake-up Function Enable Bit\nIf this bit is set to 1, while the timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.\n
23
1
read-write
0
Wake-up function Disabled if timer interrupt signal generated
#0
1
Wake-up function Enabled if timer interrupt signal generated
#1
TIMER0_EINTSTS
TIMER0_EINTSTS
Timer0 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
CAPIF
Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
0
1
read-write
0
TMx_EXT (x= 0~1) pin interrupt did not occur
#0
1
TMx_EXT (x= 0~1) pin interrupt occurred
#1
TIMER0_EXTCTL
TIMER0_EXTCTL
Timer0 External Control Register
0x14
read-write
n
0x0
0x0
ACMPSSEL
ACMP Source Selection to Trigger Capture Function\nFor Timer 0:\n
9
1
read-write
0
Capture Function source is from ACMP0 output signal for TIMER0.\nCapture Function source is from ACMP1 output signal for TIMER1
#0
1
Capture Function source is from ACMP1 output signal for TIMER0.\nCapture Function source is from ACMP0 output signal for TIMER1
#1
CAPDBEN
Timer External Capture Pin De-bounce Enable Bit\nNote1: If this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.\nNote2: The de-bounce circuit doesn't support ACMP output.
6
1
read-write
0
TMx_EXT (x= 0~1) pin de-bounce Disabled
#0
1
TMx_EXT (x= 0~1) pin de-bounce Enabled
#1
CAPEDGE
Timer External Capture Pin Edge Detection\n
1
2
read-write
0
A falling edge on TMx_EXT (x= 0~1) pin will be detected
#00
1
A rising edge on TMx_EXT (x= 0~1) pin will be detected
#01
2
Either rising or falling edge on TMx_EXT (x= 0~1) pin will be detected
#10
3
Reserved
#11
CAPEN
Timer External Capture Pin Enable Bit\nThis bit enables the TMx_EXT pin. \n
3
1
read-write
0
TMx_EXT (x= 0~1) pin Disabled
#0
1
TMx_EXT (x= 0~1) pin Enabled
#1
CAPFUNCS
Capture Function Select Bit\n
4
1
read-write
0
External Capture Mode Enabled
#0
1
External Reset Mode Enabled
#1
CAPIEN
Timer External Capture Interrupt Enable Bit\n
5
1
read-write
0
TMx_EXT (x= 0~1) pin detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~1) pin detection Interrupt Enabled
#1
CAPSEL
Capture Mode Select Bit\n
8
1
read-write
0
Timer counter reset function or free-counting mode of timer capture function
#0
1
Trigger-counting mode of timer capture function
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~1) pin de-bounce Disabled
#0
1
TMx (x= 0~1) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase \n
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
TIMER0_INTSTS
TIMER0_INTSTS
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
#1
TIMER1_CAP
TIMER1_CAP
Timer1 Capture Data Register
0x30
read-write
n
0x0
0x0
TIMER1_CMP
TIMER1_CMP
Timer1 Compare Register
0x24
read-write
n
0x0
0x0
TIMER1_CNT
TIMER1_CNT
Timer1 Data Register
0x2C
read-write
n
0x0
0x0
TIMER1_CTL
TIMER1_CTL
Timer1 Control and Status Register
0x20
read-write
n
0x0
0x0
TIMER1_EINTSTS
TIMER1_EINTSTS
Timer1 External Interrupt Status Register
0x38
read-write
n
0x0
0x0
TIMER1_EXTCTL
TIMER1_EXTCTL
Timer1 External Control Register
0x34
read-write
n
0x0
0x0
TIMER1_INTSTS
TIMER1_INTSTS
Timer1 Interrupt Status Register
0x28
read-write
n
0x0
0x0
UART0
UART Register Map
UART
0x0
0x0
0x30
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDRDEN
RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode.\nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
RS-485 address detection mode Disabled
#0
1
RS-485 address detection mode Enabled
#1
ADDRMV
Address Match Values\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation Mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation Mode (AAD) Enabled
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD) Control\nNote: It cannot be active with RS485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Function Mode (AUD) Disabled
#0
1
RS-485 Auto Direction Function Mode (AUD) Enabled
#1
RS485_NMM
RS-485 Normal Multi-drop Operation Mode (NMM) Control\nNote: It cannot be active with RS485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation Mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation Mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
Divider X Equal 1
Note: Refer to section UART Controller Baud Rate Generator for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but EDIVM1[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 8)
#1
BAUDM1
Divider X Enable Bit\nNote: In IrDA mode, this bit must be disabled.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but EDIVM1 [27:24] must = 8)
#1
BRD
Baud Rate Divider\nThe field indicates the baud rate divider.
0
16
read-write
EDIVM1
Divider X\n
24
4
read-write
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/Transmit Buffer
Write Operation:
By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
Read Operation:
By reading this register, the UART will return an 8-bit data received from receiving FIFO.
0
8
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (RDAINT) Trigger Level (Only Available In UART0)\nWhen the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set (if RDAIEN in UART_INTEN register is enable, an interrupt will generated).\n
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
RTS Trigger Level (For Auto-flow Control Use) (Only Available In UART0)\nNote: This field is used for RTS auto-flow control.
16
4
read-write
0
RTS Trigger Level is 1 byte
#0000
1
RTS Trigger Level is 4 bytes
#0001
2
RTS Trigger Level is 8 bytes
#0010
3
RTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Register (Only Available In UART0)\nThe receiver is disabled or not (setting 1 to disable the receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles.
1
1
read-write
0
No effect
#0
1
Reset RX internal state machine and pointers reset
#1
TXRST
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles.
2
1
read-write
0
No effect
#0
1
Reset TX internal state machine and pointers reset
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ADDRDETF
RS-485 Address Byte Detection Flag (Only Available In UART0)\nNote1: This field is used for RS-485 function mode.\nNote2: This bit is cleared by writing 1 to it.
3
1
read-write
BIF
Break Interrupt Flag (Read Only)
This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
Note: This bit is read only, but software can write 1 to clear it.
6
1
read-only
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit follows the last data bit or parity bit is detected as logic 0).
Note: This bit is read only, but can be cleared by writing '1' to it .
5
1
read-only
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit .
Note: This bit is read only, but can be cleared by writing '1' to it.
4
1
read-only
0
No parity error is generated
#0
1
Parity error is generated.
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXOVIF
RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
RX FIFO did not overflow
#0
1
RX FIFO overflowed
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit is cleared by writing 1 to it.
24
1
read-write
0
TX FIFO did not overflow
#0
1
TX FIFO overflowed
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
UART_FUNSEL
UART_FUNSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Selection\n
0
2
read-write
0
UART function mode
#00
1
Reserved
#01
2
IrDA function mode. (Only Available in UART0)
#10
3
RS-485 function mode. (Only Available in UART0)
#11
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ATOCTSEN
CTS Auto Flow Control Enable Bit (Only Available In UART0)\nNote: When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
CTS auto flow control Disabled
#0
1
CTS auto flow control Enabled
#1
ATORTSEN
RTS Auto Flow Control Enable Bit (Only Available In UART0)\nNote: When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO [19:16]), the UART will de-assert RTS signal.
12
1
read-write
0
RTS auto flow control Disabled
#0
1
RTS auto flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit\n
5
1
read-write
0
Buffer Error Interrupt Masked Disabled
#0
1
Buffer Error Interrupt Masked Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit\n
3
1
read-write
0
MODEMINT Masked off
#0
1
MODEMINT Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit\n
0
1
read-write
0
RDAINT Masked off
#0
1
RDAINT Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit\n
2
1
read-write
0
RLSINT Masked off
#0
1
RLSINT Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit\n
4
1
read-write
0
RXTOINT Masked off
#0
1
RXTOINT Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit\n
1
1
read-write
0
THREINT Masked off
#0
1
THREINT Enabled
#1
TOCNTEN
Time-out Counter Enable Bit\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
WKCTSIEN
Wake-up CPU Function Interrupt Enable Bit (Only Available In UART0)
Note: When the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode.
9
1
read-write
0
UART wake-up function Disabled
#0
1
UART Wake-up function Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX/RX FIFO overflow flag (TXOVIF (UART_FIFOSTS[24] or RXOVIF(UART_FIFOSTS[0])) is set. \nWhen BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TXOVIF (UART_FIFOSTS[24]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_INTSTS[5]) are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
buffer error interrupt is generated
#1
CTSWKIF
NCTS Wake-up Interrupt Flag (Read Only) (Only Available In UART0)\nNote1: If WKCTSIEN (UART_IER[9])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
16
1
read-only
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
MODEMIF
MODEM Interrupt Flag (Read Only) (Only Available In UART0)\nNote: This bit is read only and reset to 0 when bit CTSDETF (UART_MODEMSTS[0]) is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and MODENIF (UART_INTSTS[3]) are both set to 1.\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL(UART_FIFO[7:4]) then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL (UART_FIFO[7:4])).
0
1
read-only
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. (Only Available in UART0)
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UARTTOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No Time-out interrupt flag is generated
#0
1
Time-out interrupt flag is generated
#1
RXTOINT
Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1.\n
12
1
read-only
0
No Time-out interrupt is generated
#0
1
Time-out interrupt is generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN [1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-only
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal \n
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit\n
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal \n
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.\n
6
1
read-write
0
Break control Disabled
#0
1
Break control Enabled
#1
EPE
Even Parity Enable Bit\nThis bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of STOP Bit
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-, 7- and 8-bti word length, 2 STOP bit is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable Bit\n
5
1
read-write
0
Stick parity Disabled
#0
1
If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Select Bit\n
0
2
read-write
0
Word length is 5-bit
#00
1
Word length is 6-bit
#01
2
Word length is 7-bit
#10
3
Word length is 8-bit
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
RTS (Request-to-send) Signal Control\nThis bit is direct control internal RTS signal active or not, and then drive the RTS pin output with RTSACTLV bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control is enabled in UART function mode.\nNote2: This RTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
1
1
read-write
0
RTS signal is active
#0
1
RTS signal is inactive
#1
RTSACTLV
RTS Pin Active Level\nThis bit defines the active level state of RTS pin output.\nNote1: Refer to Figure 6.1013 and Figure 6.1014 UART function mode.\nNote2: Refer to Figure 6.1017 and Figure 6.1018 for RS-485 function mode.
9
1
read-write
0
RTS pin output is high level active
#0
1
RTS pin output is low level active. (Default)
#1
RTSSTS
RTS Pin State (Read Only)\nThis bit mirror from RTS pin output of voltage logic status.\n
13
1
read-only
0
RTS pin output is low level voltage logic state
#0
1
RTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\n
8
1
read-write
0
CTS pin input is high level active
#0
1
CTS pin input is low level active. (Default)
#1
CTSDETF
Detect CTS State Change Flag\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
CTS input has not change state
#0
1
CTS input has change state
#1
CTSSTS
CTS Pin Status (Read Only)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected.
4
1
read-only
0
CTS pin input is low level voltage logic state
#0
1
CTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value\nThis field is used to program the transfer delay time between the last stop bit and next start bit. The Unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator\n
0
8
read-write
UART1
UART Register Map
UART
0x0
0x0
0x10
registers
n
0x18
0x10
registers
n
0x30
0x4
registers
n
UART_BAUD
UART_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
Divider X Equal 1
Note: Refer to section UART Controller Baud Rate Generator for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but EDIVM1[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 8)
#1
BAUDM1
Divider X Enable Bit\nNote: In IrDA mode, this bit must be disabled.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but EDIVM1 [27:24] must = 8)
#1
BRD
Baud Rate Divider\nThe field indicates the baud rate divider.
0
16
read-write
EDIVM1
Divider X\n
24
4
read-write
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/Transmit Buffer
Write Operation:
By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
Read Operation:
By reading this register, the UART will return an 8-bit data received from receiving FIFO.
0
8
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (RDAINT) Trigger Level (Only Available In UART0)\nWhen the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set (if RDAIEN in UART_INTEN register is enable, an interrupt will generated).\n
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
RTS Trigger Level (For Auto-flow Control Use) (Only Available In UART0)\nNote: This field is used for RTS auto-flow control.
16
4
read-write
0
RTS Trigger Level is 1 byte
#0000
1
RTS Trigger Level is 4 bytes
#0001
2
RTS Trigger Level is 8 bytes
#0010
3
RTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Register (Only Available In UART0)\nThe receiver is disabled or not (setting 1 to disable the receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles.
1
1
read-write
0
No effect
#0
1
Reset RX internal state machine and pointers reset
#1
TXRST
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles.
2
1
read-write
0
No effect
#0
1
Reset TX internal state machine and pointers reset
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ADDRDETF
RS-485 Address Byte Detection Flag (Only Available In UART0)\nNote1: This field is used for RS-485 function mode.\nNote2: This bit is cleared by writing 1 to it.
3
1
read-write
BIF
Break Interrupt Flag (Read Only)
This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
Note: This bit is read only, but software can write 1 to clear it.
6
1
read-only
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit follows the last data bit or parity bit is detected as logic 0).
Note: This bit is read only, but can be cleared by writing '1' to it .
5
1
read-only
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit .
Note: This bit is read only, but can be cleared by writing '1' to it.
4
1
read-only
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXOVIF
RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
RX FIFO did not overflow
#0
1
RX FIFO overflowed
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit is cleared by writing 1 to it.
24
1
read-write
0
TX FIFO did not overflow
#0
1
TX FIFO overflowed
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
UART_FUNSEL
UART_FUNSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Selection\n
0
2
read-write
0
UART function mode
#00
1
Reserved
#01
2
IrDA function mode. (Only Available in UART0)
#10
3
RS-485 function mode. (Only Available in UART0)
#11
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ATOCTSEN
CTS Auto Flow Control Enable Bit (Only Available In UART0)\nNote: When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
CTS auto flow control Disabled
#0
1
CTS auto flow control Enabled
#1
ATORTSEN
RTS Auto Flow Control Enable Bit (Only Available In UART0)\nNote: When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO [19:16]), the UART will de-assert RTS signal.
12
1
read-write
0
RTS auto flow control Disabled
#0
1
RTS auto flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit\n
5
1
read-write
0
Buffer Error Interrupt Masked Disabled
#0
1
Buffer Error Interrupt Masked Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit\n
3
1
read-write
0
MODEMINT Masked off
#0
1
MODEMINT Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit\n
0
1
read-write
0
RDAINT Masked off
#0
1
RDAINT Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit\n
2
1
read-write
0
RLSINT Masked off
#0
1
RLSINT Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit\n
4
1
read-write
0
RXTOINT Masked off
#0
1
RXTOINT Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit\n
1
1
read-write
0
THREINT Masked off
#0
1
THREINT Enabled
#1
TOCNTEN
Time-out Counter Enable Bit\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
WKCTSIEN
Wake-up CPU Function Interrupt Enable Bit (Only Available In UART0)
Note: When the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode.
9
1
read-write
0
UART wake-up function Disabled
#0
1
UART Wake-up function Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX/RX FIFO overflow flag (TXOVIF (UART_FIFOSTS[24] or RXOVIF(UART_FIFOSTS[0])) is set. \nWhen BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TXOVIF (UART_FIFOSTS[24]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_INTSTS[5]) are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
buffer error interrupt is generated
#1
CTSWKIF
NCTS Wake-up Interrupt Flag (Read Only) (Only Available In UART0)\nNote1: If WKCTSIEN (UART_IER[9])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
16
1
read-only
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
MODEMIF
MODEM Interrupt Flag (Read Only) (Only Available In UART0)\nNote: This bit is read only and reset to 0 when bit CTSDETF (UART_MODEMSTS[0]) is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and MODENIF (UART_INTSTS[3]) are both set to 1.\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL(UART_FIFO[7:4]) then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL (UART_FIFO[7:4])).
0
1
read-only
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. (Only Available in UART0)
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UARTTOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No Time-out interrupt flag is generated
#0
1
Time-out interrupt flag is generated
#1
RXTOINT
Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1.\n
12
1
read-only
0
No Time-out interrupt is generated
#0
1
Time-out interrupt is generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN [1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-only
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.\n
6
1
read-write
0
Break control Disabled
#0
1
Break control Enabled
#1
EPE
Even Parity Enable Bit\nThis bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of STOP Bit
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-, 7- and 8-bti word length, 2 STOP bit is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable Bit\n
5
1
read-write
0
Stick parity Disabled
#0
1
If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Select Bit\n
0
2
read-write
0
Word length is 5-bit
#00
1
Word length is 6-bit
#01
2
Word length is 7-bit
#10
3
Word length is 8-bit
#11
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value\nThis field is used to program the transfer delay time between the last stop bit and next start bit. The Unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator\n
0
8
read-write
WDT
WDT Register Map
WDT
0x0
0x0
0x8
registers
n
ALTCTL
WDT_ALTCTL
WDT Alternative Control Register
0x4
read-write
n
0x0
0x0
RSTDSEL
WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened. User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This register will be reset to 0 if WDT time-out reset happened.
0
2
read-write
0
WDT Reset Delay Period is 1026 * WDT_CLK
#00
1
WDT Reset Delay Period is 130 * WDT_CLK
#01
2
WDT Reset Delay Period is 18 * WDT_CLK
#10
3
WDT Reset Delay Period is 3 * WDT_CLK
#11
CTL
WDT_CTL
WDT Control Register
0x0
-1
read-write
n
0x0
0x0
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement affects WDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
IF
WDT Time-out Interrupt Flag\nThis bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it.
3
1
read-write
0
WDT time-out interrupt did not occur
#0
1
WDT time-out interrupt occurred
#1
INTEN
WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. \nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
WDT time-out interrupt Disabled
#0
1
WDT time-out interrupt Enabled
#1
RSTCNT
Reset WDT Up Counter (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This bit will be automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Reset the internal 18-bit WDT up counter value
#1
RSTEN
WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
WDT time-out reset function Disabled
#0
1
WDT time-out reset function Enabled
#1
RSTF
WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
2
1
read-write
0
WDT time-out reset did not occur
#0
1
WDT time-out reset occurred
#1
TOUTSEL
WDT Time-out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
8
3
read-write
0
24 * WDT_CLK
#000
1
26 * WDT_CLK
#001
2
28 * WDT_CLK
#010
3
210 * WDT_CLK
#011
4
212 * WDT_CLK
#100
5
214 * WDT_CLK
#101
6
216 * WDT_CLK
#110
7
218 * WDT_CLK
#111
WDTEN
WDT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
WDT Disabled (This action will reset the internal up counter value)
#0
1
WDT Enabled
#1
WKEN
WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to LIRC or LXT.
4
1
read-write
0
Wake-up trigger event Disabled if WDT time-out interrupt signal generated
#0
1
Wake-up trigger event Enabled if WDT time-out interrupt signal generated
#1
WKF
WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the interrupt wake-up flag status of WDT\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This bit is cleared by writing 1 to it.
5
1
read-write
0
WDT does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated
#1
WWDT
WWDT Register Map
WWDT
0x0
0x0
0x10
registers
n
CNT
WWDT_CNT
WWDT Counter Value Register
0xC
-1
read-only
n
0x0
0x0
CNTDAT
WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
0
6
read-only
CTL
WWDT_CTL
WWDT Control Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
WWDT Window Compare Bits\nSet this register to adjust the valid reload window. \nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
16
6
read-write
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit\nWWDT down counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects WWDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
WWDT Interrupt Enable Bit\nIf this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.\n
1
1
read-write
0
WWDT counter compare match interrupt Disabled
#0
1
WWDT counter compare match interrupt Enabled
#1
PSCSEL
WWDT Counter Prescale Period Select Bits\n
8
4
read-write
0
Pre-scale is 1 Max time-out period is 1 * 64 * WWDT_CLK
#0000
1
Pre-scale is 2 Max time-out period is 2 * 64 * WWDT_CLK
#0001
2
Pre-scale is 4 Max time-out period is 4 * 64 * WWDT_CLK
#0010
3
Pre-scale is 8 Max time-out period is 8 * 64 * WWDT_CLK
#0011
4
Pre-scale is 16 Max time-out period is 16 * 64 * WWDT_CLK
#0100
5
Pre-scale is 32 Max time-out period is 32 * 64 * WWDT_CLK
#0101
6
Pre-scale is 64 Max time-out period is 64 * 64 * WWDT_CLK
#0110
7
Pre-scale is 128 Max time-out period is 128 * 64 * WWDT_CLK
#0111
8
Pre-scale is 192 Max time-out period is 192 * 64 * WWDT_CLK
#1000
9
Pre-scale is 256 Max time-out period is 256 * 64 * WWDT_CLK
#1001
10
Pre-scale is 384 Max time-out period is 384 * 64 * WWDT_CLK
#1010
11
Pre-scale is 512 Max time-out period is 512 * 64 * WWDT_CLK
#1011
12
Pre-scale is 768 Max time-out period is 768 * 64 * WWDT_CLK
#1100
13
Pre-scale is 1024 Max time-out period is 1024 * 64 * WWDT_CLK
#1101
14
Pre-scale is 1536 Max time-out period is 1536 * 64 * WWDT_CLK
#1110
15
Pre-scale is 2048 Max time-out period is 2048 * 64 * WWDT_CLK
#1111
WWDTEN
WWDT Enable Bit\nSet this bit to enable WWDT counter counting.\n
0
1
read-write
0
WWDT counter is stopped
#0
1
WWDT counter is starting counting
#1
RLDCNT
WWDT_RLDCNT
WWDT Reload Counter Register
0x0
write-only
n
0x0
0x0
RLDCNT
WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]). If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will generate immediately.
0
32
write-only
STATUS
WWDT_STATUS
WWDT Status Register
0x8
read-write
n
0x0
0x0
WWDTIF
WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
WWDT counter value matches CMPDAT
#1
WWDTRF
WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
WWDT time-out reset did not occur
#0
1
WWDT time-out reset occurred
#1