nuvoTon
N570F064_v4_2
2024.05.06
N570F064_v4_2 SVD file
8
32
ADC
ADC Register Map
ADC
0x0
0x0
0x38
registers
n
0x3C
0xC
registers
n
CHSEQ
ADC_CHSEQ
A/D Channel Sequence Register
0x24
-1
read-write
n
0x0
0x0
CHSEQ0
Select Channel N As The 1st Conversion In Scan Sequence
0
4
read-write
CHSEQ1
Select Channel N As The 2nd Conversion In Scan Sequence
The definition of channel selection is the same as CHSEQ0.
4
4
read-write
CHSEQ2
Select Channel N As The 3rd Conversion In Scan Sequence
The definition of channel selection is the same as CHSEQ0.
8
4
read-write
CHSEQ3
Select Channel N As The 4th Conversion In Scan Sequence
The definition of channel selection is the same as CHSEQ0.
12
4
read-write
CHSEQ4
Select Channel N As The 5th Conversion In Scan Sequence
The definition of channel selection is the same as CHSEQ0.
16
4
read-write
CHSEQ5
Select Channel N As The 6th Conversion In Scan Sequence
The definition of channel selection is the same as CHSEQ0.
20
4
read-write
CHSEQ6
Select Channel N As The 7th Conversion In Scan Sequence
The definition of channel selection is the same as CHSEQ0.
24
4
read-write
CHSEQ7
Select Channel N As The 8th Conversion In Scan Sequence
The definition of channel selection is the same as CHSEQ0.
28
4
read-write
CMP0
ADC_CMP0
A/D Compare Register 0
0x28
-1
read-write
n
0x0
0x0
ADCMPEN
Compare Enable
Set this bit to 1 to enable the comparison CMPDAT with specified channel conversion result when converted data is loaded into ADC_DAT register.
0
1
read-write
0
Disable compare
#0
1
Enable compare
#1
ADCMPIE
Compare Interrupt Enable
When converted data in RESULT is less (or greater) than the compare data CMPDAT, ADCMPF bit is asserted. If ADCMPIE is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Disable
#0
1
Enable
#1
CMPCH
Compare Channel Selection
3
3
read-write
0
Channel 0 conversion result is selected to be compared
#000
1
Channel 1 conversion result is selected to be compared
#001
2
Channel 2 conversion result is selected to be compared
#010
3
Channel 3 conversion result is selected to be compared
#011
4
Reserved
#100
5
The conversion result of pre-amplifier output is selected to be compared
#101
6
Channel 6 conversion result is selected to be compared
#110
7
Channel 7 conversion result is selected to be compared
#111
CMPCOND
Compare Condition
2
1
read-write
0
ADCMPFx bit is set if conversion result is less than CMPDAT
#0
1
ADCMPFx bit is set if conversion result is greater or equal to CMPDAT,
#1
CMPDAT
Compare Data
This field possessing the 5 MSB of 12-bit compare data, and 7 LSB are treated as 0 , is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software.
The data format should be consistent with the setting of ADCFM bit.
23
5
read-write
CMPMCNT
Compare Match Count
When the specified A/D channel analog conversion result matches the comparing condition, the internal match counter will increase 1. When the internal counter achieves the setting, (CMPMCNT+1) hardware will set the ADCMPF bit.
8
4
read-write
CMP1
ADC_CMP1
A/D Compare Register 1
0x2C
-1
read-write
n
0x0
0x0
CTL
ADC_CTL
A/D Control Register
0x20
-1
read-write
n
0x0
0x0
ADCEN
A/D Converter Enable
Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
0
1
read-write
0
Disable
#0
1
Enable
#1
ADCFM
Data Format Of ADC Conversion Result
12
1
read-write
0
Unsigned
#0
1
2'Complemet
#1
ADCIE
A/D Interrupt Enable
A/D conversion end interrupt request is generated if ADCIE bit is set to 1.
1
1
read-write
0
Disable A/D interrupt function
#0
1
Enable A/D interrupt function
#1
DS_EN
Down Sample Function Enable
19
1
read-write
0
Down sample function is disabled
#0
1
Down sample function is enabled. When this field is set, ADC will be forced to continuous scan mode, no matter what is specified in field OPMODE (ADC_CTL[3:2])
#1
DS_RATE
Down Sample Rate
16
2
read-write
0
Down sample X2
#00
1
Down sample X4
#01
2
Down sample X8
#10
3
Down sample X16
#11
HP_EN
High-pass Filter Enable
23
1
read-write
0
High-pass filter is disabled
#0
1
High-pass filter is enabled (must in continuous scan mode)
#1
HP_FSEL
High-pass Filter Frequency Selection:
20
3
read-write
0
Do not remove DC part
#000
1
DC part is suppressed by -40dB, -3dB at 0.005 x Sampling Rate
#001
2
DC part is suppressed by -40dB, -3dB at 0.010 x Sampling Rate
#010
3
DC part is suppressed by -40dB, -3dB at 0.014 x Sampling Rate
#011
4
DC part is suppressed by -40dB, -3dB at 0.019 x Sampling Rate
#100
5
DC part is suppressed by -40dB, -3dB at 0.023 x Sampling Rate
#101
6
DC part is suppressed by -40dB, -3dB at 0.027 x Sampling Rate
#110
7
DC part is suppressed by -40dB, -3dB at 0.032 x Sampling Rate
#111
OPMODE
A/D Converter Operation Mode
Note 1: This field will be effective only when DS_EN field in this register is set as 0 .
When DS_EN is set as 1 , ADC conversion will be forced to continuous scan mode
Note 2: When changing the operation mode, software should disable SWTRG bit firstly.
2
2
read-write
0
Single conversion
#00
1
Reserved
#01
2
Single-cycle scan
#10
3
Continuous scan
#11
PDMAEN
PDMA Transfer Enable Bit
When A/D conversion is completed, the converted data is loaded into ADC_DATn (n: 0 ~ 7) register, user can enable this bit to generate a PDMA data transfer request.
4
1
read-write
0
PDMA data transfer Disabled
#0
1
PDMA data transfer Enabled
#1
SWTRG
A/D Conversion Start
Note: SWTRG bit can be reset to 0 by software, or can be cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channel. In continuous scan mode, A/D conversion is continuously performed sequentially until software writes 0 to this bit or chip resets.
11
1
read-write
0
Conversion is stopped and A/D converter enters idle state
#0
1
Start conversion
#1
DAT0
ADC_DAT0
A/D Data Register for the Channel Defined in CHSEQ0
0x0
-1
read-only
n
0x0
0x0
EXTS
Extension Bits Of RESULT for Different Data Format
If ADCFM is 0 , EXTS all are read as 0 .
If ADCFM is 1 , EXTS all are read as bit RESULT[11].
12
4
read-only
OV
Over Run Flag
If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after ADC_DAT register is read.
16
1
read-only
0
Data in RESULT are recent conversion result
#0
1
Data in RESULT are overwritten
#1
RESULT
A/D Conversion Result
This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit.
0
12
read-only
VALID
Valid Flag
This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read.
17
1
read-only
0
Data in RESULT are not valid
#0
1
Data in RESULT are valid
#1
DAT1
ADC_DAT1
A/D Data Register for the Channel Defined in CHSEQ1
0x4
-1
read-write
n
0x0
0x0
DAT2
ADC_DAT2
A/D Data Register for the Channel Defined in CHSEQ2
0x8
-1
read-write
n
0x0
0x0
DAT3
ADC_DAT3
A/D Data Register for the Channel Defined in CHSEQ3
0xC
-1
read-write
n
0x0
0x0
DAT4
ADC_DAT4
A/D Data Register for the Channel Defined in CHSEQ4
0x10
-1
read-write
n
0x0
0x0
DAT5
ADC_DAT5
A/D Data Register for the Channel Defined in CHSEQ5
0x14
-1
read-write
n
0x0
0x0
DAT6
ADC_DAT6
A/D Data Register for the Channel Defined in CHSEQ6
0x18
-1
read-write
n
0x0
0x0
DAT7
ADC_DAT7
A/D Data Register for the Channel Defined in CHSEQ7
0x1C
-1
read-write
n
0x0
0x0
HWPARA
ADC_HWPARA
ADC H/W Parameter Control Register
0x44
-1
read-write
n
0x0
0x0
PDMA
ADC_PDMA
ADC PDMA Control Register
0x34
-1
read-write
n
0x0
0x0
PGCTL
ADC_PGCTL
ADC Pre-amplifier Gain Control Register
0x3C
-1
read-write
n
0x0
0x0
EN_PGA
1: Enable PGA 0: Disable PGA
10
1
read-write
IBGEN_TRIM
Set to 0
12
2
read-write
MICB_EN
1: Enable MIC_BIAS
16
1
read-write
MICB_VSEL
Select MIC BIAS level. 0: 0%,1:65%,2:70%,3:50% of VCCA
17
2
read-write
PD_IBEN
1: Power down analog bias generation
11
1
read-write
PGA_SEL
24
6
read-write
SAR_VREF
9
1
read-write
ZERO_CROSS
1: Gain update only on zero crossing. 0: immediate
3
1
read-write
STATUS
ADC_STATUS
A/D Status Register
0x30
-1
read-write
n
0x0
0x0
PDMA_RESULT
ADC PDMA transfer data
If DW_EN is 0 and HPF_EN is 0 , transfer SAR output to SRAM
If DW_EN is 1 and HPF_EN is 0 , transfer DW output to SRAM
If HPF_EN is 1 , transfer HPF output to SRAM
0
16
read-write
VMID
ADC_VMID
ADC VMID Control Register
0x40
-1
read-write
n
0x0
0x0
CONV_N
Specify ADC conversion clock number
CONV_N has to be equal to or great than 11.
To update this field, programmer can only revise bit [14:8] and keep other bits the same as before.
Note: CONV_N valid range is from 11~127
8
7
read-write
SHCLK_N
Specify the high level of ADC start signal.
Note: Suggested and default value is 0.
0
6
read-write
DPWM
DPWM Register Map
DPWM
0x0
0x0
0x14
registers
n
CTL
DPWM_CTL
DPWM and DAC Control Register
0x0
-1
read-write
n
0x0
0x0
CLIPIE
Read data in DATA[31:0] clipped within 0x0000-7fff ~ 0xffff-8000
Read operation of this register will get clipped data in DATA[31:0] register but
clipped with the range : 0x00 ~ 7fff ~ 0x ffff ~8000. The content of DATA[31:0]
will not be change.
7
1
read-write
DACBUFBYPASS
DAC BUFFER BYPASS
0 --- disable BYPASS DAC BUFFER
1 --- enable BYPASS DAC BUFFER
19
1
read-write
DACBUF_PD
DAC BUFFER POWER DOWN
0 --- power on DAC BUFFER
1 --- power off DAC BUFFER
20
1
read-write
DAC_EN
DAC ENABLE
0 --- DAC function disable
1 --- DAC function enable
16
1
read-write
DAC_EN_10BIT
DAC ENABLE 10Bit
0 --- 13 Bit mode
1 --- 10 bit mode, don't use lower 3BITs
17
1
read-write
DAC_INSEL
DAC input data selection
0 --- DATA from CIC and GAIN output
1 --- DATA from FIFO output
21
1
read-write
DAC_PD
DAC POWER DOWN
0 --- power on DAC13B
1 --- power down DAC13B
18
1
read-write
DEADTIME
DPWM Driver Deadtime Control.
Enabling this bit will insert an additional clock cycle deadtime into the switching of PMOS and NMOS driver transistors.
3
1
read-write
DITHEREN
DPWM Signal Dither Control
To prevent structured noise on PWM output due to DC offsets in the input signal it is possible to add random dither to the PWM signal. These bits control the dither:
0: No dither.
1: ±1 bit dither
3: ±2 bit dither
4
2
read-write
DPWMEN
DPWM Enable.
1: Enable DPWM, SPK pins are enabled and driven, data is taken from FIFO.
0: Disable DPWM, SPK pins are tri-state, CIC filter is reset, FIFO pointers are reset (FIFO data is not reset).
Note : This field will be effective only when DAC_EN field in this register is set as 0 .
6
1
read-write
MODUFRQ
DPWM Modulation Frequency.
0
3
read-write
RXTH
DPWM FIFO threshold
If the valid data count of the DPWM FIFO buffer is less than or equal to RXTH setting, the RXTHF bit will set to 1, else the RXTHF bit will be cleared to 0.
9
4
read-write
RXTHIE
DPWM FIFO threshold interrupt
1: DPWM FIFO threshold interrupt Enabled.
0: DPWM FIFO threshold interrupt Disabled.
8
1
read-write
ZCIE
Zero cross enable
0: output data doesn't cross zero point
1: output data cross zero point
14
1
read-write
DATA
DPWM_DATA
DPWM and DAC FIFO Input Register
0xC
-1
write-only
n
0x0
0x0
INDATA
DPWM and DAC FIFO Audio Data Input
A write to this register pushes data onto the DPWM and DAC FIFO and increments the write pointer. This is the address that PDMA writes audio data to.
0
16
write-only
DMACTL
DPWM_DMACTL
DPWM and DAC PDMA Control Register
0x8
-1
read-write
n
0x0
0x0
DMAEN
Enable DPWM and DAC DMA Interface.
0
1
read-write
0
Disable PDMA. No requests will be made to PDMA controller
#0
1
Enable PDMA. Block will request data from PDMA controller whenever FIFO is not empty
#1
STS
DPWM_STS
DPWM and DAC FIFO Status Register
0x4
-1
read-only
n
0x0
0x0
EMPTY
FIFO Empty
1
1
read-only
0
FIFO is not empty
#0
1
FIFO is empty
#1
FIFO_POINTER
DPWM FIFO Pointer (Read Only)
The FULL bit and FIFO_POINTER[3:0] indicates the field that the valid data count within the DPWM FIFO buffer.
The Maximum value shown in FIFO_POINTER is 15. When the using level of DPWM FIFO Buffer equal to 16, The FULL bit is set to 1.
3
4
read-only
FULL
FIFO Full
0
1
read-only
0
FIFO is not full
#0
1
FIFO is full
#1
RXTHF
DPWM FIFO threshold Interrupt Status (Read Only)
2
1
read-only
0
The valid data count within the DPWM FIFO buffer is larger than the setting value of RXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of RXTH
#1
ZOHDIV
DPWM_ZOHDIV
DPWM and DAC Zero Order Hold Division Register
0x10
-1
read-write
n
0x0
0x0
DAC_DIV
DAC clock divider
DAC data sample rate is set by this divider
16
6
read-write
GAIN
(GAIN[7:0]+1)/256, GAIN≠0
8
8
read-write
ZOH_DIV
DPWM Zero Order Hold, down-sampling divisor.
The input sample rate of the DPWM is set by HCLK frequency and the divisor set in this register by the following formula:
Valid range is 1,..,255. Default is 48, which gives a sample rate of 16kHz for a 49.152MHz (default) HCLK.
0
8
read-write
FMC
FCM Register Map
FCM
0x0
0x0
0x18
registers
n
DFBADR
FMC_DFBADR
Data Flash Base Address Register
0x14
-1
read-only
n
0x0
0x0
DFBA
Data Flash Base Address
This register reports the data flash starting address. It is a read only register.
Data flash size is defined by user configuration, register content is loaded from Config1 when chip is reset.
0
32
read-only
ISPADR
FMC_ISPADR
ISP Address Register
0x4
-1
read-write
n
0x0
0x0
ISPADR
ISP Address Register
This is the memory address register that a subsequent ISP command will access. ISP operation are carried out on 32bit words only, consequently ISPARD[1:0] must be 00b for correct ISP operation.
0
32
read-write
ISPCMD
FMC_ISPCMD
ISP Command Register
0xC
-1
read-write
n
0x0
0x0
ISPCMD
ISP Command
0
6
read-write
0
Read
0x00
11
Read CID
0x0b
12
Read DID
0x0c
33
Program
0x21
34
Page Erase
0x22
ISPCTL
FMC_ISPCTL
ISP Control Register
0x0
-1
read-write
n
0x0
0x0
BS
Boot Select
1: LDROM, 0: APROM
Modify this bit to select which ROM next boot is to occur. This bit also functions as MCU boot status flag, which can be used to check where MCU booted from. This bit is initialized after power-on reset with the inverse of CBS in Config0 It is not reset for any other reset event.
1
1
read-write
CACHE_DIS
Cache Disable
When set to 1, caching of flash memory reads is disabled.
21
1
read-write
CFGUEN
CONFIG Update Enable
When enabled, ISP functions can access the CONFIG address space and modify device configuration area.
4
1
read-write
1
Enable, 0 = Disable
#1
ISPEN
ISP Enable
0
1
read-write
0
Disable ISP function
#0
1
Enable ISP function
#1
ISPFF
ISP Fail Flag
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself.
(2) LDROM writes to itself.
(3) Destination address is illegal, such as over an available range.
Write 1 to clear.
6
1
read-write
LDUEN
LDROM Update Enable
LDROM update enable bit.
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated when the MCU runs in APROM
#1
SWRST
Software Reset
Writing 1 to this bit will initiate a software reset. It is cleared by hardware after reset.
7
1
read-write
WAIT_CFG
Flash Access Wait State Configuration
0x11: Zero wait states. HCLK < 24MHz
0x01: Two wait states.
0x00: Four wait state.
Before changing WAIT_CFG, ensure HCLK speed is < 25MHz.
16
3
read-write
ISPDAT
FMC_ISPDAT
ISP Data Register
0x8
-1
read-write
n
0x0
0x0
ISPDAT
ISP Data Register
Write data to this register before an ISP program operation.
Read data from this register after an ISP read operation
0
32
read-write
ISPTRG
FMC_ISPTRG
ISP Trigger Control Register
0x10
-1
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger
Write 1 to start ISP operation. This will be cleared to 0 by hardware automatically when ISP operation is finished.
After triggering an ISP function M0 instruction pipeline should be flushed with a ISB instruction to guarantee data integrity.
This is a protected register, user must first follow the unlock sequence (see Register Lock Control Register (SYS_REGLCTL)) to gain access.
0
1
read-write
0
ISP operation is finished
#0
1
ISP is on going
#1
GPIO
GPIO Register Map
GPIO
0x0
0x0
0x4
registers
n
0x10
0x4
registers
n
0x18
0xC
registers
n
0x40
0x4
registers
n
0x48
0x4
registers
n
0x50
0x4
registers
n
0x58
0xC
registers
n
0x8
0x4
registers
n
0x800
0x58
registers
n
PA0_PDIO
PA0_PDIO
GPIO PA.n Pin Data Input/Output Register
0x800
-1
read-write
n
0x0
0x0
PDIO
GPIO Px.n Pin Data Input/Output
Writing this bit can control one GPIO pin output value.
0
1
read-write
0
Corresponding GPIO pin set to low
#0
1
Corresponding GPIO pin set to high
#1
PA10_PDIO
PA10_PDIO
GPIO PA.n Pin Data Input/Output Register
0x828
-1
read-write
n
0x0
0x0
PA11_PDIO
PA11_PDIO
GPIO PA.n Pin Data Input/Output Register
0x82C
-1
read-write
n
0x0
0x0
PA12_PDIO
PA12_PDIO
GPIO PA.n Pin Data Input/Output Register
0x830
-1
read-write
n
0x0
0x0
PA13_PDIO
PA13_PDIO
GPIO PA.n Pin Data Input/Output Register
0x834
-1
read-write
n
0x0
0x0
PA14_PDIO
PA14_PDIO
GPIO PA.n Pin Data Input/Output Register
0x838
-1
read-write
n
0x0
0x0
PA15_PDIO
PA15_PDIO
GPIO PA.n Pin Data Input/Output Register
0x83C
-1
read-write
n
0x0
0x0
PA1_PDIO
PA1_PDIO
GPIO PA.n Pin Data Input/Output Register
0x804
-1
read-write
n
0x0
0x0
PA2_PDIO
PA2_PDIO
GPIO PA.n Pin Data Input/Output Register
0x808
-1
read-write
n
0x0
0x0
PA3_PDIO
PA3_PDIO
GPIO PA.n Pin Data Input/Output Register
0x80C
-1
read-write
n
0x0
0x0
PA4_PDIO
PA4_PDIO
GPIO PA.n Pin Data Input/Output Register
0x810
-1
read-write
n
0x0
0x0
PA5_PDIO
PA5_PDIO
GPIO PA.n Pin Data Input/Output Register
0x814
-1
read-write
n
0x0
0x0
PA6_PDIO
PA6_PDIO
GPIO PA.n Pin Data Input/Output Register
0x818
-1
read-write
n
0x0
0x0
PA7_PDIO
PA7_PDIO
GPIO PA.n Pin Data Input/Output Register
0x81C
-1
read-write
n
0x0
0x0
PA8_PDIO
PA8_PDIO
GPIO PA.n Pin Data Input/Output Register
0x820
-1
read-write
n
0x0
0x0
PA9_PDIO
PA9_PDIO
GPIO PA.n Pin Data Input/Output Register
0x824
-1
read-write
n
0x0
0x0
PA_DOUT
PA_DOUT
GPIO PA Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT
Port [A/B] Pin[N] Output Value
Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
Note: PB_DOUT[15:6] are reserved to 0.
0
16
read-write
0
GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set
0
1
GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set
1
PA_INTEN
PA_INTEN
GPIO PA Interrupt Enable
0x1C
-1
read-write
n
0x0
0x0
FLIEN0
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
0
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN1
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
1
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN10
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
10
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN11
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
11
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN12
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
12
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN13
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
13
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN14
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
14
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN15
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
15
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN2
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
2
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN3
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
3
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN4
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
4
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN5
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
5
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN6
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
6
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN7
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
7
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN8
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
8
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN9
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
9
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
RHIEN0
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
16
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN1
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
17
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN10
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
26
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN11
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
27
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN12
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
28
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN13
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
29
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN14
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
30
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN15
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
31
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN2
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
18
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN3
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
19
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN4
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
20
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN5
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
21
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN6
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
22
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN7
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
23
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN8
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
24
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN9
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
25
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
PA_INTSRC
PA_INTSRC
GPIO PA Interrupt Source Flag
0x20
-1
read-write
n
0x0
0x0
INTSRC
Port [A/B] Interrupt Source Flag
Read operation:
0
16
read-write
0
No interrupt from Px.n.
No action
0
1
Px.n generated an interrupt.
Clear the corresponding pending interrupt
1
PA_INTTYPE
PA_INTTYPE
GPIO PA Interrupt Trigger Type
0x18
-1
read-write
n
0x0
0x0
TYPE
Port [A/B] Pin[N] Edge Or Level Detection Interrupt Trigger Type Control
TYPE[n] is used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is level triggered, the input source is sampled by one HCLK clock to generate the interrupt
Note: If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set, the setting is ignored and no interrupt will occur
0
16
read-write
0
Edge triggered interrupt
0
1
Level triggered interrupt
1
PA_MODE
PA_MODE
GPIO PA Pin I/O Mode Control
0x0
-1
read-write
n
0x0
0x0
MODE0
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
0
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE1
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
2
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE10
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
20
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE11
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
22
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE12
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
24
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE13
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
26
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE14
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
28
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE15
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
30
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE2
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
4
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE3
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
6
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE4
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
8
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE5
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
10
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE6
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
12
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE7
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
14
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE8
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
16
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE9
Port [A/B] Pin[N] I/O Mode Control
Each GPIO Px pin has four modes:
Note: PB_MODE[15:6] are reserved to 0.
18
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
PA_PIN
PA_PIN
GPIO PA Pin Value
0x10
-1
read-only
n
0x0
0x0
PIN
Port [A/B] Pin[N] Pin Values
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: PB_PIN[15:6] are reserved to 0.
0
16
read-only
PB0_PDIO
PB0_PDIO
GPIO PB.n Pin Data Input/Output Register
0x840
-1
read-write
n
0x0
0x0
PB1_PDIO
PB1_PDIO
GPIO PB.n Pin Data Input/Output Register
0x844
-1
read-write
n
0x0
0x0
PB2_PDIO
PB2_PDIO
GPIO PB.n Pin Data Input/Output Register
0x848
-1
read-write
n
0x0
0x0
PB3_PDIO
PB3_PDIO
GPIO PB.n Pin Data Input/Output Register
0x84C
-1
read-write
n
0x0
0x0
PB4_PDIO
PB4_PDIO
GPIO PB.n Pin Data Input/Output Register
0x850
-1
read-write
n
0x0
0x0
PB5_PDIO
PB5_PDIO
GPIO PB.n Pin Data Input/Output Register
0x854
-1
read-write
n
0x0
0x0
PB_DOUT
PB_DOUT
GPIO PB Data Output Value
0x48
-1
read-write
n
0x0
0x0
PB_INTEN
PB_INTEN
GPIO PB Interrupt Enable
0x5C
-1
read-write
n
0x0
0x0
PB_INTSRC
PB_INTSRC
GPIO PB Interrupt Source Flag
0x60
-1
read-write
n
0x0
0x0
PB_INTTYPE
PB_INTTYPE
GPIO PB Interrupt Trigger Type
0x58
-1
read-write
n
0x0
0x0
PB_MODE
PB_MODE
GPIO PB Pin I/O Mode Control
0x40
-1
read-write
n
0x0
0x0
PB_PIN
PB_PIN
GPIO PB Pin Value
0x50
-1
read-write
n
0x0
0x0
INT
INT Register Map
INT
0x0
0x0
0x4C
registers
n
0x80
0x8
registers
n
IRQ0_SRC
IRQ0_SRC
IRQ0 (WDT) Interrupt Source Identity Register
0x0
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: WDT_INT
0
3
read-only
IRQ10_SRC
IRQ10_SRC
IRQ10 (PWM0) Interrupt Source Identity Register
0x28
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PWM0_INT
0
3
read-only
IRQ11_SRC
IRQ11_SRC
IRQ11 (PDMA) Interrupt Source Identity Register
0x2C
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PDMA_INT
0
3
read-only
IRQ12_SRC
IRQ12_SRC
IRQ12 (TimerF) Interrupt Source Identity Register
0x30
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: TimerF_INT
0
3
read-only
IRQ13_SRC
IRQ13_SRC
IRQ13 (RTC) Interrupt Source Identity Register
0x34
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: RTC_INT
0
3
read-only
IRQ14_SRC
IRQ14_SRC
Reserved
0x38
-1
read-only
n
0x0
0x0
IRQ15_SRC
IRQ15_SRC
IRQ15 (PWM1) Interrupt Source Identity Register
0x3C
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PWM1_INT
0
3
read-only
IRQ16_SRC
IRQ16_SRC
Reserved
0x40
-1
read-only
n
0x0
0x0
IRQ17_SRC
IRQ17_SRC
IRQ17 (UART0) Interrupt Source Identity Register
0x44
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: UART0_INT
0
3
read-only
IRQ18_SRC
IRQ18_SRC
IRQ18 (BOD) Interrupt Source Identity Register
0x48
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: BOD_INT
0
3
read-only
IRQ1_SRC
IRQ1_SRC
IRQ1 (DPWM) Interrupt Source Identity Register
0x4
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: DPWM_INT
0
3
read-only
IRQ2_SRC
IRQ2_SRC
IRQ2 (ADC) Interrupt Source Identity Register
0x8
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: ADC_INT
0
3
read-only
IRQ3_SRC
IRQ3_SRC
Reserved
0xC
-1
read-only
n
0x0
0x0
IRQ4_SRC
IRQ4_SRC
IRQ4 (SPIM) Interrupt Source Identity Register
0x10
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: SPIM_INT
0
3
read-only
IRQ5_SRC
IRQ5_SRC
IRQ5 (Timer0) Interrupt Source Identity Register
0x14
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: Timer0_INT
0
3
read-only
IRQ6_SRC
IRQ6_SRC
IRQ6 (Timer1) Interrupt Source Identity Register
0x18
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: Timer1_INT
0
3
read-only
IRQ7_SRC
IRQ7_SRC
IRQ7 (Timer2) Interrupt Source Identity Register
0x1C
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: Timer2_INT
0
3
read-only
IRQ8_SRC
IRQ8_SRC
IRQ8 (GPA/B) Interrupt Source Identity Register
0x20
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: GPB_INT
Bit0: GPA_INT
0
3
read-only
IRQ9_SRC
IRQ9_SRC
IRQ9 (SPI0) Interrupt Source Identity Register
0x24
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: SPI0_INT
0
3
read-only
MCU_IRQ
MCU_IRQ
MCU IRQ Number Identify Register
0x84
-1
read-write
n
0x0
0x0
MCU_IRQ
MCU IRQ Source Test Mode
The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to MCU Cortex-M0. There are two modes to generate interrupt to MCU Cortex-M0, the normal mode and test mode.
When MCU_IRQ[n] is 0 : Writing MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 IRQ[n].
When MCU_IRQ[n] is 1 (meaning an interrupt is asserted): Writing MCU_IRQ[n] 1 will clear the interrupt writing MCU_IRQ[n] 0 : has no effect.
Note: IRQ3, IRQ14 and IRQ16 are reserved.
0
16
read-write
NMI_SEL
NMI_SEL
NMI Source Interrupt Select Control Register
0x80
-1
read-write
n
0x0
0x0
IRQ_TM
IRQ Test Mode
This bit is the protected bit. To program this bit needs an open lock sequence, write 59h , 16h , 88h to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
7
1
read-write
0
The interrupt register MCU_IRQ operates in normal mode. The MCU_IRQ collects all the interrupts from the peripheral and generates interrupt to MCU
#0
1
All the interrupts from peripheral to MCU are blocked. The peripheral IRQ signals (0-15) are replaced by the value in the MCU_IRQ register
#1
NMI_SEL
NMI Source Interrupt Select
The NMI interrupt to Cortex-M0 can be selected from one of the interrupt [18:0].
The NMI_SEL bit is used to select the NMI interrupt source.
Note: IRQ3, IRQ14 and IRQ16 are reserved.
0
5
read-write
OSCFM
OSCFM Register Map
OSCFM
0x0
0x0
0xC
registers
n
CNT
OSCFM_CNT
Frequency Measurement Counter Register
0x4
-1
read-only
n
0x0
0x0
OSCFM_CNT
FM Counter Number
Report the counter
0
16
read-only
CTL
OSCFM_CTL
Frequency Measurement Control Register
0x0
-1
read-write
n
0x0
0x0
CLK_FM_SEL
CLK FM SELETION
0
2
read-write
FM_CYC
FM Cycle number
Note: OSCFM_CYC[7:0] also can write this resigster
16
8
read-write
FM_DONE
FM DONE FLAG
If FM_GO is 0 , clear the FM_DONE.
2
1
read-write
0
not done or no action
#0
1
testing done,
#1
FM_GO
FM GO BUSY
0 --- no action
1 --- start to frequency measurement
31
1
read-write
CYCLE
OSCFM_CYCLE
Frequency Measurement Cycle Register
0x8
-1
read-write
n
0x0
0x0
FM_CYC
FM iteration cycle number
Note: FM_CYC[7:0] can be overwritten by OSCFM_CTL[23:16]
0
16
read-write
PDMA_CH0
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
PDMA_BCRx
PDMA_BCRx
PDMA Channel x Transfer Byte Count Register
0xC
-1
read-write
n
0x0
0x0
BCR
PDMA Transfer Byte Count Register
This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF.
0
16
read-write
PDMA_CBCRx
PDMA_CBCRx
PDMA Channel x Current Transfer Byte Count Register
0x1C
-1
read-only
n
0x0
0x0
CBCR
PDMA Current Byte Count Register (Read Only)
This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs
0
16
read-only
PDMA_CDARx
PDMA_CDARx
PDMA Channel x Current Destination Address Register
0x18
-1
read-only
n
0x0
0x0
CDAR
PDMA Current Destination Address Register (Read Only)
This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs.
0
32
read-only
PDMA_CSARx
PDMA_CSARx
PDMA Channel x Current Source Address Register
0x14
-1
read-only
n
0x0
0x0
CSAR
PDMA Current Source Address Register (Read Only)
This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs.
0
32
read-only
PDMA_CSRx
PDMA_CSRx
PDMA Channel x Control Register
0x0
-1
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Select.
This parameter determines the data width to be transferred each PDMA transfer operation.
Note: This field is meaningful only when MODE_SEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB).
19
2
read-write
0
One word (32 bits) is transferred for every PDMA operation
#00
1
One byte (8 bits) is transferred for every PDMA operation
#01
2
One half-word (16 bits) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Destination Address Select
This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
6
2
read-write
0
Transfer Destination Address is incremented
#00
1
Reserved
#01
2
Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input)
#10
3
Transfer Destination Address is wrapped. When CBCR (Current Byte Count) equals zero, the CDAR (Current Destination Address) and CBCR registers will be reloaded from the DAR (Destination Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address
#11
MODE_SEL
PDMA Mode Select
This parameter selects to transfer direction of the PDMA channel. Possible values are:
2
2
read-write
0
Memory to Memory mode (SRAM-to-SRAM)
#00
1
IP to Memory mode (APB-to-SRAM)
#01
2
Memory to IP mode (SRAM-to-APB)
#10
PDMACEN
PDMA Channel Enable
Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
Note: SW_RST will clear this bit.
0
1
read-write
SAD_SEL
Source Address Select
This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
4
2
read-write
0
Transfer Source address is incremented
#00
1
Reserved
#01
2
Transfer Source address is fixed
#10
3
Transfer Source address is wrapped. When CBCR (Current Byte Count) equals zero, the CSAR (Current Source Address) and CBCR registers will be reloaded from the SAR (Source Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address
#11
SW_RST
Software Engine Reset
1
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles
#1
TRIG_EN
Trigger Enable - Start a PDMA operation.
Note: When PDMA transfer completed, this bit will be cleared automatically.
If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again.
23
1
read-write
0
Write: no effect. Read: Idle/Finished
#0
1
Enable PDMA data read or write transfer
#1
WRA_INT_SEL
Wrap Interrupt Select
x1x1: Both half and w interrupts generated.
12
4
read-write
PDMA_DARx
PDMA_DARx
PDMA Channel x Destination Address Register
0x8
-1
read-write
n
0x0
0x0
DAR
PDMA Transfer Destination Address Register
This register holds the initial Destination Address of PDMA transfer.
Note: The destination address must be word aligned.
0
32
read-write
PDMA_IERx
PDMA_IERx
PDMA Channel x Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Transfer Done Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.
1
1
read-write
0
Disable PDMA transfer done interrupt generation
#0
1
Enable PDMA transfer done interrupt generation
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation.
0
1
read-write
0
Disable PDMA transfer target abort interrupt generation
#0
1
Enable PDMA transfer target abort interrupt generation
#1
WAR_IE
Wraparound Interrupt Enable
If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WRA_INT_SEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA.
2
1
read-write
0
Disable Wraparound PDMA interrupt generation
#0
1
Enable Wraparound interrupt generation
#1
PDMA_ISRx
PDMA_ISRx
PDMA Channel x Interrupt Status Register
0x24
-1
read-write
n
0x0
0x0
BLKD_IF
Block Transfer Done Interrupt Flag
This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.
1
1
read-write
0
Transfer ongoing or Idle
#0
1
Transfer Complete
#1
INTR
Interrupt Pin Status (Read Only)
This bit is the Interrupt pin status of PDMA channel.
31
1
read-only
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag
This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again.
NOTE: This bit is cleared by writing 1 to itself.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
WAR_IF
Wrap around transfer byte count interrupt flag.
These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits.
8
4
read-write
1
Current transfer finished flag (CBCR==0)
#0001
4
Current transfer half complete flag (CBCR==BCR/2)
#0100
PDMA_POINTx
PDMA_POINTx
PDMA Channel x Internal Buffer Pointer Register
0x10
-1
read-only
n
0x0
0x0
POINT
PDMA Internal Buffer Pointer Register (Read Only)
A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction.
0
4
read-only
PDMA_SARx
PDMA_SARx
PDMA Channel x Source Address Register
0x4
-1
read-write
n
0x0
0x0
SAR
PDMA Transfer Source Address Register
This register holds the initial Source Address of PDMA transfer.
Note: The source address must be word aligned.
0
32
read-write
PDMA_CH1
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
PDMA_BCRx
PDMA_BCRx
PDMA Channel x Transfer Byte Count Register
0xC
-1
read-write
n
0x0
0x0
BCR
PDMA Transfer Byte Count Register
This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF.
0
16
read-write
PDMA_CBCRx
PDMA_CBCRx
PDMA Channel x Current Transfer Byte Count Register
0x1C
-1
read-only
n
0x0
0x0
CBCR
PDMA Current Byte Count Register (Read Only)
This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs
0
16
read-only
PDMA_CDARx
PDMA_CDARx
PDMA Channel x Current Destination Address Register
0x18
-1
read-only
n
0x0
0x0
CDAR
PDMA Current Destination Address Register (Read Only)
This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs.
0
32
read-only
PDMA_CSARx
PDMA_CSARx
PDMA Channel x Current Source Address Register
0x14
-1
read-only
n
0x0
0x0
CSAR
PDMA Current Source Address Register (Read Only)
This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs.
0
32
read-only
PDMA_CSRx
PDMA_CSRx
PDMA Channel x Control Register
0x0
-1
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Select.
This parameter determines the data width to be transferred each PDMA transfer operation.
Note: This field is meaningful only when MODE_SEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB).
19
2
read-write
0
One word (32 bits) is transferred for every PDMA operation
#00
1
One byte (8 bits) is transferred for every PDMA operation
#01
2
One half-word (16 bits) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Destination Address Select
This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
6
2
read-write
0
Transfer Destination Address is incremented
#00
1
Reserved
#01
2
Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input)
#10
3
Transfer Destination Address is wrapped. When CBCR (Current Byte Count) equals zero, the CDAR (Current Destination Address) and CBCR registers will be reloaded from the DAR (Destination Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address
#11
MODE_SEL
PDMA Mode Select
This parameter selects to transfer direction of the PDMA channel. Possible values are:
2
2
read-write
0
Memory to Memory mode (SRAM-to-SRAM)
#00
1
IP to Memory mode (APB-to-SRAM)
#01
2
Memory to IP mode (SRAM-to-APB)
#10
PDMACEN
PDMA Channel Enable
Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
Note: SW_RST will clear this bit.
0
1
read-write
SAD_SEL
Source Address Select
This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
4
2
read-write
0
Transfer Source address is incremented
#00
1
Reserved
#01
2
Transfer Source address is fixed
#10
3
Transfer Source address is wrapped. When CBCR (Current Byte Count) equals zero, the CSAR (Current Source Address) and CBCR registers will be reloaded from the SAR (Source Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address
#11
SW_RST
Software Engine Reset
1
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles
#1
TRIG_EN
Trigger Enable - Start a PDMA operation.
Note: When PDMA transfer completed, this bit will be cleared automatically.
If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again.
23
1
read-write
0
Write: no effect. Read: Idle/Finished
#0
1
Enable PDMA data read or write transfer
#1
WRA_INT_SEL
Wrap Interrupt Select
x1x1: Both half and w interrupts generated.
12
4
read-write
PDMA_DARx
PDMA_DARx
PDMA Channel x Destination Address Register
0x8
-1
read-write
n
0x0
0x0
DAR
PDMA Transfer Destination Address Register
This register holds the initial Destination Address of PDMA transfer.
Note: The destination address must be word aligned.
0
32
read-write
PDMA_IERx
PDMA_IERx
PDMA Channel x Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Transfer Done Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.
1
1
read-write
0
Disable PDMA transfer done interrupt generation
#0
1
Enable PDMA transfer done interrupt generation
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation.
0
1
read-write
0
Disable PDMA transfer target abort interrupt generation
#0
1
Enable PDMA transfer target abort interrupt generation
#1
WAR_IE
Wraparound Interrupt Enable
If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WRA_INT_SEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA.
2
1
read-write
0
Disable Wraparound PDMA interrupt generation
#0
1
Enable Wraparound interrupt generation
#1
PDMA_ISRx
PDMA_ISRx
PDMA Channel x Interrupt Status Register
0x24
-1
read-write
n
0x0
0x0
BLKD_IF
Block Transfer Done Interrupt Flag
This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.
1
1
read-write
0
Transfer ongoing or Idle
#0
1
Transfer Complete
#1
INTR
Interrupt Pin Status (Read Only)
This bit is the Interrupt pin status of PDMA channel.
31
1
read-only
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag
This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again.
NOTE: This bit is cleared by writing 1 to itself.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
WAR_IF
Wrap around transfer byte count interrupt flag.
These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits.
8
4
read-write
1
Current transfer finished flag (CBCR==0)
#0001
4
Current transfer half complete flag (CBCR==BCR/2)
#0100
PDMA_POINTx
PDMA_POINTx
PDMA Channel x Internal Buffer Pointer Register
0x10
-1
read-only
n
0x0
0x0
POINT
PDMA Internal Buffer Pointer Register (Read Only)
A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction.
0
4
read-only
PDMA_SARx
PDMA_SARx
PDMA Channel x Source Address Register
0x4
-1
read-write
n
0x0
0x0
SAR
PDMA Transfer Source Address Register
This register holds the initial Source Address of PDMA transfer.
Note: The source address must be word aligned.
0
32
read-write
PDMA_GCR
PDMA Register Map
PDMA
0x0
0x0
0x8
registers
n
0xC
0x4
registers
n
PDMA_GCRCSR
PDMA_GCRCSR
PDMA Global Control Register
0x0
-1
read-write
n
0x0
0x0
HCLK_EN
PDMA Controller Channel Clock Enable Control
To enable clock for channel n HCLK_EN[n] must be set.
8
2
read-write
PDMA_RST
PDMA Software Reset
Note: This bit can reset all channels (global reset).
0
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will auto clear after several clock cycles
#1
PDMA_GCRISR
PDMA_GCRISR
PDMA Global Interrupt Status Register
0xC
-1
read-only
n
0x0
0x0
GCRISR
Interrupt Pin Status (Read Only)
GCRISR[n] is the interrupt status of PDMA channel n.
0
2
read-only
PDMA_PDSSR
PDMA_PDSSR
PDMA Service Selection Control Register
0x4
-1
read-write
n
0x0
0x0
ADC_RXSEL
PDMA ADC Receive Selection
This field defines which PDMA channel is connected to ADC peripheral receive (PDMA source) request.
16
2
read-write
0
No channel select
#00
1
Select channel 0
#01
2
Select channel 1
#10
3
Reserved
#11
DPWM_TXSEL
PDMA DPWM Transmit Selection
This field defines which PDMA channel is connected to DPWM peripheral transmit (PDMA destination) request.
20
2
read-write
0
No channel select
#00
1
Select channel 0
#01
2
Select channel 1
#10
3
Reserved
#11
SPI0_RXSEL
PDMA SPI0 Receive Selection
This field defines which PDMA channel is connected to SPI0 peripheral receive (PDMA source) request.
0
2
read-write
0
No channel select
#00
1
Select channel 0
#01
2
Select channel 1
#10
3
Reserved
#11
SPI0_TXSEL
PDMA SPI0 Transmit Selection
This field defines which PDMA channel is connected to SPI0 peripheral transmit (PDMA destination) request.
4
2
read-write
0
No channel select
#00
1
Select channel 0
#01
2
Select channel 1
#10
3
Reserved
#11
SPIM_RXSEL
PDMA SPIM Receive Selection
This field defines which PDMA channel is connected to SPIM peripheral receive (PDMA source) request.
8
2
read-write
0
No channel select
#00
1
Select channel 0
#01
2
Select channel 1
#10
3
Reserved
#11
SPIM_TXSEL
PDMA SPIM Transmit Selection
This field defines which PDMA channel is connected to SPIM peripheral transmit (PDMA destination) request.
12
2
read-write
0
No channel select
#00
1
Select channel 0
#01
2
Select channel 1
#10
3
Reserved
#11
RTC
RTC Register Map
RTC
0x0
0x0
0x4
registers
n
CTL
RTC_CTL
RTC Control Register
0x0
-1
read-write
n
0x0
0x0
RTCE
RTC Enable
2
1
read-write
0
Disable RTC function
#0
1
Enable RTC function
#1
RTIE
RTC Interrupt Enable
1
1
read-write
0
Disable the RTC interrupt
#0
1
Enable the RTC interrupt
#1
RTIF
RTC Interrupt Flag
If the RTC interrupt is enabled, then the hardware will set this bit to indicate that the RTC interrupt has occurred. If the RTC interrupt is not enabled, then this bit indicates that a timeout period has elapsed.
Note: This bit is cleared by writing 1 to this bit.
0
1
read-write
0
RTC interrupt does not occur
#0
1
RTC interrupt occurs
#1
RTIS
RTC Timer Interval Select
These two bits select the timeout interval for the RTC.
3
3
read-write
0
Time-out frequency is 0.25Hz,
#000
1
Time-out frequency is 0.5Hz,
#001
2
Time-out frequency is 1Hz,
#010
3
Time-out frequency is 2Hz
#011
4
Time-out frequency is 4Hz,
#100
5
Time-out frequency is 8Hz,
#101
6
Time-out frequency is 16Hz,
#110
7
Time-out frequency is 32Hz
#111
SCS
SCS Register Map
SCS
0x0
0x100
0x4
registers
n
0x180
0x4
registers
n
0x200
0x4
registers
n
0x280
0x4
registers
n
0x400
0x14
registers
n
NVIC_ICER
NVIC_ICER
IRQ0 ~ IRQ18 Clear-enable Control Register
0x180
-1
read-write
n
0x0
0x0
CLRENA
Interrupt Clear-Enable Bit
The NVIC_ICER register disables interrupts, and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ18 (Vector number from 16 ~ 34).
Write Operation:
0
16
read-write
0
No effect.
Interrupt Disabled
0
1
Interrupt Disabled.
Interrupt Enabled
1
NVIC_ICPR
NVIC_ICPR
IRQ0 ~ IRQ18 Clear-pending Control Register
0x280
-1
read-write
n
0x0
0x0
CLRPEND
Interrupt Clear-Pending Bit
The NVIC_ICPR register removes the pending state of associated interrupts, and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ18 (Vector number from 16 ~ 34).
Write Operation:
0
16
read-write
0
No effect.
Interrupt is not pending
0
1
Removes pending state of an interrupt.
Interrupt is pending
1
NVIC_IPR0
NVIC_IPR0
IRQ0 ~ IRQ3 Priority Control Register
0x400
-1
read-write
n
0x0
0x0
PRI_0
Priority Of IRQ0
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_1
Priority Of IRQ1
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_2
Priority Of IRQ2
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_3
Priority Of IRQ3
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR1
NVIC_IPR1
IRQ4 ~ IRQ7 Priority Control Register
0x404
-1
read-write
n
0x0
0x0
PRI_4
Priority Of IRQ4
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_5
Priority Of IRQ5
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_6
Priority Of IRQ6
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_7
Priority Of IRQ7
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR2
NVIC_IPR2
IRQ8 ~ IRQ11 Priority Control Register
0x408
-1
read-write
n
0x0
0x0
PRI_10
Priority Of IRQ10
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_11
Priority Of IRQ11
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
PRI_8
Priority Of IRQ8
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_9
Priority Of IRQ9
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
NVIC_IPR3
NVIC_IPR3
IRQ12 ~ IRQ15 Priority Control Register
0x40C
-1
read-write
n
0x0
0x0
PRI_12
Priority Of IRQ12
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_13
Priority Of IRQ13
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_14
Priority Of IRQ14
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_15
Priority Of IRQ15
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR4
NVIC_IPR4
IRQ16 ~ IRQ18 Priority Control Register
0x410
-1
read-write
n
0x0
0x0
PRI_12
Priority Of IRQ12
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_13
Priority Of IRQ13
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_14
Priority Of IRQ14
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
NVIC_ISER
NVIC_ISER
IRQ0 ~ IRQ18 Set-enable Control Register
0x100
-1
read-write
n
0x0
0x0
SETENA
Interrupt Set-Enable Bit
The NVIC_ISER register enables interrupts, and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ18 (Vector number from 16 ~ 34).
Write Operation:
0
16
read-write
0
No effect.
Interrupt Disabled
0
1
Interrupt Enabled
1
NVIC_ISPR
NVIC_ISPR
IRQ0 ~ IRQ18 Set-pending Control Register
0x200
-1
read-write
n
0x0
0x0
SETPEND
Interrupt Set-Pending Bit
The NVIC_ISPR register forces interrupts into the pending state, and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ18 (Vector number from 16 ~ 34).
Write Operation:
0
16
read-write
0
No effect.
Interrupt is not pending
0
1
Changes interrupt state to pending.
Interrupt is pending
1
SPI0
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x8
registers
n
CLKDIV
SPI0_CLKDIV
Clock Divider Register (Master Only)
0x4
-1
read-write
n
0x0
0x0
DIVIDER0
Clock Divider Register (master only)
The value in this field is the frequency division of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation:
In other words, the maximum frequency of SCLK clock is one fifth of the SPI peripheral clock.
0
16
read-write
DIVIDER1
Clock Divider 2 Register (master only)
The value in this field is the 2nd frequency divider of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation:
16
16
read-write
CTL
SPI0_CTL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
BYTEITV
Insert Sleep Interval Between Bytes
This function is only valid for 32bit transfers (DWIDTH aaa 0). If set then a pause of (SUSPITV+2) SCLK cycles is inserted between each byte transmitted.
19
1
read-write
CLKPOL
Clock Polarity
11
1
read-write
0
SCLK idle low
#0
1
SCLK idle high
#1
DWIDTH
Transmit Bit Length
This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.
DWIDTH aaa 0x01 --- 1 bit
DWIDTH aaa 0x02 --- 2 bits
----
DWIDTH aaa 0x1f --- 31 bits
DWIDTH aaa 0x00 --- 32 bits
3
5
read-write
FIFOEN
FIFO Mode
21
1
read-write
0
No FIFO present on transmit and receive buffer
#0
1
Enable FIFO on transmit and receive buffer
#1
GOBUSY
Go and Busy Status
NOTE: All registers should be set before writing 1 to this BUSY bit. When a transfer is in progress, writing to any register of the SPI master/slave core has no effect.
0
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit starts the transfer. This bit remains set during the transfer and is automatically cleared after transfer finished
#1
LSB
LSB First
10
1
read-write
0
The MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the DWIDTH field)
#0
1
The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position in the Rx register (bit 0 of SPI_RX0/1)
#1
PDMASSEN
Enable DMA Automatic SS function
When enabled, interface will automatically generate a SS signal for an entire PDMA access transaction.
28
1
read-write
REORDER
Byte Endian Reorder Function
This function changes the order of bytes sent/received to be least significant physical byte first.
20
1
read-write
RXEMPTY
Receive FIFO Empty Status
24
1
read-write
0
The receive data FIFO is not empty
#0
1
The receive data FIFO is empty
#1
RXFULL
Receive FIFO Full Status
25
1
read-write
0
The receive data FIFO is not full
#0
1
The receive data FIFO is full
#1
RXNET
Receive At Negative Edge
1
1
read-write
0
The received data input signal is latched at the rising edge of SCLK
#0
1
The received data input signal is latched at the falling edge of SCLK
#1
SLAVE
Master Slave Mode Control
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SUSPITV
Suspend Interval (Master Only)
These four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKPOL aaa 0. If CLKPOL aaa 1, the interval is from the rising clock edge to the falling clock edge. The default value is 0x0. When TXCNT aaa 00b, setting this field has no effect on transfer except as determined by REORDER[0] setting. The suspend interval is determined according to the following equation:
(SUSPITV[3:0] + 2) * period of SCLK
12
4
read-write
TXEMPTY
Transmit FIFO Empty Status
26
1
read-write
0
The transmit data FIFO is not empty
#0
1
The transmit data FIFO is empty
#1
TXFULL
Transmit FIFO Full Status
27
1
read-write
0
The transmit data FIFO is not full
#0
1
The transmit data FIFO is full
#1
TXNEG
Transmit At Negative Edge
2
1
read-write
0
The transmitted data output signal is changed at the rising edge of SCLK
#0
1
The transmitted data output signal is changed at the falling edge of SCLK
#1
TXNUM
Transmit/Receive Word Numbers
This field specifies how many transmit/receive word numbers should be executed in one transfer.
8
2
read-write
0
Only one transmit/receive word will be executed in one transfer
#00
1
Two successive transmit/receive word will be executed in one transfer
#01
2
Reserved
#10
3
Reserved
#11
UNITIEN
Interrupt Enable
17
1
read-write
0
Disable SPI Interrupt
#0
1
Enable SPI Interrupt to CPU
#1
UNITIF
Interrupt Flag
NOTE: This bit is cleared by writing 1 to itself.
16
1
read-write
0
Indicates the transfer is not finished yet
#0
1
Indicates that the transfer is complete. Interrupt is generated to CPU if enabled
#1
VARCLKEN
Variable Clock Enable (Master Only)
Note that when enabled, the setting of DWIDTH must be programmed as 0x10 (16 bits mode)
23
1
read-write
0
The serial clock output frequency is fixed and determined only by the value of DIVIDER0
#0
1
SCLK output frequency is variable. The output frequency is determined by the value of SPI_VARCLK, DIVIDER0, and DIVIDER1
#1
RX0
SPI0_RX0
Data Receive Register 0
0x10
-1
read-only
n
0x0
0x0
RX
Data Receive Register
The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register. For example, if Tx_BIT_LEN is set to 0x08 and Tx_NUM is set to 0x0, bit Rx0[7:0] holds the received data.
NOTE: The Data Receive Registers are read only registers.
0
32
read-only
RX1
SPI0_RX1
Data Receive Register 1
0x14
-1
read-write
n
0x0
0x0
SPI_PDMACTL
SPI_PDMACTL
SPI PDMA Control Register
0x38
-1
read-write
n
0x0
0x0
RXPDMAEN
Receive DMA Start
Set this bit to 1 will start the receive DMA process. SPI module will issue request to DMA module automatically.
1
1
read-write
TXPDMAEN
Transmit DMA Start
Set this bit to 1 will start the transmit DMA process. SPI module will issue request to DMA module automatically.
If using DMA mode to transfer data, remember not to set GO_BUSY bit of SPI_CNTRL register. The DMA controller inside SPI module will set it automatically whenever necessary.
0
1
read-write
SPI_VARCLK
SPI_VARCLK
Variable Clock Pattern Register
0x34
-1
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern
The value in this field is the frequency pattern of the SPI clock. If the bit field of VARCLK is '0', the output frequency of SCLK is given by the value of DIVIDER. If the bit field of VARCLK is '1', the output frequency of SCLK is given by the value of DIVIDER2. Refer to register DIVIDER.
Refer to Variable Serial Clock Frequency paragraph for detailed description.
0
32
read-write
SSCTL
SPI0_SSCTL
Slave Select Register
0x8
-1
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select (Master only)
3
1
read-write
0
If this bit is cleared, slave select signals are asserted and de-asserted by setting and clearing related bits in SPI_SSCTL[1:0] register
#0
1
If this bit is set, SPISSx0/1 signals are generated automatically. It means that device/slave select signal, which is set in SPI_SSCTL[1:0] register is asserted by the SPI controller when transmit/receive is started by setting BUSY, and is de-asserted after each transmit/receive is finished
#1
LVTRGEN
Slave Select Level Trigger (Slave only)
4
1
read-write
0
The input slave select signal is edge-trigger. This is the default value
#0
1
The slave select signal will be level-trigger. It depends on SSACTPOL to decide the signal is active low or active high
#1
LVTRGSTS
Level Trigger Flag
When the LVTRGEN bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not.
Note: This bit is READ only
5
1
read-write
0
One of the received number and the received bit length doesn't meet the requirement in one transfer
#0
1
The received number and received bits met the requirement which defines in TXCNT and DWIDTH among one transfer
#1
SS
Slave Select Register (Master only)
If AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If AUTOSS bit is set, writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active level of SPISSx0/1 is specified in SSACTPOL).
Note: SPISSx0 is always defined as device/slave select input signal in slave mode.
0
2
read-write
SSACTPOL
Slave Select Active Level
It defines the active level of device/slave select signal (SPISSx0/1).
2
1
read-write
0
The slave select signal SPISSx0/1 is active at low-level/falling-edge
#0
1
The slave select signal SPISSx0/1 is active at high-level/rising-edge
#1
TX0
SPI0_TX0
Data Transmit Register 0
0x20
-1
write-only
n
0x0
0x0
Tx
Data Transmit Register
The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register. For example, if Tx_BIT_LEN is set to 0x08 and the Tx_NUM is set to 0x0, the bit Tx0[7:0] will be transmitted in next transfer. If Tx_BIT_LEN is set to 0x00 and Tx_NUM is set to 0x1, the core will perform two 32-bit transmit/receive successive using the same setting (the order is Tx0[31:0], Tx1[31:0]).
0
32
write-only
TX1
SPI0_TX1
Data Transmit Register 1
0x24
-1
read-write
n
0x0
0x0
SPIM
SPIM Register Map
SPIM
0x0
0x0
0x8
registers
n
0x10
0x20
registers
n
CTL0
SPIM_CTL0
Control and Status Register 0
0x0
-1
read-write
n
0x0
0x0
BITMODE
SPI Interface Bit Mode
Note. SPIM_MOSI is Data 0 pin for Quad Mode.
SPIM_MISO is Data 1 pin for Quad Mode.
20
2
read-write
0
Standard mode
#00
1
Dual mode
#01
2
Quad mode
#10
3
Reserved
#11
BURSTNUM
Transmit/Receive Burst Number
This field specifies how many transmit/receive transactions should be executed continuously in one transfer.
13
2
read-write
0
Only one transmit/receive transaction will be executed in one transfer
#00
1
Two successive transmit/receive transactions will be executed in one transfer
#01
2
Three successive transmit/receive transactions will be executed in one transfer
#10
3
Four successive transmit/receive transactions will be executed in one transfer
#11
DWIDTH
Transmit/Receive Bit Length
This field specifies how many bits are transmitted/received in one transmit/receive transaction.
Note: Only 8-, 16-, 24-, and 32-bit are allowed. Other bit length will result in incorrect transfer.
8
5
read-write
23
24 bits
0x17
31
32 bits
0x1f
7
8 bits
0x7
15
16 bits
0xf
IEN
Interrupt Enable Control
6
1
read-write
0
SPIM Interrupt Disabled
#0
1
SPIM Interrupt Enabled
#1
IF
Interrupt Flag
Write Operation:
7
1
read-write
0
No effect.
The transfer has not finished yet
#0
1
Write 1 to clear.
The transfer has done
#1
QDIODIR
SPI Interface Direction Select For Quad/Dual Mode
15
1
read-write
0
Interface signals are input
#0
1
Interface signals are output
#1
RXDMAEN
RX DMA Enable Control Bit
If set RXDMAEN to high, SPI interface will receive the data from slave automatically.
Note: Only support master mode.
Note2: Before setting RXDMAEN, user must set PDMA register correctly first.
0
1
read-write
0
DMA Disabled
#0
1
DMA Enable
#1
SUSPITV
Suspend Interval
16
4
read-write
0
2 HCLK clock cycles
0x0
1
3 HCLK clock cycles
0x1
14
16 HCLK clock cycles
0xe
15
17 HCLK clock cycles
0xf
TXDMAEN
TX DMA Enable Control Bit
If set TXDMAEN to high, SPI interface will transfer the data to slave automatically.
Note: Only support master mode.
Note2: Before setting RXDMAEN, user must set PDMA register correctly first.
1
1
read-write
0
DMA Disabled
#0
1
DMA Enable
#1
CTL1
SPIM_CTL1
Control Register 1
0x4
-1
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register
The value in this field is the frequency divider of the system clock to generate the serial clock on the output SPIM_CLK pin. The desired frequency is obtained according to the following equation:
Note: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of SYS_CLK.
16
16
read-write
DLYSEL
RX Sample Clock Source Delay Chain Select
12
3
read-write
0
Not Delay
#000
1
Select sample clock through 2 Delay Cell
#001
2
Select sample clock through 4 Delay Cell
#010
3
Select sample clock through 6 Delay Cell
#011
7
Select sample clock through 14 Delay Cell
#111
SPIMEN
Go and Busy Status
Write Operation:
Note: All registers should be set before writing 1 to the SPIMEN bit. When a transfer is in progress, you should not write to any register of this peripheral.
0
1
read-write
0
No effect.
The transfer has done
#0
1
Start the transfer. This bit remains set during the transfer and is automatically cleared after transfer finished.
The transfer has not finished yet
#1
SS
Slave Select Active Enable Control
Note: This interface can only drive one device/slave at a given time. Therefore, the slave selects of the selected device must be set to its active level before starting any read or write transfer.
4
1
read-write
0
SPIM_SS is in active level
#0
1
SPIM_SS is in inactive level
#1
SSACTPOL
Slave Select Active Level
It defines the active level of device/slave select signal (SPIM_SS).
5
1
read-write
0
The SPIM_SS slave select signal is Active Low
#0
1
The SPIM_SS slave select signal is Active High
#1
RX0
SPIM_RX0
Data Receive Register 0
0x10
-1
read-only
n
0x0
0x0
RX
Data Receive Register
The Data Receive Registers hold the received data of the last executed transfer.
Number of valid RX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM > 0, received data are held in the most significant RX register first.
Number of valid-bit is specified in SPIM_CTL0[DWIDTH]. If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RX register first.
In a byte, received data are held in the most significant bit of RX register first.
0
32
read-only
RX1
SPIM_RX1
Data Receive Register 1
0x14
-1
read-write
n
0x0
0x0
RX2
SPIM_RX2
Data Receive Register 2
0x18
-1
read-write
n
0x0
0x0
RX3
SPIM_RX3
Data Receive Register 3
0x1C
-1
read-write
n
0x0
0x0
TX0
SPIM_TX0
Data Transmit Register 0
0x20
-1
read-write
n
0x0
0x0
TX
Data Transmit Register
The Data Transmit Registers hold the data to be transmitted in next transfer.
Number of valid TX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM > 0, data are transmitted in the most significant TX register first.
Number of valid-bit is specified in SPIM_CTL0[DWIDTH]. If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TX register first.
In a byte, data are transmitted in the most significant bit of TX register first.
0
32
read-write
TX1
SPIM_TX1
Data Transmit Register 1
0x24
-1
read-write
n
0x0
0x0
TX2
SPIM_TX2
Data Transmit Register 2
0x28
-1
read-write
n
0x0
0x0
TX3
SPIM_TX3
Data Transmit Register 3
0x2C
-1
read-write
n
0x0
0x0
SYS
SYS Register Map
SYS
0x0
0x0
0x10
registers
n
0x110
0xC
registers
n
0x18
0x4
registers
n
0x30
0xC
registers
n
0x40
0x8
registers
n
0x4C
0x4
registers
n
0x54
0x4
registers
n
0x5C
0x4
registers
n
0xF0
0x14
registers
n
BODCTL
SYS_BODCTL
Brown-out Detector Control Register
0x18
-1
read-write
n
0x0
0x0
BOD_EN
Brown-Out Detector Enable (Initialized and Protected Bit)
The default value is set by flash controller as inverse of user configuration CBODEN bit (config0 [20]).
0
1
read-write
0
Brown-Out Detector function is disabled
#0
1
Brown-Out Detector function enabled
#1
BOD_HYS
Brown-Out Detector Hysteresis (Initialized and Protected Bit)
The default value is set by flash controller user configuration CBOV[4] bit (config0 [26]).
6
1
read-write
0
No hysteresis on BOD detection
#0
1
BOD hysteresis enabled
#1
BOD_INT
Brown-Out Detector Interrupt
8
1
read-write
1
indicates BOD_INT is active. Write 1 to clear
#1
BOD_LVL
Brown-Out Detector Threshold Voltage Selection (Initialized and Protected Bit)
2
4
read-write
BOD_OUT
Brown-Out Detector Output State
7
1
read-write
0
Brown-out Detector status output is 0, the detected voltage is higher than BOD_VL setting
#0
1
Brown-out Detector status output is 1, the detected voltage is lower than BOD_VL setting
#1
BOD_RSTEN
Brown-Out Detector Reset or Interrupt Bit (Initialized and Protected Bit)
The default value is set by flash controller as inverse of user configuration CBORST bit (config0 [21]).
When the BOD is enabled and the interrupt is asserted, the interrupt will be kept till the BOD is disabled. The interrupt for CPU can be blocked either by disabling the interrupt in the NVIC or by disabling the interrupt source by disabling the BOD. BOD can then be re-enabled as required.
1
1
read-write
0
Brown-Out Detector generate an interrupt
#0
1
Brown-Out Detector will reset chip
#1
LVR_EN
Low Voltage Reset (LVR) Enable (Initialized and Protected Bit)
The LVR function resets the chip when the input power voltage is lower than LVR trip point. Default value is set by flash controller as inverse of CLVR (config0 [27]).
16
1
read-write
0
Disable LVR function
#0
1
Enable LVR function
#1
LVR_FILTER
Default value is 00
17
2
read-write
0
LVR output will be filtered by1 HCLK
#00
1
LVR output will be filtered by 2 HCLK
#01
2
LVR output will be filtered by 8 HCLK
#10
3
LVR output will be filtered by 15 HCLK
#11
DEVICEID
SYS_DEVICEID
Device ID Register
0xF4
-1
read-only
n
0x0
0x0
DEVICEID
Device ID Data
This register provides specific read-only information for the Device ID
0
16
read-only
GPA_IEN
SYS_GPA_IEN
PA.15 ~ PA.0 Digital Input Buffer Control Register
0x4C
-1
read-write
n
0x0
0x0
IEN
0
1
read-write
0
Input buffer Enabled
#0
1
Input buffer disabled, and input signal always equals to 0
#1
GPA_MFP
SYS_GPA_MFP
GPIO PA Multiple Alternate Functions Control Register
0x30
-1
read-write
n
0x0
0x0
PA0MFP
PA.0 Multi-function Pin Selection
0
2
read-write
PA10MFP
PA.10 Multi-function Pin Selection
20
2
read-write
PA11MFP
PA.11 Multi-function Pin Selection
22
2
read-write
PA12MFP
PA.12 Multi-function Pin Selection
24
2
read-write
PA13MFP
PA.13 Multi-function Pin Selection
26
2
read-write
PA14MFP
PA.14 Multi-function Pin Selection
28
2
read-write
PA15MFP
PA.15 Multi-function Pin Selection
30
2
read-write
PA1MFP
PA.1 Multi-function Pin Selection
2
2
read-write
PA2MFP
PA.2 Multi-function Pin Selection
4
2
read-write
PA3MFP
PA.3 Multi-function Pin Selection
6
2
read-write
PA4MFP
PA.4 Multi-function Pin Selection
8
2
read-write
PA5MFP
PA.5 Multi-function Pin Selection
10
2
read-write
PA6MFP
PA.6 Multi-function Pin Selection
12
2
read-write
PA7MFP
PA.7 Multi-function Pin Selection
14
2
read-write
PA8MFP
PA.8 Multi-function Pin Selection
16
2
read-write
PA9MFP
PA.9 Multi-function Pin Selection
18
2
read-write
GPA_PULL
SYS_GPA_PULL
PA.15 ~ PA.0 Pull Resistance Control Register
0x44
-1
read-write
n
0x0
0x0
PU_EN0
This function only for the GPIO pin as an INPUT mode.
0
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN1
This function only for the GPIO pin as an INPUT mode.
1
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN10
This function only for the GPIO pin as an INPUT mode.
10
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN11
This function only for the GPIO pin as an INPUT mode.
11
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN12
This function only for the GPIO pin as an INPUT mode.
12
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN13
This function only for the GPIO pin as an INPUT mode.
13
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN14
This function only for the GPIO pin as an INPUT mode.
14
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN15
This function only for the GPIO pin as an INPUT mode.
15
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN2
This function only for the GPIO pin as an INPUT mode.
2
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN3
This function only for the GPIO pin as an INPUT mode.
3
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN4
This function only for the GPIO pin as an INPUT mode.
4
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN5
This function only for the GPIO pin as an INPUT mode.
5
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN6
This function only for the GPIO pin as an INPUT mode.
6
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN7
This function only for the GPIO pin as an INPUT mode.
7
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN8
This function only for the GPIO pin as an INPUT mode.
8
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN9
This function only for the GPIO pin as an INPUT mode.
9
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
GPB_IEN
SYS_GPB_IEN
PB.5 ~ PB.0 Digital Input Buffer Control Register
0x5C
-1
read-write
n
0x0
0x0
IEN
0
1
read-write
0
Input buffer Enabled
#0
1
Input buffer disabled, and input signal always equals to 0
#1
GPB_MFP
SYS_GPB_MFP
GPIO PB Multiple Alternate Functions Control Register
0x34
-1
read-write
n
0x0
0x0
PB0MFP
PB.0 Multi-function Pin Selection
0
2
read-write
PB1MFP
PB.1 Multi-function Pin Selection
2
2
read-write
PB2MFP
PB.2 Multi-function Pin Selection
4
2
read-write
PB3MFP
PB.3 Multi-function Pin Selection
6
2
read-write
PB4MFP
PB.4 Multi-function Pin Selection
8
2
read-write
PB5MFP
PB.5 Multi-function Pin Selection
10
2
read-write
GPB_PULL
SYS_GPB_PULL
PB.5 ~ PB.0 Pull Resistance Control Register
0x54
-1
read-write
n
0x0
0x0
PU_EN0
This function only for the GPIO pin as an INPUT mode.
0
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN1
This function only for the GPIO pin as an INPUT mode.
1
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN2
This function only for the GPIO pin as an INPUT mode.
2
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN3
This function only for the GPIO pin as an INPUT mode.
3
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN4
This function only for the GPIO pin as an INPUT mode.
4
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
PU_EN5
This function only for the GPIO pin as an INPUT mode.
5
1
read-write
0
Pull-Up function Disable
#0
1
Pull-Up function Enable
#1
GPIO_INTP
SYS_GPIO_INTP
GPIO Input Type and Slew Rate Control Register
0x40
-1
read-write
n
0x0
0x0
ICE_MFP
SYS_ICE_MFP
ICE Multi-function-pin Controller Register
0x38
-1
read-write
n
0x0
0x0
ICE_EN
This bit will set ICE_CLK and ICE_DAT pins to be serial debug wires or PA.6/7
0
1
read-write
0
ICE_CLK and ICE_DAT will be assigned as PA.6 and PA.7, for general IO purpose
#0
1
ICE_CLK and ICE_DAT will be set as ICE CLOCK/ ICE DIO, only for debugging purpose
#1
IMGMAP0
SYS_IMGMAP0
MAP0 Data Image Register
0xF8
-1
read-only
n
0x0
0x0
IMG0
Data Image of MAP0
Data in MAP0 of information block are copied to this register after power on.
0
32
read-only
IMGMAP1
SYS_IMGMAP1
MAP1 Data Image Register
0xFC
-1
read-only
n
0x0
0x0
IMG1
Data Image of MAP1
Data in MAP1 of information block are copied to this register after power on.
0
32
read-only
IMGMAP3
SYS_IMGMAP3
MAP3 Data Image Register
0xF0
-1
read-only
n
0x0
0x0
IMG3
Data Image of MAP3
Data in MAP3 of information block are copied to this register after power on.
0
32
read-only
IPRST0
SYS_IPRST0
IP Reset Control Resister0
0x8
-1
read-write
n
0x0
0x0
CHIPRST
CHIP One Shot Reset
Set this bit will reset the whole chip, this bit will automatically return to 0 after 2 clock cycles.
CHIPRST is same as POR reset, all the chip modules are reset and the chip configuration settings from Flash Memory are reloaded.
0
1
read-write
0
Normal
#0
1
Reset CHIP
#1
CPURST
CPU Kernel One Shot Reset
Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC), this bit will automatically return to 0 after the 2 clock cycles
1
1
read-write
0
Normal
#0
1
Reset CPU
#1
IPRST1
SYS_IPRST1
IP Reset Control Resister1
0xC
-1
read-write
n
0x0
0x0
ADCRST
ADC Controller Reset
28
1
read-write
0
Normal Operation
#0
1
Reset
#1
DPWMRST
DPWM Controller Reset
29
1
read-write
0
Normal Operation
#0
1
Reset
#1
GPIORST
GPIO Controller Reset
1
1
read-write
0
Normal operation
#0
1
Reset
#1
PDMARST
PDMA Controller Reset
7
1
read-write
0
Normal operation
#0
1
Reset
#1
PWM0RST
PWM0 Controller Reset
20
1
read-write
0
Normal Operation
#0
1
Reset
#1
PWM1RST
PWM1 Controller Reset
21
1
read-write
0
Normal Operation
#0
1
Reset
#1
SPI0RST
SPI0 Controller Reset
12
1
read-write
0
Normal Operation
#0
1
Reset
#1
SPIMRST
SPIM Controller Reset
13
1
read-write
0
Normal Operation
#0
1
Reset
#1
TMR0RST
Timer0 Controller Reset
2
1
read-write
0
Normal Operation
#0
1
Reset
#1
TMR1RST
Timer1 Controller Reset
3
1
read-write
0
Normal Operation
#0
1
Reset
#1
TMR2RST
Timer2 Controller Reset
4
1
read-write
0
Normal operation
#0
1
Reset
#1
TMRFRST
TimerF Controller Reset
6
1
read-write
0
Normal operation
#0
1
Reset
#1
OSC10K
SYS_OSC10K
10kHz oscillator and bias trim register
0x114
-1
read-write
n
0x0
0x0
OSCTRIM
SYS_OSCTRIM
Internal Oscillator Trim Register
0x110
-1
read-write
n
0x0
0x0
OSC10K_TRIM
23bit trim for 10kHz oscillator.
0
23
read-write
TRM_CLK
Must be toggled to load a new OSC10K_TRIM
31
1
read-write
OSC_TRIMn
SYS_OSC_TRIMn
Internal Oscillator Trim Register
0x118
-1
read-write
n
0x0
0x0
EN2MHZ
1: Low Frequency mode of oscillator active (2MHz).
0: High frequency mode (20-50MHz)
31
1
read-write
TRIM
16bit sign extended representation of 10bit trim.
OSC_TRIM[0] maps to above-mentioned OSCTRIM.
OSC_TRIM[1] and OSC_TRIM[2] are reserved.
0
16
read-write
PDID
SYS_PDID
Product Identifier Register
0x0
-1
read-only
n
0x0
0x0
IMG2
Product Identifier
Data in MAP2 of information block are copied to this register after power on. MAP2 is used to store part number defined by Nuvoton.
0
16
read-only
REGLCTL
SYS_REGLCTL
Register Lock Control Register
0x100
-1
read-write
n
0x0
0x0
RSTSTS
SYS_RSTSTS
System Reset Source Register
0x4
-1
read-write
n
0x0
0x0
BOD
BOD Reset Flag
The BOD reset flag is set by the Reset Signal from the Brown Out Reset Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
4
1
read-write
0
No reset from BOD
#0
1
BOD controller had issued the reset signal to reset the system
#1
LVRF
LVR Reset Flag
The LVR reset flag is set by the Reset Signal from the Low Voltage Reset Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
3
1
read-write
0
No reset from LVR
#0
1
LVR controller had issued the reset signal to reset the system
#1
PINRF
RESETB Pin Reset Flag
The RESETB pin reset flag is set by the Reset Signal from the RESETB Pin to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
1
1
read-write
0
No reset from RESETB pin
#0
1
Pin RESETB had issued the reset signal to reset the system
#1
PIN_WK
Wakeup from DPD From PIN
The device was woken from Deep Power Down by a low transition on the WAKEUP in or RESETB pin.
Note: Write 1 to this register to clear all wakeup flags.
8
1
read-write
0
No wakeup from PIN
#0
1
The device was issued a wakeup from DPD by a pin transition
#1
PMURSTF
Reset Source From PMU
The PMURSTF flag is set by the reset signal from the PMU module to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
6
1
read-write
0
No reset from PMU
#0
1
The PMU has issued the reset signal to reset the system
#1
PORF
POR Reset Flag
The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
0
1
read-write
0
No reset from POR
#0
1
Power-on Reset (POR) Controller had issued the reset signal to reset the system
#1
POR_WK
Wakeup from DPD From POR
The device was woken from Deep Power Down by a Power On Reset.
10
1
read-write
0
No wakeup from POR
#0
1
The device was issued a wakeup from DPD by a POR
#1
TIM_WK
Wakeup from DPD From TIMER
The device was woken from Deep Power Down by count of 10kHz timer.
9
1
read-write
0
No wakeup from TIMER
#0
1
The device was issued a wakeup from DPD by a TIMER event
#1
WDTRF
Reset Source From WDG
The WDTRF flag is set if pervious reset source originates from the Watch-Dog module.
Note: Write 1 to clear this bit to 0.
2
1
read-write
0
No reset from Watch-Dog
#0
1
The Watch-Dog module issued the reset signal to reset the system
#1
TMR
TMR Register Map
TMR
0x0
0x0
0x10
registers
n
0x20
0x18
registers
n
0x40
0x10
registers
n
IR_CTL
IR_CTL
IR Carrier Output Control Register
0x34
-1
read-write
n
0x0
0x0
TIMER0_CMP
TIMER0_CMP
Timer0 Compare Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
Timer Comparison Value
Note 1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.
Note 2: No matter CNTEN is 0 or 1, whenever software writes a new value into this register, TIMER will restart counting by using this new value and abort previous count.
0
16
read-write
TIMER0_CNT
TIMER0_CNT
Timer0 Data Register
0xC
-1
read-only
n
0x0
0x0
CNT
Timer Data Register
User can read this register for the current up-counter value while TIMERx_CTL.CNTEN is set to 1,
0
16
read-only
TIMER0_CTL
TIMER0_CTL
Timer0 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)
This bit indicates the counter status of Timer.
25
1
read-only
0
Timer is not active
#0
1
Timer is active
#1
CNTEN
Counter Enable Bit
30
1
read-write
0
Stop/Suspend counting
#0
1
Start counting
#1
INTEN
Interrupt Enable Bit
If timer interrupt is enabled, the timer asserts its interrupt signal when the associated count is equal to TIMERx_CMP.
29
1
read-write
0
Disable TIMER Interrupt
#0
1
Enable TIMER Interrupt
#1
OPMODE
Timer Operating Mode
27
2
read-write
0
The Timer is operating in the one-shot mode. The associated interrupt signal is generated once (if INTEN is 1) and CNTEN is automatically cleared by hardware
#00
1
The Timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if INTEN is 1)
#01
2
Reserved
#10
3
The Timer is operating in continuous counting mode. The associated interrupt signal is generated when TIMERx_CNT = TIMERx_CMP (if INTEN is 1) however, the 16-bit up-counter counts continuously without reset
#11
PSC
Timer Clock Prescaler
0
8
read-write
RSTCNT
Counter Reset Bit
Set this bit will reset the Timer counter, pre-scale and also force CNTEN to 0.
26
1
read-write
0
No effect
#0
1
Reset Timer's pre-scale counter, internal 16-bit up-counter and CNTEN bit
#1
TIMER0_INTSTS
TIMER0_INTSTS
Timer0 Interrupt Status Register
0x8
-1
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag (Read Only)
This bit indicates the interrupt status of Timer.
TIF bit is set by hardware when the 16-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1 to itself
0
1
read-only
0
No effect
#0
1
CNT (TIMERx_CNT[15:0]) value matches the CMPDAT (TIMERx_CMP[15:0]) value
#1
TIMER1_CMP
TIMER1_CMP
Timer1 Compare Register
0x24
-1
read-write
n
0x0
0x0
TIMER1_CNT
TIMER1_CNT
Timer1 Data Register
0x2C
-1
read-write
n
0x0
0x0
TIMER1_CTL
TIMER1_CTL
Timer1 Control and Status Register
0x20
-1
read-write
n
0x0
0x0
TIMER1_INTSTS
TIMER1_INTSTS
Timer1 Interrupt Status Register
0x28
-1
read-write
n
0x0
0x0
TIMER2_CMP
TIMER2_CMP
Timer2 Compare Register
0x44
-1
read-write
n
0x0
0x0
TIMER2_CNT
TIMER2_CNT
Timer2 Data Register
0x4C
-1
read-write
n
0x0
0x0
TIMER2_CTL
TIMER2_CTL
Timer2 Control and Status Register
0x40
-1
read-write
n
0x0
0x0
TIMER2_INTSTS
TIMER2_INTSTS
Timer2 Interrupt Status Register
0x48
-1
read-write
n
0x0
0x0
TIMERF_INTSTS
TIMERF_INTSTS
TimerF Interrupt Status Register
0x30
-1
read-write
n
0x0
0x0
TFIE
TimerF Interrupt Enable
1
1
read-write
0
Disable TimerF Interrupt
#0
1
Enable TimerF Interrupt
#1
TFIF
TimerF Interrupt Flag
This bit indicates the interrupt status of TimerF.
TFIF bit is set by hardware when TimerF time out. It is cleared by writing 1 to this bit.
0
1
read-write
0
It indicates that TimerF does not time out yet
#0
1
It indicates that TimerF time out. The interrupt flag is set if TimerF interrupt was enabled
#1
WDT
WDT Register Map
WDT
0x0
0x0
0x4
registers
n
CTL
WDT_CTL
Watchdog Timer Control Register
0x0
-1
read-write
n
0x0
0x0
IF
Watchdog Timer Interrupt Flag
If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed.
Note: This bit is cleared by writing 1 to this bit.
3
1
read-write
0
Watchdog timer interrupt has not occurred
#0
1
Watchdog timer interrupt has occurred
#1
INTEN
Watchdog Time-Out Interrupt Enable
6
1
read-write
0
Disable the WDT time-out interrupt
#0
1
Enable the WDT time-out interrupt
#1
RSTCNT
Clear Watchdog Timer
Set this bit will clear the Watchdog timer.
Note: This bit will auto clear after few clock cycles
0
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Reset the contents of the Watchdog timer
#1
RSTEN
Watchdog Timer Reset Enable
Setting this bit will enable the Watchdog timer reset function.
Note: This function cannot work with XTL32-based clock source.
1
1
read-write
0
Disable Watchdog timer reset function
#0
1
Enable Watchdog timer reset function
#1
RSTF
Watchdog Timer Reset Flag
When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is disabled, then the Watchdog timer has no effect on this bit.
Note: This bit is cleared by writing 1 to this bit.
2
1
read-write
0
Watchdog timer reset has not occurred
#0
1
Watchdog timer reset has occurred
#1
TOUTSEL
Watchdog Timer Interval Select
These three bits select the timeout interval for the Watchdog timer, a watchdog reset will occur 1024 clock cycles later if Watchdog timer is not reset.
The WDT interrupt timeout is given by:
Where WDT_CLK is the period of the Watchdog Timer clock source.
8
3
read-write
0
24 * WDT_CLK
#000
1
26 * WDT_CLK
#001
2
28 * WDT_CLK
#010
3
210 * WDT_CLK
#011
4
212 * WDT_CLK
#100
5
214 * WDT_CLK
#101
6
216 * WDT_CLK
#110
7
218 * WDT_CLK
#111
WDTEN
Watchdog Timer Enable
7
1
read-write
0
Disable the WDT(Watchdog timer) (This action will reset the internal counter)
#0
1
Enable the WDT(Watchdog timer)
#1
WKEN
WDT Time-Out Wake-Up Function Control
If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
4
1
read-write
0
Disable WDT Wakeup CPU function
#0
1
Enable the Wakeup function that WDT timeout can wake up CPU from power-down mode
#1
WKF
WDT Time-Out Wake-Up Flag
If WDT causes CPU wake up from sleep or power-down mode, this bit will be set to high.
Note: This bit is cleared by writing 1 to it.
5
1
read-write
0
WDT does not cause CPU wake-up
#0
1
CPU wakes up from sleep or power-down mode by WDT time-out interrupt
#1