nuvoTon N570J_v1 2024.05.05 N570J_v1 SVD file 8 32 ADC ADC Register Map ADC 0x0 0x0 0x38 registers n 0x3C 0xC registers n CHSEQ ADC_CHSEQ A/D Channel Sequence Register 0x24 -1 read-write n 0x0 0x0 CHSEQ0 Select Channel N As The 1st Conversion In Scan Sequence 0 4 read-write CHSEQ1 Select Channel N As The 2nd Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 4 4 read-write CHSEQ2 Select Channel N As The 3rd Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 8 4 read-write CHSEQ3 Select Channel N As The 4th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 12 4 read-write CHSEQ4 Select Channel N As The 5th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 16 4 read-write CHSEQ5 Select Channel N As The 6th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 20 4 read-write CHSEQ6 Select Channel N As The 7th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 24 4 read-write CHSEQ7 Select Channel N As The 8th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 28 4 read-write CMP0 ADC_CMP0 A/D Compare Register 0 0x28 -1 read-write n 0x0 0x0 ADCMPEN Compare Enable Set this bit to 1 to enable the comparison CMPDAT with specified channel conversion result when converted data is loaded into ADC_DAT register. 0 1 read-write 0 Disable compare #0 1 Enable compare #1 ADCMPIE Compare Interrupt Enable When converted data in RESULT is less (or greater) than the compare data CMPDAT, ADCMPF bit is asserted. If ADCMPIE is set to 1, a compare interrupt request is generated. 1 1 read-write 0 Disable #0 1 Enable #1 CMPCH Compare Channel Selection 3 3 read-write 0 Channel 0 conversion result is selected to be compared #000 1 Channel 1 conversion result is selected to be compared #001 2 Channel 2 conversion result is selected to be compared #010 3 Channel 3 conversion result is selected to be compared #011 4 Channel 4 conversion result is selected to be compared #100 5 The conversion result of pre-amplifier output is selected to be compared #101 6 Reserved. #110 7 Channel 7 conversion result is selected to be compared #111 CMPCOND Compare Condition 2 1 read-write 0 ADCMPFx bit is set if conversion result is less than CMPDAT #0 1 ADCMPFx bit is set if conversion result is greater or equal to CMPDAT, #1 CMPDAT Compare Data This field possessing the 5 MSB of 12-bit compare data, and 7 LSB are treated as '0', is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software. The data format should be consistent with the setting of ADCFM bit. 23 5 read-write CMPMCNT Compare Match Count When the specified A/D channel analog conversion result matches the comparing condition, the internal match counter will increase 1. When the internal counter achieves the setting, (CMPMCNT+1) hardware will set the ADCMPF bit. 8 4 read-write CMP1 ADC_CMP1 A/D Compare Register 1 0x2C -1 read-write n 0x0 0x0 CTL ADC_CTL A/D Control Register 0x20 -1 read-write n 0x0 0x0 ADCEN A/D Converter Enable Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption. 0 1 read-write 0 Disable #0 1 Enable #1 ADCFM Data Format Of ADC Conversion Result 12 1 read-write 0 Unsigned #0 1 2'Complemet #1 ADCIE A/D Interrupt Enable A/D conversion end interrupt request is generated if ADCIE bit is set to 1. 1 1 read-write 0 Disable A/D interrupt function #0 1 Enable A/D interrupt function #1 DS_1CH 18 1 read-write 0 2channel #0 1 1channel #1 DS_EN Down Sample Function Enable 19 1 read-write 0 Down sample function is disabled #0 1 Down sample function is enabled. When this field is set, ADC will be forced to continuous scan mode, no matter what is specified in field OPMODE (ADC_CTL [3:2]) #1 DS_RATE Down Sample Rate 16 2 read-write 0 Down sample X2 #00 1 Down sample X4 #01 2 Down sample X8 #10 3 Down sample X16 #11 HP_EN High-pass Filter Enable Note: HP_EN suggest to be used only when DS_EN enable. 23 1 read-write 0 High-pass filter is disabled #0 1 High-pass filter is enabled (must in continuous scan mode) #1 HP_FSEL High-pass Filter Frequency Selection: 20 3 read-write 0 Do not remove DC part #000 1 DC part is suppressed by -40dB, -3dB at 0.005 x Sampling Rate #001 2 DC part is suppressed by -40dB, -3dB at 0.010 x Sampling Rate #010 3 DC part is suppressed by -40dB, -3dB at 0.014 x Sampling Rate #011 4 DC part is suppressed by -40dB, -3dB at 0.019 x Sampling Rate #100 5 DC part is suppressed by -40dB, -3dB at 0.023 x Sampling Rate #101 6 DC part is suppressed by -40dB, -3dB at 0.027 x Sampling Rate #110 7 DC part is suppressed by -40dB, -3dB at 0.032 x Sampling Rate #111 OPMODE A/D Converter Operation Mode Note 1: This field will be effective only when DS_EN field in this register is set as '0'. When DS_EN is set as '1', ADC conversion will be forced to 'continuous scan mode' Note 2: When changing the operation mode, software should disable SWTRG bit firstly. 2 2 read-write 0 Single conversion #00 1 Reserved. #01 2 Single-cycle scan #10 3 Continuous scan #11 PDMAEN PDMA Transfer Enable Bit When A/D conversion is completed, the converted data is loaded into ADC_DATn (n: 0 ~ 7) register, user can enable this bit to generate a PDMA data transfer request. 4 1 read-write 0 PDMA data transfer Disabled #0 1 PDMA data transfer Enabled #1 SWTRG A/D Conversion Start Note1: SWTRG bit can be reset to 0 by software, or can be cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channel. In continuous scan mode, A/D conversion is continuously performed sequentially until software writes 0 to this bit or chip resets. Note2: Before trigger SWTRG to start ADC convert , the ADC relative setting should be completed. 11 1 read-write 0 Conversion is stopped and A/D converter enters idle state #0 1 Start conversion #1 DAT0 ADC_DAT0 A/D Data Register for the Channel Defined in CHSEQ0 0x0 -1 read-only n 0x0 0x0 EXTS Extension Bits Of RESULT for Different Data Format If ADCFM is '0', EXTS all are read as '0'. If ADCFM is '1', EXTS all are read as bit RESULT [11]. 12 4 read-only OV Over Run Flag If converted data in RESULT [11:0] have not been read before new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after ADC_DAT register is read. 16 1 read-only 0 Data in RESULT are recent conversion result #0 1 Data in RESULT are overwritten #1 RESULT A/D Conversion Result This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit. 0 12 read-only VALID Valid Flag This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read. 17 1 read-only 0 Data in RESULT are not valid #0 1 Data in RESULT are valid #1 DAT1 ADC_DAT1 A/D Data Register for the Channel Defined in CHSEQ1 0x4 -1 read-write n 0x0 0x0 DAT2 ADC_DAT2 A/D Data Register for the Channel Defined in CHSEQ2 0x8 -1 read-write n 0x0 0x0 DAT3 ADC_DAT3 A/D Data Register for the Channel Defined in CHSEQ3 0xC -1 read-write n 0x0 0x0 DAT4 ADC_DAT4 A/D Data Register for the Channel Defined in CHSEQ4 0x10 -1 read-write n 0x0 0x0 DAT5 ADC_DAT5 A/D Data Register for the Channel Defined in CHSEQ5 0x14 -1 read-write n 0x0 0x0 DAT6 ADC_DAT6 A/D Data Register for the Channel Defined in CHSEQ6 0x18 -1 read-write n 0x0 0x0 DAT7 ADC_DAT7 A/D Data Register for the Channel Defined in CHSEQ7 0x1C -1 read-write n 0x0 0x0 HWPARA ADC_HWPARA ADC H/W Parameter Control Register 0x44 -1 read-write n 0x0 0x0 CONV_N Specify ADC conversion clock number CONV_N has to be equal to or great than 11. To update this field, programmer can only revise bit [14:8] and keep other bits the same as before. Note: CONV_N valid range is from 11~127 8 7 read-write SHCLK_N Specify the high level of ADC start signal. Note: Suggested and default value is 0. 0 6 read-write PDMADAT ADC_PDMADAT ADC PDMA Result Register 0x34 -1 read-write n 0x0 0x0 PDMA_RESULT ADC PDMA transfer data If DS_EN is '0' and HPF_EN is '0', transfer SAR output to SRAM If DS_EN is '1' and HPF_EN is '0', transfer DS output to SRAM If HPF_EN is '1', transfer HPF output to SRAM 0 16 read-write PGCTL ADC_PGCTL ADC Pre-amplifier Gain Control Register 0x3C -1 read-write n 0x0 0x0 EN_PGA PGA enable control 0: Disable PGA 1: Enable PGA 10 1 read-write IBGEN_TRIM Set to 0 12 2 read-write MICB_EN MICBIAS enable 0: Disable MIC_BIAS 1: Enable MIC_BIAS 16 1 read-write MICB_VSEL Select MIC BIAS level. 17 2 read-write 0 90% of VCCA 0 1 65% of VCCA 1 2 75% of VCCA 2 3 50% of VCCA 3 MICN2PGA MICN input enable 0 : disable(open) 1 : enable( short) 31 1 read-write MICP2PGA MICP input enable 0 : disable(open) 1 : enable( short) 30 1 read-write MUTE_PGA PGA mute/unmute control 0: UNMUTE PGA 1: MUTE PGA 0 1 read-write PD_IBEN Analog bias power control 0: Power on analog bias generation 1: Power down analog bias generation 11 1 read-write PGA_SEL PGA Gain Selection. Range -18dB to +45dB, 1dB per step. 24 6 read-write 0 -18dB 0x00 18 0dB 0x12 63 45dB 0x3f SAR_VREF ADC VREF Selection 9 1 read-write ZERO_CROSS Zero cross enable control 0: immediate 1: Gain update only on zero crossing. 3 1 read-write STATUS ADC_STATUS A/D Status Register 0x30 -1 read-write n 0x0 0x0 ADCMPF0 Compare Flag When the selected channel A/D conversion result meets setting conditions in ADC_CMP0, then this bit is set to 1. And it is cleared by write 1. 1 1 read-write 0 Converted result RESULT in ADC_DAT does not meet ADC_CMP0 setting #0 1 Converted result RESULT in ADC_DAT meets ADC_CMP0 setting, #1 ADCMPF1 Compare Flag When the selected channel A/D conversion result meets setting conditions in ADC_CMP1, then this bit is set to 1. And it is cleared by write 1. 2 1 read-write 0 Converted result RESULT in ADC_DAT does not meet ADC_CMP1 setting #0 1 Converted result RESULT in ADC_DAT meets ADC_CMP1 setting, #1 ADIF A/D Conversion End Flag A status flag that indicates the end of A/D conversion. ADIF is set to 1 under the following two conditions: When A/D conversion ends in single mode, When A/D conversion ends on all channels specified by channel sequence register in scan mode. And it is cleared when 1 is written. 0 1 read-write BUSY BUSY/IDLE This bit is mirror of SWTRG bit in ADC_CTL. It is read only. 3 1 read-write 0 A/D converter is in idle state #0 1 A/D converter is busy at conversion #1 CHANNEL Current Conversion Channel It is read only. 4 3 read-write OV Over Run Flag It is a mirror to OV bit in ADC_DATn. 16 8 read-write VALID Data Valid Flag It is a mirror of VALID bit in ADC_DATn. 8 8 read-write VMID ADC_VMID ADC VMID Control Register 0x40 -1 read-write n 0x0 0x0 PDHIRES 0: Enable high resistance VMID reference. 1: Disconnect high resistance VMID reference. 2 1 read-write PDLOWRES 0: Enable low resistance VMID reference. 1: Disconnect low resistance VMID reference. 1 1 read-write PULLDWN 0: Disable pull down VMID. 1: Enable pull down VMID reference to 0V. 0 1 read-write CLK CLK Register Map CLK 0x0 0x0 0x1C registers n 0x20 0x8 registers n AHBCLK CLK_AHBCLK AHB Device Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 ISPCKEN Flash ISP Controller Clock Enable Control. The Flash ISP engine clock always is from 49 MHz RC oscillator. 2 1 read-write 0 Flash ISP engine clock Disabled #0 1 Flash ISP engine clock Enabled #1 PDMACKEN PDMA Clock Enable Control 0 1 read-write 0 PDMA engine clock Disabled #0 1 PDMA engine clock Enabled #1 SPIMCKEN SPIM Clock Enable Control 1 1 read-write 0 SPIM engine clock Disabled #0 1 SPIM engine clock Enabled #1 UARTEN UART Controller Clock Enable Control.(It works on APB) 3 1 read-write 0 UART engine clock Disabled #0 1 UART engine clock Enabled #1 APBCLK CLK_APBCLK APB Device Clock Enable Control Register 0x8 -1 read-write n 0x0 0x0 ADC_EN Audio Analog-Digital-Converter (ADC) Clock Enable Control 28 1 read-write 0 ADC clock Disabled #0 1 ADC clock Enabled #1 CSCAN_EN CSCAN clock enable control 30 1 read-write 0 CSCAN clock Disabled #0 1 CSCAN clock Enabled #1 DPWM_EN DPWM Clock Enable Control 29 1 read-write 0 DPWM clock Disabled #0 1 DPWM clock Enabled #1 PWM0_EN PWM0 Block Clock Enable Control 20 1 read-write 0 PWM0 clock Disabled #0 1 PWM0 clock Enabled #1 PWM1_EN PWM1 Block Clock Enable Control 21 1 read-write 0 PWM1 clock Disabled #0 1 PWM1 clock Enabled #1 RTC_EN Real-Time-Clock APB Interface Clock Control This bit is used to control the RTC APB clock only. The RTC engine clock source is from the LIRC and LXT (selected by RTCSEL (CLK_CLKSEL1 [24])). 1 1 read-write 0 RTC clock Disabled #0 1 RTC clock Enabled #1 SPI0_EN SPI0 Clock Enable Control 12 1 read-write 0 SPI0 clock Disabled #0 1 SPI0 clock Enabled #1 TMR0_EN Timer0 Clock Enable Control 2 1 read-write 0 Timer0 clock Disabled #0 1 Timer0 clock Enabled #1 TMR1_EN Timer1 Clock Enable Control 3 1 read-write 0 Timer1 clock Disabled #0 1 Timer1 clock Enabled #1 TMR2_EN Timer2 Clock Enable Control 4 1 read-write 0 Timer2 clock Disabled #0 1 Timer2 clock Enabled #1 TMRF_EN TimerF Clock Enable Control 5 1 read-write 0 TimerF clock Disabled #0 1 TImerF clock Enabled #1 WDT_EN Watchdog Clock Enable Control This bit is the protected bit. To program this bit needs an open lock sequence, write '59h', '16h', '88h' to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100. 0 1 read-write 0 WDT clock Disabled #0 1 WDT clock Enabled #1 CLKDIV CLK_CLKDIV Clock Divider Number Register 0x18 -1 read-write n 0x0 0x0 ADCDIV ADC Clock Divide Number From ADC Clock Source The ADC engine clock must meet the constraint: ADCLK ( HCLK/2. 16 7 read-write HCLKDIV HCLK Clock Divide Number From HCLK Clock Source 0 4 read-write UARTDIV UART Clock Divide Number From HCLK Clock Source Note: UART engine clock must bigger or equal to HCLK. 4 4 read-write CLKSEL0 CLK_CLKSEL0 Clock Source Select Control Register 0 0x10 -1 read-write n 0x0 0x0 FCLK_MUX_STATE These register state shows the current HCLK is from which source clock Others reserved. 16 3 read-write 1 from HIRC #001 2 from LXT #010 4 from LIRC #100 HCLKSEL HCLK Clock Source Select Note: 1. When power on, HIRC is selected as HCLK clock source. 2. Before clock switch, the related clock sources (pre-select and new-select) must be turned on. 0 3 read-write 0 clock source from HIRC #000 1 clock source from LXT #001 2 clock source from LIRC #010 7 clock source from HIRC #111 STICKSEL SYS_TICK Clock Source Select Note: 1. When power on, HIRC is selected as HCLK clock source. 2. Before clock switch, the related clock sources (pre-select and new-select) must be turned on. 3 2 read-write 0 clock source from HIRC #00 1 clock source from LIRC #01 2 clock source from LXT #10 3 clock source from HCLK #11 CLKSEL1 CLK_CLKSEL1 Clock Source Select Control Register 1 0x14 -1 read-write n 0x0 0x0 ADCSEL ADC Clock Source Select 2 2 read-write 0 Clock source from HCLK #00 1 Clock source from HCLK. Clock source from HIRC #01 CSCANSEL CSCAN Clock Source Select 26 1 read-write 0 Clock source from LIRC #0 1 Clock source from LXT #1 PWM0SEL PWM Timer Clock Source Select 28 2 read-write 0 Clock source from HCLK #00 1 Clock source from LXT #01 2 Clock source from LIRC #10 3 Clock source from HIRC #11 PWM1SEL PWM Timer Clock Source Select 30 2 read-write 0 Clock source from HCLK #00 1 Clock source from LXT #01 2 Clock source from LIRC #10 3 Clock source from HIRC #11 RTCSEL RTC Clock Source Select 24 1 read-write 0 Clock source from LIRC #0 1 Clock source from LXT #1 TMR0SEL Timer0 Clock Source Select 8 3 read-write 0 Clock source from HCLK #000 1 Clock source from LXT. Clock source from HIRC #001 2 Clock source from LIRC #010 3 Clock source from External Trigger #011 TMR1SEL Timer1 Clock Source Select 12 3 read-write 0 Clock source from HCLK #000 1 Clock source from LXT. Clock source from HIRC #001 2 Clock source from LIRC #010 3 Clock source from External Trigger #011 TMR2SEL Timer2 Clock Source Select 16 3 read-write 0 Clock source from HCLK #000 1 Clock source from LXT. Clock source from HIRC #001 2 Clock source from LIRC #010 3 Equivalent with '000' #011 TMRFSEL TimerF Clock Source Select 20 3 read-write 0 Clock source from external LXT / 32, #000 1 Clock source from external LXT / (4x32) #001 2 Clock source from external LIRC / 32, #010 3 Clock source from external LIRC / (4x32) #011 6 Clock source from HIRC / 32768 #110 7 Clock source from HIRC / (4x32768) #111 UARTSEL UART Clock Source Select 25 1 read-write 0 Clock source from HCLK #0 1 Clock source from HIRC #1 WDTSEL Watchdog Timer Clock Source Selection (Write Protect) These bits are protected bits. To program these bits needs an open lock sequence, write '59h', '16h', '88h' to SYS_REGLCTL to un-lock these bits. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.. 0 2 read-write 0 Clock source from LIRC #00 1 Clock source from LXT #01 2 Clock source from HCLK/2048 #10 3 Clock source from HIRC #11 DPDFLR CLK_DPDFLR DPD State Register and Flash Regulator Control 0xC -1 read-write n 0x0 0x0 PD Flash Regulator Enable control. 0: Power Up Flash LDO regulator. 1: Power Down Flash LDO regulator. Note: When power down flash LDO and no external power at VCCB pin, the IO pull low discharge register(INT_BA+0x80 [7]) suggest to enable. 31 1 read-write PD_STATE An 8bit register that is preserved when DPD (Deep Power Down) state is entered and after wakeup is available by reading PD_STATE_RB. 0 8 read-write PD_STATE_RB Current values of PD_STATE register. 8 8 read-write VSET Flash Regulator Voltage control. 0:1.8V, 1:2.4V, 2:2.5V, 3:2.7V, 4:3V, 5:3.3V, 6:1.5V, 7:1.7V 24 3 read-write PFLAG CLK_PFLAG Power Down Flag Register 0x24 -1 read-write n 0x0 0x0 DS_FLAG Device has been in DEEP_SLEEP mode - write '1' to clear 0 1 read-write STOP_FLAG Device has been in STOP mode - write '1' to clear. 1 1 read-write PWRCTL CLK_PWRCTL System Power Control Register 0x0 -1 read-write n 0x0 0x0 DEEP_PD Deep Power Down (DPD) bit. Set to '1' and issue WFI/WFE instruction to enter DPD mode. 10 1 read-write DPD_10K 17 1 read-write FLASH_PWR Determine whether FLASH memory enters deep power down. FLASH_PWR [0]: 1: flash enters deep power down upon DEEP_SLEEP FLASH_PWR [1]: 1: flash enters deep power down upon STOP mode. If FLASH_PWR is selected for a power state mode, current consumption is reduced, but a 10us wakeup time must be added to the wakeup sequence. Trade-off is wakeup time for standby power. 18 2 read-write FWK_EN STOP/DeepSleep mode fast wakeup enable control 0 1 read-write 0 normal wake up #0 1 fast wake up (default) #1 IO_FWK All IO pin is enabled fast wakeup in STOP/DeepSleep mode. 7 1 read-write 0 slow wakeup #0 1 fast wakeup #1 OSC10K_EN Internal 10kHz Oscillator Control After reset, this bit is '0'. 12 1 read-write 0 Internal 10 KHz oscillator Disabled #0 1 Internal 10 KHz oscillator Enabled #1 OSC49M_EN Internal 49.152 MHz RC Oscillator Control After reset, this bit is '1'. 2 1 read-write 0 49.152 MHz oscillation Disabled #0 1 49.152 MHz oscillation Enabled #1 STOP STOP mode bit. Set to '1' and issue WFI/WFE instruction to enter STOP mode. 9 1 read-write TIMER_SEL Select WAKEUP Timer: 20 4 read-write TIMER_SEL_RD Read-Only. Read back of the current WAKEUP timer setting. This value is updated with TIMER_SEL upon entering DPD mode. 28 4 read-write TIMER_WU Read Only. This flag indicates that wakeup of device was requested with TIMER count of the 10Khz oscillator. Flag is cleared when DPD mode is entered or any of the DPD bits of RSTSRC register (RSTSRC [10:8]) are cleared. 25 1 read-write VSET Adjusts the digital supply voltage. Should be left as default . 13 3 read-write XTL32K_EN External 32.768 kHz Crystal Control After reset, this bit is '0'. 1 1 read-write 0 External 32.768 KHz crystal Disabled #0 1 External 32.768 KHz crystal Enabled #1 XTL32K_FILTER Filter the XTL32K output clock Note 1: High level of XTL32K must keep 112 HCLK for recognition valid, when this bit is enabled. Note 2: Should be disabled when enter power down. 3 1 read-write 0 Disable, XTL32K output clock without filter #0 1 Enable, XTL32K output clock will be filtered to avoid glitches #1 STATUS CLK_STATUS Clock Status Monitor Register 0x20 -1 read-only n 0x0 0x0 HIRCSTB HIRC clock source stable flag(Read only) 2 1 read-only 0 Internal high speed RC oscillator (HIRC) clock is not stable or disabled #0 1 Internal high speed RC oscillator (HIRC) clock is stable and enabled #1 LIRCSTB LIRC Clock Source Stable Flag (Read Only) 1 1 read-only 0 Internal low speed RC oscillator (LIRC) clock is not stable or disabled #0 1 Internal low speed RC oscillator (LIRC) clock is stable and enabled #1 LXTSTB LXT Clock Source Stable Flag (Read Only) 0 1 read-only 0 External low speed crystal oscillator (LXT) clock is not stable or disabled #0 1 External low speed crystal oscillator (LXT) clock is stabled and enabled #1 CSCAN CSCAN Register Map CSCAN 0x0 0x0 0x30 registers n COUNT CSCAN_COUNT CSCAN Count Status Register 0x8 -1 read-write n 0x0 0x0 COUNT CSCAN Count Count result of single scan. 0 16 read-write CTRL CSCAN_CTRL CSCAN Control Register 0x0 -1 read-write n 0x0 0x0 CMPEN Compare Enable Note: When disable Compare function , the touch will always issue an interrupt after one scan cycle finish. 28 1 read-write 0 Disable Compare function #0 1 Enable Compare function #1 CMPLOW 8 7 read-write 0 Counter result higher than threshold will issue interrupt when CMP_EN = 1'b 0 1 Counter result lower than threshold will issue interrupt when CMP_EN = 1'b 1 CMPLOWS 15 1 read-write 0 Counter result higher than threshold will issue interrupt when CMP_EN = 1'b #0 1 Counter result lower than threshold will issue interrupt when CMP_EN = 1'b #1 CURRENT CSCAN Oscillator current Controls the analog bais current of the capacitive relaxation oscillator. 0: Level0 1: Level1 2: Level3 3: Level4 Note: Level0 is the smallest current ,and Level4 is the largest current. 16 2 read-write DURCNT CSCAN Duration Count This counter is used to set a wakeup time after a capacitive sensing scan is complete. It is in units of low frewquency clock period (either LXT or LIRC clock) and gives delay of 160, 320, 480,640, 800, 960, 1120, 1280, 1440,1600, 1920, 2240, 2560, 2880,3200 3840 periods for settings 0,..,15. 24 4 read-write EN CSCAN Enable Write 1 to start. Reset by hardware when operation finished. 30 1 read-write INTEN CSCAN Enable Interrupt 20 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MODE0 CSCAN Mode0 22 1 read-write 0 Single shot Capacitive sense #0 1 Scans each channel set in SCAN_MASK and stores in Register #1 MODE1 CSCAN Mode1 Note: When enable compare function , the DUR_CNT is ignore.Iterrupt always happens when scan fisish. 23 1 read-write 0 Interrupt when scan finished #0 1 Interrupt when DUR_CNT delay occurs #1 PD Power Down 0: Enable analog circuit 1: Power down analog circuit and block. 31 1 read-write SEL CSCAN Select In single mode selects the channel to perform measurement on. 0 7 read-write SLOWCLK CSCAN Slow Clock **Notes: In low speed mode, for CYCLE_CNT 5, the minimum frequency of oscillation of a CAPSENSE GPIO must be Fclk/2. Where Fclk is the frequency of LXT or LIRC depending which is selected as reference. 21 1 read-write 0 Timebase clock is HIRC #0 1 Timebase clock is LIRC (XTAL32K_EN = 0) or XTAL (XTAL32K_EN = 1) #1 TOINTEN Timeout interrupt enable 29 1 read-write 0 Timeout Interrupt disabled #0 1 Timeout Interrupt enabled #1 CYCCNT CSCAN_CYCCNT CSCAN Cycle Count Control Register 0x4 -1 read-write n 0x0 0x0 CYCCNT CSCAN Cycle Count 0 4 read-write MASK Scan Mask Register If MASK[n] is set then touch channel[n] is included in scan of capacitive sensing. 16 7 read-write INT CSCAN_INT CSCAN Interrupt Register 0xC -1 read-write n 0x0 0x0 CMPINT 16 7 read-write CMPINTS 23 1 read-write INT CSCAN Flag active Write '1' to clear. 0 1 read-write TOINT If the the touch channel[n] is timeout, the [n+1] bit will set to 1'b 8 7 read-write TOINTS If the the touch channel[n] is timeout, the [n+1] bit will set to 1'b 15 1 read-write RESULT0 CSCAN_RESULT0 CSCAN Counter Result Register 0 0x10 -1 read-write n 0x0 0x0 CNT0 Channel 0 Counter result register 0 16 read-write CNT1 Channel 1 Counter result register 16 16 read-write RESULT1 CSCAN_RESULT1 CSCAN Counter Result Register 1 0x14 -1 read-write n 0x0 0x0 CNT2 Channel 2 Counter result register 0 16 read-write CNT3 Channel 3 Counter result register 16 16 read-write RESULT2 CSCAN_RESULT2 CSCAN Counter Result Register 2 0x18 -1 read-write n 0x0 0x0 CNT4 Channel 4 Counter result register 0 16 read-write CNT5 Channel 5 Counter result register 16 16 read-write RESULT3 CSCAN_RESULT3 CSCAN Counter Result Register 3 0x1C -1 read-write n 0x0 0x0 CNT6 Channel 6 Counter result register 0 16 read-write THRESHOLD0 CSCAN_THRESHOLD0 CSCAN Compare Threshold Register 0 0x20 -1 read-write n 0x0 0x0 CTH0 Channel 0 compare threshold setting A 16 bits threshold value can be set by user 0 16 read-write CTH1 Channel 1 compare threshold setting A 16 bits threshold value can be set by user 16 16 read-write THRESHOLD1 CSCAN_THRESHOLD1 CSCAN Compare Threshold Register 1 0x24 -1 read-write n 0x0 0x0 CTH2 Channel 2 compare threshold setting A 16 bits threshold value can be set by user 0 16 read-write CTH3 Channel 3 compare threshold setting A 16 bits threshold value can be set by user 16 16 read-write THRESHOLD2 CSCAN_THRESHOLD2 CSCAN Compare Threshold Register 2 0x28 -1 read-write n 0x0 0x0 CTH4 Channel 4 compare threshold setting A 16 bits threshold value can be set by user 0 16 read-write CTH5 Channel 5 compare threshold setting A 16 bits threshold value can be set by user 16 16 read-write THRESHOLD3 CSCAN_THRESHOLD3 CSCAN Compare Threshold Register 3 0x2C -1 read-write n 0x0 0x0 CTH6 Channel 6 compare threshold setting A 16 bits threshold value can be set by user 0 16 read-write CTHS A 16 bits threshold value can be set by user 16 16 read-write DPWM DPWM Register Map DPWM 0x0 0x0 0x14 registers n CTL DPWM_CTL DPWM Control Register 0x0 -1 read-write n 0x0 0x0 DEADTIME DPWM Driver Deadtime Control. Enabling this bit will insert an additional clock cycle deadtime into the switching of PMOS and NMOS driver transistors. 3 1 read-write DITHEREN DPWM Signal Dither Control To prevent structured noise on PWM output due to DC offsets in the input signal it is possible to add random dither to the PWM signal. These bits control the dither: 0: No dither. 1: 1 bit dither 3: 2 bit dither 4 2 read-write DPWMEN DPWM Enable. 0: Disable DPWM, SPK pins are tristate, CIC filter is reset, FIFO pointers are reset (FIFO data is not reset). 1: Enable DPWM, SPK pins are enabled and driven, data is taken from FIFO. Note : This field will be effective only when DAC_EN field in this register is set as '0'. 6 1 read-write MODUFRQ DPWM Modulation Frequency. 0 3 read-write RXTH DPWM FIFO threshold If the valid data count of the DPWM FIFO buffer is less than or equal to RXTH setting, the RXTHF bit will set to 1, else the RXTHF bit will be cleared to 0. 9 4 read-write RXTHIE DPWM FIFO threshold interrupt 0: DPWM FIFO threshold interrupt Disabled. 1: DPWM FIFO threshold interrupt Enabled. 8 1 read-write ZCIE Zero cross enable 0: output data doesn't cross zero point 1: output data cross zero point 14 1 read-write DATA DPWM_DATA DPWM FIFO Input Register 0xC -1 write-only n 0x0 0x0 INDATA DPWM FIFO Audio Data Input A write to this register pushes data onto the DPWM FIFO and increments the write pointer. This is the address that PDMA writes audio data to. 0 16 write-only DMACTL DPWM_DMACTL DPWM PDMA Control Register 0x8 -1 read-write n 0x0 0x0 DMAEN Enable DPWM DMA Interface. 0 1 read-write 0 Disable PDMA. No requests will be made to PDMA controller #0 1 Enable PDMA. Block will request data from PDMA controller whenever FIFO is not empty #1 STS DPWM_STS DPWM FIFO Status Register 0x4 -1 read-only n 0x0 0x0 EMPTY FIFO Empty 1 1 read-only 0 FIFO is not empty #0 1 FIFO is empty #1 FIFO_POINTER DPWM FIFO Pointer (Read Only) The FULL bit and FIFO_POINTER [3:0] indicates the field that the valid data count within the DPWM FIFO buffer. The Maximum value shown in FIFO_POINTER is 15. When the using level of DPWM FIFO Buffer equal to 16, The FULL bit is set to 1. 3 4 read-only FULL FIFO Full 0 1 read-only 0 FIFO is not full #0 1 FIFO is full #1 RXTHF DPWM FIFO threshold Interrupt Status (Read Only) 2 1 read-only 0 The valid data count within the DPWM FIFO buffer is larger than the setting value of RXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of RXTH #1 ZOHDIV DPWM_ZOHDIV DPWM Zero Order Hold Division Register 0x10 -1 read-write n 0x0 0x0 GAIN (GAIN[7:0]+1)/256 8 8 read-write ZOH_DIV DPWM Zero Order Hold, down-sampling divisor. The input sample rate of the DPWM is set by HCLK frequency and the divisor set in this register by the following formula: Valid range is 1,..,255. Default is 48, which gives a sample rate of 16kHz for a 49.152 MHz (default) HCLK. 0 8 read-write FMC FMC Register Map FMC 0x0 0x0 0x18 registers n DFBADR FMC_DFBADR Data Flash Base Address 0x14 -1 read-only n 0x0 0x0 DFBA Data Flash Base Address This register reports the data flash starting address. It is a read only register. Data flash size is defined by user configuration, register content is loaded from Config1 when chip is reset. 0 32 read-only ISPADR FMC_ISPADR ISP Address Register 0x4 -1 read-write n 0x0 0x0 ISPADR ISP Address Register This is the memory address register that a subsequent ISP command will access. ISP operation are carried out on 32bit words only, consequently ISPARD [1:0] must be 00b for correct ISP operation. 0 32 read-write ISPCMD FMC_ISPCMD ISP Command Register 0xC -1 read-write n 0x0 0x0 ISPCMD ISP Command 0 6 read-write ISPCTL FMC_ISPCTL ISP Control Register 0x0 -1 read-write n 0x0 0x0 ISPDAT FMC_ISPDAT ISP Data Register 0x8 -1 read-write n 0x0 0x0 ISPDAT ISP Data Register Write data to this register before an ISP program operation. Read data from this register after an ISP read operation 0 32 read-write ISPTRG FMC_ISPTRG ISP Trigger Control Register 0x10 -1 read-write n 0x0 0x0 ISPGO ISP Start Trigger Write 1 to start ISP operation. This will be cleared to 0 by hardware automatically when ISP operation is finished. After triggering an ISP function M0 instruction pipeline should be flushed with a ISB instruction to guarantee data integrity. This is a protected register, user must first follow the unlock sequence see Register Lock Control Register (SYS_REGLCTL)) to gain access. 0 1 read-write 0 ISP operation is finished #0 1 ISP is on going #1 GPIO GPIO Register Map GPIO 0x0 0x0 0x4 registers n 0x10 0x4 registers n 0x18 0xC registers n 0x40 0x4 registers n 0x48 0x4 registers n 0x50 0x4 registers n 0x58 0xC registers n 0x8 0x4 registers n 0x800 0x70 registers n PA0_PDIO PA0_PDIO GPIO PA.n Pin Data Input/Output Register 0x800 -1 read-write n 0x0 0x0 PDIO GPIO Px.n Pin Data Input/Output Writing this bit can control one GPIO pin output value. 0 1 read-write 0 Corresponding GPIO pin set to low #0 1 Corresponding GPIO pin set to high #1 PA10_PDIO PA10_PDIO GPIO PA.n Pin Data Input/Output Register 0x828 -1 read-write n 0x0 0x0 PA11_PDIO PA11_PDIO GPIO PA.n Pin Data Input/Output Register 0x82C -1 read-write n 0x0 0x0 PA12_PDIO PA12_PDIO GPIO PA.n Pin Data Input/Output Register 0x830 -1 read-write n 0x0 0x0 PA13_PDIO PA13_PDIO GPIO PA.n Pin Data Input/Output Register 0x834 -1 read-write n 0x0 0x0 PA14_PDIO PA14_PDIO GPIO PA.n Pin Data Input/Output Register 0x838 -1 read-write n 0x0 0x0 PA15_PDIO PA15_PDIO GPIO PA.n Pin Data Input/Output Register 0x83C -1 read-write n 0x0 0x0 PA1_PDIO PA1_PDIO GPIO PA.n Pin Data Input/Output Register 0x804 -1 read-write n 0x0 0x0 PA2_PDIO PA2_PDIO GPIO PA.n Pin Data Input/Output Register 0x808 -1 read-write n 0x0 0x0 PA3_PDIO PA3_PDIO GPIO PA.n Pin Data Input/Output Register 0x80C -1 read-write n 0x0 0x0 PA4_PDIO PA4_PDIO GPIO PA.n Pin Data Input/Output Register 0x810 -1 read-write n 0x0 0x0 PA5_PDIO PA5_PDIO GPIO PA.n Pin Data Input/Output Register 0x814 -1 read-write n 0x0 0x0 PA6_PDIO PA6_PDIO GPIO PA.n Pin Data Input/Output Register 0x818 -1 read-write n 0x0 0x0 PA7_PDIO PA7_PDIO GPIO PA.n Pin Data Input/Output Register 0x81C -1 read-write n 0x0 0x0 PA8_PDIO PA8_PDIO GPIO PA.n Pin Data Input/Output Register 0x820 -1 read-write n 0x0 0x0 PA9_PDIO PA9_PDIO GPIO PA.n Pin Data Input/Output Register 0x824 -1 read-write n 0x0 0x0 PA_DOUT PA_DOUT GPIO PA Data Output Value 0x8 -1 read-write n 0x0 0x0 DOUT Port [A/B] Pin[N] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output or open-drain mode. Note: PB_DOUT [15:12] are reserved to 0. 0 16 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set 0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set 1 PA_INTEN PA_INTEN GPIO PA Interrupt Enable 0x1C -1 read-write n 0x0 0x0 FLIEN0 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 0 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN1 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 1 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN10 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 10 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN11 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 11 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN12 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 12 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN13 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 13 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN14 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 14 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN15 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 15 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN2 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 2 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN3 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 3 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN4 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 4 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN5 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 5 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN6 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 6 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN7 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 7 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN8 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 8 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN9 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:12] are reserved to 0. 9 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 RHIEN0 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 16 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN1 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 17 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN10 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 26 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN11 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 27 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN12 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 28 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN13 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 29 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN14 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 30 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN15 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 31 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN2 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 18 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN3 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 19 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN4 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 20 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN5 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 21 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN6 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 22 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN7 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 23 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN8 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 24 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN9 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:12] are reserved to 0. 25 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 PA_INTSRC PA_INTSRC GPIO PA Interrupt Source Flag 0x20 -1 read-write n 0x0 0x0 INTSRC Port [A/B] Interrupt Source Flag Read operation: Note: PB_INTSRC [15:12] are reserved to 0. 0 16 read-write 0 No interrupt from Px.n. No action 0 1 Px.n generated an interrupt. Clear the corresponding pending interrupt 1 PA_INTTYPE PA_INTTYPE GPIO PA Interrupt Trigger Type 0x18 -1 read-write n 0x0 0x0 TYPE Port [A/B] Pin[N] Edge Or Level Detection Interrupt Trigger Type Control TYPE[n] is used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is level triggered, the input source is sampled by one HCLK clock to generate the interrupt Note 1: If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set, the setting is ignored and no interrupt will occur Note 2: PB_INTTYPE [15:12] are reserved to 0. 0 16 read-write 0 Edge triggered interrupt 0 1 Level triggered interrupt 1 PA_MODE PA_MODE GPIO PA Pin I/O Mode Control 0x0 -1 read-write n 0x0 0x0 MODE0 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 0 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE1 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 2 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE10 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 20 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE11 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 22 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE12 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 24 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE13 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 26 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE14 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 28 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE15 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 30 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE2 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 4 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE3 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 6 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE4 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 8 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE5 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 10 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE6 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 12 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE7 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 14 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE8 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 16 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE9 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:24] are reserved to 0. 18 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 PA_PIN PA_PIN GPIO PA Pin Value 0x10 -1 read-only n 0x0 0x0 PIN Port [A/B] Pin[N] Pin Values Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: PB_PIN [15:12] are reserved to 0. 0 16 read-only PB0_PDIO PB0_PDIO GPIO PB.n Pin Data Input/Output Register 0x840 -1 read-write n 0x0 0x0 PB10_PDIO PB10_PDIO GPIO PB.n Pin Data Input/Output Register 0x868 -1 read-write n 0x0 0x0 PB11_PDIO PB11_PDIO GPIO PB.n Pin Data Input/Output Register 0x86C -1 read-write n 0x0 0x0 PB1_PDIO PB1_PDIO GPIO PB.n Pin Data Input/Output Register 0x844 -1 read-write n 0x0 0x0 PB2_PDIO PB2_PDIO GPIO PB.n Pin Data Input/Output Register 0x848 -1 read-write n 0x0 0x0 PB3_PDIO PB3_PDIO GPIO PB.n Pin Data Input/Output Register 0x84C -1 read-write n 0x0 0x0 PB4_PDIO PB4_PDIO GPIO PB.n Pin Data Input/Output Register 0x850 -1 read-write n 0x0 0x0 PB5_PDIO PB5_PDIO GPIO PB.n Pin Data Input/Output Register 0x854 -1 read-write n 0x0 0x0 PB6_PDIO PB6_PDIO GPIO PB.n Pin Data Input/Output Register 0x858 -1 read-write n 0x0 0x0 PB7_PDIO PB7_PDIO GPIO PB.n Pin Data Input/Output Register 0x85C -1 read-write n 0x0 0x0 PB8_PDIO PB8_PDIO GPIO PB.n Pin Data Input/Output Register 0x860 -1 read-write n 0x0 0x0 PB9_PDIO PB9_PDIO GPIO PB.n Pin Data Input/Output Register 0x864 -1 read-write n 0x0 0x0 PB_DOUT PB_DOUT GPIO PB Data Output Value 0x48 -1 read-write n 0x0 0x0 PB_INTEN PB_INTEN GPIO PB Interrupt Enable 0x5C -1 read-write n 0x0 0x0 PB_INTSRC PB_INTSRC GPIO PB Interrupt Source Flag 0x60 -1 read-write n 0x0 0x0 PB_INTTYPE PB_INTTYPE GPIO PB Interrupt Trigger Type 0x58 -1 read-write n 0x0 0x0 PB_MODE PB_MODE GPIO PB Pin I/O Mode Control 0x40 -1 read-write n 0x0 0x0 PB_PIN PB_PIN GPIO PB Pin Value 0x50 -1 read-write n 0x0 0x0 INT INT Register Map INT 0x0 0x0 0x54 registers n 0x80 0x4 registers n IRQ0_SRC IRQ0_SRC IRQ0 (WDT) Interrupt Source Identity Register 0x0 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: WDT_INT 0 3 read-only IRQ10_SRC IRQ10_SRC IRQ10 (PWM0) Interrupt Source Identity Register 0x28 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: PWM0_INT 0 3 read-only IRQ11_SRC IRQ11_SRC IRQ11 (PDMA) Interrupt Source Identity Register 0x2C -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: PDMA_INT 0 3 read-only IRQ12_SRC IRQ12_SRC IRQ12 (TimerF) Interrupt Source Identity Register 0x30 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: TimerF_INT 0 3 read-only IRQ13_SRC IRQ13_SRC IRQ13 (RTC) Interrupt Source Identity Register 0x34 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: RTC_INT 0 3 read-only IRQ14_SRC IRQ14_SRC Reserved. 0x38 -1 read-only n 0x0 0x0 IRQ15_SRC IRQ15_SRC IRQ15 (PWM1) Interrupt Source Identity Register 0x3C -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: PWM1_INT 0 3 read-only IRQ16_SRC IRQ16_SRC Reserved. 0x40 -1 read-only n 0x0 0x0 IRQ17_SRC IRQ17_SRC IRQ17 (UART) Interrupt Source Identity Register 0x44 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: UART_INT 0 3 read-only IRQ18_SRC IRQ18_SRC IRQ18 (BOD) Interrupt Source Identity Register 0x48 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: BOD_INT 0 3 read-only IRQ19_SRC IRQ19_SRC IRQ19 (IRCTRIM) Interrupt Source Identity Register 0x4C -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: IRCTRIM_INT 0 3 read-only IRQ1_SRC IRQ1_SRC IRQ1 (DPWM) Interrupt Source Identity Register 0x4 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: DPWM_INT 0 3 read-only IRQ20_SRC IRQ20_SRC IRQ20 (CSCAN) Interrupt Source Identity Register 0x50 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: CSCAN_INT 0 3 read-only IRQ2_SRC IRQ2_SRC IRQ2 (ADC) Interrupt Source Identity Register 0x8 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: ADC_INT 0 3 read-only IRQ3_SRC IRQ3_SRC Reserved. 0xC -1 read-only n 0x0 0x0 IRQ4_SRC IRQ4_SRC IRQ4 (SPIM) Interrupt Source Identity Register 0x10 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: SPIM_INT 0 3 read-only IRQ5_SRC IRQ5_SRC IRQ5 (Timer0) Interrupt Source Identity Register 0x14 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: Timer0_INT 0 3 read-only IRQ6_SRC IRQ6_SRC IRQ6 (Timer1) Interrupt Source Identity Register 0x18 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: Timer1_INT 0 3 read-only IRQ7_SRC IRQ7_SRC IRQ7 (Timer2) Interrupt Source Identity Register 0x1C -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: Timer2_INT 0 3 read-only IRQ8_SRC IRQ8_SRC IRQ8 (GPA/B) Interrupt Source Identity Register 0x20 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: GPB_INT Bit0: GPA_INT 0 3 read-only IRQ9_SRC IRQ9_SRC IRQ9 (SPI0) Interrupt Source Identity Register 0x24 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: SPI0_INT 0 3 read-only NMI_SEL NMI_SEL NMI Source Interrupt Select Control Register 0x80 -1 read-write n 0x0 0x0 IO_DISCHA IO pull low discharge control 7 1 read-write 0 Do not discharge IO output #0 1 Switch pull low discharge resistor to IO output #1 NMI_SEL NMI Source Interrupt Select The NMI interrupt to Cortex-M0 can be selected from one of the interrupt [0:20]. The NMI_SEL bit is used to select the NMI interrupt source. Note: IRQ3 IRQ14 are reserved in N570J. 0 5 read-write OSCFM OSCFM Register Map OSCFM 0x0 0x0 0xC registers n CNT OSCFM_CNT Frequency Measurement Counter Register 0x4 -1 read-only n 0x0 0x0 OSCFM_CNT FM Counter Number Report the counter 0 16 read-only CTL OSCFM_CTL Frequency Measurement Control Register 0x0 -1 read-write n 0x0 0x0 CLK_FM_SEL CLK FM SELETION Note: This bit is cleared by writing 1 to this bit. 0 2 read-write FM_CYC FM Cycle number Note: OSCFM_CYC[7:0] also can write this resister 16 8 read-write FM_DONE FM DONE FLAG If FM_GO is '0', clear the FM_DONE. 2 1 read-write 0 not done or no action #0 1 testing done, #1 FM_GO FM GO BUSY 31 1 read-write 0 no action #0 1 start to frequency measurement #1 CYC OSCFM_CYC Frequency Measurement Cycle Register 0x8 -1 read-write n 0x0 0x0 FM_CYC FM iteration cycle number Note: FM_CYC[7:0] can be overwritten by OSCFM_CTL[23:16] 0 16 read-write PDMA_CH0 PDMA Register Map PDMA 0x0 0x0 0x28 registers n PDMA_BCRx PDMA_BCRx PDMA Channel x Transfer Byte Count Register 0xC -1 read-write n 0x0 0x0 POINT PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction. 0 4 read-only PDMA_CBCRx PDMA_CBCRx PDMA Channel x Current Transfer Byte Count Register 0x1C -1 read-only n 0x0 0x0 CBCR PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs 0 16 read-only PDMA_CDARx PDMA_CDARx PDMA Channel x Current Destination Address Register 0x18 -1 read-only n 0x0 0x0 CDAR PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSARx PDMA_CSARx PDMA Channel x Current Source Address Register 0x14 -1 read-only n 0x0 0x0 CSAR PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSRx PDMA_CSRx PDMA Channel x Control Register 0x0 -1 read-write n 0x0 0x0 PDMA_DARx PDMA_DARx PDMA Channel x Destination Address Register 0x8 -1 read-write n 0x0 0x0 DAR PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned. 0 32 read-write PDMA_IERx PDMA_IERx PDMA Channel x Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 BLKD_IF Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit. 1 1 read-write 0 Transfer ongoing or Idle #0 1 Transfer Complete #1 INTR Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel. 31 1 read-only TABORT_IF PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. Note: This bit is cleared by writing 1 to itself. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 WAR_IF Wrap around transfer byte count interrupt flag. These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits. 8 4 read-write 1 Current transfer finished flag (CBCR==0) #0001 4 Current transfer half complete flag (CBCR==BCR/2) #0100 PDMA_ISRx PDMA_ISRx PDMA Channel x Interrupt Status Register 0x24 -1 read-write n 0x0 0x0 PDMA_POINTx PDMA_POINTx PDMA Channel x Internal buffer pointer Register 0x10 -1 read-only n 0x0 0x0 PDMA_SARx PDMA_SARx PDMA Channel x Source Address Register 0x4 -1 read-write n 0x0 0x0 SAR PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned. 0 32 read-write PDMA_CH1 PDMA Register Map PDMA 0x0 0x0 0x28 registers n PDMA_BCRx PDMA_BCRx PDMA Channel x Transfer Byte Count Register 0xC -1 read-write n 0x0 0x0 POINT PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction. 0 4 read-only PDMA_CBCRx PDMA_CBCRx PDMA Channel x Current Transfer Byte Count Register 0x1C -1 read-only n 0x0 0x0 CBCR PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs 0 16 read-only PDMA_CDARx PDMA_CDARx PDMA Channel x Current Destination Address Register 0x18 -1 read-only n 0x0 0x0 CDAR PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSARx PDMA_CSARx PDMA Channel x Current Source Address Register 0x14 -1 read-only n 0x0 0x0 CSAR PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSRx PDMA_CSRx PDMA Channel x Control Register 0x0 -1 read-write n 0x0 0x0 PDMA_DARx PDMA_DARx PDMA Channel x Destination Address Register 0x8 -1 read-write n 0x0 0x0 DAR PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned. 0 32 read-write PDMA_IERx PDMA_IERx PDMA Channel x Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 BLKD_IF Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit. 1 1 read-write 0 Transfer ongoing or Idle #0 1 Transfer Complete #1 INTR Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel. 31 1 read-only TABORT_IF PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. Note: This bit is cleared by writing 1 to itself. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 WAR_IF Wrap around transfer byte count interrupt flag. These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits. 8 4 read-write 1 Current transfer finished flag (CBCR==0) #0001 4 Current transfer half complete flag (CBCR==BCR/2) #0100 PDMA_ISRx PDMA_ISRx PDMA Channel x Interrupt Status Register 0x24 -1 read-write n 0x0 0x0 PDMA_POINTx PDMA_POINTx PDMA Channel x Internal buffer pointer Register 0x10 -1 read-only n 0x0 0x0 PDMA_SARx PDMA_SARx PDMA Channel x Source Address Register 0x4 -1 read-write n 0x0 0x0 SAR PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned. 0 32 read-write PDMA_GCR PDMA Register Map PDMA 0x0 0x0 0x8 registers n 0xC 0x4 registers n PDMA_GCRCSR PDMA_GCRCSR PDMA Global Control Register 0x0 -1 read-write n 0x0 0x0 HCLK_EN PDMA Controller Channel Clock Enable Control To enable clock for channel n HCLK_EN[n] must be set. 8 2 read-write PDMA_RST PDMA Software Reset Note: This bit can reset all channels (global reset). 0 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will auto clear after several clock cycles #1 PDMA_GCRISR PDMA_GCRISR PDMA Global Interrupt Status Register 0xC -1 read-only n 0x0 0x0 GCRISR Interrupt Pin Status (Read Only) GCRISR[n] is the interrupt status of PDMA channel n. 0 2 read-only PDMA_PDSSR PDMA_PDSSR PDMA Service Selection Control Register 0x4 -1 read-write n 0x0 0x0 ADC_RXSEL PDMA ADC Receive Selection This field defines which PDMA channel is connected to ADC peripheral receive (PDMA source) request. 16 2 read-write 0 No channel select #00 1 Select channel 0 #01 2 Select channel 1 #10 3 Reserved. #11 DPWM_TXSEL PDMA DPWM Transmit Selection This field defines which PDMA channel is connected to DPWM peripheral transmit (PDMA destination) request. 20 2 read-write 0 No channel select #00 1 Select channel 0 #01 2 Select channel 1 #10 3 Reserved. #11 SPI0_RXSEL PDMA SPI0 Receive Selection This field defines which PDMA channel is connected to SPI0 peripheral receive (PDMA source) request. 0 2 read-write 0 No channel select #00 1 Select channel 0 #01 2 Select channel 1 #10 3 Reserved. #11 SPI0_TXSEL PDMA SPI0 Transmit Selection This field defines which PDMA channel is connected to SPI0 peripheral transmit (PDMA destination) request. 4 2 read-write 0 No channel select #00 1 Select channel 0 #01 2 Select channel 1 #10 3 Reserved. #11 SPIM_RXSEL PDMA SPIM Receive Selection This field defines which PDMA channel is connected to SPIM peripheral receive (PDMA source) request. 8 2 read-write 0 No channel select #00 1 Select channel 0 #01 2 Select channel 1 #10 3 Reserved. #11 SPIM_TXSEL PDMA SPIM Transmit Selection This field defines which PDMA channel is connected to SPIM peripheral transmit (PDMA destination) request. 12 2 read-write 0 No channel select #00 1 Select channel 0 #01 2 Select channel 1 #10 3 Reserved. #11 PWM0 PWM Register Map PWM 0x0 0x0 0x18 registers n 0x1C 0x4 registers n 0x28 0x4 registers n 0x34 0x4 registers n 0x40 0x8 registers n 0x50 0x4 registers n 0x58 0x8 registers n 0x7C 0x4 registers n PWM_CAPCTL PWM_CAPCTL Capture Control Register 0x50 -1 read-write n 0x0 0x0 CAPEN Capture Channel Input Transition Enable/Disable When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt. 3 1 read-write 0 Disable capture function #0 1 Enable capture function #1 CAPIF Capture Indication Flag Note:If this bit is '1'(not clear by SW), PWM counter will not be reloaded when next capture event occurs. 4 1 read-write CAPINV Inverter ON/OFF 0 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 CFLIEN Falling Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on falling edge of input. 2 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CFLIF PWM_FCAPDAT Latched Indicator Bit When input channel has a falling transition, PWM_FCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it. 7 1 read-write CRLIEN Rising Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on rising edge of input. 1 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 CRLIF PWM_RCAPDAT Latched Indicator Bit When input channel has a rising transition, PWM_RCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it. 6 1 read-write PWM_CLKDIV PWM_CLKDIV PWM Clock Select Register 0x4 -1 read-write n 0x0 0x0 CLKDIV PWM Timer Clock Source Selection Value : Input clock divided by 000 : 2 001 : 4 010 : 8 011 : 16 1xx : 1 0 3 read-write PWM_CLKPSC PWM_CLKPSC PWM Prescaler Register 0x0 -1 read-write n 0x0 0x0 CLKPSC Clock Prescaler For PWM Timer Clock input is divided by (CLKPSC + 1) 0 8 read-write PWM_CMPDAT0 PWM_CMPDAT0 PWM Comparator Register 0 0x10 -1 read-write n 0x0 0x0 CMP PWM Comparator Register CMP determines the PWM duty ratio. Assumption: PWM output initial is high Note2: Any write to CMP will take effect in next PWM cycle. 0 16 read-write PWM_CMPDAT1 PWM_CMPDAT1 PWM Comparator Register 1 0x1C -1 read-write n 0x0 0x0 PWM_CMPDAT2 PWM_CMPDAT2 PWM Comparator Register 2 0x28 -1 read-write n 0x0 0x0 PWM_CMPDAT3 PWM_CMPDAT3 PWM Comparator Register 3 0x34 -1 read-write n 0x0 0x0 PWM_CNT PWM_CNT PWM Counter Register 0x14 -1 read-only n 0x0 0x0 CNT PWM Counter Register Reports the current value of the 16-bit down counter. 0 16 read-only PWM_CTL PWM_CTL PWM Control Register 0x8 -1 read-write n 0x0 0x0 CNTEN PWM-Timer Enable 0 1 read-write 0 Stop PWM-Timer Running #0 1 Enable PWM-Timer #1 CNTMODE PWM-Timer Auto-Reload/One-Shot Mode 3 1 read-write 0 One-Shot Mode #0 1 Auto-reload Mode #1 PINV PWM-Timer Output Inverter ON/OFF 2 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 PWM_FCAPDAT PWM_FCAPDAT Capture Falling Latch Register 0x5C -1 read-only n 0x0 0x0 FCAPDAT Capture Falling Latch Register In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal. 0 16 read-only PWM_INTEN PWM_INTEN PWM Interrupt Enable Register 0x40 -1 read-write n 0x0 0x0 PIEN PWM Timer Interrupt Enable 0 1 read-write 0 Disable #0 1 Enable #1 PWM_INTSTS PWM_INTSTS PWM Interrupt Flag Register 0x44 -1 read-write n 0x0 0x0 PIF PWM Timer Interrupt Flag Flag is set by hardware when PWM down counter reaches zero, software can clear this bit by writing '1' to it. 0 1 read-write PWM_PCEN PWM_PCEN PWM Output and Capture Input Enable Register 0x7C -1 read-write n 0x0 0x0 CAPINEN Capture Input Enable Register 8 1 read-write 0 OFF (PA.7/PB.4 pin input disconnected from Capture block) #0 1 ON (PA.7/PB.4 pin, if in PWM alternative function, will be configured as an input and fed to capture function) #1 POEN0 PWM Channel0 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 0 1 read-write 0 Disable PWM Channel0 output to pin #0 1 Enable PWM Channel0 output to pin #1 POEN1 PWM Channel 1 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 1 1 read-write 0 Disable PWM Channel 1 output to pin #0 1 Enable PWM Channel 1 output to pin #1 POEN2 PWM Channel 2 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 2 1 read-write 0 Disable PWM Channel 2output to pin #0 1 Enable PWM Channel 2 output to pin #1 POEN3 PWM Channel 3 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 3 1 read-write 0 Disable PWM Channel 3 output to pin #0 1 Enable PWM Channel 3 output to pin #1 PWM_PERIOD PWM_PERIOD PWM Period Register 0xC -1 read-write n 0x0 0x0 PERIOD PWM Counter/Timer Reload Value PERIOD determines the PWM period. 0 16 read-write PWM_RCAPDAT PWM_RCAPDAT Capture Rising Latch Register 0x58 -1 read-only n 0x0 0x0 RCAPDAT Capture Rising Latch Register In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal. 0 16 read-only PWM1 PWM Register Map PWM 0x0 0x0 0x18 registers n 0x1C 0x4 registers n 0x28 0x4 registers n 0x34 0x4 registers n 0x40 0x8 registers n 0x50 0x4 registers n 0x58 0x8 registers n 0x7C 0x4 registers n PWM_CAPCTL PWM_CAPCTL Capture Control Register 0x50 -1 read-write n 0x0 0x0 CAPEN Capture Channel Input Transition Enable/Disable When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt. 3 1 read-write 0 Disable capture function #0 1 Enable capture function #1 CAPIF Capture Indication Flag Note:If this bit is '1'(not clear by SW), PWM counter will not be reloaded when next capture event occurs. 4 1 read-write CAPINV Inverter ON/OFF 0 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 CFLIEN Falling Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on falling edge of input. 2 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CFLIF PWM_FCAPDAT Latched Indicator Bit When input channel has a falling transition, PWM_FCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it. 7 1 read-write CRLIEN Rising Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on rising edge of input. 1 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 CRLIF PWM_RCAPDAT Latched Indicator Bit When input channel has a rising transition, PWM_RCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it. 6 1 read-write PWM_CLKDIV PWM_CLKDIV PWM Clock Select Register 0x4 -1 read-write n 0x0 0x0 CLKDIV PWM Timer Clock Source Selection Value : Input clock divided by 000 : 2 001 : 4 010 : 8 011 : 16 1xx : 1 0 3 read-write PWM_CLKPSC PWM_CLKPSC PWM Prescaler Register 0x0 -1 read-write n 0x0 0x0 CLKPSC Clock Prescaler For PWM Timer Clock input is divided by (CLKPSC + 1) 0 8 read-write PWM_CMPDAT0 PWM_CMPDAT0 PWM Comparator Register 0 0x10 -1 read-write n 0x0 0x0 CMP PWM Comparator Register CMP determines the PWM duty ratio. Assumption: PWM output initial is high Note2: Any write to CMP will take effect in next PWM cycle. 0 16 read-write PWM_CMPDAT1 PWM_CMPDAT1 PWM Comparator Register 1 0x1C -1 read-write n 0x0 0x0 PWM_CMPDAT2 PWM_CMPDAT2 PWM Comparator Register 2 0x28 -1 read-write n 0x0 0x0 PWM_CMPDAT3 PWM_CMPDAT3 PWM Comparator Register 3 0x34 -1 read-write n 0x0 0x0 PWM_CNT PWM_CNT PWM Counter Register 0x14 -1 read-only n 0x0 0x0 CNT PWM Counter Register Reports the current value of the 16-bit down counter. 0 16 read-only PWM_CTL PWM_CTL PWM Control Register 0x8 -1 read-write n 0x0 0x0 CNTEN PWM-Timer Enable 0 1 read-write 0 Stop PWM-Timer Running #0 1 Enable PWM-Timer #1 CNTMODE PWM-Timer Auto-Reload/One-Shot Mode 3 1 read-write 0 One-Shot Mode #0 1 Auto-reload Mode #1 PINV PWM-Timer Output Inverter ON/OFF 2 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 PWM_FCAPDAT PWM_FCAPDAT Capture Falling Latch Register 0x5C -1 read-only n 0x0 0x0 FCAPDAT Capture Falling Latch Register In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal. 0 16 read-only PWM_INTEN PWM_INTEN PWM Interrupt Enable Register 0x40 -1 read-write n 0x0 0x0 PIEN PWM Timer Interrupt Enable 0 1 read-write 0 Disable #0 1 Enable #1 PWM_INTSTS PWM_INTSTS PWM Interrupt Flag Register 0x44 -1 read-write n 0x0 0x0 PIF PWM Timer Interrupt Flag Flag is set by hardware when PWM down counter reaches zero, software can clear this bit by writing '1' to it. 0 1 read-write PWM_PCEN PWM_PCEN PWM Output and Capture Input Enable Register 0x7C -1 read-write n 0x0 0x0 CAPINEN Capture Input Enable Register 8 1 read-write 0 OFF (PA.7/PB.4 pin input disconnected from Capture block) #0 1 ON (PA.7/PB.4 pin, if in PWM alternative function, will be configured as an input and fed to capture function) #1 POEN0 PWM Channel0 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 0 1 read-write 0 Disable PWM Channel0 output to pin #0 1 Enable PWM Channel0 output to pin #1 POEN1 PWM Channel 1 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 1 1 read-write 0 Disable PWM Channel 1 output to pin #0 1 Enable PWM Channel 1 output to pin #1 POEN2 PWM Channel 2 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 2 1 read-write 0 Disable PWM Channel 2output to pin #0 1 Enable PWM Channel 2 output to pin #1 POEN3 PWM Channel 3 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 3 1 read-write 0 Disable PWM Channel 3 output to pin #0 1 Enable PWM Channel 3 output to pin #1 PWM_PERIOD PWM_PERIOD PWM Period Register 0xC -1 read-write n 0x0 0x0 PERIOD PWM Counter/Timer Reload Value PERIOD determines the PWM period. 0 16 read-write PWM_RCAPDAT PWM_RCAPDAT Capture Rising Latch Register 0x58 -1 read-only n 0x0 0x0 RCAPDAT Capture Rising Latch Register In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal. 0 16 read-only RTC RTC Register Map RTC 0x0 0x0 0x4 registers n CTL RTC_CTL RTC Control Register 0x0 -1 read-write n 0x0 0x0 RTCE RTC Enable 2 1 read-write 0 Disable RTC function #0 1 Enable RTC function #1 RTIE RTC Interrupt Enable 1 1 read-write 0 Disable the RTC interrupt #0 1 Enable the RTC interrupt #1 RTIF RTC Interrupt Flag If the RTC interrupt is enabled, then the hardware will set this bit to indicate that the RTC interrupt has occurred. If the RTC interrupt is not enabled, then this bit indicates that a timeout period has elapsed. Note: This bit is cleared by writing 1 to this bit. 0 1 read-write 0 RTC interrupt does not occur #0 1 RTC interrupt occurs #1 RTIS RTC Timer Interval Select These two bits select the timeout interval for the RTC. 3 3 read-write 0 Time-out frequency is 0.25Hz, #000 1 Time-out frequency is 0.5Hz, #001 2 Time-out frequency is 1Hz, #010 3 Time-out frequency is 2Hz #011 4 Time-out frequency is 4Hz, #100 5 Time-out frequency is 8Hz, #101 6 Time-out frequency is 16Hz, #110 7 Time-out frequency is 32Hz #111 SCS SCS Register Map SCS 0x0 0x100 0x4 registers n 0x180 0x4 registers n 0x200 0x4 registers n 0x280 0x4 registers n 0x400 0x18 registers n NVIC_ICER NVIC_ICER IRQ0 ~ IRQ20 Clear-enable Control Register 0x180 -1 read-write n 0x0 0x0 CLRENA Interrupt Clear-Enable Bit The NVIC_ICER register disables interrupts, and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ20 (Vector number from 16 ~ 36). Write Operation: 0 21 read-write 0 No effect. Interrupt Disabled 0 1 Interrupt Disabled. Interrupt Enabled 1 NVIC_ICPR NVIC_ICPR IRQ0 ~ IRQ20 Clear-pending Control Register 0x280 -1 read-write n 0x0 0x0 CLRPEND Interrupt Clear-Pending Bit The NVIC_ICPR register removes the pending state of associated interrupts, and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ20 (Vector number from 16 ~ 36). Write Operation: 0 21 read-write 0 No effect. Interrupt is not pending 0 1 Removes pending state of an interrupt. Interrupt is pending 1 NVIC_IPR0 NVIC_IPR0 IRQ0 ~ IRQ3 Priority Control Register 0x400 -1 read-write n 0x0 0x0 PRI_0 Priority Of IRQ0 '0' denotes the highest priority and '3' denotes lowest priority 6 2 read-write PRI_1 Priority Of IRQ1 '0' denotes the highest priority and '3' denotes lowest priority 14 2 read-write PRI_2 Priority Of IRQ2 '0' denotes the highest priority and '3' denotes lowest priority 22 2 read-write PRI_3 Priority Of IRQ3 '0' denotes the highest priority and '3' denotes lowest priority 30 2 read-write NVIC_IPR1 NVIC_IPR1 IRQ4 ~ IRQ7 Priority Control Register 0x404 -1 read-write n 0x0 0x0 PRI_4 Priority Of IRQ4 '0' denotes the highest priority and '3' denotes lowest priority 6 2 read-write PRI_5 Priority Of IRQ5 '0' denotes the highest priority and '3' denotes lowest priority 14 2 read-write PRI_6 Priority Of IRQ6 '0' denotes the highest priority and '3' denotes lowest priority 22 2 read-write PRI_7 Priority Of IRQ7 '0' denotes the highest priority and '3' denotes lowest priority 30 2 read-write NVIC_IPR2 NVIC_IPR2 IRQ8 ~ IRQ11 Priority Control Register 0x408 -1 read-write n 0x0 0x0 PRI_10 Priority Of IRQ10 '0' denotes the highest priority and '3' denotes lowest priority 22 2 read-write PRI_11 Priority Of IRQ11 '0' denotes the highest priority and '3' denotes lowest priority 30 2 read-write PRI_8 Priority Of IRQ8 '0' denotes the highest priority and '3' denotes lowest priority 6 2 read-write PRI_9 Priority Of IRQ9 '0' denotes the highest priority and '3' denotes lowest priority 14 2 read-write NVIC_IPR3 NVIC_IPR3 IRQ12 ~ IRQ15 Priority Control Register 0x40C -1 read-write n 0x0 0x0 PRI_12 Priority Of IRQ12 '0' denotes the highest priority and '3' denotes lowest priority 6 2 read-write PRI_13 Priority Of IRQ13 '0' denotes the highest priority and '3' denotes lowest priority 14 2 read-write PRI_14 Priority Of IRQ14 '0' denotes the highest priority and '3' denotes lowest priority 22 2 read-write PRI_15 Priority Of IRQ15 '0' denotes the highest priority and '3' denotes lowest priority 30 2 read-write NVIC_IPR4 NVIC_IPR4 IRQ16 ~ IRQ19 Priority Control Register 0x410 -1 read-write n 0x0 0x0 PRI_16 Priority Of IRQ16 '0' denotes the highest priority and '3' denotes lowest priority 6 2 read-write PRI_17 Priority Of IRQ17 '0' denotes the highest priority and '3' denotes lowest priority 14 2 read-write PRI_18 Priority Of IRQ18 '0' denotes the highest priority and '3' denotes lowest priority 22 2 read-write PRI_19 Priority Of IRQ19 '0' denotes the highest priority and '3' denotes lowest priority 30 2 read-write NVIC_IPR5 NVIC_IPR5 IRQ20 Priority Control Register 0x414 -1 read-write n 0x0 0x0 PRI_20 Priority Of IRQ20 '0' denotes the highest priority and '3' denotes lowest priority 6 2 read-write NVIC_ISER NVIC_ISER IRQ0 ~ IRQ20 Set-enable Control Register 0x100 -1 read-write n 0x0 0x0 SETENA Interrupt Set-Enable Bit The NVIC_ISER register enables interrupts, and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ20 (Vector number from 16 ~ 36). Write Operation: 0 21 read-write 0 No effect. Interrupt Disabled 0 1 Interrupt Enabled 1 NVIC_ISPR NVIC_ISPR IRQ0 ~ IRQ20 Set-pending Control Register 0x200 -1 read-write n 0x0 0x0 SETPEND Interrupt Set-Pending Bit The NVIC_ISPR register forces interrupts into the pending state, and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ20 (Vector number from 16 ~ 36). Write Operation: 0 21 read-write 0 No effect. Interrupt is not pending 0 1 Changes interrupt state to pending. Interrupt is pending 1 SPI0 SPI0 Register Map SPI0 0x0 0x0 0xC registers n 0x10 0x8 registers n 0x20 0x8 registers n 0x34 0x8 registers n CLKDIV SPI0_CLKDIV Clock Divider Register (Master Only) 0x4 -1 read-write n 0x0 0x0 DIVIDER0 Clock Divider Register (master only) The value in this field is the frequency division of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation: In other words, the maximum frequency of SCLK clock is one fifth of the SPI peripheral clock. 0 16 read-write DIVIDER1 Clock Divider 1 Register (master only) The value in this field is the 2nd frequency divider of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation: 16 16 read-write CTL SPI0_CTL Control and Status Register 0x0 -1 read-write n 0x0 0x0 BYTEITV Insert Sleep Interval Between Bytes 19 1 read-write CLKPOL Clock Polarity 11 1 read-write 0 SCLK idle low #0 1 SCLK idle high #1 DWIDTH Transmit Bit Length This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted. 3 5 read-write FIFOEN FIFO Mode 21 1 read-write 0 No FIFO present on transmit and receive buffer #0 1 Enable FIFO on transmit and receive buffer #1 GOBUSY Go and Busy Status NOTE: All registers should be set before writing 1 to this BUSY bit. When a transfer is in progress, writing to any register of the SPI master/slave core has no effect. 0 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit starts the transfer. This bit remains set during the transfer and is automatically cleared after transfer finished #1 LSB LSB First 10 1 read-write 0 The MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the DWIDTH field) #0 1 The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position in the Rx register (bit 0 of SPI_RX0/1) #1 PDMASSEN Enable DMA Automatic SS function When enabled, interface will automatically generate a SS signal for an entire PDMA access transaction. 28 1 read-write REORDER Byte Endian Reorder Function This function changes the order of bytes sent/received to be least significant physical byte first. 20 1 read-write RXEMPTY Receive FIFO Empty Status 24 1 read-write 0 The receive data FIFO is not empty #0 1 The receive data FIFO is empty #1 RXFULL Receive FIFO Full Status 25 1 read-write 0 The receive data FIFO is not full #0 1 The receive data FIFO is full #1 RXNEG Receive At Negative Edge 1 1 read-write 0 The received data input signal is latched at the rising edge of SCLK #0 1 The received data input signal is latched at the falling edge of SCLK #1 SLAVE Master Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SUSPITV Suspend Interval (Master Only) (SUSPITV[3:0] + 2) * period of SCLK 12 4 read-write TXEMPTY Transmit FIFO Empty Status 26 1 read-write 0 The transmit data FIFO is not empty #0 1 The transmit data FIFO is empty #1 TXFULL Transmit FIFO Full Status 27 1 read-write 0 The transmit data FIFO is not full #0 1 The transmit data FIFO is full #1 TXNEG Transmit At Negative Edge 2 1 read-write 0 The transmitted data output signal is changed at the rising edge of SCLK #0 1 The transmitted data output signal is changed at the falling edge of SCLK #1 TXNUM Transmit/Receive Word Numbers This field specifies how many transmit/receive word numbers should be executed in one transfer. 8 2 read-write 0 Only one transmit/receive word will be executed in one transfer #00 1 Two successive transmit/receive word will be executed in one transfer #01 2 Reserved. #10 3 Reserved. #11 UNITIEN Interrupt Enable 17 1 read-write 0 Disable SPI Interrupt #0 1 Enable SPI Interrupt to CPU #1 UNITIF Interrupt Flag Note: This bit is cleared by writing 1 to itself. 16 1 read-write 0 Indicates the transfer is not finished yet #0 1 Indicates that the transfer is complete. Interrupt is generated to CPU if enabled #1 VARCLKEN Variable Clock Enable (Master Only) Note that when enabled, the setting of DWIDTH must be programmed as 0x10 (16 bits mode) 23 1 read-write 0 The serial clock output frequency is fixed and determined only by the value of DIVIDER0 #0 1 SCLK output frequency is variable. The output frequency is determined by the value of SPI_VARCLK, DIVIDER0, and DIVIDER1 #1 PDMACTL SPI0_PDMACTL SPI0 PDMA Control Register 0x38 -1 read-write n 0x0 0x0 RXPDMAEN Receive DMA Start Set this bit to 1 will start the receive DMA process. SPI module will issue request to DMA module automatically. 1 1 read-write TXPDMAEN Transmit DMA Start Set this bit to 1 will start the transmit DMA process. SPI module will issue request to DMA module automatically. If using DMA mode to transfer data, remember not to set GO_BUSY bit of SPI_CNTRL register. The DMA controller inside SPI module will set it automatically whenever necessary. 0 1 read-write RX0 SPI0_RX0 Data Receive Register 0 0x10 -1 read-only n 0x0 0x0 RX Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register. For example, if Tx_BIT_LEN is set to 0x08 and Tx_NUM is set to 0x0, bit Rx0 [7:0] holds the received data. NOTE: The Data Receive Registers are read only registers. 0 32 read-only RX1 SPI0_RX1 Data Receive Register 1 0x14 -1 read-write n 0x0 0x0 SSCTL SPI0_SSCTL Slave Select Register 0x8 -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Select (Master only) 3 1 read-write 0 If this bit is cleared, slave select signals are asserted and de-asserted by setting and clearing related bits in SPI_SSCTL[1:0] register #0 1 If this bit is set, SPISSx0/1 signals are generated automatically. It means that device/slave select signal, which is set in SPI_SSCTL [1:0] register is asserted by the SPI controller when transmit/receive is started by setting BUSY, and is de-asserted after each transmit/receive is finished #1 LVTRGEN Slave Select Level Trigger (Slave only) 4 1 read-write 0 The input slave select signal is edge-trigger. This is the default value #0 1 The slave select signal will be level-trigger. It depends on SSACTPOL to decide the signal is active low or active high #1 LVTRGSTS Level Trigger Flag When the LVTRGEN bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not. Note: This bit is READ only 5 1 read-write 0 One of the received number and the received bit length doesn't meet the requirement in one transfer #0 1 The received number and received bits met the requirement which defines in TXCNT and DWIDTH among one transfer #1 SS Slave Select Register (Master only) If AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state. If AUTOSS bit is set, writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active level of SPISSx0/1 is specified in SSACTPOL). Note: SPISSx0 is always defined as device/slave select input signal in slave mode. 0 2 read-write SSACTPOL Slave Select Active Level It defines the active level of device/slave select signal (SPISSx0/1). 2 1 read-write 0 The slave select signal SPISSx0/1 is active at low-level/falling-edge #0 1 The slave select signal SPISSx0/1 is active at high-level/rising-edge #1 TX0 SPI0_TX0 Data Transmit Register 0 0x20 -1 write-only n 0x0 0x0 TX Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register. For example, if Tx_BIT_LEN is set to 0x08 and the Tx_NUM is set to 0x0, the bit Tx0 [7:0] will be transmitted in next transfer. If Tx_BIT_LEN is set to 0x00 and Tx_NUM is set to 0x1, the core will perform two 32-bit transmit/receive successive using the same setting (the order is Tx0 [31:0], Tx1 [31:0]). 0 32 write-only TX1 SPI0_TX1 Data Transmit Register 1 0x24 -1 read-write n 0x0 0x0 VARCLK SPI0_VARCLK Variable Clock Pattern Register 0x34 -1 read-write n 0x0 0x0 VARCLK Variable Clock Pattern The value in this field is the frequency pattern of the SPI clock. If the bit field of VARCLK is '0', the output frequency of SCLK is given by the value of DIVIDER. If the bit field of VARCLK is '1', the output frequency of SCLK is given by the value of DIVIDER2. Refer to register DIVIDER. Refer to Variable Serial Clock Frequency paragraph for detailed description. 0 32 read-write SPIM SPIM Register Map SPIM 0x0 0x0 0x8 registers n 0x10 0x20 registers n CTL0 SPIM_CTL0 Control and Status Register 0 0x0 -1 read-write n 0x0 0x0 BITMODE SPI Interface Bit Mode Note. SPIM_MOSI is Data 0 pin for Quad Mode. SPIM_MISO is Data 1 pin for Quad Mode. 20 2 read-write 0 Standard mode #00 1 Dual mode #01 2 Quad mode #10 3 Reserved. #11 BURSTNUM Transmit/Receive Burst Number This field specifies how many transmit/receive transactions should be executed continuously in one transfer. 13 2 read-write 0 Only one transmit/receive transaction will be executed in one transfer #00 1 Two successive transmit/receive transactions will be executed in one transfer #01 2 Three successive transmit/receive transactions will be executed in one transfer #10 3 Four successive transmit/receive transactions will be executed in one transfer #11 DWIDTH Transmit/Receive Bit Length This field specifies how many bits are transmitted/received in one transmit/receive transaction. Note: Only 8-, 16-, 24-, and 32-bit are allowed. Other bit length will result in incorrect transfer. 8 5 read-write 23 24 bits 0x17 31 32 bits 0x1f 7 8 bits 0x7 15 16 bits 0xf IEN Interrupt Enable Control 6 1 read-write 0 SPIM Interrupt Disabled #0 1 SPIM Interrupt Enabled #1 IF Interrupt Flag Write Operation: 7 1 read-write 0 No effect. The transfer has not finished yet #0 1 Write 1 to clear. The transfer has done #1 QDIODIR SPI Interface Direction Select For Quad/Dual Mode 15 1 read-write 0 Interface signals are input #0 1 Interface signals are output #1 RXDMAEN RX DMA Enable Control Bit If set RXDMAEN to high, SPI interface will receive the data from slave automatically. Note: Before setting RXDMAEN, user must set PDMA register correctly first. 0 1 read-write 0 DMA Disabled #0 1 DMA Enable #1 SUSPITV Suspend Interval (SUSPITV+0.5)*period of SCLK+( 3 * period of HCLK) 16 4 read-write TXDMAEN TX DMA Enable Control Bit If set TXDMAEN to high, SPI interface will transfer the data to slave automatically. Note: Before setting TXDMAEN, user must set PDMA register correctly first. 1 1 read-write 0 DMA Disabled #0 1 DMA Enable #1 CTL1 SPIM_CTL1 Control Register 1 0x4 -1 read-write n 0x0 0x0 DIVIDER Clock Divider Register The value in this field is the frequency divider of the system clock to generate the serial clock on the output SPIM_CLK pin. The desired frequency is obtained according to the following equation: Note: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of SYS_CLK. 16 16 read-write DLYSEL RX Sample Clock Source Delay Chain Select 12 3 read-write 0 Not Delay #000 1 Select sample clock through 2 Delay #001 2 Select sample clock through 4 Delay #010 3 Select sample clock through 6 Delay #011 7 Select sample clock through 14 Delay #111 SPIMEN Go and Busy Status Write Operation: Note: All registers should be set before writing 1 to the SPIMEN bit. When a transfer is in progress, you should not write to any register of this peripheral. 0 1 read-write 0 No effect. The transfer has done #0 1 Start the transfer. This bit remains set during the transfer and is automatically cleared after transfer finished. The transfer has not finished yet #1 SS Slave Select Active Enable Control 4 1 read-write 0 SPIM_SS is in active level #0 1 SPIM_SS is in inactive level #1 SSACTPOL Slave Select Active Level It defines the active level of device/slave select signal (SPIM_SS). 5 1 read-write 0 The SPIM_SS slave select signal is Active Low #0 1 The SPIM_SS slave select signal is Active High #1 RX0 SPIM_RX0 Data Receive Register 0 0x10 -1 read-only n 0x0 0x0 RX Data Receive Register The Data Receive Registers hold the received data of the last executed transfer. Number of valid RX registers is specified in SPIM_CTL0 [BURSTNUM]. If BURSTNUM 0, received data are held in the most significant RX register first. Number of valid-bit is specified in SPIM_CTL0 [DWIDTH]. If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RX register first. In a byte, received data are held in the most significant bit of RX register first. 0 32 read-only RX1 SPIM_RX1 Data Receive Register 1 0x14 -1 read-write n 0x0 0x0 RX2 SPIM_RX2 Data Receive Register 2 0x18 -1 read-write n 0x0 0x0 RX3 SPIM_RX3 Data Receive Register 3 0x1C -1 read-write n 0x0 0x0 TX0 SPIM_TX0 Data Transmit Register 0 0x20 -1 read-write n 0x0 0x0 TX Data Transmit Register The Data Transmit Registers hold the data to be transmitted in next transfer. Number of valid TX registers is specified in SPIM_CTL0 [BURSTNUM]. If BURSTNUM 0, data are transmitted in the most significant TX register first. Number of valid-bit is specified in SPIM_CTL0 [DWIDTH]. If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TX register first. In a byte, data are transmitted in the most significant bit of TX register first. 0 32 read-write TX1 SPIM_TX1 Data Transmit Register 1 0x24 -1 read-write n 0x0 0x0 TX2 SPIM_TX2 Data Transmit Register 2 0x28 -1 read-write n 0x0 0x0 TX3 SPIM_TX3 Data Transmit Register 3 0x2C -1 read-write n 0x0 0x0 SYS SYS Register Map SYS 0x0 0x0 0x10 registers n 0x110 0x14 registers n 0x130 0xC registers n 0x150 0x4 registers n 0x18 0x8 registers n 0x30 0xC registers n 0x40 0x10 registers n 0x54 0xC registers n 0xF0 0x4 registers n 0xF8 0xC registers n BODCTL SYS_BODCTL Brown-out Detector Control Register 0x18 -1 read-write n 0x0 0x0 BOD_EN Brown-Out Detector Threshold Voltage Selection Extension (Initialized Protected Bit) The default value is set by flash controller as inverse of user configuration CBODEN bit (config0 [20]). 0 1 read-write 0 Brown-Out Detector function is disabled #0 1 Brown-Out Detector function enabled #1 BOD_HYS Brown-Out Detector Hysteresis (Initialized Protected Bit) The default value is set by flash controller user configuration CBOV [4] bit (config0 [26]). 6 1 read-write 0 No hysteresis on BOD detection #0 1 BOD hysteresis enabled #1 BOD_INT Brown-Out Dectector Interrupt 8 1 read-write 1 indicates BOD_INT is active. Write 1 to clear #1 BOD_LVL Brown-Out Detector Threshold Voltage Selection (Initialized Protected Bit) 2 4 read-write BOD_OUT Brown-Out Detector Output State 7 1 read-write 0 Brown-out Detector status output is 0, the detected voltage is higher than BOD_VL setting #0 1 Brown-out Detector status output is 1, the detected voltage is lower than BOD_VL setting #1 BOD_RSTEN Brown-Out Detector Reset or Interrupt Bit (Initialized Protected Bit) The default value is set by flash controller as inverse of user configuration CBORST bit (config0 [21]). When the BOD is enabled and the interrupt is asserted, the interrupt will be kept till the BOD is disabled. The interrupt for CPU can be blocked either by disabling the interrupt in the NVIC or by disabling the interrupt source by disabling the BOD. BOD can then be re-enabled as required. 1 1 read-write 0 Brown-Out Detector generate an interrupt #0 1 Brown-Out Detector will reset chip #1 LVR_EN Low Voltage Reset (LVR) Enable (Initialized Protected Bit) The LVR function resets the chip when the input power voltage is lower than LVR trip point. Default value is set by flash controller as inverse of CLVR config 0[27]. 16 1 read-write 0 Disable LVR function #0 1 Enable LVR function #1 LVR_FILTER Default value is 00. 17 2 read-write 0 LVR output will be filtered by 1 HCLK #00 1 LVR output will be filtered by 2 HCLK #01 2 LVR output will be filtered by 8 HCLK #10 3 LVR output will be filtered by 15 HCLK #11 GPA_HR SYS_GPA_HR PA.15 ~ PA.0 Pull Resistance Select Control Register 0x48 -1 read-write n 0x0 0x0 PU_HR0 This function only for the GPIO Px[n] pin as an INPUT mode. 0 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR1 This function only for the GPIO Px[n] pin as an INPUT mode. 1 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR10 This function only for the GPIO Px[n] pin as an INPUT mode. 10 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR11 This function only for the GPIO Px[n] pin as an INPUT mode. 11 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR12 This function only for the GPIO Px[n] pin as an INPUT mode. 12 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR13 This function only for the GPIO Px[n] pin as an INPUT mode. 13 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR14 This function only for the GPIO Px[n] pin as an INPUT mode. 14 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR15 This function only for the GPIO Px[n] pin as an INPUT mode. 15 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR2 This function only for the GPIO Px[n] pin as an INPUT mode. 2 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR3 This function only for the GPIO Px[n] pin as an INPUT mode. 3 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR4 This function only for the GPIO Px[n] pin as an INPUT mode. 4 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR5 This function only for the GPIO Px[n] pin as an INPUT mode. 5 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR6 This function only for the GPIO Px[n] pin as an INPUT mode. 6 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR7 This function only for the GPIO Px[n] pin as an INPUT mode. 7 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR8 This function only for the GPIO Px[n] pin as an INPUT mode. 8 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR9 This function only for the GPIO Px[n] pin as an INPUT mode. 9 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 GPA_IEN SYS_GPA_IEN PA.15 ~ PA.0 Digital and Analog Input Buffer Control Register 0x4C -1 read-write n 0x0 0x0 IEN 0 1 read-write 0 Input buffer Enabled #0 1 Input buffer disabled, and input signal always equals to 0 #1 GPA_MFP SYS_GPA_MFP GPIO PA Multiple Alternate Functions and Input Type Control Register 0x30 -1 read-write n 0x0 0x0 PA0MFP PA.0 Multi-function Pin Selection 0 2 read-write PA10MFP PA.10 Multi-function Pin Selection 20 2 read-write PA11MFP PA.11 Multi-function Pin Selection 22 2 read-write PA12MFP PA.12 Multi-function Pin Selection 24 2 read-write PA13MFP PA.13 Multi-function Pin Selection 26 2 read-write PA14MFP PA.14 Multi-function Pin Selection 28 2 read-write PA15MFP PA.15 Multi-function Pin Selection 30 2 read-write PA1MFP PA.1 Multi-function Pin Selection 2 2 read-write PA2MFP PA.2 Multi-function Pin Selection 4 2 read-write PA3MFP PA.3 Multi-function Pin Selection 6 2 read-write PA4MFP PA.4 Multi-function Pin Selection 8 2 read-write PA5MFP PA.5 Multi-function Pin Selection 10 2 read-write PA6MFP PA.6 Multi-function Pin Selection 12 2 read-write PA7MFP PA.7 Multi-function Pin Selection 14 2 read-write PA8MFP PA.8 Multi-function Pin Selection 16 2 read-write PA9MFP PA.9 Multi-function Pin Selection 18 2 read-write GPA_PULL SYS_GPA_PULL PA.15 ~ PA.0 Pull Resistance Control Register 0x44 -1 read-write n 0x0 0x0 PU_EN0 This function only for the GPIO Px[n] pin as an INPUT mode. 0 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PU_EN1 This function only for the GPIO Px[n] pin as an INPUT mode. 1 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PU_EN10 This function only for the GPIO Px[n] pin as an INPUT mode. 10 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PU_EN11 This function only for the GPIO Px[n] pin as an INPUT mode. 11 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PU_EN12 This function only for the GPIO Px[n] pin as an INPUT mode. 12 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PU_EN13 This function only for the GPIO Px[n] pin as an INPUT mode. 13 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PU_EN14 This function only for the GPIO Px[n] pin as an INPUT mode. 14 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PU_EN15 This function only for the GPIO Px[n] pin as an INPUT mode. 15 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PU_EN2 This function only for the GPIO Px[n] pin as an INPUT mode. 2 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PU_EN3 This function only for the GPIO Px[n] pin as an INPUT mode. 3 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PU_EN4 This function only for the GPIO Px[n] pin as an INPUT mode. 4 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PU_EN5 This function only for the GPIO Px[n] pin as an INPUT mode. 5 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PU_EN6 This function only for the GPIO Px[n] pin as an INPUT mode. 6 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PU_EN7 This function only for the GPIO Px[n] pin as an INPUT mode. 7 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PU_EN8 This function only for the GPIO Px[n] pin as an INPUT mode. 8 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PU_EN9 This function only for the GPIO Px[n] pin as an INPUT mode. 9 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 GPB_HR SYS_GPB_HR PB.11 ~ PB.0 Pull Resistance Select Control Register 0x58 -1 read-write n 0x0 0x0 PU_HR0 This function only for the GPIO Px[n] pin as an INPUT mode. 0 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR1 This function only for the GPIO Px[n] pin as an INPUT mode. 1 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR10 This function only for the GPIO Px[n] pin as an INPUT mode. 10 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR11 This function only for the GPIO Px[n] pin as an INPUT mode. 11 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR2 This function only for the GPIO Px[n] pin as an INPUT mode. 2 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR3 This function only for the GPIO Px[n] pin as an INPUT mode. 3 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR4 This function only for the GPIO Px[n] pin as an INPUT mode. 4 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR5 This function only for the GPIO Px[n] pin as an INPUT mode. 5 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR6 This function only for the GPIO Px[n] pin as an INPUT mode. 6 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR7 This function only for the GPIO Px[n] pin as an INPUT mode. 7 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR8 This function only for the GPIO Px[n] pin as an INPUT mode. 8 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 PU_HR9 This function only for the GPIO Px[n] pin as an INPUT mode. 9 1 read-write 0 Pull-Up 150K resistance #0 1 Pull-Up 1M resistance #1 GPB_IEN SYS_GPB_IEN PB.11 ~ PB.0 Digital Input Buffer Control Register 0x5C -1 read-write n 0x0 0x0 IEN 0 1 read-write 0 Input buffer Enabled #0 1 Input buffer disabled, and input signal always equals to 0 #1 GPB_MFP SYS_GPB_MFP GPIO PB Multiple Alternate Functions and Input Type Control Register 0x34 -1 read-write n 0x0 0x0 PB0MFP PB.0 Multi-function Pin Selection 0 2 read-write PB10MFP PB.10 Multi-function Pin Selection 20 2 read-write PB11MFP PB.11 Multi-function Pin Selection 22 2 read-write PB1MFP PB.1 Multi-function Pin Selection 2 2 read-write PB2MFP PB.2 Multi-function Pin Selection 4 2 read-write PB3MFP PB.3 Multi-function Pin Selection 6 2 read-write PB4MFP PB.4 Multi-function Pin Selection 8 2 read-write PB5MFP PB.5 Multi-function Pin Selection 10 2 read-write PB6MFP PB.6 Multi-function Pin Selection 12 2 read-write PB7MFP PB.7 Multi-function Pin Selection 14 2 read-write PB8MFP PB.8 Multi-function Pin Selection 16 2 read-write PB9MFP PB.9 Multi-function Pin Selection 18 2 read-write GPB_PULL SYS_GPB_PULL PB.11 ~ PB.0 Pull Resistance Control Register 0x54 -1 read-write n 0x0 0x0 PU_EN This function only for the GPIO Px[n] pin as an INPUT mode. 0 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 GPIO_INTP SYS_GPIO_INTP GPIO Input Type and Slew Rate Control 0x40 -1 read-write n 0x0 0x0 GPxSSGPxHS This register controls whether the GPIO input buffer Schmitt trigger is enabled and whether high or low slew rate is selected for output driver. 0 14 read-write ICE_EN SYS_ICE_EN ICE Enable Controller Register 0x38 -1 read-write n 0x0 0x0 ICE_EN This bit will set ICE_CLK ICE_DAT enable or disable 0 1 read-write 0 ICE_CLK and ICE_DAT will be disable #0 1 ICE_CLK and ICE_DAT will be enable #1 IMGMAP0 SYS_IMGMAP0 MAP0 Data Image Register 0xF8 -1 read-only n 0x0 0x0 IMG0 Data Image of MAP0 Data in MAP0 of information block are copied to this register after power on. 0 32 read-only IMGMAP1 SYS_IMGMAP1 MAP1 Data Image Register 0xFC -1 read-only n 0x0 0x0 IMG1 Data Image of MAP1 Data in MAP1 of information block are copied to this register after power on. 0 32 read-only IMGMAP3 SYS_IMGMAP3 MAP3 Data Image Register 0xF0 -1 read-only n 0x0 0x0 IMG3 Data Image of MAP3 Data in MAP3 of information block are copied to this register after power on. 0 32 read-only IPRST0 SYS_IPRST0 IP Reset Control Resister0 0x8 -1 read-write n 0x0 0x0 CHIPRST CHIP One Shot Reset Set this bit will reset the whole chip, this bit will automatically return to '0' after 2 clock cycles. CHIPRST is same as POR reset, all the chip modules are reset and the chip configuration settings from flash are reloaded. 0 1 read-write 0 Normal #0 1 Reset CHIP #1 CPURST CPU Kernel One Shot Reset Setting this bit will reset the CPU kernel and Flash Memory Controller (FMC), this bit will automatically return to '0' after the 2 clock cycles 1 1 read-write 0 Normal #0 1 Reset CPU #1 IPRST1 SYS_IPRST1 IP Reset Control Resister1 0xC -1 read-write n 0x0 0x0 ADCRST ADC Controller Reset 28 1 read-write 0 Normal Operation #0 1 Reset #1 CSCANRST CSCAN Controller Reset 30 1 read-write 0 Normal Operation #0 1 Reset #1 DPWMRST DPWM Controller Reset 29 1 read-write 0 Normal Operation #0 1 Reset #1 GPIORST GPIO Controller Reset 1 1 read-write 0 Normal operation #0 1 Reset #1 PDMARST PDMA Controller Reset 7 1 read-write 0 Normal operation #0 1 Reset #1 PWM0RST PWM0 Controller Reset 20 1 read-write 0 Normal Operation #0 1 Reset #1 PWM1RST PWM1 Controller Reset 21 1 read-write 0 Normal Operation #0 1 Reset #1 SPI0RST SPI0 Controller Reset 12 1 read-write 0 Normal Operation #0 1 Reset #1 SPIMRST SPIM Controller Reset 13 1 read-write 0 Normal Operation #0 1 Reset #1 TMR0RST Timer0 Controller Reset 2 1 read-write 0 Normal Operation #0 1 Reset #1 TMR1RST Timer1 Controller Reset 3 1 read-write 0 Normal Operation #0 1 Reset #1 TMR2RST Timer2 Controller Reset 4 1 read-write 0 Normal operation #0 1 Reset #1 TMRFRST TimerF Controller Reset 6 1 read-write 0 Normal operation #0 1 Reset #1 UARTRST UART Controller Reset 16 1 read-write 0 Normal Operation #0 1 Reset #1 IRCTCTL SYS_IRCTCTL HIRC Trim Control Register 0x130 -1 read-write n 0x0 0x0 CESTOPEN Clock Error Stop Enable Bit 8 1 read-write 0 The trim operation is keep going if clock is inaccuracy #0 1 The trim operation is stopped if clock is inaccuracy #1 FREQSEL Trim Frequency Selection This field indicates the target frequency of 49.152 MHz internal high speed RC oscillator (HIRC) auto trim. During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 0 2 read-write 0 Disable HIRC auto trim function #00 1 Reserved. #01 2 Disable HIRC auto trim function #10 3 Enable HIRC auto trim function and trim HIRC to 49.152 MHz #11 LOOPSEL Trim Calculation Loop Selection This field defines that trim value calculation is based on how many reference clocks. Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 4 2 read-write 0 Trim value calculation is based on average difference in 4 clocks of reference clock #00 1 Trim value calculation is based on average difference in 8 clocks of reference clock #01 2 Trim value calculation is based on average difference in 16 clocks of reference clock #10 3 Trim value calculation is based on average difference in 32 clocks of reference clock #11 RETRYCNT Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. Once the HIRC locked, the internal trim value update counter will be reset. If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 6 2 read-write 0 Trim retry count limitation is 64 loops #00 1 Trim retry count limitation is 128 loops #01 2 Trim retry count limitation is 256 loops #10 3 Trim retry count limitation is 512 loops #11 IRCTIEN SYS_IRCTIEN HIRC Trim Interrupt Enable Register 0x134 -1 read-write n 0x0 0x0 CLKEIEN Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. If this bit is set to1, and CLKERRIF (SYS_IRCTSTS [2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 2 1 read-write 0 Disable CLKERRIF (SYS_IRCTSTS [2]) status to trigger an interrupt to CPU #0 1 Enable CLKERRIF (SYS_IRCTSTS [2]) status to trigger an interrupt to CPU #1 TFAILIEN Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL (SYS_IRCTCTL [1:0]). If this bit is high and TFAILIF (SYS_IRCTSTS [1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 1 1 read-write 0 Disable TFAILIF (SYS_IRCTSTS [1]) status to trigger an interrupt to CPU #0 1 Enable TFAILIF (SYS_IRCTSTS [1]) status to trigger an interrupt to CPU #1 IRCTISTS SYS_IRCTISTS HIRC Trim Interrupt Status Register 0x138 -1 read-write n 0x0 0x0 CLKERRIF Clock Error Interrupt Status When the frequency of 32.768 KHz external low speed crystal oscillator (LXT) or internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy Once this bit is set to 1, the auto trim operation stopped and FREQSEL (SYS_IRCTCL [1:0]) will be cleared to 00 by hardware automatically if CESTOPEN (SYS_IRCTCTL [8]) is set to 1. If this bit is set and CLKEIEN (SYS_IRCTIEN [2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0. 2 1 read-write 0 Clock frequency is accuracy #0 1 Clock frequency is inaccuracy #1 FREQLOCK HIRC Frequency Lock Status This bit indicates the HIRC frequency is locked. This is a status bit and doesn't trigger any interrupt Write 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled. 0 1 read-write 0 The internal high-speed oscillator frequency doesn't lock at 49.152 MHz yet #0 1 The internal high-speed oscillator frequency locked at 49.152 MHz #1 TFAILIF Trim Failure Interrupt Status This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_iRCTCTL [1:0]) will be cleared to 00 by hardware automatically. If this bit is set and TFAILIEN (SYS_IRCTIEN [1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0. 1 1 read-write 0 Trim value update limitation count does not reach #0 1 Trim value update limitation count reached and HIRC frequency still not locked #1 OSC10K SYS_OSC10K 10 KHz Oscillator and Bias Trim Register 0x114 -1 read-write n 0x0 0x0 OSCTRIM SYS_OSCTRIM Internal Oscillator Trim Register 0x110 -1 read-write n 0x0 0x0 OSC10K_TRIM 23bit trim for 10 KHz oscillator. 0 23 read-write TRM_CLK Must be toggled to load a new OSC10K_TRIM 31 1 read-write OSC_TRIM0 SYS_OSC_TRIM0 Oscillator Frequency Adjustment Control Register 0x118 -1 read-write n 0x0 0x0 EN2MHZ 0: High frequency mode (20-50 MHz) 1: Low Frequency mode of oscillator active (2 MHz). 31 1 read-write TRIM 16bit sign extended representation of 10bit trim. SYS_OSC_TRIM[0] maps to above-mentiond OSCTRIM. SYS_OSC_TRIM[1] SYS_OSC_TRIM[2] are reserved. 0 16 read-write OSC_TRIM1 SYS_OSC_TRIM1 Oscillator Frequency Adjustment Control Register 0x11C -1 read-write n 0x0 0x0 OSC_TRIM2 SYS_OSC_TRIM2 Oscillator Frequency Adjustment Control Register 0x120 -1 read-write n 0x0 0x0 PDID SYS_PDID Product Identifier Register 0x0 -1 read-only n 0x0 0x0 IMG2 Product Identifier Data in MAP2 of information block are copied to this register after power on. MAP2 is used to store part number defined by Nuvoton. 0 16 read-only PORCTL SYS_PORCTL Power-On-reset Controller Register 0x1C -1 read-write n 0x0 0x0 POROFF Power-on Reset Enable Bit (Write Protected) When power is applied to device, the POR circuit generates a reset signal to reset the entire chip function. Noise on the power may cause the POR to become active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note1: This bit does write protected. Refer to the SYS_REGLCTL register. Note2: This function will not work under DPD mode. 0 16 read-write REGLCTL SYS_REGLCTL Register Lock Control Register 0x100 -1 read-write n 0x0 0x0 SYS_REGLCTL_REGLCTL Register Lock Control Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. Protected Register Lock/Unlock Index (Read Only) 0 8 write-only 0 Protected registers are locked. Any write to the target register is ignored 0 1 Protected registers are unlocked 1 RSTSTS SYS_RSTSTS System Reset Source Register 0x4 -1 read-write n 0x0 0x0 BODRF BOD Reset Flag The BOD reset flag is set by the 'Reset Signal' from the Brown Out Reset Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 4 1 read-write 0 No reset from BOD #0 1 BOD controller had issued the reset signal to reset the system #1 LVRF LVR Reset Flag The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source. Note1: Write 1 to clear this bit to 0. Note2: If power rising reach 1.6V under 20us when fast power on, the LVRF will not happen. 3 1 read-write 0 No reset from LVR #0 1 LVR controller had issued the reset signal to reset the system #1 PINRF nRESET Pin Reset Flag The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 1 1 read-write 0 No reset from nRESET pin #0 1 Pin nRESET had issued the reset signal to reset the system #1 PIN_WK Wakeup from DPD From PIN The device was woken from Deep Power Down by a low transition on the RESETn pin. Note: Write 1 to this register to clear all wakeup flags. 8 1 read-write 0 No wakeup from RESETn pin #0 1 The device was issued a wakeup from DPD by a RESETn pin trasition #1 PMURSTF Reset Source From PMU The PMURSTF flag is set by the reset signal from the PMU module to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 6 1 read-write 0 No reset from PMU #0 1 The PMU has issued the reset signal to reset the system #1 PORF POR Reset Flag The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 0 1 read-write 0 No reset from POR #0 1 Power-on Reset (POR) Controller had issued the reset signal to reset the system #1 POR_WK Wakeup from DPD From POR The device was woken from Deep Power Down by a Power On Reset. 10 1 read-write 0 No wakeup from POR #0 1 The device was issued a wakeup from DPD by a POR #1 TIM_WK Wakeup from DPD From TIMER The device was woken from Deep Power Down by count of 10 KHz timer. 9 1 read-write 0 No wakeup from TIMER #0 1 The device was issued a wakeup from DPD by a TIMER event #1 WDTRF Reset Source From WDG The WDTRF flag is set if pervious reset source originates from the Watch-Dog module. Note: Write 1 to clear this bit to 0. 2 1 read-write 0 No reset from Watch-Dog #0 1 The Watch-Dog module issued the reset signal to reset the system #1 UCIDn SYS_UCIDn Uniq Customer ID Register 0x150 -1 read-only n 0x0 0x0 UCID Uniq Customer ID Data This register provides specific read-only information for the Uniq Customer ID 0 32 read-only SYSINFO SYSINFO Register Map SYSINFO 0x0 0x0 0x8 registers n 0x1C 0x8 registers n 0xC 0x8 registers n AIRCTL SYSINFO_AIRCTL Application Interrupt and Reset Control Register 0xC -1 read-write n 0x0 0x0 CLRACTVT Clear All Active Vector Clears all active state information for fixed and configurable exceptions. The effect of writing a 1 to this bit if the processor is not halted in Debug, is UNPREDICTABLE. 1 1 read-write 0 do not clear state information #0 1 clear state information #1 ENDIANES Endianness Read Only. Reads 0 indicating little endian machine. 15 1 read-write SRSTREQ System Reset Request Writing 1 to this bit asserts a signal to request a reset by the external system. 2 1 read-write 0 do not request a reset #0 1 request reset #1 VTKEY Vector Key The value 0x05FA must be written to this register, otherwise a write to register is UNPREDICTABLE. 16 16 read-write CPUID SYSINFO_CPUID CPUID Base Register 0x0 -1 read-only n 0x0 0x0 IMPCODE Implementer Code Assigned by ARM 24 8 read-only PART ARMv6-m Parts Reads as 0xC for ARMv6-M parts 16 4 read-only PARTNO Part Number Reads as 0xC20. 4 12 read-only REVISION Revision Reads as 0x0 0 4 read-only ICSR SYSINFO_ICSR Interrupt Control State Register 0x4 -1 read-write n 0x0 0x0 ISRPEND ISR Pending Indicates if an external configurable (NVIC generated) interrupt is pending. 22 1 read-write ISRPREEM ISR Preemptive If set, a pending exception will be serviced on exit from the debug halt state. 23 1 read-write NMIPNSET NMI Pending Set Control Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not). 31 1 read-write PPSVICLR Clear a Pending PendSV Interrupt Write 1 to clear a pending PendSV interrupt. 27 1 read-write PPSVISET Set a Pending PendSV Interrupt This is normally used to request a context switch. Reads back with current state (1 if Pending, 0 if not). 28 1 read-write PSTKICLR Clear a Pending SYST Write 1 to clear a pending SYST. 25 1 read-write PSTKISET Set a Pending SYST Reads back with current state (1 if Pending, 0 if not). 26 1 read-write VTACT Vector Active 0: Thread mode Value 1: the exception number for the current executing exception. 0 9 read-write VTPEND Vector Pending Indicates the exception number for the highest priority pending exception. The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A value of zero indicates no pending exceptions. 12 9 read-write SCR SYSINFO_SCR System Control Register 0x10 -1 read-write n 0x0 0x0 SEVNONPN Send Event on Pending Bit When enabled, interrupt transitions from Inactive to Pending are included in the list of wakeup events for the WFE instruction. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction. 4 1 read-write 0 only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded #0 1 enabled events and all interrupts, including disabled interrupts, can wake-up the processor #1 SLPDEEP Controls Whether the Processor Uses Sleep or Deep Sleep As Its Low Power Mode The SLPDEEP flag is also used in conjunction with CLK_PWRCTL register to enter deeper power-down states than purely core sleep states. 2 1 read-write 0 sleep #0 1 deep sleep #1 SLPONEXC Sleep on Exception When set to 1, the core can enter a sleep state on an exception return to Thread mode. This is the mode and exception level entered at reset, the base level of execution. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 1 1 read-write SHPR2 SYSINFO_SHPR2 System Handler Priority Register 2 0x1C -1 read-write n 0x0 0x0 PRI11 Priority of System Handler 11 - SVCall '0' denotes the highest priority and '3' denotes lowest priority 30 2 read-write SHPR3 SYSINFO_SHPR3 System Handler Priority Register 3 0x20 -1 read-write n 0x0 0x0 PRI14 Priority of System Handler 14 - PendSV '0' denotes the highest priority and '3' denotes lowest priority 22 2 read-write PRI15 Priority of System Handler 15 - SYST '0' denotes the highest priority and '3' denotes lowest priority 30 2 read-write SYSTICK SYSTICK Register Map SYSTICK 0x0 0x10 0xC registers n SYST_CSR SYST_CSR SYST Control and Status Register 0x10 -1 read-write n 0x0 0x0 CLKSRC Clock Source 2 1 read-write 0 Clock selected from CLK_CLKSEL0.STCLKSEL is used as clock source #0 1 Core clock used for SYST #1 COUNTFLAG Count Flag Returns 1 if timer counted to 0 since last time this register was read. 16 1 read-write 0 Cleared on read or by a write to the Current Value register #0 1 Set by a count transition from 1 to 0 #1 ENABLE ENABLE 0 1 read-write 0 The counter is disabled #0 1 The counter will operate in a multi-shot manner #1 TICKINT Enables SYST Exception Request 1 1 read-write 0 Counting down to 0 does not cause the SYST exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred #0 1 Counting down to 0 will cause SYST exception to be pended. Clearing the SYST Current Value register by a register write in software will not cause SYST to be pended #1 SYST_CVR SYST_CVR SYST Current Value Register 0x18 -1 read-write n 0x0 0x0 CURRENT Current Counter Value This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0 and also clear the COUNTFLAG bit. 0 24 read-write SYST_RVR SYST_RVR SYST Reload Value Register 0x14 -1 read-write n 0x0 0x0 RELOAD SYST Reload Value to load into the Current Value register when the counter reaches 0. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SYST interrupt is required every 200 clock pulses, set RELOAD to 199. 0 24 read-write TMR TMR Register Map TMR 0x0 0x0 0x10 registers n 0x20 0x18 registers n 0x40 0x10 registers n IR_CTL IR_CTL IR Carrier Output Control Register 0x34 -1 read-write n 0x0 0x0 IRCEN IR carrier output enable 1 1 read-write 0 Disable IR carrier output, #0 1 Enable IR carrier output. Timer1 time out will toggle the output state on IROUT pin #1 NONCS Non-carrier state 0 1 read-write 0 IROUT keeps low when IRCEN is 0, #0 1 IROUT keeps high when IRCEN is 0 #1 TIMER0_CMP TIMER0_CMP Timer0 Compare Register 0x4 -1 read-write n 0x0 0x0 CMPDAT Timer Comparison Value CMPDAT is a 16-bit comparison register. When the 16-bit up-counter is enabled and its value is equal to CMPDAT value, a Time out flag (TOF) is requested. Note 1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly. Note 2: No matter CNTEN is 0 or 1, whenever software writes a new value into this register, TIMER will restart counting by using this new value and abort previous count. 0 16 read-write TIMER0_CNT TIMER0_CNT Timer0 Data Register 0xC -1 read-only n 0x0 0x0 CNT Timer Data Register User can read this register for the current up-counter value while TIMERx_CTL.CNTEN is set to 1, 0 16 read-only TIMER0_CTL TIMER0_CTL Timer0 Control and Status Register 0x0 -1 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only) This bit indicates the counter status of Timer. 25 1 read-only 0 Timer is not active #0 1 Timer is active #1 CNTEN Counter Enable Bit 30 1 read-write 0 Stop/Suspend counting #0 1 Start counting #1 INTEN Interrupt Enable Bit If timer interrupt is enabled, and time-out flag (TOF) is 1'b .The timer asserts its interrupt signal to CPU. 29 1 read-write 0 Disable TIMER Interrupt #0 1 Enable TIMER Interrupt #1 OPMODE Timer Operating Mode Note: When changing the Timer Operating Mode, the CNTEN bit should be set to 0 disable first. 27 2 read-write 0 The Timer is operating in the one-shot mode. The associated interrupt signal is generated once (if INTEN is 1) and CNTEN is automatically cleared by hardware #00 1 The Timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if INTEN is 1) #01 2 Reserved. #10 3 The Timer is operating in continuous counting mode. The associated interrupt signal is generated when TIMERx_CNT = TIMERx_CMP (if INTEN is 1) however, the 16-bit up-counter counts continuously without reset #11 PSC Timer Clock Prescaler Note: No matter CNTEN is 0 or 1, whenever software writes a new value into this register, TIMER will restart counting by using this new value and abort previous count. 0 8 read-write RSTCNT Counter Reset Bit Set this bit will reset the Timer counter, pre-scale and also force CNTEN to 0. 26 1 read-write 0 No effect #0 1 Reset Timer's pre-scale counter, internal 16-bit up-counter and CNTEN bit #1 TIMER0_INTSTS TIMER0_INTSTS Timer0 Interrupt Status Register 0x8 -1 read-write n 0x0 0x0 TIF Timer Interrupt Flag (Read Only) This bit indicates the interrupt status of Timer. TIF bit is set by hardware when the 16-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1 to itself 0 1 read-only 0 No effect #0 1 CNT (TIMERx_CNT [15:0]) value matches the CMPDAT (TIMERx_CMP[15:0]) value #1 TIMER1_CMP TIMER1_CMP Timer1 Compare Register 0x24 -1 read-write n 0x0 0x0 TIMER1_CNT TIMER1_CNT Timer1 Data Register 0x2C -1 read-write n 0x0 0x0 TIMER1_CTL TIMER1_CTL Timer1 Control and Status Register 0x20 -1 read-write n 0x0 0x0 TIMER1_INTSTS TIMER1_INTSTS Timer1 Interrupt Status Register 0x28 -1 read-write n 0x0 0x0 TIMER2_CMP TIMER2_CMP Timer2 Compare Register 0x44 -1 read-write n 0x0 0x0 TIMER2_CNT TIMER2_CNT Timer2 Data Register 0x4C -1 read-write n 0x0 0x0 TIMER2_CTL TIMER2_CTL Timer2 Control and Status Register 0x40 -1 read-write n 0x0 0x0 TIMER2_INTSTS TIMER2_INTSTS Timer2 Interrupt Status Register 0x48 -1 read-write n 0x0 0x0 TIMERF_INTSTS TIMERF_INTSTS TimerF Interrupt Status Register 0x30 -1 read-write n 0x0 0x0 TFIE TimerF Interrupt Enable 1 1 read-write 0 Disable TimerF Interrupt #0 1 Enable TimerF Interrupt #1 TFIF TimerF Interrupt Flag This bit indicates the interrupt status of TimerF. TFIF bit is set by hardware when TimerF time out. It is cleared by writing 1 to this bit. 0 1 read-write 0 It indicates that TimerF does not time out yet #0 1 It indicates that TimerF time out. The interrupt flag is set if TimerF interrupt was enabled #1 UART0 UART0 Register Map UART0 0x0 0x0 0x28 registers n UART_BAUD UART_BAUD UART0 Baud Rate Divisor Register 0x24 -1 read-write n 0x0 0x0 UART_DAT UART_DAT UART0 Receive/Transmit FIFO Register. 0x0 -1 read-only n 0x0 0x0 UART_FIFO UART_FIFO UART0 FIFO Control Register. 0x8 -1 read-write n 0x0 0x0 RFITL Receive FIFO Interrupt (RDAINT) Trigger Level 4 4 read-write RTSTRGLV RTS Trigger Level for Auto-flow Control 16 4 read-write RXRST Receive FIFO Reset When RXRST is set, all the bytes in the receive FIFO are cleared and receive internal state machine is reset. Note: This bit will auto-clear after 3 UART engine clock cycles. 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the receiving internal state machine and pointers #1 TXRST Transmit FIFO Reset When TXRST is set, all the bytes in the transmit FIFO are cleared and transmit internal state machine is reset. Note: This bit will auto-clear after 3 UART engine clock cycles. 2 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the transmit internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART0 FIFO Status Register. 0x18 -1 read-write n 0x0 0x0 BIF Break Interrupt Flag This bit is set to a logic 1 whenever the receive data input (Rx) is held in the space' state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). It is reset whenever the CPU writes 1 to this bit. 6 1 read-write FEF Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit. 5 1 read-write PEF Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit, and is reset whenever the CPU writes 1 to this bit. 4 1 read-write RXEMPTY Receive FIFO Empty (Read Only) This bit indicates whether the Rx FIFO is empty or not. When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only RXFULL Receive FIFO Full (Read Only) This bit indicates whether the Rx FIFO is full or not. This bit is set when Rx FIFO is full otherwise it is cleared by hardware. 15 1 read-only RXOVIF Rx Overflow Error Interrupt Flag If the Rx FIFO (UART_DAT) is full, and an additional byte is received by the UART, an overflow condition will occur and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled. NOTE: This bit is cleared by writing 1 to itself. 0 1 read-write RXPTR Rx FIFO Pointer (Read Only) This field returns the Rx FIFO buffer pointer. It is the number of bytes available for read in the Rx FIFO. When UART receives one byte from external device, RXPTR is incremented. When one byte of Rx FIFO is read by CPU, RXPTR is decremented. 8 6 read-only TXEMPTY Transmit FIFO Empty (Read Only) This bit indicates whether the Tx FIFO is empty or not. When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared after writing data to FIFO (Tx FIFO not empty). 22 1 read-only TXEMPTYF Transmitter Empty (Read Only) Bit is set by hardware when Tx FIFO is empty and the STOP bit of the last byte has been transmitted. Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed. NOTE: This bit is read only. 28 1 read-only TXFULL Transmit FIFO Full (Read Only) This bit indicates whether the Tx FIFO is full or not. 23 1 read-only TXOVIF Tx Overflow Error Interrupt Flag If the Tx FIFO (UART_DAT) is full, an additional write to UART_DAT will cause an overflow condition and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled. NOTE: This bit is cleared by writing 1 to itself. 24 1 read-write TXPTR Tx FIFO Pointer (Read Only) This field returns the Tx FIFO buffer pointer. When CPU writes a byte into the Tx FIFO, TXPTR is incremented. When a byte from Tx FIFO is transferred to the Transmit Shift Register, TXPTR is decremented. 16 6 read-only UART_INTEN UART_INTEN UART0 Interrupt Enable Register. 0x4 -1 read-write n 0x0 0x0 ATOCTSEN CTS Auto Flow Control Enable When CTS auto-flow is enabled, the UART will send data to external device when CTS input is asserted (UART will not send data to device until CTS is asserted). 13 1 read-write 0 Disable CTS auto flow control #0 1 Enable #1 ATORTSEN RTS Auto Flow Control Enable When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals UART_FIFO.RTSTRGLV, the UART will de-assert the RTS signal. 12 1 read-write 0 Disable RTS auto flow control #0 1 Enable #1 BUFERRIEN Buffer Error Interrupt Enable 5 1 read-write 0 Mask off BUFERRINT #0 1 Enable IBUFERRINT #1 MODEMIEN Modem Status Interrupt Enable 3 1 read-write 0 Mask off MODEMINT #0 1 Enable MODEMINT #1 RDAIEN Receive Data Available Interrupt Enable 0 1 read-write 0 Mask off RDAINT #0 1 Enable RDAINT #1 RLSIEN Receive Line Status Interrupt Enable 2 1 read-write 0 Mask off RLSINT #0 1 Enable RLSINT #1 RXTOIEN Receive Time Out Interrupt Enable 4 1 read-write 0 Mask off RXTOINT #0 1 Enable RXTOINT #1 THREIEN Transmit FIFO Register Empty Interrupt Enable 1 1 read-write 0 Mask off THERINT #0 1 Enable THERINT #1 TOCNTEN Time-out Counter Enable 11 1 read-write 0 Disable Time-out counter #0 1 Enable #1 UART_INTSTS UART_INTSTS UART0 Interrupt Status Register. 0x1C -1 read-write n 0x0 0x0 BUFERRIF Buffer Error Interrupt Flag (Read Only) This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be generated. NOTE: This bit is cleared when both UART_FIFOSTS.TXOVIF and UART_FIFOSTS.RXOVIF are cleared. 5 1 read-only BUFERRINT Buffer Error Interrupt Indicator to Interrupt Controller Logical AND of UART_INTEN.BUFERRIEN and BUFERRIF. 13 1 read-write MODEMINT MODEM Status Interrupt Indicator to Interrupt Logical AND of UART_INTEN.MODEMIEN and MODENIF. 11 1 read-write MODENIF MODEM Interrupt Flag (Read Only) NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1. 3 1 read-only RDAIF Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the Rx FIFO equals UART_FIFO.RFITL then the RDAIF will be set. If UART_INTEN.RDAIEN is enabled, the RDA interrupt will be generated. NOTE: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL). 0 1 read-only RDAINT Receive Data Available Interrupt Indicator to Interrupt Controller Logical AND of UART_INTEN.RDAIEN and RDAIF. 8 1 read-write RLSIF Receive Line Status Interrupt Flag (Read Only) This bit is set when the Rx receive data has a parity, framing or break error (at least one of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated. NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. 2 1 read-only RLSINT Receive Line Status Interrupt Indicator to Interrupt Controller Logical AND of UART_INTEN.RLSIEN and RLSIF. 10 1 read-write RXTOIF Time Out Interrupt Flag (Read Only) This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU interrupt request will be generated. NOTE: This bit is read only and user can read FIFO to clear it. 4 1 read-only RXTOINT Time Out Interrupt Indicator to Interrupt Controller Logical AND of UART_INTEN.RXTOIEN and RXTOIF. 12 1 read-write THERINT Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller Logical AND of UART_INTEN.THREIEN and THREIF. 9 1 read-write THREIF Transmit Holding Register Empty Interrupt Flag (Read Only) This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If UART_INTEN.THREIEN is enabled, the THRE interrupt will be generated. NOTE: This bit is read only and it will be cleared when writing data into the Tx FIFO. 1 1 read-only UART_LINE UART_LINE UART0 Line Control Register. 0xC -1 read-write n 0x0 0x0 BCB Break Control Bit When this bit is set to logic 1, the serial data output (Tx) is forced to the 'Space' state (logic 0). Normal condition is serial data output is 'Mark' state. This bit acts only on Tx and has no effect on the transmitter logic. 6 1 read-write EPE Even Parity Enable This bit has effect only when PBE (parity bit enable) is set. 4 1 read-write 0 Odd number of logic 1's are transmitted or checked in the data word and parity bits #0 1 Even number of logic 1's are transmitted or checked in the data word and parity bits #1 NSB Number of STOP bits 2 1 read-write 0 One 'STOP bit' is generated after the transmitted data #0 1 Two 'STOP bits' are generated when 6-, 7- and 8-bit word length is selected One and a half 'STOP bits' are generated in the transmitted data when 5-bit word length is selected #1 PBE Parity Bit Enable 3 1 read-write 0 Parity bit is not generated (transmit data) or checked (receive data) during transfer #0 1 Parity bit is generated or checked between the last data word bit and stop bit of the serial data #1 SPE Stick Parity Enable 5 1 read-write 0 Disable stick parity #0 1 When bits PBE and SPE are set 'Stick Parity' is enabled. If EPE=0 the parity bit is transmitted and checked as always set, if EPE=1, the parity bit is transmitted and checked as always cleared #1 WLS Word Length Select 0 2 read-write UART_MODEM UART_MODEM UART0 Modem Control Register. 0x10 -1 read-write n 0x0 0x0 LBMEN Loopback Mode Enable 4 1 read-write 0 Disable #0 1 Enable #1 RTS RTS (Request-to-send) Signal 1 1 read-write 0 Drive RTS inactive ( = ~RTSACTLV) #0 1 Drive RTS active ( = RTSACTLV) #1 RTSACTLV Request-to-send (RTS) Active Trigger Level This bit can change the RTS trigger level. 9 1 read-write 0 RTS is active low level #0 1 RTS is active high level #1 RTSSTS RTS Pin State (Read Only) This bit is the pin status of RTS. 13 1 read-only UART_MODEMSTS UART_MODEMSTS UART0 Modem Status Register. 0x14 -1 read-write n 0x0 0x0 CTSACTLV Clear-to-send (CTS) Active Trigger Level This bit can change the CTS trigger level. 8 1 read-write 0 CTS is active low level #0 1 CTS is active high level #1 CTSDETF Detect CTS State Change Flag NOTE: This bit is cleared by writing 1 to itself. 0 1 read-write CTSSTS CTS Pin Status (Read Only) This bit is the pin status of CTS. 4 1 read-only UART_TOUT UART_TOUT UART0 Time Out Register 0x20 -1 read-write n 0x0 0x0 BAUDM0 Divider X Equal 1 Refer to Table 5116 UART Baud Rate Setting Table for more information. 28 1 read-write BAUDM1 Divider X Enable Refer to Table 5116 UART Baud Rate Setting Table for more information. NOTE: When in IrDA mode, this bit must disabled. 29 1 read-write 0 Disable divider X ( M = 16) #0 1 Enable divider X (M = EDIVM1+1, with EDIVM1 8) #1 BRD Baud Rate Divider. Refer to Table 510 for more information. 0 16 read-write EDIVM1 Divider x 24 4 read-write WDT WDT Register Map WDT 0x0 0x0 0x4 registers n CTL WDT_CTL Watchdog Timer Control Register 0x0 -1 read-write n 0x0 0x0 IF Watchdog Timer Interrupt Flag If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed. Note: This bit is cleared by writing 1 to this bit. 3 1 read-write 0 Watchdog timer interrupt has not occurred #0 1 Watchdog timer interrupt has occurred #1 INTEN Watchdog Time-Out Interrupt Enable 6 1 read-write 0 Disable the WDT time-out interrupt #0 1 Enable the WDT time-out interrupt #1 RSTCNT Clear Watchdog Timer (Write Protected) Set this bit will clear the Watchdog timer. Note1: This bit will be automatically cleared by hardware. Note2: This bit is writing protected. Refer to the SYS_REGLCTL. 0 1 read-write 0 Writing 0 to this bit has no effect #0 1 Reset the contents of the Watchdog timer #1 RSTEN Watchdog Timer Reset Enable(Write Protected) Setting this bit will enable the Watchdog timer reset function. Note: This bit is writing protected. Refer to the SYS_REGLCTL. 1 1 read-write 0 Disable Watchdog timer reset function #0 1 Enable Watchdog timer reset function #1 RSTF Watchdog Timer Reset Flag When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is disabled, then the Watchdog timer has no effect on this bit. Note: This bit is cleared by writing 1 to this bit. 2 1 read-write 0 Watchdog timer reset has not occurred #0 1 Watchdog timer reset has occurred #1 TOUTSEL Watchdog Timer Interval Select These three bits select the timeout interval for the Watchdog timer, a watchdog reset will occur 1024 clock cycles later if Watchdog timer is not reset. The WDT interrupt timeout is given by: Where WDT_CLK is the period of the Watchdog Timer clock source. 8 3 read-write 0 24 * WDT_CLK #000 1 26 * WDT_CLK #001 2 28 * WDT_CLK #010 3 210 * WDT_CLK #011 4 212 * WDT_CLK #100 5 214 * WDT_CLK #101 6 216 * WDT_CLK #110 7 218 * WDT_CLK #111 WDTEN Watchdog Timer Enable 7 1 read-write 0 Disable the WDT (Watchdog timer) (This action will reset the internal counter) #0 1 Enable the WDT (Watchdog timer) #1