nuvoTon N571P032_v3 2024.05.05 N571P032_v3 SVD file 8 32 ADC ADC Register Map ADC 0x0 0x0 0x34 registers n 0x3C 0x4 registers n 0x44 0x4 registers n CHSEQ ADC_CHSEQ A/D Channel Sequence Register 0x24 -1 read-write n 0x0 0x0 CHSEQ0 Select Channel N As The 1st Conversion In Scan Sequence 0 4 read-write CHSEQ1 Select Channel N As The 2nd Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 4 4 read-write CHSEQ2 Select Channel N As The 3rd Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 8 4 read-write CHSEQ3 Select Channel N As The 4th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 12 4 read-write CHSEQ4 Select Channel N As The 5th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 16 4 read-write CHSEQ5 Select Channel N As The 6th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 20 4 read-write CHSEQ6 Select Channel N As The 7th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 24 4 read-write CHSEQ7 Select Channel N As The 8th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 28 4 read-write CMP0 ADC_CMP0 A/D Compare Register 0 0x28 -1 read-write n 0x0 0x0 ADCMPEN Compare Enable Set this bit to 1 to enable the comparison CMPDAT with specified channel conversion result when converted data is loaded into ADC_DAT register. 0 1 read-write 0 Disable compare #0 1 Enable compare #1 ADCMPIE Compare Interrupt Enable When converted data in RESULT is less (or greater) than the compare data CMPDAT, ADCMPF bit is asserted. If ADCMPIE is set to 1, a compare interrupt request is generated. 1 1 read-write 0 Disable #0 1 Enable #1 CMPCH Compare Channel Selection 3 3 read-write 0 Reserved #000 1 Reserved #001 2 Channel 2 conversion result is selected to be compared #010 3 Channel 3 conversion result is selected to be compared #011 4 Reserved #100 5 The conversion result of pre-amplifier output is selected to be compared #101 6 Reserved #110 7 Reserved #111 CMPCOND Compare Condition 2 1 read-write 0 ADCMPFx bit is set if conversion result is less than CMPDAT #0 1 ADCMPFx bit is set if conversion result is greater or equal to CMPDAT, #1 CMPDAT Compare Data This field possessing the 5 MSB of 12-bit compare data, and 7 LSB are treated as 0 , is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software. The data format should be consistent with the setting of ADCFM bit. 23 5 read-write CMPMCNT Compare Match Count When the specified A/D channel analog conversion result matches the comparing condition, the internal match counter will increase 1. When the internal counter achieves the setting, (CMPMCNT+1) hardware will set the ADCMPF bit. 8 4 read-write CMP1 0x2C -1 read-write n 0x0 0x0 CTL ADC_CTL A/D Control Register 0x20 -1 read-write n 0x0 0x0 ADCEN A/D Converter Enable Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption. 0 1 read-write 0 Disable #0 1 Enable #1 ADCFM Data Format Of ADC Conversion Result 12 1 read-write 0 Unsigned #0 1 2'Complemet #1 ADCIE A/D Interrupt Enable A/D conversion end interrupt request is generated if ADCIE bit is set to 1. 1 1 read-write 0 Disable A/D interrupt function #0 1 Enable A/D interrupt function #1 DS_1CH This bit will be effective only when field DS_EN effective. 18 1 read-write 0 ADC down sample is applied to 2 ADC channels which are specified in CHSEQ0 and CHSEQ1. The ADC conversion output after completing the down sample function is saved in 8 ADC BUFFERs sequentially in the order of CHSEQ0 and CHSEQ1 #0 1 ADC down sample function is applied to one ADC channel, which is specified by CHSEQ0. Since the pre-amplifier output labeled by channel 4 is the only meaningful audio channel in this chip, so CHSEQ0 must be set to 0xC when DS_1CH and DS_EN are both set to 1. The ADC conversion output after completing the down sample function is saved in 8 ADC BUFFERs sequentially #1 DS_EN Down Sample Function Enable 19 1 read-write 0 Down sample function is disabled #0 1 Down sample function is enabled. When this field is set, ADC will be forced to continuous scan mode, no matter what is specified in field OPMODE (ADC_CTL[3:2]) #1 DS_RATE Down Sample Rate 16 2 read-write 0 Down sample X2 #00 1 Down sample X4 #01 2 Down sample X8 #10 3 Down sample X16 #11 HP_EN High-pass Filter Enable 23 1 read-write 0 High-pass filter is disabled #0 1 High-pass filter is enabled (must in continuous scan mode) #1 HP_FSEL High-pass Filter Frequency Selection: 20 3 read-write 0 Do not remove DC part #000 1 DC part is suppressed by -40dB, -3dB at 0.005 x Sampling Rate #001 2 DC part is suppressed by -40dB, -3dB at 0.010 x Sampling Rate #010 3 DC part is suppressed by -40dB, -3dB at 0.014 x Sampling Rate #011 4 DC part is suppressed by -40dB, -3dB at 0.019 x Sampling Rate #100 5 DC part is suppressed by -40dB, -3dB at 0.023 x Sampling Rate #101 6 DC part is suppressed by -40dB, -3dB at 0.027 x Sampling Rate #110 7 DC part is suppressed by -40dB, -3dB at 0.032 x Sampling Rate #111 OPMODE A/D Converter Operation Mode Note 1: This field will be effective only when DS_EN field in this register is set as 0 . When DS_EN is set as 1 , ADC conversion will be forced to continuous scan mode Note 2: When changing the operation mode, software should disable SWTRG bit firstly. 2 2 read-write 0 Single conversion #00 1 Reserved #01 2 Single-cycle scan #10 3 Continuous scan #11 SWTRG A/D Conversion Start Note: SWTRG bit can be reset to 0 by software, or can be cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channel. In continuous scan mode, A/D conversion is continuously performed sequentially until software writes 0 to this bit or chip resets. 11 1 read-write 0 Conversion is stopped and A/D converter enters idle state #0 1 Start conversion #1 DAT0 ADC_DAT0 A/D Data Register for the channel defined in CHSEQ0 0x0 -1 read-only n 0x0 0x0 EXTS Extension Bits Of RESULT for Different Data Format If ADCFM is 0 , EXTS all are read as 0 . If ADCFM is 1 , EXTS all are read as bit RESULT[11]. 12 4 read-only OV Over Run Flag If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after ADC_DAT register is read. 16 1 read-only 0 Data in RESULT are recent conversion result #0 1 Data in RESULT are overwritten #1 RESULT A/D Conversion Result This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit. 0 12 read-only VALID Valid Flag This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read. 17 1 read-only 0 Data in RESULT are not valid #0 1 Data in RESULT are valid #1 DAT1 0x4 -1 read-write n 0x0 0x0 DAT2 0x8 -1 read-write n 0x0 0x0 DAT3 0xC -1 read-write n 0x0 0x0 DAT4 0x10 -1 read-write n 0x0 0x0 DAT5 0x14 -1 read-write n 0x0 0x0 DAT6 0x18 -1 read-write n 0x0 0x0 DAT7 0x1C -1 read-write n 0x0 0x0 HWPARA ADC_HWPARA ADC H/W Parameter Control Register 0x44 -1 read-write n 0x0 0x0 CONV_N Specify ADC conversion clock number CONV_N has to be equal to or great than 11. To update this field, programmer can only revise bit [14:8] and keep other bits the same as before. Note: CONV_N valid range is from 11~127 8 7 read-write SHCLK_N Specify the high level of ADC start signal. Note: Suggested and default value is 0. 0 6 read-write PGCTL ADC_PGCTL ADC Pre-amplifier Gain Control Register 0x3C -1 read-write n 0x0 0x0 BOOST_GAIN Gain Setting Bits For The First Stage Of Pre-Amp 1 2 read-write 0 0 dB #00 1 10 dB #01 2 20 dB #10 3 Reserved #11 GAIN_CHG Change Gain method of PGC 3 1 read-write 0 Load Boost and Post gain to PGC directly #0 1 Load Boost and Post gain to PGC when zero cross occurs #1 OPMUTE Mute Control of First Stage Pre-Amp for Offset Bias Calibration When this bit set is as 1 , two input end of first stage pre-amp will be shorted, and feedback resistor of this stage will be shorted. 0 1 read-write 0 Open #0 1 Short #1 OS Configuration for Pre-Amp OP Offset Bias Compensation Voltage There are 64 levels and 0.25mV per level @ 5V condition. 8 6 read-write POST_GAIN Gain setting bits for the second stage of pre-amp. Gain start from 14dB till 34dB for 0.65dB per step. 24 5 read-write 0 14 dB #00000 1 14.65 dB #00001 2 15.3 dB #00010 3 15.95 dB #00011 4 16.6 dB #00100 5 17.25 dB #00101 6 17.9 dB #00110 7 18.55 dB #00111 8 19.2 dB #01000 9 19.85 dB #01001 10 20.5 dB #01010 11 21.15 dB #01011 12 21.8 dB #01100 13 22.45 dB #01101 14 23.1 dB #01110 15 23.75 dB #01111 16 24.4 dB #10000 31 34.15 dB #11111 STATUS ADC_STATUS A/D Status Register 0x30 -1 read-write n 0x0 0x0 ADCMPF0 Compare Flag When the selected channel A/D conversion result meets setting conditions in ADC_CMP0, then this bit is set to 1. And it is cleared by write 1. 1 1 read-write 0 Converted result RESULT in ADC_DAT does not meet ADC_CMP0 setting #0 1 Converted result RESULT in ADC_DAT meets ADC_CMP0 setting, #1 ADCMPF1 Compare Flag When the selected channel A/D conversion result meets setting conditions in ADC_CMP1, then this bit is set to 1. And it is cleared by write 1. 2 1 read-write 0 Converted result RESULT in ADC_DAT does not meet ADC_CMP1 setting #0 1 Converted result RESULT in ADC_DAT meets ADC_CMP1 setting, #1 ADIF A/D Conversion End Flag A status flag that indicates the end of A/D conversion. ADIF is set to 1 under the following two conditions: When A/D conversion ends in single mode, When A/D conversion ends on all channels specified by channel sequence register in scan mode. And it is cleared when 1 is written. 0 1 read-write BUSY BUSY/IDLE This bit is mirror of SWTRG bit in ADC_CTL. It is read only. 3 1 read-write 0 A/D converter is in idle state #0 1 A/D converter is busy at conversion #1 CHANNEL Current Conversion Channel It is read only. 4 3 read-write OV Over Run Flag It is a mirror to OV bit in ADC_DATn. 16 8 read-write VALID Data Valid Flag It is a mirror of VALID bit in ADC_DATn. 8 8 read-write APU APU Register Map APU 0x0 0x0 0x8 registers n 0xC 0x24 registers n CH0DAT0 APU_CH0DAT0 APU Channel 0 Data Buffer Register 0 0x10 -1 read-write n 0x0 0x0 PCM PCM Data Of Channel 0 This field contains 16-bit PCM data that will be sent to mixer H/W. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically. The data format of PCM is 2'complement. 0 16 read-write CH0DAT1 0x14 -1 read-write n 0x0 0x0 CH0DAT2 0x18 -1 read-write n 0x0 0x0 CH0DAT3 0x1C -1 read-write n 0x0 0x0 CH0DAT4 0x20 -1 read-write n 0x0 0x0 CH0DAT5 0x24 -1 read-write n 0x0 0x0 CH0DAT6 0x28 -1 read-write n 0x0 0x0 CH0DAT7 0x2C -1 read-write n 0x0 0x0 CH1DAT0 APU_CH1DAT0 APU Channel 1 Data Buffer Register 0xC -1 read-write n 0x0 0x0 PCM1 PCM Data Of Channel 1 This field contains 16-bit PCM data that is one of the Mixer input. User needs to take care of the effective bit of PCM because the H/W mixer output is clipped to 13 bits automatically. The data format of PCM is 2'complement. 0 16 read-write CTL APU_CTL APU Control Register 0x0 -1 read-write n 0x0 0x0 APUIE APU Interrupt Enable 6 1 read-write 0 Disable the APU threshold interrupt #0 1 Enable the APU threshold interrupt #1 APUIS APU Interrupt Status This flag is set by hardware when APU threshold is met. Software can clear this bit by writing a zero to it. 5 1 read-write 0 APU threshold interrupt does not occur #0 1 APU threshold interrupt occur #1 BPPAM Bypass Power Amplifier, DAC Output To Pin 9 1 read-write 0 SPK+/DAC pin is one of power amplifier output, #0 1 SPK+/DAC pin is current DAC output, no output on SPK- #1 DACE DAC Enable 8 1 read-write 0 Disable DAC function #0 1 Enable DAC function #1 DAC_ZERO_CROSS DAC Output Data Cross Zero Point Flag Note: This bit is set by hardware when DAC output data cross zero point, software can clear this bit by write 1. 10 1 read-write 0 DAC output data doesn't cross zero point #0 1 DAC output data cross zero point #1 FIXI DAC mode select 4 1 read-write 0 DAC current varies by voltage (structure is same as N572F072) #0 1 DAC current fix (structure is same as N572F064) #1 PAMPE Power Amplifier Enable 7 1 read-write 0 Disable PA function #0 1 Enable PA function #1 TSHD APU Interrupt Threshold 0 3 read-write 0 Buffer 0 is read out by APU #000 1 Buffer 1 is read out by APU #001 2 Buffer 2 is read out by APU #010 3 Buffer 3 is read out by APU #011 4 Buffer 4 is read out by APU #100 5 Buffer 5 is read out by APU #101 6 Buffer 6 is read out by APU #110 7 Buffer 7 is read out by APU #111 UP4EN Up sample X4 Enable Note: Once UP4_EN set as 1, TM0CP field in TM0CPR suggest to be set as multiple times of 4 to avoid playback rate shift. Worst case of the playback rate deviation is 3/TM0CPR * 100% when least significant 2 bits of is TM0CPR b'11. 3 1 read-write 0 Disable the APU up sample X4 #0 1 Enable the APU up sample X4 and filtering #1 VM APU_VM APU Volume Control Register 0x4 -1 read-write n 0x0 0x0 VOLUM APU Volume Adjustment 0 3 read-write 0 0 dB #000 1 -3 dB #001 2 -6 dB #010 3 -9 dB #011 4 -12 dB #100 5 -15 dB #101 6 -18 dB #110 7 Reserved #111 CLK CLK Register Map CLK 0x0 0x0 0xC registers n 0x10 0xC registers n 0x20 0x4 registers n AHBCLK CLK_AHBCLK AHB Device Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 APUCKEN APU Clock Enable Control 3 1 read-write 0 To disable the APU engine clock #0 1 To enable the APU engine clock #1 ISPCKEN OTP ISP Controller Clock Enable Control. The OTP ISP engine clock always is from 46MHz RC oscillator. 2 1 read-write 0 Disable the OTP ISP engine clock #0 1 Enable the OTP ISP engine clock #1 APBCLK CLK_APBCLK APB Device Clock Enable Control Register 0x8 -1 read-write n 0x0 0x0 ADC_EN Audio Analog-Digital-Converter (ADC) Clock Enable Control 28 1 read-write 0 Disable #0 1 Enable #1 PWM_EN PWM Block Clock Enable Control 20 1 read-write 0 Disable #0 1 Enable #1 RTC_EN Real-Time-Clock APB Interface Clock Control This bit is used to control the RTC APB clock only. The RTC engine clock source is from the 32.768KHz crystal. 1 1 read-write 0 Disable #0 1 Enable #1 SPI0_EN SPI0 Clock Enable Control 12 1 read-write 0 Disable #0 1 Enable #1 TMR0_EN Timer0 Clock Enable Control 2 1 read-write 0 Disable #0 1 Enable #1 TMR1_EN Timer1 Clock Enable Control 3 1 read-write 0 Disable #0 1 Enable #1 TMR2_EN Timer2 Clock Enable Control 4 1 read-write 0 Disable #0 1 Enable #1 TMRF_EN TimerF Clock Enable Control 5 1 read-write 0 Disable #0 1 Enable #1 WDT_EN Watchdog Clock Enable Control This bit is the protected bit. To program this bit needs an open lock sequence, write 59h , 16h , 88h to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100. The default bit value is set according to the Flash Controller User Configuration Register CONFIG[31]. 0 1 read-write 0 Disable #0 1 Enable #1 CLKDIV CLK_CLKDIV Clock Divider Number Register 0x18 -1 read-write n 0x0 0x0 ADCDIV ADC Clock Divide Number From ADC Clock Source The ADC engine clock must meet the constraint: ADCLK ( HCKL/2. 16 8 read-write HCLKDIV HCLK Clock Divide Number From HCLK Clock Source 0 4 read-write CLKSEL0 CLK_CLKSEL0 Clock Source Select Control Register 0 0x10 -1 read-write n 0x0 0x0 HCLKSEL HCLK Clock Source Select Note: 1. When power on, 23MHz RC is selected as HCLK clock source. 2. Before clock switch, the related clock sources (pre-select and new-select) must be turned on. 0 3 read-write 0 clock source from XTL_32K #000 2 clock source from PLL_23M #010 4 clock source from PLL_23M #100 7 clock source from RC_23M #111 CLKSEL1 CLK_CLKSEL1 Clock Source Select Control Register 1 0x14 -1 read-write n 0x0 0x0 ADCSEL ADC Clock Source Select 2 2 read-write 0 Clock source from PLL_FOUT, #00 1 Clock source from HCLK,. Clock source from RC_46M #01 PWMSEL PWM Timer Clock Source Select 28 2 read-write 0 Clock source from HCLK #00 1 Clock source from XTL_32K #01 2 Equivalent with 00 #10 3 Clock source from RC_46M #11 SPI0SEL SPI0 Clock Source Select 4 2 read-write 0 Clock source from HCLK #00 1 Clock source from PLL_FOUT. Clock source from RC_46M #01 TMR0SEL Timer0 Clock Source Select 8 3 read-write 0 Clock source from HCLK #000 1 Clock source from XTL_32K. Clock source from RC_46M #001 2 Equivalent with 000 #010 3 Clock source from external trigger #011 TMR1SEL Timer1 Clock Source Select 12 3 read-write 0 Clock source from HCLK #000 1 Clock source from XTL_32K. Clock source from RC_46M #001 2 Equivalent with 000 #010 3 Clock source from external trigger #011 TMR2SEL Timer2 Clock Source Select 16 3 read-write 0 Clock source from HCLK #000 1 Clock source from XTL_32K. Clock source from RC_46M #001 2 Equivalent with 000 #010 3 Equivalent with 000 #011 TMRFSEL TimerF Clock Source Select 20 3 read-write 0 Clock source from external XTL_32K/32, #000 1 Clock source from external XTL_32K/(4x32), #001 6 Clock source from RC_46M/32768, #110 7 Clock source from RC_46M/(4x32768), #111 WDTSEL Watchdog Timer Clock Source Selection (Write Protect) These bits are protected bits. To program these bits needs an open lock sequence, write 59h , 16h , 88h to SYS_REGLCTL to un-lock these bits. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.. 0 2 read-write 0 Clock source from HCLK/2048, #00 1 Clock source from XTL_32K, #01 2 Clock source from PLL_FOUT, #10 3 Clock source from RC_23M #11 PLLCON CLK_PLLCON PLL Control Register 0x20 -1 read-write n 0x0 0x0 PWRCTL CLK_PWRCTL System Power Control Register 0x0 -1 read-write n 0x0 0x0 OSC46M_EN Internal 46MHz RC Oscillator Control After reset, this bit is 1 . 2 1 read-write 0 46MHz oscillation is disabled #0 1 46MHz oscillation is enabled #1 PD_WAIT_CPU This Bit Controls the Power Down Entry Condition Please refer to PWR_DOWN bit for the usage of PD_WAIT_CPU bit. The following is a brief description of PD_WAIT_CPU bit. 8 1 read-write 0 Chip is at normal mode. Note that PWR_DOWN cannot be set to 1 when PD_WAIT_CPU value remains at 0, otherwise the chip may not wake up normally #0 1 Chip waits to enter power-down mode #1 PWR_DOWN System Power Down Active Or Enable Bit 7 1 read-write 0 Chip operates at normal mode #0 1 Chip is standing by power-down entry condition #1 WINT_EN Enable Interrupt When Wake Up From Power Down Mode 5 1 read-write 0 Disable #0 1 Enable. The interrupt will occur when MCU wakes up from power down mode #1 WINT_STS Chip Power Down Wake Up Status Flag Set by power down wake up , it indicates that resume from power down mode. The flag is set if the GPIO, WDT or RTC wakeup. Note: Write 1 to clear the bit. 6 1 read-write WU_DLY Enable the Wake Up Delay Time Selection When the chip wakes up from power down, the clock control will delay some times as selection to wait LDO33 stable. 1: Delay 200us for LDO33 stable. 0: Delay 60us for LDO33 stable. 4 1 read-write XTL32K_EN External 32.768KHz Crystal Control After reset, this bit is 0 . 1 1 read-write 0 32.768KHz Crystal is disabled #0 1 32.768KHz Crystal is enabled #1 XTL32K_FILTER Filter the XTL32K output clock Note: High level of XTL32K must keep 112 HCLK for recognition valid, when this bit is enabled. 3 1 read-write 0 Disable, XTL32K output clock without filter #0 1 Enable, XTL32K output clock will be filtered to avoid glitch occurs #1 XTL32K_WEAK XTL32K weak mode 0 1 read-write 0 Normal mode #0 1 Weak mode #1 GPIO GPIO Register Map GPIO 0x0 0x0 0x4 registers n 0x10 0x4 registers n 0x18 0xC registers n 0x40 0x4 registers n 0x48 0x4 registers n 0x50 0x4 registers n 0x58 0xC registers n 0x8 0x4 registers n PA_DOUT PA_DOUT GPIO PA Data Output Value 0x8 -1 read-write n 0x0 0x0 DOUT Port [A/B] Pin[N] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. Note: PB_DOUT[3:0] are reserved to 0. 0 16 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set 0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set 1 PA_INTEN PA_INTEN GPIO PA Interrupt Enable 0x1C -1 read-write n 0x0 0x0 FLIEN0 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 0 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN1 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 1 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN10 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 10 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN11 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 11 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN12 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 12 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN13 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 13 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN14 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 14 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN15 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 15 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN2 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 2 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN3 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 3 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN4 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 4 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN5 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 5 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN6 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 6 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN7 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 7 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN8 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 8 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN9 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. 9 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 RHIEN0 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 16 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN1 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 17 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN10 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 26 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN11 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 27 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN12 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 28 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN13 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 29 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN14 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 30 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN15 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 31 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN2 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 18 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN3 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 19 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN4 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 20 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN5 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 21 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN6 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 22 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN7 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 23 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN8 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 24 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN9 Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. 25 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 PA_INTSRC PA_INTSRC GPIO PA Interrupt Source Flag 0x20 -1 read-write n 0x0 0x0 INTSRC Port [A/B] Interrupt Source Flag Read operation: 0 16 read-write 0 No interrupt from Px.n. No action 0 1 Px.n generated an interrupt. Clear the corresponding pending interrupt 1 PA_INTTYPE PA_INTTYPE GPIO PA Interrupt Trigger Type 0x18 -1 read-write n 0x0 0x0 TYPE Port [A/B] Pin[N] Edge Or Level Detection Interrupt Trigger Type Control TYPE[n] is used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is level triggered, the input source is sampled by one HCLK clock to generate the interrupt Note: If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set, the setting is ignored and no interrupt will occur 0 16 read-write 0 Edge triggered interrupt 0 1 Level triggered interrupt 1 PA_MODE PA_MODE GPIO PA Pin I/O Mode Control 0x0 -1 read-write n 0x0 0x0 MODE0 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 0 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 MODE1 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 2 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 MODE10 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 20 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 MODE11 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 22 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 MODE12 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 24 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 MODE13 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 26 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 MODE14 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 28 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 MODE15 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 30 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 MODE2 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 4 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 MODE3 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 6 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 MODE4 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 8 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 MODE5 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 10 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 MODE6 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 12 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 MODE7 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 14 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 MODE8 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 16 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 MODE9 Port [A/B] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE[7:0] are reserved to 0. 18 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in Quasi-bidirectional mode #11 PA_PIN PA_PIN GPIO PA Pin Value 0x10 -1 read-only n 0x0 0x0 PIN Port [A/B] Pin[N] Pin Values Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: PB_PIN[3:0] are reserved to 0. 0 16 read-only PB_DOUT 0x48 -1 read-write n 0x0 0x0 PB_INTEN 0x5C -1 read-write n 0x0 0x0 PB_INTSRC 0x60 -1 read-write n 0x0 0x0 PB_INTTYPE 0x58 -1 read-write n 0x0 0x0 PB_MODE 0x40 -1 read-write n 0x0 0x0 PB_PIN 0x50 -1 read-write n 0x0 0x0 INT INT Register Map INT 0x0 0x0 0xC registers n 0x14 0x18 registers n 0x30 0xC registers n 0x80 0x8 registers n IRQ0_SRC IRQ0_SRC IRQ0 (WDT) Interrupt Source Identity Register 0x0 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: WDT_INT 0 3 read-only IRQ10_SRC IRQ10_SRC IRQ10 (PWM) Interrupt Source Identity Register 0x28 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: PWM_INT 0 3 read-only IRQ12_SRC IRQ12_SRC IRQ12 (TimerF) Interrupt Source Identity Register 0x30 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: TimerF_INT 0 3 read-only IRQ13_SRC IRQ13_SRC IRQ13 (RTC) Interrupt Source Identity Register 0x34 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: RTC_INT 0 3 read-only IRQ14_SRC IRQ14_SRC IRQ14 (PWRWU) Interrupt Source Identity Register 0x38 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: PWRWU_INT 0 3 read-only IRQ1_SRC IRQ1_SRC IRQ1 (APU) Interrupt Source Identity Register 0x4 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: APU_INT 0 3 read-only IRQ2_SRC IRQ2_SRC IRQ2 (ADC) Interrupt Source Identity Register 0x8 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: ADC_INT 0 3 read-only IRQ5_SRC IRQ5_SRC IRQ5 (Timer0) Interrupt Source Identity Register 0x14 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: Timer0_INT 0 3 read-only IRQ6_SRC IRQ6_SRC IRQ6 (Timer1) Interrupt Source Identity Register 0x18 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: Timer1_INT 0 3 read-only IRQ7_SRC IRQ7_SRC IRQ7 (Timer2) Interrupt Source Identity Register 0x1C -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: Timer2_INT 0 3 read-only IRQ8_SRC IRQ8_SRC IRQ8 (GPA/B) Interrupt Source Identity Register 0x20 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: GPB_INT Bit0: GPA_INT 0 3 read-only IRQ9_SRC IRQ9_SRC IRQ9 (SPI0) Interrupt Source Identity Register 0x24 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: SPI0_INT 0 3 read-only MCU_IRQ MCU_IRQ MCU IRQ Number Identify Register 0x84 -1 read-write n 0x0 0x0 MCU_IRQ MCU IRQ Source Test Mode The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to MCU Cortex-M0. There are two modes to generate interrupt to MCU Cortex-M0, the normal mode and test mode. When MCU_IRQ[n] is 0 : Writing MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 IRQ[n]. When MCU_IRQ[n] is 1 (meaning an interrupt is asserted): Writing MCU_IRQ[n] 1 will clear the interrupt writing MCU_IRQ[n] 0 : has no effect. Note: IRQ4 and IRQ15 are reserved in N571P032. 0 16 read-write NMI_SEL NMI_SEL NMI Source Interrupt Select Control Register 0x80 -1 read-write n 0x0 0x0 IRQ_TM IRQ Test Mode This bit is the protected bit. To program this bit needs an open lock sequence, write 59h , 16h , 88h to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100. 7 1 read-write 0 The interrupt register MCU_IRQ operates in normal mode. The MCU_IRQ collects all the interrupts from the peripheral and generates interrupt to MCU #0 1 All the interrupts from peripheral to MCU are blocked. The peripheral IRQ signals (0-15) are replaced by the value in the MCU_IRQ register #1 NMI_SEL NMI Source Interrupt Select The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[15:0]. The NMI_SEL bit is used to select the NMI interrupt source. Note: IRQ4 and IRQ15 are reserved in N571P032. 0 4 read-write PWM PWM Register Map PWM 0x0 0x0 0x18 registers n 0x1C 0x4 registers n 0x28 0x4 registers n 0x34 0x4 registers n 0x40 0x8 registers n 0x50 0x4 registers n 0x58 0x8 registers n 0x7C 0x4 registers n CAPCTL PWM_CAPCTL Capture Control Register 0x50 -1 read-write n 0x0 0x0 CAPEN Capture Channel Input Transition Enable/Disable When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt. 3 1 read-write 0 Disable capture function #0 1 Enable capture function #1 CAPIF Capture Interrupt Indication Flag Note:If this bit is 1 , PWM counter will not be reloaded when next capture interrupt occurs. 4 1 read-write CAPINV Inverter ON/OFF 0 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 CFLIEN Falling Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on falling edge of input. 2 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CFLIF PWM_FCAPDAT Latched Indicator Bit When input channel has a falling transition, PWM_FCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it. 7 1 read-write CRLIEN Rising Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on rising edge of input. 1 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 CRLIF PWM_RCAPDAT Latched Indicator Bit When input channel has a rising transition, PWM_RCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it. 6 1 read-write CLKDIV PWM_CLKDIV PWM Clock Select Register 0x4 -1 read-write n 0x0 0x0 CLKDIV PWM Timer Clock Source Selection Value : Input clock divided by 000 : 2 001 : 4 010 : 8 011 : 16 1xx : 1 0 3 read-write CLKPSC PWM_CLKPSC PWM Prescaler Register 0x0 -1 read-write n 0x0 0x0 CLKPSC Clock Prescaler For PWM Timer Clock input is divided by (CLKPSC + 1) 0 8 read-write DZI0 Dead Zone Interval Register 0 These 8 bits determine dead zone length. The unit time of dead zone length is that from clock selector. 16 8 read-write DZI1 Dead Zone Interval Register 1 These 8 bits determine dead zone length. The unit time of dead zone length is that from clock selector. 24 8 read-write CMPDAT0 PWM_CMPDAT0 PWM Comparator Register 0 0x10 -1 read-write n 0x0 0x0 CMP PWM Comparator Register CMP determines the PWM duty ratio. Assumption: PWM output initial is high Note2: Any write to CMP will take effect in next PWM cycle. 0 16 read-write CMPDAT1 0x1C -1 read-write n 0x0 0x0 CMPDAT2 0x28 -1 read-write n 0x0 0x0 CMPDAT3 0x34 -1 read-write n 0x0 0x0 CNT PWM_CNT PWM Counter Register 0x14 -1 read-only n 0x0 0x0 CNT PWM Counter Register Reports the current value of the 16-bit down counter. 0 16 read-only CTL PWM_CTL PWM Control Register 0x8 -1 read-write n 0x0 0x0 CNTEN PWM-Timer Enable 0 1 read-write 0 Stop PWM-Timer Running #0 1 Enable PWM-Timer #1 CNTMODE PWM-Timer Auto-Reload/One-Shot Mode 3 1 read-write 0 One-Shot Mode #0 1 Auto-reload Mode #1 DTEN0 Dead-Zone 0 Generator Enable/Disable 4 1 read-write 0 Disable #0 1 Enable #1 DTEN1 Dead-Zone 1 Generator Enable/Disable 5 1 read-write 0 Disable #0 1 Enable #1 PINV PWM-Timer Output Inverter ON/OFF 2 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 FCAPDAT PWM_FCAPDAT Capture Falling Latch Register 0x5C -1 read-only n 0x0 0x0 FCAPDAT Capture Falling Latch Register In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal. 0 16 read-only INTEN PWM_INTEN PWM Interrupt Enable Register 0x40 -1 read-write n 0x0 0x0 PIEN PWM Timer Interrupt Enable 0 1 read-write 0 Disable #0 1 Enable #1 INTSTS PWM_INTSTS PWM Interrupt Flag Register 0x44 -1 read-write n 0x0 0x0 PIF PWM Timer Interrupt Flag Flag is set by hardware when PWM down counter reaches zero, software can clear this bit by writing '1' to it. 0 1 read-write PCEN PWM_PCEN PWM Output and Capture Input Enable Register 0x7C -1 read-write n 0x0 0x0 CAPINEN Capture Input Enable Register 8 1 read-write 0 OFF (PB.12 pin input disconnected from Capture block) #0 1 ON (PB.12 pin, if in PWM alternative function, will be configured as an input and fed to capture function) #1 POEN0 PWM0 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 58) 0 1 read-write 0 Disable PWM0 output to pin #0 1 Enable PWM0 output to pin #1 POEN1 PWM1 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 58) 1 1 read-write 0 Disable PWM1 output to pin #0 1 Enable PWM1 output to pin #1 POEN2 PWM2 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 58) 2 1 read-write 0 Disable PWM2 output to pin #0 1 Enable PWM2 output to pin #1 POEN3 PWM3 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPB_MFP Table 58) 3 1 read-write 0 Disable PWM3 output to pin #0 1 Enable PWM3 output to pin #1 PERIOD PWM_PERIOD PWM Period Register 0xC -1 read-write n 0x0 0x0 PERIOD PWM Counter/Timer Reload Value PERIOD determines the PWM period. 0 16 read-write RCAPDAT PWM_RCAPDAT Capture Rising Latch Register 0x58 -1 read-only n 0x0 0x0 RCAPDAT Capture Rising Latch Register In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal. 0 16 read-only RTC RTC Register Map RTC 0x0 0x0 0x4 registers n CTL RTC_CTL RTC Control Register 0x0 -1 read-write n 0x0 0x0 RTCE RTC Enable 2 1 read-write 0 Disable RTC function #0 1 Enable RTC function #1 RTIE RTC Interrupt Enable 1 1 read-write 0 Disable the RTC interrupt #0 1 Enable the RTC interrupt #1 RTIF RTC Interrupt Flag If the RTC interrupt is enabled, then the hardware will set this bit to indicate that the RTC interrupt has occurred. If the RTC interrupt is not enabled, then this bit indicates that a timeout period has elapsed. Note: This bit is cleared by writing 1 to this bit. 0 1 read-write 0 RTC interrupt does not occur #0 1 RTC interrupt occurs #1 RTIS RTC Timer Interval Select These two bits select the timeout interval for the RTC. 3 2 read-write 0 Time-out frequency is 0.25Hz, #00 1 Time-out frequency is 2Hz, #01 2 Time-out frequency is 8Hz, #10 3 Time-out frequency is 32Hz #11 SCS SCS Register Map SCS 0x0 0x100 0x4 registers n 0x180 0x4 registers n 0x200 0x4 registers n 0x280 0x4 registers n 0x400 0x10 registers n NVIC_ICER NVIC_ICER IRQ0 ~ IRQ15 Clear-Enable Control Register 0x180 -1 read-write n 0x0 0x0 CLRENA Interrupt Clear-Enable Bit The NVIC_ICER register disables interrupts, and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31). Write Operation: 0 16 read-write 0 No effect. Interrupt Disabled 0 1 Interrupt Disabled. Interrupt Enabled 1 NVIC_ICPR NVIC_ICPR IRQ0 ~ IRQ15 Clear-Pending Control Register 0x280 -1 read-write n 0x0 0x0 CLRPEND Interrupt Clear-Pending Bit The NVIC_ICPR register removes the pending state of associated interrupts, and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31). Write Operation: 0 16 read-write 0 No effect. Interrupt is not pending 0 1 Removes pending state of an interrupt. Interrupt is pending 1 NVIC_IPR0 NVIC_IPR0 IRQ0 ~ IRQ3 Priority Control Register 0x400 -1 read-write n 0x0 0x0 PRI_0 Priority Of IRQ0 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_1 Priority Of IRQ1 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_2 Priority Of IRQ2 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_3 Priority Of IRQ3 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR1 NVIC_IPR1 IRQ4 ~ IRQ7 Priority Control Register 0x404 -1 read-write n 0x0 0x0 PRI_4 Priority Of IRQ4 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_5 Priority Of IRQ5 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_6 Priority Of IRQ6 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_7 Priority Of IRQ7 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR2 NVIC_IPR2 IRQ8 ~ IRQ11 Priority Control Register 0x408 -1 read-write n 0x0 0x0 PRI_10 Priority Of IRQ10 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_11 Priority Of IRQ11 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write PRI_8 Priority Of IRQ8 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_9 Priority Of IRQ9 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write NVIC_IPR3 NVIC_IPR3 IRQ12 ~ IRQ15 Priority Control Register 0x40C -1 read-write n 0x0 0x0 PRI_12 Priority Of IRQ12 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_13 Priority Of IRQ13 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_14 Priority Of IRQ14 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_15 Priority Of IRQ15 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_ISER NVIC_ISER IRQ0 ~ IRQ15 Set-Enable Control Register 0x100 -1 read-write n 0x0 0x0 SETENA Interrupt Set-Enable Bit The NVIC_ISER register enables interrupts, and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31). Write Operation: 0 16 read-write 0 No effect. Interrupt Disabled 0 1 Interrupt Enabled 1 NVIC_ISPR NVIC_ISPR IRQ0 ~ IRQ15 Set-Pending Control Register 0x200 -1 read-write n 0x0 0x0 SETPEND Interrupt Set-Pending Bit The NVIC_ISPR register forces interrupts into the pending state, and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31). Write Operation: 0 16 read-write 0 No effect. Interrupt is not pending 0 1 Changes interrupt state to pending. Interrupt is pending 1 SPI0 SPI Register Map SPI 0x0 0x0 0xC registers n 0x10 0x8 registers n 0x20 0x8 registers n 0x30 0x4 registers n CLKDIV SPI0_CLKDIV Clock Divider Register (Master Only) 0x4 -1 read-write n 0x0 0x0 DIVIDER Clock Divider Register (Master Mode Only) SPI0 clock pin SPI_SCLK0 output clock frequency is SPI0_CIN/(DIVIDER+1).DIVIDER can be from 0 to 65535. But due to I/O transaction speed limitation, the maximum clock of SPI_SCLK0 is 23 MHz. So the DIVIDER value cannot be set to 0 when RC_46M is selected as the SPI clock source. 0 16 read-write CTL SPI0_CTL Control and Status Register 0x0 -1 read-write n 0x0 0x0 CLKP Clock Polarity 11 1 read-write 0 SPI_SCLK0 idle low #0 1 SPI_SCLK0 idle high #1 DWIDTH Transmit Bit Length This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted. 3 5 read-write GO_BUSY Go And Busy Status NOTE: All registers should be set readily before writing 1 to the GO_BUSY bit. When a transfer is in progress, writing to any register of the SPI core has no effect. 0 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit starts the transfer. This bit remains 1 during the transfer and is automatically cleared after the transfer is finished #1 LSB Send LSB First 10 1 read-write 0 The MSB is transmitted/received first (which bit in SPI0_TXn/SPI0_RXn is MSB is dependent on DWIDTH) #0 1 The LSB (SPI0_TXn[0]) is sent first to SPI0_MOSI0, and the first bit received from SPI0_MISO0 will be put in the LSB (SPI0_RXn[0]) #1 REORDER BYTE ENDIAN 20 1 read-write 0 Disable the BYTE ENDIAN #0 1 Enable the BYTE ENDIAN. Only the 16, 24, and 32 bits which are defined in DWIDTH are supported #1 RX_NEG Receive On Negative Edge 1 1 read-write 0 The input on SPI_MISO0 is latched on the rising edge of SPI_SCLK0 #0 1 The input on SPI_MISO0 is latched on the falling edge of SPI_SCLK0 #1 SLAVE Master/Slave Mode Select 18 1 read-write 0 Master mode #0 1 Slave mode #1 SUSPITV Suspend Interval (Master Mode Only) (SUSPITV+2)* SPI0_CLK clock cycles Note: SUSPITV cannot be 0 . 12 4 read-write TX_NEG Transmit On Negative Edge 2 1 read-write 0 The output on SPI_MOSI0 is changed on the rising edge of SPI_SCLK0 #0 1 The output on SPI_MOSI0 is changed on the falling edge of SPI_SCLK0 #1 TX_NUM Transmit/Receive Numbers This field specifies how many transmit/receive numbers should be executed in one transfer. 8 2 read-write 0 Only one transmit/receive will be executed in one transfer #00 1 Two successive transmit/receive will be executed in one transfer. Reserved #01 UNIT_INTEN Unit Transfer Interrupt Enable 17 1 read-write 0 Disable SPI Unit Transfer Interrupt #0 1 Enable SPI Unit Transfer Interrupt to CPU #1 UNIT_INTSTS Unit Transfer Interrupt Status Note: This bit is read only, but can be cleared by writing 1 to this bit. 16 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 RCLK SPI0_RCLK SPI0 Receive Timing Control Register 0x30 -1 read-write n 0x0 0x0 SPI0_CTIM Coarse Timing Control For SPI0 Data Receiving Setting these bits can adjust receiving clock for latching serial-in data correctly in high speed transmission mode. 2 2 read-write 0 Receiving data clock of SPI0 is same as the SPI_SCLK0 #00 1 Receiving data clock of SPI0 is delayed 2 half SPI_SCLK0 clock cycle, #01 2 Receiving data clock of SPI0 is delayed 3 half SPI_SCLK0 clock cycle, #10 3 Receiving data clock of SPI0 is delayed 1 half SPI_SCLK0 clock cycle , #11 SPI0_FTIM Fine Timing Control For SPI0 Data Receiving The delay timing selected by SPI0_CTIM can be further tuned finely by SPI0_FTIM. 0 2 read-write 0 Receiving data clock of SPI0 has extra 7.5nS delay #00 1 Receiving data clock of SPI0 has extra 5.0nS delay, #01 2 Receiving data clock of SPI0 has extra 2.5nS delay, #10 3 Receiving data clock of SPI0 has no extra delay #11 RX0 SPI0_RX0 Data Receive Register 0 0x10 -1 read-only n 0x0 0x0 RX Data Receive Register Note: The Data Receive Registers are read only registers. A Write to these registers will actually modify the Data Transmit Registers because those registers share the same flip-flops. 0 32 read-only RX1 0x14 -1 read-write n 0x0 0x0 SSCTL SPI0_SSCTL Slave Select Register 0x8 -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Select (Master Mode Only) 3 1 read-write 0 Slave select signal (SPI_SSB00/SPI_SSB01) is asserted and de-asserted by setting and clearing related bit SS #0 1 Slave select signal (SPI_SSB00/SPI_SSB01) is generated automatically. It means that slave select signal, which is set in bits SS, is asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and is de-asserted after the transfer is finished #1 LTRIG_FLAG Level Trigger Flag (Slave Mode Only) When the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the received bit number meets the requirement or not. Note 1: This bit is READ only. 5 1 read-write 0 One of the received number and the received bit length doesn't meet the requirement in one transfer #0 1 The received number and received bits meet the requirement which is defined in TX_NUM and DWIDTH among one transfer #1 SS Slave Select Pin Control If AUTOSS bit is 0, SPI0_SSB00 and SPI0_SSB01 output are determined by SS[0] and SS[1] respectively. Note 1: This interface can only drive one device/slave at a given time. Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer. Note 2: SPIn_SSB10 is also defined as device/slave select input signal in slave mode. And that the slave select input signal must be driven by edge active trigger which level depend on the SS_LVL setting, otherwise the SPI slave core will go into dead path until the edge active trigger again or reset the SPI core by software. 0 2 read-write 0 Any bit location of this field forces the pin to inactive state. Any bit location of this field will select appropriate SPI0_SSB00/SPI0_SSB01 pin to be driven to inactive state 0 1 Any bit location of this field forces the proper SPIn_SSBx0/SPIn_SSBx1 pin to an active state Any bit location of this field will select appropriate SPIn_SSB00/SPIn_SSB01 pin to be automatically driven to active state for the duration of the transmit/receive, and to be driven to inactive state for the rest of the time. The active state of SPI0_SSB00/SPI0_SSB01 is specified in SS_LVL bit (SPI_SSCTL[2]) 1 SS_LTRIG Slave Select Level Trigger (Slave Mode Only) 4 1 read-write 0 The input slave select signal is edge-trigger. This is the default value #0 1 The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high #1 SS_LVL Slave Select Active Level It defines the active level of device/slave select signal. 2 1 read-write 0 The SPI_SSB00/SPI_SSB01 slave select signal is active Low #0 1 The SPI_SSB00/SPI_SSB01 slave select signal is active High #1 TX0 SPI0_TX0 Data Transmit Register 0 0x20 -1 write-only n 0x0 0x0 TX Data Transmit Register Note: The SPI0_RXn and SPI0_TXn registers share the same flip-flops, which mean that what is received in one transfer will be transmitted in the next transfer if there is not any write to the SPI0_TXn register between the two transfers. 0 32 write-only TX1 0x24 -1 read-write n 0x0 0x0 SYS SYS Register Map SYS 0x0 0x0 0x10 registers n 0x120 0x4 registers n 0x18 0x8 registers n 0x30 0xC registers n 0x40 0x4 registers n 0xF4 0x4 registers n 0xFC 0x8 registers n BODCTL SYS_BODCTL Brown-Out Detector Control Register 0x18 -1 read-write n 0x0 0x0 BOD_EN Brown-Out Detector Enable (Initiated and Protected Bit) 0 1 read-write 0 Brown-Out Detector function is disabled #0 1 Brown-Out Detector function is enabled, #1 BOD_OUT The Status for Brown-Out Detector Output It's a read only bit. 6 1 read-write 0 The detected voltage is lower than BOD_VL setting. If the BOD_EN is 0 , this bit always responses 0 #0 1 The detected voltage is higher than BOD_VL setting #1 BOD_POL Brown-Out Detector Output Polarity Select 2 1 read-write 0 PB.15 will output the BOD out directly when PB.15 multi-function is active #0 1 PB.15 will output the inverse of BOD out when PB.15 multi-function is active #1 BOD_VL Brown-Out Detector Threshold Voltage Selection (Initiated and Protected Bit) 1 1 read-write 0 Threshold voltage is 2.7V #0 1 Threshold voltage is 3.0V #1 LVR_EN Low Voltage Reset (LVR) Enable (Protected Bit) The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default. 7 1 read-write 0 Disable LVR function #0 1 Enable LVR function - After enable the bit, the LVR function will active with 100uS delay for LVR output stable #1 LVR_FILTER 8 2 read-write 0 LVR outputs without to be filtered #00 1 LVR output will be filtered by 2 HCLK #01 2 LVR output will be filtered by 8 HCLK #10 3 LVR output will be filtered by 15 HCLK #11 DEVICEID SYS_DEVICEID Device ID Register 0xF4 -1 read-only n 0x0 0x0 DEVICEID Device ID Data This register provides specific read-only information for the Device ID 0 16 read-only GPA_HS SYS_GPA_HS PA.4 ~ PA.0 High Speed Transition Control Register 0x38 -1 read-write n 0x0 0x0 GPA_HS 0 5 read-write GPA_MFP SYS_GPA_MFP GPIO PA Multiple Alternate Functions and Input Type Control Register 0x30 -1 read-write n 0x0 0x0 PA0MFP 0 1 read-write 0 The GPIOA-0 is selected to the pin PA.0 #0 1 SPI0 2nd chip select output #1 PA10MFP 10 1 read-write 0 The GPIOA-10 is selected to the pin PA.10 #0 1 ADC input channel 2 #1 PA11MFP 11 1 read-write 0 The GPIOA-11 is selected to the pin PA.11 #0 1 ADC input channel 3 #1 PA12MFP 12 1 read-write 0 The GPIOA-12 is selected to the pin PA.12 #0 1 Mic. IN+ pin to Pre-Amp #1 PA13MFP 13 1 read-write 0 The GPIOA-13 is selected to the pin PA.13 #0 1 Mic. IN- pin to Pre-Amp #1 PA14MFP 14 1 read-write 0 The GPIOA-14 is selected to the pin PA.14 #0 1 MIC Bias pin #1 PA15MFP 15 1 read-write 0 The GPIOA-15 is selected to the pin PA.15 #0 1 PGC Reference Voltage pin #1 PA1MFP 1 1 read-write 0 The GPIOA-1 is selected to the pin PA.1 #0 1 SPI0 1st chip select output #1 PA2MFP 2 1 read-write 0 The GPIOA-2 is selected to the pin PA.2 #0 1 SPI0 clock output #1 PA3MFP 3 1 read-write 0 The GPIOA-3 is selected to the pin PA.3 #0 1 SPI0 data input #1 PA4MFP 4 1 read-write 0 The GPIOA-4 is selected to the pin PA.4 #0 1 SPI0 data output #1 PA5MFP 5 1 read-write 0 The GPIOA-5 is selected to the pin PA.5 #0 1 Timer0 counter external input #1 GPB_MFP SYS_GPB_MFP GPIO PB Multiple Alternate Functions and Input Type Control Register 0x34 -1 read-write n 0x0 0x0 PB10MFP 10 1 read-write 0 The GPIOB-10 is selected to the pin PB.10 #0 1 PWM output pin 2 #1 PB11MFP 11 1 read-write 0 The GPIOB-11 is selected to the pin PB.11 #0 1 PWM output pin 3 #1 PB12MFP 12 1 read-write 0 The GPIOB-12 is selected to the pin PB.12 #0 1 PWM timer capture input #1 PB13MFP 13 1 read-write 0 The GPIOB-13 is selected to the pin PB.13 #0 1 IR carrier output #1 PB14MFP 14 1 read-write 0 The GPIOB-14 is selected to the pin PB.14 #0 1 Timer1 counter external input #1 PB15MFP 15 1 read-write 0 The GPIOB-15 is selected to the pin PB.15 #0 1 BOD active signal output #1 PB8MFP 8 1 read-write 0 The GPIOB-8 is selected to the pin PB.8 #0 1 PWM output pin 0 #1 PB9MFP 9 1 read-write 0 The GPIOB-9 is selected to the pin PB.9 #0 1 PWM output pin 1 #1 ICE_MFP SYS_ICE_MFP ICE Multi-Function-Pin Controller Register 0x40 -1 read-write n 0x0 0x0 ICE_EN This bit will set ICE_CLK and ICE_DAT pins to be serial debug wires or PB.4/5 0 1 read-write 0 ICE_CLK and ICE_DAT will be assigned as PB.4 and PB.5, for general IO purpose #0 1 ICE_CLK and ICE_DAT will be set as ICE CLCOK/ ICE DIO, only for debugging purpose #1 IMGMAP1 SYS_IMGMAP1 MAP1 Data Image Register 0xFC -1 read-only n 0x0 0x0 IMG1 Data Image of MAP1 Data in MAP1 of information block are copied to this register after power on. 0 32 read-only IPRST0 SYS_IPRST0 IP Reset Control Resister0 0x8 -1 read-write n 0x0 0x0 CHIPRST CHIP One Shot Reset Set this bit will reset the whole chip, this bit will automatically return to 0 after 2 clock cycles. CHIPRST is same as POR reset, all the chip modules are reset and the chip configuration settings from OTP are reloaded. 0 1 read-write 0 Normal #0 1 Reset CHIP #1 CPURST CPU Kernel One Shot Reset Setting this bit will reset the CPU kernel and OTP Memory Controller(OMC), this bit will automatically return to 0 after the 2 clock cycles 1 1 read-write 0 Normal #0 1 Reset CPU #1 CPUWS CPU Wait-State Control For OTP Memory Access Note: there must be 1 HCLK wait state if HCLK equal 23MHz. 2 1 read-write 0 1 HCLK clock wait-state #0 1 zero wait-state #1 IPRST1 SYS_IPRST1 IP Reset Control Resister1 0xC -1 read-write n 0x0 0x0 ADCRST ADC Controller Reset 28 1 read-write 0 Normal Operation #0 1 Reset #1 APURST APU Controller Reset 5 1 read-write 0 Normal operation #0 1 Reset #1 GPIORST GPIO Controller Reset 1 1 read-write 0 Normal operation #0 1 Reset #1 PWMRST PWM Controller Reset 20 1 read-write 0 Normal Operation #0 1 Reset #1 SPI0RST SPI0 Controller Reset 12 1 read-write 0 Normal Operation #0 1 Reset #1 TMR0RST Timer0 Controller Reset 2 1 read-write 0 Normal Operation #0 1 Reset #1 TMR1RST Timer1 Controller Reset 3 1 read-write 0 Normal Operation #0 1 Reset #1 TMR2RST Timer2 Controller Reset 4 1 read-write 0 Normal operation #0 1 Reset #1 TMRFRST TimerF Controller Reset 6 1 read-write 0 Normal operation #0 1 Reset #1 PA_ADJ SYS_PA_ADJ PA Offset Voltage Adjustment Register 0x120 -1 read-write n 0x0 0x0 PADCADJ Turning the Offset voltage between SPKP/SPKN PADCADJ[5] is selection bit, PADCADJ[4:0] are offset trim bits. 0 6 read-write PDID SYS_PDID Product Identifier Register 0x0 -1 read-only n 0x0 0x0 IMG2 Product Identifier Data in MAP2 of information block are copied to this register after power on. MAP2 is used to store part number defined by Nuvoton. 0 16 read-only PORCTL SYS_PORCTL Power-On-Reset Controller Register 0x1C -1 read-write n 0x0 0x0 POROFF Power-On Reset Enable Code (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, ICE reset command and the software-chip reset function. 0 16 read-write POROFFSTS This bit is status bit of POR, it is read only. 16 1 read-write 0 POR is active now #0 1 POR is non-active now while POROFF equals 0x5aa5 #1 REGLCTL SYS_REGLCTL Register Lock Control Register 0x100 -1 read-write n 0x0 0x0 REGLCTL Protected Register Lock/Unlock Index (Read Only) SPI0_RCLK - address 0x4003_0030 WDT_CTL -- address 0x4000_4000 0 1 read-only 0 Protected registers are locked. Any write to the target register is ignored #0 1 Protected registers are unlocked #1 SYS_REGLCTL Register Lock Control Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. 0 8 write-only RSTSTS SYS_RSTSTS System Reset Source Register 0x4 -1 read-write n 0x0 0x0 LVRF LVR Reset Flag The LVR reset flag is set by the Reset Signal from the Low Voltage Reset Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 3 1 read-write 0 No reset from LVR #0 1 LVR controller had issued the reset signal to reset the system #1 PINRF nRESET Pin Reset Flag The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 1 1 read-write 0 No reset from nRESET pin #0 1 Pin nRESET had issued the reset signal to reset the system #1 PMURSTF Reset Source From PMU The PMURSTF flag is set by the reset signal from the PMU module to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 6 1 read-write 0 No reset from PMU #0 1 The PMU has issued the reset signal to reset the system #1 PORF POR Reset Flag The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 0 1 read-write 0 No reset from POR #0 1 Power-on Reset (POR) Controller had issued the reset signal to reset the system #1 WDTRF Reset Source From WDG The WDTRF flag is set if pervious reset source originates from the Watch-Dog module. Note: Write 1 to clear this bit to 0. 2 1 read-write 0 No reset from Watch-Dog #0 1 The Watch-Dog module issued the reset signal to reset the system #1 TMR TMR Register Map TMR 0x0 0x0 0x10 registers n 0x20 0x18 registers n 0x40 0x10 registers n IR_CTL IR_CTL IR Carrier Output Control Register 0x34 -1 read-write n 0x0 0x0 TIMER0_CMP TIMER0_CMP Timer0 Compare Register 0x4 -1 read-write n 0x0 0x0 CMPDAT Timer Comparison Value Note 1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly. Note 2: No matter CNTEN is 0 or 1, whenever software writes a new value into this register, TIMER will restart counting by using this new value and abort previous count. 0 16 read-write TIMER0_CNT TIMER0_CNT Timer0 Data Register 0xC -1 read-only n 0x0 0x0 CNT Timer Data Register User can read this register for the current up-counter value while TIMERx_CTL.CNTEN is set to 1, 0 16 read-only TIMER0_CTL TIMER0_CTL Timer0 Control and Status Register 0x0 -1 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only) This bit indicates the counter status of Timer. 25 1 read-only 0 Timer is not active #0 1 Timer is active #1 CNTEN Counter Enable Bit 30 1 read-write 0 Stop/Suspend counting #0 1 Start counting #1 INTEN Interrupt Enable Bit If timer interrupt is enabled, the timer asserts its interrupt signal when the associated count is equal to TIMERx_CMP. 29 1 read-write 0 Disable TIMER Interrupt #0 1 Enable TIMER Interrupt #1 OPMODE Timer Operating Mode 27 2 read-write 0 The Timer is operating in the one-shot mode. The associated interrupt signal is generated once (if INTEN is 1) and CNTEN is automatically cleared by hardware #00 1 The Timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if INTEN is 1) #01 2 Reserved #10 3 The Timer is operating in continuous counting mode. The associated interrupt signal is generated when TIMERx_CNT = TIMERx_CMP (if INTEN is 1) however, the 16-bit up-counter counts continuously without reset #11 PSC Timer Clock Prescaler 0 8 read-write Reserved Reserved. 31 1 read-write RSTCNT Counter Reset Bit Set this bit will reset the Timer counter, pre-scale and also force CNTEN to 0. 26 1 read-write 0 No effect #0 1 Reset Timer's pre-scale counter, internal 16-bit up-counter and CNTEN bit #1 TIMER0_INTSTS TIMER0_INTSTS Timer0 Interrupt Status Register 0x8 -1 read-write n 0x0 0x0 TIF Timer Interrupt Flag (Read Only) This bit indicates the interrupt status of Timer. TIF bit is set by hardware when the 16-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1 to itself 0 1 read-only 0 No effect #0 1 CNT (TIMERx_CNT[15:0]) value matches the CMPDAT (TIMERx_CMP[15:0]) value #1 TIMER1_CMP 0x24 -1 read-write n 0x0 0x0 TIMER1_CNT 0x2C -1 read-write n 0x0 0x0 TIMER1_CTL 0x20 -1 read-write n 0x0 0x0 TIMER1_INTSTS 0x28 -1 read-write n 0x0 0x0 TIMER2_CMP 0x44 -1 read-write n 0x0 0x0 TIMER2_CNT 0x4C -1 read-write n 0x0 0x0 TIMER2_CTL 0x40 -1 read-write n 0x0 0x0 TIMER2_INTSTS 0x48 -1 read-write n 0x0 0x0 TIMERF_INTSTS TIMERF_INTSTS TimerF Interrupt Status Register 0x30 -1 read-write n 0x0 0x0 TFIE TimerF Interrupt Enable 1 1 read-write 0 Disable TimerF Interrupt #0 1 Enable TimerF Interrupt #1 TFIF TimerF Interrupt Flag This bit indicates the interrupt status of TimerF. TFIF bit is set by hardware when TimerF time out. It is cleared by writing 1 to this bit. 0 1 read-write 0 It indicates that TimerF does not time out yet #0 1 It indicates that TimerF time out. The interrupt flag is set if TimerF interrupt was enabled #1 WDT WDT Register Map WDT 0x0 0x0 0x4 registers n CTL WDT_CTL Watchdog Timer Control Register 0x0 -1 read-write n 0x0 0x0 IF Watchdog Timer Interrupt Flag If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed. Note: This bit is cleared by writing 1 to this bit. 3 1 read-write 0 Watchdog timer interrupt has not occurred #0 1 Watchdog timer interrupt has occurred #1 INTEN Watchdog Time-Out Interrupt Enable 6 1 read-write 0 Disable the WDT time-out interrupt #0 1 Enable the WDT time-out interrupt #1 RSTCNT Clear Watchdog Timer Set this bit will clear the Watchdog timer. Note: This bit will auto clear after few clock cycles 0 1 read-write 0 Writing 0 to this bit has no effect #0 1 Reset the contents of the Watchdog timer #1 RSTEN Watchdog Timer Reset Enable Setting this bit will enable the Watchdog timer reset function. Note: This function cannot work with XTL32-based clock source. 1 1 read-write 0 Disable Watchdog timer reset function #0 1 Enable Watchdog timer reset function #1 RSTF Watchdog Timer Reset Flag When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is disabled, then the Watchdog timer has no effect on this bit. Note: This bit is cleared by writing 1 to this bit. 2 1 read-write 0 Watchdog timer reset has not occurred #0 1 Watchdog timer reset has occurred #1 TOUTSEL Watchdog Timer Interval Select These three bits select the timeout interval for the Watchdog timer, a watchdog reset will occur 1024 clock cycles later if Watchdog timer is not reset. The WDT interrupt timeout is given by: Where WDT_CLK is the period of the Watchdog Timer clock source. 8 3 read-write 0 24 * WDT_CLK #000 1 26 * WDT_CLK #001 2 28 * WDT_CLK #010 3 210 * WDT_CLK #011 4 212 * WDT_CLK #100 5 214 * WDT_CLK #101 6 216 * WDT_CLK #110 7 218 * WDT_CLK #111 WDTEN Watchdog Timer Enable 7 1 read-write 0 Disable the WDT(Watchdog timer) (This action will reset the internal counter) #0 1 Enable the WDT(Watchdog timer) #1 WKEN WDT Time-Out Wake-Up Function Control If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. 4 1 read-write 0 Enable the Wakeup function that WDT timeout can wake up CPU from power-down mode #0 1 Disable WDT Wakeup CPU function #1 WKF WDT Time-Out Wake-Up Flag If WDT causes CPU wake up from sleep or power-down mode, this bit will be set to high. Note: This bit is cleared by writing 1 to it. 5 1 read-write 0 WDT does not cause CPU wake-up #0 1 CPU wakes up from sleep or power-down mode by WDT time-out interrupt #1