nuvoTon
N572F065_v3
2024.05.03
N572F065_v3 SVD file
8
32
ADC
ADC Register Map
ADC
0x0
0x0
0x38
registers
n
0x3C
0x4
registers
n
CAL
ADC_CAL
A/D Calibration Register
0x34
-1
read-write
n
0x0
0x0
CALDONE
Calibration is Done (read only)
When 0 is written to CALEN bit, CALDONE bit is cleared by hardware immediately and be set to 1 after 96 ADC clocks. It is a read only bit.
1
1
read-only
0
A/D converter has not been calibrated or calibration is in progress if CALEN bit is set
#0
1
A/D converter self-calibration is done
#1
CALEN
Self-Calibration Enable
Software can set this bit to 1 enables A/D converter to do self-calibration function. It needs 127 ADC clocks to complete calibration. This bit must be kept at 1 after CALDONE asserted. Clearing this bit will disable self-calibration function.
0
1
read-write
0
Disable self-calibration
#0
1
Enable self-calibration
#1
CHSEQ
ADC_CHSEQ
A/D Channel Sequence Register
0x24
-1
read-write
n
0x0
0x0
CHSEQ0
Select Channel N As The 1st Conversion In Scan Sequence
0
4
read-write
1
no channel is selected, scan sequence end
#1001
CHSEQ1
Select Channel N As The 2nd Conversion In Scan Sequence
The definition of channel selection is the same as CHSEQ0.
4
4
read-write
CHSEQ2
Select Channel N As The 3rd Conversion In Scan Sequence
The definition of channel selection is the same as CHSEQ0.
8
4
read-write
CHSEQ3
Select Channel N As The 4th Conversion In Scan Sequence
The definition of channel selection is the same as CHSEQ0.
12
4
read-write
CHSEQ4
Select Channel N As The 5th Conversion In Scan Sequence
The definition of channel selection is the same as CHSEQ0.
16
4
read-write
CHSEQ5
Select Channel N As The 6th Conversion In Scan Sequence
The definition of channel selection is the same as CHSEQ0.
20
4
read-write
CHSEQ6
Select Channel N As The 7th Conversion In Scan Sequence
The definition of channel selection is the same as CHSEQ0.
24
4
read-write
CHSEQ7
Select Channel N As The 8th Conversion In Scan Sequence
The definition of channel selection is the same as CHSEQ0.
28
4
read-write
CMP0
ADC_CMP0
A/D Compare Register 0
0x28
-1
read-write
n
0x0
0x0
ADCMPEN
Compare Enable
Set this bit to 1 to enable the comparison CMPDAT[11:0] with specified channel conversion result when converted data is loaded into ADC_DAT register.
0
1
read-write
0
Disable compare
#0
1
Enable compare
#1
ADCMPIE
Compare Interrupt Enable
When converted data in RESULT is less (or greater) than the compare data CMPDAT[11:0], ADCMPF bit is asserted. If ADCMPIE is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Disable
#0
1
Enable
#1
CMPCH
Compare Channel Selection
3
3
read-write
0
Channel 0 conversion result is selected to be compared
#000
1
Channel 1 conversion result is selected to be compared
#001
2
Channel 2 conversion result is selected to be compared
#010
3
Channel 3 conversion result is selected to be compared
#011
4
Channel 4 conversion result is selected to be compared
#100
5
Channel 5 conversion result is selected to be compared
#101
6
Channel 6 conversion result is selected to be compared
#110
7
Channel 7 conversion result is selected to be compared
#111
CMPCOND
Compare Condition
2
1
read-write
0
ADCMPFx bit is set if conversion result is less than CMPDAT[11:0]
#0
1
ADCMPFx bit is set if conversion result is greater or equal to CMPDAT[11:0],
#1
CMPDAT
Compare Data
The 12 bits data are used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software.
The data format should be consistent with the setting of ADCFM bit.
16
12
read-write
CMPMCNT
Compare Match Count
When the specified A/D channel analog conversion result matches the comparing condition, the internal match counter will increase 1. When the internal counter achieves the setting, (CMPMCNT+1) hardware will set the ADCMPF bit.
8
4
read-write
CMP1
0x2C
-1
read-write
n
0x0
0x0
CTL
ADC_CTL
A/D Control Register
0x20
-1
read-write
n
0x0
0x0
ADCEN
A/D Converter Enable
Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
0
1
read-write
0
Disable
#0
1
Enable
#1
ADCFM
Data Format Of ADC Conversion Result
12
1
read-write
0
Unsigned
#0
1
2'Complemet
#1
ADCIE
A/D Interrupt Enable
A/D conversion end interrupt request is generated if ADCIE bit is set to 1.
1
1
read-write
0
Disable A/D interrupt function
#0
1
Enable A/D interrupt function
#1
HWTRGCOND
Trigger Condition
These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state.
6
2
read-write
0
Low level
#00
1
High level
#01
2
Falling edge
#10
3
Positive edge
#11
HWTRGEN
Trigger Enable
Enable or disable triggering of A/D conversion by external STADC pin.
8
1
read-write
0
Disable
#0
1
Enable
#1
OPMODE
A/D Converter Operation Mode
When changing the operation mode, software should disable SWTRG bit firstly.
2
2
read-write
0
Single conversion
#00
1
Reserved
#01
2
Single-cycle scan
#10
3
Continuous scan
#11
SWTRG
A/D Conversion Start
Note: SWTRG bit can be set to 1 from three sources: software write and external pin STADC. SWTRG is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channel. In continuous scan mode, A/D conversion is continuously performed sequentially until software writes 0 to this bit or chip resets.
11
1
read-write
0
Conversion is stopped and A/D converter enters idle state
#0
1
Start conversion
#1
DAT0
ADC_DAT0
A/D Data Register for the channel defined in CHSEQ0
0x0
-1
read-only
n
0x0
0x0
EXTS
Extension Bits Of RESULT for Different Data Format
If ADCFM is 0 , EXTS all are read as 0 .
If ADCFM is 1 , EXTS all are read as bit RESULT[11].
12
4
read-only
OV
Over Run Flag
If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after ADC_DAT register is read.
16
1
read-only
0
Data in RESULT are recent conversion result
#0
1
Data in RESULT are overwritten
#1
RESULT
A/D Conversion Result
This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit.
0
12
read-only
VALID
Valid Flag
This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read.
17
1
read-only
0
Data in RESULT are not valid
#0
1
Data in RESULT are valid
#1
DAT1
0x4
-1
read-write
n
0x0
0x0
DAT2
0x8
-1
read-write
n
0x0
0x0
DAT3
0xC
-1
read-write
n
0x0
0x0
DAT4
0x10
-1
read-write
n
0x0
0x0
DAT5
0x14
-1
read-write
n
0x0
0x0
DAT6
0x18
-1
read-write
n
0x0
0x0
DAT7
0x1C
-1
read-write
n
0x0
0x0
PGCTL
ADC_PGCTL
ADC Pre-amplifier Gain Control Register
0x3C
-1
read-write
n
0x0
0x0
OPMUTE
Mute Control of First Stage Pre-Amp for Offset Bias Calibration
When this bit is set as 1 , two input end of first stage pre-amp will be shorted, and feedback resistor of this stage will be shorted.
0
1
read-write
0
open
#0
1
short
#1
OS
Configuration for Pre-Amp OP Offset Bias Compensation Voltage
There are 32 levels and 2mV per level @ 5V condition.
6
5
read-write
PAG_I
Gain Setting Bits for the First Stage Of Pre-Amp
11
2
read-write
0
-6 dB,
#00
1
0 dB,
#01
2
8 dB,
#10
3
14 dB,
#11
PAG_II
Gain Setting Bits for the Second Stage Of Pre-Amp
1
5
read-write
0
0 dB,
#00000
1
16 dB,
#00001
2
17 dB,
#00010
3
18 dB,
#00011
31
46 dB
#11111
STATUS
ADC_STATUS
A/D Status Register
0x30
-1
read-write
n
0x0
0x0
ADCMPF0
Compare Flag
When the selected channel A/D conversion result meets setting conditions in ADC_CMP0, then this bit is set to 1. And it is cleared by write 1.
1
1
read-write
0
Converted result RESULT in ADC_DAT does not meet ADC_CMP0 setting
#0
1
Converted result RESULT in ADC_DAT meets ADC_CMP0 setting,
#1
ADCMPF1
Compare Flag
When the selected channel A/D conversion result meets setting conditions in ADC_CMP1, then this bit is set to 1. And it is cleared by write 1.
2
1
read-write
0
Converted result RESULT in ADC_DAT does not meet ADC_CMP1 setting
#0
1
Converted result RESULT in ADC_DAT meets ADC_CMP1 setting,
#1
ADIF
A/D Conversion End Flag
A status flag that indicates the end of A/D conversion.
ADIF is set to 1 under the following two conditions:
When A/D conversion ends in single mode,
When A/D conversion ends on all channels specified by channel sequence register in scan mode.
And it is cleared when 1 is written.
0
1
read-write
BUSY
BUSY/IDLE
This bit is mirror of SWTRG bit in ADC_CTL.
It is read only.
3
1
read-write
0
A/D converter is in idle state
#0
1
A/D converter is busy at conversion
#1
CHANNEL
Current Conversion Channel
It is read only.
4
3
read-write
OV
Over Run Flag
It is a mirror to OV bit in ADC_DATn.
16
8
read-write
VALID
Data Valid Flag
It is a mirror of VALID bit in ADC_DATn.
8
8
read-write
APU
APU Register Map
APU
0x0
0x0
0x8
registers
n
0xC
0x24
registers
n
CH0DAT0
APU_CH0DAT0
APU Channel 0 Data Buffer Register 0
0x10
-1
read-write
n
0x0
0x0
PCM
PCM Data Of Channel 0
This field contains 13 bits PCM data that is one of the mixer input.
The data format of PCM is 2'complement.
0
13
read-write
CH0DAT1
0x14
-1
read-write
n
0x0
0x0
CH0DAT2
0x18
-1
read-write
n
0x0
0x0
CH0DAT3
0x1C
-1
read-write
n
0x0
0x0
CH0DAT4
0x20
-1
read-write
n
0x0
0x0
CH0DAT5
0x24
-1
read-write
n
0x0
0x0
CH0DAT6
0x28
-1
read-write
n
0x0
0x0
CH0DAT7
0x2C
-1
read-write
n
0x0
0x0
CH1DAT0
APU_CH1DAT0
APU Channel 1 Data Buffer Register
0xC
-1
read-write
n
0x0
0x0
PCM1
PCM Data Of Channel 1
This field contains 13 bits PCM data that is one of the mixer input.
The data format of PCM is 2'complement.
0
13
read-write
CTL
APU_CTL
APU Control Register
0x0
-1
read-write
n
0x0
0x0
APUIE
APU Interrupt Enable
6
1
read-write
0
Disable the APU threshold interrupt
#0
1
Enable the APU threshold interrupt
#1
APUIS
APU Interrupt Status
This flag is set by hardware when APU threshold is met. Software can clear this bit by writing a zero to it.
5
1
read-write
0
APU threshold interrupt does not occur
#0
1
APU threshold interrupt occur
#1
BPPAM
Bypass Power Amplifier, DAC Output To Pin
Note: User must set BPPAM to 0 to use SPK+ and SPK- as the power amplifier outputs.
9
1
read-write
0
SPK+ and SPK- are power amplifier outputs
#0
1
No output at SPK-. This setting is for testing only and prohibited for normal operation
#1
DACE
DAC Enable
8
1
read-write
0
Disable DAC function
#0
1
Enable DAC function
#1
DACGN
DAC Output Current Control
This bit is effective only when BPPAM is 1 .
13
1
read-write
0
3mA
#0
1
5mA
#1
PAMPE
Power Amplifier Enable
7
1
read-write
0
Disable PA function
#0
1
Enable PA function
#1
TSHD
APU Interrupt Threshold
0
3
read-write
0
Buffer 0 is read out by APU
#000
1
Buffer 1 is read out by APU
#001
2
Buffer 2 is read out by APU
#010
3
Buffer 3 is read out by APU
#011
4
Buffer 4 is read out by APU
#100
5
Buffer 5 is read out by APU
#101
6
Buffer 6 is read out by APU
#110
7
Buffer 7 is read out by APU
#111
VM
APU_VM
APU Volume Control Register
0x4
-1
read-write
n
0x0
0x0
VOLUM
APU Volume Adjustment
0
3
read-write
0
0 dB
#000
1
-3 dB
#001
2
-6 dB
#010
3
-9 dB
#011
4
-12 dB
#100
5
-15 dB
#101
6
-18 dB
#110
7
Reserved
#111
CFG
CONFIGURE Register Map
CONFIGURE
0x0
0x0
0x4
registers
n
CONFIG
CONFIG
User Configuration Memory
0x0
-1
read-write
n
0x0
0x0
CFOSC
Power-on Clock Source Selection
24
3
read-write
CKF
Clock Filter Enable
28
1
read-write
0
Disable clock filter
#0
1
Enable clock filter
#1
CVDEN
Voltage Detector Enable
23
1
read-write
0
Enable Voltage Detector after power on
#0
1
Disable Voltage Detector after power on
#1
CVDTV
Voltage Detector Threshold Voltage Selection
21
1
read-write
CWDTEN
Watchdog Enable
31
1
read-write
0
Watchdog is disabled after power on
#0
1
Watchdog is enabled after power on
#1
LOCK
Security Lock
When flash data is locked,(1) only device ID, CONFIG can be read by Writer and ICP thru serial debug interface. Other data are locked as 0xFFFFFFFF.(2) ISP can read data anywhere regardless of LOCK bit value. (3) SWD interface cannot access internal RAM and Flash
1
1
read-write
0
Flash data are locked
#0
1
Flash data are not locked
#1
CLK
CLK Register Map
CLK
0x0
0x0
0xC
registers
n
0x10
0xC
registers
n
0x20
0x4
registers
n
AHBCLK
CLK_AHBCLK
AHB Device Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
ISPCKEN
Flash ISP Engine Clock Enable Control
2
1
read-write
0
To disable the Flash ISP engine clock
#0
1
To enable the Flash ISP engine clock
#1
APBCLK
CLK_APBCLK
APB Device Clock Enable Control Register
0x8
-1
read-write
n
0x0
0x0
ADC_EN
Audio Analog-Digital-Converter (ADC) Clock Enable Control
28
1
read-write
0
Disable
#0
1
Enable
#1
APU_EN
APU Clock Enable Control
30
1
read-write
0
To disable the APU engine clock
#0
1
To enable the APU engine clock
#1
PWM_EN
PWM Block Clock Enable Control
20
1
read-write
0
Disable
#0
1
Enable
#1
RTC_EN
Real-Time-Clock APB Interface Clock Control
This bit is used to control the RTC APB clock only. The RTC engine clock source is from the 32.768KHz crystal.
1
1
read-write
0
Disable
#0
1
Enable
#1
SPI0_EN
SPI0 Clock Enable Control
12
1
read-write
0
Disable
#0
1
Enable
#1
SPI1_EN
SPI1 Clock Enable Control
13
1
read-write
0
Disable
#0
1
Enable
#1
TMR0_EN
Timer0 Clock Enable Control
2
1
read-write
0
Disable
#0
1
Enable
#1
TMR1_EN
Timer1 Clock Enable Control
3
1
read-write
0
Disable
#0
1
Enable
#1
TMR2_EN
Timer2 Clock Enable Control
4
1
read-write
0
Disable
#0
1
Enable
#1
TMRF_EN
TimerF Clock Enable Control
5
1
read-write
0
Disable
#0
1
Enable
#1
USBD_EN
USB FS Device Controller Clock Enable Control
27
1
read-write
0
Disable
#0
1
Enable
#1
WDT_EN
Watchdog Clock Enable Control
This bit is the protected bit. To program this bit needs an open lock sequence, write 59h , 16h , 88h to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
The default bit value is set according to the Flash Controller User Configuration Register CONFIG[31].
0
1
read-write
0
Disable
#0
1
Enable
#1
CLKDIV
CLK_CLKDIV
Clock Divider Number Register
0x18
-1
read-write
n
0x0
0x0
ADCDIV
ADC Clock Divide Number From ADC Clock Source
The ADC clock must meet the constraint: ADCLK ( HCKL/2
16
8
read-write
HCLKDIV
HCLK Clock Divide Number From HCLK Clock Source
0
4
read-write
CLKSEL0
CLK_CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLKSEL
HCLK clock source select.
Note:
1. Before clock switch, the related clock sources (pre-select and new-select) must be turned on.
2. The 3-bit default value is reloaded with the value of CFOSC (CONFIG[26:24]) in user configuration register in Flash controller by any reset. Therefore the default value is either 001b or 111b. Besides, before chip enters power down mode, HCLKSEL only can be either 001b or 111b.
0
3
read-write
0
clock source from external 32KHz crystal clock
#000
1
clock source from external 12MHz (or 6MHz) crystal clock
#001
2
clock source from PLL1 output
#010
4
clock source from PLL2 output
#100
7
clock source from internal 24MHz oscillator clock
#111
CLKSEL1
CLK_CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
ADCSEL
ADC Clock Source Select
2
2
read-write
0
Clock source from PLL2 clock
#00
1
Clock source from external 12MHz (or 6MHz) crystal clock
Clock source from internal 24MHz oscillator clock
#01
PWMSEL
PWM Timer Clock Source Select
28
2
read-write
0
Clock source from HCLK
#00
1
Clock source from external 32KHz crystal clock
#01
2
Clock source from external 12MHz (or 6MHz) crystal clock
#10
3
Clock source from internal 24MHz oscillator clock
#11
TMR0SEL
Timer0 Clock Source Select
8
3
read-write
0
Clock source from HCLK
#000
1
Clock source from external 32KHz crystal clock
Clock source from internal 24MHz oscillator clock
#001
2
Clock source from external 12MHz (or 6MHz) crystal clock
#010
3
Clock source from external trigger
#011
TMR1SEL
Timer1 Clock Source Select
12
3
read-write
0
Clock source from HCLK
#000
1
Clock source from external 32KHz crystal clock
Clock source from internal 24MHz oscillator clock
#001
2
Clock source from external 12MHz (or 6MHz) crystal clock
#010
3
Clock source from external trigger
#011
TMR2SEL
Timer2 Clock Source Select
16
3
read-write
0
Clock source from HCLK
#000
1
Clock source from external 32KHz crystal clock
Clock source from internal 24MHz oscillator clock
#001
2
Clock source from external 12MHz (or 6MHz) crystal clock
#010
3
Clock source from external trigger
#011
TMRFSEL
TimerF Clock Source Select
20
3
read-write
0
Clock source from external 32KHz crystal clock / 32
#000
1
Clock source from external 32KHz crystal clock / (4x32)
#001
2
Clock source from external 12MHz (or 6MHz) crystal clock / 16384
#010
3
Clock source from external 12MHz (or 6MHz) crystal clock / (4x16384)
#011
6
Clock source from 24MHz OSC clock / 32768
#110
7
Clock source from 24MHz OSC clock / (4x32768)
#111
WDTSEL
Watchdog Timer Clock Source Selection (Write Protect)
These bits are protected bits. To program these bits needs an open lock sequence, write 59h , 16h , 88h to SYS_REGLCTL to un-lock these bits. Refer to the register SYS_REGLCTL at address SYS_BA+0x100..
0
2
read-write
0
Clock source from HCLK/2048 clock
#00
1
Clock source from external 32KHz crystal clock
#01
2
Clock source from external 12MHz (or 6MHz) crystal clock
#10
3
Clock source from internal 24MHz oscillator clock
#11
PLLCON
CLK_PLLCON
PLL Control Register
0x20
-1
read-write
n
0x0
0x0
PWRCTL
CLK_PWRCTL
System Power Control Register
0x0
-1
read-write
n
0x0
0x0
OSC24M_EN
Internal 24MHz Oscillator Control
After reset, this bit is 1 .
2
1
read-write
0
24MHz oscillation is disabled
#0
1
24MHz Oscillation is enabled
#1
PD_WAIT_CPU
This Bit Controls The Power Down Entry Condition
Please refer to PWR_DOWN bit for the usage of PD_WAIT_CPU bit.
The following is a brief description of PD_WAIT_CPU bit.
8
1
read-write
0
Chip is at normal mode. Note that PWR_DOWN cannot be set to 1 when PD_WAIT_CPU value remains at 0, otherwise the chip may not wake up normally
#0
1
Chip waits to enter power-down mode
#1
PWR_DOWN
System Power Down Active Or Enable Bit
7
1
read-write
0
Chip operates at normal mode
#0
1
Chip is standing by power-down entry condition
#1
VOUTX_PD
Driving Out 3.0V (Through VOUTX Pad) LDO Control
3
1
read-write
0
3.0V LDO (VOUTX) is enabled
#0
1
3.0V LDO (VOUTX) is disabled
#1
WINT_EN
Enable Interrupt When Wake Up From Power Down Mode
5
1
read-write
0
Disable,
#0
1
Enable. The interrupt will occur when MCU wakes up from power down mode
#1
WINT_STS
Chip Power Down Wake Up Status Flag
Set by power down wake up , it indicates that resume from power down mode.
The flag is set if the GPIO, USB, WDT or RTC wakeup.
Note: Write 1 to clear the bit.
6
1
read-write
WU_DLY
Enable The Wake Up Delay Counter
When the chip wakes up from idle mode, the clock control will delay some clock cycles to wait the 12MHz (or 6MHz) crystal or the internal 24MHz oscillator clock stable.
4
1
read-write
0
Disable the clock cycles delay
#0
1
Enable the clock cycles delay. The delay is 4096 clock cycles for 12MHz (or 6MHz) crystal, 256 clock cycles for 24MHz oscillator
#1
XTL12M_EN
External 12MHz (or 6MHz) Crystal Oscillator Control
This bit is set by the combination logic of flash controller user configuration register CONFIG[26:24] after power on.
0
1
read-write
0
12MHz (or 6MHz) crystal oscillation is disabled
#0
1
12MHz (or 6MHz) crystal oscillation is enabled
#1
XTL32K_EN
External 32.768KHz Crystal Control
After reset, this bit is 0 .
1
1
read-write
0
32.768KHz Crystal is disabled
#0
1
32.768KHz Crystal is enabled
#1
FMC
FMC Register Map
FMC
0x0
0x0
0x14
registers
n
0x18
0x4
registers
n
FAT
FMC_FAT
Flash Access Time Control Register
0x18
-1
read-write
n
0x0
0x0
ISPADDR
FMC_ISPADDR
ISP Address Register
0x4
-1
read-write
n
0x0
0x0
ISPADDR
ISP Address Register
This is the memory address register that a subsequent ISP command will access. ISP operation are carried out on 32-bit word only, consequently ISPADDR [1:0] must be 00b for correct ISP operation.
N572F064 equips with an 16Kx32 bits embedded flash.
0
32
read-write
ISPCMD
FMC_ISPCMD
ISP Command Register
0xC
-1
read-write
n
0x0
0x0
CMD
ISP Command
Operation Mode : CMD
-------------------- -------
Standby : 0x3X
Read CID : 0x0B
Read DID : 0x0C
Flash Page Erase : 0x22
Flash Program : 0x21
Flash Read : 0x00
0
6
read-write
ISPCTL
FMC_ISPCTL
ISP Control Register
0x0
-1
read-write
n
0x0
0x0
CFGUEN
CONFIG Update Enable
When enabled, ISP functions can access the CONFIG address space and modify device configuration area.
4
1
read-write
0
Disable
#0
1
Enable
#1
ET
Flash Page Erase Time
12
3
read-write
0
20 ms (default)
#000
1
25 ms
#001
2
30 ms
#010
3
35 ms
#011
4
3 ms
#100
5
5 ms
#101
6
10 ms
#110
7
15 ms
#111
EWEN
Enable Erase/Write Of ISP Function
1
1
read-write
0
Disable erase/write
#0
1
Enable erase/write
#1
ISPEN
ISP Enable
0
1
read-write
0
Disable ISP function
#0
1
Enable ISP function
#1
ISPFF
ISP Fail Flag
This bit is set by hardware when a triggered ISP meets any of the following conditions:
MCU writes (or erase) to Flash when EWEN is 0 .
Destination address is illegal, such as over an available range.
Write 1 to clear.
6
1
read-write
PT
Flash Program Time
8
3
read-write
0
40 (s (default)
#000
1
45 (s
#001
2
50 (s
#010
3
55 (s
#011
4
20 (s
#100
5
25 (s
#101
6
30 (s
#110
7
35 (s
#111
ISPDAT
FMC_ISPDAT
ISP Data Register
0x8
-1
read-write
n
0x0
0x0
ISPDAT
ISP Data Register
Write data to this register before an ISP program operation.
Read data from this register after an ISP read operation
0
32
read-write
ISPTRG
FMC_ISPTRG
ISP Trigger Control Register
0x10
-1
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger
Write 1 to start ISP operation. This bit will be cleared to 0 by hardware automatically when ISP operation is finished.
0
1
read-write
0
ISP operation is finished
#0
1
ISP is ongoing
#1
GPIO
GPIO Register Map
GPIO
0x0
0x0
0x14
registers
n
0x18
0xC
registers
n
0x40
0x14
registers
n
0x58
0xC
registers
n
PA_DATMSK
PA_DATMSK
GPIO PA Data Output Write Mask
0xC
-1
read-write
n
0x0
0x0
DATMSK
Port [A/B] Pin[N] Data Output Write Mask
These bits are used to protect the corresponding register of Px_DOUT[n]. When set the DATMSK[n] to 1 , the corresponding Px_DOUT[n] bit is writing protected.
0
16
read-write
0
The corresponding Px_DOUT[n] bit can be updated
0
1
The corresponding Px_DOUT[n] bit is read only
1
PA_DINOFF
PA_DINOFF
GPIO PA Digital Input Path Disable Control
0x4
-1
read-write
n
0x0
0x0
DINOFF0
Port [A/B] Pin[N] Digital Input Path Disable Control
16
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
DINOFF1
Port [A/B] Pin[N] Digital Input Path Disable Control
17
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
DINOFF10
Port [A/B] Pin[N] Digital Input Path Disable Control
26
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
DINOFF11
Port [A/B] Pin[N] Digital Input Path Disable Control
27
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
DINOFF12
Port [A/B] Pin[N] Digital Input Path Disable Control
28
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
DINOFF13
Port [A/B] Pin[N] Digital Input Path Disable Control
29
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
DINOFF14
Port [A/B] Pin[N] Digital Input Path Disable Control
30
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
DINOFF15
Port [A/B] Pin[N] Digital Input Path Disable Control
31
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
DINOFF2
Port [A/B] Pin[N] Digital Input Path Disable Control
18
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
DINOFF3
Port [A/B] Pin[N] Digital Input Path Disable Control
19
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
DINOFF4
Port [A/B] Pin[N] Digital Input Path Disable Control
20
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
DINOFF5
Port [A/B] Pin[N] Digital Input Path Disable Control
21
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
DINOFF6
Port [A/B] Pin[N] Digital Input Path Disable Control
22
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
DINOFF7
Port [A/B] Pin[N] Digital Input Path Disable Control
23
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
DINOFF8
Port [A/B] Pin[N] Digital Input Path Disable Control
24
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
DINOFF9
Port [A/B] Pin[N] Digital Input Path Disable Control
25
1
read-write
0
Px.n Digital input path Enable (Default)
#0
1
Px.n Digital input path Disable (digital input tied to low)
#1
PA_DOUT
PA_DOUT
GPIO PA Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT
Port [A/B] Pin[N] Output Value
Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
0
16
read-write
0
GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set
0
1
GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set
1
PA_INTEN
PA_INTEN
GPIO PA Interrupt Enable
0x1C
-1
read-write
n
0x0
0x0
FLIEN0
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
0
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN1
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
1
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN10
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
10
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN11
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
11
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN12
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
12
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN13
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
13
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN14
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
14
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN15
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
15
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN2
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
2
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN3
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
3
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN4
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
4
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN5
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
5
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN6
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
6
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN7
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
7
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN8
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
8
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
FLIEN9
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
9
1
read-write
0
Disable Px.n for low-level or high-to-low interrupt
#0
1
Enable Px.n for low-level or high-to-low interrupt
#1
RHIEN0
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
16
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN1
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
17
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN10
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
26
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN11
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
27
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN12
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
28
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN13
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
29
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN14
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
30
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN15
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
31
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN2
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
18
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN3
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
19
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN4
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
20
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN5
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
21
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN6
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
22
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN7
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
23
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN8
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
24
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
RHIEN9
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function.
When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 :
If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
25
1
read-write
0
Disable Px.n for low-to-high or level-high interrupt
#0
1
Enable Px.n for low-to-high or level-high interrupt
#1
PA_INTSRC
PA_INTSRC
GPIO PA Interrupt Source Flag
0x20
-1
read-write
n
0x0
0x0
INTSRC
Port [A/B] Interrupt Source Flag
Read operation:
0
16
read-write
0
No interrupt from Px.n.
No action
0
1
Px.n generated an interrupt.
Clear the corresponding pending interrupt
1
PA_INTTYPE
PA_INTTYPE
GPIO PA Interrupt Trigger Type
0x18
-1
read-write
n
0x0
0x0
TYPE
Port [A/B] Pin[N] Edge Or Level Detection Interrupt Trigger Type Control
TYPE[n] is used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is level triggered, the input source is sampled by one HCLK clock to generate the interrupt
Note: If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set, the setting is ignored and no interrupt will occur
0
16
read-write
0
Edge triggered interrupt
0
1
Level triggered interrupt
1
PA_MODE
PA_MODE
GPIO PA Pin I/O Mode Control
0x0
-1
read-write
n
0x0
0x0
MODE0
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
0
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE1
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
2
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE10
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
20
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE11
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
22
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE12
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
24
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE13
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
26
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE14
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
28
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE15
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
30
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE2
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
4
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE3
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
6
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE4
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
8
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE5
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
10
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE6
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
12
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE7
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
14
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE8
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
16
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
MODE9
Port [A/B] Pin[N] I/O Mode Control
Determine each I/O type of GPIO Px pins
18
2
read-write
0
GPIO Px[n] pin is in INPUT mode
#00
1
GPIO Px[n] pin is in OUTPUT mode
#01
2
GPIO Px[n] pin is in Open-Drain mode
#10
3
GPIO Px[n] pin is in Quasi-bidirectional mode
#11
PA_PIN
PA_PIN
GPIO PA Pin Value
0x10
-1
read-only
n
0x0
0x0
PIN
Port [A/B] Pin[N] Pin Values
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
0
16
read-only
PB_DATMSK
0x4C
-1
read-write
n
0x0
0x0
PB_DINOFF
0x44
-1
read-write
n
0x0
0x0
PB_DOUT
0x48
-1
read-write
n
0x0
0x0
PB_INTEN
0x5C
-1
read-write
n
0x0
0x0
PB_INTSRC
0x60
-1
read-write
n
0x0
0x0
PB_INTTYPE
0x58
-1
read-write
n
0x0
0x0
PB_MODE
0x40
-1
read-write
n
0x0
0x0
PB_PIN
0x50
-1
read-write
n
0x0
0x0
INT
INT Register Map
INT
0x0
0x0
0x3C
registers
n
0x80
0x8
registers
n
IRQ0_SRC
IRQ0_SRC
IRQ0 (WDT) Interrupt Source Identity Register
0x0
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: WDT_INT
0
3
read-only
IRQ10_SRC
IRQ10_SRC
IRQ10 (PWM) Interrupt Source Identity Register
0x28
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PWM_INT
0
3
read-only
IRQ11_SRC
IRQ11_SRC
IRQ11 (SPI1) Interrupt Source Identity Register
0x2C
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: SPI1_INT
0
3
read-only
IRQ12_SRC
IRQ12_SRC
IRQ12 (TimerF) Interrupt Source Identity Register
0x30
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: TimerF_INT
0
3
read-only
IRQ13_SRC
IRQ13_SRC
IRQ13 (RTC) Interrupt Source Identity Register
0x34
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: RTC_INT
0
3
read-only
IRQ14_SRC
IRQ14_SRC
IRQ14 (PWRWU) Interrupt Source Identity Register
0x38
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PWRWU_INT
0
3
read-only
IRQ1_SRC
IRQ1_SRC
IRQ1 (APU) Interrupt Source Identity Register
0x4
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: APU_INT
0
3
read-only
IRQ2_SRC
IRQ2_SRC
IRQ2 (ADC) Interrupt Source Identity Register
0x8
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: ADC_INT
0
3
read-only
IRQ3_SRC
IRQ3_SRC
IRQ3 (EXINT) Interrupt Source Identity Register
0xC
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: External interrupt
0
3
read-only
IRQ4_SRC
IRQ4_SRC
IRQ4 (USBD) Interrupt Source Identity Register
0x10
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: USBD_INT
0
3
read-only
IRQ5_SRC
IRQ5_SRC
IRQ5 (Timer0) Interrupt Source Identity Register
0x14
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: Timer0_INT
0
3
read-only
IRQ6_SRC
IRQ6_SRC
IRQ6 (Timer1) Interrupt Source Identity Register
0x18
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: Timer1_INT
0
3
read-only
IRQ7_SRC
IRQ7_SRC
IRQ7 (Timer2) Interrupt Source Identity Register
0x1C
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: Timer2_INT
0
3
read-only
IRQ8_SRC
IRQ8_SRC
IRQ8 (GPA/B) Interrupt Source Identity Register
0x20
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: GPB_INT
Bit0: GPA_INT
0
3
read-only
IRQ9_SRC
IRQ9_SRC
IRQ9 (SPI0) Interrupt Source Identity Register
0x24
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: SPI0_INT
0
3
read-only
MCU_IRQ
MCU_IRQ
MCU IRQ Number Identify Register
0x84
-1
read-write
n
0x0
0x0
MCU_IRQ
MCU IRQ Source Test Mode
The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to MCU Cortex-M0. There are two modes to generate interrupt to MCU Cortex-M0, the normal mode and test mode.
When MCU_IRQ[n] is 0 : Writing MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 IRQ[n].
When MCU_IRQ[n] is 1 (meaning an interrupt is asserted): Writing MCU_IRQ[n] 1 will clear the interrupt writing MCU_IRQ[n] 0 : has no effect.
Note: IRQ15 is reserved in N572F064_F065.
0
16
read-write
NMI_SEL
NMI_SEL
NMI Source Interrupt Select Control Register
0x80
-1
read-write
n
0x0
0x0
IRQ_TM
IRQ Test Mode
This bit is the protected bit. To program this bit needs an open lock sequence, write 59h , 16h , 88h to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
7
1
read-write
0
The interrupt register MCU_IRQ operates in normal mode. The MCU_IRQ collects all the interrupts from the peripheral and generates interrupt to MCU
#0
1
All the interrupts from peripheral to MCU are blocked. The peripheral IRQ signals (0-15) are replaced by the value in the MCU_IRQ register
#1
NMI_SEL
NMI Source Interrupt Select
The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[15:0].
The NMI_SEL bit is used to select the NMI interrupt source.
Note: IRQ15 is reserved in N572F064_F065
0
4
read-write
PWM
PWM Register Map
PWM
0x0
0x0
0x18
registers
n
0x1C
0x4
registers
n
0x28
0x4
registers
n
0x34
0x4
registers
n
0x40
0x8
registers
n
0x50
0x4
registers
n
0x58
0x8
registers
n
0x7C
0x4
registers
n
CAPCTL
PWM_CAPCTL
Capture Control Register
0x50
-1
read-write
n
0x0
0x0
CAPEN
Capture Channel Input Transition Enable/Disable
When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.
When disabled, Capture function is inactive as is interrupt.
3
1
read-write
0
Disable capture function
#0
1
Enable capture function
#1
CAPIF
Capture Interrupt Indication Flag
Note:If this bit is 1 , PWM counter will not be reloaded when next capture interrupt occurs.
4
1
read-write
CAPINV
Inverter ON/OFF
0
1
read-write
0
Inverter OFF
#0
1
Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
#1
CFLIEN
Falling Latch Interrupt Enable ON/OFF
When enabled, capture block generates an interrupt on falling edge of input.
2
1
read-write
0
Disable falling latch interrupt
#0
1
Enable falling latch interrupt
#1
CFLIF
PWM_FCAPDAT Latched Indicator Bit
When input channel has a falling transition, PWM_FCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
7
1
read-write
CRLIEN
Rising Latch Interrupt Enable ON/OFF
When enabled, capture block generates an interrupt on rising edge of input.
1
1
read-write
0
Disable rising latch interrupt
#0
1
Enable rising latch interrupt
#1
CRLIF
PWM_RCAPDAT Latched Indicator Bit
When input channel has a rising transition, PWM_RCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
6
1
read-write
CLKDIV
PWM_CLKDIV
PWM Clock Select Register
0x4
-1
read-write
n
0x0
0x0
CLKDIV
PWM Timer Clock Source Selection
Value : Input clock divided by
000 : 2
001 : 4
010 : 8
011 : 16
1xx : 1
0
3
read-write
CLKPSC
PWM_CLKPSC
PWM Prescaler Register
0x0
-1
read-write
n
0x0
0x0
CLKPSC
Clock Prescaler For PWM Timer
Clock input is divided by (CLKPSC + 1)
0
8
read-write
DZI0
Dead Zone Interval Register 0
These 8 bits determine dead zone length.
The unit time of dead zone length is that from clock selector.
16
8
read-write
DZI1
Dead Zone Interval Register 1
These 8 bits determine dead zone length.
The unit time of dead zone length is that from clock selector.
24
8
read-write
CMPDAT0
PWM_CMPDAT0
PWM Comparator Register 0
0x10
-1
read-write
n
0x0
0x0
CMP
PWM Comparator Register
CMP determines the PWM duty ratio.
Assumption: PWM output initial is high
Note2: Any write to CMP will take effect in next PWM cycle.
0
16
read-write
CMPDAT1
0x1C
-1
read-write
n
0x0
0x0
CMPDAT2
0x28
-1
read-write
n
0x0
0x0
CMPDAT3
0x34
-1
read-write
n
0x0
0x0
CNT
PWM_CNT
PWM Counter Register
0x14
-1
read-only
n
0x0
0x0
CNT
PWM Counter Register
Reports the current value of the 16-bit down counter.
0
16
read-only
CTL
PWM_CTL
PWM Control Register
0x8
-1
read-write
n
0x0
0x0
CNTEN
PWM-Timer Enable
0
1
read-write
0
Stop PWM-Timer Running
#0
1
Enable PWM-Timer
#1
CNTMODE
PWM-Timer Auto-Reload/One-Shot Mode
3
1
read-write
0
One-Shot Mode
#0
1
Auto-reload Mode
#1
DTEN0
Dead-Zone 0 Generator Enable/Disable
4
1
read-write
0
Disable
#0
1
Enable
#1
DTEN1
Dead-Zone 1 Generator Enable/Disable
5
1
read-write
0
Disable
#0
1
Enable
#1
PINV
PWM-Timer Output Inverter ON/OFF
2
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
FCAPDAT
PWM_FCAPDAT
Capture Falling Latch Register
0x5C
-1
read-only
n
0x0
0x0
FCAPDAT
Capture Falling Latch Register
In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal.
0
16
read-only
INTEN
PWM_INTEN
PWM Interrupt Enable Register
0x40
-1
read-write
n
0x0
0x0
PIEN
PWM Timer Interrupt Enable
0
1
read-write
0
Disable
#0
1
Enable
#1
INTSTS
PWM_INTSTS
PWM Interrupt Flag Register
0x44
-1
read-write
n
0x0
0x0
PIF
PWM Timer Interrupt Flag
Flag is set by hardware when PWM down counter reaches zero, software can clear this bit by writing '1' to it.
0
1
read-write
PCEN
PWM_PCEN
PWM Output and Capture Input Enable Register
0x7C
-1
read-write
n
0x0
0x0
CAPINEN
Capture Input Enable Register
8
1
read-write
0
OFF (PB.12 pin input disconnected from Capture block)
#0
1
ON (PB.12 pin, if in PWM alternative function, will be configured as an input and fed to capture function)
#1
POEN0
PWM0 Output Enable Register
Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Error! Reference source not found.)
0
1
read-write
0
Disable PWM0 output to pin
#0
1
Enable PWM0 output to pin
#1
POEN1
PWM1 Output Enable Register
Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Error! Reference source not found.)
1
1
read-write
0
Disable PWM1 output to pin
#0
1
Enable PWM1 output to pin
#1
POEN2
PWM2 Output Enable Register
Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Error! Reference source not found.)
2
1
read-write
0
Disable PWM2 output to pin
#0
1
Enable PWM2 output to pin
#1
POEN3
PWM3 Output Enable Register
Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPB_MFP Error! Reference source not found.)
3
1
read-write
0
Disable PWM3 output to pin
#0
1
Enable PWM3 output to pin
#1
PERIOD
PWM_PERIOD
PWM Period Register
0xC
-1
read-write
n
0x0
0x0
PERIOD
PWM Counter/Timer Reload Value
PERIOD determines the PWM period.
0
16
read-write
RCAPDAT
PWM_RCAPDAT
Capture Rising Latch Register
0x58
-1
read-only
n
0x0
0x0
RCAPDAT
Capture Rising Latch Register
In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal.
0
16
read-only
RTC
RTC Register Map
RTC
0x0
0x0
0x4
registers
n
CTL
RTC_CTL
RTC Control Register
0x0
-1
read-write
n
0x0
0x0
RTCE
RTC Enable
2
1
read-write
0
Disable RTC function
#0
1
Enable RTC function
#1
RTIE
RTC Interrupt Enable
1
1
read-write
0
Disable the RTC interrupt
#0
1
Enable the RTC interrupt
#1
RTIF
RTC Interrupt Flag
If the RTC interrupt is enabled, then the hardware will set this bit to indicate that the RTC interrupt has occurred. If the RTC interrupt is not enabled, then this bit indicates that a timeout period has elapsed.
Note: This bit is cleared by writing 1 to this bit.
0
1
read-write
0
RTC interrupt does not occur
#0
1
RTC interrupt occurs
#1
RTIS
RTC Timer Interval Select
These two bits select the timeout interval for the RTC.
3
2
read-write
0
Time-out frequency is 0.25Hz,
#00
1
Time-out frequency is 2Hz,
#01
2
Time-out frequency is 8Hz,
#10
3
Time-out frequency is 32Hz
#11
SCS
SCS Register Map
SCS
0x0
0x100
0x4
registers
n
0x180
0x4
registers
n
0x200
0x4
registers
n
0x280
0x4
registers
n
0x400
0x10
registers
n
NVIC_ICER
NVIC_ICER
IRQ0 ~ IRQ15 Clear-Enable Control Register
0x180
-1
read-write
n
0x0
0x0
CLRENA
Interrupt Clear-Enable Bit
The NVIC_ICER register disables interrupts, and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).
Write Operation:
0
16
read-write
0
No effect.
Interrupt Disabled
0
1
Interrupt Disabled.
Interrupt Enabled
1
NVIC_ICPR
NVIC_ICPR
IRQ0 ~ IRQ15 Clear-Pending Control Register
0x280
-1
read-write
n
0x0
0x0
CLRPEND
Interrupt Clear-Pending Bit
The NVIC_ICPR register removes the pending state of associated interrupts, and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).
Write Operation:
0
16
read-write
0
No effect.
Interrupt is not pending
0
1
Removes pending state of an interrupt.
Interrupt is pending
1
NVIC_IPR0
NVIC_IPR0
IRQ0 ~ IRQ3 Priority Control Register
0x400
-1
read-write
n
0x0
0x0
PRI_0
Priority Of IRQ0
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_1
Priority Of IRQ1
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_2
Priority Of IRQ2
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_3
Priority Of IRQ3
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR1
NVIC_IPR1
IRQ4 ~ IRQ7 Priority Control Register
0x404
-1
read-write
n
0x0
0x0
PRI_4
Priority Of IRQ4
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_5
Priority Of IRQ5
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_6
Priority Of IRQ6
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_7
Priority Of IRQ7
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR2
NVIC_IPR2
IRQ8 ~ IRQ11 Priority Control Register
0x408
-1
read-write
n
0x0
0x0
PRI_10
Priority Of IRQ10
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_11
Priority Of IRQ11
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
PRI_8
Priority Of IRQ8
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_9
Priority Of IRQ9
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
NVIC_IPR3
NVIC_IPR3
IRQ12 ~ IRQ15 Priority Control Register
0x40C
-1
read-write
n
0x0
0x0
PRI_12
Priority Of IRQ12
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_13
Priority Of IRQ13
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_14
Priority Of IRQ14
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_15
Priority Of IRQ15
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_ISER
NVIC_ISER
IRQ0 ~ IRQ15 Set-Enable Control Register
0x100
-1
read-write
n
0x0
0x0
SETENA
Interrupt Set-Enable Bit
The NVIC_ISER register enables interrupts, and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).
Write Operation:
0
16
read-write
0
No effect.
Interrupt Disabled
0
1
Interrupt Enabled
1
NVIC_ISPR
NVIC_ISPR
IRQ0 ~ IRQ15 Set-Pending Control Register
0x200
-1
read-write
n
0x0
0x0
SETPEND
Interrupt Set-Pending Bit
The NVIC_ISPR register forces interrupts into the pending state, and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).
Write Operation:
0
16
read-write
0
No effect.
Interrupt is not pending
0
1
Changes interrupt state to pending.
Interrupt is pending
1
SPI0
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
SPI_CLKDIV
SPI_CLKDIV
Clock Divider Register
0x4
-1
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register
The value in this field is the frequency divider of the system clock, PCLK, to generate the serial clock on the output (SPICLK).The desired frequency is obtained according to the following equation:
/
NOTE: Suggest DIVIDER should be at least 1 in master mode.
0
16
read-write
SPI_CTL
SPI_CTL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity
11
1
read-write
0
SPI_SCLKn idle low
#0
1
SPI_SCLKn idle high
#1
DWIDTH
Transmit Bit Length
This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.
3
5
read-write
GO_BUSY
Go And Busy Status
NOTE: All registers should be set readily before writing 1 to the GO_BUSY bit. When a transfer is in progress, writing to any register of the SPI core has no effect.
0
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit starts the transfer. This bit remains 1 during the transfer and is automatically cleared after the transfer is finished
#1
LSB
Send LSB First
10
1
read-write
0
The MSB is transmitted/received first (which bit in SPI_TXn/SPI_RXn is MSB is dependent on DWIDTH)
#0
1
The LSB (SPI_TXn[0]) is sent first to SPI_MOSIn, and the first bit received from SPI_MISOn will be put in the LSB (SPI_RXn[0])
#1
REORDER
BYTE ENDIAN
20
1
read-write
0
Disable the BYTE ENDIAN
#0
1
Enable the BYTE ENDIAN. Only the 16, 24, and 32 bits which are defined in DWIDTH are supported
#1
RX_NEG
Receive On Negative Edge
1
1
read-write
0
The input on SPI_MISOn is latched on the rising edge of SPI_SCLKn
#0
1
The input on SPI_MISOn is latched on the falling edge of SPI_SCLKn
#1
SUSPITV
Suspend Interval (Master Mode Only)
(SUSPITV+2)* SPI_SCLKn clock cycles
Note: SUSPITV cannot be 0 for SPI0.
12
4
read-write
TX_NEG
Transmit On Negative Edge
2
1
read-write
0
The output on SPI_MOSIn is changed on the rising edge of SPI_SCLKn
#0
1
The output on SPI_MOSIn is changed on the falling edge of SPI_SCLKn
#1
TX_NUM
Transmit/Receive Numbers
This field specifies how many transmit/receive numbers should be executed in one transfer.
8
2
read-write
0
Only one transmit/receive will be executed in one transfer
#00
1
Two successive transmit/receive will be executed in one transfer.
Reserved
#01
UNIT_INTEN
Unit Transfer Interrupt Enable
17
1
read-write
0
Disable SPI Unit Transfer Interrupt
#0
1
Enable SPI Unit Transfer Interrupt to CPU
#1
UNIT_INTSTS
Unit Transfer Interrupt Status
Note: This bit is read only, but can be cleared by writing 1 to this bit.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
-1
read-only
n
0x0
0x0
RX
Data Receive Register
Note: The Data Receive Registers are read only registers. A Write to these registers will actually modify the Data Transmit Registers because those registers share the same flip-flops.
0
32
read-only
SPI_RX1
0x14
-1
read-write
n
0x0
0x0
SPI_SSCTL
SPI_SSCTL
Slave Select Register
0x8
-1
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select
3
1
read-write
0
Slave select signal (SPI_SSBx0/SPI_SSBx1) is asserted and de-asserted by setting and clearing related bit SS
#0
1
Slave select signal (SPI_SSBx0/SPI_SSBx1) is generated automatically. It means that slave select signal, which is set in bits SS, is asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and is de-asserted after the transfer is finished
#1
SS
Slave Select Pin Control (Master Mode Only)
If AUTOSS bit is 0,
SPIn_SSBx0 and SPIn_SSBx1 output are determined by SS[0] and SS[1] respectively.
0
2
read-write
0
Any bit location of this field forces the pin to inactive state.
Any bit location of this field will select appropriate SPIn_SSBx0/SPIn_SSBx1 pin to be driven to inactive state
0
1
Any bit location of this field forces the proper SPIn_SSBx0/SPIn_SSBx1 pin to an active state
Any bit location of this field will select appropriate SPIn_SSBx0/SPIn_SSBx1 pin to be automatically driven to active state for the duration of the transmit/receive, and to be driven to inactive state for the rest of the time. The active state of SPIn_SSBx0/SPIn_SSBx1 is specified in SS_LVL bit (SPI_SSCTL[2])
1
SS_LVL
Slave Select Active Level
It defines the active level of device/slave select signal.
2
1
read-write
0
The SPI_SSBx0/SPI_SSBx1 slave select signal is active Low
#0
1
The SPI_SSBx0/SPI_SSBx1 slave select signal is active High
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
-1
write-only
n
0x0
0x0
TX
Data Transmit Register
Note: The SPI_RXn and SPI_TXn registers share the same flip-flops, which mean that what is received in one transfer will be transmitted in the next transfer if there is not any write to the SPI_TXn register between the two transfers.
0
32
write-only
SPI_TX1
0x24
-1
read-write
n
0x0
0x0
SPI1
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
SPI_CLKDIV
SPI_CLKDIV
Clock Divider Register
0x4
-1
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register
The value in this field is the frequency divider of the system clock, PCLK, to generate the serial clock on the output (SPICLK).The desired frequency is obtained according to the following equation:
/
NOTE: Suggest DIVIDER should be at least 1 in master mode.
0
16
read-write
SPI_CTL
SPI_CTL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity
11
1
read-write
0
SPI_SCLKn idle low
#0
1
SPI_SCLKn idle high
#1
DWIDTH
Transmit Bit Length
This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.
3
5
read-write
GO_BUSY
Go And Busy Status
NOTE: All registers should be set readily before writing 1 to the GO_BUSY bit. When a transfer is in progress, writing to any register of the SPI core has no effect.
0
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit starts the transfer. This bit remains 1 during the transfer and is automatically cleared after the transfer is finished
#1
LSB
Send LSB First
10
1
read-write
0
The MSB is transmitted/received first (which bit in SPI_TXn/SPI_RXn is MSB is dependent on DWIDTH)
#0
1
The LSB (SPI_TXn[0]) is sent first to SPI_MOSIn, and the first bit received from SPI_MISOn will be put in the LSB (SPI_RXn[0])
#1
REORDER
BYTE ENDIAN
20
1
read-write
0
Disable the BYTE ENDIAN
#0
1
Enable the BYTE ENDIAN. Only the 16, 24, and 32 bits which are defined in DWIDTH are supported
#1
RX_NEG
Receive On Negative Edge
1
1
read-write
0
The input on SPI_MISOn is latched on the rising edge of SPI_SCLKn
#0
1
The input on SPI_MISOn is latched on the falling edge of SPI_SCLKn
#1
SUSPITV
Suspend Interval (Master Mode Only)
(SUSPITV+2)* SPI_SCLKn clock cycles
Note: SUSPITV cannot be 0 for SPI0.
12
4
read-write
TX_NEG
Transmit On Negative Edge
2
1
read-write
0
The output on SPI_MOSIn is changed on the rising edge of SPI_SCLKn
#0
1
The output on SPI_MOSIn is changed on the falling edge of SPI_SCLKn
#1
TX_NUM
Transmit/Receive Numbers
This field specifies how many transmit/receive numbers should be executed in one transfer.
8
2
read-write
0
Only one transmit/receive will be executed in one transfer
#00
1
Two successive transmit/receive will be executed in one transfer.
Reserved
#01
UNIT_INTEN
Unit Transfer Interrupt Enable
17
1
read-write
0
Disable SPI Unit Transfer Interrupt
#0
1
Enable SPI Unit Transfer Interrupt to CPU
#1
UNIT_INTSTS
Unit Transfer Interrupt Status
Note: This bit is read only, but can be cleared by writing 1 to this bit.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
-1
read-only
n
0x0
0x0
RX
Data Receive Register
Note: The Data Receive Registers are read only registers. A Write to these registers will actually modify the Data Transmit Registers because those registers share the same flip-flops.
0
32
read-only
SPI_RX1
0x14
-1
read-write
n
0x0
0x0
SPI_SSCTL
SPI_SSCTL
Slave Select Register
0x8
-1
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select
3
1
read-write
0
Slave select signal (SPI_SSBx0/SPI_SSBx1) is asserted and de-asserted by setting and clearing related bit SS
#0
1
Slave select signal (SPI_SSBx0/SPI_SSBx1) is generated automatically. It means that slave select signal, which is set in bits SS, is asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and is de-asserted after the transfer is finished
#1
SS
Slave Select Pin Control (Master Mode Only)
If AUTOSS bit is 0,
SPIn_SSBx0 and SPIn_SSBx1 output are determined by SS[0] and SS[1] respectively.
0
2
read-write
0
Any bit location of this field forces the pin to inactive state.
Any bit location of this field will select appropriate SPIn_SSBx0/SPIn_SSBx1 pin to be driven to inactive state
0
1
Any bit location of this field forces the proper SPIn_SSBx0/SPIn_SSBx1 pin to an active state
Any bit location of this field will select appropriate SPIn_SSBx0/SPIn_SSBx1 pin to be automatically driven to active state for the duration of the transmit/receive, and to be driven to inactive state for the rest of the time. The active state of SPIn_SSBx0/SPIn_SSBx1 is specified in SS_LVL bit (SPI_SSCTL[2])
1
SS_LVL
Slave Select Active Level
It defines the active level of device/slave select signal.
2
1
read-write
0
The SPI_SSBx0/SPI_SSBx1 slave select signal is active Low
#0
1
The SPI_SSBx0/SPI_SSBx1 slave select signal is active High
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
-1
write-only
n
0x0
0x0
TX
Data Transmit Register
Note: The SPI_RXn and SPI_TXn registers share the same flip-flops, which mean that what is received in one transfer will be transmitted in the next transfer if there is not any write to the SPI_TXn register between the two transfers.
0
32
write-only
SPI_TX1
0x24
-1
read-write
n
0x0
0x0
SYS
SYS Register Map
SYS
0x0
0x0
0x10
registers
n
0x100
0x4
registers
n
0x18
0x8
registers
n
0x30
0x8
registers
n
BODCTL
SYS_BODCTL
Brown-Out Detector Control Register
0x18
-1
read-write
n
0x0
0x0
BOD_EN
Brown-Out Detector Enable (Initiated and Protected Bit)
0
1
read-write
0
Brown-Out Detector function is disabled
#0
1
Brown-Out Detector function is enabled,
#1
BOD_OUT
The Status For Brown-Out Detector Output It's a read only bit.
6
1
read-write
0
The detected voltage is lower than BOD_VL setting. If the BOD_EN is 0 , this bit always responses 0
#0
1
The detected voltage is higher than BOD_VL setting
#1
BOD_VL
Brown-Out Detector Threshold Voltage Selection (Initiate and Protected Bit)
The default value is set by flash controller user configuration register CONFIG[21].
1
1
read-write
0
Threshold voltage is 2.7V
#0
1
Threshold voltage is 3.0V
#1
LVR_EN
Low Voltage Reset (LVR) Enable (Protected Bit)
The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default.
7
1
read-write
0
Disable LVR function
#0
1
Enable LVR function - After enable the bit, the LVR function will active with 100uS delay for LVR output stable
#1
GPA_MFP
SYS_GPA_MFP
GPIO PA Multiple Alternate Functions and Input Type Control Register
0x30
-1
read-write
n
0x0
0x0
PA0MFP
0
1
read-write
0
The GPIOA-0 is selected to the pin PA.0
#0
1
SPI0 2nd chip select output
#1
PA10MFP
10
1
read-write
0
The GPIOA-10 is selected to the pin PA.10
#0
1
ADC input channel 2
#1
PA11MFP
11
1
read-write
0
The GPIOA-11 is selected to the pin PA.11
#0
1
ADC input channel 3
#1
PA12MFP
12
1
read-write
0
The GPIOA-12 is selected to the pin PA.12
#0
1
ADC input channel 4
#1
PA13MFP
13
1
read-write
0
The GPIOA-13 is selected to the pin PA.13
#0
1
ADC input channel 5
#1
PA14MFP
14
1
read-write
0
The GPIOA-14 is selected to the pin PA.14
#0
1
ADC input channel 6
#1
PA15MFP
15
1
read-write
0
The GPIOA-15 is selected to the pin PA.15
#0
1
ADC input channel 7
#1
PA1MFP
1
1
read-write
0
The GPIOA-1 is selected to the pin PA.1
#0
1
SPI0 1st chip select output
#1
PA2MFP
2
1
read-write
0
The GPIOA-2 is selected to the pin PA.2
#0
1
SPI0 clock output
#1
PA3MFP
3
1
read-write
0
The GPIOA-3 is selected to the pin PA.3
#0
1
SPI0 data input
#1
PA4MFP
4
1
read-write
0
The GPIOA-4 is selected to the pin PA.4
#0
1
SPI0 data output
#1
PA5MFP
5
1
read-write
0
The GPIOA-5 is selected to the pin PA.5
#0
1
Timer0 counter external input
#1
PA6MFP
6
1
read-write
0
The GPIOA-6 is selected to the pin PA.6
#0
1
External interrupt input
#1
PA7MFP
7
1
read-write
0
The GPIOA-7 is selected to the pin PA.7
#0
1
ADC input external trigger input
#1
PA8MFP
8
1
read-write
0
The GPIOA-8 is selected to the pin PA.8
#0
1
ADC input channel 0
#1
PA9MFP
9
1
read-write
0
The GPIOA-9 is selected to the pin PA.9
#0
1
ADC input channel 1
#1
PAnTYPEn
16
16
read-write
0
PA.n I/O cell input Schmitt Trigger function is disabled
0
1
PA.n I/O cell input Schmitt Trigger function is enabled
1
GPB_MFP
SYS_GPB_MFP
GPIO PB Multiple Alternate Functions and Input Type Control Register
0x34
-1
read-write
n
0x0
0x0
PB0MFP
0
1
read-write
0
The GPIOB-0 is selected to the pin PB.0
#0
1
SPI1 2nd chip select output
#1
PB10MFP
10
1
read-write
0
The GPIOB-10 is selected to the pin PB.10
#0
1
PWM output pin 2
#1
PB11MFP
11
1
read-write
0
The GPIOB-11 is selected to the pin PB.11
#0
1
PWM output pin 3
#1
PB12MFP
12
1
read-write
0
The GPIOB-12 is selected to the pin PB.12
#0
1
PWM timer capture input
#1
PB13MFP
13
1
read-write
0
The GPIOB-13 is selected to the pin PB.13
#0
1
IR carrier output
#1
PB14MFP
14
1
read-write
0
The GPIOB-14 is selected to the pin PB.14
#0
1
Timer1 counter external input
#1
PB15MFP
15
1
read-write
0
The GPIOB-15 is selected to the pin PB.15
#0
1
Timer2 counter external input
#1
PB1MFP
1
1
read-write
0
The GPIOB-1 is selected to the pin PB.1
#0
1
SPI1 1st chip select output or slave select input
#1
PB2MFP
2
1
read-write
0
The GPIOB-2 is selected to the pin PB.2
#0
1
SPI1 clock output/input
#1
PB3MFP
3
1
read-write
0
The GPIOB-3 is selected to the pin PB.3
#0
1
SPI1 data input/output
#1
PB4MFP
4
1
read-write
0
The GPIOB-4 is selected to the pin PB.4
#0
1
SPI1 data output/input
#1
PB8MFP
8
1
read-write
0
The GPIOB-8 is selected to the pin PB.8
#0
1
PWM output pin 0
#1
PB9MFP
9
1
read-write
0
The GPIOB-9 is selected to the pin PB.9
#0
1
PWM output pin 1
#1
PBnTYPEn
16
16
read-write
0
PB.n I/O cell input Schmitt Trigger function is disabled
0
1
PB.n I/O cell input Schmitt Trigger function is enabled
1
IPRST0
SYS_IPRST0
IP Reset Control Resister0
0x8
-1
read-write
n
0x0
0x0
CHIPRST
CHIP One Shot Reset
Set this bit will reset the whole chip, this bit will automatically return to 0 after 2 clock cycles.
The CHIPRST is almost the same as the POR reset, all the chip modules are reset but the chip settings from flash are not reloaded.
0
1
read-write
0
Normal
#0
1
Reset CHIP
#1
CPURST
CPU Kernel One Shot Reset
Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC), this bit will automatically return to 0 after the 2 clock cycles
1
1
read-write
0
Normal
#0
1
Reset CPU
#1
CPUWS
CPU Wait-State Control For Flash Memory Access
Note: that CPUWS cannot be set as 1 when CPU runs the program to do Flash ISP operation.
2
1
read-write
0
1 HCLK clock wait-state
#0
1
zero wait-state
#1
RAMWS
Wait State Control For CPU Access RAM
3
1
read-write
0
1 HCLK clock wait-state
#0
1
zero wait-state
#1
IPRST1
SYS_IPRST1
IP Reset Control Resister1
0xC
-1
read-write
n
0x0
0x0
ADCRST
ADC Controller Reset
28
1
read-write
0
Normal Operation
#0
1
IP reset
#1
APURST
APU Controller Reset
5
1
read-write
0
Normal operation
#0
1
IP reset
#1
GPIORST
GPIO Controller Reset
1
1
read-write
0
Normal operation
#0
1
IP reset
#1
PWMRST
PWM Controller Reset
20
1
read-write
0
Normal Operation
#0
1
IP reset
#1
SPI0RST
SPI0 Controller Reset
12
1
read-write
0
Normal Operation
#0
1
IP reset
#1
SPI1RST
SPI1 Controller Reset
13
1
read-write
0
Normal Operation
#0
1
IP reset
#1
TMR0RST
Timer0 Controller Reset
2
1
read-write
0
Normal Operation
#0
1
IP reset
#1
TMR1RST
Timer1 Controller Reset
3
1
read-write
0
Normal Operation
#0
1
IP reset
#1
TMR2RST
Timer2 Controller Reset
4
1
read-write
0
Normal operation
#0
1
IP reset
#1
TMRFRST
TimerF Controller Reset
6
1
read-write
0
Normal operation
#0
1
IP reset
#1
USBDRST
USB Device Controller Reset
27
1
read-write
0
Normal operation
#0
1
IP reset
#1
PDID
SYS_PDID
Product Identifier Register
0x0
-1
read-only
n
0x0
0x0
PDID
Product Identifier
Chip identifier (part number) for N572F064 series.
0
32
read-only
PORCTL
SYS_PORCTL
Power-On-Reset Controller Register
0x1C
-1
read-write
n
0x0
0x0
POROFF
Power-On Reset Enable Bit (Write Protect)
When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
nRESET, Watchdog, LVR reset, ICE reset command and the software-chip reset function.
0
16
read-write
REGLCTL
SYS_REGLCTL
Register Lock Control Register
0x100
-1
read-write
n
0x0
0x0
REGLCTL
Protected Register Lock/Unlock Index (Read Only)
SPI0_RCLK - address 0x4003_0030
FMC_ISPCTL - address 0x5000_C000 (Flash ISP Control register)
WDT_CTL - address 0x4000_4000
FATCON - address 0x5000_C018
0
1
read-only
0
Protected registers are locked. Any write to the target register is ignored
#0
1
Protected registers are unlocked
#1
SYS_REGLCTL
Register Lock Control Code (Write Only)
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
0
8
write-only
RSTSTS
SYS_RSTSTS
System Reset Source Register
0x4
-1
read-write
n
0x0
0x0
LVRF
LVR Reset Flag
The LVR reset flag is set by the Reset Signal from the Low Voltage Reset Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
3
1
read-write
0
No reset from LVR
#0
1
LVR controller had issued the reset signal to reset the system
#1
MCURF
MCU Reset Flag
The MCURF flag is set by the reset signal from the MCU Cortex_M0 module to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
5
1
read-write
0
No reset from MCU
#0
1
The MCU Cortex_M0 had issued the reset signal to reset the system
#1
PINRF
nRESET Pin Reset Flag
The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
1
1
read-write
0
No reset from nRESET pin
#0
1
Pin nRESET had issued the reset signal to reset the system
#1
PMURSTF
Reset Source From PMU
The PMURSTF flag is set by the reset signal from the PMU module to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
6
1
read-write
0
No reset from PMU
#0
1
The PMU has issued the reset signal to reset the system
#1
PORF
POR Reset Flag
The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
0
1
read-write
0
No reset from POR
#0
1
Power-on Reset (POR) Controller had issued the reset signal to reset the system
#1
WDTRF
Reset Source From WDG
The WDTRF flag is set if pervious reset source originates from the Watch-Dog module.
Note: Write 1 to clear this bit to 0.
2
1
read-write
0
No reset from Watch-Dog
#0
1
The Watch-Dog module issued the reset signal to reset the system
#1
TMR
TMR Register Map
TMR
0x0
0x0
0x10
registers
n
0x20
0x18
registers
n
0x40
0x10
registers
n
IR_CTL
IR_CTL
IR Carrier Output Control Register
0x34
-1
read-write
n
0x0
0x0
TIMER0_CMP
TIMER0_CMP
Timer0 Compare Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
Timer Comparison Value
Note 1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.
Note 2: No matter CNTEN is 0 or 1, whenever software writes a new value into this register, TIMER will restart counting by using this new value and abort previous count.
0
16
read-write
TIMER0_CNT
TIMER0_CNT
Timer0 Data Register
0xC
-1
read-only
n
0x0
0x0
CNT
Timer Data Register
User can read this register for the current up-counter value while TIMERx_CTL.CNTEN is set to 1,
0
16
read-only
TIMER0_CTL
TIMER0_CTL
Timer0 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)
This bit indicates the counter status of Timer.
25
1
read-only
0
Timer is not active
#0
1
Timer is active
#1
CNTEN
Counter Enable Bit
30
1
read-write
0
Stop/Suspend counting
#0
1
Start counting
#1
INTEN
Interrupt Enable Bit
If timer interrupt is enabled, the timer asserts its interrupt signal when the associated count is equal to TIMERx_CMP.
29
1
read-write
0
Disable TIMER Interrupt
#0
1
Enable TIMER Interrupt
#1
OPMODE
Timer Operating Mode
27
2
read-write
0
The Timer is operating in the one-shot mode. The associated interrupt signal is generated once (if INTEN is 1) and CNTEN is automatically cleared by hardware
#00
1
The Timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if INTEN is 1)
#01
2
Reserved
#10
3
The Timer is operating in continuous counting mode. The associated interrupt signal is generated when TIMERx_CNT = TIMERx_CMP (if INTEN is 1) however, the 16-bit up-counter counts continuously without reset
#11
PSC
Timer Clock Prescaler
0
8
read-write
Reserved
Reserved.
31
1
read-write
RSTCNT
Counter Reset Bit
Set this bit will reset the Timer counter, pre-scale and also force CNTEN to 0.
26
1
read-write
0
No effect
#0
1
Reset Timer's pre-scale counter, internal 16-bit up-counter and CNTEN bit
#1
TIMER0_INTSTS
TIMER0_INTSTS
Timer0 Interrupt Status Register
0x8
-1
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag (Read Only)
This bit indicates the interrupt status of Timer.
TIF bit is set by hardware when the 16-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1 to itself
0
1
read-only
0
No effect
#0
1
CNT (TIMERx_CNT[15:0]) value matches the CMPDAT (TIMERx_CMP[15:0]) value
#1
TIMER1_CMP
0x24
-1
read-write
n
0x0
0x0
TIMER1_CNT
0x2C
-1
read-write
n
0x0
0x0
TIMER1_CTL
0x20
-1
read-write
n
0x0
0x0
TIMER1_INTSTS
0x28
-1
read-write
n
0x0
0x0
TIMER2_CMP
0x44
-1
read-write
n
0x0
0x0
TIMER2_CNT
0x4C
-1
read-write
n
0x0
0x0
TIMER2_CTL
0x40
-1
read-write
n
0x0
0x0
TIMER2_INTSTS
0x48
-1
read-write
n
0x0
0x0
TIMERF_INTSTS
TIMERF_INTSTS
TimerF Interrupt Status Register
0x30
-1
read-write
n
0x0
0x0
TFIE
TimerF Interrupt Enable
1
1
read-write
0
Disable TimerF Interrupt
#0
1
Enable TimerF Interrupt
#1
TFIF
TimerF Interrupt Flag
This bit indicates the interrupt status of TimerF.
TFIF bit is set by hardware when TimerF time out. It is cleared by writing 1 to this bit.
0
1
read-write
0
It indicates that TimerF does not time out yet
#0
1
It indicates that TimerF time out. The interrupt flag is set if TimerF interrupt was enabled
#1
USBD
USBD Register Map
USBD
0x0
0x0
0x1C
registers
n
0x20
0x60
registers
n
0x90
0x4
registers
n
0xA0
0x4
registers
n
ATTR
USBD_ATTR
USB Device Bus Status and Attribution Register
0x10
-1
read-write
n
0x0
0x0
BYTEM
CPU Access USB SRAM Size Mode Selection
10
1
read-write
0
Word mode: The size of the transfer from CPU to USB SRAM can be Word only
#0
1
Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only
#1
DPPUEN
Pull-Up Resistor On USB_DP Enable Bit
8
1
read-write
0
Pull-up resistor in USB_D+ bus Disabled
#0
1
Pull-up resistor in USB_D+ bus Active
#1
PDB
Power Down USB-IP Related Power and Control
9
1
read-write
0
Enable power down
#0
1
Disable power down
#1
PHYEN
PHY Transceiver Function Enable Bit
4
1
read-write
0
PHY transceiver function Disabled. The PHY means USB transceiver output
#0
1
PHY transceiver function Enabled
#1
RESUME
Resume Status
Note: This bit is read only.
2
1
read-write
0
No bus resume
#0
1
Resume from suspend
#1
RWAKEUP
Remote Wake-Up
5
1
read-write
0
Release the USB bus from K state
#0
1
Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up
#1
SUSPEND
Suspend Status
Note: This bit is read only.
1
1
read-write
0
Bus no suspend
#0
1
Bus idle more than 3ms, either cable is plugged off or host is sleeping
#1
TOUT
Time-Out Status
Note: This bit is read only.
3
1
read-write
0
No time-out
#0
1
No Bus response more than 18 bits time
#1
USBEN
USB Controller Enable Bit
7
1
read-write
0
USB Controller Disabled
#0
1
USB Controller Enabled
#1
USBRST
USB Reset Status
Note: This bit is read only.
0
1
read-write
0
Bus no reset
#0
1
Bus reset when SE0 (single-ended 0) more than 2.5us
#1
BIST
USBD_BIST
USB Buffer Self-test Register
0xA0
-1
read-write
n
0x0
0x0
BISTEN
BIST mode enable
0
1
read-write
0
BIST is disabled or completed (automatically cleared by BIST controller)
#0
1
BIST is enabled begin to perform BIST on selected memory group
#1
BISTFAIL
BIST Fail
The BISTFAIL indicates if the BIST test fails or succeeds. If the BISTFAIL is low at the end, the embedded SRAM pass the BIST test, otherwise, it is faulty. The BISTFAIL will be high once the BIST detects the error and remains high during the BIST operation.
The BISTFAIL is a write clear field. Write 1 to this field clears the content and write 0 has no effect.
Note: This bit is read only.
2
1
read-write
FINISH
BIST Operation Finish
It indicates the end of the BIST operation. When BIST controller finishes all operations, this bit will be set high.
This bit is a write clear field. Write 1 to this field clears the content and write 0 has no effect.
Note: This bit is read only.
1
1
read-write
BUFSEG0
USBD_BUFSEG0
Endpoint 0 Buffer Segmentation Register
0x20
-1
read-write
n
0x0
0x0
BUFSEG
Endpoint Buffer Segmentation
It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
USBD_SRAM address + { BUFSEG[8:3], 3'b000}
Refer to the section 5.5.4.7 for the endpoint SRAM structure and its description.
3
6
read-write
BUFSEG1
0x30
-1
read-write
n
0x0
0x0
BUFSEG2
0x40
-1
read-write
n
0x0
0x0
BUFSEG3
0x50
-1
read-write
n
0x0
0x0
BUFSEG4
0x60
-1
read-write
n
0x0
0x0
BUFSEG5
0x70
-1
read-write
n
0x0
0x0
CFG0
USBD_CFG0
Endpoint 0 Configuration Register
0x28
-1
read-write
n
0x0
0x0
CSTALL
Clear STALL Response
9
1
read-write
0
Disable the device to clear the STALL handshake in setup stage
#0
1
Clear the device to response STALL handshake in setup stage
#1
DSQSYNC
Data Sequence Synchronization
Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit.
7
1
read-write
0
DATA0 PID
#0
1
DATA1 PID
#1
EPNUM
Endpoint Number
These bits are used to define the endpoint number of the current endpoint
0
4
read-write
ISOCH
Isochronous Endpoint
This bit is used to set the endpoint as Isochronous endpoint, no handshake.
4
1
read-write
0
No Isochronous endpoint
#0
1
Isochronous endpoint
#1
STATE
Endpoint STATE
5
2
read-write
0
Endpoint is Disabled
#00
1
Out endpoint
#01
2
IN endpoint
#10
3
Undefined
#11
CFG1
0x38
-1
read-write
n
0x0
0x0
CFG2
0x48
-1
read-write
n
0x0
0x0
CFG3
0x58
-1
read-write
n
0x0
0x0
CFG4
0x68
-1
read-write
n
0x0
0x0
CFG5
0x78
-1
read-write
n
0x0
0x0
CFGP0
USBD_CFGP0
Endpoint 0 Set Stall and Clear In/Out Ready Control Register
0x2C
-1
read-write
n
0x0
0x0
CLRRDY
Clear Ready
When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.
For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
This bit is written only and is always 0 when it is read back.
0
1
read-write
SSTALL
Set STALL
1
1
read-write
0
Disable the device to response STALL
#0
1
Set the device to respond STALL automatically
#1
CFGP1
0x3C
-1
read-write
n
0x0
0x0
CFGP2
0x4C
-1
read-write
n
0x0
0x0
CFGP3
0x5C
-1
read-write
n
0x0
0x0
CFGP4
0x6C
-1
read-write
n
0x0
0x0
CFGP5
0x7C
-1
read-write
n
0x0
0x0
EPSTS
USBD_EPSTS
USB Device Endpoint Status Register
0xC
-1
read-only
n
0x0
0x0
EPSTS0
Endpoint 0 Status
These bits are used to indicate the current status of this endpoint
8
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS1
Endpoint 1 Status
These bits are used to indicate the current status of this endpoint
11
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS2
Endpoint 2 Status
These bits are used to indicate the current status of this endpoint
14
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS3
Endpoint 3 Status
These bits are used to indicate the current status of this endpoint
17
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS4
Endpoint 4 Status
These bits are used to indicate the current status of this endpoint
20
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS5
Endpoint 5 Status
These bits are used to indicate the current status of this endpoint
23
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPT
Endpoint number
0
4
read-only
OV
Overrun
It indicates that the received data is over the maximum payload number or not.
7
1
read-only
0
No overrun
#0
1
Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes
#1
STS
4
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out 0 ACK
#010
3
Setup ACK
#011
6
Out 1 ACK
#110
7
Isochronous translation end
#111
FADDR
USBD_FADDR
USB Device Function Address Register
0x8
-1
read-write
n
0x0
0x0
FADDR
USB Device Function Address
0
7
read-write
INTEN
USBD_INTEN
USB Device Interrupt Enable Register
0x0
-1
read-write
n
0x0
0x0
BUSIEN
Bus Event Interrupt Enable Bit
0
1
read-write
0
BUS event interrupt Disabled
#0
1
BUS event interrupt Enabled
#1
INNAKEN
Active NAK Function And Its Status In IN Token
15
1
read-write
0
When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS register, so that the USB interrupt event will not be asserted
#0
1
IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token
#1
NEVWKIEN
USB No-Event-Wake-Up Interrupt Enable Bit
3
1
read-write
0
No-event-wake-up Interrupt Disabled
#0
1
No-event-wake-up Interrupt Enabled
#1
USBIEN
USB Event Interrupt Enable Bit
1
1
read-write
0
USB event interrupt Disabled
#0
1
USB event interrupt Enabled
#1
VBDETIEN
VBUS Detection Interrupt Enable Bit
2
1
read-write
0
VBUS detection Interrupt Disabled
#0
1
VBUS detection Interrupt Enabled
#1
WKEN
Wake-Up Function Enable Bit
8
1
read-write
0
USB wake-up function Disabled
#0
1
USB wake-up function Enabled
#1
INTSTS
USBD_INTSTS
USB Device Interrupt Event Status Register
0x4
-1
read-write
n
0x0
0x0
BUSIF
BUS Interrupt Status
The BUS event means that there is one of the suspense or the resume function in the bus.
0
1
read-write
0
No BUS event occurred
#0
1
Bus event occurred check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0]
#1
EPEVT0
Endpoint 0's USB Event Status
16
1
read-write
0
No event occurred in endpoint 0
#0
1
USB event occurred on Endpoint 0, check USBD_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1]
#1
EPEVT1
Endpoint 1's USB Event Status
17
1
read-write
0
No event occurred in endpoint 1
#0
1
USB event occurred on Endpoint 1, check USBD_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1]
#1
EPEVT2
Endpoint 2's USB Event Status
18
1
read-write
0
No event occurred in endpoint 2
#0
1
USB event occurred on Endpoint 2, check USBD_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1]
#1
EPEVT3
Endpoint 3's USB Event Status
USBD_INTSTS[1].
19
1
read-write
0
No event occurred in endpoint 3
#0
1
USB event occurred on Endpoint 3, check USBD_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or
#1
EPEVT4
Endpoint 4's USB Event Status
20
1
read-write
0
No event occurred in endpoint 4
#0
1
USB event occurred on Endpoint 4, check USBD_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1]
#1
EPEVT5
Endpoint 5's USB Event Status
21
1
read-write
0
No event occurred in endpoint 5
#0
1
USB event occurred on Endpoint 5, check USBD_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1]
#1
NEVWKIF
No-Event-Wake-Up Interrupt Status
3
1
read-write
0
NEVWK event does not occur
#0
1
No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3]
#1
SETUP
Setup Event Status
31
1
read-write
0
No Setup event
#0
1
Setup event occurred, cleared by write 1 to USBD_INTSTS[31]
#1
USBIF
USB Event Interrupt Status
The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
1
1
read-write
0
No USB event occurred
#0
1
USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~7 and SETUP (USBD_INTSTS[31])
#1
VBDETIF
VBUS Detection Interrupt Status
2
1
read-write
0
There is not attached/detached event in the USB
#0
1
There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2]
#1
MXPLD0
USBD_MXPLD0
Endpoint 0 Maximal Payload Register
0x24
-1
read-write
n
0x0
0x0
MXPLD
Maximal Payload
Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
(1) When the register is written by CPU,
For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
(2) When the register is read by CPU,
For IN token, the value of MXPLD is indicated by the data length be transmitted to host
For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
0
9
read-write
MXPLD1
0x34
-1
read-write
n
0x0
0x0
MXPLD2
0x44
-1
read-write
n
0x0
0x0
MXPLD3
0x54
-1
read-write
n
0x0
0x0
MXPLD4
0x64
-1
read-write
n
0x0
0x0
MXPLD5
0x74
-1
read-write
n
0x0
0x0
SE0
USBD_SE0
USB Device Drive SE0 Control Register
0x90
-1
read-write
n
0x0
0x0
SE0
Drive Single Ended Zero In USB Bus
The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
0
1
read-write
0
Normal operation
#0
1
Force USB PHY transceiver to drive SE0
#1
STBUFSEG
USBD_STBUFSEG
SETUP Token Buffer Segmentation Register
0x18
-1
read-write
n
0x0
0x0
STBUFSEG
SETUP Token Buffer Segmentation
It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
USBD_SRAM address + {STBUFSEG[8:3], 3'b000}
Note: It is used for SETUP token only.
3
6
read-write
VBUSDET
USBD_VBUSDET
USB Device VBUS Detection Register
0x14
-1
read-only
n
0x0
0x0
VBUSDET
Device VBUS Detection
Note: This bit is read only.
0
1
read-only
0
Controller is not attached to the USB host
#0
1
Controller is attached to the USB host
#1
WDT
WDT Register Map
WDT
0x0
0x0
0x4
registers
n
CTL
WDT_CTL
Watchdog Timer Control Register
0x0
-1
read-write
n
0x0
0x0
IF
Watchdog Timer Interrupt Flag
If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed.
Note: This bit is cleared by writing 1 to this bit.
3
1
read-write
0
Watchdog timer interrupt has not occurred
#0
1
Watchdog timer interrupt has occurred
#1
INTEN
Watchdog Time-Out Interrupt Enable
6
1
read-write
0
Disable the WDT time-out interrupt
#0
1
Enable the WDT time-out interrupt
#1
RSTCNT
Clear Watchdog Timer
Set this bit will clear the Watchdog timer.
Note: This bit will auto clear after few clock cycles
0
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Reset the contents of the Watchdog timer
#1
RSTEN
Watchdog Timer Reset Enable
Setting this bit will enable the Watchdog timer reset function.
Note: This function cannot work with XTL32-based clock source.
1
1
read-write
0
Disable Watchdog timer reset function
#0
1
Enable Watchdog timer reset function
#1
RSTF
Watchdog Timer Reset Flag
When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is disabled, then the Watchdog timer has no effect on this bit.
Note: This bit is cleared by writing 1 to this bit.
2
1
read-write
0
Watchdog timer reset has not occurred
#0
1
Watchdog timer reset has occurred
#1
TOUTSEL
Watchdog Timer Interval Select
These three bits select the timeout interval for the Watchdog timer, a watchdog reset will occur 1024 clock cycles later if Watchdog timer is not reset.
The WDT interrupt timeout is given by:
Where WDT_CLK is the period of the Watchdog Timer clock source.
8
3
read-write
0
24 * WDT_CLK
#000
1
26 * WDT_CLK
#001
2
28 * WDT_CLK
#010
3
210 * WDT_CLK
#011
4
212 * WDT_CLK
#100
5
214 * WDT_CLK
#101
6
216 * WDT_CLK
#110
7
218 * WDT_CLK
#111
WDTEN
Watchdog Timer Enable
7
1
read-write
0
Disable the WDT(Watchdog timer) (This action will reset the internal counter)
#0
1
Enable the WDT(Watchdog timer)
#1
WKEN
WDT Time-Out Wake-Up Function Control
If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
4
1
read-write
0
Enable the Wakeup function that WDT timeout can wake up CPU from power-down mode
#0
1
Disable WDT Wakeup CPU function
#1
WKF
WDT Time-Out Wake-Up Flag
If WDT causes CPU wake up from sleep or power-down mode, this bit will be set to high.
Note: This bit is cleared by writing 1 to it.
5
1
read-write
0
WDT does not cause CPU wake-up
#0
1
CPU wakes up from sleep or power-down mode by WDT time-out interrupt
#1