nuvoTon N575F145_v1 2024.05.03 N575F145_v1 SVD file 8 32 ACMP ACMP Register Map ACMP 0x0 0x0 0x10 registers n CMPCR0 CMPCR0 Analog Comparator 0 Control Register 0x0 -1 read-write n 0x0 0x0 CMPCN Comparator0 Negative Input Select 4 1 read-write 0 VBG, Bandgap reference voltage = 1.2V #0 1 VMID reference voltage = VCCA/2 #1 CMPEN Comparator Enable 0 1 read-write 0 Disable #0 1 Enable #1 CMPIE CMP0 Interrupt Enable 1 1 read-write 0 Disable CMP0 interrupt function #0 1 Enable CMP0 interrupt function #1 CMPCR1 CMPCR1 Analog Comparator 1 Control Register 0x4 -1 read-write n 0x0 0x0 CMPCN Comparator1 Negative Input Select 4 1 read-write 0 GPIOB[7] #0 1 VBG, Bandgap reference voltage = 1.2V #1 CMPEN Comparator Enable 0 1 read-write 0 Disable #0 1 Enable #1 CMPIE CMP1 Interrupt Enable 1 1 read-write 0 Disable CMP1interrupt function #0 1 Enable CMP1 interrupt function #1 CMPSEL CMPSEL Comparator Select Register 0xC -1 read-write n 0x0 0x0 CMPSEL Comparator0 GPIO Selection GPIOB[CMPSEL] is the active analog GPIO input selected to Comparator 0 positive input. 0 3 read-write CMPSR CMPSR Comparator Status Register 0x8 -1 read-write n 0x0 0x0 CMPF0 Compare 0 Flag This bit is set by hardware whenever the comparator output changes state. This bit will cause a hardware interrupt if enabled. This bit is cleared by writing 1 to itself. 0 1 read-write CMPF1 Compare 1 Flag This bit is set by hardware whenever the comparator output changes state. This bit will cause a hardware interrupt if enabled. This bit is cleared by writing 1 to itself. 1 1 read-write CO0 Comparator0 Output Synchronized to the APB clock to allow reading by software. Cleared when the comparator is disabled (CMP0EN = 0). 2 1 read-write CO1 Comparator1 Output Synchronized to the APB clock to allow reading by software. Cleared when the comparator is disabled (CMP1EN = 0). 3 1 read-write ADC ADC Register Map ADC 0x0 0x0 0x20 registers n ADCMPR0 ADCMPR0 ADC Comparator 0 Control Register 0x18 -1 read-write n 0x0 0x0 CMPCOND Compare Condition Note: When the internal counter reaches the value (CMPMATCNT +1), the CMPF bit will be set. 2 1 read-write 0 Set the compare condition that result is less than CMPD #0 1 Set the compare condition that result is greater or equal to CMPD #1 CMPD Comparison Data 16 bit value to compare to FIFO output word. 16 16 read-write CMPEN Compare Enable Set this bit to 1 to enable compare CMPD with FIFO data output. 0 1 read-write 0 Disable compare #0 1 Enable compare #1 CMPF Compare Flag When the conversion result meets condition in ADCMPR0 this bit is set to 1. It is cleared by writing 1 to self. 7 1 read-write CMPIE Compare Interrupt Enable If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, if CMPIE is set to 1, a compare interrupt request is generated. 1 1 read-write 0 Disable compare function interrupt #0 1 Enable compare function interrupt #1 CMPMATCNT Compare Match Count When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set. 8 4 read-write ADCMPR1 ADCMPR1 ADC Comparator 1 Control Register 0x1C -1 read-write n 0x0 0x0 CMPCOND Compare Condition Note: When the internal counter reaches the value (CMPMATCNT +1), the CMPF bit will be set. 2 1 read-write 0 Set the compare condition that result is less than CMPD #0 1 Set the compare condition that result is greater or equal to CMPD #1 CMPD Comparison Data 16 bit value to compare to FIFO output word. 16 16 read-write CMPEN Compare Enable Set this bit to 1 to enable compare CMPD with FIFO data output. 0 1 read-write 0 Disable compare #0 1 Enable compare #1 CMPF Compare Flag When the conversion result meets condition in ADCMPR0 this bit is set to 1. It is cleared by writing 1 to self. 7 1 read-write CMPIE Compare Interrupt Enable If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, if CMPIE is set to 1, a compare interrupt request is generated. 1 1 read-write 0 Disable compare function interrupt #0 1 Enable compare function interrupt #1 CMPMATCNT Compare Match Count When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set. 8 4 read-write ADCOUT ADCOUT ADC FIFO Data Out. 0x0 -1 read-only n 0x0 0x0 ADCOUT ADC Audio Data FIFO Read A read of this register will read data from the audio FIFO and increment the read pointer. A read past empty will repeat the last data. Can be used with FIFO_IE_LEV interrupt to determine if valid data is present in FIFO. 0 16 read-only ADCPDMA ADCPDMA ADC PDMA Control Register 0x14 -1 read-write n 0x0 0x0 RxDmaEn Enable ADC PDMA Receive Channel Enable ADC PDMA. If set, then ADC will request PDMA service when data is available. 0 1 read-write CLK_DIV CLK_DIV ADC Clock Divider Register 0x8 -1 read-write n 0x0 0x0 CLK_DIV ADC Clock Divider This register determines the clock division ration between the incoming ADC_CLK (= HCLK by default) and the Delta-Sigma sampling clock of the ADC. This together with the over-sampling ratio (OSR) determines the audio sample rate of the converter. CLK_DIV should be set to give a SD_CLK frequency in the range of 1.024-6.144MHz. CLK_DIV must be greater than 2. SD_CLK frequency = HCLK / CLK_DIV 0 8 read-write DEC DEC ADC Decimation Control Register 0xC -1 read-write n 0x0 0x0 GAIN CIC Filter Additional Gain This should normally remain default 0. Can be set to non-zero values to provide additional digital gain from the decimation filter. An additional gain is applied to signal of GAIN/2. 16 4 read-write OSR Decimation Over-Sampling Ratio This term determines the over-sampling ratio of the decimation filter. Valid values are: 0: OSR = 64 1: OSR = 128 2: OSR = 192 3: OSR = 384 0 4 read-write EN EN ADC Enable Register 0x4 -1 read-write n 0x0 0x0 EN ADC Enable 0 1 read-write 0 Conversion stopped and ADC is reset including FIFO pointers #0 1 ADC Conversion enabled #1 INT INT ADC Interrupt Control Register 0x10 -1 read-write n 0x0 0x0 FIFO_IE_LEV FIFO Interrupt Level Determines at what level the ADC FIFO will generate a servicing interrupt to the CPU. Interrupt will be generated when number of words present in ADC FIFO is > FIFO_IE_LEV. 0 3 read-write IE Interrupt Enable If set to '1' an interrupt is generated whenever FIFO level exceeds that set in FIFO_IE_LEV. 31 1 read-write ALC ALC Register Map ALC 0x0 0x0 0x10 registers n CTRL ALC_CTRL ALC Control Register 0x0 -1 read-write n 0x0 0x0 ALCATK ALC Attack Time (Value: 0~10) When ALCMODE = 0, Range: 500us to 512ms When ALCMODE = 1,Range: 125us to 128ms (Both ALC time doubles with every step) 4 4 read-write ALCDCY ALC Decay Time (Value: 0~10) When ALCMODE = 0, Range: 125us to 128ms When ALCMODE = 1, Range: 31us to 32ms (time doubles with every step) 8 4 read-write ALCHLD ALC Hold Time (Value: 0~10). Hold Time = (2^ALCHLD) ms 17 4 read-write ALCLVL ALC Target Level 13 4 read-write 0 -28.5 dB 0 1 -27 dB 1 10 -13.5 dB 10 11 -12 dB 11 12 -10.5 dB 12 13 -9 dB 13 14 -7.5 dB 14 15 -6 dB 15 2 -25.5 dB 2 3 -24 dB 3 4 -22.5 dB 4 5 -21 dB 5 6 -19.5 dB 6 7 -18 dB 7 8 -16.5 dB 8 9 -15 dB 9 ALCMAX ALC Maximum Gain 25 3 read-write 0 -6.75 dB 0 1 -0.75 dB 1 2 +5.25 dB 2 3 +11.25 dB 3 4 +17.25 dB 4 5 +23.25 dB 5 6 +29.25 dB 6 7 +35.25 dB 7 ALCMIN ALC Minimum Gain 22 3 read-write 0 -12 dB 0 1 -6 dB 1 2 0 dB 2 3 6 dB 3 4 12 dB 4 5 18 dB 5 6 24 dB 6 7 30 dB 7 ALCMODE ALC Mode 12 1 read-write 0 ALC normal operation mode #0 1 ALC limiter mode #1 ALCNGSEL ALC noise gate peak detector select 29 1 read-write 0 use peak-to-peak value for noise gate threshold determination (default) #0 1 use absolute peak value for noise gate threshold determination #1 ALCPKLIM ALC peak limiter enable 31 1 read-write 0 enable fast decrement when signal exceeds 87.5% of full scale (default) #0 1 disable fast decrement when signal exceeds 87.5% of full scale #1 ALCPKSEL ALC gain peak detector select 30 1 read-write 0 use absolute peak value for ALC training (default) #0 1 use peak-to-peak value for ALC training #1 ALCSEL ALC select 28 1 read-write 0 ALC disabled (default) #0 1 ALC enabled #1 ALCZC ALC Zero Crossing 21 1 read-write 0 zero crossing disabled #0 1 zero crossing enabled #1 NGEN Noise Gate Enable 3 1 read-write 0 Noise gate disabled #0 1 Noise gate enabled #1 NGTH Noise Gate Threshold Boost disabled: Threshold = (-81+6xNGTH) dB Boost enabled: Threshold = (-87+6xNGTH) dB 0 3 read-write INT ALC_INT ALC interrupt register 0x8 -1 read-write n 0x0 0x0 ALC_INT ALC interrupt This interrupt flag asserts whenever the interrupt is enabled and the PGA gain is updated, either through an ALC change with the ALC enabled or through a PGA gain write with the ALC disabled. Write a 1 to this register to clear. 0 1 read-write INTEN ALC_INTEN ALC interrupt enable register 0xC -1 read-write n 0x0 0x0 ALC_INTEN ALC Interrupt Enable 0 1 read-write 0 ALC_INT disabled #0 1 ALC_INT enabled #1 STATUS ALC_STATUS ALC status register 0x4 -1 read-only n 0x0 0x0 FAST_DEC Clipping Flag Asserted when signal level is detected to be above 87.5% of full scale 0 1 read-only NOISE Noise Flag Asserted when signal level is detected to be below NGTH 1 1 read-only P2P Peak-To-Peak Value 9 MSBs of measured peak-to-peak value 2 9 read-only PEAK Peak Value 9 MSBs of measured absolute peak value 11 8 read-only ANA ANA Register Map ANA 0x0 0x0 0x4 registers n 0x20 0x10 registers n 0x38 0xC registers n 0x50 0x4 registers n 0x60 0xC registers n 0x8 0x4 registers n 0x84 0x4 registers n 0x8C 0x10 registers n AMUX AMUX Analog Multiplexer Control Register 0x50 -1 read-write n 0x0 0x0 EN Enable The Analog Multiplexer 14 1 read-write 0 All channels disabled #0 1 Selection determined by register setting #1 MIC_SEL Select MICP/MICN To PGA Inputs 13 1 read-write MUXN_SEL Selects Connection Of GPIOB[7:0] To PGA_INN, Negative Input Of PGA If MUXN_SEL[n] = 1 then GPIOB[n] is connected to PGA_INN. 0 8 read-write MUXP_SEL Selects Connection Of GPIOB[7,5,3,1] To PGA_INP, Positive Input Of PGA 1000b: GPIOB[7] connected to PGA_INP 0100b: GPIOB[5] connected to PGA_INP 0010b: GPIOB[3] connected to PGA_INP 0001b: GPIOB[1] connected to PGA_INP 8 4 read-write TEMP_SEL Select PTAT Current I_PTAT, to PGA_INN, negative input to PGA, for temperature measurement. 12 1 read-write CAPS_CNT CAPS_CNT Capacitive Touch Sensing Count Register 0x90 -1 read-only n 0x0 0x0 CAPS_CNT Counter Read Back Value Of Capacitive Touch Sensing Block 0 24 read-only CAPS_CTRL CAPS_CTRL Capacitive Touch Sensing Control Register 0x8C -1 read-write n 0x0 0x0 CLK_DIV Reference Clock Divider Circuit can be used to generate a reference clock output of SDCLK/2/(CLK_DIV+1) instead of a Capacitive Touch Sensing reset signal. 8 8 read-write CYCLE_CNT Number of Relaxation Cycles Peripheral performs 2^(CYCLE_CNT) relaxation cycles before generating interrupt. 2 3 read-write EN Enable 31 1 read-write 0 Disable/Reset block #0 1 Enable Block #1 INT_EN Interrupt Enable 30 1 read-write 0 Disable/Reset CAPS_IRQ interrupt #0 1 Enable CAPS_IRQ interrupt #1 LOW_TIME Output Low Time Number of PCLK cycles to discharge external capacitor. 0 2 read-write 0 1cycle 0 1 2cycles 1 2 8cycles 2 3 16cycles 3 REF_CLK_MD Reference Clock Mode 5 1 read-write 0 Capacitive Touch Sensing Mode #0 1 Circuit is in Reference clock generation mode #1 RST_CNT Reset Count 0: Release/Activate CAP_CNT 1: Set high to reset CAP_CNT. 29 1 read-write FREQ_CNT FREQ_CNT Frequency Measurement Count Register 0x98 -1 read-only n 0x0 0x0 FREQ_CNT Frequency Measurement Count When FM_DONE = 1 and G0 = 1, this is number of PCLK periods counted for frequency measurement. The frequency will be PCLK = FREQ_CNT * Fref /(FM_CYCLE+1) Hz Maximum resolution of measurement is Fref /(FM_CYCLE+1)*2 Hz 0 16 read-only FREQ_CTRL FREQ_CTRL Frequency Measurement Control Register 0x94 -1 read-write n 0x0 0x0 FM_CYCLE Frequency Measurement Cycles Number of reference clock periods plus one to measure target clock (PCLK). For example if reference clock is OSC32K (T is 30.5175us), set FM_CYCLE to 7, then measurement period would be 30.5175*(7+1), 244.1us. 16 8 read-write FM_DONE Measurement Done 2 1 read-write 0 Measurement Ongoing #0 1 Measurement Complete #1 FM_SEL Reference Clock Source 00b: OSC16K, 01b: OSC32K (default), 1xb: I2S_WS - can be GPIOA[4,8,12] according to GPA_ALT register, configure I2S in SLAVE mode to enable. 0 2 read-write GO GO 31 1 read-write 0 Disable/Reset block #0 1 Start Frequency Measurement #1 ISRC ISRC Current Source Control Register 0x8 -1 read-write n 0x0 0x0 EN Enable Current Source to GPIOB[x] Individually enable current source to GPIOB pins. Each GPIOB pin has a separate current source. 0 8 read-write 0 Disable 0 1 Enable current source to pin GPIOB[x] 1 VAL Current Source Value Select master current for source generation 8 2 read-write 0 0.5 uA 0 1 1 uA 1 2 2.5 uA 2 3 5 uA 3 LDOPD LDOPD LDO Power Down Register 0x24 -1 read-write n 0x0 0x0 DISCH Discharge 1 1 read-write 0 No load on VD33 #0 1 Switch discharge resistor to VD33 #1 PD Power Down LDO When powered down no current delivered to VD33. 0 1 read-write 0 Enable LDO #0 1 Power Down #1 LDOSET LDOSET LDO Voltage Select Register 0x20 -1 read-write n 0x0 0x0 LDOSET Select LDO Output Voltage Note that maximum I/O pad operation speed only specified for voltage >2.4V. 0 2 read-write 0 3.0V 0 1 1.8V 1 2 2.4V 2 3 3.3V 3 MICBEN MICBEN Microphone Bias Enable Register 0x2C -1 read-write n 0x0 0x0 MICBEN Enable Microphone Bias Generator 0 1 read-write 0 Powered Down #0 1 Enabled #1 MICBSEL MICBSEL Microphone Bias Select Register 0x28 -1 read-write n 0x0 0x0 REF Select Reference Source For MICBIAS Generator VMID provides superior noise performance for MICBIAS generation and should be used unless fixed voltage is absolutely necessary, then noise performance can be sacrificed and bandgap voltage used as reference. 2 1 read-write 0 VMID = VCCA/2 is reference source #0 1 VBG (bandgap voltage reference) is reference source #1 SEL Select Microphone Bias Voltage MICBMODE = 0 0: 90% VCCA 1: 65% VCCA 2: 75% VCCA 3: 50% VCCA MICBMODE = 1 0: 2.4V 1: 1.7V 2: 2.0V 3: 1.3V 0 2 read-write PGAEN PGAEN PGA Enable Register 0x60 -1 read-write n 0x0 0x0 BOOSTGAIN Boost Stage Gain Setting 3 1 read-write 0 Gain = 0dB #0 1 Gain = 26dB #1 PU_BOOST Power Up Control For Boost Stage Amplifier This amplifier must be powered up for signal path operation. 2 1 read-write 0 Power Down #0 1 Power up #1 PU_PGA Power Up Control For PGA Amplifier This amplifier must be powered up for signal path operation. 1 1 read-write 0 Power Down #0 1 Power up #1 REF_SEL Select Reference For Analog Path Signal path is normally referenced to VMID (VCCA/2). To use an absolute reference this can be set to VBG = 1.2V. 0 1 read-write 0 Select VMID voltage as analog ground reference #0 1 Select Bandgap voltage as analog ground reference #1 PGAGAIN PGAGAIN PGA Gain Select Register 0x68 -1 read-write n 0x0 0x0 GAIN Select The PGA Gain Setting From -12dB to 35.25dB in 0.75dB step size. 0x00 is lowest gain setting at -12dB and 0x3F is largest gain at 35.25dB. 0 6 read-write GAIN_READ Current PGA Gain Read Only. May be different from GAIN register when AGC is enabled and is controlling the PGA gain. 8 6 read-write SIGCTRL SIGCTRL Signal Path Control Register 0x64 -1 read-write n 0x0 0x0 MUTE_IPBOOST Boost Stage Mute Control 6 1 read-write 0 Normal #0 1 Signal Muted #1 MUTE_PGA PGA Mute Control 5 1 read-write 0 Normal #0 1 Signal Muted #1 PU_BUFADC Power Up Control For ADC Reference Buffer This block must be powered up for signal path operation. 2 1 read-write 0 Power down #0 1 Power up #1 PU_BUFPGA Power Up Control For PGA Reference Buffer This block must be powered up for signal path operation. 1 1 read-write 0 Power down #0 1 Power up #1 PU_IBGEN Power Up Control For Current Bias Generation This block must be powered up for signal path operation. 3 1 read-write 0 Power down #0 1 Power up #1 PU_MOD Power Up ADC ΣΔ Modulator This block must be powered up for ADC operation. 4 1 read-write 0 Power down #0 1 Power up #1 PU_ZCD Power Up And Enable Control For Zero Cross Detect Comparator When enabled PGA gain settings will only be updated when ADC input signal crosses zero signal threshold. To operate ZCD the ALC peripheral clock (SYSCLK.BIQALC_EN) must also be enabled and BIQ->BIQ_CTRL.RSTn = 1 to allow ZCD clocks to be generated. 0 1 read-write 0 Power down #0 1 Power up and enable zero cross detection #1 TMANALOG TMANALOG Analog Test Mode Register 0x40 -1 read-write n 0x0 0x0 TMPOWER TMPOWER Power Test Mode Register 0x3C -1 read-write n 0x0 0x0 TRIM TRIM Oscillator Trim Register 0x84 -1 read-write n 0x0 0x0 COARSE COARSE Current COARSE range setting of the oscillator. Read Only 8 8 read-write OSCTRIM Oscillator Trim Reads current oscillator trim setting. Read Only. 0 8 read-write SUPERFINE Superfine The SUPERFINE trim setting is an 8bit signed integer. It adjusts the master oscillator by dithering the FINE trim setting between the current setting and one setting above (values 1,127) or below (values -1, -128) the current trim setting. Each step effectively moves the frequency 1/128th of the full FINE trim step size. 16 8 read-write VMID VMID VMID Reference Control Register 0x0 -1 read-write n 0x0 0x0 PDHIRES Power Down High (360kΩ) Resistance Reference 2 1 read-write 0 Connect the High Resistance reference to VMID. Use this setting for minimum power consumption #0 1 The High Resistance reference is disconnected from VMID. Default power down and reset condition #1 PDLORES Power Down Low (4.8kΩ) Resistance Reference 1 1 read-write 0 Connect the Low Resistance reference to VMID. Use this setting for fast power up of VMID. Can be turned off after 50ms to save power #0 1 The Low Resistance reference is disconnected from VMID. Default power down and reset condition #1 PULLDOWN VMID Pulldown 0 1 read-write 0 Release VMID pin for reference operation #0 1 Pull VMID pin to ground. Default power down and reset condition #1 VSET VSET Logic Power Control Register 0x38 -1 read-write n 0x0 0x0 BIQ BIQ Register Map BIQ 0x0 0x0 0x3C registers n 0x40 0x4 registers n COEFF0 BIQ_COEFF0 Coefficient b0 In H(z) Transfer Function (3.16 format) - 1st stage BIQ Coefficients 0x0 -1 read-write n 0x0 0x0 COEFF1 BIQ_COEFF1 Coefficient b1 In H(z) Transfer Function (3.16 format) - 1st stage BIQ Coefficients 0x4 -1 read-write n 0x0 0x0 COEFF10 BIQ_COEFF10 Coefficient b0 In H(z) Transfer Function (3.16 format) - 3rd stage BIQ Coefficients 0x28 -1 read-write n 0x0 0x0 COEFF11 BIQ_COEFF11 Coefficient b1 In H(z) Transfer Function (3.16 format) - 3rd stage BIQ Coefficients 0x2C -1 read-write n 0x0 0x0 COEFF12 BIQ_COEFF12 Coefficient b2 In H(z) Transfer Function (3.16 format) - 3rd stage BIQ Coefficients 0x30 -1 read-write n 0x0 0x0 COEFF13 BIQ_COEFF13 Coefficient a1 In H(z) Transfer Function (3.16 format) - 3rd stage BIQ Coefficients 0x34 -1 read-write n 0x0 0x0 COEFF14 BIQ_COEFF14 Coefficient a2 In H(z) Transfer Function (3.16 format) - 3rd stage BIQ Coefficients 0x38 -1 read-write n 0x0 0x0 COEFF2 BIQ_COEFF2 Coefficient b2 In H(z) Transfer Function (3.16 format) - 1st stage BIQ Coefficients 0x8 -1 read-write n 0x0 0x0 COEFF3 BIQ_COEFF3 Coefficient a1 In H(z) Transfer Function (3.16 format) - 1st stage BIQ Coefficients 0xC -1 read-write n 0x0 0x0 COEFF4 BIQ_COEFF4 Coefficient a2 In H(z) Transfer Function (3.16 format) - 1st stage BIQ Coefficients 0x10 -1 read-write n 0x0 0x0 COEFF5 BIQ_COEFF5 Coefficient b0 In H(z) Transfer Function (3.16 format) - 2nd stage BIQ Coefficients 0x14 -1 read-write n 0x0 0x0 COEFF6 BIQ_COEFF6 Coefficient b1 In H(z) Transfer Function (3.16 format) - 2nd stage BIQ Coefficients 0x18 -1 read-write n 0x0 0x0 COEFF7 BIQ_COEFF7 Coefficient b2 In H(z) Transfer Function (3.16 format) - 2nd stage BIQ Coefficients 0x1C -1 read-write n 0x0 0x0 COEFF8 BIQ_COEFF8 Coefficient a1 In H(z) Transfer Function (3.16 format) - 2nd stage BIQ Coefficients 0x20 -1 read-write n 0x0 0x0 COEFF9 BIQ_COEFF9 Coefficient a2 In H(z) Transfer Function (3.16 format) - 2nd stage BIQ Coefficients 0x24 -1 read-write n 0x0 0x0 CTRL BIQ_CTRL BIQ Control Register 0x40 -1 read-write n 0x0 0x0 EN BIQ Filter Start To Run 0 1 read-write 0 BIQ filter is not processing #0 1 BIQ filter is on #1 PRGCOEF Programming Mode Coefficient Control Bit This bit must be turned off when BIQEN in on. 2 1 read-write 0 Coefficient RAM is in normal mode #0 1 coefficient RAM is under programming mode #1 RSTn Move BIQ Out Of Reset State 3 1 read-write 0 BIQ filter is in reset state #0 1 When this bit is on, the default coefficients will be downloaded to the coefficient ram automatically in 32 internal system clocks. Processor must delay enough time before changing the coefficients or turn the BIQ on #1 SELPWM AC Path Selection For BIQ 1 1 read-write 0 used in ADC path #0 1 used in DPWM path #1 SR_DIV Sample Rate Divider This register is used to program the operating sampling rate of the biquad filter. The sample rate is defined as HCLK/(SR_DIV+1). Default to 3071 so the sampling rate is 16K when HCLK is 49.152MHz. 16 13 read-write UPSR DPWM Path Up Sample Rate (From SR_DIV Result) This register is only used when SELPWM is set to 1. The operating sample rate for the biquad filter will be (UPSR+1)*HCLK/(SR_DIV+1). Default value for this register is 3. 4 3 read-write BOD BOD Register Map BOD 0x0 0x0 0x14 registers n DET_TIMER DET_TIMER Brown Out Detector Timer Register 0x10 -1 read-write n 0x0 0x0 OFF_DUR Time BOD Detector Is Off (OFF_DUR+1)*100us . Minimum value is 7. (default is 99.6ms) 0 16 read-write ON_DUR Time BOD Detector Is Active (ON_DUR+1) * 100us. Minimum value is 1. (default is 400us) 16 4 read-write EN BOD_EN Brown Out Detector Enable Register 0x4 -1 read-write n 0x0 0x0 BOD_OUT Output of BOD Detection Block This signal can be monitored to determine the current state of the BOD comparator. Read '1' implies that VCC is less than BOD_LVL. 4 1 read-write EN BOD Enable 1xb = Enable continuous BOD detection. 01b = Enable time multiplexed BOD detection. See DET_TIMER register. 00b = Disable BOD Detection. 0 2 read-write IE BOD Interrupt Enable 2 1 read-write 0 Disable BOD Interrupt #0 1 Enable BOD Interrupt #1 INT Current Status Of Interrupt Latched whenever a BOD event occurs and IE = 1. Write '1' to clear. 3 1 read-write SEL BOD_SEL Brown Out Detector Select Register 0x0 -1 read-write n 0x0 0x0 BOD_HYS BOD Hysteresis 3 1 read-write 0 Hysteresis Disabled #0 1 Enable Hysteresis of BOD detection #1 BOD_LVL BOD Voltage Level 111b = 4.6V 110b = 3.0V 101b = 2.8V 100b = 2.625V 011b = 2.5V 010b = 2.4V 001b = 2.2V 000b = 2.1V 0 3 read-write TALARM_EN TALARM_EN Temperature Alarm Enable Register 0xC -1 read-write n 0x0 0x0 EN TALARM Enable 0 1 read-write 0 Disable TALARM Detection #0 1 Enable TALARM Detection #1 IE TALARM Interrupt Enable 2 1 read-write 0 Disable TALARM Interrupt #0 1 Enable TALARM Interrupt #1 INT Current status of interrupt Latched whenever a Temperature Sense event occurs and IE = 1. Write '1' to clear. 3 1 read-write TALARM Output of TALARM Block Can be polled to determine whether TALARM active (be 1). 1 1 read-write TALARM_SEL TALARM_SEL Temperature Alarm Select Register 0x8 -1 read-write n 0x0 0x0 LVL Temperature Alarm Sense Level 0000:105C 0001:115C 0010:125C 0100:135C 1000:145C 0 4 read-write CLK CLK Register Map CLK 0x0 0x0 0x2C registers n AHBCLK AHBCLK AHB Device Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 CPU_EN CPU Clock Enable (HCLK) Must be left as '1' for normal operation. 0 1 read-write ISP_EN Flash ISP Controller Clock Enable Control 2 1 read-write 0 To disable the Flash ISP engine clock #0 1 To enable the Flash ISP engine clock #1 PDMA_EN PDMA Controller Clock Enable Control 1 1 read-write 0 To disable the PDMA engine clock #0 1 To enable the PDMA engine clock #1 APBCLK APBCLK APB Device Clock Enable Control Register 0x8 -1 read-write n 0x0 0x0 ACMP_EN Analog Comparator Clock Enable Control 22 1 read-write 0 Disable #0 1 Enable #1 ADC_EN Audio Analog-Digital-Converter (ADC) Clock Enable Control 28 1 read-write 0 Disable #0 1 Enable #1 ANA_EN Analog Block Clock Enable Control 30 1 read-write 0 Disable #0 1 Enable #1 BIQALC_EN Biquad Filter And Automatic Level Control Block Clock Enable Control 18 1 read-write 0 Disable #0 1 Enable #1 CRC_EN Cyclic Redundancy Check Block Clock Enable Control 19 1 read-write 0 Disable #0 1 Enable #1 DPWM_EN Differential PWM Speaker Driver Clock Enable Control 13 1 read-write 0 Disable #0 1 Enable #1 I2C0_EN I2C0 Clock Enable Control 8 1 read-write 0 Disable #0 1 Enable #1 I2S_EN I2S Clock Enable Control 29 1 read-write 0 Disable #0 1 Enable #1 PWM01_EN PWM Block Clock Enable Control 20 1 read-write 0 Disable #0 1 Enable #1 RTC_EN Real-Time-Clock APB Interface Clock Control 5 1 read-write 0 Disable #0 1 Enable #1 SBRAM_EN Standby RAM Clock Enable Control 26 1 read-write 0 Disable #0 1 Enable #1 SPI0_EN SPI0 Clock Enable Control 12 1 read-write 0 Disable #0 1 Enable #1 TMR0_EN Timer0 Clock Enable Control 6 1 read-write 0 Disable #0 1 Enable #1 TMR1_EN Timer1 Clock Enable Control 7 1 read-write 0 Disable #0 1 Enable #1 UART0_EN UART0 Clock Enable Control 16 1 read-write 0 Disable #0 1 Enable #1 WDG_EN Watchdog Clock Enable Control 4 1 read-write 0 Disable #0 1 Enable #1 CLKDIV CLKDIV Clock Divider Number Register 0x18 -1 read-write n 0x0 0x0 ADC_N ADC Clock Divide Number From ADC Clock Source The ADC clock frequency = (ADC clock source frequency ) / (ADC_N + 1) 16 8 read-write HCLK_N HCLK Clock Divide Number From HCLK Clock Source The HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1) 0 4 read-write UART_N UART Clock Divide Number From UART Clock Source The UART clock frequency = (UART clock source frequency ) / (UART_N + 1) 8 4 read-write CLKSEL0 CLKSEL0 Clock Source Select Control Register 0 0x10 -1 read-write n 0x0 0x0 HCLK_S HCLK Clock Source Select Ensure that related clock sources (pre-select and new-select) are enabled before updating register. These bits are protected, to write to bits first perform the unlock sequence (see Protected Register Lock Key Register (REGLOCK)) 000 = clock source from internal OSC48M oscillator. 001 = clock source from external 32kHz crystal clock 010 = clock source from internal 16 kHz oscillator clock Others = reserved 0 3 read-write OSCFSel OSC48M Frequency Select Determines which trim setting to use for OSC48M internal oscillator. Oscillator is factory trimmed within 1% to: 6 1 read-write 0 49.152MHz (Default) #0 1 32.768MHz #1 STCLK_S MCU Cortex_M0 SysTick Clock Source Select These bits are protected, to write to bits first perform the unlock sequence (see Protected Register Lock Key Register (REGLOCK)) 000 = clock source from 16 kHz internal clock 001 = clock source from external 32kHz crystal clock 010 = clock source from 16 kHz internal oscillator divided by 2 011 = clock source from OSC49M internal oscillator divided by 2 1xx = clock source from HCLK / 2 (Default) Note that to use STCLK_S as source of SysTic timer the CLKSRC bit of SysTick->CTRL must be set to 0. 3 3 read-write CLKSEL1 CLKSEL1 Clock Source Select Control Register 1 0x14 -1 read-write n 0x0 0x0 DPWM_S Differential Speaker Driver PWM Clock Source Select 4 1 read-write 0 OSC48M clock #0 1 2x OSC48M clock #1 PWM01_S PWM0 And PWM1 Clock Source Select PWM0 and PWM1 uses the same clock source, and prescaler 28 2 read-write 0 clock source from internal 16 kHz oscillator #00 1 clock source from external 32kHz crystal clock #01 2 clock source from HCLK #10 3 clock source from internal OSC48M oscillator clock #11 TMR0_S TIMER0 Clock Source Select 000 = clock source from internal 16 kHz oscillator 001 = clock source from external 32kHz crystal clock 010 = clock source from HCLK 011 = clock source from external pin (GPIOA[14]) 1xx = clock source from internal OSC48M oscillator clock 8 3 read-write TMR1_S TIMER1 Clock Source Select 000 = clock source from internal 16 kHz oscillator 001 = clock source from external 32kHz crystal clock 010 = clock source from HCLK 011 = clock source from external pin (GPIOA[15]) 1xx = clock source from internal OSC48M oscillator clock 12 3 read-write WDG_S WDG CLK Clock Source Select 0 2 read-write 0 clock source from internal OSC48M oscillator clock #00 1 clock source from external 32kHz crystal clock #01 2 clock source from HCLK/2048 clock #10 3 clock source from internal 16 kHz oscillator clock #11 CLKSEL2 CLKSEL2 Clock Source Select Control Register 2 0x1C -1 read-write n 0x0 0x0 I2S_S I2S Clock Source Select 0 2 read-write 0 clock source from internal 16 kHz oscillator #00 1 clock source from external 32kHz crystal clock #01 2 clock source from HCLK #10 3 clock source from internal OSC48M oscillator clock #11 CLKSLEEP CLKSLEEP Sleep Clock Source Select Register 0x20 -1 read-write n 0x0 0x0 ACMP_EN Analog Comparator Sleep Clock Enable Control 22 1 read-write 0 Disable #0 1 Enable #1 ADC_EN Audio Analog-Digital-Converter (ADC) Sleep Clock Enable Control 28 1 read-write 0 Disable #0 1 Enable #1 ANA_EN Analog Block Sleep Clock Enable Control 30 1 read-write 0 Disable #0 1 Enable #1 BIQALC_EN Biquad filter/ALC block Sleep Clock Enable Control 18 1 read-write 0 Disable #0 1 Enable #1 CPU_EN CPU Clock Sleep Enable (HCLK) Must be left as '1' for normal operation. 0 1 read-write 0 Disable #0 1 Enable #1 CRC_EN Cyclic Redundancy Check Sleep Block Clock Enable Control 19 1 read-write 0 Disable #0 1 Enable #1 DPWM_EN Differential PWM Speaker Driver Sleep Clock Enable Control 13 1 read-write 0 Disable #0 1 Enable #1 I2C0_EN I2C0 Sleep Clock Enable Control 8 1 read-write 0 Disable #0 1 Enable #1 I2S_EN I2S Sleep Clock Enable Control 29 1 read-write 0 Disable #0 1 Enable #1 ISP_EN Flash ISP Controller Sleep Clock Enable Control 2 1 read-write 0 Disable #0 1 Enable #1 PDMA_EN PDMA Controller Sleep Clock Enable Control 1 1 read-write 0 Disable #0 1 Enable #1 PWM01_EN PWM Block Sleep Clock Enable Control 20 1 read-write 0 Disable #0 1 Enable #1 RTC_EN Real-Time- Sleep Clock APB Interface Clock Control 5 1 read-write 0 Disable #0 1 Enable #1 SBRAM_EN Standby RAM Sleep Clock Enable Control 26 1 read-write 0 Disable #0 1 Enable #1 SPI0_EN SPI0 Sleep Clock Enable Control 12 1 read-write 0 Disable #0 1 Enable #1 TMR0_EN Timer0 Sleep Clock Enable Control 6 1 read-write 0 Disable #0 1 Enable #1 TMR1_EN Timer1 Sleep Clock Enable Control 7 1 read-write 0 Disable #0 1 Enable #1 UART0_EN UART0 Sleep Clock Enable Control 16 1 read-write 0 Disable #0 1 Enable #1 WDG_EN Watchdog Sleep Clock Enable Control 4 1 read-write 0 Disable #0 1 Enable #1 DBGPD DBGPD Debug Port Power Down Disable Register 0x28 -1 read-write n 0x0 0x0 DISABLE_PD Disable Power Down 0 1 read-write 0 Enable power down requests #0 1 Disable power down requests #1 ICE_CLK ICE_CLK Pin State Read Only. Current state of ICE_CLK pin. 6 1 read-write ICE_DAT ICE_DAT Pin State Read Only. Current state of ICE_DAT pin. 7 1 read-write DPDSTATE DPDSTATE Deep Power Down State Register 0xC -1 read-write n 0x0 0x0 DPD_STATE_RD DPD State Read Back Read back of DPDSTATE register. This register was preserved from last DPD event . 8 8 read-write DPD_STATE_WR DPD State Write To set the DPDSTATE register, write value to this register. Data is latched on next DPD event. 0 8 read-write PFLAGCON PFLAGCON Power State Flag Register 0x24 -1 read-write n 0x0 0x0 DS_FLAG Deep Sleep Flag This flag is set if core logic was placed in Deep Sleep mode. Write '1' to clear flag. 0 1 read-write PD_FLAG Powered Down Flag This flag is set if core logic was powered down to Standby (SPD). Write '1' to clear flag. 2 1 read-write STOP_FLAG Stop Flag This flag is set if core logic was stopped but not powered down. Write '1' to clear flag. 1 1 read-write PWRCON PWRCON System Power Control Register 0x0 -1 read-write n 0x0 0x0 DEEP_PD Deep Power Down (DPD) Bit Set to '1' and issue WFI/WFE instruction to enter DPD mode. 11 1 read-write OSC16K_EN OSC16K Oscillator Enable Bit 3 1 read-write 0 disable #0 1 enable (default) #1 OSC16K_ENB OSC16K Enabled Control Determines whether OSC16K is enabled in DPD mode. If OSC16K is disabled, device cannot wake from DPD with TIMER_SEL delay. 17 1 read-write 0 enabled #0 1 disabled #1 OSC49M_EN OSC49M Oscillator Enable Bit 2 1 read-write 0 disable #0 1 enable (default) #1 PIN_ENB Wakeup Pin Enabled Control Determines whether WAKEUP pin is enabled in DPD mode. 16 1 read-write 0 enabled #0 1 disabled #1 PIN_WAKE Pin Wakeup Flag Read Only. This flag indicates that wakeup of device was requested with a high to low transition of the WAKEUP pin. Flag is cleared when DPD mode is entered. 24 1 read-write POI_WAKE POI Wakeup Flag Read Only. This flag indicates that wakeup of device was requested with a power-on reset. Flag is cleared when DPD mode is entered. 26 1 read-write STANDBY_PD Standby Power Down (SPD) Bit Set to '1' and issue WFI/WFE instruction to enter SPD mode. 10 1 read-write STOP Stop Reserved - do not set to '1' 9 1 read-write TIMER_SEL Select Wakeup Timer TIMER_SEL[0] = 1: WAKEUP after 128 OSC16K clocks (12.8 ms) TIMER_SEL[1] = 1: WAKEUP after 256 OSC16K clocks (25.6 ms) TIMER_SEL[2] = 1: WAKEUP after 512 OSC16K clocks (51.2 ms) TIMER_SEL[3] = 1: WAKEUP after 1024 OSC16K clocks (102.4ms) 20 4 read-write TIMER_SEL_RD Current Wakeup Timer Setting Read-Only. Read back of the current WAKEUP timer setting. This value is updated with TIMER_SEL upon entering DPD mode. 28 4 read-write TIMER_WAKE Timer Wakeup Flag Read Only. This flag indicates that wakeup of device was requested with TIMER count of the 16Khz oscillator. Flag is cleared when DPD mode is entered. 25 1 read-write XTAL32K_EN External 32.768 kHz Crystal Enable Bit 1 1 read-write 0 disable (default) #0 1 enable #1 CRC CRC Register Map CRC 0x0 0x0 0xC registers n EN CRC_EN CRC Enable Control Register 0x0 -1 read-write n 0x0 0x0 LEN CRC Packet Length Indicates number of bytes of CRC input to process. CRC calculation will stop once input number of bytes = LEN+1. Maximum packet size is 512 bytes, for LEN = 511. Writing any value to this register will flush all previous calculations and restart a new CRC calculation. 0 9 read-write LSB CRC LSB mode Determines whether CRC Generator processes input words (32bit/4Bytes) LSB (least significant byte) first or MSB (most significant byte) first. For example if LSB = 1, and 0x01020304 is written to CRC_IN, bytes will be processed in order 0x04, 0x03, 0x02, 0x01. If LSB = 0, then order would be 0x01, 0x02, 0x3, 0x04. Writing any value to this register will flush all previous calculations and restart a new CRC calculation. 16 1 read-write 0 CRC input is MSB first (default) #0 1 CRC input is LSB first #1 IN CRC_IN CRC Input Register 0x4 -1 read-write n 0x0 0x0 CRC_IN CRC Input The string of bytes to perform CRC calculation on. When LSB = 0, CRC performs calculation byte by byte in the order CRC_IN[31:24], CRC_IN[23:16], CRC_IN[15:8], CRC_IN[7:0]. When LSB = 1, CRC performs calculation byte by byte in the order CRC_IN[7:0], CRC_IN[15:8], CRC_IN[23:16], CRC_IN[31:24]. If number of input bytes exceeds CRC Packet Length (CRC_EN[8:0]+1), any additional input bytes will be ignored. The CRC generator takes four clock cycles to process the CRC input. Software must ensure that at least four clock cycles occur between writes of CRC_IN. Compiled assembly language can be examined to ensure this requirement is met. 0 32 read-write OUT CRC_OUT CRC Output Register 0x8 -1 read-only n 0x0 0x0 CRC_OUT CRC Output The result of CRC computation. The result is valid four clock cycles after last CRC_IN input data is written to CRC generator. 0 16 read-only DPWM DPWM Register Map DPWM 0x0 0x0 0x14 registers n CTRL CTRL DPWM Control Register 0x0 -1 read-write n 0x0 0x0 Deadtime DPWM Driver Deadtime Control Enabling this bit will insert an additional clock cycle deadtime into the switching of PMOS and NMOS driver transistors. 3 1 read-write Dither DPWM Signal Dither Control To prevent structured noise on PWM output due to DC offsets in the input signal it is possible to add random dither to the PWM signal. These bits control the dither: 4 2 read-write 0 No dither 0 1 +/- 1 bit dither 1 3 +/- 2 bit dither 3 Enable DPWM Enable 6 1 read-write 0 Disable DPWM, SPK pins are tri-state, CIC filter is reset, FIFO pointers are reset (FIFO data is not reset) #0 1 Enable DPWM, SPK pins are enabled and driven, data is taken from FIFO #1 Freq DPWM Modulation Frequency This parameter controls the carrier modulation frequency of the PWM signal as a proportion of DPWM_CLK. Freq : DPWM_CLK Division : Frequency for DPWM_CLK = 98.304MHZ 0 : 228 : 431158 1 : 156 : 630154 2 : 76 : 1293474 3 : 52 : 1890462 4 : 780 : 126031 5 : 524 : 187603 6 : 396 : 248242 7 : 268 : 366806 0 3 read-write DMA DMA DPWM PDMA Control Register 0x8 -1 read-write n 0x0 0x0 EnablePDMA Enable DPWM DMA Interface 0 1 read-write 0 Disable PDMA. No requests will be made to PDMA controller #0 1 Enable PDMA. Block will request data from PDMA controller whenever FIFO is not empty #1 FIFO FIFO DPWM FIFO Input 0xC -1 write-only n 0x0 0x0 FIFO DPWM FIFO Audio Data Input A write to this register pushes data onto the DPWM FIFO and increments the write pointer. This is the address that PDMA writes audio data to. 0 16 write-only STAT STAT DPWM FIFO Status Register 0x4 -1 read-only n 0x0 0x0 EMPTY FIFO Empty 1 1 read-only 0 FIFO is not empty #0 1 FIFO is empty #1 FULL FIFO Full 0 1 read-only 0 FIFO is not full #0 1 FIFO is full #1 ZOH_DIV ZOH_DIV DPWM Zero Order Hold Division Register 0x10 -1 read-write n 0x0 0x0 ZOH_DIV DPWM Zero Order Hold, Down-Sampling Divisor The input sample rate of the DPWM is set by HCLK frequency and the divisor set in this register by the following formula: Fs = HCLK/ZOH_DIV/64 Valid range is 1 to 255. Default is 48, which gives a sample rate of 16kHz for a 49.152MHz (default) HCLK. 0 8 read-write FMC FMC Register Map FMC 0x0 0x0 0x18 registers n DFBADR DFBADR Data Flash Base Address 0x14 -1 read-only n 0x0 0x0 DFBA Data Flash Base Address This register reports the data flash starting address. It is a read only register. Data flash size is defined by user configuration, register content is loaded from Config1 when chip is reset. 0 32 read-only ISPADR ISPADR ISP Address Register 0x4 -1 read-write n 0x0 0x0 ISPADR ISP Address Register This is the memory address register that a subsequent ISP command will access. ISP operation are carried out on 32bit words only, consequently ISPARD[1:0] must be 00b for correct ISP operation. 0 32 read-write ISPCMD ISPCMD ISP Command Register 0xC -1 read-write n 0x0 0x0 ISPCMD ISP Command Operation Mode : ISPCMD Standby : 0x3X Read : 0x00 Program : 0x21 Page Erase : 0x22 Read CID : 0x0B Read DID : 0x0C 0 6 read-write ISPCON ISPCON ISP Control Register 0x0 -1 read-write n 0x0 0x0 BS Boot Select Modify this bit to select which ROM next boot is to occur. This bit also functions as MCU boot status flag, which can be used to check where MCU booted from. This bit is initialized after power-on reset with the inverse of CBS in Config0 It is not reset for any other reset event. 1 1 read-write 0 APROM #0 1 LDROM #1 CFGUEN CONFIG Update Enable When enabled, ISP functions can access the CONFIG address space and modify device configuration area. 4 1 read-write 0 Disable #0 1 Enable #1 ISPEN ISP Enable 0 1 read-write 0 Disable ISP function #0 1 Enable ISP function #1 ISPFF ISP Fail Flag This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself. (2) LDROM writes to itself. (3) Destination address is illegal, such as over an available range. Write 1 to clear. 6 1 read-write LDUEN LDROM Update Enable LDROM update enable bit. 5 1 read-write 0 LDROM cannot be updated #0 1 LDROM can be updated when the MCU runs in APROM #1 SWRST Software Reset Writing 1 to this bit will initiate a software reset. It is cleared by hardware after reset. 7 1 read-write ISPDAT ISPDAT ISP Data Register 0x8 -1 read-write n 0x0 0x0 ISPDAT ISP Data Register Write data to this register before an ISP program operation. Read data from this register after an ISP read operation 0 32 read-write ISPTRG ISPTRG ISP Trigger Control Register 0x10 -1 read-write n 0x0 0x0 ISPGO ISP Start Trigger Write 1 to start ISP operation. This will be cleared to 0 by hardware automatically when ISP operation is finished. After triggering an ISP function M0 instruction pipeline should be flushed with a ISB instruction to guarantee data integrity. This is a protected register, user must first follow the unlock sequence (see Protected Register Lock Key Register (REGLOCK)) to gain access. 0 1 read-write 0 ISP operation is finished #0 1 ISP is on going #1 GCR GCR Register Map GCR 0x0 0x100 0x4 registers n 0x110 0x8 registers n 0x30 0x10 registers n 0x4 0xC registers n 0x54 0x4 registers n GPA_ALT GPA_ALT GPIOA multiple function control register 0x38 -1 read-write n 0x0 0x0 GPA0 Alternate Function Setting For GPA1 0 2 read-write 0 GPIO #00 1 SPI_MOSI0 #01 2 MCLK #10 GPA1 Alternate Function Setting For GPA2 2 2 read-write 0 GPIO #00 1 SPI_SCLK #01 2 I2C_SCL #10 GPA10 Alternate Function Setting For GPA10 20 2 read-write 0 GPIO #00 1 I2C_SDA #01 2 I2S_SDI #10 3 UART_RTSn #11 GPA11 Alternate Function Setting For GPA11 22 2 read-write 0 GPIO #00 1 I2C_SCL #01 2 I2S_SDO #10 3 UART_CTSn #11 GPA12 Alternate Function Setting For GPA12 24 2 read-write 0 GPIO #00 1 PWM0 #01 2 SPKP #10 3 I2S_FS #11 GPA13 Alternate Function Setting For GPA13 26 2 read-write 0 GPIO #00 1 PWM1 #01 2 SPKM #10 3 I2S_BCLK #11 GPA14 Alternate Function Setting For GPA14 28 2 read-write 0 GPIO #00 1 TM0 #01 2 SDCLK #10 3 SDCLKn #11 GPA15 Alternate Function Setting For GPA15 30 2 read-write 0 GPIO #00 1 TM1 #01 2 SDIN #10 GPA2 Alternate Function Setting For GPA3 4 2 read-write 0 GPIO #00 1 SPI_SSB0 #01 GPA3 Alternate Function Setting For GPA3 6 2 read-write 0 GPIO #00 1 SPI_MISO0 #01 2 I2C_SDA #10 GPA4 Alternate Function Setting For GPA4 8 2 read-write 0 GPIO #00 1 I2S_FS #01 GPA5 Alternate Function Setting For GPA5 10 2 read-write 0 GPIO #00 1 I2S_BCLK #01 GPA6 Alternate Function Setting For GPA6 12 2 read-write 0 GPIO #00 1 I2S_SDI #01 GPA7 Alternate Function Setting For GPA7 14 2 read-write 0 GPIO #00 1 I2S_SDO #01 GPA8 Alternate Function Setting For GPA8 16 2 read-write 0 GPIO #00 1 UART_TX #01 2 I2S_FS #10 GPA9 Alternate Function Setting For GPA9 18 2 read-write 0 GPIO #00 1 UART_RX #01 2 I2S_BCLK #10 GPA_INP GPA_INP GPIOA input type control register 0x30 -1 read-write n 0x0 0x0 SCHMITT16 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 16 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 SCHMITT17 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 17 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 SCHMITT18 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 18 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 SCHMITT19 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 19 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 SCHMITT20 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 20 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 SCHMITT21 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 21 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 SCHMITT22 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 22 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 SCHMITT23 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 23 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 SCHMITT24 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 24 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 SCHMITT25 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 25 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 SCHMITT26 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 26 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 SCHMITT27 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 27 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 SCHMITT28 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 28 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 SCHMITT29 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 29 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 SCHMITT30 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 30 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 SCHMITT31 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 31 1 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger disabled #0 1 GPIOA[15:0] I/O input Schmitt Trigger enabled #1 GPB_ALT GPB_ALT GPIOB multiple function control register 0x3C -1 read-write n 0x0 0x0 GPB0 Alternate Function Setting For GPB0 0 2 read-write 0 GPIO #00 1 SPI_SSB1 #01 2 CMP0 #10 3 SPI_SSB0 #11 GPB1 Alternate Function Setting For GPB1 2 2 read-write 0 GPIO #00 1 MCLK #01 2 CMP1 #10 3 SPI_SSB1 #11 GPB2 Alternate Function Setting For GPB2 4 2 read-write 0 GPIO #00 1 I2C_SCL #01 2 CMP2 #10 3 SPI_SCLK #11 GPB3 Alternate Function Setting For GPB3 6 2 read-write 0 GPIO #00 1 I2C_SDA #01 2 CMP3 #10 3 SPI_MISO0 #11 GPB4 Alternate Function Setting For GPB4 8 2 read-write 0 GPIO #00 1 PWM0B #01 2 CMP4 #10 3 SPI_MOSI0 #11 GPB5 Alternate Function Setting For GPB5 10 2 read-write 0 GPIO #00 1 PWM1B #01 2 CMP5 #10 3 SPI_MISO1 #11 GPB6 Alternate Function Setting For GPB6 12 2 read-write 0 GPIO #00 1 I2S_SDI #01 2 CMP6 #10 3 SPI_MOSI1 #11 GPB7 Alternate Function Setting For GPB7 14 2 read-write 0 GPIO #00 1 I2S_SDO #01 2 CMP7 #10 GPB_INP GPB_INP GPIOB input type control register 0x34 -1 read-write n 0x0 0x0 SCHMITT16 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 16 1 read-write 0 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled #0 1 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled #1 SCHMITT17 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 17 1 read-write 0 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled #0 1 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled #1 SCHMITT18 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 18 1 read-write 0 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled #0 1 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled #1 SCHMITT19 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 19 1 read-write 0 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled #0 1 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled #1 SCHMITT20 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 20 1 read-write 0 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled #0 1 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled #1 SCHMITT21 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 21 1 read-write 0 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled #0 1 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled #1 SCHMITT22 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 22 1 read-write 0 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled #0 1 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled #1 SCHMITT23 Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled. 23 1 read-write 0 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled #0 1 GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled #1 IPRSTC1 IPRSTC1 IP Reset Control Resister1 0x8 -1 read-write n 0x0 0x0 CHIP_RST CHIP One Shot Reset Set this bit will reset the whole chip, this bit will automatically return to 0 after the 2 clock cycles. CHIP_RST has same behavior as POR reset, all the chip modules are reset and the chip configuration settings from flash are reloaded. This bit is a protected bit, to program first issue the unlock sequence (see Protected Register Lock Key Register (REGLOCK)) 0 1 read-write 0 Normal #0 1 Reset CHIP #1 CPU_RST CPU Kernel One Shot Reset Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC), this bit will automatically return to 0 after the 2 clock cycles This bit is a protected bit, to program first issue the unlock sequence (see Protected Register Lock Key Register (REGLOCK)) 1 1 read-write 0 Normal #0 1 Reset CPU #1 PDMA_RST PDMA Controller Reset Set 1 will generate a reset signal to the PDMA Block. User needs to set this bit to 0 to release from the reset state 2 1 read-write 0 Normal operation #0 1 PDMA IP reset #1 IPRSTC2 IPRSTC2 IP Reset Control Resister2 0xC -1 read-write n 0x0 0x0 ACMP_RST Analog Comparator Reset 22 1 read-write 0 Normal Operation #0 1 Reset #1 ADC_RST ADC Controller Reset 28 1 read-write 0 Normal Operation #0 1 Reset #1 ANA_RST Analog Block Control Reset 30 1 read-write 0 Normal Operation #0 1 Reset #1 BIQ_RST Biquad Filter Block Reset 18 1 read-write 0 Normal Operation #0 1 Reset #1 CRC_RST CRC Generation Block Reset 19 1 read-write 0 Normal Operation #0 1 Reset #1 DPWM_RST DPWM Speaker Driver Reset 13 1 read-write 0 Normal Operation #0 1 Reset #1 I2C0_RST I2C0 Controller Reset 8 1 read-write 0 Normal Operation #0 1 Reset #1 I2S_RST I2S Controller Reset 29 1 read-write 0 Normal Operation #0 1 Reset #1 PWM10_RST PWM10 controller Reset 20 1 read-write 0 Normal Operation #0 1 Reset #1 SPI0_RST SPI0 Controller Reset 12 1 read-write 0 Normal Operation #0 1 Reset #1 TMR0_RST Timer0 Controller Reset 6 1 read-write 0 Normal Operation #0 1 Reset #1 TMR1_RST Timer1 Controller Reset 7 1 read-write 0 Normal Operation #0 1 Reset #1 UART0_RST UART0 Controller Reset 16 1 read-write 0 Normal Operation #0 1 Reset #1 OSC16K OSC16K 16K Oscillator trim register 0x114 -1 read-write n 0x0 0x0 OSCTRIM OSCTRIM Oscillator Frequency Adjustment control register 0x110 -1 read-write n 0x0 0x0 OSCTRIM0_RANGE Range Bit For Oscillator 8 1 read-write 0 high range #0 1 low range #1 OSCTRIM0_TRIM 8 Bit Trim For Oscillator TRIM[7:5] are 8 coarse trim ranges which overlap in frequency. TRIM[4:0] are 32 fine trim steps of approximately 0.5% resolution. 0 8 read-write OSCTRIM1_RANGE Range Bit For Oscillator 24 1 read-write 0 high range #0 1 low range #1 OSCTRIM1_TRIM 8 Bit Trim For Oscillator TRIM[7:5] are 8 coarse trim ranges which overlap in frequency. TRIM[4:0] are 32 fine trim steps of approximately 0.5% resolution. 16 8 read-write REGLOCK REGLOCK Register Lock Key Address register 0x100 -1 read-write n 0x0 0x0 RegUnLock Protected Register Unlock Register 0 1 read-write 0 Protected registers are locked. Any write to the target register is ignored #0 1 Protected registers are unlocked #1 RSTSRC RSTSRC System Reset Source Register 0x4 -1 read-write n 0x0 0x0 RSTS_CORE Reset Source From CORE The RSTS_CORE flag is set if the core has been reset. Possible sources of reset are a Power-On Reset (POR), RESETn Pin Reset or PMU reset. This bit is cleared by writing 1 to itself. 0 1 read-write 0 No reset from CORE #0 1 Core was reset by hardware block #1 RSTS_CPU Reset Source From CPU The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTCR1[1]) with a 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC). This bit is cleared by writing 1 to itself. 7 1 read-write 0 No reset from CPU #0 1 The Cortex-M0 CPU kernel and FMC has been reset by software setting CPU_RST to 1 #1 RSTS_PMU Reset Source From PMU The RSTS_PMU flag is set if the PMU. This bit is cleared by writing 1 to itself. 6 1 read-write 0 No reset from PMU #0 1 PMU reset the system from a power down/standby event #1 RSTS_SYS Reset Source From MCU The RSTS_SYS flag is set if the previous reset source originates from the Cortex_M0 kernel. This bit is cleared by writing 1 to itself. 5 1 read-write 0 No reset from MCU #0 1 The Cortex_M0 MCU issued a reset signal to reset the system by software writing 1 to bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel #1 RSTS_WDG Reset Source From WDG The RSTS_WDG flag is set if pervious reset source originates from the Watch-Dog module. This bit is cleared by writing 1 to itself. 2 1 read-write 0 No reset from Watch-Dog #0 1 The Watch-Dog module issued the reset signal to reset the system #1 WAKECR WAKECR WAKEUP pin control register 0x54 -1 read-write n 0x0 0x0 WAKE_DIN State Of Wakeup Pin Read only. 0 1 read-write WAKE_DOUT Wakeup Output State 3 1 read-write 0 drive Low if the corresponding output mode bit is set (default) #0 1 drive High if the corresponding output mode bit is set #1 WAKE_OENB Wakeup Pin Output Enable Bar 2 1 read-write 0 drive WAKE_DOUT to pin #0 1 tristate (default) #1 WAKE_TRI Wakeup Pin Pull-up Control This signal is latched in deep power down and preserved. 1 1 read-write 0 pull-up enable #0 1 tristate (default) #1 GP GPIO Register Map GPIO 0x0 0x0 0x24 registers n 0x180 0x4 registers n 0x40 0x24 registers n DBNCECON DBNCECON Interrupt De-bounce Control 0x180 -1 read-write n 0x0 0x0 DBCLKSEL De-bounce Sampling Cycle Selection. For edge level interrupt GPIO state is sampled every 2^(DBCLKSEL) de-bounce clocks. For example if DBCLKSRC = 6, then interrupt is sampled every 2^6 = 64 de-bounce clocks. If DBCLKSRC is 16KHz oscillator this would be a 64ms debounce. 0 4 read-write DBCLKSRC De-bounce Counter Clock Source Select 4 1 read-write 0 De-bounce counter clock source is HCLK #0 1 De-bounce counter clock source is the internal 16 kHz clock #1 ICLK_ON Interrupt Clock On Mode Set this bit 0 will gate the clock to the interrupt generation circuit if the GPIOx[n] interrupt is disabled. 5 1 read-write 0 disable the clock if the GPIOx[n] interrupt is disabled #0 1 Interrupt generation clock always active #1 GPIOA_DBEN GPIOA_DBEN GPIO Port A De-bounce Enable 0x14 -1 read-write n 0x0 0x0 DBEN0 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 0 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN1 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 1 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN10 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 10 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN11 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 11 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN12 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 12 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN13 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 13 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN14 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 14 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN15 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 15 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN2 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 2 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN3 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 3 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN4 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 4 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN5 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 5 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN6 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 6 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN7 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 7 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN8 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 8 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN9 Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the DBNCECON register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt 9 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 GPIOA_DMASK GPIOA_DMASK GPIO Port A Data Output Write Mask 0xC -1 read-write n 0x0 0x0 DMASK0 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 0 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 DMASK1 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 1 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 DMASK10 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 10 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 DMASK11 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 11 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 DMASK12 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 12 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 DMASK13 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 13 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 DMASK14 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 14 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 DMASK15 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 15 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 DMASK2 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 2 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 DMASK3 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 3 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 DMASK4 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 4 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 DMASK5 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 5 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 DMASK6 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 6 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 DMASK7 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 7 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 DMASK8 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 8 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 DMASK9 Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding DOUTn bit is write protected. 9 1 read-write 0 The corresponding GPIO_DOUT[n] bit can be updated #0 1 The corresponding GPIO_DOUT[n] bit is read only #1 GPIOA_DOUT GPIOA_DOUT GPIO Port A Data Output Value 0x8 -1 read-write n 0x0 0x0 DOUT0 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 0 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 DOUT1 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 1 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 DOUT10 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 10 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 DOUT11 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 11 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 DOUT12 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 12 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 DOUT13 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 13 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 DOUT14 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 14 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 DOUT15 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 15 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 DOUT2 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 2 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 DOUT3 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 3 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 DOUT4 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 4 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 DOUT5 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 5 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 DOUT6 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 6 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 DOUT7 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 7 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 DOUT8 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 8 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 DOUT9 GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode. 9 1 read-write 0 GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set #0 1 GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set #1 GPIOA_IEN GPIOA_IEN GPIO Port A Interrupt Enable 0x1C -1 read-write n 0x0 0x0 IF_EN0 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 0 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IF_EN1 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 1 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IF_EN10 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 10 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IF_EN11 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 11 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IF_EN12 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 12 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IF_EN13 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 13 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IF_EN14 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 14 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IF_EN15 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 15 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IF_EN2 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 2 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IF_EN3 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 3 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IF_EN4 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 4 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IF_EN5 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 5 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IF_EN6 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 6 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IF_EN7 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 7 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IF_EN8 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 8 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IF_EN9 Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 9 1 read-write 0 Disable GPIOx[n] for low-level or high-to-low interrupt #0 1 Enable GPIOx[n] for low-level or high-to-low interrupt #1 IR_EN0 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 16 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 IR_EN1 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 17 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 IR_EN10 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 26 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 IR_EN11 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 27 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 IR_EN12 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 28 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 IR_EN13 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 29 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 IR_EN14 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 30 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 IR_EN15 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 31 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 IR_EN2 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 18 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 IR_EN3 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 19 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 IR_EN4 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 20 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 IR_EN5 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 21 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 IR_EN6 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 22 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 IR_EN7 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 23 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 IR_EN8 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 24 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 IR_EN9 Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4. 25 1 read-write 0 Disable GPIOx[n] for level-high or low-to-high interrupt #0 1 Enable GPIOx[n] for level-high or low-to-high interrupt #1 GPIOA_IMD GPIOA_IMD GPIO Port A Interrupt Mode Control 0x18 -1 read-write n 0x0 0x0 IMD0 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 0 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 IMD1 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 1 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 IMD10 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 10 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 IMD11 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 11 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 IMD12 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 12 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 IMD13 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 13 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 IMD14 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 14 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 IMD15 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 15 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 IMD2 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 2 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 IMD3 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 3 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 IMD4 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 4 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 IMD5 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 5 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 IMD6 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 6 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 IMD7 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 7 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 IMD8 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 8 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 IMD9 Port [A/B] Edge Or Level Detection Interrupt Control IMD[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the GPIOX_IEN register. If both levels are set no interrupt will occur. 9 1 read-write 0 Edge triggered interrupt #0 1 Level triggered interrupt #1 GPIOA_INDIS GPIOA_INDIS GPIO Port A Pin Digital Input Disable 0x4 -1 read-write n 0x0 0x0 INDIS16 GPIOx Pin[n] OFF Digital Input Path Enable 16 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 INDIS17 GPIOx Pin[n] OFF Digital Input Path Enable 17 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 INDIS18 GPIOx Pin[n] OFF Digital Input Path Enable 18 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 INDIS19 GPIOx Pin[n] OFF Digital Input Path Enable 19 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 INDIS20 GPIOx Pin[n] OFF Digital Input Path Enable 20 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 INDIS21 GPIOx Pin[n] OFF Digital Input Path Enable 21 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 INDIS22 GPIOx Pin[n] OFF Digital Input Path Enable 22 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 INDIS23 GPIOx Pin[n] OFF Digital Input Path Enable 23 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 INDIS24 GPIOx Pin[n] OFF Digital Input Path Enable 24 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 INDIS25 GPIOx Pin[n] OFF Digital Input Path Enable 25 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 INDIS26 GPIOx Pin[n] OFF Digital Input Path Enable 26 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 INDIS27 GPIOx Pin[n] OFF Digital Input Path Enable 27 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 INDIS28 GPIOx Pin[n] OFF Digital Input Path Enable 28 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 INDIS29 GPIOx Pin[n] OFF Digital Input Path Enable 29 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 INDIS30 GPIOx Pin[n] OFF Digital Input Path Enable 30 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 INDIS31 GPIOx Pin[n] OFF Digital Input Path Enable 31 1 read-write 0 Enable IO digital input path (Default) #0 1 Disable IO digital input path (low leakage mode) #1 GPIOA_ISRC GPIOA_ISRC GPIO Port A Interrupt Trigger Source Indicator 0x20 -1 read-write n 0x0 0x0 ISRC0 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 0 1 read-write ISRC1 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 1 1 read-write ISRC10 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 10 1 read-write ISRC11 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 11 1 read-write ISRC12 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 12 1 read-write ISRC13 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 13 1 read-write ISRC14 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 14 1 read-write ISRC15 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 15 1 read-write ISRC2 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 2 1 read-write ISRC3 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 3 1 read-write ISRC4 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 4 1 read-write ISRC5 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 5 1 read-write ISRC6 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 6 1 read-write ISRC7 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 7 1 read-write ISRC8 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 8 1 read-write ISRC9 Port [A/B] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generated an interrupt 0 = No interrupt from GPIOx[n] Write : 1 = Clear the corresponding pending interrupt. 0 = No action 9 1 read-write GPIOA_PIN GPIOA_PIN GPIO Port A Pin Value 0x10 -1 read-only n 0x0 0x0 PIN0 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 0 1 read-only PIN1 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 1 1 read-only PIN10 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 10 1 read-only PIN11 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 11 1 read-only PIN12 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 12 1 read-only PIN13 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 13 1 read-only PIN14 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 14 1 read-only PIN15 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 15 1 read-only PIN2 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 2 1 read-only PIN3 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 3 1 read-only PIN4 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 4 1 read-only PIN5 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 5 1 read-only PIN6 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 6 1 read-only PIN7 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 7 1 read-only PIN8 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 8 1 read-only PIN9 Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin 9 1 read-only GPIOA_PMD GPIOA_PMD GPIO Port A Pin I/O Mode Control 0x0 -1 read-write n 0x0 0x0 PMD0 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 0 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD1 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 2 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD10 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 20 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD11 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 22 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD12 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 24 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD13 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 26 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD14 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 28 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD15 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 30 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD2 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 4 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD3 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 6 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD4 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 8 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD5 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 10 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD6 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 12 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD7 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 14 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD8 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 16 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD9 GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins. 18 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 GPIOB_DBEN 0x54 -1 read-write n 0x0 0x0 GPIOB_DMASK 0x4C -1 read-write n 0x0 0x0 GPIOB_DOUT 0x48 -1 read-write n 0x0 0x0 GPIOB_IEN 0x5C -1 read-write n 0x0 0x0 GPIOB_IMD 0x58 -1 read-write n 0x0 0x0 GPIOB_INDIS 0x44 -1 read-write n 0x0 0x0 GPIOB_ISRC 0x60 -1 read-write n 0x0 0x0 GPIOB_PIN 0x50 -1 read-write n 0x0 0x0 GPIOB_PMD 0x40 -1 read-write n 0x0 0x0 I2C I2C Register Map I2C 0x0 0x0 0x34 registers n ADDR0 ADDR0 I2C Slave address Register0 0x4 -1 read-write n 0x0 0x0 ADDR I2C Address Register The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if any of the addresses are matched. 1 7 read-write GC General Call Function 0 1 read-write 0 Disable General Call Function #0 1 Enable General Call Function #1 ADDR1 0x18 -1 read-write n 0x0 0x0 ADDR2 0x1C -1 read-write n 0x0 0x0 ADDR3 0x20 -1 read-write n 0x0 0x0 ADM0 ADM0 I2C Slave address Mask Register0 0x24 -1 read-write n 0x0 0x0 ADMx1 I2C Address Mask register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison. 1 1 read-write 0 Mask disable #0 1 Mask enable (the received corresponding address bit is don't care.) #1 ADMx2 I2C Address Mask register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison. 2 1 read-write 0 Mask disable #0 1 Mask enable (the received corresponding address bit is don't care.) #1 ADMx3 I2C Address Mask register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison. 3 1 read-write 0 Mask disable #0 1 Mask enable (the received corresponding address bit is don't care.) #1 ADMx4 I2C Address Mask register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison. 4 1 read-write 0 Mask disable #0 1 Mask enable (the received corresponding address bit is don't care.) #1 ADMx5 I2C Address Mask register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison. 5 1 read-write 0 Mask disable #0 1 Mask enable (the received corresponding address bit is don't care.) #1 ADMx6 I2C Address Mask register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison. 6 1 read-write 0 Mask disable #0 1 Mask enable (the received corresponding address bit is don't care.) #1 ADMx7 I2C Address Mask register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison. 7 1 read-write 0 Mask disable #0 1 Mask enable (the received corresponding address bit is don't care.) #1 ADM1 0x28 -1 read-write n 0x0 0x0 ADM2 0x2C -1 read-write n 0x0 0x0 ADM3 0x30 -1 read-write n 0x0 0x0 CLK CLK I2C clock divided Register 0x10 -1 read-write n 0x0 0x0 CLK I2C Clock Divided Register The I2C clock rate bits: Data Baud Rate of I2C = PCLK /(4x(I2C->CLK+1)). 0 8 read-write CON CON I2C Control Register 0x0 -1 read-write n 0x0 0x0 AA Assert Acknowledge Control Bit 1. A slave is acknowledging the address sent from master, 2. The receiver devices are acknowledging the data sent by transmitter. When AA = 0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line. 2 1 read-write EI Enable Interrupt 7 1 read-write 0 Disable interrupt #0 1 Enable interrupt CPU #1 ENSI I2C Controller Enable Bit Set to enable I2C serial function block. 6 1 read-write 0 Disable #0 1 Enable #1 SI I2C Interrupt Flag When a new SIO state is present in the I2C->STATUS register, the SI flag is set by hardware, and if bit EI (I2C->CON[7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one to this bit. 3 1 read-write STA I2C START Control Bit Setting STA to logic 1 will enter master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control Bit In master mode, set STO to transmit a STOP condition to bus. I2C hardware will check the bus condition, when a STOP condition is detected this bit will be cleared by hardware automatically. In slave mode, setting STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode able receive data from the master transmit device. 4 1 read-write DATA DATA I2C DATA Register 0x8 -1 read-write n 0x0 0x0 DATA I2C Data Register During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. 0 8 read-write STATUS STATUS I2C Status Register 0xC -1 read-only n 0x0 0x0 STATUS I2C Status Register The status register of I2C: The three least significant bits are always 0. The five most significant bits contain the status code. There are 26 possible status codes. When I2C->STATUS contains F8H, no serial interrupt is requested. All other I2C->STATUS values correspond to defined I2C states. When each of these states is entered, a status interrupt is requested (SI = 1). A valid status code is present in I2C->STATUS one PCLK cycle after SI is set by hardware and is still present one PCLK cycle after SI has been reset by software. In addition, states 00H stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an illegal position in the frame. Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. 0 8 read-only TOC TOC I2C Time out control Register 0x14 -1 read-write n 0x0 0x0 DIV4 Time-Out Counter Input Clock Divide By 4 When enabled, the time-out clock is PCLK/4. 1 1 read-write 0 Disable #0 1 Enable #1 ENTI Time-out Counter Control Bit When enabled, the 14 bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared. 2 1 read-write 0 Disable #0 1 Enable #1 TIF Time-Out Flag 0 1 read-write 0 No time-out #0 1 Time-out flag is set by H/W. It can interrupt CPU. Write 1 to clear. #1 I2S I2S Register Map I2S 0x0 0x0 0x18 registers n CLKDIV CLKDIV I2S Clock Divider Register 0x4 -1 read-write n 0x0 0x0 BCLK_DIV Bit Clock Divider If I2S operates in master mode, bit clock is provided by ISD9160. Software can program these bits to generate bit clock frequency for the desired sample rate. For sample rate Fs, the desired bit clock frequency is: F(BCLK) = Fs x Word_width_in_bytes x 16 For example if Fs = 16kHz, and word width is 2-bytes (16bit) then desired bit clock frequency is 512kHz. The bit clock frequency is given by: F(BCLK) = F(I2S_CLK) / 2x(BCLK_DIV+1) Or, BCLK_DIV = F(I2S_CLK) / (2 x F(BCLK)) -1 So if F(I2S_CLK) = HCLK = 49.152MHz , desired F(BCLK) = 512kHz then BCLK_DIV = 47 8 8 read-write MCLK_DIV Master Clock Divider ISD9160 can generate a master clock to synchronously drive an external audio device. If MCLK_DIV is set to 0, MCLK is the same as I2S_CLK clock input, otherwise MCLK frequency is given by: F(MCLK) = F(I2S_CLK) / (2xMCLK_DIV) Or, MCLK_DIV = F(I2S_CLK) / (2 x F(MCLK)) If the desired MCLK frequency is 254Fs and Fs = 16kHz then MCLK_DIV = 6 0 3 read-write CON CON I2S Control Register 0x0 -1 read-write n 0x0 0x0 CLR_RXFIFO Clear Receive FIFO Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXFIFO_LEVEL[3:0] returns to zero and receive FIFO becomes empty. This bit is cleared by hardware automatically when clear operation complete. 19 1 read-write CLR_TXFIFO Clear Transmit FIFO Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXFIFO_LEVEL[3:0] returns to zero and transmit FIFO becomes empty. Data in transmit FIFO is not changed. This bit is cleared by hardware automatically when clear operation complete. 18 1 read-write FORMAT Data format See Figure 561 and Figure 562 for timing differences. 7 1 read-write 0 I2S data format #0 1 MSB justified data format #1 I2SEN Enable I2S Controller 0 1 read-write 0 Disable #0 1 Enable #1 LCHZCEN Left Channel Zero Cross Detect Enable If this bit is set to 1, when left channel data sign bit changes, or data bits are all zero, the LZCF flag in I2S_STATUS register will be set to 1. 17 1 read-write 0 Disable left channel zero cross detect #0 1 Enable left channel zero cross detect #1 MCLKEN Master Clock Enable The ISD9160 can generate a master clock signal to an external audio CODEC to synchronize the audio devices. If audio devices are not synchronous, then data will be periodically corrupted. Software needs to implement a way to drop/repeat or interpolate samples in a jitter buffer if devices are not synchronized. The master clock frequency is determined by the CLKDIV.MCLK_DIV[2:0] register. 15 1 read-write 0 Disable master clock #0 1 Enable master clock #1 MONO Monaural data This parameter sets whether mono or stereo data is processed. See Figure 563 for details of how data is formatted in transmit and receive FIFO. 6 1 read-write 0 Data is stereo format #0 1 Data is monaural format #1 MUTE Transmit Mute Enable 3 1 read-write 0 Transmit data is shifted from FIFO #0 1 Transmit channel zero #1 RCHZCEN Right Channel Zero Cross Detect Enable If this bit is set to 1, when right channel data sign bit changes, or data bits are all zero, the RZCF flag in I2S_STATUS register will be set to 1. 16 1 read-write 0 Disable right channel zero cross detect #0 1 Enable right channel zero cross detect #1 RXDMA Enable Receive DMA When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty. 21 1 read-write 0 Disable RX DMA #0 1 Enable RX DMA #1 RXEN Receive Enable 2 1 read-write 0 Disable data receive #0 1 Enable data receive #1 RXTH Receive FIFO Threshold Level When received data word(s) in buffer is equal or higher than threshold level then RXTHI flag is set. 12 3 read-write SLAVE Slave Mode I2S can operate as a master or slave. For master mode, I2S_BCLK and I2S_FS pins are outputs and send bit clock and frame sync from ISD9160. In slave mode, I2S_BCLK and I2S_FS pins are inputs and bit clock and frame sync are received from external audio device. 8 1 read-write 0 Master mode #0 1 Slave mode #1 TXDMA Enable Transmit DMA When TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full. 20 1 read-write 0 Disable TX DMA #0 1 Enable TX DMA #1 TXEN Transmit Enable 1 1 read-write 0 Disable data transmit #0 1 Enable data transmit #1 TXTH Transmit FIFO Threshold Level If remaining data words in transmit FIFO less than or equal to the threshold level then TXTHI flag is set. 9 3 read-write WORDWIDTH Word Width This parameter sets the word width of audio data. See Figure 563 for details of how data is formatted in transmit and receive FIFO. 4 2 read-write 0 data is 8 bit #00 1 data is 16 bit #01 2 data is 24 bit #10 3 data is 32 bit #11 IE IE I2S Interrupt Enable Register 0x8 -1 read-write n 0x0 0x0 LZCIE Left Channel Zero Cross Interrupt Enable Interrupt will occur if this bit is set to 1 and left channel has zero cross event 12 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 RXOVFIE Receive FIFO Overflow Interrupt Enable 1 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 RXTHIE Receive FIFO Threshold Level Interrupt Interrupt occurs if this bit is set to 1 and data words in receive FIFO is greater than or equal to RXTH[2:0]. 2 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 RXUDFIE Receive FIFO Underflow Interrupt Enable If software read receive FIFO when it is empty then RXUDF flag in I2SSTATUS register is set to 1. 0 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 RZCIE Right Channel Zero Cross Interrupt Enable Interrupt will occur if this bit is set to 1 and right channel has zero cross event 11 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 TXOVFIE Transmit FIFO Overflow Interrupt Enable Interrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1 9 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 TXTHIE Transmit FIFO Threshold Level Interrupt Enable Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[2:0]. 10 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 TXUDFIE Transmit FIFO Underflow Interrupt Enable Interrupt occur if this bit is set to 1 and transmit FIFO underflow flag is set to 1. 8 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 RXFIFO RXFIFO I2S Receive FIFO Register 0x14 -1 read-only n 0x0 0x0 RXFIFO Receive FIFO Register (Read Only) A read of this register will pop data from the receive FIFO. The receive FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S->STATUS.RX_LEVEL. 0 32 read-only STATUS STATUS I2S Status Register 0xC -1 read-write n 0x0 0x0 I2SINT I2S Interrupt (Read Only) This bit is set if any enabled I2S interrupt is active. 0 1 read-only 0 No I2S interrupt #0 1 I2S interrupt active #1 I2SRXINT I2S Receive Interrupt (Read Only) This indicates that there is an active receive interrupt source. This could be RXOVF, RXUDF or RXTHF if corresponding interrupt enable bits are active. To clear interrupt the corresponding source(s) must be cleared. 1 1 read-only 0 No receive interrupt #0 1 Receive interrupt occurred #1 I2STXINT I2S Transmit Interrupt (Read Only) This indicates that there is an active transmit interrupt source. This could be TXOVF, TXUDF, TXTHF, LZCF or RZCF if corresponding interrupt enable bits are active. To clear interrupt the corresponding source(s) must be cleared. 2 1 read-only 0 No transmit interrupt #0 1 Transmit interrupt occurred #1 LZCF Left channel zero cross flag (write '1' to clear, or clear LCHZCEN) 23 1 read-write 0 No zero cross detected #0 1 Left channel zero cross is detected #1 RIGHT Right Channel Active (Read Only) This bit indicates current data being transmitted/received belongs to right channel 3 1 read-only 0 Left channel #0 1 Right channel #1 RXEMPTY Receive FIFO empty (Read Only) This is set when receive FIFO is empty. 12 1 read-only 0 Not empty #0 1 Empty #1 RXFULL Receive FIFO full (Read Only) This bit is set when receive FIFO is full. 11 1 read-only 0 Not full #0 1 Full #1 RXOVF Receive FIFO Overflow Flag (Write '1' to clear) This flag is set if I2S controller writes to receive FIFO when it is full. Audio data is lost. 9 1 read-write 0 No overflow #0 1 Overflow #1 RXTHF Receive FIFO Threshold Flag (Read Only) When data word(s) in receive FIFO is greater than or equal to threshold value set in RXTH[2:0] the RXTHF bit becomes to 1. It remains set until receive FIFO level is less than RXTH[2:0]. It is cleared by reading RXFIFO until threshold satisfied. 10 1 read-only 0 Data word(s) in FIFO is less than threshold level #0 1 Data word(s) in FIFO is greater than or equal to threshold level #1 RXUDF Receive FIFO Underflow Flag (Write '1' to clear) This flag is set if attempt is made to read receive FIFO while it is empty. 8 1 read-write 0 No underflow #0 1 Underflow #1 RX_LEVEL Receive FIFO level (Read Only) 24 4 read-only RZCF Right channel zero cross flag (write '1' to clear, or clear RCHZCEN) 22 1 read-write 0 No zero cross #0 1 Right channel zero cross is detected #1 TXBUSY Transmit Busy (Read Only) This bit is cleared when all data in transmit FIFO and Tx shift register is shifted out. It is set when first data is loaded to Tx shift register. 21 1 read-only 0 Transmit shift register is empty #0 1 Transmit shift register is busy #1 TXEMPTY Transmit FIFO Empty (Read Only) This is set when transmit FIFO is empty. 20 1 read-only 0 Not empty #0 1 Empty #1 TXFULL Transmit FIFO Full (Read Only) This bit is set when transmit FIFO is full. 19 1 read-only 0 Not full #0 1 Full #1 TXOVF Transmit FIFO Overflow Flag (Write '1' to clear) This flag is set if data is written to transmit FIFO when it is full. 17 1 read-write 0 No overflow #0 1 Overflow #1 TXTHF Transmit FIFO Threshold Flag (Read Only) When data word(s) in transmit FIFO is less than or equal to the threshold value set in TXTH[2:0] the TXTHF bit becomes to 1. It remains set until transmit FIFO level is greater than TXTH[2:0]. Cleared by writing to TXFIFO register until threshold exceeded. 18 1 read-only 0 Data word(s) in FIFO is greater than threshold level #0 1 Data word(s) in FIFO is less than or equal to threshold level #1 TXUDF Transmit FIFO underflow flag (Write '1' to clear) This flag is set if I2S controller requests data when transmit FIFO is empty. 16 1 read-write 0 No underflow #0 1 Underflow #1 TX_LEVEL Transmit FIFO level (Read Only) 28 4 read-only TXFIFO TXFIFO I2S Transmit FIFO Register 0x10 -1 write-only n 0x0 0x0 TXFIFO Transmit FIFO Register (Write Only) A write to this register pushes data onto the transmit FIFO. The transmit FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S->STATUS.TX_LEVEL. 0 32 write-only INT INT Register Map INT 0x0 0x0 0x88 registers n IRQ0_SRC IRQ0_SRC IRQ0 (BOD) Interrupt Source Identity Register 0x0 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: BOD_INT 0 3 read-only IRQ10_SRC IRQ10_SRC IRQ10 (Reserved) Interrupt Source Identity Register 0x28 -1 read-only n 0x0 0x0 IRQ11_SRC IRQ11_SRC IRQ11 (Reserved) Interrupt Source Identity Register 0x2C -1 read-only n 0x0 0x0 IRQ12_SRC IRQ12_SRC IRQ12 (UART0) Interrupt Source Identity Register 0x30 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: UART0_INT 0 3 read-only IRQ13_SRC IRQ13_SRC IRQ13 (Reserved) Interrupt Source Identity Register 0x34 -1 read-only n 0x0 0x0 IRQ14_SRC IRQ14_SRC IRQ14 (SPI0) Interrupt Source Identity Register 0x38 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: SPI0_INT 0 3 read-only IRQ15_SRC IRQ15_SRC IRQ15 (Reserved) Interrupt Source Identity Register 0x3C -1 read-only n 0x0 0x0 IRQ16_SRC IRQ16_SRC IRQ16 (Reserved) Interrupt Source Identity Register 0x40 -1 read-only n 0x0 0x0 IRQ17_SRC IRQ17_SRC IRQ17 (Reserved) Interrupt Source Identity Register 0x44 -1 read-only n 0x0 0x0 IRQ18_SRC IRQ18_SRC IRQ18 (I2C0) Interrupt Source Identity Register 0x48 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: I2C0_INT 0 3 read-only IRQ19_SRC IRQ19_SRC IRQ19 (Reserved) Interrupt Source Identity Register 0x4C -1 read-only n 0x0 0x0 IRQ1_SRC IRQ1_SRC IRQ1 (WDT) Interrupt Source Identity Register 0x4 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: WDT_INT 0 3 read-only IRQ20_SRC IRQ20_SRC IRQ20 (Reserved) Interrupt Source Identity Register 0x50 -1 read-only n 0x0 0x0 IRQ21_SRC IRQ21_SRC IRQ21 (TALARM) Interrupt Source Identity Register 0x54 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: TALARM_INT 0 3 read-only IRQ22_SRC IRQ22_SRC IRQ22 (Reserved ) Interrupt Source Identity Register 0x58 -1 read-only n 0x0 0x0 IRQ23_SRC IRQ23_SRC IRQ23 (Reserved) Interrupt Source Identity Register 0x5C -1 read-only n 0x0 0x0 IRQ24_SRC IRQ24_SRC IRQ24 (Reserved) Interrupt Source Identity Register 0x60 -1 read-only n 0x0 0x0 IRQ25_SRC IRQ25_SRC IRQ25 (ACMP) Interrupt Source Identity Register 0x64 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: TALARM_INT 0 3 read-only IRQ26_SRC IRQ26_SRC IRQ26 (PDMA) Interrupt Source Identity Register 0x68 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: PDMA_INT 0 3 read-only IRQ27_SRC IRQ27_SRC IRQ27 (I2S) Interrupt Source Identity Register 0x6C -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: I2S_INT 0 3 read-only IRQ28_SRC IRQ28_SRC IRQ28 (CAPS) Interrupt Source Identity Register 0x70 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: CAPS_INT 0 3 read-only IRQ29_SRC IRQ29_SRC IRQ29 (ADC) Interrupt Source Identity Register 0x74 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: ADC_INT 0 3 read-only IRQ2_SRC IRQ2_SRC IRQ2 (EINT0) Interrupt Source Identity Register 0x8 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: INT0_INT 0 3 read-only IRQ30_SRC IRQ30_SRC IRQ30 (Reserved) Interrupt Source Identity Register 0x78 -1 read-only n 0x0 0x0 IRQ31_SRC IRQ31_SRC IRQ31 (RTC) Interrupt Source Identity Register 0x7C -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: RTC_INT 0 3 read-only IRQ3_SRC IRQ3_SRC IRQ3 (EINT1) Interrupt Source Identity Register 0xC -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: INT0_INT 0 3 read-only IRQ4_SRC IRQ4_SRC IRQ4 (GPA/B) Interrupt Source Identity Register 0x10 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: GPB_INT Bit0: GPA_INT 0 3 read-only IRQ5_SRC IRQ5_SRC IRQ5 (ALC) Interrupt Source Identity Register 0x14 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: ALC_INT 0 3 read-only IRQ6_SRC IRQ6_SRC IRQ6 (PWMA) Interrupt Source Identity Register 0x18 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: PWMA_INT 0 3 read-only IRQ7_SRC IRQ7_SRC IRQ7 (Reserved) Interrupt Source Identity Register 0x1C -1 read-only n 0x0 0x0 IRQ8_SRC IRQ8_SRC IRQ8 (TMR0) Interrupt Source Identity Register 0x20 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: TMR0_INT 0 3 read-only IRQ9_SRC IRQ9_SRC IRQ9 (TMR1) Interrupt Source Identity Register 0x24 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: TMR1_INT 0 3 read-only MCU_IRQ MCU_IRQ MCU IRQ Number Identify Register 0x84 -1 read-write n 0x0 0x0 MCU_IRQ MCU IRQ Source Test Mode In Normal mode (NMI_SEL register bit [7] = 0) The device collects interrupts from each peripheral and synchronizes them to interrupt the Cortex-M0. In Test mode (NMI_SEL register bit [7] = 1), the interrupts from peripherals are blocked, and the interrupts are replaces by MCU_IRQ[31:0]. When MCU_IRQ[n] is 0 : Writing MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 NVIC[n]. When MCU_IRQ[n] is 1 (meaning an interrupt is asserted) writing MCU_bit[n] '1' will clear the interrupt Writing MCU_IRQ[n] 0 : has no effect. 0 32 read-write NMI_SEL NMI_SEL NMI Source Interrupt Select Control Register 0x80 -1 read-write n 0x0 0x0 IRQ_TM IRQ Test Mode If set to 1 then peripheral IRQ signals (0-31) are replaced by the value in the MCU_IRQ register. This is a protected register to program first issue the unlock sequence (see Protected Register Lock Key Register (REGLOCK)) 7 1 read-write NMI_SEL NMI Source Interrupt Select The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0] The NMI_SEL bit[4:0] used to select the NMI interrupt source 0 5 read-write PDMA0 PDMA Register Map PDMA 0x0 0x0 0x28 registers n BCRn BCRn PDMA Transfer Byte Count Register of Channel n 0xC -1 read-write n 0x0 0x0 BCR PDMA Transfer Byte Count Register This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF. Note: When in memory-to-memory (CSR.MODE_SEL = 00b) mode, the transfer byte count must be word aligned, that is multiples of 4bytes. 0 16 read-write CBCRn CBCRn PDMA Current Byte Count Register of Channel n 0x1C -1 read-only n 0x0 0x0 CBCR PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs 0 16 read-only CDARn CDARn PDMA Current Destination Address Register of Channel n 0x18 -1 read-only n 0x0 0x0 CDAR PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only CSARn CSARn PDMA Current Source Address Register of Channel n 0x14 -1 read-only n 0x0 0x0 CSAR PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only CSRn CSRn PDMA Control Register of Channel n 0x0 -1 read-write n 0x0 0x0 APB_TWS Peripheral Transfer Width Select This parameter determines the data width to be transferred each PDMA transfer operation. Note: This field is meaningful only when MODE_SEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB). 19 2 read-write 0 One word (32 bits) is transferred for every PDMA operation #00 1 One byte (8 bits) is transferred for every PDMA operation #01 2 One half-word (16 bits) is transferred for every PDMA operation #10 3 Reserved #11 DAD_SEL Destination Address Select This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 6 2 read-write 0 Transfer Destination Address is incremented #00 1 Reserved #01 2 Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input) #10 3 Transfer Destination Address is wrapped. When CBCR (Current Byte Count) equals zero, the CDAR (Current Destination Address) and CBCR registers will be reloaded from the DAR (Destination Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 MODE_SEL PDMA Mode Select This parameter selects to transfer direction of the PDMA channel. Possible values are: 2 2 read-write 0 Memory to Memory mode (SRAM-to-SRAM) #00 1 IP to Memory mode (APB-to-SRAM) #01 2 Memory to IP mode (SRAM-to-APB) #10 PDMACEN PDMA Channel Enable Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. Note: SW_RST will clear this bit. 0 1 read-write SAD_SEL Source Address Select This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 4 2 read-write 0 Transfer Source address is incremented #00 1 Reserved #01 2 Transfer Source address is fixed #10 3 Transfer Source address is wrapped. When CBCR (Current Byte Count) equals zero, the CSAR (Current Source Address) and CBCR registers will be reloaded from the SAR (Source Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN = 0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 SW_RST Software Engine Reset 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles #1 TRIG_EN Trigger Enable - Start a PDMA operation Note: When PDMA transfer completed, this bit will be cleared automatically. If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again. 23 1 read-write 0 Write: no effect. Read: Idle/Finished #0 1 Enable PDMA data read or write transfer #1 WRA_INT_SEL Wrap Interrupt Select x1xx: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when half each PDMA transfer is complete. For example if BCR = 32 then an interrupt could be generated when 16 bytes were sent. xxx1: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when each PDMA transfer is wrapped. For example if BCR = 32 then an interrupt could be generated when 32 bytes were sent and PDMA wraps around. x1x1: Both half and w interrupts generated. 12 4 read-write DARn DARn PDMA Transfer Destination Address Register of Channel n 0x8 -1 read-write n 0x0 0x0 DAR PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned. 0 32 read-write IERn IERn PDMA Interrupt Enable Control Register of Channel n 0x20 -1 read-write n 0x0 0x0 BLKD_IE PDMA Transfer Done Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete. 1 1 read-write 0 Disable PDMA transfer done interrupt generation #0 1 Enable PDMA transfer done interrupt generation #1 TABORT_IE PDMA Read/Write Target Abort Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation. 0 1 read-write 0 Disable PDMA transfer target abort interrupt generation #0 1 Enable PDMA transfer target abort interrupt generation #1 WAR_IE Wraparound Interrupt Enable If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WRA_INT_SEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA. 2 1 read-write 0 Disable Wraparound PDMA interrupt generation #0 1 Enable Wraparound interrupt generation #1 ISRn ISRn PDMA Interrupt Status Register of Channel n 0x24 -1 read-write n 0x0 0x0 BLKD_IF Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit. 1 1 read-write 0 Transfer ongoing or Idle #0 1 Transfer Complete #1 INTR Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel. 31 1 read-only TABORT_IF PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. NOTE: This bit is cleared by writing 1 to itself. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 WAR_IF Wrap Around Transfer Byte Count Interrupt Flag These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits. 0001 = Current transfer finished flag (CBCR == 0). 0100 = Current transfer half complete flag (CBCR == BCR/2). 8 4 read-write POINTn POINTn PDMA Internal Buffer Pointer Register of Channel n 0x10 -1 read-only n 0x0 0x0 POINT PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction. 0 4 read-only SARn SARn PDMA Transfer Source Address Register of Channel n 0x4 -1 read-write n 0x0 0x0 SAR PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned. 0 32 read-write PDMA1 PDMA Register Map PDMA 0x0 0x0 0x28 registers n BCRn BCRn PDMA Transfer Byte Count Register of Channel n 0xC -1 read-write n 0x0 0x0 BCR PDMA Transfer Byte Count Register This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF. Note: When in memory-to-memory (CSR.MODE_SEL = 00b) mode, the transfer byte count must be word aligned, that is multiples of 4bytes. 0 16 read-write CBCRn CBCRn PDMA Current Byte Count Register of Channel n 0x1C -1 read-only n 0x0 0x0 CBCR PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs 0 16 read-only CDARn CDARn PDMA Current Destination Address Register of Channel n 0x18 -1 read-only n 0x0 0x0 CDAR PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only CSARn CSARn PDMA Current Source Address Register of Channel n 0x14 -1 read-only n 0x0 0x0 CSAR PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only CSRn CSRn PDMA Control Register of Channel n 0x0 -1 read-write n 0x0 0x0 APB_TWS Peripheral Transfer Width Select This parameter determines the data width to be transferred each PDMA transfer operation. Note: This field is meaningful only when MODE_SEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB). 19 2 read-write 0 One word (32 bits) is transferred for every PDMA operation #00 1 One byte (8 bits) is transferred for every PDMA operation #01 2 One half-word (16 bits) is transferred for every PDMA operation #10 3 Reserved #11 DAD_SEL Destination Address Select This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 6 2 read-write 0 Transfer Destination Address is incremented #00 1 Reserved #01 2 Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input) #10 3 Transfer Destination Address is wrapped. When CBCR (Current Byte Count) equals zero, the CDAR (Current Destination Address) and CBCR registers will be reloaded from the DAR (Destination Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 MODE_SEL PDMA Mode Select This parameter selects to transfer direction of the PDMA channel. Possible values are: 2 2 read-write 0 Memory to Memory mode (SRAM-to-SRAM) #00 1 IP to Memory mode (APB-to-SRAM) #01 2 Memory to IP mode (SRAM-to-APB) #10 PDMACEN PDMA Channel Enable Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. Note: SW_RST will clear this bit. 0 1 read-write SAD_SEL Source Address Select This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 4 2 read-write 0 Transfer Source address is incremented #00 1 Reserved #01 2 Transfer Source address is fixed #10 3 Transfer Source address is wrapped. When CBCR (Current Byte Count) equals zero, the CSAR (Current Source Address) and CBCR registers will be reloaded from the SAR (Source Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN = 0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 SW_RST Software Engine Reset 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles #1 TRIG_EN Trigger Enable - Start a PDMA operation Note: When PDMA transfer completed, this bit will be cleared automatically. If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again. 23 1 read-write 0 Write: no effect. Read: Idle/Finished #0 1 Enable PDMA data read or write transfer #1 WRA_INT_SEL Wrap Interrupt Select x1xx: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when half each PDMA transfer is complete. For example if BCR = 32 then an interrupt could be generated when 16 bytes were sent. xxx1: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when each PDMA transfer is wrapped. For example if BCR = 32 then an interrupt could be generated when 32 bytes were sent and PDMA wraps around. x1x1: Both half and w interrupts generated. 12 4 read-write DARn DARn PDMA Transfer Destination Address Register of Channel n 0x8 -1 read-write n 0x0 0x0 DAR PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned. 0 32 read-write IERn IERn PDMA Interrupt Enable Control Register of Channel n 0x20 -1 read-write n 0x0 0x0 BLKD_IE PDMA Transfer Done Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete. 1 1 read-write 0 Disable PDMA transfer done interrupt generation #0 1 Enable PDMA transfer done interrupt generation #1 TABORT_IE PDMA Read/Write Target Abort Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation. 0 1 read-write 0 Disable PDMA transfer target abort interrupt generation #0 1 Enable PDMA transfer target abort interrupt generation #1 WAR_IE Wraparound Interrupt Enable If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WRA_INT_SEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA. 2 1 read-write 0 Disable Wraparound PDMA interrupt generation #0 1 Enable Wraparound interrupt generation #1 ISRn ISRn PDMA Interrupt Status Register of Channel n 0x24 -1 read-write n 0x0 0x0 BLKD_IF Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit. 1 1 read-write 0 Transfer ongoing or Idle #0 1 Transfer Complete #1 INTR Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel. 31 1 read-only TABORT_IF PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. NOTE: This bit is cleared by writing 1 to itself. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 WAR_IF Wrap Around Transfer Byte Count Interrupt Flag These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits. 0001 = Current transfer finished flag (CBCR == 0). 0100 = Current transfer half complete flag (CBCR == BCR/2). 8 4 read-write POINTn POINTn PDMA Internal Buffer Pointer Register of Channel n 0x10 -1 read-only n 0x0 0x0 POINT PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction. 0 4 read-only SARn SARn PDMA Transfer Source Address Register of Channel n 0x4 -1 read-write n 0x0 0x0 SAR PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned. 0 32 read-write PDMA2 PDMA Register Map PDMA 0x0 0x0 0x28 registers n BCRn BCRn PDMA Transfer Byte Count Register of Channel n 0xC -1 read-write n 0x0 0x0 BCR PDMA Transfer Byte Count Register This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF. Note: When in memory-to-memory (CSR.MODE_SEL = 00b) mode, the transfer byte count must be word aligned, that is multiples of 4bytes. 0 16 read-write CBCRn CBCRn PDMA Current Byte Count Register of Channel n 0x1C -1 read-only n 0x0 0x0 CBCR PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs 0 16 read-only CDARn CDARn PDMA Current Destination Address Register of Channel n 0x18 -1 read-only n 0x0 0x0 CDAR PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only CSARn CSARn PDMA Current Source Address Register of Channel n 0x14 -1 read-only n 0x0 0x0 CSAR PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only CSRn CSRn PDMA Control Register of Channel n 0x0 -1 read-write n 0x0 0x0 APB_TWS Peripheral Transfer Width Select This parameter determines the data width to be transferred each PDMA transfer operation. Note: This field is meaningful only when MODE_SEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB). 19 2 read-write 0 One word (32 bits) is transferred for every PDMA operation #00 1 One byte (8 bits) is transferred for every PDMA operation #01 2 One half-word (16 bits) is transferred for every PDMA operation #10 3 Reserved #11 DAD_SEL Destination Address Select This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 6 2 read-write 0 Transfer Destination Address is incremented #00 1 Reserved #01 2 Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input) #10 3 Transfer Destination Address is wrapped. When CBCR (Current Byte Count) equals zero, the CDAR (Current Destination Address) and CBCR registers will be reloaded from the DAR (Destination Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 MODE_SEL PDMA Mode Select This parameter selects to transfer direction of the PDMA channel. Possible values are: 2 2 read-write 0 Memory to Memory mode (SRAM-to-SRAM) #00 1 IP to Memory mode (APB-to-SRAM) #01 2 Memory to IP mode (SRAM-to-APB) #10 PDMACEN PDMA Channel Enable Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. Note: SW_RST will clear this bit. 0 1 read-write SAD_SEL Source Address Select This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 4 2 read-write 0 Transfer Source address is incremented #00 1 Reserved #01 2 Transfer Source address is fixed #10 3 Transfer Source address is wrapped. When CBCR (Current Byte Count) equals zero, the CSAR (Current Source Address) and CBCR registers will be reloaded from the SAR (Source Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN = 0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 SW_RST Software Engine Reset 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles #1 TRIG_EN Trigger Enable - Start a PDMA operation Note: When PDMA transfer completed, this bit will be cleared automatically. If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again. 23 1 read-write 0 Write: no effect. Read: Idle/Finished #0 1 Enable PDMA data read or write transfer #1 WRA_INT_SEL Wrap Interrupt Select x1xx: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when half each PDMA transfer is complete. For example if BCR = 32 then an interrupt could be generated when 16 bytes were sent. xxx1: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when each PDMA transfer is wrapped. For example if BCR = 32 then an interrupt could be generated when 32 bytes were sent and PDMA wraps around. x1x1: Both half and w interrupts generated. 12 4 read-write DARn DARn PDMA Transfer Destination Address Register of Channel n 0x8 -1 read-write n 0x0 0x0 DAR PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned. 0 32 read-write IERn IERn PDMA Interrupt Enable Control Register of Channel n 0x20 -1 read-write n 0x0 0x0 BLKD_IE PDMA Transfer Done Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete. 1 1 read-write 0 Disable PDMA transfer done interrupt generation #0 1 Enable PDMA transfer done interrupt generation #1 TABORT_IE PDMA Read/Write Target Abort Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation. 0 1 read-write 0 Disable PDMA transfer target abort interrupt generation #0 1 Enable PDMA transfer target abort interrupt generation #1 WAR_IE Wraparound Interrupt Enable If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WRA_INT_SEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA. 2 1 read-write 0 Disable Wraparound PDMA interrupt generation #0 1 Enable Wraparound interrupt generation #1 ISRn ISRn PDMA Interrupt Status Register of Channel n 0x24 -1 read-write n 0x0 0x0 BLKD_IF Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit. 1 1 read-write 0 Transfer ongoing or Idle #0 1 Transfer Complete #1 INTR Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel. 31 1 read-only TABORT_IF PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. NOTE: This bit is cleared by writing 1 to itself. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 WAR_IF Wrap Around Transfer Byte Count Interrupt Flag These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits. 0001 = Current transfer finished flag (CBCR == 0). 0100 = Current transfer half complete flag (CBCR == BCR/2). 8 4 read-write POINTn POINTn PDMA Internal Buffer Pointer Register of Channel n 0x10 -1 read-only n 0x0 0x0 POINT PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction. 0 4 read-only SARn SARn PDMA Transfer Source Address Register of Channel n 0x4 -1 read-write n 0x0 0x0 SAR PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned. 0 32 read-write PDMA3 PDMA Register Map PDMA 0x0 0x0 0x28 registers n BCRn BCRn PDMA Transfer Byte Count Register of Channel n 0xC -1 read-write n 0x0 0x0 BCR PDMA Transfer Byte Count Register This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF. Note: When in memory-to-memory (CSR.MODE_SEL = 00b) mode, the transfer byte count must be word aligned, that is multiples of 4bytes. 0 16 read-write CBCRn CBCRn PDMA Current Byte Count Register of Channel n 0x1C -1 read-only n 0x0 0x0 CBCR PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs 0 16 read-only CDARn CDARn PDMA Current Destination Address Register of Channel n 0x18 -1 read-only n 0x0 0x0 CDAR PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only CSARn CSARn PDMA Current Source Address Register of Channel n 0x14 -1 read-only n 0x0 0x0 CSAR PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only CSRn CSRn PDMA Control Register of Channel n 0x0 -1 read-write n 0x0 0x0 APB_TWS Peripheral Transfer Width Select This parameter determines the data width to be transferred each PDMA transfer operation. Note: This field is meaningful only when MODE_SEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB). 19 2 read-write 0 One word (32 bits) is transferred for every PDMA operation #00 1 One byte (8 bits) is transferred for every PDMA operation #01 2 One half-word (16 bits) is transferred for every PDMA operation #10 3 Reserved #11 DAD_SEL Destination Address Select This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 6 2 read-write 0 Transfer Destination Address is incremented #00 1 Reserved #01 2 Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input) #10 3 Transfer Destination Address is wrapped. When CBCR (Current Byte Count) equals zero, the CDAR (Current Destination Address) and CBCR registers will be reloaded from the DAR (Destination Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 MODE_SEL PDMA Mode Select This parameter selects to transfer direction of the PDMA channel. Possible values are: 2 2 read-write 0 Memory to Memory mode (SRAM-to-SRAM) #00 1 IP to Memory mode (APB-to-SRAM) #01 2 Memory to IP mode (SRAM-to-APB) #10 PDMACEN PDMA Channel Enable Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. Note: SW_RST will clear this bit. 0 1 read-write SAD_SEL Source Address Select This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 4 2 read-write 0 Transfer Source address is incremented #00 1 Reserved #01 2 Transfer Source address is fixed #10 3 Transfer Source address is wrapped. When CBCR (Current Byte Count) equals zero, the CSAR (Current Source Address) and CBCR registers will be reloaded from the SAR (Source Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN = 0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 SW_RST Software Engine Reset 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles #1 TRIG_EN Trigger Enable - Start a PDMA operation Note: When PDMA transfer completed, this bit will be cleared automatically. If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again. 23 1 read-write 0 Write: no effect. Read: Idle/Finished #0 1 Enable PDMA data read or write transfer #1 WRA_INT_SEL Wrap Interrupt Select x1xx: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when half each PDMA transfer is complete. For example if BCR = 32 then an interrupt could be generated when 16 bytes were sent. xxx1: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when each PDMA transfer is wrapped. For example if BCR = 32 then an interrupt could be generated when 32 bytes were sent and PDMA wraps around. x1x1: Both half and w interrupts generated. 12 4 read-write DARn DARn PDMA Transfer Destination Address Register of Channel n 0x8 -1 read-write n 0x0 0x0 DAR PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned. 0 32 read-write IERn IERn PDMA Interrupt Enable Control Register of Channel n 0x20 -1 read-write n 0x0 0x0 BLKD_IE PDMA Transfer Done Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete. 1 1 read-write 0 Disable PDMA transfer done interrupt generation #0 1 Enable PDMA transfer done interrupt generation #1 TABORT_IE PDMA Read/Write Target Abort Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation. 0 1 read-write 0 Disable PDMA transfer target abort interrupt generation #0 1 Enable PDMA transfer target abort interrupt generation #1 WAR_IE Wraparound Interrupt Enable If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WRA_INT_SEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA. 2 1 read-write 0 Disable Wraparound PDMA interrupt generation #0 1 Enable Wraparound interrupt generation #1 ISRn ISRn PDMA Interrupt Status Register of Channel n 0x24 -1 read-write n 0x0 0x0 BLKD_IF Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit. 1 1 read-write 0 Transfer ongoing or Idle #0 1 Transfer Complete #1 INTR Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel. 31 1 read-only TABORT_IF PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. NOTE: This bit is cleared by writing 1 to itself. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 WAR_IF Wrap Around Transfer Byte Count Interrupt Flag These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits. 0001 = Current transfer finished flag (CBCR == 0). 0100 = Current transfer half complete flag (CBCR == BCR/2). 8 4 read-write POINTn POINTn PDMA Internal Buffer Pointer Register of Channel n 0x10 -1 read-only n 0x0 0x0 POINT PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction. 0 4 read-only SARn SARn PDMA Transfer Source Address Register of Channel n 0x4 -1 read-write n 0x0 0x0 SAR PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned. 0 32 read-write PDMA_GCR PDMA Register Map PDMA 0x0 0x0 0x8 registers n 0xC 0x4 registers n GCR GCR PDMA Global Control Register 0x0 -1 read-write n 0x0 0x0 HCLK_EN PDMA Controller Channel Clock Enable Control To enable clock for channel n HCLK_EN[n] must be set. HCLK_EN[n] = 1: Enable Channel n clock HCLK_EN[n] = 0: Disable Channel n clock 8 4 read-write PDMA_RST PDMA Software Reset Note: This bit can reset all channels (global reset). 0 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will auto clear after several clock cycles #1 GCRISR GCRISR PDMA Global Interrupt Status Register 0xC -1 read-only n 0x0 0x0 GCRISR Interrupt Pin Status (Read Only) GCRISR[n] is the interrupt status of PDMA channel n. 0 4 read-only PDSSR PDSSR PDMA Service Selection Control Register 0x4 -1 read-write n 0x0 0x0 ADC_RXSEL PDMA ADC Receive Selection This field defines which PDMA channel is connected to ADC peripheral receive (PDMA source) request. 8 4 read-write DPWM_TXSEL PDMA DPWM Transmit Selection This field defines which PDMA channel is connected to DPWM peripheral transmit (PDMA destination) request. 12 4 read-write I2S_RXSEL PDMA I2S Receive Selection This field defines which PDMA channel is connected to I2S peripheral receive (PDMA source) request. 24 4 read-write I2S_TXSEL PDMA I2S Transmit Selection This field defines which PDMA channel is connected to I2S peripheral transmit (PDMA destination) request. 28 4 read-write SPI0_RXSEL PDMA SPI0 Receive Selection This field defines which PDMA channel is connected to SPI0 peripheral receive (PDMA source) request. 0 4 read-write SPI0_TXSEL PDMA SPI0 Transmit Selection This field defines which PDMA channel is connected to SPI0 peripheral transmit (PDMA destination) request. 4 4 read-write UART0_RXSEL PDMA UART0 Receive Selection This field defines which PDMA channel is connected to UART0 peripheral receive (PDMA source) request. 16 4 read-write UART0_TXSEL PDMA UART0 Transmit Selection This field defines which PDMA channel is connected to UART0 peripheral transmit (PDMA destination) request. 20 4 read-write PWMA PWMA Register Map PWMA 0x0 0x0 0x24 registers n 0x40 0x8 registers n 0x50 0x4 registers n 0x58 0x10 registers n 0x78 0x8 registers n CAPENR CAPENR Capture Input Enable Register 0x78 -1 read-write n 0x0 0x0 CAPENR Capture Input Enable Register 0 : OFF (GPA[13:12] pin input disconnected from Capture block) 1 : ON (GPA[13:12] pin, if in PWM alternative function, will be configured as an input and fed to capture function) CAPENR[1:0] Bit 10 Bit x1 : Capture channel 0 is from GPA [12] Bit 1x : Capture channel 1 is from GPA [13] 0 4 read-write CCR0 CCR0 Capture Control Register 0 0x50 -1 read-write n 0x0 0x0 CAPCH0EN Capture Channel 0 transition Enable/Disable When enabled, Capture function latches the PMW-counter to CRLR (Rising latch) and CFLR (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt. 3 1 read-write 0 Disable capture function on channel 0 #0 1 Enable capture function on channel 0 #1 CAPCH1EN Capture Channel 1 Transition Enable/Disable When enabled, Capture function latches the PMW-counter to CRLR (Rising latch) and CFLR (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt. 19 1 read-write 0 Disable capture function on channel 1 #0 1 Enable capture function on channel 1 #1 CAPIF0 Capture0 Interrupt Indication Flag If channel 0 rising latch interrupt is enabled (CRL_IE0 = 1), a rising transition at input channel 0 will result in CAPIF0 to high Similarly, a falling transition will cause CAPIF0 to be set high if channel 0 falling latch interrupt is enabled (CFL_IE0 = 1). This flag is cleared by software writing a '1' to it. 4 1 read-write CAPIF1 Capture1 Interrupt Indication Flag If channel 1 rising latch interrupt is enabled (CRL_IE1 = 1), a rising transition at input channel 1 will result in CAPIF1 to high Similarly, a falling transition will cause CAPIF1 to be set high if channel 1 falling latch interrupt is enabled (CFL_IE1 = 1). This flag is cleared by software writing a '1' to it. 20 1 read-write CFLRI0 CFLR0 Latched Indicator Bit When input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it. 7 1 read-write CFLRI1 CFLR1 Latched Indicator Bit When input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it. 23 1 read-write CFL_IE0 Channel 0 Falling Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on falling edge of input. 2 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CFL_IE1 Channel 1 Falling Latch Interrupt Enable When enabled, capture block generates an interrupt on falling edge of input. 18 1 read-write 0 Disable falling edge latch interrupt #0 1 Enable falling edge latch interrupt #1 CRLRI0 CRLR0 Latched Indicator Bit When input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it. 6 1 read-write CRLRI1 CRLR1 Latched Indicator Bit When input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it. 22 1 read-write CRL_IE0 Channel 0 Rising Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on rising edge of input. 1 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 CRL_IE1 Channel 1 Rising Latch Interrupt Enable When enabled, capture block generates an interrupt on rising edge of input. 17 1 read-write 0 Disable rising edge latch interrupt #0 1 Enable rising edge latch interrupt #1 INV0 Channel 0 Inverter ON/OFF 0 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before Capture timer #1 INV1 Channel 1 Inverter ON/OFF 16 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before Capture timer #1 CFLR0 CFLR0 Capture Falling Latch Register (Channel 0) 0x5C -1 read-only n 0x0 0x0 CFLR Capture Falling Latch Register In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal. 0 16 read-only CFLR1 0x64 -1 read-write n 0x0 0x0 CMR0 CMR0 PWM Comparator Register 0 0x10 -1 read-write n 0x0 0x0 CMR PWM Comparator Register CMR determines the PWM duty cycle. PWM frequency = PWM01_CLK/(prescale+1)*(clock divider)/(CNR+1) Duty Cycle = (CMR+1)/(CNR+1). CMR > = CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CMR will take effect in next PWM cycle. 0 16 read-write CMR1 0x1C -1 read-write n 0x0 0x0 CNR0 CNR0 PWM Counter Register 0 0xC -1 read-write n 0x0 0x0 CNR PWM Counter/Timer Reload Value CNR determines the PWM period. PWM frequency = PWM01_CLK/(prescale+1)*(clock divider)/(CNR+1) Duty ratio = (CMR+1)/(CNR+1). CMR > = CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle. 0 16 read-write CNR1 0x18 -1 read-write n 0x0 0x0 CRLR0 CRLR0 Capture Rising Latch Register (Channel 0) 0x58 -1 read-only n 0x0 0x0 CRLR Capture Rising Latch Register In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal. 0 16 read-only CRLR1 0x60 -1 read-write n 0x0 0x0 CSR CSR PWM Clock Select Register 0x4 -1 read-write n 0x0 0x0 CSR0 Timer 0 Clock Source Selection (Table is as CSR1) 0 3 read-write CSR1 Timer 1 Clock Source Selection Value : Input clock divided by 0 : 2 1 : 4 2 : 8 3 : 16 4 : 1 4 3 read-write PCR PCR PWM Control Register 0x8 -1 read-write n 0x0 0x0 CH0EN PWM-Timer 0 Enable/Disable Start Run 0 1 read-write 0 Stop PWM-Timer 0 Running #0 1 Enable PWM-Timer 0 Start/Run #1 CH0INV PWM-Timer 0 Output Inverter ON/OFF 2 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH0MOD PWM-Timer 0 Auto-reload/One-Shot Mode Note: A rising transition of this bit will cause CNR0 and CMR0 to be cleared. 3 1 read-write 0 One-Shot Mode #0 1 Auto-reload Mode #1 CH1EN PWM-Timer 1 Enable/Disable Start Run 8 1 read-write 0 Stop PWM-Timer 1 #0 1 Enable PWM-Timer 1 Start/Run #1 CH1INV PWM-Timer 1 Output Inverter ON/OFF 10 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH1MOD PWM-Timer 1 Auto-reload/One-Shot Mode Note: A rising transition of this bit will cause CNR1 and CMR1 to be cleared. 11 1 read-write 0 One-Shot Mode #0 1 Auto-load Mode #1 DZEN01 Dead-Zone 0 Generator Enable/Disable Note: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 become a complementary pair. 4 1 read-write 0 Disable #0 1 Enable #1 PDR0 PDR0 PWM Data Register 0 0x14 -1 read-only n 0x0 0x0 PDR PWM Data Register Reports the current value of the 16-bit down counter. 0 16 read-only PDR1 0x20 -1 read-write n 0x0 0x0 PIER PIER PWM Interrupt Enable Register 0x40 -1 read-write n 0x0 0x0 PWMIE0 PWM Timer 0 Interrupt Enable 0 1 read-write 0 Disable #0 1 Enable #1 PWMIE1 PWM Timer 1 Interrupt Enable 1 1 read-write 0 Disable #0 1 Enable #1 PIFR PIFR PWM Interrupt Flag Register 0x44 -1 read-write n 0x0 0x0 PWMIF0 PWM Timer 0 Interrupt Flag Flag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing '1' to it. 0 1 read-write PWMIF1 PWM Timer 1 Interrupt Flag Flag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing '1' to it. 1 1 read-write POE POE PWM Output Enable Register for PWM0~PWM1 0x7C -1 read-write n 0x0 0x0 PWM0 PWM0 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to GPA_ALT Table 57) 0 1 read-write 0 Disable PWM0 output to pin #0 1 Enable PWM0 output to pin #1 PWM1 PWM1 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to GPA_ALT Table 57) 1 1 read-write 0 Disable PWM1 output to pin #0 1 Enable PWM1 output to pin #1 PPR PPR PWM Prescaler Register 0x0 -1 read-write n 0x0 0x0 CP01 Clock Pre-scaler Clock input is divided by (CP01 + 1). If CP01 = 0, then the pre-scaler output clock will be stopped. This implies PWM counter 0 and 1 will also be stopped. 0 8 read-write DZI01 Dead Zone Interval Register For Pair Of PWM0 And PWM1 These 8 bits determine dead zone length. The unit time of dead zone length is that from clock selector 0. 16 8 read-write RTC RTC Register Map RTC 0x0 0x0 0x34 registers n AER AER RTC Access Enable Register 0x4 -1 read-write n 0x0 0x0 AER RTC Register Access Enable Password (Write only) 0xA965 = Enable RTC access Others = Disable RTC access 0 16 write-only ENF RTC Register Access Enable Flag (Read only) This bit will be set after AER[15:0] register is set to 0xA965, it will clear automatically in 512 RTC clock cycles or AER[15:0] ! = 0xA965. The effect of AER.ENF on access to each register is given Table 572. Table 572 AER.ENF Register Access Effect. Register : ENF = 1 : ENF = 0 INIR : R/W : R/W FCR : R/W : - TLR : R/W : R CLR : R/W : R TSSR : R/W : R/W DWR : R/W : R TAR : R/W : - CAR : R/W : - LIR : R : R RIER : R/W : R/W RIIR : R/W : R/W TTR : R/W : - 16 1 read-only 0 RTC register read/write disable #0 1 RTC register read/write enable #1 CAR CAR Calendar Alarm Register 0x20 -1 read-write n 0x0 0x0 _10DAY 10-Day Calendar Digit of Alarm Setting (0~3) 4 2 read-write _10MON 10-Month Calendar Digit of Alarm Setting (0~1) 12 1 read-write _10YEAR 10-Year Calendar Digit of Alarm Setting (0~9) 20 4 read-write _1DAY 1-Day Calendar Digit of Alarm Setting (0~9) 0 4 read-write _1MON 1-Month Calendar Digit of Alarm Setting (0~9) 8 4 read-write _1YEAR 1-Year Calendar Digit of Alarm Setting (0~9) 16 4 read-write CLR CLR Calendar Load Register 0x10 -1 read-write n 0x0 0x0 _10DAY 10-Day Calendar Digit (0~3) 4 2 read-write _10MON 10-Month Calendar Digit (0~1) 12 1 read-write _10YEAR 10-Year Calendar Digit (0~9) 20 4 read-write _1DAY 1-Day Calendar Digit (0~9) 0 4 read-write _1MON 1-Month Calendar Digit (0~9) 8 4 read-write _1YEAR 1-Year Calendar Digit (0~9) 16 4 read-write DWR DWR Day of the Week Register 0x18 -1 read-write n 0x0 0x0 DWR Day of the Week Register 0 (Sunday), 1 (Monday), 2 (Tuesday), 3 (Wednesday) 4 (Thursday), 5 (Friday), 6 (Saturday) 0 3 read-write FCR FCR RTC Frequency Compensation Register 0x8 -1 read-write n 0x0 0x0 FRACTION Fractional Part Formula = (fraction part of detected value) x 60 Refer to 5.8.4.4 for the examples. 0 6 read-write INTEGER Integer Part Register should contain the value (INT(Factual) - 32761) Ex: Integer part of detected value = 32772, FCR.INTEGER = 32772-32761 = 11 (1011b) The range between 32761 and 32776 8 4 read-write INIR INIR RTC Initialization Register 0x0 -1 read-write n 0x0 0x0 Active RTC Active Status (Read only) 0: RTC is in reset state 1: RTC is in normal active state. 0 1 read-only INIR RTC Initialization After a power-on reset (POR) RTC block should be initialized by writing 0xA5EB1357 to INIR. This will force a hardware reset then release all logic and counters. 1 31 read-write LIR LIR Leap year Indicator Register 0x24 -1 read-only n 0x0 0x0 LIR Leap Year Indication Register (read only) 0 1 read-only 0 Current year is not a leap year #0 1 Current year is leap year #1 RIER RIER RTC Interrupt Enable Register 0x28 -1 read-write n 0x0 0x0 AIER Alarm Interrupt Enable 0 1 read-write 0 RTC Alarm Interrupt is disabled #0 1 RTC Alarm Interrupt is enabled #1 TIER Time-Tick Interrupt and Wakeup-by-Tick Enable 1 1 read-write 0 RTC Time-Tick Interrupt is disabled #0 1 RTC Time-Tick Interrupt is enabled #1 RIIR RIIR RTC Interrupt Indicator Register 0x2C -1 read-write n 0x0 0x0 AI RTC Alarm Interrupt Flag 0 1 read-write 0 Indicates no Alarm Interrupt condition #0 1 Indicates RTC Alarm Interrupt generated #1 TI RTC Time-Tick Interrupt Flag 1 1 read-write 0 Indicates no Time-Tick Interrupt condition #0 1 Indicates RTC Time-Tick Interrupt generated #1 TAR TAR Time Alarm Register 0x1C -1 read-write n 0x0 0x0 _10HR 10 Hour Time Digit of Alarm Setting (0~3) 20 2 read-write _10MIN 10 Min Time Digit of Alarm Setting (0~5) 12 3 read-write _10SEC 10 Sec Time Digit of Alarm Setting (0~5) 4 3 read-write _1HR 1 Hour Time Digit of Alarm Setting (0~9) 16 4 read-write _1MIN 1 Min Time Digit of Alarm Setting (0~9) 8 4 read-write _1SEC 1 Sec Time Digit of Alarm Setting (0~9) 0 4 read-write TLR TLR Time Load Register 0xC -1 read-write n 0x0 0x0 _10HR 10 Hour Time Digit (0~3) 20 2 read-write _10MIN 10 Min Time Digit (0~5) 12 3 read-write _10SEC 10 Sec Time Digit (0~5) 4 3 read-write _1HR 1 Hour Time Digit (0~9) 16 4 read-write _1MIN 1 Min Time Digit (0~9) 8 4 read-write _1SEC 1 Sec Time Digit (0~9) 0 4 read-write TSSR TSSR Time Scale Selection Register 0x14 -1 read-write n 0x0 0x0 HR24 24-Hour / 12-Hour Mode Selection Determines whether TLR and TAR are in 24-hour mode or 12-hour mode The range of 24-hour time scale is between 0 and 23. 12-hour time scale: 01(AM01), 02(AM02), 03(AM03), 04(AM04), 05(AM05), 06(AM06) 07(AM07), 08(AM08), 09(AM09), 10(AM10), 11(AM11), 12(AM12) 21(PM01), 22(PM02), 23(PM03), 24(PM04), 25(PM05), 26(PM06) 27(PM07), 28(PM08), 29(PM09), 30(PM10), 31(PM11), 32(PM12) 0 1 read-write 0 select 12-hour time scale with AM and PM indication #0 1 select 24-hour time scale #1 TTR TTR RTC Time Tick Register 0x30 -1 read-write n 0x0 0x0 TTR Time Tick Register The RTC time tick period for Periodic Time-Tick Interrupt request. Time Tick (second) : 1 / (2^TTR) Note: This register can be read back after the RTC is active. 0 3 read-write TWKE RTC Timer Wakeup CPU Function Enable Bit If TWKE is set before CPU is in power-down mode, when a RTC Time-Tick or Alarm Match occurs, CPU will wake up. 3 1 read-write 0 Disable Wakeup CPU function #0 1 Enable the Wakeup function #1 SCS SCS Register Map SCS 0x0 0x10 0xC registers n 0x100 0x4 registers n 0x180 0x4 registers n 0x200 0x4 registers n 0x280 0x4 registers n 0x400 0x20 registers n 0xD00 0x8 registers n 0xD0C 0x8 registers n 0xD1C 0x8 registers n AIRCR AIRCR Application Interrupt and Reset Control Register 0xD0C -1 read-write n 0x0 0x0 ENDIANESS Endianess Read Only. Reads 0 indicating little endian machine. 15 1 read-write SYSRESETREQ System Reset Request Writing 1 to this bit asserts a signal to request a reset by the external system. 2 1 read-write 0 do not request a reset #0 1 request reset #1 VECTCLRACTIVE Clear All Active Vector Clears all active state information for fixed and configurable exceptions. The effect of writing a 1 to this bit if the processor is not halted in Debug, is UNPREDICTABLE. 1 1 read-write 0 do not clear state information #0 1 clear state information #1 VECTKEY Vector Key The value 0x05FA must be written to this register, otherwise a write to register is UNPREDICTABLE. 16 16 read-write CPUID CPUID CPUID Base Register 0xD00 -1 read-only n 0x0 0x0 IMPLEMENTER Implementer Code Assigned By ARM ARM = 0x41. 24 8 read-only PART ARMv6-M Parts Reads as 0xC for ARMv6-M parts 16 4 read-only PARTNO Part Number Reads as 0xC20. 4 12 read-only REVISION Revision Reads as 0x0 0 4 read-only CTRL CTRL SysTick Control and Status Register 0x10 -1 read-write n 0x0 0x0 CLKSRC Clock Source 2 1 read-write 0 Core clock unused #0 1 Core clock used for SysTick, this bit will read as 1 and ignore writes #1 COUNTFLAG Count Flag Returns 1 if timer counted to 0 since last time this register was read. 16 1 read-write 0 Cleared on read or by a write to the Current Value register #0 1 Set by a count transition from 1 to 0 #1 ENABLE ENABLE 0 1 read-write 0 The counter is disabled #0 1 The counter will operate in a multi-shot manner #1 TICKINT Enables SysTick Exception Request 1 1 read-write 0 Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred #0 1 Counting down to 0 will cause SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended #1 ICSR ICSR Interrupt Control State Register 0xD04 -1 read-write n 0x0 0x0 ISRPENDING ISR Pending Indicates if an external configurable (NVIC generated) interrupt is pending. 22 1 read-write ISRPREEMPT ISR Preemptive If set, a pending exception will be serviced on exit from the debug halt state. 23 1 read-write NMIPENDSET NMI Pending Set Control Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not). 31 1 read-write PENDSTCLR Clear A pending SysTick Write 1 to clear a pending SysTick. 25 1 read-write PENDSTSET Set A pending SysTick Reads back with current state (1 if Pending, 0 if not). 26 1 read-write PENDSVCLR Clear A Pending PendSV Interrupt Write 1 to clear a pending PendSV interrupt. 27 1 read-write PENDSVSET Set A Pending PendSV Interrupt This is normally used to request a context switch. Reads back with current state (1 if Pending, 0 if not). 28 1 read-write VECTACTIVE Vector Active 0: Thread mode Value > 1: the exception number for the current executing exception. 0 9 read-write VECTPENDING Vector Pending Indicates the exception number for the highest priority pending exception. The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A value of zero indicates no pending exceptions. 12 9 read-write LOAD LOAD SysTick Reload value Register 0x14 -1 read-write n 0x0 0x0 RELOAD SysTick Reload Value to load into the Current Value register when the counter reaches 0. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 200 clock pulses, set RELOAD to 199. 0 24 read-write NVIC_ICER NVIC_ICER IRQ0 ~ IRQ31 Clear-Enable Control Register 0x180 -1 read-write n 0x0 0x0 CLRENA Clear-Enable Control Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 1 will disable the associated interrupt. Writing 0 has no effect. The register reads back with the current enable state. 0 32 read-write NVIC_ICPR NVIC_ICPR IRQ0 ~ IRQ31 Clear-Pending Control Register 0x280 -1 read-write n 0x0 0x0 CLRPEND Clear-Pending Control Writing 1 to a bit to clear the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 0 has no effect. The register reads back with the current pending state. 0 32 read-write NVIC_IPR0 NVIC_IPR0 IRQ0 ~ IRQ3 Priority Control Register 0x400 -1 read-write n 0x0 0x0 PRI_0 Priority of IRQ0 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_1 Priority of IRQ1 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_2 Priority of IRQ2 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_3 Priority of IRQ3 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR1 NVIC_IPR1 IRQ4 ~ IRQ7 Priority Control Register 0x404 -1 read-write n 0x0 0x0 PRI_4 Priority of IRQ4 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_5 Priority of IRQ5 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_6 Priority of IRQ6 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_7 Priority of IRQ7 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR2 NVIC_IPR2 IRQ8 ~ IRQ11 Priority Control Register 0x408 -1 read-write n 0x0 0x0 PRI_10 Priority of IRQ10 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_11 Priority of IRQ11 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write PRI_8 Priority of IRQ8 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_9 Priority of IRQ9 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write NVIC_IPR3 NVIC_IPR3 IRQ12 ~ IRQ15 Priority Control Register 0x40C -1 read-write n 0x0 0x0 PRI_12 Priority of IRQ12 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_13 Priority of IRQ13 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_14 Priority of IRQ14 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_15 Priority of IRQ15 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR4 NVIC_IPR4 IRQ16 ~ IRQ19 Priority Control Register 0x410 -1 read-write n 0x0 0x0 PRI_16 Priority of IRQ16 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_17 Priority of IRQ17 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_18 Priority of IRQ18 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_19 Priority of IRQ19 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR5 NVIC_IPR5 IRQ20 ~ IRQ23 Priority Control Register 0x414 -1 read-write n 0x0 0x0 PRI_20 Priority of IRQ20 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_21 Priority of IRQ21 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_22 Priority of IRQ22 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_23 Priority of IRQ23 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR6 NVIC_IPR6 IRQ24 ~ IRQ27 Priority Control Register 0x418 -1 read-write n 0x0 0x0 PRI_24 Priority of IRQ24 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_25 Priority of IRQ25 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_26 Priority of IRQ26 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_27 Priority of IRQ27 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR7 NVIC_IPR7 IRQ28 ~ IRQ31 Priority Control Register 0x41C -1 read-write n 0x0 0x0 PRI_28 Priority of IRQ28 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_29 Priority of IRQ29 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_30 Priority of IRQ30 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_31 Priority of IRQ31 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_ISER NVIC_ISER IRQ0 ~ IRQ31 Set-Enable Control Register 0x100 -1 read-write n 0x0 0x0 SETENA Set-Enable Control Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 1 will enable the associated interrupt. Writing 0 has no effect. The register reads back the current enable state. 0 32 read-write NVIC_ISPR NVIC_ISPR IRQ0 ~ IRQ31 Set-Pending Control Register 0x200 -1 read-write n 0x0 0x0 SETPEND Set-Pending Control Writing 1 to a bit forces pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 0 has no effect. The register reads back with the current pending state. 0 32 read-write SCR SCR System Control Register 0xD10 -1 read-write n 0x0 0x0 SEVONPEND Send Event On Pending Bit When enabled, interrupt transitions from Inactive to Pending are included in the list of wakeup events for the WFE instruction. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction. 4 1 read-write 0 only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded #0 1 enabled events and all interrupts, including disabled interrupts, can wake-up the processor #1 SLEEPDEEP Sleep Deep Control Controls whether the processor uses sleep or deep sleep as its low power mode: The SLEEPDEEP flag is also used in conjunction with PWRCON register to enter deeper power-down states than purely core sleep states. 2 1 read-write 0 sleep #0 1 deep sleep #1 SLEEPONEXIT Sleep On Exception When set to 1, the core can enter a sleep state on an exception return to Thread mode. This is the mode and exception level entered at reset, the base level of execution. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 1 1 read-write SHPR2 SHPR2 System Handler Priority Register 2 0xD1C -1 read-write n 0x0 0x0 PRI_11 Priority Of System Handler 11 - SVCall 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write SHPR3 SHPR3 System Handler Priority Register 3 0xD20 -1 read-write n 0x0 0x0 PRI_14 Priority Of System Handler 14 - PendSV 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_15 Priority Of System Handler 15 - SysTick 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write VAL VAL SysTick Current value Register 0x18 -1 read-write n 0x0 0x0 CURRENT Current Counter Value This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0 and also clear the COUNTFLAG bit. 0 24 read-write SPI0 SPI0 Register Map SPI0 0x0 0x0 0xC registers n 0x10 0x8 registers n 0x20 0x8 registers n 0x34 0x8 registers n CNTRL CNTRL Control and Status Register 0x0 -1 read-write n 0x0 0x0 BYTE_ENDIAN Byte Endian Reorder Function This function changes the order of bytes sent/received to be least significant physical byte first. 20 1 read-write BYTE_SLEEP Insert Sleep Interval Between Bytes This function is only valid for 32bit transfers (TX_BIT_LEN = 0). If set then a pause of (SLEEP+2) SCLK cycles is inserted between each byte transmitted. 19 1 read-write CLKP Clock Polarity 11 1 read-write 0 SCLK idle low #0 1 SCLK idle high #1 DMA_ASS_BURST Enable DMA Automatic SS function When enabled, interface will automatically generate a SS signal for an entire PDMA access transaction. 28 1 read-write FIFO FIFO Mode 21 1 read-write 0 No FIFO present on transmit and receive buffer #0 1 Enable FIFO on transmit and receive buffer #1 GO_BUSY Go and Busy Status NOTE: All registers should be set before writing 1 to this GO_BUSY bit. When a transfer is in progress, writing to any register of the SPI master/slave core has no effect. 0 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit starts the transfer. This bit remains set during the transfer and is automatically cleared after transfer finished #1 IE Interrupt Enable 17 1 read-write 0 Disable SPI Interrupt #0 1 Enable SPI Interrupt to CPU #1 IF Interrupt Flag NOTE: This bit is cleared by writing 1 to itself. 16 1 read-write 0 Indicates the transfer is not finished yet #0 1 Indicates that the transfer is complete. Interrupt is generated to CPU if enabled #1 LSB LSB First 10 1 read-write 0 The MSB is transmitted/received first (which bit in SPI_TX[0]/[1] and SPI_RX[0]/[1] register that is depends on the TX_BIT_LEN field) #0 1 The LSB is sent first on the line (bit 0 of SPI_TX[0]/[1]), and the first bit received from the line will be put in the LSB position in the Rx register (bit 0 of SPI_RX[0]/[1]) #1 RX_EMPTY Receive FIFO Empty Status 24 1 read-write 0 The receive data FIFO is not empty #0 1 The receive data FIFO is empty #1 RX_FULL Receive FIFO Full Status 25 1 read-write 0 The receive data FIFO is not full #0 1 The receive data FIFO is full #1 RX_NEG Receive At Negative Edge 1 1 read-write 0 The received data input signal is latched at the rising edge of SCLK #0 1 The received data input signal is latched at the falling edge of SCLK #1 SLAVE Master Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SLEEP Suspend Interval (Master Only) These four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKP = 0. If CLKP = 1, the interval is from the rising clock edge to the falling clock edge. The default value is 0x0. When TX_NUM = 00b, setting this field has no effect on transfer except as determined by REORDER[0] setting. The suspend interval is determined according to the following equation: (SLEEP[3:0] + 2) * period of SCLK 12 4 read-write TWOB Two Bits Transfer Mode Note that when enabled in master mode, MOSI0 data comes from TX[0] and MOSI1 data from TX[1]. Likewise RX[0] receives bit stream from MISO0 and RX[1] from MISO1. Note that when enabled, the setting of TX_NUM must be programmed as 0x00 22 1 read-write 0 Disable two-bit transfer mode #0 1 Enable two-bit transfer mode #1 TX_BIT_LEN Transmit Bit Length This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted. TX_BIT_LEN = 0x01 --- 1 bit TX_BIT_LEN = 0x02 --- 2 bits ---- TX_BIT_LEN = 0x1f --- 31 bits TX_BIT_LEN = 0x00 --- 32 bits 3 5 read-write TX_EMPTY Transmit FIFO Empty Status 26 1 read-write 0 The transmit data FIFO is not empty #0 1 The transmit data FIFO is empty #1 TX_FULL Transmit FIFO Full Status 27 1 read-write 0 The transmit data FIFO is not full #0 1 The transmit data FIFO is full #1 TX_NEG Transmit At Negative Edge 2 1 read-write 0 The transmitted data output signal is changed at the rising edge of SCLK #0 1 The transmitted data output signal is changed at the falling edge of SCLK #1 TX_NUM Transmit/Receive Word Numbers This field specifies how many transmit/receive word numbers should be executed in one transfer. 8 2 read-write 0 Only one transmit/receive word will be executed in one transfer #00 1 Two successive transmit/receive word will be executed in one transfer #01 2 Reserved #10 3 Reserved #11 VARCLK_EN Variable Clock Enable (Master Only) Note that when enabled, the setting of TX_BIT_LEN must be programmed as 0x10 (16 bits mode) 23 1 read-write 0 The serial clock output frequency is fixed and determined only by the value of DIVIDER #0 1 SCLK output frequency is variable. The output frequency is determined by the value of VARCLK, DIVIDER, and DIVIDER2 #1 DIVIDER DIVIDER Clock Divider Register (Master Only) 0x4 -1 read-write n 0x0 0x0 DIVIDER Clock Divider Register (master only) The value in this field is the frequency division of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation: Fsclk = Fpclk / ((DIVIDER+1) * 2) In slave mode, the period of SPI clock driven by a master shall satisfy Fsclk < = (Fpclk / 5) In other words, the maximum frequency of SCLK clock is one fifth of the SPI peripheral clock. 0 16 read-write DIVIDER2 Clock Divider 2 Register (master only) The value in this field is the 2nd frequency divider of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation: Fsclk = Fpclk / ((DIVIDER2+1) * 2) 16 16 read-write DMA DMA SPI DMA Control Register 0x38 -1 read-write n 0x0 0x0 Rx_DMA_GO Receive DMA Start Set this bit to 1 will start the receive DMA process. SPI module will issue request to DMA module automatically. 1 1 read-write Tx_DMA_GO Transmit DMA Start Set this bit to 1 will start the transmit DMA process. SPI module will issue request to DMA module automatically. If using DMA mode to transfer data, remember not to set GO_BUSY bit of SPI_CNTRL register. The DMA controller inside SPI module will set it automatically whenever necessary. 0 1 read-write RX0 RX0 Data Receive Register 0 0x10 -1 read-only n 0x0 0x0 RX Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register. For example, if Tx_BIT_LEN is set to 0x08 and Tx_NUM is set to 0x0, bit Rx0[7:0] holds the received data. NOTE: The Data Receive Registers are read only registers. 0 32 read-only RX1 0x14 -1 read-write n 0x0 0x0 SSR SSR Slave Select Register 0x8 -1 read-write n 0x0 0x0 ASS Automatic Slave Select (Master only) 3 1 read-write 0 If this bit is cleared, slave select signals are asserted and de-asserted by setting and clearing related bits in SSR[1:0] register #0 1 If this bit is set, SPISSx0/1 signals are generated automatically. It means that device/slave select signal, which is set in SSR[1:0] register is asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and is de-asserted after each transmit/receive is finished #1 LTRIG_FLAG Level Trigger Flag When the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not. Note: This bit is READ only 5 1 read-write 0 One of the received number and the received bit length doesn't meet the requirement in one transfer #0 1 The received number and received bits met the requirement which defines in Tx_NUM and Tx_BIT_LEN among one transfer #1 SSR Slave Select Register (Master only) If ASS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state. If ASS bit is set, writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active level of SPISSx0/1 is specified in SS_LVL). Note: SPISSx0 is always defined as device/slave select input signal in slave mode. 0 2 read-write SS_LTRIG Slave Select Level Trigger (Slave only) 4 1 read-write 0 The input slave select signal is edge-trigger. This is the default value #0 1 The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high #1 SS_LVL Slave Select Active Level It defines the active level of device/slave select signal (SPISSx0/1). 2 1 read-write 0 The slave select signal SPISSx0/1 is active at low-level/falling-edge #0 1 The slave select signal SPISSx0/1 is active at high-level/rising-edge #1 TX0 TX0 Data Transmit Register 0 0x20 -1 write-only n 0x0 0x0 Tx Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register. For example, if Tx_BIT_LEN is set to 0x08 and the Tx_NUM is set to 0x0, the bit Tx0[7:0] will be transmitted in next transfer. If Tx_BIT_LEN is set to 0x00 and Tx_NUM is set to 0x1, the core will perform two 32-bit transmit/receive successive using the same setting (the order is Tx0[31:0], Tx1[31:0]). 0 32 write-only TX1 0x24 -1 read-write n 0x0 0x0 VARCLK VARCLK Variable Clock Pattern Register 0x34 -1 read-write n 0x0 0x0 VARCLK Variable Clock Pattern The value in this field is the frequency pattern of the SPI clock. If the bit field of VARCLK is '0', the output frequency of SCLK is given by the value of DIVIDER. If the bit field of VARCLK is '1', the output frequency of SCLK is given by the value of DIVIDER2. Refer to register DIVIDER. Refer to Variable Serial Clock Frequency paragraph for detailed description. 0 32 read-write TMR0 TMR Register Map TMR 0x0 0x0 0x10 registers n TCMPR TCMPR Timer Compare Register 0x4 -1 read-write n 0x0 0x0 TCMP Timer Comparison Value TCMP is a 24-bit comparison register. When the 24-bit up-counter is enabled and its value is equal to TCMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TCSR.IE = 1. The TCMP value defines the timer cycle time. Time out period = (Period of timer clock input) * (8-bit PRESCALE + 1) * (24-bit TCMP) NOTE1: Never set TCMP to 0x000 or 0x001. Timer will not function correctly. NOTE2: Regardless of CEN state, whenever a new value is written to this register, TIMER will restart counting using this new value and abort previous count. 0 25 read-write TCSR TCSR Timer Control and Status Register 0x0 -1 read-write n 0x0 0x0 CACT Timer Active Status Bit (Read only) This bit indicates the counter status of timer. 25 1 read-only 0 Timer is not active #0 1 Timer is active #1 CEN Counter Enable Bit Note1: Setting CEN = 1 enables 24-bit counter. It continues count from last value. Note2: This bit is auto-cleared by hardware in one-shot mode (MODE = 00b) when the timer interrupt is generated (IE = 1b). 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 CRST Counter Reset Bit Set this bit will reset the timer counter, prescale and also force CEN to 0. 26 1 read-write 0 No effect #0 1 Reset Timer's prescale counter, internal 24-bit up-counter and CEN bit #1 IE Interrupt Enable Bit If timer interrupt is enabled, the timer asserts its interrupt signal when the count is equal to TCMPR. 29 1 read-write 0 Disable TIMER Interrupt #0 1 Enable TIMER Interrupt #1 MODE Timer Operating Mode 27 2 read-write 0 The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if IE is enabled) and CEN is automatically cleared by hardware 0 1 The timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if IE is enabled) 1 2 Reserved 2 3 The timer is operating in continuous counting mode. The associated interrupt signal is generated when TDR = TCMPR (if IE is enabled) however, the 24-bit up-counter counts continuously without reset 3 PRESCALE Pre-scale Counter Clock input is divided by PRESCALE+1 before it is fed to the counter. If PRESCALE = 0, then there is no scaling. 0 8 read-write TDR_EN Data Latch Enable When TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-counter value as the timer is counting. 16 1 read-write 0 Timer Data Register update disable #0 1 Timer Data Register update enable #1 TDR TDR Timer Data Register 0xC -1 read-write n 0x0 0x0 TDR Timer Data Register When TCSR.TDR_EN is set to 1, the internal 24-bit timer up-counter value will be latched into TDR. User can read this register for the up-counter value. 0 24 read-write TISR TISR Timer Interrupt Status Register 0x8 -1 read-write n 0x0 0x0 TIF Timer Interrupt Flag This bit indicates the interrupt status of Timer. TIF bit is set by hardware when the 24-bit counter matches the timer comparison value (TCMP). It is cleared by writing 1. 0 1 read-write TMR1 TMR Register Map TMR 0x0 0x0 0x10 registers n TCMPR TCMPR Timer Compare Register 0x4 -1 read-write n 0x0 0x0 TCMP Timer Comparison Value TCMP is a 24-bit comparison register. When the 24-bit up-counter is enabled and its value is equal to TCMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TCSR.IE = 1. The TCMP value defines the timer cycle time. Time out period = (Period of timer clock input) * (8-bit PRESCALE + 1) * (24-bit TCMP) NOTE1: Never set TCMP to 0x000 or 0x001. Timer will not function correctly. NOTE2: Regardless of CEN state, whenever a new value is written to this register, TIMER will restart counting using this new value and abort previous count. 0 25 read-write TCSR TCSR Timer Control and Status Register 0x0 -1 read-write n 0x0 0x0 CACT Timer Active Status Bit (Read only) This bit indicates the counter status of timer. 25 1 read-only 0 Timer is not active #0 1 Timer is active #1 CEN Counter Enable Bit Note1: Setting CEN = 1 enables 24-bit counter. It continues count from last value. Note2: This bit is auto-cleared by hardware in one-shot mode (MODE = 00b) when the timer interrupt is generated (IE = 1b). 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 CRST Counter Reset Bit Set this bit will reset the timer counter, prescale and also force CEN to 0. 26 1 read-write 0 No effect #0 1 Reset Timer's prescale counter, internal 24-bit up-counter and CEN bit #1 IE Interrupt Enable Bit If timer interrupt is enabled, the timer asserts its interrupt signal when the count is equal to TCMPR. 29 1 read-write 0 Disable TIMER Interrupt #0 1 Enable TIMER Interrupt #1 MODE Timer Operating Mode 27 2 read-write 0 The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if IE is enabled) and CEN is automatically cleared by hardware 0 1 The timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if IE is enabled) 1 2 Reserved 2 3 The timer is operating in continuous counting mode. The associated interrupt signal is generated when TDR = TCMPR (if IE is enabled) however, the 24-bit up-counter counts continuously without reset 3 PRESCALE Pre-scale Counter Clock input is divided by PRESCALE+1 before it is fed to the counter. If PRESCALE = 0, then there is no scaling. 0 8 read-write TDR_EN Data Latch Enable When TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-counter value as the timer is counting. 16 1 read-write 0 Timer Data Register update disable #0 1 Timer Data Register update enable #1 TDR TDR Timer Data Register 0xC -1 read-write n 0x0 0x0 TDR Timer Data Register When TCSR.TDR_EN is set to 1, the internal 24-bit timer up-counter value will be latched into TDR. User can read this register for the up-counter value. 0 24 read-write TISR TISR Timer Interrupt Status Register 0x8 -1 read-write n 0x0 0x0 TIF Timer Interrupt Flag This bit indicates the interrupt status of Timer. TIF bit is set by hardware when the 24-bit counter matches the timer comparison value (TCMP). It is cleared by writing 1. 0 1 read-write UART0 UART0 Register Map UART0 0x0 0x0 0x34 registers n BAUD BAUD UART0 Baud Rate Divisor Register 0x24 -1 read-write n 0x0 0x0 BRD Baud Rate Divider Refer to Table 5111 for more information. 0 16 read-write DIVX Divider X The baud rate divider M = DIVX+1. 24 4 read-write DIVX_EN Divider X Enable The baud rate equation is: Baud Rate = UART_CLK / [ M * (BRD + 2) ] The default value of M is 16. Refer to Table 5111 for more information. NOTE: When in IrDA mode, this bit must disabled. 29 1 read-write 0 Disable divider X ( M = 16) #0 1 Enable divider X (M = DIVX+1, with DIVX ≥ 8) #1 DIVX_ONE Divider X equal 1 0: M = DIVX+1, with restriction DIVX ≥ 8. 1: M = 1, with restriction BRD[15:0] ≥ 3. Refer to Table 5111 for more information. 28 1 read-write DATA DATA UART0 Receive/Transfer FIFO Register. 0x0 -1 read-write n 0x0 0x0 _8_bitReceivedData Receive FIFO Register Reading this register will return data from the receive data FIFO. By reading this register, the UART will return the 8-bit data received from Rx pin (LSB first). 0 8 read-write FCR FCR UART0 FIFO Control Register. 0x8 -1 read-write n 0x0 0x0 RFITL Receive FIFO Interrupt (RDA_INT) Trigger Level When the number of bytes in the receive FIFO equals the RFITL then the RDA_IF will be set and, if enabled, an RDA_INT interrupt will generated. Value : INTR_RDA Trigger Level (Bytes) 0 : 1 1 : 4 2 : 8 4 4 read-write RFR Receive FIFO Reset When RFR is set, all the bytes in the receive FIFO are cleared and receive internal state machine is reset. Note: This bit will auto-clear after 3 UART engine clock cycles. 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the receive internal state machine and pointers #1 RTS_TRIG_LEVEL RTS Trigger Level for Auto-flow Control Sets the FIFO trigger level when auto-flow control will de-assert RTS (request-to-send). Value : Trigger Level (Bytes) 0 : 1 1 : 4 2 : 8 16 4 read-write TFR Transmit FIFO Reset When TFR is set, all the bytes in the transmit FIFO are cleared and transmit internal state machine is reset. Note: This bit will auto-clear after 3 UART engine clock cycles. 2 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the transmit internal state machine and pointers #1 FSR FSR UART0 FIFO Status Register. 0x18 -1 read-write n 0x0 0x0 BIF Break Interrupt Flag This bit is set to a logic 1 whenever the receive data input (Rx) is held in the space state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). It is reset whenever the CPU writes 1 to this bit. 6 1 read-write FEF Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit. 5 1 read-write PEF Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit. 4 1 read-write RX_EMPTY Receive FIFO Empty (Read Only) This bit indicates whether the Rx FIFO is empty or not. When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only RX_FULL Receive FIFO Full (Read Only) This bit indicates whether the Rx FIFO is full or not. This bit is set when Rx FIFO is full otherwise it is cleared by hardware. 15 1 read-only RX_OVF_IF Rx Overflow Error Interrupt Flag If the Rx FIFO (UART0->DATA) is full, and an additional byte is received by the UART, an overflow condition will occur and set this bit to logic 1. It will also generate a BUF_ERR_IF event and interrupt if enabled. NOTE: This bit is cleared by writing 1 to itself. 0 1 read-write RX_POINTER Rx FIFO pointer (Read Only) This field returns the Rx FIFO buffer pointer. It is the number of bytes available for read in the Rx FIFO. When UART receives one byte from external device, RX_POINTER is incremented. When one byte of Rx FIFO is read by CPU, RX_POINTER is decremented. 8 6 read-only TE Transmitter Empty (Read Only) Bit is set by hardware when Tx FIFO is empty and the STOP bit of the last byte has been transmitted. Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed. NOTE: This bit is read only. 28 1 read-only TX_EMPTY Transmit FIFO Empty (Read Only) This bit indicates whether the Tx FIFO is empty or not. When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared after writing data to FIFO (Tx FIFO not empty). 22 1 read-only TX_FULL Transmit FIFO Full (Read Only) This bit indicates whether the Tx FIFO is full or not. 23 1 read-only TX_OVF_IF Tx Overflow Error Interrupt Flag If the Tx FIFO (UART0->DATA) is full, an additional write to UART0->DATA will cause an overflow condition and set this bit to logic 1. It will also generate a BUF_ERR_IF event and interrupt if enabled. NOTE: This bit is cleared by writing 1 to itself. 24 1 read-write TX_POINTER Tx FIFO Pointer (Read Only) This field returns the Tx FIFO buffer pointer. When CPU writes a byte into the Tx FIFO, TX_POINTER is incremented. When a byte from Tx FIFO is transferred to the Transmit Shift Register, TX_POINTER is decremented. 16 6 read-only FUNSEL FUNSEL UART0 Function Select Register. 0x30 -1 read-write n 0x0 0x0 IrDA_EN Enable IrDA Function 1 1 read-write 0 UART Function #0 1 Enable IrDA Function #1 LIN_EN Enable LIN Function Note that IrDA and LIN functions are mutually exclusive: both cannot be active at same time. 0 1 read-write 0 UART Function #0 1 Enable LIN Function #1 IER IER UART0 Interrupt Enable Register. 0x4 -1 read-write n 0x0 0x0 AUTO_CTS_EN CTS Auto Flow Control Enable When CTS auto-flow is enabled, the UART will send data to external device when CTS input is asserted (UART will not send data to device until CTS is asserted). 13 1 read-write 0 Disable CTS auto flow control #0 1 Enable #1 AUTO_RTS_EN RTS Auto Flow Control Enable When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals FCR.RTS_TRIG_LEVEL, the UART will de-assert the RTS signal. 12 1 read-write 0 Disable RTS auto flow control #0 1 Enable #1 BUF_ERR_IEN Buffer Error Interrupt Enable 5 1 read-write 0 Mask off BUF_ERR_INT #0 1 Enable IBUF_ERR_INT #1 DMA_RX_EN Receive DMA Enable If enabled, the UART will request DMA service when data is available in receive FIFO. 15 1 read-write DMA_TX_EN Transmit DMA Enable If enabled, the UART will request DMA service when space is available in transmit FIFO. 14 1 read-write LIN_RX_BRK_IEN LIN RX Break Field Detected Interrupt Enable 8 1 read-write 0 Mask off Lin bus Rx break field interrupt #0 1 Enable Lin bus Rx break field interrupt #1 MS_IEN Modem Status Interrupt Enable 3 1 read-write 0 Mask off MODEM_INT #0 1 Enable MODEM_INT #1 RDA_IEN Receive Data Available Interrupt Enable. 0 1 read-write 0 Mask off RDA_INT #0 1 Enable RDA_INT #1 RLS_IEN Receive Line Status Interrupt Enable 2 1 read-write 0 Mask off RLS_INT #0 1 Enable RLS_INT #1 RTO_IEN Receive Time out Interrupt Enable 4 1 read-write 0 Mask off TOUT_INT #0 1 Enable TOUT_INT #1 THRE_IEN Transmit FIFO Register Empty Interrupt Enable 1 1 read-write 0 Mask off THRE_INT #0 1 Enable THRE_INT #1 TOC_EN Time-Out Counter Enable 11 1 read-write 0 Disable Time-out counter #0 1 Enable #1 IRCR IRCR UART0 IrDA Control Register. 0x28 -1 read-write n 0x0 0x0 LOOPBACK IrDA Loopback Test Mode Loopback Tx to Rx. 2 1 read-write RX_INV_EN Receive Inversion Enable 6 1 read-write 0 No inversion #0 1 Invert Rx input signal #1 TX_INV_EN Transmit inversion enable 5 1 read-write 0 No inversion #0 1 Invert Tx output signal #1 TX_SELECT Transmit/Receive Selection 1 1 read-write 0 Enable IrDA receiver #0 1 Enable IrDA transmitter #1 ISR ISR UART0 Interrupt Status Register. 0x1C -1 read-write n 0x0 0x0 BUF_ERR_IF Buffer Error Interrupt Flag (Read Only) This bit is set when either the Tx or Rx FIFO overflows (FSR.TX_OVF_IF or FSR.RX_OVF_IF is set). When BUF_ERR_IF is set, the serial transfer may be corrupted. If IER.BUF_ERR_IEN is enabled a CPU interrupt request will be generated. NOTE: This bit is cleared when both FSR.TX_OVF_IF and FSR.RX_OVF_IF are cleared. 5 1 read-only BUF_ERR_INT Buffer Error Interrupt Indicator to Interrupt Controller Logical AND of IER.BUF_ERR_IEN and BUF_ERR_IF. 13 1 read-write DMAmodeBits DMA Mode Bits DMA mode equivalent following interrupt indicators and flags. See Table 5107 and normal mode descriptions below. In DMA mode (either DMA transmit or receive requests are active) these bits are generated rather than the normal use bits below. 16 16 read-write LIN_Rx_Break_IF LIN Bus Rx Break Field Detected Flag This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1. 7 1 read-write LIN_Rx_Break_INT LIN Bus Rx Break Field Detected Interrupt Indicator to Interrupt Controller Logical AND of IER.LIN_RX_BRK_IEN and LIN_Rx_Break_IF. 15 1 read-write MODEM_IF MODEM Interrupt Flag (Read Only) NOTE: This bit is read only and reset when bit MSR.DCTSF is cleared by a write 1. 3 1 read-only MODEM_INT MODEM Status Interrupt Indicator to Interrupt Logical AND of IER.MS_IEN and MODEM_IF. 11 1 read-write RDA_IF Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the Rx FIFO equals FCR.RFITL then the RDA_IF will be set. If IER.RDA_IEN is enabled, the RDA interrupt will be generated. NOTE: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL). 0 1 read-only RDA_INT Receive Data Available Interrupt Indicator to Interrupt Controller Logical AND of IER.RDA_IEN and RDA_IF. 8 1 read-write RLS_IF Receive Line Status Interrupt Flag (Read Only) This bit is set when the Rx receive data has a parity, framing or break error (at least one of, FSR.BIF, FSR.FEF and FSR.PEF, is set). If IER.RLS_IEN is enabled, the RLS interrupt will be generated. NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. 2 1 read-only RLS_INT Receive Line Status Interrupt Indicator to Interrupt Controller Logical AND of IER.RLS_IEN and RLS_IF. 10 1 read-write THRE_IF Transmit Holding Register Empty Interrupt Flag (Read Only) This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If IER.THRE_IEN is enabled, the THRE interrupt will be generated. NOTE: This bit is read only and it will be cleared when writing data into the Tx FIFO. 1 1 read-only THRE_INT Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller Logical AND of IER.THRE_IEN and THRE_IF. 9 1 read-write TOUT_IF Time Out Interrupt Flag (Read Only) This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If IER.TOUT_IEN is enabled a CPU interrupt request will be generated. NOTE: This bit is read only and user can read FIFO to clear it. 4 1 read-only TOUT_INT Time Out Interrupt Indicator to Interrupt Controller Logical AND of IER.RTO_IEN and TOUT_IF. 12 1 read-write LCR LCR UART0 Line Control Register. 0xC -1 read-write n 0x0 0x0 BCB Break Control Bit When this bit is set to logic 1, the serial data output (Tx) is forced to the 'Space' state (logic 0). Normal condition is serial data output is 'Mark' state. This bit acts only on Tx and has no effect on the transmitter logic. 6 1 read-write EPE Even Parity Enable This bit has effect only when PBE (parity bit enable) is set. 4 1 read-write 0 Odd number of logic 1's are transmitted or checked in the data word and parity bits #0 1 Even number of logic 1's are transmitted or checked in the data word and parity bits #1 NSB Number of STOP bits 2 1 read-write 0 One STOP bit is generated after the transmitted data #0 1 Two STOP bits are generated when 6-, 7- and 8-bit word length is selected One and a half STOP bits are generated in the transmitted data when 5-bit word length is selected #1 PBE Parity Bit Enable 3 1 read-write 0 Parity bit is not generated (transmit data) or checked (receive data) during transfer #0 1 Parity bit is generated or checked between the last data word bit and stop bit of the serial data #1 SPE Stick Parity Enable 5 1 read-write 0 Disable stick parity #0 1 When bits PBE and SPE are set 'Stick Parity' is enabled. If EPE=0 the parity bit is transmitted and checked as always set, if EPE=1, the parity bit is transmitted and checked as always cleared #1 WLS Word Length Select 0 (5bits), 1(6bits), 2(7bits), 3(8bits) 0 2 read-write LINCON LINCON UART0 LIN Control Register. 0x2C -1 read-write n 0x0 0x0 LINBCNT UART LIN Break Field Length Count This field indicates a 4-bit LIN Tx break field count. NOTE: This break field length is LINBCNT + 2 0 4 read-write LIN_RX_EN LIN RX Enable 6 1 read-write 0 Disable LIN Rx mode #0 1 Enable LIN Rx mode #1 LIN_TX_EN LIN TX Break Mode Enable NOTE: When Tx break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 Disable LIN Tx Break Mode #0 1 Enable LIN Tx Break Mode #1 MCR MCR UART0 Modem Control Register. 0x10 -1 read-write n 0x0 0x0 LBME Loopback Mode Enable 4 1 read-write 0 Disable #0 1 Enable #1 RTS_ACT Request-to-Send (RTS) Active Trigger Level This bit can change the RTS trigger level. 9 1 read-write 0 RTS is active low level #0 1 RTS is active high level #1 RTS_SET RTS (Request-To-Send) Signal If IER.AUTO_RTS_EN = 0, this bit controls whether RTS pin is active or not. 1 1 read-write 0 Drive RTS inactive ( = ~RTS_ACT) #0 1 Drive RTS active ( = RTS_ACT) #1 RTS_ST RTS Pin State (read only) This bit is the pin status of RTS. 13 1 read-only MSR MSR UART0 Modem Status Register. 0x14 -1 read-write n 0x0 0x0 CTS_ACT Clear-to-Send (CTS) Active Trigger Level This bit can change the CTS trigger level. 8 1 read-write 0 CTS is active low level #0 1 CTS is active high level #1 CTS_ST CTS Pin Status (read only) This bit is the pin status of CTS. 4 1 read-only DCTSF Detect CTS State Change Flag This bit is set whenever CTS input has state change. It will generate Modem interrupt to CPU when IER.MS_IEN = 1 NOTE: This bit is cleared by writing 1 to itself. 0 1 read-write TOR TOR UART0 Time Out Register 0x20 -1 read-write n 0x0 0x0 TOIC Time Out Interrupt Comparator The time out counter resets and starts counting whenever the Rx FIFO receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (TOUT_INT) is generated if IER.RTO_IEN is set. A new incoming data word or RX FIFO empty clears TOUT_IF. The period of the time out counter is the baud rate. 0 7 read-write WDT WDT Register Map WDT 0x0 0x0 0x4 registers n WTCR WTCR Watchdog Timer Control Register 0x0 -1 read-write n 0x0 0x0 WTE Watchdog Timer Enable 7 1 read-write 0 Disable the Watchdog timer (This action will reset the internal counter) #0 1 Enable the Watchdog timer #1 WTIE Watchdog Timer Interrupt Enable 6 1 read-write 0 Disable the Watchdog timer interrupt #0 1 Enable the Watchdog timer interrupt #1 WTIF Watchdog Timer Interrupt Flag If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed. NOTE: This bit is cleared by writing 1 to this bit. 3 1 read-write 0 Watchdog timer interrupt has not occurred #0 1 Watchdog timer interrupt has occurred #1 WTIS Watchdog Timer Interval Select These three bits select the timeout interval for the Watchdog timer, a watchdog reset will occur 1024 clock cycles later if WDG not reset. The timeout is given by: Interrupt Timeout = 2^(2xWTIS+4) x WDT_CLK Reset Timeout = (2^(2xWTIS+4) +1024) x WDT_CLK Where WDT_CLK is the period of the Watchdog Timer clock source. 8 3 read-write WTR Clear Watchdog Timer Set this bit will clear the Watchdog timer. NOTE: This bit will auto clear after few clock cycle 0 1 read-write 0 Writing 0 to this bit has no effect #0 1 Reset the contents of the Watchdog timer #1 WTRE Watchdog Timer Reset Enable Setting this bit will enable the Watchdog timer reset function. 1 1 read-write 0 Disable Watchdog timer reset function #0 1 Enable Watchdog timer reset function #1 WTRF Watchdog Timer Reset Flag When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If WTRE is disabled, then the Watchdog timer has no effect on this bit. NOTE: This bit is cleared by writing 1 to this bit. 2 1 read-write 0 Watchdog timer reset has not occurred #0 1 Watchdog timer reset has occurred #1