nuvoTon NANO103AE_v1 2024.05.02 NANO103AE_v1 SVD file 8 32 ACMP0 ACMP0 Register Map ACMP0 0x0 0x0 0xC registers n ACMP_CTL0 ACMP_CTL0 Analog Comparator 0 Control Register 0x0 read-write n 0x0 0x0 ACMPEN Comparator Enable Bit 0 1 read-write 0 Comparator 0 Disabled #0 1 Comparator 0 Enabled #1 ACMPIE Comparator Interrupt Enable Bit 1 1 read-write 0 Comparator 0 interrupt Disabled #0 1 Comparator 0 interrupt Enabled. If WKEN (ACMP_CTL0[31]) is set to 1, the wake-up interrupt function will be enabled as well #1 HYSEN Comparator Hysteresis Enable Bit 2 1 read-write 0 Comparator 0 hysteresis Disabled #0 1 Comparator 0 hysteresis Enabled #1 NEGSEL Comparator Negative Input Selection 4 2 read-write 0 ACMP0_N pin #00 1 Internal comparator reference voltage (CRV) #01 2 Internal reference voltage (Int_VREF) #10 3 AVSS pin #11 WKEN Power-down Wake-up Enable Bit 31 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 ACMP_STATUS ACMP_STATUS Analog Comparator Status Register 0x4 read-write n 0x0 0x0 ACMPIF ComparatorInterrupt Flag This bit is set by hardware whenever the comparator 0 output changes state. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1 Note: Write 1 to clear this bit to 0. 0 1 read-write ACMPO ComparatorOutput\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.\nNote: This bit is read only. 1 1 read-write ACMP_VREF ACMP_VREF Analog Comparator Reference Voltage Control Register 0x8 read-write n 0x0 0x0 CRVCTL Comparator Reference Voltage Setting 0 4 read-write CRVEN CRV Enable Bit 4 1 read-write 0 CRV Disabled #0 1 CRV Enabled #1 CRVSSEL CRV Source Voltage Selection 5 1 read-write 0 VDDA is selected as CRV source voltage #0 1 The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage #1 ADC ADC Register Map ADC 0x0 0x0 0x20 registers n 0x30 0x2C registers n 0x60 0x18 registers n CALCTL ADC_CALCTL A/D Calibration Control Register 0x68 -1 read-write n 0x0 0x0 CALDONE Calibrate Functional Block Done\nNote:This bit is set by hardware and auto cleard by hardware, This bit can also be cleared by software writing 1. 2 1 read-write 0 Not yet #0 1 Selected calibrationfunctional block complete #1 CALEN Calibration Function EnableBit\nEnable this bit to turn on the calibration function block. 0 1 read-write 0 Bypass calibrationfunctionalblock #0 1 Enabledcalibrationfunctionalblock #1 CALSEL Calibration Functional Block Selection 3 1 read-write 0 Load calibration functional block #0 1 Calibration functional block #1 CALSTART Calibration Functional Block Start 1 1 read-write 0 Stops calibration functional block #0 1 Starts calibration functional block #1 CALWORD ADC_CALWORD A/D Calibration Load word Register 0x6C read-write n 0x0 0x0 CALWORD Calibration Word Bits Write to this register with the previous calibration word before load calibration action, read this register after calibration done. Note:The calibration block contains two parts CALIBRATION and LOAD CALIBRATION if thecalibration block configure as CALIBRATION then this register represent the result of calibration when calibration is completed if configure as LOAD CALIBRATION configure this register before loading calibration action, after loading calibration complete, the loaded calibration word will apply to the ADC while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done. 0 7 read-write CHEN ADC_CHEN A/D Channel Enable Register 0x4C read-write n 0x0 0x0 CHEN0 Analog Input Channel 0 Enable Bit (Convert Input Voltage From PA.0)\nNote:If software enables more than one channel, the channel with the smallest number will be selected and the other enabled channels will be ignored. 0 1 read-write 0 Channel 0 Disabled #0 1 Channel 0 Enabled #1 CHEN1 Analog Input Channel 1 EnableBit (Convert Input Voltage From PA.1) 1 1 read-write 0 Channel 1 Disabled #0 1 Channel 1 Enabled #1 CHEN12 Analog Input Channel 12 Enable Bit (Convert VBG) 12 1 read-write 0 Channel 12 Disabled #0 1 Channel 12 Enabled #1 CHEN13 Analog Input Channel 13 Enable Bit (Convert VBAT) 13 1 read-write 0 Channel 13 Disabled #0 1 Channel 13 Enabled #1 CHEN14 Analog Input Channel 14 EnableBit (Convert VTEMP) 14 1 read-write 0 Channel 14 Disabled #0 1 Channel 14 Enabled #1 CHEN15 Analog Input Channel 15 EnableBit (Convert Int_VREF) 15 1 read-write 0 Channel 15 Disabled #0 1 Channel 15 Enabled #1 CHEN16 Analog Input Channel 16 EnableBit (Convert AVDD) 16 1 read-write 0 Channel 16 Disabled #0 1 Channel 16 Enabled #1 CHEN17 Analog Input Channel 17 EnableBit (ConvertAVSS) 17 1 read-write 0 Channel 17 Disabled #0 1 Channel 17 Enabled #1 CHEN2 Analog Input Channel 2 EnableBit (Convert Input Voltage From PA.2) 2 1 read-write 0 Channel 2 Disabled #0 1 Channel 2 Enabled #1 CHEN3 Analog Input Channel 3 EnableBit (Convert Input Voltage From PA.3) 3 1 read-write 0 Channel 3 Disabled #0 1 Channel 3 Enabled #1 CHEN4 Analog Input Channel 4 EnableBit (Convert Input Voltage From PA.4) 4 1 read-write 0 Channel 4 Disabled #0 1 Channel 4 Enabled #1 CHEN5 Analog Input Channel 5 EnableBit (Convert Input Voltage From PA.5) 5 1 read-write 0 Channel 5 Disabled #0 1 Channel 5 Enabled #1 CHEN6 Analog Input Channel 6 EnableBit (Convert Input Voltage From PA.6) 6 1 read-write 0 Channel 6 Disabled #0 1 Channel 6 Enabled #1 CHEN7 Analog Input Channel 7 EnableBit (Convert Input Voltage From PA.7) 7 1 read-write 0 Channel 7 Disabled #0 1 Channel 7 Enabled #1 CMP0 ADC_CMP0 A/D Compare Register 0 0x50 read-write n 0x0 0x0 ADCMPEN A/D Compare EnableBit\nSet 1 to this bit to enable comparing CMPDAT (ADC_CMPx[27:16]) with specified channel conversion results when converted data is loaded into the ADC_DATx register.\nNote:When this bit is set to 1 and CMPMCNT (ADC_CMPx[11:8]) is 0, the ADCMPFx (ADC_STATUS[2:1]) will be set once the match is hit. 0 1 read-write 0 Compare function Disabled #0 1 Compare function Enabled #1 ADCMPIE A/D Compare Interrupt EnableBit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT (ADC_CMPx[11:8]), ADCMPFx(ADC_STATUS[2:1]) bit will be asserted, in the meanwhile, if ADCMPIE(ADC_CMPx[1]) is set to 1, a compare interrupt request will generate. 1 1 read-write 0 Compare function interrupt Disabled #0 1 Compare function interrupt Enabled #1 CMPCH Compare Channel Selection\nSet this field to select which channel's result to be compared.\nNote: Valid setting of this field is channel 0~17, but channel 8~12 are reserved. 3 5 read-write CMPCOND Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set. 2 1 read-write 0 Set the compare condition as that when a A/D conversion result is less than the CMPDAT(ADC_CMPx[27:16]), the internal match counter will increase one #0 1 Set the compare condition as that when a A/D conversion result is more than or equal to the CMPDAT(ADC_CMPx[27:16]), the internal match counter will increase one #1 CMPDAT Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software. 16 12 read-write CMPMCNT Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]), the internal match counter will increase 1. \nNote:When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set. 8 4 read-write CMP1 ADC_CMP1 A/D Compare Register 1 0x54 read-write n 0x0 0x0 CTL ADC_CTL A/D Control Register 0x48 -1 read-write n 0x0 0x0 ADCEN A/D Converter EnableBit\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption. 0 1 read-write 0 A/D Converter Disabled #0 1 A/D Converter Enabled #1 ADCIEN A/D Interrupt EnableBit\nA/D conversion end interrupt request is generated if ADCIEN(ADC_CTL[1]) bit is set to 1. 1 1 read-write 0 A/D interrupt function Disabled #0 1 A/D interrupt function Enabled #1 ADMD A/D Converter Operation Mode 2 2 read-write 0 Single conversion #00 1 Reserved #01 2 Single-cycle scan #10 3 Continuous scan #11 DIFF Differential Mode Selection\nNote: Calibration should calibrated each time when switching between single-ended and differential mode. 10 1 read-write 0 ADC is operated in single-ended mode #0 1 ADC is operated in differential mode #1 HWTRGCOND Hardware External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state. 6 2 read-write 0 Low level #00 1 High level #01 2 Falling edge #10 3 Rising edge #11 HWTRGEN Hardware External Trigger EnableBit\nEnable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled, ADC starts to convert by the selected hardware trigger source. 8 1 read-write 0 External trigger Disabled #0 1 External trigger Enabled #1 HWTRGSEL Hardware Trigger Source Select Bit\nIn hardware trigger mode, ADC starts to convert by the external trigger from STADC pin or PWM trigger.\nNote:Software should disable HWTRGEN (ADC_CTL[8]) and clear SWTRG (ADC_CTL[11]) before change HWTRGSEL (ADC_CTL[5:4]). 4 2 read-write 0 A/D conversion is started by external STADC pin #00 1 Reserved #01 2 Reserved #10 3 A/D conversion is started by PWM0 trigger #11 PTEN PDMA Transfer EnableBit\nWhen A/D conversion is completed, the converted data is loaded into ADC_DATx, software can enable this bit to generate a PDMA data transfer request. 9 1 read-write 0 PDMA data transfer Disabled #0 1 PDMA data transfer in ADC_DATx Enabled #1 REFSEL Reference Voltage Source Selection 16 2 read-write 0 Select #00 1 Select #01 2 Select #10 3 Reserved #11 RESSEL Resolution Selection 18 2 read-write 0 6-bit. ADC result will put at RESULT(ADC_DATx[5:0]) #00 1 8-bit. ADC result will put at RESULT(ADC_DATx[7:0]) #01 2 10-bit. ADC result will put at RESULT(ADC_DATx[9:0]) #10 3 12-bit. ADC result will put at RESULT(ADC_DATx[11:0]) #11 SWTRG Software Trigger A/D Conversion Start\nADC can be start to convert from three sources: software write, external pin STADC and PWM trigger. SWTRG(ADC_CTL[11]) is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels. In continuous scan mode, A/D conversion is continuously performed sequentially unless software writes 0 to this bit or chip reset.\nNote: After ADC conversion is done, SW needs to wait at least one ADC clock before to set this bit high again. 11 1 read-write 0 Conversion stopped and A/D converter enter idle state #0 1 Conversion starts #1 TMPDMACNT Timer Event PDMA Count\nWhen each timer event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting.\nNote: The total amount of PDMA transferring data should be set in PDMA byte count register. When PDMA finish is set, ADC will not be enabled and will start transfer even though the timer event occurred. 24 8 read-write TMSEL Select A/D Enable Time-out Source\nSelects one of four timer events sourceto trigger ADC starts to convert. 12 2 read-write 0 TMR0 #00 1 TMR1 #01 2 TMR2 #10 3 TMR3 #11 TMTRGMOD Timer Event Trigger ADC Conversion Mode\nNote1: setting TMSEL (ADC_CTL[13:12]) to select timer event from timer0~3.\nNote2:If timer event is used as ADC trigger source, ADCEN (ADC_CTL[0]) needs to be disabled. 15 1 read-write 0 Timer event trigger ADC conversion disabled #0 1 ADC can be start to conversion by timer out event #1 DAT0 ADC_DAT0 A/D Data Register 0 0x0 read-only n 0x0 0x0 OV Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register, OVis set to 1. It is cleared by hardware after the ADC_DATx register is read. 17 1 read-only 0 Data in RESULT (ADC_DAT[11:0]) is recent conversion result #0 1 Data in RESULT (ADC_DAT[11:0]) overwrote #1 RESULT A/D Conversion Result\nThis field contains conversion result of ADC. 0 12 read-only VALID Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read. 16 1 read-only 0 Data in RESULT (ADC_DAT[11:0]) bits is not valid #0 1 Data in RESULT (ADC_DAT[11:0]) bits is valid #1 DAT1 ADC_DAT1 A/D Data Register 1 0x4 read-write n 0x0 0x0 DAT12 ADC_DAT12 A/D Data Register 12 0x30 read-write n 0x0 0x0 DAT13 ADC_DAT13 A/D Data Register 13 0x34 read-write n 0x0 0x0 DAT14 ADC_DAT14 A/D Data Register 14 0x38 read-write n 0x0 0x0 DAT15 ADC_DAT15 A/D Data Register 15 0x3C read-write n 0x0 0x0 DAT16 ADC_DAT16 A/D Data Register 16 0x40 read-write n 0x0 0x0 DAT17 ADC_DAT17 A/D Data Register 17 0x44 read-write n 0x0 0x0 DAT2 ADC_DAT2 A/D Data Register 2 0x8 read-write n 0x0 0x0 DAT3 ADC_DAT3 A/D Data Register 3 0xC read-write n 0x0 0x0 DAT4 ADC_DAT4 A/D Data Register 4 0x10 read-write n 0x0 0x0 DAT5 ADC_DAT5 A/D Data Register 5 0x14 read-write n 0x0 0x0 DAT6 ADC_DAT6 A/D Data Register 6 0x18 read-write n 0x0 0x0 DAT7 ADC_DAT7 A/D Data Register 7 0x1C read-write n 0x0 0x0 EXTSMPT0 ADC_EXTSMPT0 A/D Sampling Time Counter Register 0 0x70 read-write n 0x0 0x0 EXTSMPT_CH0 Additional ADC Sample Clockfor Channel 0\nIf the ADC input is unstable, user can set this register to increase the sampling time to get a stable ADC input signal. The default sampling time is 1 ADC clocks. The additional clock number will be inserted to lengthen the sampling clock. 0 4 read-write 0 Number of additional clock cycles is 0 0 1 Number of additional clock cycles is 1 1 10 Number of additional clock cycles is 512 10 11 Number of additional clock cycles is 1024 11 12 Number of additional clock cycles is 1024 12 13 Number of additional clock cycles is 1024 13 14 Number of additional clock cycles is 1024 14 15 Number of additional clock cycles is 1024 15 2 Number of additional clock cycles is 2 2 3 Number of additional clock cycles is 4 3 4 Number of additional clock cycles is 8 4 5 Number of additional clock cycles is 16 5 6 Number of additional clock cycles is 32 6 7 Number of additional clock cycles is 64 7 8 Number of additional clock cycles is 128 8 9 Number of additional clock cycles is 256 9 EXTSMPT_CH1 Additional ADC Sample Clockfor Channel 1\nThe same as channel 0 description. 4 4 read-write EXTSMPT_CH2 Additional ADC Sample Clockfor Channel 2\nThe same as channel 0 description. 8 4 read-write EXTSMPT_CH3 Additional ADC Sample Clockfor Channel 3\nThe same as channel 0 description. 12 4 read-write EXTSMPT_CH4 Additional ADC Sample Clockfor Channel 4\nThe same as channel 0 description. 16 4 read-write EXTSMPT_CH5 Additional ADC Sample Clockfor Channel 5\nThe same as channel 0 description. 20 4 read-write EXTSMPT_CH6 Additional ADC Sample Clockfor Channel 6\nThe same as channel 0 description. 24 4 read-write EXTSMPT_CH7 Additional ADC Sample Clockfor Channel 7\nThe same as channel 0 description. 28 4 read-write EXTSMPT1 ADC_EXTSMPT1 A/D Sampling Time Counter Register 1 0x74 read-write n 0x0 0x0 EXTSMPT_INTCH Additional ADC Sample Clock for Internal Channel (VTEMP, AVDD, AVSS, Int_VREF, VBAT, VBG)\nThe same as channel 0 description. 16 4 read-write PDMA ADC_PDMA A/D PDMA Current Transfer Data Register 0x60 read-only n 0x0 0x0 AD_PDMA ADC PDMA Current Transfer Data(Read Only)\nDuring PDMAtransfer, reading these bits can monitor the current PDMA transfer data. 0 12 read-only PWD ADC_PWD A/D Power Management Register 0x64 -1 read-write n 0x0 0x0 PWDCALEN Power Up Calibration Function EnableBit\nNote:This bit works together with CALSEL (ADC_CALCTL[3]),see the following\n{PWDCALEN,CALFBSEL}Description:\nPWDCALEN is 0 and CALFBSEL is 0: No need to calibrate. \nPWDCALEN is 0 and CALFBSEL is 1: No need to calibrate.\nPWDCALEN is 1 and CALFBSEL is 0: Load calibration word when power up.\nPWDCALEN is 1 and CALFBSEL is 1: Calibrate when power up. 1 1 read-write 0 Power up without calibration #0 1 Power up with calibration #1 PWDMOD ADC Power Saving Mode\nSet this bit fields to select ADC power saving mode.\nNote1: Different power saving mode has different power down/up sequence.To avoid ADC powering up with wrong sequence, user must keep PWMOD (ADC_PWD[3:2]) consistent each time in power down and power up. \nNote2:While the ADC is powered up from power saving mode (set to 00b/01b/11b) without calibration, the PWDCALEN(ADC_PWD[1]) is set to 0, and the calibration value will be reset. 2 2 read-write 0 Reserved #00 1 ADC Power-down mode #01 2 ADC Standby mode #10 3 Reserved #11 PWUPRDY ADC Power-up Sequence Completed and Ready for Conversion 0 1 read-write 0 ADC is not ready for conversion, itmay be in power saving state or in the progress of power up #0 1 ADC is ready for conversion #1 STATUS ADC_STATUS A/D Status Register 0x58 read-write n 0x0 0x0 ADCMPF0 A/D Compare Flag0\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP0, this bit is set to 1.\nThis flag can be cleared by writing 1 to it.\nNote: This flag can be cleared by software writing 1 to it, when this flag is set, the matching counter will be reset to 0,and continue to count when user writes 1 to clear ADCMPF0 (ADC_STATUS[1]). 1 1 read-write 0 Conversion result in ADC_DATx does not meet the CMPDAT (ADC_CMP0[27:16]) setting #0 1 Conversion result in ADC_DATx meets the CMPDAT (ADC_CMP0[27:16]) setting #1 ADCMPF1 A/D Compare Flag1\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP1, this bit is set to 1.\nNote: This flag can be cleared by software writing 1 to it, when this flag is set, the matching counter will be reset to 0,and continue to count when user writes 1 to clear ADCMPF1 (ADC_STATUS[2]). 2 1 read-write 0 Conversion result in ADC_DATx does not meet the CMPDAT (ADC_CMP1[27:16]) setting #0 1 Conversion result in ADC_DATx meets the CMPDAT (ADC_CMP1[27:16]) setting #1 ADIF A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion, ADIF (ADC_STATUS[0]) is set to 1 at these two conditions:\nWhen A/D conversion ends in single mode\nWhen A/D conversion ends on all specified channels in scan mode.\nNote: This bit can be cleared to 0 by software writing 1. 0 1 read-write BUSY BUSY/IDLE(Read Only)\nNote:This bit is mirror of SWTRG (ADC_CTL [11]) bit. 3 1 read-only 0 A/D converter is in idle state #0 1 A/D converter is busy at conversion #1 CHANNEL Current Conversion Channel(Read Only) 4 5 read-only INITRDY ADC Initial Ready by Power-up Sequence Completed\nNote: This bit will be set after system reset occurred and automatically cleared by power-up event. 16 1 read-write 0 ADC not powered up after system reset #0 1 ADC has been powered up since the last system reset #1 CLK CLK Register Map CLK 0x0 0x0 0x2C registers n 0x30 0x1C registers n AHBCLK CLK_AHBCLK AHB Devices Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 GPIOCKEN GPIO Controller Clock Enable Control 0 1 read-write 0 GPIO peripheral clock Disabled #0 1 GPIO peripheral clock Enabled #1 ISPCKEN Flash ISP Controller Clock Enable Bit 2 1 read-write 0 Flash ISP peripheral clock Disabled #0 1 Flash ISP peripheral clock Enabled #1 PDMACKEN PDMA Controller Clock Enable Bit 1 1 read-write 0 PDMA peripheral clock Disabled #0 1 PDMA peripheral clock Enabled #1 SRAMCKEN SRAM Controller Clock Enable Control Bit 4 1 read-write 0 SRAM peripheral clock Disabled #0 1 SRAM peripheral clock Enabled #1 STCKEN System Tick Clock Enable Control Bit 5 1 read-write 0 System Tick Clock Disabled #0 1 System Tick Clock Enabled #1 APBCLK CLK_APBCLK APB Devices Clock Enable Control Register 0x8 -1 read-write n 0x0 0x0 ACMP0CKEN ACMP0 Clock Enable Control 11 1 read-write 0 ACMP0 Clock Disabled #0 1 ACMP0 Clock Enabled #1 ADCCKEN Analog-digital-converter (ADC) Clock Enable Control 28 1 read-write 0 ADC Clock Disabled #0 1 ADC Clock Enabled #1 CLKOCKEN ClocK Output Clock Enable Control 6 1 read-write 0 Clock Output Clock Disabled #0 1 Clock Output Clock Enabled #1 DSRCCKEN DSRC Clock Enable Control 7 1 read-write 0 DSRC Clock Disabled #0 1 DSRC Clock Enabled #1 I2C0CKEN I2C0 Clock Enable Control 8 1 read-write 0 I2C0 Clock Disabled #0 1 I2C0 Clock Enabled #1 I2C1CKEN I2C1 Clock Enable Control 9 1 read-write 0 I2C1 Clock Disabled #0 1 I2C1 Clock Enabled #1 PWM0CKEN PWM0 Clock Enable Control 20 1 read-write 0 PWM0 Clock Disabled #0 1 PWM0 Clock Enabled #1 RTCCKEN Real-time-clock Clock Enable Control \nThis bit is used to control the RTC APB clock only, The RTC engine Clock Source is from LXT. 1 1 read-write 0 Real-time-clock Clock Disabled #0 1 Real-time-clock Clock Enabled #1 SC0CKEN SmartCard 0 Clock Enable Control 30 1 read-write 0 SmartCard 0 Clock Disabled #0 1 SmartCard 0 Clock Enabled #1 SC1CKEN SmartCard 1 Clock Enable Control 31 1 read-write 0 SmartCard 1 Clock Disabled #0 1 SmartCard 1 Clock Enabled #1 SPI0CKEN SPI0 Clock Enable Control 12 1 read-write 0 SPI0 Clock Disabled #0 1 SPI0 Clock Enabled #1 SPI1CKEN SPI1 Clock Enable Control 13 1 read-write 0 SPI1 Clock Disabled #0 1 SPI1 Clock Enabled #1 SPI2CKEN SPI2 Clock Enable Control 14 1 read-write 0 SPI2 Clock Disabled #0 1 SPI2 Clock Enabled #1 SPI3CKEN SPI3 Clock Enable Control 15 1 read-write 0 SPI3 Clock Disabled #0 1 SPI3 Clock Enabled #1 TMR0CKEN Timer0 Clock Enable Control 2 1 read-write 0 Timer0 Clock Disabled #0 1 Timer0 Clock Enabled #1 TMR1CKEN Timer1 Clock Enable Control 3 1 read-write 0 Timer1 Clock Disabled #0 1 Timer1 Clock Enabled #1 TMR2CKEN Timer2 Clock Enable Control 4 1 read-write 0 Timer2 Clock Disabled #0 1 Timer2 Clock Enabled #1 TMR3CKEN Timer3 Clock Enable Control 5 1 read-write 0 Timer3 Clock Disabled #0 1 Timer3 Clock Enabled #1 UART0CKEN UART0 Clock Enable Control 16 1 read-write 0 UART0 Clock Disabled #0 1 UART0 Clock Enabled #1 UART1CKEN UART1 Clock Enable Control 17 1 read-write 0 UART1 Clock Disabled #0 1 UART1 Clock Enabled #1 WDTCKEN Watchdog Timer Clock Enable Control \nThis is a protected register. Please refer to open lock sequence to program it.\nThis bit is used to control the WDT APB clock only, The WDT engine Clock Source is from LIRC. 0 1 read-write 0 Watchdog Timer Clock Disabled #0 1 Watchdog Timer Clock Enabled #1 APBDIV CLK_APBDIV APB Clock Divider 0x34 read-write n 0x0 0x0 APB0DIV APB0 Clock Divider\nAPB0 PCLK0 can be divided from HCLK. 0 3 read-write APB1DIV APB1 Clock Divider\nAPB1 PCLK1 can be divided from HCLK. 4 3 read-write CDLOWB CLK_CDLOWB Clock Frequency Detector Lower Boundary Register 0x48 read-write n 0x0 0x0 LOWERBD HXT Clock Frequency Detector Lower Boundary\nThe bits define the low value of frequency monitor window.\nWhen HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1. 0 11 read-write CDUPB CLK_CDUPB Clock Frequency Detector Upper Boundary Register 0x44 read-write n 0x0 0x0 UPERBD HXT Clock Frequency Detector Upper Boundary\nThe bits define the high value of frequency monitor window.\nWhen HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1. 0 11 read-write CLKDCTL CLK_CLKDCTL Clock Fail Detector Control Register 0x38 read-write n 0x0 0x0 HXTFDEN HXT Clock Fail Detector Enable Bit 0 1 read-write 0 4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled #0 1 4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled #1 HXTFQDEN HXT Clock Frequency Monitor Enable Bit 2 1 read-write 0 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled #0 1 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled #1 LXTFDEN LXT Clock Fail Detector Enable Bit 1 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled #1 CLKDIE CLK_CLKDIE Clock Fail Detector Interrupt Enable Register 0x3C read-write n 0x0 0x0 HXTFIEN HXT Clock Fail Interrupt Enable Bit 0 1 read-write 0 4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled #0 1 4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled #1 HXTFQIEN HXT Clock Frequency Monitor Interrupt Enable Bit 2 1 read-write 0 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled #0 1 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled #1 LXTFIEN LXT Clock Fail Interrupt Enable Bit 1 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled #1 CLKDIV0 CLK_CLKDIV0 Clock Divider Number Register 0 0x1C read-write n 0x0 0x0 ADCDIV ADC Clock Divide Number From ADC Clock Source 16 8 read-write HCLKDIV HCLK Clock Divide Number From HCLK Clock Source 0 4 read-write SC0DIV SC0Clock Divide Number From SC0Clock Source 28 4 read-write UART0DIV UART0Clock Divide Number From UART Clock Source 8 4 read-write UART1DIV UART1Clock Divide Number From UART Clock Source 12 4 read-write CLKDIV1 CLK_CLKDIV1 Clock Divider Number Register 1 0x20 read-write n 0x0 0x0 DSRCDIV DSRC Clock Divide Number From DSRCClock Source 24 5 read-write SC1DIV SC 1Clock Divide Number From SC 1Clock Source 0 4 read-write TMR0DIV Timer0Clock Divide Number From Timer0Clock Source 8 4 read-write TMR1DIV Timer1Clock Divide Number From Timer1Clock Source 12 4 read-write TMR2DIV Timer2Clock Divide Number From Timer2Clock Source 16 4 read-write TMR3DIV Timer3Clock Divide Number From Timer3Clock Source 20 4 read-write CLKDSTS CLK_CLKDSTS Clock Fail Detector Status Register 0x40 read-only n 0x0 0x0 HXTFIF HXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0. 0 1 read-only 0 4~32 MHz external high speed crystal oscillator (HXT) clock is normal #0 1 4~32 MHz external high speed crystal oscillator (HXT) clock stops #1 HXTFQIF HXT Clock Frequency Monitor Interrupt Flag\nNote: Write 1 to clear the bit to 0. 2 1 read-only 0 4~32 MHz external high speed crystal oscillator (HXT) clock is normal #0 1 4~32 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal #1 LXTFIF LXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0. 1 1 read-only 0 32.768 kHz external low speed crystal oscillator (LXT) clock is normal #0 1 32.768 kHz external low speed crystal oscillator (LXT) stops #1 CLKOCTL CLK_CLKOCTL Clock Output Control Register 0x28 read-write n 0x0 0x0 CLKOEN Clock Output Enable Bit 4 1 read-write 0 Clock Output function Disabled #0 1 Clock Output function Enabled #1 DIV1EN Clock Output Divide One Enable Bit 5 1 read-write 0 Clock Output will output clock with source frequency divided by FREQSEL #0 1 Clock Output will output clock with source frequency #1 FREQSEL Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]. 0 4 read-write CLKSEL0 CLK_CLKSEL0 Clock Source Select Control Register 0 0x10 -1 read-write n 0x0 0x0 HCLKSEL HCLK Clock Source Selection(Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turned on.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register. 0 3 read-write 0 Clock source from HXT #000 1 Clock source from LXT #001 2 Clock source from PLL #010 3 Clock source from LIRC #011 4 Clock source from HIRC1 or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #100 HIRCSEL HIRC Source Selection 3 1 read-write 0 Clock source from HIRC0 (12~16MHz) #0 1 Clock source from HIRC1 (36MHz) #1 ISPSEL ISP Clock Source Selection 4 1 read-write 0 Clock source from HIRC1 or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #0 1 Clock source from MIRC #1 CLKSEL1 CLK_CLKSEL1 Clock Source Select Control Register 1 0x14 -1 read-write n 0x0 0x0 ADCSEL ADC Clock Source Selection 19 3 read-write 0 Clock source from 4~32 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from PLL #010 3 Clock source from36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #011 4 Clock source from 4 MHz internal medium speed RC oscillator (MIRC) #100 PWM0SEL PWM0 Clock Source Selection 4 1 read-write 0 Clock source from PLL #0 1 Clock source from PCLK0 #1 SPI0SEL SPI0 Clock Source Selection 24 2 read-write 0 Clock source from PLL #00 1 Clock source from HCLK #01 2 Clock source from 4~32 MHz external high speed crystal oscillator (HXT) #10 3 Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #11 SPI2SEL SPI2 Clock Source Selection 26 2 read-write 0 Clock source from PLL #00 1 Clock source from HCLK #01 2 Clock source from 4~32 MHz external high speed crystal oscillator (HXT) #10 3 Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #11 TMR0SEL Timer0 Clock Source Selection 8 3 read-write 0 Clock source from 4~32 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #010 3 Clock source from external clock pin #011 4 Clock source from36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #100 5 Clock source from 4 MHz internal medium speed RC oscillator (MIRC) #101 TMR1SEL Timer1 Clock Source Selection 12 3 read-write 0 Clock source from 4~32 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #010 3 Clock source from external clock pin #011 4 Clock source from36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #100 5 Clock source from 4 MHz internal medium speed RC oscillator (MIRC) #101 UART0SEL UART0 Clock Source Selection 0 3 read-write 0 Clock source from 4~32 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from PLL #010 3 Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #011 WDTSEL WDT Clock Source Selection 28 2 read-write 0 reserved #00 1 Clock source from LXT #01 2 Clock source from HCLK/2048 #10 3 Clock source from LIRC #11 WWDTSEL WDT Clock Source Selection 30 2 read-write 0 reserved #00 1 reserved #01 2 Clock source from HCLK/2048 #10 3 Clock source from LIRC #11 CLKSEL2 CLK_CLKSEL2 Clock Source Select Control Register 2 0x18 -1 read-write n 0x0 0x0 CLKOSEL Clock Divider Clock Source Selection 4 3 read-write 0 Clock source from 4~32 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from HCLK #010 3 Clock source from36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #011 DSRCSEL DSRC Clock Source Selection 7 1 read-write 0 Clock source from 4 MHz internal medium speed RC oscillator (MIRC) #0 1 Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #1 SC0SEL SC0 Clock Source Selection 16 3 read-write 0 Clock source from 4~32 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from PLL #001 2 Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #010 3 Clock source from 4 MHz internal medium speed RC oscillator (MIRC) #011 SC1SEL SC1 Clock Source Selection 20 3 read-write 0 Clock source from 4~32 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from PLL #001 2 Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #010 3 Clock source from 4 MHz internal medium speed RC oscillator (MIRC) #011 SPI1SEL SPI1 Clock Source Selection 24 2 read-write 0 Clock source from PLL #00 1 Clock source from HCLK #01 2 Clock source from 4~32 MHz external high speed crystal oscillator (HXT) #10 3 Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #11 SPI3SEL SPI3 Clock Source Selection 26 2 read-write 0 Clock source from PLL #00 1 Clock source from HCLK #01 2 Clock source from 4~32 MHz external high speed crystal oscillator (HXT) #10 3 Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #11 TMR2SEL Timer2 Clock Source Selection 8 3 read-write 0 Clock source from 4~32 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #010 3 Clock source from external clock pin #011 4 Clock source from36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #100 5 Clock source from 4 MHz internal medium speed RC oscillator (MIRC) #101 TMR3SEL Timer3 Clock Source Selection 12 3 read-write 0 Clock source from 4~32 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #010 3 Clock source from external clock pin #011 4 Clock source from36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #100 5 Clock source from 4 MHz internal medium speed RC oscillator (MIRC) #101 UART1SEL UART1 Clock Source Selection 0 3 read-write 0 Clock source from 4~32 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from PLL #010 3 Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting #011 PLLCTL CLK_PLLCTL PLL Control Register 0x24 -1 read-write n 0x0 0x0 INDIV PLL Input Source Divider \nPLL input clock frequency range: 0.8MHz ~ 2MHz 8 6 read-write PD Power-down Mode If set the PDEN bit 1 in CLK_PWRCTL register, the PLL will enter Power-down mode too 16 1 read-write 0 PLL is in normal mode #0 1 PLL is in power-down mode (default) #1 PLLMLP PLL Multiple\n000000: Reserved\n000001: X1\n000010: X2\n000011: X3\n000100: X4\n...\n010000:X16\n...\n100000: X32\n100100: X36\n0thers: Reserved \nPLL output frequency: PLL input frequency * PLLMLP.\nPLL output frequency range: 16MHz ~ 36MHz 0 6 read-write PLLSRC PLL Source Clock Select 17 2 read-write 0 PLL source clock from HXT #00 1 PLL source clock from HIRC0 or HIRC1 #01 2 PLL source clock from MIRC #10 3 reserved #11 STBCNT PLL Stable Time Selection 14 2 read-write 0 100 cycle time of input clock source #00 1 120 cycle time of input clock source #01 2 180 cycle time of input clock source #10 3 240 cycle time of input clock source #11 PWRCTL CLK_PWRCTL System Power-down Control Register 0x0 -1 read-write n 0x0 0x0 HIRC0EN HIRC0 Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 12~16 MHz internal high speed RC oscillator (HIRC0)Disabled #0 1 12~16 MHz internal high speed RC oscillator (HIRC0)Enabled #1 HIRC0FSEL HIRC0 Output Frequency Select Bit 13 1 read-write 0 HIRC0 will output 12MHz clock #0 1 HIRC0 will output 16MHz Clock #1 HIRC0FSTOP HIRC0 Stop Output When Frequency Changes (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 14 1 read-write 0 HIRC0 will continue to output when HIRC frequency changes #0 1 HIRC0will suppress to output during first 16 clocks when HIRC frequency change #1 HIRC1EN HIRC1 Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 24 1 read-write 0 36 MHz internal high speed RC oscillator (HIRC1)Disabled #0 1 36 MHz internal high speed RC oscillator (HIRC1)Enabled #1 HXTEN HXT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 4~32 MHz external high speed crystal (HXT) Disabled #0 1 4~32 MHz external high speed crystal (HXT) Enabled #1 HXTGAIN HXT Gain Control Bit(Write Protect)\nGain control is used to enlarge the gain of crystal to make sure crystal wok normally. If gain control is enabled, crystal will consume more power than gain control off.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 10 3 read-write 0 HXT frequency is lower than from 4 MHz #000 1 HXT frequency is from 4 MHz to 8 MHz #001 2 HXT frequency is from 8 MHz to 12 MHz #010 3 HXT frequency is from 12 MHz to 16 MHz #011 4 HXT frequency is from 16 MHz to 24 MHz #100 5 HXT frequency is from 24 MHz to 32 MHz #101 6 HXT frequency is from 32 MHz to 36 MHz #110 7 HXT frequency is higher than 36 MHz #111 HXTSLTYP HXT Mode Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 8 1 read-write 0 High frequency crystal loop back path Disabled. It is used for external oscillator #0 1 High frequency crystal loop back path Enabled. It is used for external crystal #1 LIRCEN LIRC Enable Bit(Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 10 kHz internal low speed RC oscillator (LIRC) Disabled #0 1 10 kHz internal low speed RC oscillator (LIRC)Enabled #1 LXTEN LXT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 32.768 kHz external lowspeed crystal (LXT) Disabled #0 1 32.768 kHz external lowspeed crystal (LXT) Enabled #1 MIRCEN MIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 25 1 read-write 0 4 MHz internal medium speed RC oscillator (MIRC)Disabled #0 1 4 MHz internal medium speed RC oscillator (MIRC)Enabled #1 PDEN System Power-down Enable (Write Protect) When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit. (a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set. (default) (b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down. In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 Chip operating normally or chip in idle mode because of WFI command #0 1 Chip enters Power-down mode instant or wait CPU sleep command WFI #1 PDWKDLY Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay4096 clock cycles to wait system clock stable when chip works at 4~32 MHz external high speed crystal oscillator (HXT).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 Clock cycles delayDisabled #0 1 Clock cycles delayEnabled #1 PDWKIEN Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt (EINT0~1, GPIO,, UART0~1, WDT, ACMP01, BOD, RTC, TMR0~3, I2C0~1 or SPI0 ~3)will occur when PDWKIEN are high.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 Power-down mode wake-up interrupt Disabled #0 1 Power-down mode wake-up interrupt Enabled #1 STATUS CLK_STATUS Clock status monitor Register 0xC -1 read-only n 0x0 0x0 CLKSFAIL Clock Switching Fail Flag(Read Only)\nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1. 7 1 read-only 0 Clock switching success #0 1 Clock switching failure #1 HIRC0STB HIRC0 Clock Source Stable Flag (Read Only) 4 1 read-only 0 12~16 MHz internal high speed RC oscillator (HIRC0) clock is not stable or disabled #0 1 12~16 MHz internal high speed RC oscillator (HIRC0) clock is stable and enabled #1 HIRC1STB HIRCClock Source Stable Flag(Read Only) 5 1 read-only 0 36 MHz internal high speed RC oscillator (HIRC1) clock is not stable or disabled #0 1 36 MHz internal high speed RC oscillator (HIRC1) clock is stable and enabled #1 HXTSTB HXTClock Source Stable Flag(Read Only) 0 1 read-only 0 4~36 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled #0 1 4~36 MHz external high speed crystal oscillator (HXT)clock is stable and enabled #1 LIRCSTB LIRCClock Source Stable Flag(Read Only) 3 1 read-only 0 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled #1 LXTSTB LXTClock Source Stable Flag(Read Only) 1 1 read-only 0 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled #1 MIRCSTB MIRCClock Source Stable Flag(Read Only) 6 1 read-only 0 4 MHz internal medium speed RC oscillator (MIRC) clock is not stable or disabled #0 1 4 MHz internal medium speed RC oscillator (MIRC) clock is stable and enabled #1 PLLSTB Internal PLL Clock Source Stable Flag(Read Only) 2 1 read-only 0 Internal PLL clock is not stable or disabled #0 1 Internal PLL clock is stable and enabled #1 WKINTSTS CLK_WKINTSTS Wake-up Interrupt Status 0x30 read-only n 0x0 0x0 PDWKIF Wake-up Interrupt Status in Chip Power-down Mode\nThis bit indicates that some event resumes chip from Power-down mode\nThe status is set if external interrupts, UART, GPIO, RTC, USB, SPI, Timer, WDT, and BOD wake-up occurred.\nWrite 1 to clear this bit. 0 1 read-only CRC PDMA Register Map PDMA 0x0 0x0 0x8 registers n 0x14 0x4 registers n 0x1C 0xC registers n 0x80 0xC registers n 0xC 0x4 registers n CHECKSUM CRC_CHECKSUM CRC Checksum Register 0x88 -1 read-only n 0x0 0x0 CHECKSUM CRC Checksum Results\nThis field indicates the CRC checksum result 0 32 read-only CTL CRC_CTL CRC Control Register 0x0 -1 read-write n 0x0 0x0 CHKSFMT Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. 27 1 read-write 0 1's complementfor CRC checksum Disabled #0 1 1's complement for CRC checksum Enabled #1 CHKSREV Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0XDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB. 25 1 read-write 0 Bit order reverse for CRC checksum Disabled #0 1 Bit order reverse for CRC checksum Enabled #1 CRCEN CRC Channel Enable Bit 0 1 read-write 0 No effect #0 1 CRC operation Enabled #1 CRCMODE CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode. 30 2 read-write 0 CRC-CCITT Polynomial Mode #00 1 CRC-8 Polynomial Mode #01 2 CRC-16 Polynomial Mode #10 3 CRC-32 Polynomial Mode #11 CRCRST CRC Engine Reset Bit\nNote1: This bit will be cleared automatically.\nNote2: When operating in CPU mode, setting this bit will reload the seed value from CRC_SEED register as checksum initial value. 1 1 read-write 0 No effect #0 1 Reset the internal CRC state machine and internal buffer. The others contents of CRC_CTL register will not be cleared #1 DATFMT Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DTA register. 26 1 read-write 0 1's complement for CRC writes data in Disabled #0 1 1's complement for CRC writes data in Enabled #1 DATLEN CPU Write Data Length This field indicates the CPU write data length only when operating in CPU mode. Note1: This field is only valid when operating in CPU mode. Note2: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA [7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA [15:0]. 28 2 read-write 0 The write data length is 8-bit mode #00 1 The write data length is 16-bit mode #01 2 The write data length is 32-bit mode #10 3 Reserved #11 DATREV Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function for writing data value in CRC_DTA register.\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC data write in is 0x55DD33BB. 24 1 read-write 0 Bit order reverse for CRC data write in Disabled #0 1 Bit order reverse for CRC data write in Enabled (per byte) #1 TRIGEN Trigger Enable Bit\nThis bit is used to trigger the CRC DMA transfer.\nNote1: If this bit asserts which indicates the CRC engine operation in CRC DMA mode, do not fill in any data in CRC_DAT register.\nNote2: When CRC DMA transfer completed, this bit will be cleared automatically.\nNote3: If the bus error occurs when CRC DMA transfer data, all CRC DMA transfer will be stopped. User must reset all DMA channel before trigger DMA again. 23 1 read-write 0 No effect #0 1 CRC DMA data read or write transfer Enabled #1 DAT CRC_DAT CRC Write Data Register 0x80 read-write n 0x0 0x0 DATA CRC Write Data Bits When operating in CPU mode, user can write data to this field to perform CRC operation. When operating in DMA mode, this field indicates the DMA read data from memory and cannot be written by user. Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register are only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register are only DATA[15:0] bits. 0 32 read-write DMABCNT CRC_DMABCNT CRC DMA Transfer Byte Count Register 0xC read-write n 0x0 0x0 BCNT CRC DMA Transfer Byte Count \nThis field indicates a 16-bit total transfer byte count number of CRC DMA. 0 16 read-write DMACBCNT CRC_DMACBCNT CRC DMA Current Transfer Byte Count Register 0x1C read-only n 0x0 0x0 CBCNT CRC DMA Current Remained Byte Count (Read Only)\nThis field indicates the current remained byte count of CRC DMA.\nNote: Setting the CRCRST (CRC_CTL[1]) bit to 1 will clear this register value. 0 16 read-only DMACSA CRC_DMACSA CRC DMA Current Source Address Register 0x14 read-only n 0x0 0x0 CSA CRC DMA Current Source Address Bits (Read Only)\nThis field indicates the current source address where the CRC DMA transfer just occurs. 0 32 read-only DMAINTEN CRC_DMAINTEN CRC DMA Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 TABTIEN CRC DMA Read/Write Target Abort Interrupt Enable Bit\nEnable this bit will generate the CRC DMA Target Abort interrupt signal while TABTIF (CRC_DMAINTSTS[0]) bit is set to 1. 0 1 read-write 0 Target abort interrupt Disabled during CRC DMA transfer #0 1 Target abort interrupt Enabled during CRC DMA transfer #1 TDIEN CRC DMA Block Transfer Done Interrupt Enable Bit\nEnable this bit will generate the CRC DMA Transfer Done interrupt signal while TDIF (CRC_DMAINTSTS[1]) bit is set to 1. 1 1 read-write 0 Interrupt Disabled when CRC DMA transfer done #0 1 Interrupt Enabled when CRC DMA transfer done #1 DMAISTS CRC_DMAISTS CRC DMA Interrupt Status Register 0x24 read-write n 0x0 0x0 TABTIF CRC DMA Read/Write Target Abort Interrupt Flag This bit indicates that CRC bus has error or not during CRC DMA transfer. Note1: This bit is cleared by writing 1 to it. Note2: This bit indicates bus master received error response or not. If bus master received error response, it means that CRC transfer data from an invalid address or to an invalid adress .At this time target abort is happened.DMA will stop transfer and respond this event to user then CRC state machine goes to IDLE state. When target abort occurred, user must reset DMA before transfer those data again. 0 1 read-write 0 No bus error response received during CRC DMA transfer #0 1 Bus error response received during CRC DMA transfer #1 TDIF CRC DMA Transfer Done Interrupt Flag This bit indicates that CRC DMA transfer has finished or not. Note1: This bit is cleared by writing 1 to it. Note2: When CRC DMA transfer is done, TRIGEN (CRC_CTL[23]) will be cleared automatically. 1 1 read-write 0 Not finished if TRIGEN (CRC_CTL[23]) has enabled #0 1 CRC transfer done if TRIGEN (CRC_CTL[23]) has enabled #1 DMASA CRC_DMASA CRC DMA Source Address Register 0x4 read-write n 0x0 0x0 SA CRC DMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of CRC DMA.\nNote: The source address must be word alignment. 0 32 read-write SEED CRC_SEED CRC Seed Register 0x84 -1 read-write n 0x0 0x0 SEED CRC Seed Value\nThis field indicates the CRC seed value. 0 32 read-write DSRC DSRC Register Map DSRC 0x0 0x0 0x1C registers n 0x20 0x8 registers n 0x200 0x4 registers n 0x210 0xC registers n 0x38 0xC registers n CHKSUM DSRC_CHKSUM DSRC Checksum Register 0x18 read-only n 0x0 0x0 CHECKSUM0 The CRC Checksum0\nThe bit field indicates the CRC checksum of the initial value is CHKSUM0 (DSRC_CHKSUM[15:0]). 0 16 read-only CHECKSUM1 The CRC Checksum1\nThe bit field indicates the CRC checksum of the initial value is CHKSUM1 (DSRC_CHKSUM[31:16]) 16 16 read-only CRCSEED DSRC_CRCSEED DSRC CRC Seed Initial Register 0x10 -1 read-write n 0x0 0x0 CRCSEED0 The CRC Seed Initial Pattern 0\nThe bits field indicates the CRC seed initial pattern 0 of DSRC.\nFor receiver:\nThe CRC will be calculated by the initial value. The TBP will auto compare the calculated result with the received CRC data and report its compare result into CRC0_OK (DSRC_STATUAS[24])\nFor Transmit:\nThe bit field is used to generate the CRC when the SEEDM (DSRC_CTL[20]) is set to 0. 0 16 read-write CRCSEED1 The CRC Seed Initial Pattern 1\nThe bit field indicates the CRC seed initial pattern 1 of DSRC.\nFor receiver:\nThe CRC will be calculated by the initial value. The TBP will auto compare the calculated result with the received CRC data and report its compare result into CRC1_OK (DSRC_STATUAS[25])\nFor transmitter:\nThe bit field is used to generate the CRC when the SEEDM (DSRC_CTL[20]) is set to 1. 16 16 read-write CTL DSRC_CTL DSRC Control Register 0x0 -1 read-write n 0x0 0x0 BRATEACC Bit Rate Accuracy Control Bits\nPlease refer to Table 6.181.\nNote: This function is only for FM0 CODEC. 28 3 read-write BRATEMOD Bit Rate Error Mode 5 1 read-write 0 The DSRC receives the start of frame again #0 1 The DSRC does not care the bit rate error message and continue receiving data #1 BRDETEN Bit Rate Detection Enable Bit \nNote: This function is only for FM0 CODEC. 4 1 read-write 0 Bit rate detection Disabled #0 1 Bit rate detection Enabled #1 CHKSFMT Checksum Format 11 1 read-write 0 No 1's complement for CRC checksum #0 1 1's complement for CRC checksum #1 CHKSREV Checksum Reverse\nNote: If the checksum data is 0XDD7B0F2E, the bit order reversed for CRC checksum is 0x74F0DEBB. 10 1 read-write 0 No bit order reverse for CRC checksum #0 1 Bit order reverse for CRC checksum #1 CODECEN CODEC Enable Bit\nNote: When both DSRCEN and CODECEN are enabled, the SPI1 will set TXNEG (SPI_CTL[2]), RXNEG (SPI_CTL[1]), CLKPOL (SPI_CTL[11]), SS (SPI_SSCTL[1:0]), SSACTPOL (SPI_SSCTL[2]), AUTOSS (SPI_SSCTL[3]) and SLV3WIRE (SPI_SSCTL[5]) as 0, 1, 0, 0x1, 1, 1, and 1 automatically for FM0 (or Manchester) CODEC communication. In this codition, SPI1 will set the SLAVE (SPI_CTL[18]) bit automatically and operate as Master mode in data transmitting phase and Slave 3-wired mode in data receiving phase automatically. 2 1 read-write 0 CODEC Disabled #0 1 CODEC Enabled #1 CODECFMT CODEC Format Select Bit 3 1 read-write 0 FM0 CODEC #0 1 MONCHESTER CODEC #1 CRCBSWAP CRC BYTE SWAP 20 1 read-write 0 The received CRC value is not byte swap #0 1 The received CRC value is byte swap #1 CRCEN CRC Engine Enable Bit 8 1 read-write 0 CRC function Disabled #0 1 CRC function Enabled #1 CRCMSB CRC Generation on Data MSB\nNote: If the input data is 0xaa, the sequence of CRC bit generation is 01010101 when the bit is set as 0. Otherwise, the sequence of CRC bit generation is 10101010 when the bit is set as 1. 9 1 read-write 0 The CRC generation start on the LSB input data first #0 1 The CRC generation start on the MSB input data first #1 DSRCEN DSRC Enable Bit\nNote: When DSRC is enabled, SPI1 will set SUSPITV (SPI_CTL[15:12]), DWIDTH (SPI_CTL[7:3]), REORDER (SPI_CTL[19]), FIFOM (SPI_CTL[21]), TWOBIT (SPI_CTL[22]), and DUALIOEN (SPI_CTL[29]) set as 0x0, 0x8, 0, 1, 0, and 0 automatically for data byte transaction in DSRC application. 0 1 read-write 0 DSRC Disabled #0 1 DSRC Enabled #1 FORCERX Force RX State Control Bit\nNote: This bit will be cleared automatically. 22 1 read-write 0 No effect #0 1 DSRC returns Start_Rx state immediately #1 FORCETX Force TX State Control Bit\nNote: This bit will be cleared automatically 21 1 read-write 0 No effect #0 1 DSRC returns TX state to transmit data immediately #1 PDRXDIS Power-down Mode RXON Disable Bit 14 1 read-write 0 RXON signal is always controlled by RXON(DSRC_CTL[23]) bit #0 1 RXON signal is disabled during DSRC Power-Down period #1 PREAMFMT Preamble Pattern Format\nNote: It is MSB first to be sent. 13 1 read-write 0 The preamble length is half word and its pattern is PREPAT (DSRC_PREAMBLE[15:0]) #0 1 The preamble length is one word and its pattern is PREPAT (DSRC_PREAMBLE[31:0]) #1 RXON RX_ON Control Bit 23 1 read-write 0 RX_ON signal Enabled #0 1 RX_ON signal Disabled #1 SEEDM CRC Seed Mode 12 1 read-write 0 The transmit CRC seed initial value is CRCSEED0 (DSRC_CRCSEED[15:0]) #0 1 The transmit CRC seed initial value is CRCSEED1 (DSRC_CRCSEED[31:15]) #1 SWRXEN Software Control RX_ON Enable Bit 1 1 read-write 0 Software control RX_ON signal Disabled #0 1 Software control RX_ON signal Enabled #1 TBPEN TBP Enable Bit\nSetting this bit to 1 enables TBP operation. 16 1 read-write 0 TBP function Disabled #0 1 TBP function Enabled #1 TRANSFIN TBP Transfer Done\nWhen the TTDMAEN (DSRC_CTL[20]) is disabled and the transmitted data is written into DSRC_TX by user, this bit shall be set into the TBP to terminate the processor before the last the transmitted data. The minimum length of transmitted data is 2 bytes.\nNote: This bit will be cleared after the TTBP transfer is done. 17 1 read-write 0 Indicate the TTBP processor is not finished #0 1 Inform the TTBP to finish the transparent bit processor after the current byte processed done #1 TRDMAEN TBP Receive DMA Enable Bit 19 1 read-write 0 TBP Receiving DMA Disabled #0 1 TBP Receiving DMA Enabled #1 TTDMAEN TBP Transmit DMA Enable Bit 18 1 read-write 0 TBP Transmitting DMA Disabled #0 1 TBP Transmitting DMA Enabled #1 WKHXTEN Wake-up HXT Clock Enable Bit \nSetting this bit to 1 enables RF wake-up HXT clock. 15 1 read-write 0 RF wake-up HXT clock Disabled #0 1 RF T wake-up HXT clock Enabled #1 WKPOL Wake-up Pin Polarity Control Bit 26 2 read-write 0 Wake-up pin rising edge wake-up DSRC #00 1 Wake-up pin falling edge wake-up DSRC #01 CTL2 DSRC_CTL2 DSRC Control Register 2 0x200 -1 read-write n 0x0 0x0 CODECDEGSEL FM0 CODEC Deglitch Selection\nThis bits field is used to define how much width of glitch would be filtered. 8 3 read-write 0 disable to the CODECdeglitch selection #000 1 Filter the glitches that the width is 0.25us or less #001 2 Filter the glitches that the width is 0.50us or less #010 3 Filter the glitches that the width is 0.75us or less #011 4 Filter the glitches that the width is 1.00us or less #100 5 Filter the glitches that the width is 1.25us or less #101 SOFNUM Start of Frame Number for Transmission\nThis bit field is used to define the number of SOF packet which is repeated send in the SPI bus before the transmitted data. 0 2 read-write 0 1 Start field of frame after the Preamble #00 1 2Start field of frame after the Preamble #01 2 3Start field of framesafter the Preamble #10 3 4 Start field of frames after the Preamble #11 ICR DSRC_ICR DSRC Internal Use Control Register 0x218 read-only n 0x0 0x0 INTEN DSRC_INTEN DSRC Interrupt Enable Register 0x4 read-write n 0x0 0x0 BRATERRIE Bit Rate Error Interrupt Enable Bit 5 1 read-write 0 Bit Rate Error interrupt Disabled #0 1 Bit Rate Error interrupt Enabled #1 CRCCORIE CRC Check Correct Interrupt Enable Bit 0 1 read-write 0 CRC check done without error Interrupt Disabled #0 1 CRC check done without error Interrupt Enabled #1 CRCERRIE CRC Error Interrupt Enable Bit 1 1 read-write 0 CRC error interrupt Disabled #0 1 CRC rate error interrupt Enabled #1 EPWKIE External Pin Wake-up Interrupt Enable Bit 26 1 read-write 0 External Pin Wake-up event interrupt Disabled #0 1 External Pin Wake-up event interrupt Enabled #1 RTBPDIE TBP Byte Receive Done Interrupt Enable Bit 9 1 read-write 0 The TBP byte receive done interrupt Disabled #0 1 The TBP byte receive done interrupt Enabled #1 RXDATERRIE Received Data Error Interrupt Enable Bit 4 1 read-write 0 Received DATA Error interrupt Disabled #0 1 Received DATA Rate Error interrupt Enabled #1 STPFRMIE Stop Field of Frame Detection Interrupt Enable Bit 3 1 read-write 0 Stop Field of Frame detection Interrupt Disabled #0 1 Stop Field of Frame detection Interrupt Enabled #1 STRFRMIE Start Field of Frame Detection Interrupt Enable Bit 2 1 read-write 0 Start Field of Frame detection interrupt Disabled #0 1 Start Field of Frame detection interrupt Enabled #1 T2TOIE Timer 2 Time-out Interrupt Enable Bit 18 1 read-write 0 T2 Time-out interrupt Disabled #0 1 T2 Time-out interrupt Enabled #1 T3TOIE Timer 3 Time-out Interrupt Enable Bit 19 1 read-write 0 T3 Time-out interrupt Disabled #0 1 T3 Time-out interrupt Enabled #1 T4TOIE Timer 4 Time-out Interrupt Enable Bit 20 1 read-write 0 T4 Time-out interrupt Disabled #0 1 T4 Time-out interrupt Enabled #1 TXDONEIE Transmit Data Done Interrupt Enable Bit 12 1 read-write 0 Transmit data done interrupt Disabled #0 1 Transmit data done interrupt Enabled #1 PREAMBLE DSRC_PREAMBLE DSRC Preamble Pattern Register 0xC read-write n 0x0 0x0 PREPAT The Preamble Pattern\nThe bit field indicates the preamble pattern of DSRC. If the PREAMFMT (DSRC_CTL[24]) is set to 1, 32-bit preamble pattern is transmitted and the transmitted sequence is PREPAT[31:24], PREPAT[23:16], PREPAT[15:8] and PREPAT[7:0].\nIf the PREAMFMT (DSRC_CTL[24]) is set to 0, 16-bit preamble pattern is transmitted and the transmitted sequence is PREPAT[15:8] and PREPAT[7:0]. 0 32 read-write RBCNT DSRC_RBCNT DSRC Receive Byte Count Register 0x14 read-only n 0x0 0x0 TBPBCNT TBP Receive Byte Count\nThe bits field indicates the number of receive byte count on RTBP when the CRCCOR (DSRC_STATUS[0]) is set to 1 and the STPFRM(DSRC_STATUS[3]) is set to 1. Otherwise, the value is 0.\nNote 1: The 2 bytes CRC is not calculated in this field.\nNote 2: If there is CRC calculation check error, the value will be cleared by hardware to calculate the next incoming data stream. 0 9 read-only RX DSRC_RX DSRC RX Data Register 0x24 read-only n 0x0 0x0 RX TBP Receiver Data\nThe bit field indicates the received data on the TBP after the RTBP. 0 8 read-only RXR DSRC_RXR DSRC Receive Data Before RTBP Register 0x214 read-only n 0x0 0x0 RXDATR Receive Data Before RTBP \nThe bits field indicates the current receive data before the RTBP (It comes from the SPI RX buffer). Before the 8-Bit is processed by the RTBP, the register indicates the un-processed content. 0 8 read-only STATUS DSRC_STATUS DSRC Status Register 0x8 read-write n 0x0 0x0 BRATERR Bit Rate Error Flag\nThis flag indicates FM0 or MANCHESTER bit rate error depending on CODECFMT (DSRC_CTL[3]) setting if BRDETEN (DSRC_CTL[4]) is set to 1.\nNote: Write 1 to clear this flag. 5 1 read-write CRC0_OK CRC0 Compare OK\nNote: Writing1 to CRCCOR (DSRC_STATUS[0]), CRCERR (DSRC_STATUS[1]) and itself can clear this flag. 24 1 read-write 0 The compare result between the receive CRC data and the CHKSUM0 (DSRC_CHKSUM[15:0])is not the same #0 1 The compare result between the receive CRC data and the CHKSUM0 (DSRC_CHKSUM[15:0]) is the same #1 CRC1_OK CRC1 Compare OK\nNote: Writing1 to CRCCOR (DSRC_STATUS[0]), CRCERR (DSRC_STATUS[1]) and itself can clear this flag. 25 1 read-write 0 The compare result between the receive CRC data and the CHKSUM1 (DSRC_CHKSUM[31:16])is not the same #0 1 The compare result between the receive CRC data and the CHKSUM1 (DSRC_CHKSUM[31:16]) is the same #1 CRCCOR CRC CorrectBit 0 1 read-write 0 This flag indicates CRC check done and result is not correct on CHKSUM0 (DSRC_CHKSUM[15:0]) and CHKSUM1 (DSRC_CHKSUM[31:16]) #0 1 If the CRC function is enabled (CRCEN(DSRC_CTL[8])=1, this flag indicates CRC check done and result is correct on CHKSUM0 (DSRC_CHKSUM[15:0]) or CHKSUM1 (DSRC_CHKSUM[31:16]), else writ 1 to this bit to indicate that MCU CRC check correct #1 CRCERR CRC Error Bit 1 1 read-write 0 This flag indicates CRC check done and result is correct #0 1 If the CRC function is enabled (CRCEN(DSRC_CTL[8])=1,this flag indicates CRC check done and result is error on CHKSUM0 (DSRC_CHKSUM[15:0]) and CHKSUM1 (DSRC_CHKSUM[31:16]), else writ 1 to this bit to indicate that MCU CRC check error #1 EPWKF External Pin Wake-up Event Flag\nNote: Write 1 to clear this flag. 26 1 read-write 0 No external pin wake-up event happened #0 1 External pin wake-up event happened #1 RTBPDONE TBP Byte Receive Done\nNote: This bit is automatically cleared by TBP_RXDMA_ACK when the TRDMAEN (DSRC_CTL[19]) is set or by the read signal of DSRC_RX register when the TRDMAEN (DSRC_CTL[19]) is not set. 9 1 read-write 0 The TBP byte receive is not finished #0 1 The TBP byte receive has done #1 RXDATERR Received Data Error Flag\nNote: Write 1 to clear this flag. 4 1 read-write 0 The received data packet error happened #0 1 The received data packet has successive 7 bit 1. It indicates the receive frame shall be thrown out #1 STPFRM Stop Field of Frame Detection Flag\nThis flag indicates stop field of frame is detected.\nNote: Write 1 to clear this flag. 3 1 read-write STRFRM Start Field of Frame Detection Flag\nThis flag indicates start field of frame is detected.\nNote: Write 1 to clear this flag. 2 1 read-write T2TO Timer 2 Time-out Flag\nThis flag is set after the Timer Controller finishes counting the value set by DSRC_TMR2.\nNote1: The Timer Counter is started when DSRC wake-up and the counter is cleared when the Start of Frame is detected before T2TO event is set.\nNote2: Write 1 to clear this flag. 18 1 read-write T3TO Timer 3 Time-out Flag\nThis flag is set after the Timer Controller finishes counting the value set by DSRC_TMR3.\nNote1: The Timer Counter is startedwhen the Start of Frame is detected and the counter is cleared when the Stop of Frame is detect before the T3TO event is set.\nNote2: Write 1 to clear this flag. 19 1 read-write T4TO Timer 4 Time-out Flag\nThis flag is set after the Timer Controller finishes counting the value set by DSRC_TMR4.\nNote1: The Timer Counter is started when SPI detected the Stop of Frame and DSRC CRC correct flag is active.\nNote2: Write 1 to clear this flag. 20 1 read-write TTBPDONE TBP Byte Transfer Done\nNote 1: This bit is automatically cleared by TBP_TXDMA_ACK when the TTDMAEN (DSRC_CTL[18]) is set or by the write signal of DSRC_TX register when the TTDMAEN (DSRC_CTL[18]) is not set.\nNote 2: If the TTDMAEN (DSRC_CTL[18]) is not set, the first TTBPDONE is set after the TTBP module send out the PREAMBLE and Head 7E patterns. The first transmitted data shall be written into the TX (DSRC_TX) after this flag is set.\nNote 3: After the TRANFIN (DSRC_CTL[17]) is set, this bit won't report the byte transfer done status again. The user shall check the TXDONE (DSRC_STATUS[12]) to know the current transfer has done both on the TTBP and SPI device. 8 1 read-write 0 The TBP byte transfer is not finished #0 1 The TBP byte transfer has been finished #1 TTBPFULL TTBPTransmit Full\nNote: If the TTDMAEN (DSRC_CTL[18] is disabled, the transmitted data can be written into the DSRC_TX register when the TTBPDONE (DSRC_STATUS[8]) is set to 1 and the TTBPFULL must be set as 0. Otherwise, the TTBP transmit done flag TTBPDONE (DSRC_STATUS[8]) won't be active in next data. 15 1 read-write 0 TBP TX Transmit is not full #0 1 TBP TX Transmit is full #1 TXFINISH TX Transfer Finish\nNote:Write 1 to clear this flag. 12 1 read-write 0 The TX transfer is not finished #0 1 All the data processed by the TTBP block and the CRC, trail 7E patterns had been transmitted finish by SPI interface #1 TMR2 DSRC_TMR2 DSRC Timer 2 Register 0x38 read-write n 0x0 0x0 CMPDAT Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT, or the core will run into unknown state. 0 24 read-write PSC Prescale Counter 24 8 read-write TMR3 DSRC_TMR3 DSRC Timer 3 Register 0x3C read-write n 0x0 0x0 CMPDAT Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT, or the core will run into unknown state. 0 24 read-write PSC Prescale Counter 24 8 read-write TMR4 DSRC_TMR4 DSRC Timer 4 Register 0x40 read-write n 0x0 0x0 CMPDAT Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT, or the core will run into unknown state. 0 24 read-write PSC Prescale Counter 24 8 read-write TX DSRC_TX DSRC TX Data Register 0x20 write-only n 0x0 0x0 TX TBP Transmit Data\nThe bit field indicates the transmitted data on the TBP before being transmitted to TTBP. 0 8 write-only TXR DSRC_TXR DSRC Transmit Data After TTBP Register 0x210 read-only n 0x0 0x0 TXDATR Transmit Data After TTBP \nThe bits field indicates the transmitted data after the TTBP. When the 8-Bit transmitted data is processed by the TTBP, the register indicates the processed content. 0 8 read-only FMC FMC Register Map FMC 0x0 0x0 0x1C registers n 0x40 0x4 registers n 0x50 0x1C registers n DFBA FMC_DFBA Data Flash Base Address 0x14 read-only n 0x0 0x0 DFBA Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash is shared with APROM. the content of this register is loaded from CONFIG1 0 32 read-only FTCTL FMC_FTCTL Flash Access Time Control Register 0x18 -1 read-write n 0x0 0x0 CACHEOFF Flash Cache Disable Control (Write Protect)\nNote:This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Flash Cache function Enabled (default) #0 1 Flash Cache function Disabled #1 FOM Frequency Optimization Mode (Write Protect)\nThe Nano103 series supports adjustable flash access timing to optimize the flash access cycles in different working frequency.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register. 4 3 read-write 1 Frequency 20MHz #001 4 Frequency 40MHz. (default power-on setting) #100 ISPADDR FMC_ISPADDR ISP Address Register 0x4 read-write n 0x0 0x0 ISPADDR ISP Address\nThe Nano103 series is equipped with embedded flash. ISPADDR [1:0] must be kept 00 for ISP 32-bit operation. \nFor both CRC-32 Checksum Calculation and Flash All-One Verification commands, this field is the flash starting address for checksum calculation and 512 bytes address alignment is necessary. 0 32 read-write ISPCMD FMC_ISPCMD ISP CMD Register 0xC read-write n 0x0 0x0 CMD ISP CMD\nISP command table is shown below:\nThe other commands are invalid. 0 6 read-write 0 FLASH 32-bit Read 0x00 4 Read Unique ID 0x04 8 Read All-One Verification Result 0x08 11 Read Company ID 0x0b 12 Read Device ID 0x0c 13 Read Checksum 0x0d 33 FLASH 32-bit Program 0x21 34 FLASH Page Erase 0x22 38 FLASH Mass Erase 0x26 40 Run All-One Verification 0x28 45 Run CRC-32 Checksum Calculation 0x2d 46 Vector Remap 0x2e ISPCTL FMC_ISPCTL ISP Control Register 0x0 read-write n 0x0 0x0 APUEN APROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 APROM cannot be updated when the chip runs in APROM #0 1 APROM can be updated when the chip runs in APROM #1 BS Boot Select (Write Protect) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Booting from APROM #0 1 Booting from LDROM #1 CFGUEN CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 CONFIG cannot be updated #0 1 CONFIG can be updated #1 ISPEN ISP Enable Bit (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 ISP function Disabled #0 1 ISP function Enabled #1 ISPFF ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: This bit needs to be cleared by writing 1 to it. (1) APROM writes to itself if APUEN is set to 0. (2) LDROM writes to itself if LDUEN is set to 0. (3) CONFIG is erased/programmed if CFGUEN is set to 0. (4) SPROM is erased/programmed if SPUEN is set to 0 (5) SPROM is programmed at SPROM secured mode. (6) Page Erase command at LOCK mode with ICE connection (7) Erase or Program command at brown-out detected (8) Destination address is illegal, such as over an available range. (9) Invalid ISP commands (10) Vector address is mapping to SPROM region (11) KPROM is erased/programmed if KEYLOCK is set to 1 (12) APROM(not include Data Flash) is erased/programmed if KEYLOCK is set to 1 Note: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write LDUEN LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 LDROM cannot be updated #0 1 LDROM can be updated #1 SPUEN SPROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 SPROM cannot be updated #0 1 SPROM can be updated #1 ISPDAT FMC_ISPDAT ISP Data Register 0x8 read-write n 0x0 0x0 ISPDAT ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation. 0 32 read-write ISPSTS FMC_ISPSTS ISP Status Register 0x40 read-write n 0x0 0x0 ALLONE Flash All-one Verification Flag This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after Run Flash All-One Verification complete this bit also can be clear by writing 1 7 1 read-write 0 All of flash bits are 1 after Run Flash All-One Verification complete #0 1 Flash bits are not all 1 after Run Flash All-One Verification complete #1 CBS Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0 [7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. 1 2 read-only 0 LDROM with IAP mode #00 1 LDROM without IAP mode #01 2 APROM with IAP mode #10 3 APROM without IAP mode #11 ISPBUSY ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]). 0 1 read-only 0 ISP operation is finished #0 1 ISP is progressed #1 ISPFF ISP Fail Flag (Write Protect) This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself if APUEN is set to 0. (2) LDROM writes to itself if LDUEN is set to 0. (3) CONFIG is erased/programmed if CFGUEN is set to 0. (4) SPROM is erased/programmed if SPUEN is set to 0 (5) SPROM is programmed at SPROM secured mode. (6) Page Erase command at LOCK mode with ICE connection (7) Erase or Program command at brown-out detected (8) Destination address is illegal, such as over an available range. (9) Invalid ISP commands (10) Vector address is mapping to SPROM region (11) KPROM is erased/programmed if KEYLOCK is set to 1 (12) APROM(not include Data Flash) is erased/programmed if KEYLOCK is set to 1 Note: This bit is write-protected. Refer to the SYS_REGLCTL register. 6 1 read-write PGFF Flash Program with Fast Verification Flag(Read Only)\nThis bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP flash erase or ISP read CID operation 5 1 read-only 0 Flash Program is success #0 1 Flash Program is fail. Program data is different with data in the flash memory #1 SCODE Security Code Active Flag This bit is set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active this bit is clear by SPROM page erase operation. 31 1 read-write 0 Secured code is inactive #0 1 Secured code is active #1 VECMAP Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}\nVECMAP [18:12] should be 0. 9 21 read-only ISPTRG FMC_ISPTRG ISP Trigger Control Register 0x10 read-write n 0x0 0x0 ISPGO ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 ISP operation is finished #0 1 ISP is progressed #1 KECNT FMC_KECNT KEY-Unmatched Counting Register 0x64 read-only n 0x0 0x0 KECNT Error Key Entry Counter at Each Power-on (Read Only)\nKECNT is increased when entry keys is wrong in Security Key protection. KECNT is cleared to 0 if key comparison is matched or system power-on. 0 6 read-only KEMAX Maximum Number for Error Key Entry at Each Power-on (Read Only)\nKEMAX is the maximum error key entry number at each power-on. When KEMAXROM of KPROM is erased or programmed, KEMAX will also be updated. KEMAX is used to limit KECNT(FMC_KECNT[5:0]) maximum counting. The FORBID (FMC_KEYSTS [3]) will be set to 1 when KECNT is more than KEMAX. 8 6 read-only KEY0 FMC_KEY0 KEY0 Data Register 0x50 write-only n 0x0 0x0 KEY0 KEY0 Data (Write Only)\nWrite KEY0 data to this register before KEY Comparison operation. 0 32 write-only KEY1 FMC_KEY1 KEY1 Data Register 0x54 write-only n 0x0 0x0 KEY1 KEY1 Data (Write Only)\nWrite KEY1 data to this register before KEY Comparison operation. 0 32 write-only KEY2 FMC_KEY2 KEY2 Data Register 0x58 write-only n 0x0 0x0 KEY2 KEY2 Data (Write Only)\nWrite KEY2 data to this register before KEY Comparison operation. 0 32 write-only KEYSTS FMC_KEYSTS KEY Comparison Status Register 0x60 read-write n 0x0 0x0 CFGFLAG CONFIG Write-protection Enable Flag(Read Only)\nThis bit is set while the KEYENROM [0] is 0 at power-on or reset. This bit is cleared to 0 by hardware while KPROM is erased. This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0. 5 1 read-only 0 CONFIG write-protection Disabled #0 1 CONFIG write-protection Enabled #1 FORBID KEY Comparison Forbidden Flag(Read Only)\nThis bit is set to 1 whenKECNT(FMC_KECNT[4:0])is more than KEMAX (FMC_KECNT[12:8]) orKPCNT (FMC_KPCNT [2:0])is more than KPMAX (FMC_KPCNT [10:8]). 3 1 read-only 0 KEY comparison is not forbidden #0 1 KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger #1 KEYBUSY KEY Comparison Busy (Read Only) 0 1 read-only 0 KEY comparison is finished #0 1 KEY comparison is busy #1 KEYFLAG KEY Protection Enable Flag(Read Only)\nThis bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset. This bit is cleared to 0 by hardware while KPROM is erased. This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value. 4 1 read-only 0 Security Key protection Disabled #0 1 Security KeyprotectionEnabled #1 KEYLOCK KEY LOCK Flag\nThis bit is set to 1 if KEYMATCH (FMC_KEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection. This bit also can be set to 1 while \nCPU write 1 to KEYLOCK(FMC_KEYSTS[1]) or\nKEYFLAG(FMC_KEYSTS[4]) is 1 at power-on or reset or\nKEYENROM is programmed a non-0xFF value or\nTime-out event or\nFORBID(FMC_KEYSTS[3]) is 1\nSPROM write protect is depended on SPFLAG.\nCONFIG write protect is depended on CFGFLAG 1 1 read-write 0 KPROM and APROM (not include Data Flash) is not in write protection #0 1 KPROM and APROM (not include Data Flash) is in write protection #1 KEYMATCH KEY Match Flag(Read Only) This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM and cleared to 0 if KEYs are unmatched. This bit is also cleared to 0 while CPU writing 1 to KEYLOCK(FMC_KEYSTS[1]) or Time-out event or KPROM is erased or KEYENROM is programmed to a non-0xFF value. Chip is in Power-down mode. 2 1 read-only 0 KEY0, KEY1, and KEY2 are unmatched with the KPROM setting #0 1 KEY0, KEY1, and KEY2 are matched with the KPROM setting #1 SPFLAG SPROM Write-protection Enable Flag(Read Only)\nThis bit is set while the KEYENROM [1] is 0 at power-on or reset. This bit is cleared to 0 by hardware while KPROM is erased. This bit is set to 1 by hardware while KEYENROM[1] is programmed to 0. 6 1 read-only 0 SPROM write-protection Disabled #0 1 SPROM write-protection Enabled #1 KEYTRG FMC_KEYTRG KEY Comparison Trigger Control Register 0x5C read-write n 0x0 0x0 KEYGO KEY Comparison Start Trigger (Write Protection)\nWrite 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished. This trigger operation is valid while FORBID (FMC_KEYSTS [3]) is 0.\nNote:This bit is write-protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 KEY comparison operation is finished #0 1 KEY comparison is progressed #1 TCEN Time-out Counting Enable Bit (Write Protection)\n10 minutes is at least for time-out, and average is about 20 minutes.\nNote:This bit is write-protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Time-out counting Disabled #0 1 Time-out counting Enabled if key is matched after key comparison finish #1 KPCNT FMC_KPCNT KEY-Unmatched Power-on Counting Register 0x68 read-only n 0x0 0x0 KPCNT Power-on Counter for Error Key Entry(Read Only)\nKPCNT is the power-on counting for error key entry in Security Key protection. KPCNT is cleared to 0 if key comparison is matched. 0 4 read-only KPMAX Power-on Maximum Number for Error Key Entry (Read Only)\nKPMAX is the power-on maximum number for error key entry. When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated. KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting. The FORBID(FMC_KEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX 8 4 read-only GPIO GPIO Register Map GPIO 0x0 0x0 0x2C registers n 0x100 0x2C registers n 0x140 0x2C registers n 0x180 0x4 registers n 0x200 0x13C registers n 0x340 0x20 registers n 0x40 0x2C registers n 0x80 0x2C registers n 0xC0 0x2C registers n DBCTL GPIO_DBCTL Interrupt De-bounce Control Register 0x180 read-write n 0x0 0x0 DBCLKSEL De-bounce Sampling Cycle Selection 0 4 read-write 0 Sample interrupt input once per 1 clocks #0000 1 Sample interrupt input once per 2 clocks #0001 2 Sample interrupt input once per 4 clocks #0010 3 Sample interrupt input once per 8 clocks #0011 4 Sample interrupt input once per 16 clocks #0100 5 Sample interrupt input once per 32 clocks #0101 6 Sample interrupt input once per 64 clocks #0110 7 Sample interrupt input once per 128 clocks #0111 8 Sample interrupt input once per 256 clocks #1000 9 Sample interrupt input once per 2*256 clocks #1001 10 Sample interrupt input once per 4*256 clocks #1010 11 Sample interrupt input once per 8*256 clocks #1011 12 Sample interrupt input once per 16*256 clocks #1100 13 Sample interrupt input once per 32*256 clocks #1101 14 Sample interrupt input once per 64*256 clocks #1110 15 Sample interrupt input once per 128*256 clocks #1111 DBCLKSRC De-bounce Counter Clock Source Selection 4 1 read-write 0 De-bounce counter clock source is the HCLK #0 1 De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC) #1 ICLKON Interrupt Clock on Mode\nNote:It is recommended to disable this bit to save system power if no special application concern. 5 1 read-write 0 Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1 #0 1 All I/O pins edge detection circuit is always active after reset #1 PA0_PDIO PA0_PDIO GPIO PA.0 Pin Data Input/Output Register 0x200 read-write n 0x0 0x0 PDIO GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 0 1 read-write 0 Corresponding GPIO pin set to low #0 1 Corresponding GPIO pin set to high #1 PA10_PDIO PA10_PDIO GPIO PA.10 Pin Data Input/Output Register 0x228 read-write n 0x0 0x0 PA11_PDIO PA11_PDIO GPIO PA.11 Pin Data Input/Output Register 0x22C read-write n 0x0 0x0 PA12_PDIO PA12_PDIO GPIO PA.12 Pin Data Input/Output Register 0x230 read-write n 0x0 0x0 PA13_PDIO PA13_PDIO GPIO PA.13 Pin Data Input/Output Register 0x234 read-write n 0x0 0x0 PA14_PDIO PA14_PDIO GPIO PA.14 Pin Data Input/Output Register 0x238 read-write n 0x0 0x0 PA15_PDIO PA15_PDIO GPIO PA.15 Pin Data Input/Output Register 0x23C read-write n 0x0 0x0 PA1_PDIO PA1_PDIO GPIO PA.1 Pin Data Input/Output Register 0x204 read-write n 0x0 0x0 PA2_PDIO PA2_PDIO GPIO PA.2 Pin Data Input/Output Register 0x208 read-write n 0x0 0x0 PA3_PDIO PA3_PDIO GPIO PA.3 Pin Data Input/Output Register 0x20C read-write n 0x0 0x0 PA4_PDIO PA4_PDIO GPIO PA.4 Pin Data Input/Output Register 0x210 read-write n 0x0 0x0 PA5_PDIO PA5_PDIO GPIO PA.5 Pin Data Input/Output Register 0x214 read-write n 0x0 0x0 PA6_PDIO PA6_PDIO GPIO PA.6 Pin Data Input/Output Register 0x218 read-write n 0x0 0x0 PA7_PDIO PA7_PDIO GPIO PA.7 Pin Data Input/Output Register 0x21C read-write n 0x0 0x0 PA8_PDIO PA8_PDIO GPIO PA.8 Pin Data Input/Output Register 0x220 read-write n 0x0 0x0 PA9_PDIO PA9_PDIO GPIO PA.9 Pin Data Input/Output Register 0x224 read-write n 0x0 0x0 PA_DATMSK PA_DATMSK PA Data Output Write Mask 0xC read-write n 0x0 0x0 DMASK0 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 0 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DMASK1 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 1 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DMASK10 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 10 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DMASK11 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 11 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DMASK12 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 12 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DMASK13 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 13 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DMASK14 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 14 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DMASK15 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 15 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DMASK2 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 2 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DMASK3 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 3 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DMASK4 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 4 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DMASK5 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 5 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DMASK6 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 6 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DMASK7 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 7 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DMASK8 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 8 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DMASK9 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 9 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 PA_DBEN PA_DBEN PA De-Bounce Enable Control Register 0x14 read-write n 0x0 0x0 DBEN0 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 0 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN1 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 1 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN10 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 10 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN11 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 11 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN12 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 12 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN13 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 13 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN14 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 14 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN15 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 15 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN2 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 2 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN3 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 3 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN4 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 4 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN5 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 5 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN6 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 6 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN7 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 7 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN8 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 8 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN9 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 9 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 PA_DINOFF PA_DINOFF PA Digital Input Path Disable Control 0x4 read-write n 0x0 0x0 DINOFF0 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 16 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF1 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 17 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF10 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 26 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF11 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 27 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF12 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 28 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF13 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 29 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF14 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 30 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF15 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 31 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF2 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 18 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF3 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 19 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF4 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 20 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF5 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 21 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF6 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 22 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF7 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 23 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF8 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 24 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF9 Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 25 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 PA_DOUT PA_DOUT PA Data Output Value 0x8 -1 read-write n 0x0 0x0 DOUT0 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 0 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 DOUT1 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 1 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 DOUT10 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 10 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 DOUT11 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 11 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 DOUT12 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 12 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 DOUT13 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 13 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 DOUT14 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 14 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 DOUT15 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 15 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 DOUT2 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 2 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 DOUT3 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 3 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 DOUT4 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 4 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 DOUT5 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 5 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 DOUT6 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 6 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 DOUT7 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 7 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 DOUT8 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 8 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 DOUT9 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 9 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output #1 PA_INTEN PA_INTEN PA Interrupt Enable Control Register 0x1C read-write n 0x0 0x0 FLIEN0 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 0 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN1 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 1 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN10 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 10 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN11 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 11 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN12 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 12 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN13 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 13 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN14 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 14 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN15 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 15 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN2 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 2 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN3 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 3 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN4 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 4 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN5 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 5 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN6 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 6 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN7 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 7 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN8 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 8 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN9 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 9 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 RHIEN0 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 16 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN1 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 17 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN10 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 26 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN11 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 27 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN12 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 28 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN13 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 29 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN14 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 30 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN15 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 31 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN2 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 18 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN3 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 19 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN4 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 20 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN5 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 21 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN6 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 22 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN7 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 23 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN8 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 24 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN9 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 25 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 PA_INTSRC PA_INTSRC PA Interrupt Source Flag 0x20 read-write n 0x0 0x0 INTSRC0 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 0 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC1 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 1 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC10 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 10 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC11 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 11 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC12 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 12 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC13 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 13 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC14 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 14 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC15 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 15 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC2 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 2 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC3 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 3 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC4 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 4 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC5 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 5 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC6 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 6 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC7 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 7 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC8 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 8 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC9 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 9 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 PA_INTSTS PA_INTSTS PA Interrupt Status 0x28 read-only n 0x0 0x0 FLISTS0 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 0 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 FLISTS1 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 1 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 FLISTS10 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 10 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 FLISTS11 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 11 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 FLISTS12 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 12 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 FLISTS13 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 13 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 FLISTS14 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 14 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 FLISTS15 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 15 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 FLISTS2 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 2 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 FLISTS3 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 3 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 FLISTS4 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 4 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 FLISTS5 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 5 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 FLISTS6 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 6 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 FLISTS7 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 7 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 FLISTS8 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 8 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 FLISTS9 Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 9 1 read-only 0 No falling edge interrupt at Px.n #0 1 Px.n generates an falling edge interrupt #1 RHISTS0 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 16 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 RHISTS1 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 17 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 RHISTS10 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 26 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 RHISTS11 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 27 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 RHISTS12 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 28 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 RHISTS13 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 29 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 RHISTS14 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 30 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 RHISTS15 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 31 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 RHISTS2 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 18 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 RHISTS3 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 19 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 RHISTS4 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 20 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 RHISTS5 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 21 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 RHISTS6 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 22 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 RHISTS7 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 23 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 RHISTS8 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 24 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 RHISTS9 Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). \nNote2:\nThe PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 25 1 read-only 0 No rising edge interrupt at Px.n #0 1 Px.n generates an rising edge interrupt #1 PA_INTTYPE PA_INTTYPE PA Interrupt Trigger Type Control 0x18 read-write n 0x0 0x0 TYPE0 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 0 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE1 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 1 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE10 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 10 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE11 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 11 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE12 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 12 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE13 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 13 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE14 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 14 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE15 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 15 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE2 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 2 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE3 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 3 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE4 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 4 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE5 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 5 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE6 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 6 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE7 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 7 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE8 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 8 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE9 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 9 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 PA_MODE PA_MODE PA I/O Mode Control 0x0 read-write n 0x0 0x0 MODE0 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 0 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 MODE1 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 2 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 MODE10 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 20 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 MODE11 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 22 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 MODE12 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 24 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 MODE13 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 26 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 MODE14 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 28 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 MODE15 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 30 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 MODE2 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 4 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 MODE3 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 6 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 MODE4 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 8 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 MODE5 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 10 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 MODE6 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 12 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 MODE7 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 14 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 MODE8 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 16 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 MODE9 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 18 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Reserved #11 PA_PIN PA_PIN PA Pin Value 0x10 read-only n 0x0 0x0 PIN0 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 0 1 read-only PIN1 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 1 1 read-only PIN10 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 10 1 read-only PIN11 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 11 1 read-only PIN12 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 12 1 read-only PIN13 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 13 1 read-only PIN14 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 14 1 read-only PIN15 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 15 1 read-only PIN2 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 2 1 read-only PIN3 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 3 1 read-only PIN4 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 4 1 read-only PIN5 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 5 1 read-only PIN6 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 6 1 read-only PIN7 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 7 1 read-only PIN8 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 8 1 read-only PIN9 Port A-f Pin[N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: ThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 9 1 read-only PA_PUEN PA_PUEN PA Pull-Up Enable Control Register 0x24 read-write n 0x0 0x0 PUEN0 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 0 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PUEN1 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 1 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PUEN10 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 10 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PUEN11 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 11 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PUEN12 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 12 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PUEN13 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 13 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PUEN14 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 14 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PUEN15 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 15 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PUEN2 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 2 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PUEN3 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 3 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PUEN4 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 4 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PUEN5 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 5 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PUEN6 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 6 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PUEN7 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 7 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PUEN8 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 8 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PUEN9 Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. 9 1 read-write 0 Px.n internal pull-up resistor Disabled #0 1 Px.n internal pull-up resistor Enabled #1 PB0_PDIO PB0_PDIO GPIO PB.0 Pin Data Input/Output Register 0x240 read-write n 0x0 0x0 PB10_PDIO PB10_PDIO GPIO PB.10 Pin Data Input/Output Register 0x268 read-write n 0x0 0x0 PB11_PDIO PB11_PDIO GPIO PB.11 Pin Data Input/Output Register 0x26C read-write n 0x0 0x0 PB12_PDIO PB12_PDIO GPIO PB.12 Pin Data Input/Output Register 0x270 read-write n 0x0 0x0 PB13_PDIO PB13_PDIO GPIO PB.13 Pin Data Input/Output Register 0x274 read-write n 0x0 0x0 PB14_PDIO PB14_PDIO GPIO PB.14 Pin Data Input/Output Register 0x278 read-write n 0x0 0x0 PB15_PDIO PB15_PDIO GPIO PB.15 Pin Data Input/Output Register 0x27C read-write n 0x0 0x0 PB1_PDIO PB1_PDIO GPIO PB.1 Pin Data Input/Output Register 0x244 read-write n 0x0 0x0 PB2_PDIO PB2_PDIO GPIO PB.2 Pin Data Input/Output Register 0x248 read-write n 0x0 0x0 PB3_PDIO PB3_PDIO GPIO PB.3 Pin Data Input/Output Register 0x24C read-write n 0x0 0x0 PB4_PDIO PB4_PDIO GPIO PB.4 Pin Data Input/Output Register 0x250 read-write n 0x0 0x0 PB5_PDIO PB5_PDIO GPIO PB.5 Pin Data Input/Output Register 0x254 read-write n 0x0 0x0 PB6_PDIO PB6_PDIO GPIO PB.6 Pin Data Input/Output Register 0x258 read-write n 0x0 0x0 PB7_PDIO PB7_PDIO GPIO PB.7 Pin Data Input/Output Register 0x25C read-write n 0x0 0x0 PB8_PDIO PB8_PDIO GPIO PB.8 Pin Data Input/Output Register 0x260 read-write n 0x0 0x0 PB9_PDIO PB9_PDIO GPIO PB.9 Pin Data Input/Output Register 0x264 read-write n 0x0 0x0 PB_DATMSK PB_DATMSK PB Data Output Write Mask 0x4C read-write n 0x0 0x0 PB_DBEN PB_DBEN PB De-Bounce Enable Control Register 0x54 read-write n 0x0 0x0 PB_DINOFF PB_DINOFF PB Digital Input Path Disable Control 0x44 read-write n 0x0 0x0 PB_DOUT PB_DOUT PB Data Output Value 0x48 read-write n 0x0 0x0 PB_INTEN PB_INTEN PB Interrupt Enable Control Register 0x5C read-write n 0x0 0x0 PB_INTSRC PB_INTSRC PB Interrupt Source Flag 0x60 read-write n 0x0 0x0 PB_INTSTS PB_INTSTS PB Interrupt Status 0x68 read-write n 0x0 0x0 PB_INTTYPE PB_INTTYPE PB Interrupt Trigger Type Control 0x58 read-write n 0x0 0x0 PB_MODE PB_MODE PB I/O Mode Control 0x40 read-write n 0x0 0x0 PB_PIN PB_PIN PB Pin Value 0x50 read-write n 0x0 0x0 PB_PUEN PB_PUEN PB Pull-Up Enable Control Register 0x64 read-write n 0x0 0x0 PC0_PDIO PC0_PDIO GPIO PC.0 Pin Data Input/Output Register 0x280 read-write n 0x0 0x0 PC10_PDIO PC10_PDIO GPIO PC.10 Pin Data Input/Output Register 0x2A8 read-write n 0x0 0x0 PC11_PDIO PC11_PDIO GPIO PC.11 Pin Data Input/Output Register 0x2AC read-write n 0x0 0x0 PC12_PDIO PC12_PDIO GPIO PC.12 Pin Data Input/Output Register 0x2B0 read-write n 0x0 0x0 PC13_PDIO PC13_PDIO GPIO PC.13 Pin Data Input/Output Register 0x2B4 read-write n 0x0 0x0 PC14_PDIO PC14_PDIO GPIO PC.14 Pin Data Input/Output Register 0x2B8 read-write n 0x0 0x0 PC15_PDIO PC15_PDIO GPIO PC.15 Pin Data Input/Output Register 0x2BC read-write n 0x0 0x0 PC1_PDIO PC1_PDIO GPIO PC.1 Pin Data Input/Output Register 0x284 read-write n 0x0 0x0 PC2_PDIO PC2_PDIO GPIO PC.2 Pin Data Input/Output Register 0x288 read-write n 0x0 0x0 PC3_PDIO PC3_PDIO GPIO PC.3 Pin Data Input/Output Register 0x28C read-write n 0x0 0x0 PC4_PDIO PC4_PDIO GPIO PC.4 Pin Data Input/Output Register 0x290 read-write n 0x0 0x0 PC5_PDIO PC5_PDIO GPIO PC.5 Pin Data Input/Output Register 0x294 read-write n 0x0 0x0 PC6_PDIO PC6_PDIO GPIO PC.6 Pin Data Input/Output Register 0x298 read-write n 0x0 0x0 PC7_PDIO PC7_PDIO GPIO PC.7 Pin Data Input/Output Register 0x29C read-write n 0x0 0x0 PC8_PDIO PC8_PDIO GPIO PC.8 Pin Data Input/Output Register 0x2A0 read-write n 0x0 0x0 PC9_PDIO PC9_PDIO GPIO PC.9 Pin Data Input/Output Register 0x2A4 read-write n 0x0 0x0 PC_DATMSK PC_DATMSK PC Data Output Write Mask 0x8C read-write n 0x0 0x0 PC_DBEN PC_DBEN PC De-Bounce Enable Control Register 0x94 read-write n 0x0 0x0 PC_DINOFF PC_DINOFF PC Digital Input Path Disable Control 0x84 read-write n 0x0 0x0 PC_DOUT PC_DOUT PC Data Output Value 0x88 read-write n 0x0 0x0 PC_INTEN PC_INTEN PC Interrupt Enable Control Register 0x9C read-write n 0x0 0x0 PC_INTSRC PC_INTSRC PC Interrupt Source Flag 0xA0 read-write n 0x0 0x0 PC_INTSTS PC_INTSTS PC Interrupt Status 0xA8 read-write n 0x0 0x0 PC_INTTYPE PC_INTTYPE PC Interrupt Trigger Type Control 0x98 read-write n 0x0 0x0 PC_MODE PC_MODE PC I/O Mode Control 0x80 read-write n 0x0 0x0 PC_PIN PC_PIN PC Pin Value 0x90 read-write n 0x0 0x0 PC_PUEN PC_PUEN PC Pull-Up Enable Control Register 0xA4 read-write n 0x0 0x0 PD0_PDIO PD0_PDIO GPIO PD.0 Pin Data Input/Output Register 0x2C0 read-write n 0x0 0x0 PD10_PDIO PD10_PDIO GPIO PD.10 Pin Data Input/Output Register 0x2E8 read-write n 0x0 0x0 PD11_PDIO PD11_PDIO GPIO PD.11 Pin Data Input/Output Register 0x2EC read-write n 0x0 0x0 PD12_PDIO PD12_PDIO GPIO PD.12 Pin Data Input/Output Register 0x2F0 read-write n 0x0 0x0 PD13_PDIO PD13_PDIO GPIO PD.13 Pin Data Input/Output Register 0x2F4 read-write n 0x0 0x0 PD14_PDIO PD14_PDIO GPIO PD.14 Pin Data Input/Output Register 0x2F8 read-write n 0x0 0x0 PD15_PDIO PD15_PDIO GPIO PD.15 Pin Data Input/Output Register 0x2FC read-write n 0x0 0x0 PD1_PDIO PD1_PDIO GPIO PD.1 Pin Data Input/Output Register 0x2C4 read-write n 0x0 0x0 PD2_PDIO PD2_PDIO GPIO PD.2 Pin Data Input/Output Register 0x2C8 read-write n 0x0 0x0 PD3_PDIO PD3_PDIO GPIO PD.3 Pin Data Input/Output Register 0x2CC read-write n 0x0 0x0 PD4_PDIO PD4_PDIO GPIO PD.4 Pin Data Input/Output Register 0x2D0 read-write n 0x0 0x0 PD5_PDIO PD5_PDIO GPIO PD.5 Pin Data Input/Output Register 0x2D4 read-write n 0x0 0x0 PD6_PDIO PD6_PDIO GPIO PD.6 Pin Data Input/Output Register 0x2D8 read-write n 0x0 0x0 PD7_PDIO PD7_PDIO GPIO PD.7 Pin Data Input/Output Register 0x2DC read-write n 0x0 0x0 PD8_PDIO PD8_PDIO GPIO PD.8 Pin Data Input/Output Register 0x2E0 read-write n 0x0 0x0 PD9_PDIO PD9_PDIO GPIO PD.9 Pin Data Input/Output Register 0x2E4 read-write n 0x0 0x0 PD_DATMSK PD_DATMSK PD Data Output Write Mask 0xCC read-write n 0x0 0x0 PD_DBEN PD_DBEN PD De-Bounce Enable Control Register 0xD4 read-write n 0x0 0x0 PD_DINOFF PD_DINOFF PD Digital Input Path Disable Control 0xC4 read-write n 0x0 0x0 PD_DOUT PD_DOUT PD Data Output Value 0xC8 read-write n 0x0 0x0 PD_INTEN PD_INTEN PD Interrupt Enable Control Register 0xDC read-write n 0x0 0x0 PD_INTSRC PD_INTSRC PD Interrupt Source Flag 0xE0 read-write n 0x0 0x0 PD_INTSTS PD_INTSTS PD Interrupt Status 0xE8 read-write n 0x0 0x0 PD_INTTYPE PD_INTTYPE PD Interrupt Trigger Type Control 0xD8 read-write n 0x0 0x0 PD_MODE PD_MODE PD I/O Mode Control 0xC0 read-write n 0x0 0x0 PD_PIN PD_PIN PD Pin Value 0xD0 read-write n 0x0 0x0 PD_PUEN PD_PUEN PD Pull-Up Enable Control Register 0xE4 read-write n 0x0 0x0 PE0_PDIO PE0_PDIO GPIO PE.0 Pin Data Input/Output Register 0x300 read-write n 0x0 0x0 PE10_PDIO PE10_PDIO GPIO PE.10 Pin Data Input/Output Register 0x328 read-write n 0x0 0x0 PE11_PDIO PE11_PDIO GPIO PE.11 Pin Data Input/Output Register 0x32C read-write n 0x0 0x0 PE12_PDIO PE12_PDIO GPIO PE.12 Pin Data Input/Output Register 0x330 read-write n 0x0 0x0 PE13_PDIO PE13_PDIO GPIO PE.13 Pin Data Input/Output Register 0x334 read-write n 0x0 0x0 PE14_PDIO PE14_PDIO GPIO PE.14 Pin Data Input/Output Register 0x338 read-write n 0x0 0x0 PE1_PDIO PE1_PDIO GPIO PE.1 Pin Data Input/Output Register 0x304 read-write n 0x0 0x0 PE2_PDIO PE2_PDIO GPIO PE.2 Pin Data Input/Output Register 0x308 read-write n 0x0 0x0 PE3_PDIO PE3_PDIO GPIO PE.3 Pin Data Input/Output Register 0x30C read-write n 0x0 0x0 PE4_PDIO PE4_PDIO GPIO PE.4 Pin Data Input/Output Register 0x310 read-write n 0x0 0x0 PE5_PDIO PE5_PDIO GPIO PE.5 Pin Data Input/Output Register 0x314 read-write n 0x0 0x0 PE6_PDIO PE6_PDIO GPIO PE.6 Pin Data Input/Output Register 0x318 read-write n 0x0 0x0 PE7_PDIO PE7_PDIO GPIO PE.7 Pin Data Input/Output Register 0x31C read-write n 0x0 0x0 PE8_PDIO PE8_PDIO GPIO PE.8 Pin Data Input/Output Register 0x320 read-write n 0x0 0x0 PE9_PDIO PE9_PDIO GPIO PE.9 Pin Data Input/Output Register 0x324 read-write n 0x0 0x0 PE_DATMSK PE_DATMSK PE Data Output Write Mask 0x10C read-write n 0x0 0x0 PE_DBEN PE_DBEN PE De-Bounce Enable Control Register 0x114 read-write n 0x0 0x0 PE_DINOFF PE_DINOFF PE Digital Input Path Disable Control 0x104 read-write n 0x0 0x0 PE_DOUT PE_DOUT PE Data Output Value 0x108 read-write n 0x0 0x0 PE_INTEN PE_INTEN PE Interrupt Enable Control Register 0x11C read-write n 0x0 0x0 PE_INTSRC PE_INTSRC PE Interrupt Source Flag 0x120 read-write n 0x0 0x0 PE_INTSTS PE_INTSTS PE Interrupt Status 0x128 read-write n 0x0 0x0 PE_INTTYPE PE_INTTYPE PE Interrupt Trigger Type Control 0x118 read-write n 0x0 0x0 PE_MODE PE_MODE PE I/O Mode Control 0x100 read-write n 0x0 0x0 PE_PIN PE_PIN PE Pin Value 0x110 read-write n 0x0 0x0 PE_PUEN PE_PUEN PE Pull-Up Enable Control Register 0x124 read-write n 0x0 0x0 PF0_PDIO PF0_PDIO GPIO PF.0 Pin Data Input/Output Register 0x340 read-write n 0x0 0x0 PF1_PDIO PF1_PDIO GPIO PF.1 Pin Data Input/Output Register 0x344 read-write n 0x0 0x0 PF2_PDIO PF2_PDIO GPIO PF.2 Pin Data Input/Output Register 0x348 read-write n 0x0 0x0 PF3_PDIO PF3_PDIO GPIO PF.3 Pin Data Input/Output Register 0x34C read-write n 0x0 0x0 PF4_PDIO PF4_PDIO GPIO PF.4 Pin Data Input/Output Register 0x350 read-write n 0x0 0x0 PF5_PDIO PF5_PDIO GPIO PF.5 Pin Data Input/Output Register 0x354 read-write n 0x0 0x0 PF6_PDIO PF6_PDIO GPIO PF.6 Pin Data Input/Output Register 0x358 read-write n 0x0 0x0 PF7_PDIO PF7_PDIO GPIO PF.7 Pin Data Input/Output Register 0x35C read-write n 0x0 0x0 PF_DATMSK PF_DATMSK PF Data Output Write Mask 0x14C read-write n 0x0 0x0 PF_DBEN PF_DBEN PF De-Bounce Enable Control Register 0x154 read-write n 0x0 0x0 PF_DINOFF PF_DINOFF PF Digital Input Path Disable Control 0x144 read-write n 0x0 0x0 PF_DOUT PF_DOUT PF Data Output Value 0x148 read-write n 0x0 0x0 PF_INTEN PF_INTEN PF Interrupt Enable Control Register 0x15C read-write n 0x0 0x0 PF_INTSRC PF_INTSRC PF Interrupt Source Flag 0x160 read-write n 0x0 0x0 PF_INTSTS PF_INTSTS PF Interrupt Status 0x168 read-write n 0x0 0x0 PF_INTTYPE PF_INTTYPE PF Interrupt Trigger Type Control 0x158 read-write n 0x0 0x0 PF_MODE PF_MODE PF I/O Mode Control 0x140 read-write n 0x0 0x0 PF_PIN PF_PIN PF Pin Value 0x150 read-write n 0x0 0x0 PF_PUEN PF_PUEN PF Pull-Up Enable Control Register 0x164 read-write n 0x0 0x0 I2C0 I2C Register Map I2C 0x0 0x0 0x20 registers n 0x28 0x8 registers n 0x40 0x8 registers n I2C_ADDR0 I2C_ADDR0 I2C Slave Address Register0 0x18 read-write n 0x0 0x0 ADDR I2C Salve Address Bits\nThe content of this register is irrelevant when the device is in Master mode. In the Slave mode, the seven most significant bits must be loaded with the device's own address. The device will react if either of the address is matched. 1 7 read-write GC General Call FunctionControl\nNote: Refer to Address Register section for more detailed information.. 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 I2C_ADDR1 I2C_ADDR1 I2C Slave Address Register1 0x1C read-write n 0x0 0x0 I2C_ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register0 0x28 read-write n 0x0 0x0 ADDRMSK I2C Slave Address Mask Bits\nI2C bus controllers support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 1 7 read-write 0 Mask disable (the received corresponding register bit should be exact the same as address register) 0 1 Mask enable (the received corresponding address bit is don't care) 1 I2C_ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register1 0x2C read-write n 0x0 0x0 I2C_CLKDIV I2C_CLKDIV I2C Clock Divided Register 0xC read-write n 0x0 0x0 DIVIDER I2C Clock DividedBits\nNote:The minimum value of I2C_CLKDIV is 4. 0 8 read-write I2C_CTL I2C_CTL I2C Control Register 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control Bit 1 1 read-write I2CEN I2C Function EnableBit 0 1 read-write 0 I2C function Disabled #0 1 I2C function Enabled #1 INTEN Interrupt EnableBit 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 SI I2C Status\nWhen a new state is present in the I2C_STATUS register, if the INTEN bit is set, the I2C interrupt is requested. It must write one by software to this bit after the INTSTS (I2C_INTSTS[0]) is set to 1 and the I2C protocol function will go ahead until the STOP is active or the I2CEN is disabled.\nNote:If software wants to skip clearing INTSTS (I2C_INTSTS[0]), it also can write 1 to SI bit and must set INTEN bit. That INTSTS (I2C_INTSTS[0]) wll be cleared when SI is cleared. 4 1 read-write 0 I2C's Status disabled and the I2C protocol function will go ahead #0 1 I2C's Status active #1 STA I2C START Command\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 3 1 read-write STO I2C STOP Control Bit\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically. 2 1 read-write I2C_CTL2 I2C_CTL2 I2C Control Register 2 0x40 read-write n 0x0 0x0 DATMODE Data Mode Enable Bit 6 1 read-write 0 Data mode Disabled #0 1 Data mode Enabled #1 MSDAT Master or Slave in Data Mode Enable Control 7 1 read-write 0 Master writes data to device #0 1 Slave reads data from device #1 NOSTRETCH I2C BuS Stretch 5 1 read-write 0 The I2C SCL bus is stretched by hardware if the SI (I2C_CTL[4]) is not cleared #0 1 The I2C SCL bus is not stretched by hardware if the SI is not cleared #1 OVIEN I2C Overrun Interrupt Control Bit 1 1 read-write 0 Overrun event interrupt Disabled #0 1 Send a interrupt to system when the TWOLVBUF bit is enabled and there is overrun event in received buffer #1 TWOLVBUF Two Level Buffer Enable Bit 4 1 read-write 0 Two level bufferDisabled #0 1 Two level bufferEnabled #1 URIEN I2C Underrun Interrupt Control Bit 2 1 read-write 0 Underrun event interrupt Disabled #0 1 Send a interrupt to system when theTWOLVBUF bit is enabled and there is underrun event happened in transmitted buffer #1 WKUPEN I2C Wake-up Function EnableBit 0 1 read-write 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 I2C_DAT I2C_DAT I2C Data Register 0x14 read-write n 0x0 0x0 DAT I2C Data\nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port. 0 8 read-write I2C_INTSTS I2C_INTSTS I2C Interrupt Status Register 0x4 read-write n 0x0 0x0 INTSTS I2C STATUS's Interrupt Status\nWhen a new I2C state is present in the I2C_STATUS register, the INTSTS flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested.This bit must be cleared by software writing '1' .\nNote:If software wants to skip clearing INTSTS, it can also write 1 to SI (I2C_CTL [4]) bit and must set INTEN (I2C_CTL [7]) bit. INISTS wll be cleared when SI is cleared. 0 1 read-write TOIF Time-out Status\nNote:This bit can be cleared by writing '1' to it. 1 1 read-write 0 No Time-out flag #0 1 Time-out flag active and it is set by hardware. It can interrupt CPU when INTEN bit is set #1 WKAKDONE Wake-up Address Frame Acknowledge Bit Done\nNote:This bit can be cleared by writing'1' toit. 7 1 read-write 0 The ACK bit cycle of address match frame is not done #0 1 The ACK bit cycle of address match frame is done in power-down #1 I2C_STATUS I2C_STATUS I2C Status Register 0x8 -1 read-only n 0x0 0x0 STATUS I2C Status Bits (Read Only) 0 8 read-only I2C_STATUS2 I2C_STATUS2 I2C Status Register 2 0x44 -1 read-write n 0x0 0x0 BUSFREE Bus Free Status\nThe bus status in the controller. 6 1 read-write 0 I2C's Start condition is detected on the bus #0 1 Bus is free and released by STOP condition or the controller is disabled #1 EMPTY I2C Two Level Buffer Empty 5 1 read-write 0 RX buffer is not empty when the TWOLVBUF = 1 #0 1 RX buffer is empty when the TWOLVBUF = 1 #1 FULL I2C Two Level Buffer Full 4 1 read-write 0 TX buffer no full when the TWOLVBUF = 1 #0 1 TX buffer full when the TWOLVBUF = 1 #1 OVIF I2C Overrun Status Bit\nNote:This bit can be cleared by writing '1' toit. 1 1 read-write 0 The received buffer is not overrun when the TWOLVBUF = 1 #0 1 The received buffer is overrun when the TWOLVBUF = 1 #1 URIF I2C Underrun Status Bit\nNote:This bit can be cleared by writing '1' toit. 2 1 read-write 0 The transmitted buffer is not underrun when the TWOLVBUF = 1 #0 1 The transmitted buffer is underrun when the TWOLVBUF = 1 #1 WKIF Wake-up Interrupt Flag\nNote:This bit can be cleared by writing '1' toit. 0 1 read-write 0 Wake-up flag is inactive #0 1 Wake-up flag is active #1 WRSTSWK I2C Read/Write Status Bit in Address Wake-up Frame 3 1 read-write 0 Write command is recorded on the address match wake-up frame #0 1 Read command is recorded on the address match wake-up frame #1 I2C_TOCTL I2C_TOCTL I2C Time-out Control Register 0x10 read-write n 0x0 0x0 TOCDIV4 Time-out Counter Input Clock Divider by 4\nWhen enabled, the time-out period is extended 4 times. 1 1 read-write 0 Time-out counter input clock divider by 4Disabled #0 1 Time-out counter input clock divider by 4 Enabled #1 TOCEN Time-out Counter Enable Bit\nWhen this bit is set to enabled and clcok be stretched, the 14 bits time-out counter will start counting. 0 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 I2C1 I2C Register Map I2C 0x0 0x0 0x20 registers n 0x28 0x8 registers n 0x40 0x8 registers n I2C_ADDR0 I2C_ADDR0 I2C Slave Address Register0 0x18 read-write n 0x0 0x0 ADDR I2C Salve Address Bits\nThe content of this register is irrelevant when the device is in Master mode. In the Slave mode, the seven most significant bits must be loaded with the device's own address. The device will react if either of the address is matched. 1 7 read-write GC General Call FunctionControl\nNote: Refer to Address Register section for more detailed information.. 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 I2C_ADDR1 I2C_ADDR1 I2C Slave Address Register1 0x1C read-write n 0x0 0x0 I2C_ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register0 0x28 read-write n 0x0 0x0 ADDRMSK I2C Slave Address Mask Bits\nI2C bus controllers support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 1 7 read-write 0 Mask disable (the received corresponding register bit should be exact the same as address register) 0 1 Mask enable (the received corresponding address bit is don't care) 1 I2C_ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register1 0x2C read-write n 0x0 0x0 I2C_CLKDIV I2C_CLKDIV I2C Clock Divided Register 0xC read-write n 0x0 0x0 DIVIDER I2C Clock DividedBits\nNote:The minimum value of I2C_CLKDIV is 4. 0 8 read-write I2C_CTL I2C_CTL I2C Control Register 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control Bit 1 1 read-write I2CEN I2C Function EnableBit 0 1 read-write 0 I2C function Disabled #0 1 I2C function Enabled #1 INTEN Interrupt EnableBit 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 SI I2C Status\nWhen a new state is present in the I2C_STATUS register, if the INTEN bit is set, the I2C interrupt is requested. It must write one by software to this bit after the INTSTS (I2C_INTSTS[0]) is set to 1 and the I2C protocol function will go ahead until the STOP is active or the I2CEN is disabled.\nNote:If software wants to skip clearing INTSTS (I2C_INTSTS[0]), it also can write 1 to SI bit and must set INTEN bit. That INTSTS (I2C_INTSTS[0]) wll be cleared when SI is cleared. 4 1 read-write 0 I2C's Status disabled and the I2C protocol function will go ahead #0 1 I2C's Status active #1 STA I2C START Command\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 3 1 read-write STO I2C STOP Control Bit\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically. 2 1 read-write I2C_CTL2 I2C_CTL2 I2C Control Register 2 0x40 read-write n 0x0 0x0 DATMODE Data Mode Enable Bit 6 1 read-write 0 Data mode Disabled #0 1 Data mode Enabled #1 MSDAT Master or Slave in Data Mode Enable Control 7 1 read-write 0 Master writes data to device #0 1 Slave reads data from device #1 NOSTRETCH I2C BuS Stretch 5 1 read-write 0 The I2C SCL bus is stretched by hardware if the SI (I2C_CTL[4]) is not cleared #0 1 The I2C SCL bus is not stretched by hardware if the SI is not cleared #1 OVIEN I2C Overrun Interrupt Control Bit 1 1 read-write 0 Overrun event interrupt Disabled #0 1 Send a interrupt to system when the TWOLVBUF bit is enabled and there is overrun event in received buffer #1 TWOLVBUF Two Level Buffer Enable Bit 4 1 read-write 0 Two level bufferDisabled #0 1 Two level bufferEnabled #1 URIEN I2C Underrun Interrupt Control Bit 2 1 read-write 0 Underrun event interrupt Disabled #0 1 Send a interrupt to system when theTWOLVBUF bit is enabled and there is underrun event happened in transmitted buffer #1 WKUPEN I2C Wake-up Function EnableBit 0 1 read-write 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 I2C_DAT I2C_DAT I2C Data Register 0x14 read-write n 0x0 0x0 DAT I2C Data\nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port. 0 8 read-write I2C_INTSTS I2C_INTSTS I2C Interrupt Status Register 0x4 read-write n 0x0 0x0 INTSTS I2C STATUS's Interrupt Status\nWhen a new I2C state is present in the I2C_STATUS register, the INTSTS flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested.This bit must be cleared by software writing '1' .\nNote:If software wants to skip clearing INTSTS, it can also write 1 to SI (I2C_CTL [4]) bit and must set INTEN (I2C_CTL [7]) bit. INISTS wll be cleared when SI is cleared. 0 1 read-write TOIF Time-out Status\nNote:This bit can be cleared by writing '1' to it. 1 1 read-write 0 No Time-out flag #0 1 Time-out flag active and it is set by hardware. It can interrupt CPU when INTEN bit is set #1 WKAKDONE Wake-up Address Frame Acknowledge Bit Done\nNote:This bit can be cleared by writing'1' toit. 7 1 read-write 0 The ACK bit cycle of address match frame is not done #0 1 The ACK bit cycle of address match frame is done in power-down #1 I2C_STATUS I2C_STATUS I2C Status Register 0x8 -1 read-only n 0x0 0x0 STATUS I2C Status Bits (Read Only) 0 8 read-only I2C_STATUS2 I2C_STATUS2 I2C Status Register 2 0x44 -1 read-write n 0x0 0x0 BUSFREE Bus Free Status\nThe bus status in the controller. 6 1 read-write 0 I2C's Start condition is detected on the bus #0 1 Bus is free and released by STOP condition or the controller is disabled #1 EMPTY I2C Two Level Buffer Empty 5 1 read-write 0 RX buffer is not empty when the TWOLVBUF = 1 #0 1 RX buffer is empty when the TWOLVBUF = 1 #1 FULL I2C Two Level Buffer Full 4 1 read-write 0 TX buffer no full when the TWOLVBUF = 1 #0 1 TX buffer full when the TWOLVBUF = 1 #1 OVIF I2C Overrun Status Bit\nNote:This bit can be cleared by writing '1' toit. 1 1 read-write 0 The received buffer is not overrun when the TWOLVBUF = 1 #0 1 The received buffer is overrun when the TWOLVBUF = 1 #1 URIF I2C Underrun Status Bit\nNote:This bit can be cleared by writing '1' toit. 2 1 read-write 0 The transmitted buffer is not underrun when the TWOLVBUF = 1 #0 1 The transmitted buffer is underrun when the TWOLVBUF = 1 #1 WKIF Wake-up Interrupt Flag\nNote:This bit can be cleared by writing '1' toit. 0 1 read-write 0 Wake-up flag is inactive #0 1 Wake-up flag is active #1 WRSTSWK I2C Read/Write Status Bit in Address Wake-up Frame 3 1 read-write 0 Write command is recorded on the address match wake-up frame #0 1 Read command is recorded on the address match wake-up frame #1 I2C_TOCTL I2C_TOCTL I2C Time-out Control Register 0x10 read-write n 0x0 0x0 TOCDIV4 Time-out Counter Input Clock Divider by 4\nWhen enabled, the time-out period is extended 4 times. 1 1 read-write 0 Time-out counter input clock divider by 4Disabled #0 1 Time-out counter input clock divider by 4 Enabled #1 TOCEN Time-out Counter Enable Bit\nWhen this bit is set to enabled and clcok be stretched, the 14 bits time-out counter will start counting. 0 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 INT SCS Register Map SCS 0x0 0x0 0x88 registers n IRQ0_SRC IRQ0_SRC MCU IRQ0 (BOD_INT) interrupt source identify 0x0 read-only n 0x0 0x0 INT_SRC Interrupt Source\nDefine the interrupt sources for interrupt event. 0 4 read-only IRQ10_SRC IRQ10_SRC MCU IRQ10 (BOD_INT) interrupt source identify 0x28 read-write n 0x0 0x0 IRQ11_SRC IRQ11_SRC MCU IRQ11 (BOD_INT) interrupt source identify 0x2C read-write n 0x0 0x0 IRQ12_SRC IRQ12_SRC MCU IRQ12 (BOD_INT) interrupt source identify 0x30 read-write n 0x0 0x0 IRQ13_SRC IRQ13_SRC MCU IRQ13 (BOD_INT) interrupt source identify 0x34 read-write n 0x0 0x0 IRQ14_SRC IRQ14_SRC MCU IRQ14 (BOD_INT) interrupt source identify 0x38 read-write n 0x0 0x0 IRQ15_SRC IRQ15_SRC MCU IRQ15 (BOD_INT) interrupt source identify 0x3C read-write n 0x0 0x0 IRQ16_SRC IRQ16_SRC MCU IRQ16 (BOD_INT) interrupt source identify 0x40 read-write n 0x0 0x0 IRQ17_SRC IRQ17_SRC MCU IRQ17 (BOD_INT) interrupt source identify 0x44 read-write n 0x0 0x0 IRQ18_SRC IRQ18_SRC MCU IRQ18 (BOD_INT) interrupt source identify 0x48 read-write n 0x0 0x0 IRQ19_SRC IRQ19_SRC MCU IRQ19 (BOD_INT) interrupt source identify 0x4C read-write n 0x0 0x0 IRQ1_SRC IRQ1_SRC MCU IRQ1 (BOD_INT) interrupt source identify 0x4 read-write n 0x0 0x0 IRQ20_SRC IRQ20_SRC MCU IRQ20 (BOD_INT) interrupt source identify 0x50 read-write n 0x0 0x0 IRQ21_SRC IRQ21_SRC MCU IRQ21 (BOD_INT) interrupt source identify 0x54 read-write n 0x0 0x0 IRQ22_SRC IRQ22_SRC MCU IRQ22 (BOD_INT) interrupt source identify 0x58 read-write n 0x0 0x0 IRQ23_SRC IRQ23_SRC MCU IRQ23 (BOD_INT) interrupt source identify 0x5C read-write n 0x0 0x0 IRQ24_SRC IRQ24_SRC MCU IRQ24 (BOD_INT) interrupt source identify 0x60 read-write n 0x0 0x0 IRQ25_SRC IRQ25_SRC MCU IRQ25 (BOD_INT) interrupt source identify 0x64 read-write n 0x0 0x0 IRQ26_SRC IRQ26_SRC MCU IRQ26 (BOD_INT) interrupt source identify 0x68 read-write n 0x0 0x0 IRQ27_SRC IRQ27_SRC MCU IRQ27 (BOD_INT) interrupt source identify 0x6C read-write n 0x0 0x0 IRQ28_SRC IRQ28_SRC MCU IRQ28 (BOD_INT) interrupt source identify 0x70 read-write n 0x0 0x0 IRQ29_SRC IRQ29_SRC MCU IRQ29 (BOD_INT) interrupt source identify 0x74 read-write n 0x0 0x0 IRQ2_SRC IRQ2_SRC MCU IRQ2 (BOD_INT) interrupt source identify 0x8 read-write n 0x0 0x0 IRQ30_SRC IRQ30_SRC MCU IRQ30 (BOD_INT) interrupt source identify 0x78 read-write n 0x0 0x0 IRQ31_SRC IRQ31_SRC MCU IRQ31 (BOD_INT) interrupt source identify 0x7C read-write n 0x0 0x0 IRQ3_SRC IRQ3_SRC MCU IRQ3 (BOD_INT) interrupt source identify 0xC read-write n 0x0 0x0 IRQ4_SRC IRQ4_SRC MCU IRQ4 (BOD_INT) interrupt source identify 0x10 read-write n 0x0 0x0 IRQ5_SRC IRQ5_SRC MCU IRQ5 (BOD_INT) interrupt source identify 0x14 read-write n 0x0 0x0 IRQ6_SRC IRQ6_SRC MCU IRQ6 (BOD_INT) interrupt source identify 0x18 read-write n 0x0 0x0 IRQ7_SRC IRQ7_SRC MCU IRQ7 (BOD_INT) interrupt source identify 0x1C read-write n 0x0 0x0 IRQ8_SRC IRQ8_SRC MCU IRQ8 (BOD_INT) interrupt source identify 0x20 read-write n 0x0 0x0 IRQ9_SRC IRQ9_SRC MCU IRQ9 (BOD_INT) interrupt source identify 0x24 read-write n 0x0 0x0 MCU_IRQ MCU_IRQ MCU Interrupt Request Source Register 0x84 read-write n 0x0 0x0 MCU_IRQ MCU IRQ Source Bits The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to MCU Cortex-M0. There are two modes to generate interrupt to Cortex-M0, the normal mode. The MCU_IRQ collects all interrupts from each peripheral and synchronizes them and then interrupts the Cortex-M0. When the MCU_IRQ[n] is 0 , setting MCU_IRQ[n] 1 will generate an interrupt to Cortex-M0 NVIC[n]. When the MCU_IRQ[n] is 1 (means an interrupt is asserted), setting the MCU_bit[n] will clear the interrupt Set MCU_IRQ[n] 0 : no any effect 0 32 read-write NMI_SEL NMI_SEL NMI Source Interrupt Select Control Register 0x80 read-write n 0x0 0x0 NMI_SEL NMI Interrupt to Cortex-M0 Can Be Selected From One of the Interrupt[31:0]\nThe NMI_SEL bit[4:0] is used to select the NMI interrupt source 0 5 read-write PDMA_CH1 PDMA Register Map PDMA 0x0 0x0 0x10 registers n 0x14 0x18 registers n PDMA_CCNTn PDMA_CCNTn PDMA Channel n Current Transfer Count Register 0x1C read-only n 0x0 0x0 CCNT PDMA Current Count Bits (Read Only)\nThis field indicates the current remained transfer count of PDMA. 0 16 read-only PDMA_CDAn PDMA_CDAn PDMA Channel n Current Destination Address Register 0x18 read-only n 0x0 0x0 CDA PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred. 0 32 read-only PDMA_CNTn PDMA_CNTn PDMA Channel n Transfer Count Register 0xC read-write n 0x0 0x0 PCNTITH PDMA Periodic Count Interrupt Threshold\nThis field indicates how many data transferred to generate periodic interrupt\nNote: write 0 to this field to disable this function. 16 16 read-write TCNT PDMA Transfer Count Bits\nThis field indicates a 16-bit transfer count number of PDMA. 0 16 read-write PDMA_CSAn PDMA_CSAn PDMA Channel n Current Source Address Register 0x14 read-only n 0x0 0x0 CSA PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred. 0 32 read-only PDMA_CTLn PDMA_CTLn PDMA Channel n Control Register 0x0 read-write n 0x0 0x0 CHEN PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write DASEL Transfer Destination Address Direction Selection 6 2 read-write 0 Transfer Destination address is incremented successively #00 1 Reserved #01 2 Transfer Destination address is fixed. (This feature can be used when data transferred from multiple sources to a single destination) #10 3 Transfer Destination address is wrapped around (When the PDMA_CCNT is equal to 0, the PDMA_CDA and PDMA_CCNT registers will be updated by PDMA_DA and PDMA_CNT automatically. PDMA will start another transfer without user trigger until CHEN disabled. When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address) #11 SASEL Transfer Source Address Direction Selection 4 2 read-write 0 Transfer Source address is incremented successively #00 1 Reserved #01 2 Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) #10 3 Transfer Source address is wrap around (When the PDMA_CCNT is equal to 0, the PDMA_CSA and PDMA_CCNT registers will be updated by PDMA_SA and PDMA_CNT automatically. PDMA will start another transfer without user trigger until CHEN disabled. When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address) #11 SWRST Software Engine Reset 1 1 read-write 0 No effect #0 1 Reset the internal state machine, pointers and internal buffer. The contents of all control registers will not be cleared. This bit will be automatically cleared after few clock cycles #1 TOUTEN Time-out Enable Bit 12 1 read-write 0 PDMA internal counter Disabled #0 1 PDMA internal counter Enabled #1 TRIGEN Trigger Enable Bit \nNote1: When PDMA transfer completed, this bit will be cleared automatically.\nNote2: If the bus error occurs, all PDMA transfer will be stopped. User must reset all PDMA channels, and then trigger again. 23 1 read-write 0 No effect #0 1 PDMA data transfer Enabled #1 TXWIDTH Transfer Width Selection\nThis field is used for transfer width. 19 2 read-write 0 One word (32-bit) is transferred for every PDMA operation #00 1 One byte (8-bit) is transferred for every PDMA operation #01 2 One half-word (16-bit) is transferred for every PDMA operation #10 3 Reserved #11 PDMA_DAn PDMA_DAn PDMA Channel n Destination Address Register 0x8 read-write n 0x0 0x0 DA PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote: The Destination address must be word alignment. 0 32 read-write PDMA_INTENn PDMA_INTENn PDMA Channel n Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 PCNTIEN Periodic Count Interrupt Enable Bit\nThis field indicates how many data transferred to generate interrupt periodically. 8 1 read-write 0 Periodic transfer count interrupt Disabled #0 1 Periodic transfer count interrupt Enabled #1 TABTIEN PDMA Read/Write Target Abort Interrupt Enable Bit 0 1 read-write 0 Target abort interrupt Disabled during PDMA transfer #0 1 Target abort interrupt Enabled during PDMA transfer #1 TDIEN PDMA Transfer Done Interrupt Enable Bit 1 1 read-write 0 Interrupt Disabled when PDMA transfer is done #0 1 Interrupt Enabled when PDMA transfer is done #1 TOUTIEN Time-out Interrupt Enable Bit 6 1 read-write 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 PDMA_INTSTSn PDMA_INTSTSn PDMA Channel n Interrupt Status Register 0x24 read-write n 0x0 0x0 PCNTIF Periodic Count Interrupt Status Flag Note: This bit is cleared by writing 1 to it. 8 1 read-write TABTIF PDMA Read/Write Target Abort Interrupt Status Flag Note1: This bit is cleared by writing 1 to it. Note2: This bit indicates bus master received error response or not, if bus master received error response, it means that PDMA transfer data from an invalid address or to an invalid adress .At this time target abort is happened..PDMA controller will stop transfer and respond this event to user then go to IDLE state. When target abort occurred, user must reset PDMA controller, and then transfer those data again. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 TDIF Transfer Done Interrupt Status Flag This bit indicates that PDMA has finished all transfer. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 Not finished yet #0 1 Done #1 TOUTIF Time-out Interrupt Status Flag This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TOC. Note: This bit is cleared by writing 1 to it. 6 1 read-write 0 No time-out flag #0 1 Time-out flag #1 PDMA_SAn PDMA_SAn PDMA Channel n Source Address Register 0x4 read-write n 0x0 0x0 SA PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. 0 32 read-write PDMA_TOCn PDMA_TOCn PDMA Channel n Time-out Counter Register 0x28 read-write n 0x0 0x0 TOC PDMA Time-out Period Counter 0 16 read-write TPSC PDMA Time-out Counter Clock Source Prescaler 16 3 read-write 0 PDMA time-out clock source is HCLK/28 #000 1 PDMA time-out clock source is HCLK/29 #001 2 PDMA time-out clock source is HCLK/210 #010 3 PDMA time-out clock source is HCLK/211 #011 4 PDMA time-out clock source is HCLK/212 #100 5 PDMA time-out clock source is HCLK/213 #101 6 PDMA time-out clock source is HCLK/214 #110 7 PDMA time-out clock source is HCLK/215 #111 PDMA_CH2 PDMA Register Map PDMA 0x0 0x0 0x10 registers n 0x14 0x18 registers n PDMA_CCNTn PDMA_CCNTn PDMA Channel n Current Transfer Count Register 0x1C read-only n 0x0 0x0 CCNT PDMA Current Count Bits (Read Only)\nThis field indicates the current remained transfer count of PDMA. 0 16 read-only PDMA_CDAn PDMA_CDAn PDMA Channel n Current Destination Address Register 0x18 read-only n 0x0 0x0 CDA PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred. 0 32 read-only PDMA_CNTn PDMA_CNTn PDMA Channel n Transfer Count Register 0xC read-write n 0x0 0x0 PCNTITH PDMA Periodic Count Interrupt Threshold\nThis field indicates how many data transferred to generate periodic interrupt\nNote: write 0 to this field to disable this function. 16 16 read-write TCNT PDMA Transfer Count Bits\nThis field indicates a 16-bit transfer count number of PDMA. 0 16 read-write PDMA_CSAn PDMA_CSAn PDMA Channel n Current Source Address Register 0x14 read-only n 0x0 0x0 CSA PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred. 0 32 read-only PDMA_CTLn PDMA_CTLn PDMA Channel n Control Register 0x0 read-write n 0x0 0x0 CHEN PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write DASEL Transfer Destination Address Direction Selection 6 2 read-write 0 Transfer Destination address is incremented successively #00 1 Reserved #01 2 Transfer Destination address is fixed. (This feature can be used when data transferred from multiple sources to a single destination) #10 3 Transfer Destination address is wrapped around (When the PDMA_CCNT is equal to 0, the PDMA_CDA and PDMA_CCNT registers will be updated by PDMA_DA and PDMA_CNT automatically. PDMA will start another transfer without user trigger until CHEN disabled. When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address) #11 SASEL Transfer Source Address Direction Selection 4 2 read-write 0 Transfer Source address is incremented successively #00 1 Reserved #01 2 Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) #10 3 Transfer Source address is wrap around (When the PDMA_CCNT is equal to 0, the PDMA_CSA and PDMA_CCNT registers will be updated by PDMA_SA and PDMA_CNT automatically. PDMA will start another transfer without user trigger until CHEN disabled. When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address) #11 SWRST Software Engine Reset 1 1 read-write 0 No effect #0 1 Reset the internal state machine, pointers and internal buffer. The contents of all control registers will not be cleared. This bit will be automatically cleared after few clock cycles #1 TOUTEN Time-out Enable Bit 12 1 read-write 0 PDMA internal counter Disabled #0 1 PDMA internal counter Enabled #1 TRIGEN Trigger Enable Bit \nNote1: When PDMA transfer completed, this bit will be cleared automatically.\nNote2: If the bus error occurs, all PDMA transfer will be stopped. User must reset all PDMA channels, and then trigger again. 23 1 read-write 0 No effect #0 1 PDMA data transfer Enabled #1 TXWIDTH Transfer Width Selection\nThis field is used for transfer width. 19 2 read-write 0 One word (32-bit) is transferred for every PDMA operation #00 1 One byte (8-bit) is transferred for every PDMA operation #01 2 One half-word (16-bit) is transferred for every PDMA operation #10 3 Reserved #11 PDMA_DAn PDMA_DAn PDMA Channel n Destination Address Register 0x8 read-write n 0x0 0x0 DA PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote: The Destination address must be word alignment. 0 32 read-write PDMA_INTENn PDMA_INTENn PDMA Channel n Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 PCNTIEN Periodic Count Interrupt Enable Bit\nThis field indicates how many data transferred to generate interrupt periodically. 8 1 read-write 0 Periodic transfer count interrupt Disabled #0 1 Periodic transfer count interrupt Enabled #1 TABTIEN PDMA Read/Write Target Abort Interrupt Enable Bit 0 1 read-write 0 Target abort interrupt Disabled during PDMA transfer #0 1 Target abort interrupt Enabled during PDMA transfer #1 TDIEN PDMA Transfer Done Interrupt Enable Bit 1 1 read-write 0 Interrupt Disabled when PDMA transfer is done #0 1 Interrupt Enabled when PDMA transfer is done #1 TOUTIEN Time-out Interrupt Enable Bit 6 1 read-write 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 PDMA_INTSTSn PDMA_INTSTSn PDMA Channel n Interrupt Status Register 0x24 read-write n 0x0 0x0 PCNTIF Periodic Count Interrupt Status Flag Note: This bit is cleared by writing 1 to it. 8 1 read-write TABTIF PDMA Read/Write Target Abort Interrupt Status Flag Note1: This bit is cleared by writing 1 to it. Note2: This bit indicates bus master received error response or not, if bus master received error response, it means that PDMA transfer data from an invalid address or to an invalid adress .At this time target abort is happened..PDMA controller will stop transfer and respond this event to user then go to IDLE state. When target abort occurred, user must reset PDMA controller, and then transfer those data again. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 TDIF Transfer Done Interrupt Status Flag This bit indicates that PDMA has finished all transfer. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 Not finished yet #0 1 Done #1 TOUTIF Time-out Interrupt Status Flag This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TOC. Note: This bit is cleared by writing 1 to it. 6 1 read-write 0 No time-out flag #0 1 Time-out flag #1 PDMA_SAn PDMA_SAn PDMA Channel n Source Address Register 0x4 read-write n 0x0 0x0 SA PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. 0 32 read-write PDMA_TOCn PDMA_TOCn PDMA Channel n Time-out Counter Register 0x28 read-write n 0x0 0x0 TOC PDMA Time-out Period Counter 0 16 read-write TPSC PDMA Time-out Counter Clock Source Prescaler 16 3 read-write 0 PDMA time-out clock source is HCLK/28 #000 1 PDMA time-out clock source is HCLK/29 #001 2 PDMA time-out clock source is HCLK/210 #010 3 PDMA time-out clock source is HCLK/211 #011 4 PDMA time-out clock source is HCLK/212 #100 5 PDMA time-out clock source is HCLK/213 #101 6 PDMA time-out clock source is HCLK/214 #110 7 PDMA time-out clock source is HCLK/215 #111 PDMA_CH3 PDMA Register Map PDMA 0x0 0x0 0x10 registers n 0x14 0x18 registers n PDMA_CCNTn PDMA_CCNTn PDMA Channel n Current Transfer Count Register 0x1C read-only n 0x0 0x0 CCNT PDMA Current Count Bits (Read Only)\nThis field indicates the current remained transfer count of PDMA. 0 16 read-only PDMA_CDAn PDMA_CDAn PDMA Channel n Current Destination Address Register 0x18 read-only n 0x0 0x0 CDA PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred. 0 32 read-only PDMA_CNTn PDMA_CNTn PDMA Channel n Transfer Count Register 0xC read-write n 0x0 0x0 PCNTITH PDMA Periodic Count Interrupt Threshold\nThis field indicates how many data transferred to generate periodic interrupt\nNote: write 0 to this field to disable this function. 16 16 read-write TCNT PDMA Transfer Count Bits\nThis field indicates a 16-bit transfer count number of PDMA. 0 16 read-write PDMA_CSAn PDMA_CSAn PDMA Channel n Current Source Address Register 0x14 read-only n 0x0 0x0 CSA PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred. 0 32 read-only PDMA_CTLn PDMA_CTLn PDMA Channel n Control Register 0x0 read-write n 0x0 0x0 CHEN PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write DASEL Transfer Destination Address Direction Selection 6 2 read-write 0 Transfer Destination address is incremented successively #00 1 Reserved #01 2 Transfer Destination address is fixed. (This feature can be used when data transferred from multiple sources to a single destination) #10 3 Transfer Destination address is wrapped around (When the PDMA_CCNT is equal to 0, the PDMA_CDA and PDMA_CCNT registers will be updated by PDMA_DA and PDMA_CNT automatically. PDMA will start another transfer without user trigger until CHEN disabled. When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address) #11 SASEL Transfer Source Address Direction Selection 4 2 read-write 0 Transfer Source address is incremented successively #00 1 Reserved #01 2 Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) #10 3 Transfer Source address is wrap around (When the PDMA_CCNT is equal to 0, the PDMA_CSA and PDMA_CCNT registers will be updated by PDMA_SA and PDMA_CNT automatically. PDMA will start another transfer without user trigger until CHEN disabled. When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address) #11 SWRST Software Engine Reset 1 1 read-write 0 No effect #0 1 Reset the internal state machine, pointers and internal buffer. The contents of all control registers will not be cleared. This bit will be automatically cleared after few clock cycles #1 TOUTEN Time-out Enable Bit 12 1 read-write 0 PDMA internal counter Disabled #0 1 PDMA internal counter Enabled #1 TRIGEN Trigger Enable Bit \nNote1: When PDMA transfer completed, this bit will be cleared automatically.\nNote2: If the bus error occurs, all PDMA transfer will be stopped. User must reset all PDMA channels, and then trigger again. 23 1 read-write 0 No effect #0 1 PDMA data transfer Enabled #1 TXWIDTH Transfer Width Selection\nThis field is used for transfer width. 19 2 read-write 0 One word (32-bit) is transferred for every PDMA operation #00 1 One byte (8-bit) is transferred for every PDMA operation #01 2 One half-word (16-bit) is transferred for every PDMA operation #10 3 Reserved #11 PDMA_DAn PDMA_DAn PDMA Channel n Destination Address Register 0x8 read-write n 0x0 0x0 DA PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote: The Destination address must be word alignment. 0 32 read-write PDMA_INTENn PDMA_INTENn PDMA Channel n Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 PCNTIEN Periodic Count Interrupt Enable Bit\nThis field indicates how many data transferred to generate interrupt periodically. 8 1 read-write 0 Periodic transfer count interrupt Disabled #0 1 Periodic transfer count interrupt Enabled #1 TABTIEN PDMA Read/Write Target Abort Interrupt Enable Bit 0 1 read-write 0 Target abort interrupt Disabled during PDMA transfer #0 1 Target abort interrupt Enabled during PDMA transfer #1 TDIEN PDMA Transfer Done Interrupt Enable Bit 1 1 read-write 0 Interrupt Disabled when PDMA transfer is done #0 1 Interrupt Enabled when PDMA transfer is done #1 TOUTIEN Time-out Interrupt Enable Bit 6 1 read-write 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 PDMA_INTSTSn PDMA_INTSTSn PDMA Channel n Interrupt Status Register 0x24 read-write n 0x0 0x0 PCNTIF Periodic Count Interrupt Status Flag Note: This bit is cleared by writing 1 to it. 8 1 read-write TABTIF PDMA Read/Write Target Abort Interrupt Status Flag Note1: This bit is cleared by writing 1 to it. Note2: This bit indicates bus master received error response or not, if bus master received error response, it means that PDMA transfer data from an invalid address or to an invalid adress .At this time target abort is happened..PDMA controller will stop transfer and respond this event to user then go to IDLE state. When target abort occurred, user must reset PDMA controller, and then transfer those data again. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 TDIF Transfer Done Interrupt Status Flag This bit indicates that PDMA has finished all transfer. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 Not finished yet #0 1 Done #1 TOUTIF Time-out Interrupt Status Flag This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TOC. Note: This bit is cleared by writing 1 to it. 6 1 read-write 0 No time-out flag #0 1 Time-out flag #1 PDMA_SAn PDMA_SAn PDMA Channel n Source Address Register 0x4 read-write n 0x0 0x0 SA PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. 0 32 read-write PDMA_TOCn PDMA_TOCn PDMA Channel n Time-out Counter Register 0x28 read-write n 0x0 0x0 TOC PDMA Time-out Period Counter 0 16 read-write TPSC PDMA Time-out Counter Clock Source Prescaler 16 3 read-write 0 PDMA time-out clock source is HCLK/28 #000 1 PDMA time-out clock source is HCLK/29 #001 2 PDMA time-out clock source is HCLK/210 #010 3 PDMA time-out clock source is HCLK/211 #011 4 PDMA time-out clock source is HCLK/212 #100 5 PDMA time-out clock source is HCLK/213 #101 6 PDMA time-out clock source is HCLK/214 #110 7 PDMA time-out clock source is HCLK/215 #111 PDMA_CH4 PDMA Register Map PDMA 0x0 0x0 0x10 registers n 0x14 0x18 registers n PDMA_CCNTn PDMA_CCNTn PDMA Channel n Current Transfer Count Register 0x1C read-only n 0x0 0x0 CCNT PDMA Current Count Bits (Read Only)\nThis field indicates the current remained transfer count of PDMA. 0 16 read-only PDMA_CDAn PDMA_CDAn PDMA Channel n Current Destination Address Register 0x18 read-only n 0x0 0x0 CDA PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred. 0 32 read-only PDMA_CNTn PDMA_CNTn PDMA Channel n Transfer Count Register 0xC read-write n 0x0 0x0 PCNTITH PDMA Periodic Count Interrupt Threshold\nThis field indicates how many data transferred to generate periodic interrupt\nNote: write 0 to this field to disable this function. 16 16 read-write TCNT PDMA Transfer Count Bits\nThis field indicates a 16-bit transfer count number of PDMA. 0 16 read-write PDMA_CSAn PDMA_CSAn PDMA Channel n Current Source Address Register 0x14 read-only n 0x0 0x0 CSA PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred. 0 32 read-only PDMA_CTLn PDMA_CTLn PDMA Channel n Control Register 0x0 read-write n 0x0 0x0 CHEN PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write DASEL Transfer Destination Address Direction Selection 6 2 read-write 0 Transfer Destination address is incremented successively #00 1 Reserved #01 2 Transfer Destination address is fixed. (This feature can be used when data transferred from multiple sources to a single destination) #10 3 Transfer Destination address is wrapped around (When the PDMA_CCNT is equal to 0, the PDMA_CDA and PDMA_CCNT registers will be updated by PDMA_DA and PDMA_CNT automatically. PDMA will start another transfer without user trigger until CHEN disabled. When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address) #11 SASEL Transfer Source Address Direction Selection 4 2 read-write 0 Transfer Source address is incremented successively #00 1 Reserved #01 2 Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) #10 3 Transfer Source address is wrap around (When the PDMA_CCNT is equal to 0, the PDMA_CSA and PDMA_CCNT registers will be updated by PDMA_SA and PDMA_CNT automatically. PDMA will start another transfer without user trigger until CHEN disabled. When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address) #11 SWRST Software Engine Reset 1 1 read-write 0 No effect #0 1 Reset the internal state machine, pointers and internal buffer. The contents of all control registers will not be cleared. This bit will be automatically cleared after few clock cycles #1 TOUTEN Time-out Enable Bit 12 1 read-write 0 PDMA internal counter Disabled #0 1 PDMA internal counter Enabled #1 TRIGEN Trigger Enable Bit \nNote1: When PDMA transfer completed, this bit will be cleared automatically.\nNote2: If the bus error occurs, all PDMA transfer will be stopped. User must reset all PDMA channels, and then trigger again. 23 1 read-write 0 No effect #0 1 PDMA data transfer Enabled #1 TXWIDTH Transfer Width Selection\nThis field is used for transfer width. 19 2 read-write 0 One word (32-bit) is transferred for every PDMA operation #00 1 One byte (8-bit) is transferred for every PDMA operation #01 2 One half-word (16-bit) is transferred for every PDMA operation #10 3 Reserved #11 PDMA_DAn PDMA_DAn PDMA Channel n Destination Address Register 0x8 read-write n 0x0 0x0 DA PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote: The Destination address must be word alignment. 0 32 read-write PDMA_INTENn PDMA_INTENn PDMA Channel n Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 PCNTIEN Periodic Count Interrupt Enable Bit\nThis field indicates how many data transferred to generate interrupt periodically. 8 1 read-write 0 Periodic transfer count interrupt Disabled #0 1 Periodic transfer count interrupt Enabled #1 TABTIEN PDMA Read/Write Target Abort Interrupt Enable Bit 0 1 read-write 0 Target abort interrupt Disabled during PDMA transfer #0 1 Target abort interrupt Enabled during PDMA transfer #1 TDIEN PDMA Transfer Done Interrupt Enable Bit 1 1 read-write 0 Interrupt Disabled when PDMA transfer is done #0 1 Interrupt Enabled when PDMA transfer is done #1 TOUTIEN Time-out Interrupt Enable Bit 6 1 read-write 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 PDMA_INTSTSn PDMA_INTSTSn PDMA Channel n Interrupt Status Register 0x24 read-write n 0x0 0x0 PCNTIF Periodic Count Interrupt Status Flag Note: This bit is cleared by writing 1 to it. 8 1 read-write TABTIF PDMA Read/Write Target Abort Interrupt Status Flag Note1: This bit is cleared by writing 1 to it. Note2: This bit indicates bus master received error response or not, if bus master received error response, it means that PDMA transfer data from an invalid address or to an invalid adress .At this time target abort is happened..PDMA controller will stop transfer and respond this event to user then go to IDLE state. When target abort occurred, user must reset PDMA controller, and then transfer those data again. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 TDIF Transfer Done Interrupt Status Flag This bit indicates that PDMA has finished all transfer. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 Not finished yet #0 1 Done #1 TOUTIF Time-out Interrupt Status Flag This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TOC. Note: This bit is cleared by writing 1 to it. 6 1 read-write 0 No time-out flag #0 1 Time-out flag #1 PDMA_SAn PDMA_SAn PDMA Channel n Source Address Register 0x4 read-write n 0x0 0x0 SA PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. 0 32 read-write PDMA_TOCn PDMA_TOCn PDMA Channel n Time-out Counter Register 0x28 read-write n 0x0 0x0 TOC PDMA Time-out Period Counter 0 16 read-write TPSC PDMA Time-out Counter Clock Source Prescaler 16 3 read-write 0 PDMA time-out clock source is HCLK/28 #000 1 PDMA time-out clock source is HCLK/29 #001 2 PDMA time-out clock source is HCLK/210 #010 3 PDMA time-out clock source is HCLK/211 #011 4 PDMA time-out clock source is HCLK/212 #100 5 PDMA time-out clock source is HCLK/213 #101 6 PDMA time-out clock source is HCLK/214 #110 7 PDMA time-out clock source is HCLK/215 #111 PDMA_GCR PDMA Register Map PDMA 0x0 0x0 0x10 registers n PDMA_GCTL PDMA_GCTL PDMA Global Control Register 0x0 read-write n 0x0 0x0 CKEN1 PDMA Controller Channel 1 Clock Enable Bit 9 1 read-write 0 PDMA channel 1 clock Disabled #0 1 PDMA channel 1 clock Enabled #1 CKEN2 PDMA Controller Channel 2 Clock Enable Bit 10 1 read-write 0 PDMA channel 2 clock Disabled #0 1 PDMA channel 2 clock Enabled #1 CKEN3 PDMA Controller Channel 3 Clock Enable Bit 11 1 read-write 0 PDMA channel 3 clock Disabled #0 1 PDMA channel 3 clock Enabled #1 CKEN4 PDMA Controller Channel 4 Clock Enable Bit 12 1 read-write 0 PDMA channel 4 clock Disabled #0 1 PDMA channel 4 clock Enabled #1 CKENCRC CRC Controller Clock Enable Bit 24 1 read-write 0 CRC channel clock Disabled #0 1 CRC channel clock Enabled #1 PDMA_GINTSTS PDMA_GINTSTS PDMA Global Interrupt Status Register 0xC read-only n 0x0 0x0 IF1 PDMA Channel 1 Interrupt Status (Read Only)\nThis bit indicates the interrupt status of PDMA channel 1. 1 1 read-only IF2 PDMA Channel 2 Interrupt Status Flag of (Read Only)\nThis bit indicates the interrupt status of PDMA channel 2. 2 1 read-only IF3 PDMA Channel 3 Interrupt Status (Read Only)\nThis bit indicates the interrupt status of PDMA channel 3. 3 1 read-only IF4 PDMA Channel 4 Interrupt Status Flag (Read Only)\nThis bit indicates the interrupt status of PDMA channel 4. 4 1 read-only IFCRC CRC Controller Interrupt Status Flag (Read Only)\nThis bit indicates the interrupt status of CRC controller 16 1 read-only PDMA_REQSEL0 PDMA_REQSEL0 PDMA Request Source Select Register 0 0x4 -1 read-write n 0x0 0x0 REQSRC1 Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral by setting REQSRC1 8 5 read-write 0 Connect to SPI0_TX #00000 1 Connect to SPI1_TX #00001 2 Connect to UART0_TX #00010 3 Connect to UART1_TX #00011 4 Reserved #00100 5 Connect to SPI3_TX #00101 6 Reserved #00110 7 Reserved #00111 8 Connect to SPI2_TX #01000 9 Connect to TMR0 #01001 10 Connect to TMR1 #01010 11 Connect to TMR2 #01011 12 Connect to TMR3 #01100 16 Connect to SPI0_RX #10000 17 Connect to SPI1_RX #10001 18 Connect to UART0_RX #10010 19 Connect to UART1_RX #10011 20 Reserved #10100 21 Connect to SPI3_RX #10101 22 Connect to ADC #10110 23 Reserved #10111 24 Connect to SPI2_RX #11000 25 Reserved #11001 26 Reserved #11010 27 Reserved #11011 28 Reserved #11100 REQSRC2 Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC1 field. Please refer to the explanation of REQSRC1. 16 5 read-write REQSRC3 Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC1 field. Please refer to the explanation of REQSRC1. 24 5 read-write PDMA_REQSEL1 PDMA_REQSEL1 PDMA Request Source Select Register 1 0x8 -1 read-write n 0x0 0x0 REQSRC4 Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC1 field. Please refer to the explanation of REQSRC1. 0 5 read-write PWM0 PWM0 Register Map PWM0 0x0 0x0 0x8 registers n 0x10 0x18 registers n 0x120 0x4 registers n 0x200 0x3C registers n 0x250 0x8 registers n 0x30 0x4 registers n 0x300 0x8 registers n 0x30C 0x4 registers n 0x314 0x4 registers n 0x31C 0x18 registers n 0x38 0x4 registers n 0x40 0x4 registers n 0x50 0x18 registers n 0x70 0xC registers n 0x90 0x4 registers n 0x98 0x4 registers n 0xA0 0x4 registers n 0xB0 0x40 registers n 0xF8 0x8 registers n 0xFFC 0x4 registers n ADCTS0 PWM0_ADCTS0 PWM0 Trigger ADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 PWM0_CH0 Trigger EADC Enable Bit 7 1 read-write 0 PWM0_CH0 Trigger EADC Disabled #0 1 PWM0_CH0 Trigger EADC Enabled #1 TRGEN1 PWM0_CH1 Trigger EADC Enable Bit 15 1 read-write 0 PWM0_CH1 Trigger EADC Disabled #0 1 PWM0_CH1 Trigger EADC Enabled #1 TRGEN2 PWM0_CH2 Trigger EADC Enable Bit 23 1 read-write 0 PWM0_CH2 Trigger EADC Disabled #0 1 PWM0_CH2 Trigger EADC Enabled #1 TRGEN3 PWM0_CH3 Trigger EADC Enable Bit 31 1 read-write 0 PWM0_CH3 Trigger EADC Disabled #0 1 PWM0_CH3 Trigger EADC Enabled #1 TRGSEL0 PWM0_CH0 Trigger ADC Source Select\nOthers reserved 0 4 read-write 0 PWM0_CH0 zero point #0000 1 PWM0_CH0 period point #0001 2 PWM0_CH0 zero or period point #0010 3 PWM0_CH0 up-count CMPDAT point #0011 4 PWM0_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM0_CH1 up-count CMPDAT point #1000 9 PWM0_CH1 down-count CMPDAT point #1001 TRGSEL1 PWM0_CH1 Trigger ADC Source Select\nOthers reserved 8 4 read-write 0 PWM0_CH0 zero point #0000 1 PWM0_CH0 period point #0001 2 PWM0_CH0 zero or period point #0010 3 PWM0_CH0 up-count CMPDAT point #0011 4 PWM0_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM0_CH1 up-count CMPDAT point #1000 9 PWM0_CH1 down-count CMPDAT point #1001 TRGSEL2 PWM0_CH2 Trigger ADC Source Select\nOthers reserved 16 4 read-write 0 PWM0_CH2 zero point #0000 1 PWM0_CH2 period point #0001 2 PWM0_CH2 zero or period point #0010 3 PWM0_CH2 up-count CMPDAT point #0011 4 PWM0_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM0_CH3 up-count CMPDAT point #1000 9 PWM0_CH3 down-count CMPDAT point #1001 TRGSEL3 PWM0_CH3 Trigger ADC Source Select\nOthers reserved 24 4 read-write 0 PWM0_CH2 zero point #0000 1 PWM0_CH2 period point #0001 2 PWM0_CH2 zero or period point #0010 3 PWM0_CH2 up-count CMPDAT point #0011 4 PWM0_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM0_CH3 up-count CMPDAT point #1000 9 PWM0_CH3 down-count CMPDAT point #1001 ADCTS1 PWM0_ADCTS1 PWM0 Trigger ADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 PWM0_CH4 Trigger EADC Enable Bit 7 1 read-write 0 PWM0_CH4 Trigger EADC Disabled #0 1 PWM0_CH4 Trigger EADC Enabled #1 TRGEN5 PWM0_CH5 Trigger EADC Enable Bit 15 1 read-write 0 PWM0_CH5 Trigger EADC Disabled #0 1 PWM0_CH5 Trigger EADC Enabled #1 TRGSEL4 PWM0_CH4 Trigger ADC Source Select\nOthers reserved 0 4 read-write 0 PWM0_CH4 zero point #0000 1 PWM0_CH4 period point #0001 2 PWM0_CH4 zero or period point #0010 3 PWM0_CH4 up-count CMPDAT point #0011 4 PWM0_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM0_CH5 up-count CMPDAT point #1000 9 PWM0_CH5 down-count CMPDAT point #1001 TRGSEL5 PWM0_CH5 Trigger ADC Source Select\nOthers reserved 8 4 read-write 0 PWM0_CH4 zero point #0000 1 PWM0_CH4 period point #0001 2 PWM0_CH4 zero or period point #0010 3 PWM0_CH4 up-count CMPDAT point #0011 4 PWM0_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM0_CH5 up-count CMPDAT point #1000 9 PWM0_CH5 down-count CMPDAT point #1001 BNF PWM0_BNF PWM0 Brake Noise Filter Register 0xC0 read-write n 0x0 0x0 BK0SRC Brake 0 Pin Source Select\nFor PWM0 setting: 16 1 read-write 0 Brake 0 pin source come from PWM0_BRAKE0.\nBrake 0 pin source come from PWM1_BRAKE0 #0 1 Brake 0 pin source come from PWM1_BRAKE0.\nBrake 0 pin source come from PWM0_BRAKE0 #1 BK1SRC Brake 1 Pin Source Select\nFor PWM0 setting: 24 1 read-write 0 Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1 #0 1 Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1 #1 BRK0FCNT Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. 4 3 read-write BRK0FCS Brake 0 Edge Detector Filter Clock Selection 1 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK0FEN PWM0 Brake 0 Noise Filter Enable Bit 0 1 read-write 0 Noise filter of PWM0 Brake 0 Disabled #0 1 Noise filter of PWM0 Brake 0 Enabled #1 BRK0PINV Brake 0 Pin Inverse 7 1 read-write 0 The state of pin PWMx_BRAKE0 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector #1 BRK1FCNT Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 12 3 read-write BRK1FCS Brake 1 Edge Detector Filter Clock Selection 9 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK1FEN PWM0 Brake 1 Noise Filter Enable Bit 8 1 read-write 0 Noise filter of PWM0 Brake 1 Disabled #0 1 Noise filter of PWM0 Brake 1 Enabled #1 BRK1PINV Brake 1 Pin Inverse 15 1 read-write 0 The state of pin PWMx_BRAKE1 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector #1 BRKCTL0_1 PWM0_BRKCTL0_1 PWM0 Brake Edge Detect Control Register 0_1 0xC8 read-write n 0x0 0x0 BRKAEVEN PWM0 Brake Action Select for Even Channel (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register. 16 2 read-write 0 PWM0 even channelbrake function not affect channel output #00 1 PWM0 even channel output tri-state when brake happened #01 2 PWM0 even channel output low level whenbrake happened #10 3 PWM0 even channel output high level when brake happened #11 BRKAODD PWM0 Brake Action Select for Odd Channel (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register. 18 2 read-write 0 PWM0 odd channel brake function not affect channel output #00 1 PWM0 odd channel output tri-state when brake happened #01 2 PWM0 odd channel output low level whenbrake happened #10 3 PWM0 odd channel output high level when brake happened #11 BRKP0EEN Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register. 4 1 read-write 0 BKP0 pin as edge-detect brake source Disabled #0 1 BKP0 pin as edge-detect brake source Enabled #1 BRKP0LEN Enable BKP0 Pin As Level-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register. 12 1 read-write 0 PWMx_BRAKE0 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE0 pin as level-detect brake source Enabled #1 BRKP1EEN Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register. 5 1 read-write 0 BKP1 pin as edge-detect brake source Disabled #0 1 BKP1 pin as edge-detect brake source Enabled #1 BRKP1LEN Enable BKP1 Pin As Level-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register. 13 1 read-write 0 PWMx_BRAKE1 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE1 pin as level-detect brake source Enabled #1 SYSEEN Enable System Fail As Edge-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register. 7 1 read-write 0 System Fail condition as edge-detect brake source Disabled #0 1 System Fail condition as edge-detect brake source Enabled #1 SYSLEN Enable System Fail As Level-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register. 15 1 read-write 0 System Fail condition as level-detect brake source Disabled #0 1 System Fail condition as level-detect brake source Enabled #1 BRKCTL2_3 PWM0_BRKCTL2_3 PWM0 Brake Edge Detect Control Register 2_3 0xCC read-write n 0x0 0x0 BRKCTL4_5 PWM0_BRKCTL4_5 PWM0 Brake Edge Detect Control Register 4_5 0xD0 read-write n 0x0 0x0 CAPCTL PWM0_CAPCTL PWM0 Capture Control Register 0x204 read-write n 0x0 0x0 CAPENn Capture Function Enable Bits\nEach bit n controls the corresponding PWM0 channel n. 0 6 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated 0 1 Capture function Enabled. Capture latched the PWM0 counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) 1 CAPINVn Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM0 channel n. 8 6 read-write 0 Capture source inverter Disabled 0 1 Capture source inverter Enabled. Reverse the input signal from GPIO 1 FCRLDENn Falling Capture Reload EnableBits\nEach bit n controls the corresponding PWM0 channel n. 24 6 read-write 0 Falling capture reload counter Disabled 0 1 Falling capture reload counter Enabled 1 RCRLDENn Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM0 channel n. 16 6 read-write 0 Risingcapture reload counter Disabled 0 1 Risingcapture reload counter Enabled 1 CAPIEN PWM0_CAPIEN PWM0 Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIENn PWM0 Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM0 channel n. 8 6 read-write 0 Capture falling edge latch interrupt Disabled 0 1 Capture falling edge latch interrupt Enabled 1 CAPRIENn PWM0 Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM0 channel n. 0 6 read-write 0 Capture rising edge latch interrupt Disabled 0 1 Capture rising edge latch interrupt Enabled 1 CAPIF PWM0_CAPIF PWM0 Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CAPFIFn PWM0 Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM0 channel n. 8 6 read-write 0 No capture falling latch condition happened 0 1 Capture falling latch condition happened, this flag will be set to high 1 CAPRIFn PWM0 Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM0 channel n. 0 6 read-write 0 No capture rising latch condition happened 0 1 Capture rising latch condition happened, this flag will be set to high 1 CAPINEN PWM0_CAPINEN PWM0 Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINENn Capture Input Enable Bits\nEach bit n controls the corresponding PWM0 channel n. 0 6 read-write 0 PWM0 Channel capture input path Disabled. The input of PWM0 channel capture function is always regarded as 0 0 1 PWM0 Channel capture input path Enabled. The input of PWM0 channel capture function comes from correlative multifunction pin 1 CAPSTS PWM0_CAPSTS PWM0 Capture Status Register 0x208 read-only n 0x0 0x0 CFIFOVn Capture Falling Interrupt Flag Overrun Status(Read Only)\nThis flag indicatesif falling latch happenedwhen the corresponding CAPFIFis 1. Each bit n controls the corresponding PWM0 channel n.\nNote:This bit will be cleared automatically when user clear corresponding CAPFIF. 8 6 read-only CRIFOVn Capture Rising Interrupt Flag Overrun Status(Read Only)\nThis flag indicatesif rising latch happenedwhen the corresponding CAPRIFis 1. Each bit n controls the corresponding PWM0 channel n.\nNote:This bit will be cleared automatically when user clear corresponding CAPRIF. 0 6 read-only CLKPSC0_1 PWM0_CLKPSC0_1 PWM0 Clock Pre-Scale Register 0_1 0x14 read-write n 0x0 0x0 CLKPSC PWM0 Counter Clock Pre-scale \nThe clock of PWM0 counter is decided by clock prescaler. Each PWM0 pair share one PWM0 counter clock prescaler. The clock of PWM0 counter is divided by (CLKPSC+ 1). 0 12 read-write CLKPSC2_3 PWM0_CLKPSC2_3 PWM0 Clock Pre-Scale Register 2_3 0x18 read-write n 0x0 0x0 CLKPSC4_5 PWM0_CLKPSC4_5 PWM0 Clock Pre-Scale Register 4_5 0x1C read-write n 0x0 0x0 CLKSRC PWM0_CLKSRC PWM0 Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 PWM0_CH01 External Clock Source Select 0 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC2 PWM0_CH23 External Clock Source Select 8 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC4 PWM0_CH45 External Clock Source Select 16 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 CMPBUF0 PWM0_CMPBUF0 PWM0 CMPDAT0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF PWM0 Comparator Register Buffer(Read Only)\nUsed as CMP active register. 0 16 read-only CMPBUF1 PWM0_CMPBUF1 PWM0 CMPDAT1 Buffer 0x320 read-write n 0x0 0x0 CMPBUF2 PWM0_CMPBUF2 PWM0 CMPDAT2 Buffer 0x324 read-write n 0x0 0x0 CMPBUF3 PWM0_CMPBUF3 PWM0 CMPDAT3 Buffer 0x328 read-write n 0x0 0x0 CMPBUF4 PWM0_CMPBUF4 PWM0 CMPDAT4 Buffer 0x32C read-write n 0x0 0x0 CMPBUF5 PWM0_CMPBUF5 PWM0 CMPDAT5 Buffer 0x330 read-write n 0x0 0x0 CMPDAT0 PWM0_CMPDAT0 PWM0 Comparator Register 0 0x50 read-write n 0x0 0x0 CMPDAT PWM0 Comparator Register\nCMPDAT use to compare with CNTR to generate PWM0 waveform, interrupt and trigger ADC.\nIn independent mode, CMPDAT0~5 denote as 6 independent PWM0_CH0~5 compared point.\nIn complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM0_CH0 and PWM0_CH1, PWM0_CH2 and PWM0_CH3, PWM0_CH4 and PWM0_CH5. 0 16 read-write CMPDAT1 PWM0_CMPDAT1 PWM0 Comparator Register 1 0x54 read-write n 0x0 0x0 CMPDAT2 PWM0_CMPDAT2 PWM0 Comparator Register 2 0x58 read-write n 0x0 0x0 CMPDAT3 PWM0_CMPDAT3 PWM0 Comparator Register 3 0x5C read-write n 0x0 0x0 CMPDAT4 PWM0_CMPDAT4 PWM0 Comparator Register 4 0x60 read-write n 0x0 0x0 CMPDAT5 PWM0_CMPDAT5 PWM0 Comparator Register 5 0x64 read-write n 0x0 0x0 CNT0 PWM0_CNT0 PWM0 Counter Register 0 0x90 read-only n 0x0 0x0 CNT PWM0 Data Register(Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter. 0 16 read-only DIRF PWM0 Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 CNT2 PWM0_CNT2 PWM0 Counter Register 2 0x98 read-write n 0x0 0x0 CNT4 PWM0_CNT4 PWM0 Counter Register 4 0xA0 read-write n 0x0 0x0 CNTCLR PWM0_CNTCLR PWM0 Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLR0 Clear PWM0 Counter Control Bit 0\nIt is automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Clear 16-bit PWM0 counter to 0000H #1 CNTCLR2 Clear PWM0 Counter Control Bit 2\nIt is automatically cleared by hardware. 2 1 read-write 0 No effect #0 1 Clear 16-bit PWM0 counter to 0000H #1 CNTCLR4 Clear PWM0 Counter Control Bit 4\nIt is automatically cleared by hardware. 4 1 read-write 0 No effect #0 1 Clear 16-bit PWM0 counter to 0000H #1 CNTEN PWM0_CNTEN PWM0 Counter Enable Register 0x20 read-write n 0x0 0x0 CNTEN0 PWM0 Counter Enable Bit 0 0 1 read-write 0 PWM0 Counter0_1 and clock prescaler0 Stop Running #0 1 PWM0 Counter0_1 and clock prescaler0 Start Running #1 CNTEN2 PWM0 Counter Enable Bit 2 2 1 read-write 0 PWM0 Counter2_3 and clock prescaler2 Stop Running #0 1 PWM0 Counter2_3 and clock prescaler2 Start Running #1 CNTEN4 PWM0 Counter Enable Bit4 4 1 read-write 0 PWM0 Counter4_5 and clock prescaler4 Stop Running. .... #0 1 PWM0 Counter4_5 and clock prescaler4 Start Running #1 CTL0 PWM0_CTL0 PWM0 Control Register 0 0x0 read-write n 0x0 0x0 CTRLDn Center Re-load\nEach bit n controls the corresponding PWM0 channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 6 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM0 all counters will keep current value until exit ICE debug mode. \nNote:This bit is write protected. Refer toSYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM0 pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer toSYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects PWM0 output #0 1 ICE debug mode acknowledgement disabled #1 IMMLDENn Immediately Load Enable Bits\nEach bit n controls the corresponding PWM0 channel n.\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 16 6 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit 0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT 1 CTL1 PWM0_CTL1 PWM0 Control Register 1 0x4 read-write n 0x0 0x0 CNTTYPE0 PWM0 Counter Behavior Type 0\nEach bit n controls corresponding PWM0 channel n. 0 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE2 PWM0 Counter Behavior Type 2\nEach bit n controls corresponding PWM0 channel n. 4 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE4 PWM0 Counter Behavior Type 4\nEach bit n controls corresponding PWM0 channel n. 8 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 PWMMODEn PWM0 Mode\nEach bit n controls the corresponding PWM0 channel n.\nNote: When operating in group function, these bits must all set to the same mode. 24 3 read-write 0 PWM0 independent mode 0 1 PWM0 complementary mode 1 DTCTL0_1 PWM0_DTCTL0_1 PWM0 Dead-Time Control Register 0_1 0x70 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect)\nNote:This register is write protected. Refer toREGWRPROT register. 24 1 read-write 0 Dead-time clock source from PWM0_CLKn #0 1 Dead-time clock source from prescaler output #1 DTCNT Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote:This register is write protected. Refer toSYS_REGLCTL register. 0 12 read-write DTEN Enable Dead-time Insertion for PWM0 Pair (PWM0_CH0, PWM0_CH1)(PWM0_CH2, PWM0_CH3)(PWM0_CH4, PWM0_CH5)(Write Protect)\nDead-time insertion is only active when this PWM0 pair complementary mode is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote:This register is write protected. Refer toSYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 DTCTL2_3 PWM0_DTCTL2_3 PWM0 Dead-Time Control Register 2_3 0x74 read-write n 0x0 0x0 DTCTL4_5 PWM0_DTCTL4_5 PWM0 Dead-Time Control Register 4_5 0x78 read-write n 0x0 0x0 FAILBRK PWM0_FAILBRK PWM0 System Fail Brake Control Register 0xC4 read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger PWM0 Brake Function 0 Enable Bit 1 1 read-write 0 Brake Function triggered by BOD Disabled #0 1 Brake Function triggered by BOD Enabled #1 CORBRKEN Core Lockup Detection Trigger PWM0 Brake Function 0 Enable Bit 3 1 read-write 0 Brake Function triggered by Core lockup detection Disabled #0 1 Brake Function triggered by Core lockup detection Enabled #1 FCAPDAT0 PWM0_FCAPDAT0 PWM0 Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT PWM0 Falling Capture Data Register(Read Only)\nWhen falling capture condition happened, the PWM0 counter value will be saved in this register. 0 16 read-only FCAPDAT1 PWM0_FCAPDAT1 PWM0 Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 FCAPDAT2 PWM0_FCAPDAT2 PWM0 Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 FCAPDAT3 PWM0_FCAPDAT3 PWM0 Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 FCAPDAT4 PWM0_FCAPDAT4 PWM0 Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 FCAPDAT5 PWM0_FCAPDAT5 PWM0 Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 INTEN0 PWM0_INTEN0 PWM0 Interrupt Enable Register 0 0xE0 read-write n 0x0 0x0 CMPDIENn PWM0 Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM0 channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 24 6 read-write 0 Compare down count interrupt Disabled 0 1 Compare down count interrupt Enabled 1 CMPUIENn PWM0 Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM0 channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 16 6 read-write 0 Compare up count interrupt Disabled 0 1 Compare up count interrupt Enabled 1 PIEN0 PWM0 Period Point Interrupt Enable Bit 0\nNote: When operating in up-down counter type, period point means center point. 8 1 read-write 0 PWM0counter0_1 period point interrupt Disabled #0 1 PWM0counter0_1 period point interrupt Enabled #1 PIEN2 PWM0 Period Point Interrupt Enable Bit 2\nNote: When operating in up-down counter type, period point means center point. 10 1 read-write 0 PWM0counter2_3 period point interrupt Disabled #0 1 PWM0counter2_3 period point interrupt Enabled #1 PIEN4 PWM0 Period Point Interrupt Enable Bit 4\nNote: When operating in up-down counter type, period point means center point. 12 1 read-write 0 PWM0counter4_5 period point interrupt Disabled #0 1 PWM0counter4_5 period point interrupt Enabled #1 ZIEN0 PWM0 Zero Point Interrupt Enable Bit 0\nNote: Odd channels will read always 0 at complementary mode. 0 1 read-write 0 PWM0counter0_1 zero point interrupt Disabled #0 1 PWM0counter0_1 zero point interrupt Enabled #1 ZIEN2 PWM0 Zero Point Interrupt Enable Bit 2\nNote: Odd channels will read always 0 at complementary mode. 2 1 read-write 0 PWM0counter2_3 zero point interrupt Disabled #0 1 PWM0counter2_3 zero point interrupt Enabled #1 ZIEN4 PWM0 Zero Point Interrupt Enable Bit 4\nNote: Odd channels will read always 0 at complementary mode. 4 1 read-write 0 PWM0counter4_5 zero point interrupt Disabled #0 1 PWM0counter4_5 zero point interrupt Enabled #1 INTEN1 PWM0_INTEN1 PWM0 Interrupt Enable Register 1 0xE4 read-write n 0x0 0x0 BRKEIEN0_1 PWM0 Edge-detect Brake Interrupt Enable Bitfor Channel0/1(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register. 0 1 read-write 0 Edge-detect Brake interrupt for channel0/1 Disabled #0 1 Edge-detect Brake interrupt for channel0/1 Enabled #1 BRKEIEN2_3 PWM0 Edge-detect Brake Interrupt Enable Bitfor Channel2/3(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register. 1 1 read-write 0 Edge-detect Brake interrupt for channel2/3 Disabled #0 1 Edge-detect Brake interrupt for channel2/3 Enabled #1 BRKEIEN4_5 PWM0 Edge-detect Brake Interrupt Enable Bitfor Channel4/5(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register. 2 1 read-write 0 Edge-detect Brake interrupt for channel4/5 Disabled #0 1 Edge-detect Brake interrupt for channel4/5 Enabled #1 BRKLIEN0_1 PWM0 Level-detect Brake Interrupt Enable Bitfor Channel0/1(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register. 8 1 read-write 0 Level-detect Brake interrupt for channel0/1 Disabled #0 1 Level-detect Brake interrupt for channel0/1 Enabled #1 BRKLIEN2_3 PWM0 Level-detect Brake Interrupt Enable Bitfor Channel2/3(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register. 9 1 read-write 0 Level-detect Brake interrupt for channel2/3 Disabled #0 1 Level-detect Brake interrupt for channel2/3 Enabled #1 BRKLIEN4_5 PWM0 Level-detect Brake Interrupt Enable Bit for Channel4/5(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register. 10 1 read-write 0 Level-detect Brake interrupt for channel4/5 Disabled #0 1 Level-detect Brake interrupt for channel4/5 Enabled #1 INTSTS0 PWM0_INTSTS0 PWM0 Interrupt Flag Register 0 0xE8 read-write n 0x0 0x0 CMPDIFn PWM0 Compare Down Count Interrupt Flag\nEach bit n controls the corresponding PWM0 channel n.\nFlag is set by hardware when PWM0 counter down count and reaches PWM0_CMPDATn, software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 24 6 read-write CMPUIFn PWM0 Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM0 counter up count and reaches PWM0_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM0 channel n.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 16 6 read-write PIF0 PWM0 Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM0_CH0 counter reaches PWM0_PERIOD0, software can write 1 to clear this bit to zero. 8 1 read-write PIF2 PWM0 Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM0_CH2 counter reaches PWM0_PERIOD2, software can write 1 to clear this bit to zero. 10 1 read-write PIF4 PWM0 Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM0_CH4 counter reaches PWM0_PERIOD4, software can write 1 to clear this bit to zero. 12 1 read-write ZIF0 PWM0 Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM0_CH0 counter reaches zero, software can write 1 to clear this bit to zero. 0 1 read-write ZIF2 PWM0 Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM0_CH2 counter reaches zero, software can write 1 to clear this bit to zero. 2 1 read-write ZIF4 PWM0 Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM0_CH4 counter reaches zero, software can write 1 to clear this bit to zero. 4 1 read-write INTSTS1 PWM0_INTSTS1 PWM0 Interrupt Flag Register 1 0xEC read-write n 0x0 0x0 BRKEIF0 PWM0 Channel0 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register. 0 1 read-write 0 PWM0 channel0 edge-detect brake event do not happened #0 1 When PWM0 channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF1 PWM0 Channel1 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register. 1 1 read-write 0 PWM0 channel1 edge-detect brake event do not happened #0 1 When PWM0 channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF2 PWM0 Channel2 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register. 2 1 read-write 0 PWM0 channel2 edge-detect brake event do not happened #0 1 When PWM0 channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF3 PWM0 Channel3 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register. 3 1 read-write 0 PWM0 channel3 edge-detect brake event do not happened #0 1 When PWM0 channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF4 PWM0 Channel4 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register. 4 1 read-write 0 PWM0 channel4 edge-detect brake event do not happened #0 1 When PWM0 channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF5 PWM0 Channel5 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register. 5 1 read-write 0 PWM0 channel5 edge-detect brake event do not happened #0 1 When PWM0 channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKESTS0 PWM0 Channel0 Edge-detect Brake Status (Read Only) 16 1 read-only 0 PWM0 channel0 edge-detect brake state is released #0 1 When PWM0 channel0 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel0 at brake state, writing 1 to clear #1 BRKESTS1 PWM0 Channel1 Edge-detect Brake Status (Read Only) 17 1 read-only 0 PWM0 channel1 edge-detect brake state is released #0 1 When PWM0 channel1 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel1 at brake state, writing 1 to clear #1 BRKESTS2 PWM0 Channel2 Edge-detect Brake Status (Read Only) 18 1 read-only 0 PWM0 channel2 edge-detect brake state is released #0 1 When PWM0 channel2 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel2 at brake state, writing 1 to clear #1 BRKESTS3 PWM0 Channel3 Edge-detect Brake Status (Read Only) 19 1 read-only 0 PWM0 channel3 edge-detect brake state is released #0 1 When PWM0 channel3 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel3 at brake state, writing 1 to clear #1 BRKESTS4 PWM0 Channel4 Edge-detect Brake Status (Read Only) 20 1 read-only 0 PWM0 channel4 edge-detect brake state is released #0 1 When PWM0 channel4 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel4 at brake state, writing 1 to clear #1 BRKESTS5 PWM0 Channel5 Edge-detect Brake Status (Read Only) 21 1 read-only 0 PWM0 channel5 edge-detect brake state is released #0 1 When PWM0 channel5 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel5 at brake state, writing 1 to clear #1 BRKLIF0 PWM0 Channel0 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register. 8 1 read-write 0 PWM0 channel0 level-detect brake event do not happened #0 1 When PWM0 channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF1 PWM0 Channel1 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register. 9 1 read-write 0 PWM0 channel1 level-detect brake event do not happened #0 1 When PWM0 channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF2 PWM0 Channel2 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register. 10 1 read-write 0 PWM0 channel2 level-detect brake event do not happened #0 1 When PWM0 channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF3 PWM0 Channel3 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register. 11 1 read-write 0 PWM0 channel3 level-detect brake event do not happened #0 1 When PWM0 channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF4 PWM0 Channel4 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register. 12 1 read-write 0 PWM0 channel4 level-detect brake event do not happened #0 1 When PWM0 channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF5 PWM0 Channel5 Level-detect Brake Interrupt Flag(Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register. 13 1 read-write 0 PWM0 channel5 level-detect brake event do not happened #0 1 When PWM0 channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLSTS0 PWM0 Channel0 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform will start output from next full PWM0 period. 24 1 read-only 0 PWM0 channel0 level-detect brake state is released #0 1 When PWM0 channel0 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel0 at brake state #1 BRKLSTS1 PWM0 Channel1 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform will start output from next full PWM0 period. 25 1 read-only 0 PWM0 channel1 level-detect brake state is released #0 1 When PWM0 channel1 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel1 at brake state #1 BRKLSTS2 PWM0 Channel2 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform will start output from next full PWM0 period. 26 1 read-only 0 PWM0 channel2 level-detect brake state is released #0 1 When PWM0 channel2 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel2 at brake state #1 BRKLSTS3 PWM0 Channel3 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform will start output from next full PWM0 period. 27 1 read-only 0 PWM0 channel3 level-detect brake state is released #0 1 When PWM0 channel3 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel3 at brake state #1 BRKLSTS4 PWM0 Channel4 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform will start output from next full PWM0 period. 28 1 read-only 0 PWM0 channel4 level-detect brake state is released #0 1 When PWM0 channel4 level-detect brake detects a falling edgeof any enabled brake source this flag will be set to indicate the PWM0 channel4 at brake state #1 BRKLSTS5 PWM0 Channel5 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform will start output from next full PWM0 period. 29 1 read-only 0 PWM0 channel5 level-detect brake state is released #0 1 When PWM0 channel5 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel5 at brake state #1 MSK PWM0_MSK PWM0 Mask Data Register 0xBC read-write n 0x0 0x0 MSKDATn PWM0 Mask Data Bits\nThis data bit control the state of PWM0_CHn output pin, if corresponding mask function is enabled. 0 6 read-write 0 Output logic low to PWM0_CHn 0 1 Output logic high to PWM0_CHn 1 MSKEN PWM0_MSKEN PWM0 Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKENn PWM0 Mask Enable Bits\nEach bit n controls the corresponding PWM0 channel n.\nThe PWM0 output signal will be masked when this bit is enabled. The corresponding PWM0 channel n will output MSKDATn (PWM0_MSK[5:0]) data. 0 6 read-write 0 PWM0 output signal is non-masked 0 1 PWM0 output signal is masked and output MSKDATn data 1 PBUF0 PWM0_PBUF0 PWM0 PERIOD0 Buffer 0x304 read-only n 0x0 0x0 PBUF PWM0 Period Register Buffer(Read Only)\nUsed as PERIOD active register. 0 16 read-only PBUF2 PWM0_PBUF2 PWM0 PERIOD2 Buffer 0x30C read-write n 0x0 0x0 PBUF4 PWM0_PBUF4 PWM0 PERIOD4 Buffer 0x314 read-write n 0x0 0x0 PERIOD0 PWM0_PERIOD0 PWM0 Period Register 0 0x30 read-write n 0x0 0x0 PERIOD PWM0 Period Register\nUp-Count mode: In this mode, PWM0 counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, PWM0 counter counts from PERIOD to 0, and restarts from PERIOD. 0 16 read-write PERIOD2 PWM0_PERIOD2 PWM0 Period Register 2 0x38 read-write n 0x0 0x0 PERIOD4 PWM0_PERIOD4 PWM0 Period Register 4 0x40 read-write n 0x0 0x0 POEN PWM0_POEN PWM0 Output Enable Register 0xD8 read-write n 0x0 0x0 POENn PWM0 Pin Output Enable Bits\nEach bit n controls the corresponding PWM0 channel n. 0 6 read-write 0 PWM0 pin at tri-state 0 1 PWM0 pin in output mode 1 POLCTL PWM0_POLCTL PWM0 Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINVn PWM0 PIN Polar Inverse Control\nThe register controls polarity state of PWM0 output. Each bit n controls the corresponding PWM0 channel n. 0 6 read-write 0 PWM0 output polar inverse Disabled 0 1 PWM0 output polar inverse Enabled 1 RCAPDAT0 PWM0_RCAPDAT0 PWM0 Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT PWM0 Rising Capture Data Register(Read Only)\nWhen rising capture condition happened, the PWM0 counter value will be saved in this register. 0 16 read-only RCAPDAT1 PWM0_RCAPDAT1 PWM0 Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 RCAPDAT2 PWM0_RCAPDAT2 PWM0 Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 RCAPDAT3 PWM0_RCAPDAT3 PWM0 Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 RCAPDAT4 PWM0_RCAPDAT4 PWM0 Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 RCAPDAT5 PWM0_RCAPDAT5 PWM0 Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 SELFTEST PWM0_SELFTEST PWM0 Self-test Mode Enable 0x300 read-write n 0x0 0x0 STATUS PWM0_STATUS PWM0 Status Register 0x120 read-write n 0x0 0x0 ADCTRGn ADC Start of Conversion Status\nEach bit n controls the corresponding PWM0 channel n. 16 6 read-write 0 Indicates no ADC start of conversion trigger event has occurred 0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit 1 CNTMAX0 Time-base Counter 0 Equal to 0xFFFF Latched Status 0 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 CNTMAX2 Time-base Counter 2 Equal to 0xFFFF Latched Status 2 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 CNTMAX4 Time-base Counter 4 Equal to 0xFFFF Latched Status 4 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 SWBRK PWM0_SWBRK PWM0 Software Brake Control Register 0xDC write-only n 0x0 0x0 BRKETRGn PWM0 Edge Brake Software Trigger (Write Only)(Write Protect)\nEach bit n controls the corresponding PWM0 pair n.\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM0_INTSTS1 register. \nNote:This register is write protected. Refer toSYS_REGLCTL register. 0 3 write-only BRKLTRGn PWM0 Level Brake Software Trigger (Write Only)(Write Protect)\nEach bit n controls the corresponding PWM0 pair n.\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM0_INTSTS1 register. \nNote:This register is write protected. Refer toSYS_REGLCTL register. 8 3 write-only VERSION PWM0_VERSION PWM0 RTL Design Version Number 0xFFC -1 read-only n 0x0 0x0 WGCTL0 PWM0_WGCTL0 PWM0Waveform Generation Control Register 0 0xB0 read-write n 0x0 0x0 PRDPCTLn PWM0 Period (Center) Point Control\nEach bit n controls the corresponding PWM0 channel n.\nPWM0 can control output level when PWM0 counter count to (PERIODn+1).\nNote: This bit is center point control when PWM0 counter operating in up-down counter type. 16 12 read-write 0 Do nothing 00 1 PWM0 period (center) point output Low 01 10 PWM0 period (center) point output High 10 11 PWM0 period (center) point output Toggle 11 ZPCTLn PWM0 Zero Point Control\nEach bit n controls the corresponding PWM0 channel n.\nPWM0 can control output level when PWM0 counter count to zero. 0 12 read-write 0 Do nothing 00 1 PWM0 zero point output Low 01 10 PWM0 zero point output High 10 11 PWM0 zero point output Toggle 11 WGCTL1 PWM0_WGCTL1 PWM0Waveform Generation Control Register 1 0xB4 read-write n 0x0 0x0 CMPDCTLn PWM0 Compare Down Point Control\nEach bit n controls the corresponding PWM0 channel n.\nPWM0 can control output level when PWM0 counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 16 12 read-write 0 Do nothing 00 1 PWM0 compare down point output Low 01 10 PWM0 compare down point output High 10 11 PWM0 compare down point output Toggle 11 CMPUCTLn PWM0 Compare Up Point Control\nEach bit n controls the corresponding PWM0 channel n.\nPWM0 can control output level when PWM0 counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 0 12 read-write 0 Do nothing 00 1 PWM0 compare up point output Low 01 10 PWM0 compare up point output High 10 11 PWM0 compare up point output Toggle 11 RTC RTC Register Map RTC 0x0 0x0 0x54 registers n 0x100 0x10 registers n CAL RTC_CAL RTC Calendar Loading Register 0x10 -1 read-write n 0x0 0x0 DAY 1-Day Calendar Digit (0~9) 0 4 read-write MON 1-Month Calendar Digit (0~9) 8 4 read-write TENDAY 10-Day Calendar Digit (0~3) 4 2 read-write TENMON 10-Month Calendar Digit (0~1) 12 1 read-write TENYEAR 10-Year Calendar Digit (0~9) 20 4 read-write YEAR 1-Year Calendar Digit (0~9) 16 4 read-write CALM RTC_CALM RTC Calendar Alarm Register 0x20 read-write n 0x0 0x0 DAY 1-Day Calendar Digit of Alarm Setting (0~9) 0 4 read-write MON 1-Month Calendar Digit of Alarm Setting (0~9) 8 4 read-write TENDAY 10-Day Calendar Digit of Alarm Setting (0~3) 4 2 read-write TENMON 10-Month Calendar Digit of Alarm Setting (0~1) 12 1 read-write TENYEAR 10-Year Calendar Digit of Alarm Setting (0~9) 20 4 read-write YEAR 1-Year Calendar Digit of Alarm Setting (0~9) 16 4 read-write CAMSK RTC_CAMSK RTC Calendar Alarm Mask Register 0x38 read-write n 0x0 0x0 MDAY Mask 1-Day Calendar Digit of Alarm Setting (0~9) 0 1 read-write MMON Mask 1-Month Calendar Digit of Alarm Setting (0~9) 2 1 read-write MTENDAY Mask 10-Day Calendar Digit of Alarm Setting (0~3) 1 1 read-write MTENMON Mask 10-Month Calendar Digit of Alarm Setting (0~1) 3 1 read-write MTENYEAR Mask 10-Year Calendar Digit of Alarm Setting (0~9) 5 1 read-write MYEAR Mask 1-Year Calendar Digit of Alarm Setting (0~9) 4 1 read-write CLKFMT RTC_CLKFMT RTC Time Scale Selection Register 0x14 -1 read-write n 0x0 0x0 _24HEN 24-hour /12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale 0 1 read-write 0 12-hour time scale with AM and PM indication selected #0 1 24-hour time scale selected #1 FREQADJ RTC_FREQADJ RTC Frequency Compensation Register 0x8 -1 read-write n 0x0 0x0 FREQADJ Frequence Compensation Register LXT period: the clock period (Hz) of LXT. 0 22 read-write INIT RTC_INIT RTC Initiation Register 0x0 read-write n 0x0 0x0 INIT RTC Initiation\nWhen RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.\nThe INIT is a write-only field and read value will be always 0. 1 31 read-write INIT_ACTIVE RTC Active Status (Read Only) 0 1 read-only 0 RTC is at reset state #0 1 RTC is at normal active state #1 INTEN RTC_INTEN RTC Interrupt Enable Register 0x28 read-write n 0x0 0x0 ALMIEN Alarm Interrupt Enable Bit 0 1 read-write 0 RTC Alarm interrupt Disabled #0 1 RTC Alarm interrupt Enabled #1 SNPDIEN Snoop Detection Interrupt Enable Bit 2 1 read-write 0 Snoop detectedinterrupt Disabled #0 1 Snoop detected interrupt Enabled #1 TICKIEN Time Tick Interrupt Enable Bit 1 1 read-write 0 RTC Time Tick interrupt Disabled #0 1 RTC Time Tick interrupt Enabled #1 INTSTS RTC_INTSTS RTC Interrupt Indicator Register 0x2C read-write n 0x0 0x0 ALMIF RTC Alarm Interrupt Flag\nWhen RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1. Chip will be waken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode.\nNote: Write 1 to clear this bit. 0 1 read-write 0 Alarm condition is not matched #0 1 Alarm condition is matched #1 SNPDIF Snoop Detect Interrupt Flag\nWhen tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1. Chip will be waken up from Power-down mode if spare register snooper detect interrupt is enabled.\nNote:Write 1 to clear this bit. 2 1 read-write 0 No snoop event is detected #0 1 Snoop event is detected #1 TICKIF RTC Time Tick Interrupt Flag\nWhen RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1. Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.\nNote:Write 1 to clear to clear this bit. 1 1 read-write 0 Tick condition does not occur #0 1 Tick condition occur #1 LEAPYEAR RTC_LEAPYEAR RTC Leap Year Indicator Register 0x24 read-only n 0x0 0x0 LEAPYEAR Leap Year Indication Register (Read Only) 0 1 read-only 0 This year is not a leap year #0 1 This year is leap year #1 LXTCTL RTC_LXTCTL RTC 32.768 kHz Oscillator Control Register 0x100 read-write n 0x0 0x0 LXT_TYPE LXT TYPE Selection 0 1 read-write 0 Crystal type ( Crystal connect to X32KI with X32KO) #0 1 Oscator illator type ( LXT source from X32KI PIN , X32KO as GPIO #1 LXTICTL RTC_LXTICTL X32KI Pin Control Register 0x108 read-write n 0x0 0x0 CTLSEL IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled, X32KI (PF.7) pin can be used as GPIO function. User can program CTLSEL bit to decide X32KI (PF.7) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL control register. 3 1 read-write 0 X32KI (PF.7) pin I/O function is controlled by GPIO module. It becomes floating state when system power is turned off #0 1 X32KI (PF.7) pin I/O function is controlled by VBAT power domain, X32KI (PF.7) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1. I/O pin keeps the previous state after system power is turned off #1 DOUT IO Output Data 2 1 read-write 0 X32KI (PF.7) output low #0 1 X32KI (PF.7) output high #1 OPMODE IO Operation Mode 0 2 read-write 0 X32KI (PF.7) is input only mode, without pull-up resistor #00 1 X32KI (PF.7) is output push pull mode #01 2 X32KI (PF.7) is open drain mode #10 3 X32KI (PF.7) is input only mode with internal pull up #11 LXTOCTL RTC_LXTOCTL X32KO Pin Control Register 0x104 read-write n 0x0 0x0 CTLSEL IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled, X32KO (PF.6) pin can be used as GPIO function. User can program CTLSEL bit to decide X32KO (PF.6) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL control register. 3 1 read-write 0 X32KO (PF.6) pin I/O function is controlled by GPIO module. It becomes floating when system power is turned off #0 1 X32KO (PF.6) pin I/O function is controlled by VBAT power domain, X32KO (PF.6) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1. I/O pin keeps the previous state after system power is turned off #1 DOUT IO Output Data 2 1 read-write 0 X32KO (PF.6) output low #0 1 X32KO (PF.6) output high #1 OPMODE GPF0 Operation Mode 0 2 read-write 0 X32KO (PF.6) is input only mode, without pull-up resistor #00 1 X32KO (PF.6) is output push pull mode #01 2 X32KO (PF.6) is open drain mode #10 3 X32KO (PF.6) is input only mode with internal pull up #11 RWEN RTC_RWEN RTC Access Enable Register 0x4 read-write n 0x0 0x0 RTCBUSY RTC Write Busy Flag 0: RTC write access enable 1: RTC write access disable , RTC under Busy Status. Note: BUSY By Exceed RTC IP Prcessing Write Counter Capacity ( 6 counts Per 1120 PCLK cycles) . 24 1 read-write RWEN RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this register will enable RTC access and keep 1024 RTC clock.\nWriting other vaule will clear RWENF. 0 16 write-only RWENF RTC Register Access Enable Flag (Read Only) 16 1 read-only 0 RTC register read/write Disabled #0 1 RTC register read/write Enabled #1 SPR0 RTC_SPR0 RTC Spare Register 0 0x40 read-write n 0x0 0x0 SPARE Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a snooper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled. 0 32 read-write SPR1 RTC_SPR1 RTC Spare Register 1 0x44 read-write n 0x0 0x0 SPR2 RTC_SPR2 RTC Spare Register 2 0x48 read-write n 0x0 0x0 SPR3 RTC_SPR3 RTC Spare Register 3 0x4C read-write n 0x0 0x0 SPR4 RTC_SPR4 RTC Spare Register 4 0x50 read-write n 0x0 0x0 SPRCTL RTC_SPRCTL RTC Spare Functional Control Register 0x3C read-write n 0x0 0x0 SNPDEN Snoop Detection Enable Bit 0 1 read-write 0 TAMPER pin detection Disabled #0 1 TAMPER pin detection Enabled #1 SNPTYPE0 Snoop Detection Level\nThis bit controls TAMPER detect event is rising edge or falling edge. 1 1 read-write 0 Rising edge detection #0 1 Falling edge detection #1 SPRCSTS SPR Clear Flag \nThis bit indicates if the RTC_SPR0 ~RTC_SPR4 content is cleared when specify snoop event is detected.\nWrites 1 to clear this bit. 5 1 read-write 0 Spare register content is not cleared #0 1 Spare register content is cleared #1 SPRRWEN Spare Register Enable Bit Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR4 cannot be accessed Did not change the content of the spare register, but read data all 0 .. 2 1 read-write 0 Spare register Disabled #0 1 Spare register Enabled #1 TALM RTC_TALM RTC Time Alarm Register 0x1C read-write n 0x0 0x0 HR 1-Hour Time Digit of Alarm Setting (0~9) 16 4 read-write MIN 1-Min Time Digit of Alarm Setting (0~9) 8 4 read-write SEC 1-Sec Time Digit of Alarm Setting (0~9) 0 4 read-write TENHR 10-hour Time Digit of Alarm Setting (0~2)\nWhen RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication. (If RTC_TIME[21] is 1, it indicates PM time message.)the high bit of TENHR (RTC_TIME[21]) means AM/PM indication. 20 2 read-write TENMIN 10-Min Time Digit of Alarm Setting (0~5) 12 3 read-write TENSEC 10-Sec Time Digit of Alarm Setting (0~5) 4 3 read-write TAMPCTL RTC_TAMPCTL TAMPER Pin Control Register 0x10C read-write n 0x0 0x0 CTLSEL IO Pin State Backup Selection\nWhen tamper function is disabled, TAMPER pin can be used as GPIO function. User can program CTLSEL bit to decide (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL control register. 3 1 read-write 0 TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by GPIO module. It becomes floating state when system power is turned off #0 1 TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by VBAT power domain. LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8 function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1. I/O pin state keeps previous state after system power is turned off #1 DOUT IO Output Data 2 1 read-write 0 TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) output low #0 1 TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) output high #1 OPMODE IO Operation Mode 0 2 read-write 0 TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is input only mode, without pull-up resistor #00 1 TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is output push pull mode #01 2 TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is open drain mode #10 3 TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is input only mode with internal pull up #11 TAMSK RTC_TAMSK RTC Time Alarm Mask Register 0x34 read-write n 0x0 0x0 MHR Mask 1-Hour Time Digit of Alarm Setting (0~9) 4 1 read-write MMIN Mask 1-Min Time Digit of Alarm Setting (0~9) 2 1 read-write MSEC Mask 1-Sec Time Digit of Alarm Setting (0~9) 0 1 read-write MTENHR Mask 10-Hour Time Digit of Alarm Setting (0~2) 5 1 read-write MTENMIN Mask 10-Min Time Digit of Alarm Setting (0~5) 3 1 read-write MTENSEC Mask 10-Sec Time Digit of Alarm Setting (0~5) 1 1 read-write TICK RTC_TICK RTC Time Tick Register 0x30 read-write n 0x0 0x0 TICK Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. \nNote:This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active. 0 3 read-write 0 Time tick is 1 second #000 1 Time tick is 1/2 second #001 2 Time tick is 1/4 second #010 3 Time tick is 1/8 second #011 4 Time tick is 1/16 second #100 5 Time tick is 1/32 second #101 6 Time tick is 1/64 second #110 7 Time tick is 1/128 second #111 TIME RTC_TIME RTC Time Loading Register 0xC read-write n 0x0 0x0 HR 1-Hour Time Digit (0~9) 16 4 read-write MIN 1-Min Time Digit (0~9) 8 4 read-write SEC 1-Sec Time Digit (0~9) 0 4 read-write TENHR 10-hour Time Digit (0~2)\nWhen RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication. (If RTC_TIME[21] is 1, it indicates PM time message.) the high bit of TENHR (RTC_TIME[21]) means AM/PM indication. 20 2 read-write TENMIN 10-Min Time Digit (0~5) 12 3 read-write TENSEC 10-Sec Time Digit (0~5) 4 3 read-write WEEKDAY RTC_WEEKDAY RTC Day of the Week Register 0x18 -1 read-write n 0x0 0x0 WEEKDAY Day of the Week Register 0 3 read-write 0 Sunday #000 1 Monday #001 2 Tuesday #010 3 Wednesday #011 4 Thursday #100 5 Friday #101 6 Saturday #110 7 Reserved #111 SC0 SC Register Map SC 0x0 0x0 0x38 registers n 0x40 0x4 registers n SCn_ACTCTL SCn_ACTCTL SCn Activation Control Register. 0x40 read-write n 0x0 0x0 T1EXT Configurable Cycles T1EXT in Hardware Activation \nThis field provide the configurable cycles to extend the Activation time T1\nThe cycle scaling factor is 2048.\nNote: setting 0 to this field conforms to the protocol ISO/IEC 7816-3 0 5 read-write SCn_ALTCTL SCn_ALTCTL SCn Alternate Control Register. 0x8 read-write n 0x0 0x0 ACTEN Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1, RXOFF(SC_CTL[2]) will be clear to 0.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. 3 1 read-write 0 No effect #0 1 Activation sequence generator Enabled #1 ACTSTS0 Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT(SC_TMRCTL0[23:0]). 13 1 read-only 0 Timer0 is not active #0 1 Timer0 is active #1 ACTSTS1 Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT(SC_TMRCTL1[7:0]). 14 1 read-only 0 Timer1 is not active #0 1 Timer1 is active #1 ACTSTS2 Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT(SC_TMRCTL2[7:0]). 15 1 read-only 0 Timer2 is not active #0 1 Timer2 is active #1 CNTEN0 Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. 5 1 read-write 0 Stops counting #0 1 Start counting #1 CNTEN1 Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. 6 1 read-write 0 Stops counting #0 1 Start counting #1 CNTEN2 Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. 7 1 read-write 0 Stops counting #0 1 Start counting #1 DACTEN Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST, and RXRST at the same time.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 2 1 read-write 0 No effect #0 1 Deactivation sequence generator Enabled #1 INITSEL Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: Refer to SC Activation Sequence in Figure 6.154SC Activation Sequence.\nWarm-reset: Refer to Warm-Reset Sequence in Figure 6.155SC Warm Reset Sequence\nDeactivation: Refer to Deactivation Sequence in Figure 6.156SC Deactivation Sequence\nNote: When set Activation and Warm reset in mode 11, it may have deviation at most 128 cycles. 8 2 read-write OUTSEL Smartcard Data Pin Output Mode Selection\nUse this bit to select smartcard data pin output mode. 16 1 read-write 0 Quasi mode #0 1 Open-drain mode #1 RXBGTEN Receiver Block Guard Time Function Enable Bit 12 1 read-write 0 Receiver block guard time function Disabled #0 1 Receiver block guard time function Enabled #1 RXRST Rx Software Reset\nWhen RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 1 1 read-write 0 No effect #0 1 Reset the Rx internal state machine and pointers #1 TXRST TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 0 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 WARSTEN Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1, RXOFF(SC_CTL[2]) will be clear to 0.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST, and RXRST at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. 4 1 read-write 0 No effect #0 1 Warm reset sequence generator Enabled #1 SCn_CTL SCn_CTL SCn Control Register. 0x4 read-write n 0x0 0x0 AUTOCEN Auto Convention Enable Bit 3 1 read-write 0 Auto-convention Disabled #0 1 Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11 #1 BGT Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1. 8 5 read-write CDDBSEL Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved. 24 2 read-write 0 De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks #00 CONSEL Convention Selection\nNote: If AUTOCEN(SC_CTL[3]) is enabled, this field is ignored. 4 2 read-write 0 Direct convention #00 1 Reserved #01 2 Reserved #10 3 Inverse convention #11 NSB Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopt NSB to program the stop bit length. 15 1 read-write 0 The stop bit length is 2 ETU #0 1 The stop bit length is 1 ETU #1 RXOFF RX Transition Disable Bit\nNote1: If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored.\nNote2: After hardware activation and hardware warm reset are done, RXOFF is set to 0 automatically. 1 1 read-write 0 The receiver Enabled #0 1 The receiver Disabled #1 RXRTY RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RX_ERETRY_EN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value. 16 3 read-write RXRTYEN RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: Software must fill in the RXRTY value before enabling this bit. 19 1 read-write 0 RX error retry function Disabled #0 1 RX error retry function Enabled #1 RXTRGLV Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if SC_INTEN [RDAIEN] is enabled, an interrupt will be generated). 6 2 read-write 0 INTR_RDA Trigger Level with 01 Bytes #00 1 INTR_RDA Trigger Level with 02 Bytes #01 2 INTR_RDA Trigger Level with 03 Bytes #10 3 Reserved #11 SCEN SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state\nNote1: SCEN must be set to 1 before filling in other registers, or smart card will not work properly.\nNote2: If SCEN is activated, all function can work correctly. If SCEN is not activated, when CPU write data to SMC, only Flip-flop which works in PCLK domain will turn on for two PCLK cycle, Flip-flop working in SCLK domain will not be turn on. 0 1 read-write SYNC SYNC Flag Indicator(Read Only)\nDue to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.SYNC delay is 30 1 read-only 0 synchronizing is completion, user can write new data to RXRTY and TXRTY #0 1 Last value is synchronizing #1 TMRSEL Timer Selection \nOther configurations are reserved 13 2 read-write 0 All internal timer function Disabled #00 3 Internal 24 bit timer and two 8 bit timers Enabled. Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0] #11 TXOFF TX Transition Disable Bit 2 1 read-write 0 The transceiver Enabled #0 1 The transceiver Disabled #1 TXRTY TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TXRTYEN first and then fill in new retry value. 20 3 read-write TXRTYEN TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred. 23 1 read-write 0 TX error retry function Disabled #0 1 TX error retry function Enabled #1 SCn_DAT SCn_DAT SCn Receive/Transmit Holding Buffer Register. 0x0 read-write n 0x0 0x0 DAT Receive/Transmit Holding Buffer \nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data. 0 8 read-write SCn_EGT SCn_EGT SCn Extra Guard Time Register. 0xC read-write n 0x0 0x0 EGT Extra Guard Time\nThis field indicates the extra guard timer value.\nNote: The counter is ETU base . 0 8 read-write SCn_ETUCTL SCn_ETUCTL SCn Element Time Unit Control Register. 0x14 -1 read-write n 0x0 0x0 ETURDIV ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004. 0 12 read-write SCn_INTEN SCn_INTEN SCn Interrupt Enable Control Register. 0x18 read-write n 0x0 0x0 ACERRIEN Auto Convention Error Interrupt Enable Bit\nThis field is used to enable auto-convention error interrupt. 10 1 read-write 0 Auto-convention error interrupt Disabled #0 1 Auto-convention error interrupt Enabled #1 BGTIEN Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt. 6 1 read-write 0 Block guard time Disabled #0 1 Block guard time Enabled #1 CDIEN Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt. The card detect status is CINSERT(SC_STATUS[12]) 7 1 read-write 0 Card detect interrupt Disabled #0 1 Card detect interrupt Enabled #1 INITIEN Initial End Interrupt Enable Bit 8 1 read-write 0 Initial end interrupt Disabled #0 1 Initial end interrupt Enabled #1 RDAIEN Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt. 0 1 read-write 0 Receive data reach trigger level interrupt Disabled #0 1 Receive data reach trigger level interrupt Enabled #1 RXTOEN Receiver Buffer Time-out Interrupt Enable Bit\nThis field is used to enable receiver buffer time-out interrupt. 9 1 read-write 0 Receiver buffer time-out interrupt Disabled #0 1 Receiver buffer time-out interrupt Enabled #1 TBEIEN Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt. 1 1 read-write 0 Transmit buffer empty interrupt Disabled #0 1 Transmit buffer empty interrupt Enabled #1 TERRIEN Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR (SC_STATUS[30]). 2 1 read-write 0 Transfer error interrupt Disabled #0 1 Transfer error interrupt Enabled #1 TMR0IEN Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt. 3 1 read-write 0 Timer0 interrupt Disabled #0 1 Timer0 interrupt Enabled #1 TMR1IEN Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt. 4 1 read-write 0 Timer1 interrupt Disabled #0 1 Timer1 interrupt Enabled #1 TMR2IEN Timer2 Interrupt Enable Bit\nThis field is used to enable TMR2 interrupt. 5 1 read-write 0 Timer2 interrupt Disabled #0 1 Timer2 interrupt Enabled #1 SCn_INTSTS SCn_INTSTS SCn Interrupt Status Register. 0x1C -1 read-write n 0x0 0x0 ACERRIF Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 10 1 read-only BGTIF Block Guard Time Interrupt Status Flag (Read Only) This field is used for block guard time interrupt status flag. Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled. Note2: This bit is read only, but it can be cleared by writing 1 to it. 6 1 read-only CDIF Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).\nNote: This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])]. So if software wants to clear these bits, software must write 1 to these field. 7 1 read-only INITIF Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 8 1 read-only RBTOIF Receiver Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer, 9 1 read-only RDAIF Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]). If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically. 0 1 read-only TBEIF Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to DAT(SC_DAT[7:0]) buffer and then this bit will be cleared automatically. 1 1 read-only TERRIF Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30]).\nNote: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5]), PEF(SC_STATUS[4]), RXOV(SC_STATUS[0]), TXOV(SC_STATUS[8]), RXOVERR(SC_STATUS[22]) or TXOVERR(SC_STATUS[30]). So, if software wants to clear this bit, software must write 1 to each field. 2 1 read-only TMR0IF Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 3 1 read-only TMR1IF Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 4 1 read-only TMR2IF Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 5 1 read-only SCn_PINCTL SCn_PINCTL SCn Pin Control State Register. 0x24 read-write n 0x0 0x0 ADACEN Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set). If this process completes, hardware will generate an interrupt INITIF to CPU. 7 1 read-write 0 Auto deactivation Disabled when hardware detected the card removal #0 1 Auto deactivation Enabled when hardware detected the card removal #1 CDLV Card Detect Level\ndetected. \nNote: Software must select card detect level before Smart Card engine is enabled. 10 1 read-write 0 When hardware detects the card detect pin (SC_CD) from high to low, it indicates a #0 1 When hardware detects the card detect pin from low to high, it indicates a card is #1 CDPINSTS Card Detect Status of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD 4 1 read-only 0 The SC_CD pin state at low #0 1 The SC_CD pin state at high #1 CINSERT Card Detect Insert Status of SC_CD Pin (Read Only) This bit is set whenever card has been inserted. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: Thecard detect engine will start after SCEN (SC_CTL[0]) set. 3 1 read-only 0 No effect #0 1 Card insert #1 CLKKEEP SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. Thus,do not fill in this field when operating in these modes. 6 1 read-write 0 SC clock generation Disabled #0 1 SC clock always keeps free running #1 CREMOVE Card Detect Removal Status of SC_CD Pin (Read Only) This bit is set whenever card has been removal. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: Card detect engine will start after SCEN (SC_CTL[0])set. 2 1 read-only 0 No effect #0 1 Card removed #1 DATSTS SC Data Input Pin Status (Read Only)\nThis bit is the pin status of SC_DAT 16 1 read-only 0 The SC_DAT pin is low #0 1 The SC_DAT pin is high #1 PWREN SC_PWREN Pin Signal\nSoftware can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level.\nRead this field to get SC_PWR pin status.\nNote: When operating at hardware activation, warm reset or deactivation mode, this bit will be changed automatically. Thus,do not fill in this field when operating in these modes. 0 1 read-write 0 SC_PWR pin status is low #0 1 SC_PWR pin status is high #1 PWRINV SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]). PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for SC_POW_Pin as high or low voltage selection.\nNote:Software must select PWRINV (SC_PINCTL[11]) before Smart Card is enabled by SCEN (SC_CTL[0]). 11 1 read-write SCDOUT SC Data Output Pin \nThis bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus,do not fill in this field when SC is in these modes. 9 1 read-write 0 Drive SCDATOUT pin to low #0 1 Drive SCDATOUT pin to high #1 SCRST SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus,do not fill in this field when operating in these modes. 1 1 read-write 0 Drive SC_RST pin to low.\nSC_RST pin status is low #0 1 Drive SC_RST pin to high.\nSC_RST pin status is high #1 SYNC SYNC Flag Indicator(Read Only)\nDue to synchronization, software should check this bit when writing a new value to SC_PINCTL register. 30 1 read-only 0 Synchronizing is completion, user can write new data to SC_PINCTL register #0 1 Last value is synchronizing #1 SCn_RXTOUT SCn_RXTOUT SCn Receive buffer Time-out Register. 0x10 read-write n 0x0 0x0 RFTM SC Receiver FIFO Time-out \nNote1:The counter unit is ETU based and the interval of time-out is RFTM + 0.5.\nNote2: Filling in all 0 to this field indicates to disable this function. 0 9 read-write SCn_STATUS SCn_STATUS SCn Transfer Status Register. 0x20 -1 read-write n 0x0 0x0 BEF Receiver Break Error Status Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). . Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. 6 1 read-only FEF Receiver Frame Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. 5 1 read-only PEF Receiver Parity Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. 4 1 read-only RXACT Receiver in Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished. 23 1 read-only RXEMPTY Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data. 1 1 read-only RXFULL Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware. 2 1 read-only RXOV RX Overflow Error Status Flag (Read Only)\nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 0 1 read-only RXOVERR Receiver over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])). 22 1 read-only RXPOINT Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one. When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one. 16 2 read-only RXRERR Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])). 21 1 read-only TXACT Transmit in Active Status Flag (Read Only) 31 1 read-only 0 This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed #0 1 This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted #1 TXEMPTY Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT(SC_DAT[7:0]) (TX buffer not empty). 9 1 read-only TXFULL Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware. 10 1 read-only TXOV TX Overflow Error Interrupt Status Flag (Read Only) If TX buffer is full, an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to 1 by hardware. Note: This bit is read only, but it can be cleared by writing 1 to it. 8 1 read-only TXOVERR Transmitter over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 30 1 read-only TXPOINT Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_DAT, TXPOINT increases one. When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one. 24 2 read-only TXRERR Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU. 29 1 read-only SCn_TMRCTL0 SCn_TMRCTL0 SCn Internal Timer 0 Control Register. 0x28 read-write n 0x0 0x0 CNT Timer 0 Counter Value (ETU Based)\nThis field indicates the internal timer operation values. 0 24 read-write OPMODE Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer toTable6.153TimerOperation Modefor programming Timer0. 24 4 read-write SYNC SYNC Flag Indicator(Read Only)\nDue to synchronization, software should check this bit when writing a new value to the SC_TMRCTL0 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SC_TMRCTL0 register #0 1 Last value is synchronizing #1 SCn_TMRCTL1 SCn_TMRCTL1 SCn Internal Timer 1 Control Register. 0x2C read-write n 0x0 0x0 CNT Timer 1 Counter Value (ETU Based)\nThis field indicates the internal timer operation values. 0 8 read-write OPMODE Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer toTable6.153TimerOperation Modefor programming Timer1. 24 4 read-write SYNC SYNC Flag Indicator(Read Only)\nDue to synchronization, software should check this bit when writing a new value to the SC_TMRCTL1 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SC_TMRCTL1 register #0 1 Last value is synchronizing #1 SCn_TMRCTL2 SCn_TMRCTL2 SCn Internal Timer 2 Control Register. 0x30 read-write n 0x0 0x0 CNT Timer 2 Counter Value (ETU Based)\nThis field indicates the internal timer operation values. 0 8 read-write OPMODE Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to Table6.153TimerOperation Modefor programming Timer2. 24 4 read-write SYNC SYNC Flag Indicator(Read Only)\nDue to synchronization, software should check this bit when writing a new value to SC_TMRCTL2 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SC_TMRCTL2 register #0 1 Last value is synchronizing #1 SCn_UARTCTL SCn_UARTCTL SCn UART Mode Control Register. 0x34 read-write n 0x0 0x0 OPE Odd Parity Enable Bit\nNote: This bit has effect only when PBOFF bit is '0'. 7 1 read-write 0 Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode #0 1 Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode #1 PBOFF Parity Bit Disable Control\nNote: In smart card mode, this field must be '0' (default setting is with parity bit) 6 1 read-write 0 Parity bit is generated or checked between the last data word bit and stop bit of the serial data #0 1 Parity bit is not generated (transmitting data) or checked (receiving data) during transfer #1 UARTEN UART Mode Enable Bit\nNote3: When UART is enabled, hardware will generate a resetto reset FIFO and internal state machine. 0 1 read-write 0 Smart Card mode #0 1 UART mode #1 WLS Word Length Selection\nNote: In smart card mode, this WLS must be '00' 4 2 read-write 0 Word length is 8 bits #00 1 Word length is 7 bits #01 2 Word length is 6 bits #10 3 Word length is 5 bits #11 SC1 SC Register Map SC 0x0 0x0 0x38 registers n 0x40 0x4 registers n SCn_ACTCTL SCn_ACTCTL SCn Activation Control Register. 0x40 read-write n 0x0 0x0 T1EXT Configurable Cycles T1EXT in Hardware Activation \nThis field provide the configurable cycles to extend the Activation time T1\nThe cycle scaling factor is 2048.\nNote: setting 0 to this field conforms to the protocol ISO/IEC 7816-3 0 5 read-write SCn_ALTCTL SCn_ALTCTL SCn Alternate Control Register. 0x8 read-write n 0x0 0x0 ACTEN Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1, RXOFF(SC_CTL[2]) will be clear to 0.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. 3 1 read-write 0 No effect #0 1 Activation sequence generator Enabled #1 ACTSTS0 Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT(SC_TMRCTL0[23:0]). 13 1 read-only 0 Timer0 is not active #0 1 Timer0 is active #1 ACTSTS1 Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT(SC_TMRCTL1[7:0]). 14 1 read-only 0 Timer1 is not active #0 1 Timer1 is active #1 ACTSTS2 Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT(SC_TMRCTL2[7:0]). 15 1 read-only 0 Timer2 is not active #0 1 Timer2 is active #1 CNTEN0 Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. 5 1 read-write 0 Stops counting #0 1 Start counting #1 CNTEN1 Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. 6 1 read-write 0 Stops counting #0 1 Start counting #1 CNTEN2 Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. 7 1 read-write 0 Stops counting #0 1 Start counting #1 DACTEN Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST, and RXRST at the same time.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 2 1 read-write 0 No effect #0 1 Deactivation sequence generator Enabled #1 INITSEL Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: Refer to SC Activation Sequence in Figure 6.154SC Activation Sequence.\nWarm-reset: Refer to Warm-Reset Sequence in Figure 6.155SC Warm Reset Sequence\nDeactivation: Refer to Deactivation Sequence in Figure 6.156SC Deactivation Sequence\nNote: When set Activation and Warm reset in mode 11, it may have deviation at most 128 cycles. 8 2 read-write OUTSEL Smartcard Data Pin Output Mode Selection\nUse this bit to select smartcard data pin output mode. 16 1 read-write 0 Quasi mode #0 1 Open-drain mode #1 RXBGTEN Receiver Block Guard Time Function Enable Bit 12 1 read-write 0 Receiver block guard time function Disabled #0 1 Receiver block guard time function Enabled #1 RXRST Rx Software Reset\nWhen RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 1 1 read-write 0 No effect #0 1 Reset the Rx internal state machine and pointers #1 TXRST TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 0 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 WARSTEN Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1, RXOFF(SC_CTL[2]) will be clear to 0.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST, and RXRST at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. 4 1 read-write 0 No effect #0 1 Warm reset sequence generator Enabled #1 SCn_CTL SCn_CTL SCn Control Register. 0x4 read-write n 0x0 0x0 AUTOCEN Auto Convention Enable Bit 3 1 read-write 0 Auto-convention Disabled #0 1 Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11 #1 BGT Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1. 8 5 read-write CDDBSEL Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved. 24 2 read-write 0 De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks #00 CONSEL Convention Selection\nNote: If AUTOCEN(SC_CTL[3]) is enabled, this field is ignored. 4 2 read-write 0 Direct convention #00 1 Reserved #01 2 Reserved #10 3 Inverse convention #11 NSB Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopt NSB to program the stop bit length. 15 1 read-write 0 The stop bit length is 2 ETU #0 1 The stop bit length is 1 ETU #1 RXOFF RX Transition Disable Bit\nNote1: If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored.\nNote2: After hardware activation and hardware warm reset are done, RXOFF is set to 0 automatically. 1 1 read-write 0 The receiver Enabled #0 1 The receiver Disabled #1 RXRTY RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RX_ERETRY_EN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value. 16 3 read-write RXRTYEN RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: Software must fill in the RXRTY value before enabling this bit. 19 1 read-write 0 RX error retry function Disabled #0 1 RX error retry function Enabled #1 RXTRGLV Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if SC_INTEN [RDAIEN] is enabled, an interrupt will be generated). 6 2 read-write 0 INTR_RDA Trigger Level with 01 Bytes #00 1 INTR_RDA Trigger Level with 02 Bytes #01 2 INTR_RDA Trigger Level with 03 Bytes #10 3 Reserved #11 SCEN SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state\nNote1: SCEN must be set to 1 before filling in other registers, or smart card will not work properly.\nNote2: If SCEN is activated, all function can work correctly. If SCEN is not activated, when CPU write data to SMC, only Flip-flop which works in PCLK domain will turn on for two PCLK cycle, Flip-flop working in SCLK domain will not be turn on. 0 1 read-write SYNC SYNC Flag Indicator(Read Only)\nDue to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.SYNC delay is 30 1 read-only 0 synchronizing is completion, user can write new data to RXRTY and TXRTY #0 1 Last value is synchronizing #1 TMRSEL Timer Selection \nOther configurations are reserved 13 2 read-write 0 All internal timer function Disabled #00 3 Internal 24 bit timer and two 8 bit timers Enabled. Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0] #11 TXOFF TX Transition Disable Bit 2 1 read-write 0 The transceiver Enabled #0 1 The transceiver Disabled #1 TXRTY TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TXRTYEN first and then fill in new retry value. 20 3 read-write TXRTYEN TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred. 23 1 read-write 0 TX error retry function Disabled #0 1 TX error retry function Enabled #1 SCn_DAT SCn_DAT SCn Receive/Transmit Holding Buffer Register. 0x0 read-write n 0x0 0x0 DAT Receive/Transmit Holding Buffer \nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data. 0 8 read-write SCn_EGT SCn_EGT SCn Extra Guard Time Register. 0xC read-write n 0x0 0x0 EGT Extra Guard Time\nThis field indicates the extra guard timer value.\nNote: The counter is ETU base . 0 8 read-write SCn_ETUCTL SCn_ETUCTL SCn Element Time Unit Control Register. 0x14 -1 read-write n 0x0 0x0 ETURDIV ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004. 0 12 read-write SCn_INTEN SCn_INTEN SCn Interrupt Enable Control Register. 0x18 read-write n 0x0 0x0 ACERRIEN Auto Convention Error Interrupt Enable Bit\nThis field is used to enable auto-convention error interrupt. 10 1 read-write 0 Auto-convention error interrupt Disabled #0 1 Auto-convention error interrupt Enabled #1 BGTIEN Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt. 6 1 read-write 0 Block guard time Disabled #0 1 Block guard time Enabled #1 CDIEN Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt. The card detect status is CINSERT(SC_STATUS[12]) 7 1 read-write 0 Card detect interrupt Disabled #0 1 Card detect interrupt Enabled #1 INITIEN Initial End Interrupt Enable Bit 8 1 read-write 0 Initial end interrupt Disabled #0 1 Initial end interrupt Enabled #1 RDAIEN Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt. 0 1 read-write 0 Receive data reach trigger level interrupt Disabled #0 1 Receive data reach trigger level interrupt Enabled #1 RXTOEN Receiver Buffer Time-out Interrupt Enable Bit\nThis field is used to enable receiver buffer time-out interrupt. 9 1 read-write 0 Receiver buffer time-out interrupt Disabled #0 1 Receiver buffer time-out interrupt Enabled #1 TBEIEN Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt. 1 1 read-write 0 Transmit buffer empty interrupt Disabled #0 1 Transmit buffer empty interrupt Enabled #1 TERRIEN Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR (SC_STATUS[30]). 2 1 read-write 0 Transfer error interrupt Disabled #0 1 Transfer error interrupt Enabled #1 TMR0IEN Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt. 3 1 read-write 0 Timer0 interrupt Disabled #0 1 Timer0 interrupt Enabled #1 TMR1IEN Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt. 4 1 read-write 0 Timer1 interrupt Disabled #0 1 Timer1 interrupt Enabled #1 TMR2IEN Timer2 Interrupt Enable Bit\nThis field is used to enable TMR2 interrupt. 5 1 read-write 0 Timer2 interrupt Disabled #0 1 Timer2 interrupt Enabled #1 SCn_INTSTS SCn_INTSTS SCn Interrupt Status Register. 0x1C -1 read-write n 0x0 0x0 ACERRIF Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 10 1 read-only BGTIF Block Guard Time Interrupt Status Flag (Read Only) This field is used for block guard time interrupt status flag. Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled. Note2: This bit is read only, but it can be cleared by writing 1 to it. 6 1 read-only CDIF Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).\nNote: This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])]. So if software wants to clear these bits, software must write 1 to these field. 7 1 read-only INITIF Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 8 1 read-only RBTOIF Receiver Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer, 9 1 read-only RDAIF Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]). If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically. 0 1 read-only TBEIF Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to DAT(SC_DAT[7:0]) buffer and then this bit will be cleared automatically. 1 1 read-only TERRIF Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30]).\nNote: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5]), PEF(SC_STATUS[4]), RXOV(SC_STATUS[0]), TXOV(SC_STATUS[8]), RXOVERR(SC_STATUS[22]) or TXOVERR(SC_STATUS[30]). So, if software wants to clear this bit, software must write 1 to each field. 2 1 read-only TMR0IF Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 3 1 read-only TMR1IF Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 4 1 read-only TMR2IF Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 5 1 read-only SCn_PINCTL SCn_PINCTL SCn Pin Control State Register. 0x24 read-write n 0x0 0x0 ADACEN Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set). If this process completes, hardware will generate an interrupt INITIF to CPU. 7 1 read-write 0 Auto deactivation Disabled when hardware detected the card removal #0 1 Auto deactivation Enabled when hardware detected the card removal #1 CDLV Card Detect Level\ndetected. \nNote: Software must select card detect level before Smart Card engine is enabled. 10 1 read-write 0 When hardware detects the card detect pin (SC_CD) from high to low, it indicates a #0 1 When hardware detects the card detect pin from low to high, it indicates a card is #1 CDPINSTS Card Detect Status of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD 4 1 read-only 0 The SC_CD pin state at low #0 1 The SC_CD pin state at high #1 CINSERT Card Detect Insert Status of SC_CD Pin (Read Only) This bit is set whenever card has been inserted. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: Thecard detect engine will start after SCEN (SC_CTL[0]) set. 3 1 read-only 0 No effect #0 1 Card insert #1 CLKKEEP SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. Thus,do not fill in this field when operating in these modes. 6 1 read-write 0 SC clock generation Disabled #0 1 SC clock always keeps free running #1 CREMOVE Card Detect Removal Status of SC_CD Pin (Read Only) This bit is set whenever card has been removal. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: Card detect engine will start after SCEN (SC_CTL[0])set. 2 1 read-only 0 No effect #0 1 Card removed #1 DATSTS SC Data Input Pin Status (Read Only)\nThis bit is the pin status of SC_DAT 16 1 read-only 0 The SC_DAT pin is low #0 1 The SC_DAT pin is high #1 PWREN SC_PWREN Pin Signal\nSoftware can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level.\nRead this field to get SC_PWR pin status.\nNote: When operating at hardware activation, warm reset or deactivation mode, this bit will be changed automatically. Thus,do not fill in this field when operating in these modes. 0 1 read-write 0 SC_PWR pin status is low #0 1 SC_PWR pin status is high #1 PWRINV SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]). PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for SC_POW_Pin as high or low voltage selection.\nNote:Software must select PWRINV (SC_PINCTL[11]) before Smart Card is enabled by SCEN (SC_CTL[0]). 11 1 read-write SCDOUT SC Data Output Pin \nThis bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus,do not fill in this field when SC is in these modes. 9 1 read-write 0 Drive SCDATOUT pin to low #0 1 Drive SCDATOUT pin to high #1 SCRST SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus,do not fill in this field when operating in these modes. 1 1 read-write 0 Drive SC_RST pin to low.\nSC_RST pin status is low #0 1 Drive SC_RST pin to high.\nSC_RST pin status is high #1 SYNC SYNC Flag Indicator(Read Only)\nDue to synchronization, software should check this bit when writing a new value to SC_PINCTL register. 30 1 read-only 0 Synchronizing is completion, user can write new data to SC_PINCTL register #0 1 Last value is synchronizing #1 SCn_RXTOUT SCn_RXTOUT SCn Receive buffer Time-out Register. 0x10 read-write n 0x0 0x0 RFTM SC Receiver FIFO Time-out \nNote1:The counter unit is ETU based and the interval of time-out is RFTM + 0.5.\nNote2: Filling in all 0 to this field indicates to disable this function. 0 9 read-write SCn_STATUS SCn_STATUS SCn Transfer Status Register. 0x20 -1 read-write n 0x0 0x0 BEF Receiver Break Error Status Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). . Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. 6 1 read-only FEF Receiver Frame Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. 5 1 read-only PEF Receiver Parity Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. 4 1 read-only RXACT Receiver in Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished. 23 1 read-only RXEMPTY Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data. 1 1 read-only RXFULL Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware. 2 1 read-only RXOV RX Overflow Error Status Flag (Read Only)\nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 0 1 read-only RXOVERR Receiver over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])). 22 1 read-only RXPOINT Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one. When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one. 16 2 read-only RXRERR Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])). 21 1 read-only TXACT Transmit in Active Status Flag (Read Only) 31 1 read-only 0 This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed #0 1 This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted #1 TXEMPTY Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT(SC_DAT[7:0]) (TX buffer not empty). 9 1 read-only TXFULL Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware. 10 1 read-only TXOV TX Overflow Error Interrupt Status Flag (Read Only) If TX buffer is full, an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to 1 by hardware. Note: This bit is read only, but it can be cleared by writing 1 to it. 8 1 read-only TXOVERR Transmitter over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 30 1 read-only TXPOINT Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_DAT, TXPOINT increases one. When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one. 24 2 read-only TXRERR Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU. 29 1 read-only SCn_TMRCTL0 SCn_TMRCTL0 SCn Internal Timer 0 Control Register. 0x28 read-write n 0x0 0x0 CNT Timer 0 Counter Value (ETU Based)\nThis field indicates the internal timer operation values. 0 24 read-write OPMODE Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer toTable6.153TimerOperation Modefor programming Timer0. 24 4 read-write SYNC SYNC Flag Indicator(Read Only)\nDue to synchronization, software should check this bit when writing a new value to the SC_TMRCTL0 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SC_TMRCTL0 register #0 1 Last value is synchronizing #1 SCn_TMRCTL1 SCn_TMRCTL1 SCn Internal Timer 1 Control Register. 0x2C read-write n 0x0 0x0 CNT Timer 1 Counter Value (ETU Based)\nThis field indicates the internal timer operation values. 0 8 read-write OPMODE Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer toTable6.153TimerOperation Modefor programming Timer1. 24 4 read-write SYNC SYNC Flag Indicator(Read Only)\nDue to synchronization, software should check this bit when writing a new value to the SC_TMRCTL1 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SC_TMRCTL1 register #0 1 Last value is synchronizing #1 SCn_TMRCTL2 SCn_TMRCTL2 SCn Internal Timer 2 Control Register. 0x30 read-write n 0x0 0x0 CNT Timer 2 Counter Value (ETU Based)\nThis field indicates the internal timer operation values. 0 8 read-write OPMODE Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to Table6.153TimerOperation Modefor programming Timer2. 24 4 read-write SYNC SYNC Flag Indicator(Read Only)\nDue to synchronization, software should check this bit when writing a new value to SC_TMRCTL2 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SC_TMRCTL2 register #0 1 Last value is synchronizing #1 SCn_UARTCTL SCn_UARTCTL SCn UART Mode Control Register. 0x34 read-write n 0x0 0x0 OPE Odd Parity Enable Bit\nNote: This bit has effect only when PBOFF bit is '0'. 7 1 read-write 0 Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode #0 1 Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode #1 PBOFF Parity Bit Disable Control\nNote: In smart card mode, this field must be '0' (default setting is with parity bit) 6 1 read-write 0 Parity bit is generated or checked between the last data word bit and stop bit of the serial data #0 1 Parity bit is not generated (transmitting data) or checked (receiving data) during transfer #1 UARTEN UART Mode Enable Bit\nNote3: When UART is enabled, hardware will generate a resetto reset FIFO and internal state machine. 0 1 read-write 0 Smart Card mode #0 1 UART mode #1 WLS Word Length Selection\nNote: In smart card mode, this WLS must be '00' 4 2 read-write 0 Word length is 8 bits #00 1 Word length is 7 bits #01 2 Word length is 6 bits #10 3 Word length is 5 bits #11 SCS SCS Register Map SCS 0x0 0x10 0xC registers n 0x100 0x4 registers n 0x180 0x4 registers n 0x200 0x4 registers n 0x280 0x4 registers n 0x400 0x20 registers n 0xD00 0x8 registers n 0xD10 0x4 registers n 0xD1C 0x8 registers n CPUID CPUID CPUID Base Register 0xD00 -1 read-only n 0x0 0x0 IMPLEMENTER Implementer Code 24 8 read-only PART Architecture of the Processor \nReads as 0xC for ARMv6-M parts 16 4 read-only PARTNO Part Number of the Processor \nReads as 0xC20. 4 12 read-only REVISION Revision Number \nReads as 0x0 0 4 read-only ICSR ICSR Interrupt Control State Register 0xD04 read-write n 0x0 0x0 ISRPENDING Interrupt Pending Flag,Excluding NMI and Faults (Read Only) 22 1 read-only 0 Interrupt not pending #0 1 Interrupt pending #1 ISRPREEMPT Interrupt Preempt Bit(Read Only)\nIf set, a pending exception will be serviced on exit from the debug halt state 23 1 read-only NMIPENDSET NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception, normally the processor entersthe NMI exception handler as soon as it detects a write of 1 to this bit. Entering thehandler then clears this bit to 0. This means a read of this bit by the NMI exceptionhandler returns 1 only if the NMI signal is reasserted while the processor is executingthat handler. 31 1 read-write 0 No effect.\nNMI exception not pending #0 1 Changes NMI exception state to pending.\nNMI exception pending #1 PENDSTCLR SysTick Exception Clear-pending Bit Write Operation: Note: This bit is write-only. When you want to clear PENDST bit, you must write 0 toPENDSTSET and write 1 to PENDSTCLR at the same time. 25 1 read-write 0 No effect #0 1 Removes the pending state from the SysTick exception #1 PENDSTSET SysTick Exception Set-pending Bit\nWrite Operation: 26 1 read-write 0 No effect.\nSysTick exception is not pending #0 1 Changes SysTick exception state to pending.\nSysTick exception is pending #1 PENDSVCLR PendSV Clear-pending Bit Write Operation: This bit is write-only. To clear the PENDSV bit, you must write 0 to PENDSVSET andwrite 1 to PENDSVCLR at the same time. 27 1 read-write 0 No effect #0 1 Removes the pending state from the PendSV exception #1 PENDSVSET PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending 28 1 read-write 0 No effect.\nPendSV exception is not pending #0 1 Changes PendSV exception state to pending.\nPendSV exception is pending #1 VECTACTIVE Contains the Active Exception Number 0 9 read-write 0 Thread mode 0 VECTPENDING Exception Number of the Highest Priority Pending Enabled Exception 12 9 read-write 0 No pending exceptions 0 NVIC_ICER NVIC_ICER IRQ0~IRQ31 Clear-Enable Control Register 0x180 read-write n 0x0 0x0 CLRENA Interrupt Disable Bits\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nNote: Read value indicates the current enable status. 0 32 read-write 0 No effect.\nAssociated interrupt status is Disabled 0 1 Write 1 to disable associated interrupt.\nAssociated interrupt status is Enabled 1 NVIC_ICPR NVIC_ICPR IRQ0~IRQ31Clear-Pending Control Register 0x280 read-write n 0x0 0x0 CLRPEND Clear Interrupt Pending\nWrite Operation:\nNote: Read value indicates the current pending status. 0 32 read-write 0 No effect.\nAssociated interrupt in not in pending status 0 1 Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status 1 NVIC_IPR0 NVIC_IPR0 IRQ0~IRQ3 Priority Control Register 0x400 read-write n 0x0 0x0 PRI_0 Priority of IRQ0 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_1 Priority of IRQ1 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_2 Priority of IRQ2 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_3 Priority of IRQ3 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR1 NVIC_IPR1 IRQ4~IRQ7 Priority Control Register 0x404 read-write n 0x0 0x0 PRI_4 Priority of IRQ4 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_5 Priority of IRQ5 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_6 Priority of IRQ6 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_7 Priority of IRQ7 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR2 NVIC_IPR2 IRQ8~IRQ11 Priority Control Register 0x408 read-write n 0x0 0x0 PRI_10 Priority of IRQ10 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_11 Priority of IRQ11 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write PRI_8 Priority of IRQ8 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_9 Priority of IRQ9 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write NVIC_IPR3 NVIC_IPR3 IRQ12~IRQ15 Priority Control Register 0x40C read-write n 0x0 0x0 PRI_12 Priority of IRQ12 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_13 Priority of IRQ13 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_14 Priority of IRQ14 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_15 Priorityof IRQ15 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR4 NVIC_IPR4 IRQ16~IRQ19 Priority Control Register 0x410 read-write n 0x0 0x0 PRI_16 Priority of IRQ16 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_17 Priority of IRQ17 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_18 Priority of IRQ18 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_19 Priority of IRQ19 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR5 NVIC_IPR5 IRQ20~IRQ23 Priority Control Register 0x414 read-write n 0x0 0x0 PRI_20 Priority of IRQ20 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_21 Priority of IRQ21 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_22 Priority of IRQ22 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_23 Priority of IRQ23 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR6 NVIC_IPR6 IRQ24~IRQ27 Priority Control Register 0x418 read-write n 0x0 0x0 PRI_24 Priority of IRQ24 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_25 Priority of IRQ25 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_26 Priority of IRQ26 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_27 Priority of IRQ27 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR7 NVIC_IPR7 IRQ28~IRQ31 Priority Control Register 0x41C read-write n 0x0 0x0 PRI_28 Priority of IRQ28 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_29 Priority of IRQ29 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_30 Priority of IRQ30 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_31 Priority of IRQ31 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_ISER NVIC_ISER IRQ0~IRQ31 Set-Enable Control Register 0x100 read-write n 0x0 0x0 SETENA Interrupt Enable Bits\nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nNote: Read value indicates the current enable status. 0 32 read-write 0 No effect.\nAssociated interrupt status is Disabled 0 1 Write 1 to enable associated interrupt.\nAssociated interrupt status is Enabled 1 NVIC_ISPR NVIC_ISPR IRQ0~IRQ31 Set-Pending Control Register 0x200 read-write n 0x0 0x0 SETPEND Set Interrupt Pending\nWrite Operation:\nNote: Read value indicates the current pending status. 0 32 read-write 0 No effect.\nAssociated interrupt in not in pending status 0 1 Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status 1 SCR SCR System Control Register 0xD10 read-write n 0x0 0x0 SEVONPEND Send Event on Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processorfrom WFE. If the processor is not waiting for an event, the event is registered and affectsthe next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event. 4 1 read-write 0 Only enabled interrupts or events can wake-up the processor, disabled interrupts areexcluded #0 1 Enabled events and all interrupts, including disabled interrupts, can wake-up theprocessor #1 SLEEPDEEP Processor Deep Sleep and Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode: 2 1 read-write 0 Sleep mode #0 1 Deep Sleep mode #1 SLEEPONEXIT Sleep-on-exit Enable Control\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode. 1 1 read-write 0 Do not sleep when returning to Thread mode #0 1 Enter Sleep or Deep Sleep when returning from ISR to Thread mode.Setting this bit to 1 enables an interrupt driven application to avoid returning to an emptymain application #1 SHPR2 SHPR2 System Handler Priority Register 2 0xD1C read-write n 0x0 0x0 PRI_11 Priority of System Handler 11 - SVCall 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write SHPR3 SHPR3 System Handler Priority Register 3 0xD20 read-write n 0x0 0x0 PRI_14 Priority of System Handler 14 - PendSV 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_15 Priority of System Handler 15 - SysTick 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write SYST_CTL SYST_CTL SysTick Control and Status 0x10 -1 read-write n 0x0 0x0 CLKSRC System Tick Clock Source Select Bit 2 1 read-write 0 Clock source is optional, refer to STCLKSEL #0 1 Core clock used for SysTick timer #1 COUNTFLAG System Tick Counter Flag\nReturns 1 If Timer Counted to 0 Since Last Time this Register Was Read 16 1 read-write 0 COUNTFLAG is cleared on read or by a write to the Current Value register #0 1 COUNTFLAG is set by a count transition from 1 to 0 #1 ENABLE System Tick Counter Enable Control 0 1 read-write 0 System Tick counter Disabled #0 1 System Tick counter will operate in a multi-shot manner #1 TICKINT System Tick Interrupt Enable Control 1 1 read-write 0 Counting down to 0 will not cause the SysTick exception to be pended. User can use COUNTFLAG to determine if a count to zero has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended #1 SYST_CVR SYST_CVR SysTick Current Value Register 0x18 read-write n 0x0 0x0 CURRENT System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. 0 24 read-write SYST_RVR SYST_RVR SysTick Reload Value Register 0x14 read-write n 0x0 0x0 RELOAD System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0. 0 24 read-write SPI0 SPI Register Map SPI 0x0 0x0 0x18 registers n 0x20 0x8 registers n 0x38 0x8 registers n 0x50 0x4 registers n SPI_CLKDIV SPI_CLKDIV SPI Clock Divider Register 0x8 read-write n 0x0 0x0 DIVIDER Clock Divider\nThe value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation:\nWhere\n is the SPI peripheral clock source. It is defined in the CLK_SEL2[21:20] in Clock control section (CLK_BA + 0x18). 0 8 read-write SPI_CTL SPI_CTL SPI Control Register 0x0 -1 read-write n 0x0 0x0 CLKPOL Clock Polarity\nNote: Refer to Clock Parity section. 11 1 read-write 0 The default level of SCLK is low #0 1 The default level of SCLK is high #1 DUALDIR Dual I/O Mode Direction Control\nRefer to Dual I/O Mode section. 28 1 read-write 0 Date read in the Dual I/O Mode function #0 1 Data write in the Dual I/O Mode function. #1 DUALIOEN Dual I/O Mode EnableBit\nRefer to Dual I/O Mode section. 29 1 read-write 0 Dual I/O Mode function Disabled #0 1 Dual I/O Mode function Enabled #1 DWIDTH Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can be up to 32 bits. 3 5 read-write 0 32 bits are transmitted in one transaction #00000 8 8 bits are transmitted in one transaction #01000 9 9 bits are transmitted in one transaction #01001 10 10 bits are transmitted in one transaction #01010 30 30 bits are transmitted in one transaction #11110 31 31 bits are transmitted in one transaction #11111 FIFOM FIFO Mode EnableBit\nNote: Refer to FIFO Mode section. 21 1 read-write 0 FIFO mode Disabled (in Normal mode) #0 1 FIFO mode Enabled #1 GOBUSY SPI Transfer Control Bit and Busy Status If the FIFO mode is disabled, during the data transfer, this bit keeps the value of '1'. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status. In FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In slave mode, this bit always returns 1 when software reads this register. In master mode, this bit reflects the busy or idle status of SPI. Note: 1.When FIFO mode is disabled, all configurations should be set before writing 1 to the GOBUSY bit in the SPI_CTL register. 2. When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer. 0 1 read-write 0 Writing this bit 0 will stop data transfer if SPI is transferring #0 1 In Master mode, writing 1 to this bit will start the SPI data transfer In Slave mode, writing '1' to this bit indicates that the slave is ready to communicate with a master #1 LSB Send LSB First\nNote: Refer to LSB first section. 10 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH (SPI_CTL[7:3]), is transmitted/received first #0 1 The LSB, bit 0 of the SPI_TX0/1, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of theRX register (SPI_RX0/1) #1 REORDER Byte Reorder Function EnableBit\nNote: The suspend interval is defined in SUSPITV.Refer to Byte Reorder section.\nNote: Byte Suspend is only used in SPI Byte Reorder mode. 19 1 read-write 0 Byte reorderfunction Disabled #0 1 Enable byte reorder function and insert a byte suspend interval among each byte. The setting of DWIDTH must be configured as 00b ( 32 bits/ word) #1 RXNEG Receiveon Negative Edge\nNote: Refer to Edge section. 1 1 read-write 0 The received data is latched on the rising edge of SPI_SCLK #0 1 The received data is latched on the falling edge of SPI_SCLK #1 SLAVE Slave Mode Selection\nNote: Refer to Slave Selection section 18 1 read-write 0 SPI controller set as Master mode #0 1 SPI controller set as Slave mode #1 SUSPITV Suspend Interval (Master Only) 12 4 read-write TWOBIT 2-bit Transfer Mode Enable Bit\nRefer to Two Bit Transfer Mode section\nNote: automatically 22 1 read-write 0 2-bit transfer mode Disabled #0 1 2-bit transfer mode Enabled #1 TXNEG Transmit on Negative Edge\nNote: Refer to Edge section. 2 1 read-write 0 The transmitted data output is changed on the rising edge of SPI_SCLK #0 1 The transmitted data output is changed on the falling edge of SPI_SCLK #1 UNITIEN Unit Transfer Interrupt Enable Bit 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transferinterrupt Enabled #1 WKCLKEN Wake-up by SPI Clock EnableBit\nNote: When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_CLK port. After the system wake-up, this bit must be cleared by user to disable the wake-up requirement. 31 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 WKSSEN Wake-up by Slave Select EnableBit\nNote: The Slave select wake-up function is only available in SPI Slave mode. When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_SS port. After the system wake-up, this bit must be cleared by user to disable the wake-up requirement. 30 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 SPI_FIFOCTL SPI_FIFOCTL SPI FIFO Control Register 0x3C -1 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear Note:This bit is used to clear the receiver counter in FIFO Mode. This bit can be written 1 to clear the receiver counter and this bit will be cleared to 0 automatically after clearing receiving counter. After the clear operation, the flag of RXEMPTY in SPI_STATUS[0] will be set to 1 . 0 1 read-write 0 No clear the received FIFO #0 1 Clear the received FIFO #1 RXOVIEN ReceiveFIFO Overrun Interrupt Enable Bit 4 1 read-write 0 RXFIFO overrun interrupt Disabled #0 1 RX FIFO overrun interrupt Enabled #1 RXTH Received FIFO Threshold\nIf RX valid data counts are greater than RXTH, RXTHIF (SPI_STATUS[8])will be set to 1.. 24 3 read-write RXTHIEN Receive Threshold Interrupt Enable Bit 2 1 read-write 0 RX threshold interrupt Disabled #0 1 RX threshold interrupt Enabled #1 RXTOIEN RX Read Time Out Interrupt Enable Bit 7 1 read-write 0 RXread Time-out Interrupt Disabled #0 1 RX read Time-out Interrupt Enabled #1 TXFBCLR Transmit FIFO Buffer Clear Note:This bit is used to clear the transmit counter in FIFO Mode. This bit can be written 1 to clear the transmitting counter and this bit will be cleared to 0 automatically after clearing transmitting counter. After the clear operation, the flag of TXEMPTY in SPI_STATUS[2] will be set to 1 . 1 1 read-write 0 Not clear the transmitted FIFO #0 1 Clear the transmitted FIFO #1 TXTH Transmit FIFO Threshold\nIf TX valid data counts are smaller than or equal to TXTH, TXTHIF(SPI_STATUS[10])will be set to 1. 28 3 read-write TXTHIEN Transmit Threshold Interrupt Enable Bit 3 1 read-write 0 TX threshold interrupt Disabled #0 1 TX threshold interrupt Enabled #1 SPI_INTERNAL SPI_INTERNAL SPI INTERNAL Register 0x50 read-write n 0x0 0x0 SPI_PDMACTL SPI_PDMACTL SPI PDMA Control Register 0x38 read-write n 0x0 0x0 PDMARST PDMA Reset It is used to reset the SPI PDMA function into default state. Note:It is auto cleared to 0 after the reset function has done. 2 1 read-write 0 After reset PDMA function or in normal operation #0 1 Reset PDMA function #1 RXPDMAEN Receiving PDMA EnableBit Refer to PDMA section for more detail information. Note: Hardware will clear this bit to 0 automatically after PDMA transfer done. In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clock + 4 APB clock. 1 1 read-write 0 Receiver PDMA function Disabled #0 1 Receiver PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit\nRefer to PDMA section for more detailed information.\nSPI_CTLNote:\n1. Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode.\n2. If the 2-bit function is enabled, the requirement timing shall append 18 APB clock based on the above clock period.\nHardware will clear this bit to 0 automatically after PDMA transfer is done. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPI_RX0 SPI_RX0 SPI Receive Data FIFO Register 0 0x10 read-only n 0x0 0x0 RX Receive Data Register (Read Only)\nThe received data can be read on it. If the FIFO bit is set as 1, the user also checks the RXEMPTY, SPI_STATUS[0], to check if there is any more received data or not.\nNote:The SPI_RX1 is used only in TWOBIT bit (SPI_CTL[22])is set 1. The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode. SPI_RX0 shall be read first in TWOBIT mode.\nIn FIFO and two-bit mode, the first read back data in SPI_RX0 is the first channel data and the second read back data in SPI_RX0 is the second channel data. 0 32 read-only SPI_RX1 SPI_RX1 SPI Receive Data FIFO Register 1 0x14 read-write n 0x0 0x0 SPI_SSCTL SPI_SSCTL SPI Slave Select Control Register 0xC -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit (Master Only) 3 1 read-write 0 If this bit is set as 0 , slave select signals are asserted and de-asserted by setting and clearing related bits in SS[1:0] (SPI_CTL[1:0]) #0 1 If this bit is set as 1 , SPI_SS0 and SPI_SS1 signals are generated automatically. It means that device/slave select signal, which is set in SS[1:0] (SPI_CTL[1:0]) is asserted by the SPI controller when transmit/receive is started, and is de-asserted after each transaction is done #1 SLV3WIRE Slave 3-wire Mode Enable Bit This bit is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI when it is set as a slave device. Note 1:Refer to No Slave Select Mode. Note 2: In no slave select signal mode, hardware will set the SSLTRIG (SPI_SSCTL[4]) as 1 automatically. 5 1 read-write 0 The controller is 4-wire bi-direction interface #0 1 The controller is 3-wire bi-direction interface in Slave mode. When this bit is set as 1, the controller start to transmit/receive data after the GOBUSY bit active and the SPI clock input #1 SLVABORT Abort in Slave Mode with No Slave Selected Refer to No Slave Select Mode. Note: It is auto cleared to 0 by hardware when the abort event is active. 8 1 read-write 0 No force the slave abort #0 1 Force the current transfer done in no slave select mode #1 SLVTOCNT Slave Mode Time-out Period\nIn Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled. 20 10 read-write SLVTOIEN Slave Time-out Interrupt Enable Bit\nThis bit is used to enable the slave time-out function in slave mode and there will be an interrupt if slave time-out event occur 6 1 read-write 0 Slave time-out function and interrupt both Disabled #0 1 Slave time-out function and interrupt both Enabled #1 SS Slave SelectionControl (Master Only) If AUTOSS bit (SPI_SSCTL[3]) is cleared, writing 1 to SS[0] (SPI_CTL[0]) bit sets the SPI_SS0 line to an active state and writing 0 sets the line back to inactive state(the same as SPI_CTL[1] for SPI_SS1). Note: 1. This interface can only drive one device/slave at a given time. Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer. 2. SPI_SS0 is also defined as device/slave select input in Slave mode. And that the slave select input must be driven by edge active trigger which level depend on the SSACTPOL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software. 0 2 read-write 0 Both SPI_SS1 and SPI_SS0 are inactive #00 1 SPI_SS1 is inactive, SPI_SS0 is active.\nSPI_SS1 is inactive, SPI_SS0 is active on the duration of transaction #01 2 SPI_SS1 is active, SPI_SS0 is inactive.\nSPI_SS1 is active on the duration of transaction, SPI_SS0 is inactive #10 3 Both SPI_SS1 and SPI_SS0 are active..\nBoth SPI_SS1 and SPI_SS0 are active on the duration of transaction #11 SSACTPOL Slave Selection Active Polarity\nIt defines the active polarity of slave selection signal (SPI_SS[1:0]). 2 1 read-write 0 The SPI_SS slave select signal is active Low #0 1 The SPI_SS slave select signal is active High #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit\nIt is used to enable the interrupt when the transfer has done in slave mode. 16 1 read-write 0 No any interrupt, even there is slave select inactive event #0 1 There is interrupt event when the slave select becomes inactive from active condition. It is used to inform the user to know that the transaction has finished and the slave select into the inactive state #1 SSLTRIG Slave Select Level Trigger Control 4 1 read-write 0 The input slave select signal is edge-trigger #0 1 The slave select signal will be level-trigger. It depends on SSACTPOL to decide the signal is active low or active high #1 SSTAIEN Slave Start Interrupt EnableBit\nRefer to No Slave Select Mode. 9 1 read-write 0 Transfer start interrupt Disabled in no slave select mode #0 1 Transaction start interrupt Enabled in no slave select mode. It is cleared when the current transfer done or the SLVSTAIF bit cleared (write 1 clear) #1 SPI_STATUS SPI_STATUS SPI Status Register 0x4 -1 read-write n 0x0 0x0 LTRIGF Level Trigger Accomplish Flag(Read Only)\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only. As the software sets the GOBUSY bit to 1, the LTRIGF will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit is unmeaning. 4 1 read-only 0 The transferred bit length of one transaction does not meet the specified requirement #0 1 The transferred bit length meets the specified requirement which defined in DWIDTH #1 RXCNT Receive FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 16 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator(Read Only) 0 1 read-only 0 Received data FIFO is not empty in the FIFO mode #0 1 Received data FIFO is empty in the FIFO mode #1 RXFULL Receive FIFO Buffer Full Indicator(Read Only) 1 1 read-only 0 Received data FIFO is not full in FIFO mode #0 1 Received data FIFO is full in the FIFO mode #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nNote 1: If SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will be dropped.\nNote 2: This bit will be cleared by writing 1 to it. 9 1 read-write 0 No FIFO over run #0 1 Receive FIFO over run #1 RXTHIF RX FIFO Threshold Interrupt Flag(Read Only) 8 1 read-only 0 RX valid data counts small or equal than RXTH (SPI_FIFOCTL[27:24]) #0 1 RX valid data counts bigger than RXTH #1 RXTOIF Receive Time-outInterrupt Flag\nRefer to Time Out section.\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 There is not time-out event on the received buffer #0 1 Time out event active in RX FIFO is not empty #1 SLVSTAIF Slave Start Interrupt Flag\nIt is used to dedicate that the transfer has started in Slave mode with no slave select. 6 1 read-write 0 Slave started transfer no active #0 1 Transfer has started in Slave mode with no slave select. It is automatically cleared by transfer done or writing '1' #1 SLVTOIF Slave Time-out Interrupt Flag\nIf SLVTOIEN (SPI_SSCTL[6]) is set to 1, this bit will be asserted when slave time-out event occur. Software can clear this bit by setting RXFBCLR (SPI_FIFOCTL[0]) or writing 1 to clear this bit. 13 1 read-write 0 Slave time-out does not occur yet #0 1 Slave time-out has occurred #1 SLVTXSKE Slave Mode Transmit Skew Buffer Empty Status\nThis bit indicates the empty status of transmit skew buffer which is used in Slave mode. 15 1 read-write TXCNT Transmit FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 20 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator(Read Only) 2 1 read-only 0 Transmitted data FIFO is not empty in the FIFO mode #0 1 Transmitted data FIFO is empty in the FIFO mode #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 3 1 read-only 0 Transmitted data FIFO is not full in the FIFO mode #0 1 Transmitted data FIFO is full in the FIFO mode #1 TXTHIF Transmit FIFO Threshold Interrupt Flag(Read Only) 10 1 read-only 0 TX valid data counts bigger than TXTH (SPI_FIFOCTL[31:28]) #0 1 TX valid data counts small or equal than TXTH #1 UNITIF Unit Transfer Interrupt Flag Note 2: This bitcan be cleared by writing 1 to it. 7 1 read-write 0 No transaction has been finished since this bit was cleared to 0.\nTransfer is not finished yet #0 1 SPI controller has finished one unit transfer.\nTransfer is done. The interrupt is requested when the UNITIEN(SPI_CTL[17]) bit is enabled #1 WKCLKIF Wake-up by SPI Clock Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_CLK port, this bit is set to 1. This bit can be cleared by writing '1' to it. 31 1 read-write WKSSIF Wake-up by Slave Select Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_SS port, this bit is set to 1. This bit can be cleared by writing '1' to it. 30 1 read-write SPI_TX0 SPI_TX0 SPI Transmit Data FIFO Register 0 0x20 write-only n 0x0 0x0 TX Transmit Data Register (Write Only)\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example, if DWIDTH is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer. If DWIDTH is set to 0x0, the SPI controller will perform a 32-bit transfer.\nNote:\n1. The SPI_TX1 is used only when TWOBIT bit (SPI_CTL[22])is set 1. The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in two-bit mode. SPI_TX0 shall be written first in TWOBIT mode.\nIn FIFO and two-bit mode, the first written into data in SPI_TX0 is the first channel's transmitted data and the second written data in SPI_TX1 is the second channel's transmitted data.\n2.If the SPI controller operates as slave device and FIFO mode is disabled, software must update the transmit data register before setting the GOBUSY bit to 1. 0 32 write-only SPI_TX1 SPI_TX1 SPI Transmit Data FIFO Register 1 0x24 read-write n 0x0 0x0 SPI1 SPI Register Map SPI 0x0 0x0 0x18 registers n 0x20 0x8 registers n 0x38 0x8 registers n 0x50 0x4 registers n SPI_CLKDIV SPI_CLKDIV SPI Clock Divider Register 0x8 read-write n 0x0 0x0 DIVIDER Clock Divider\nThe value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation:\nWhere\n is the SPI peripheral clock source. It is defined in the CLK_SEL2[21:20] in Clock control section (CLK_BA + 0x18). 0 8 read-write SPI_CTL SPI_CTL SPI Control Register 0x0 -1 read-write n 0x0 0x0 CLKPOL Clock Polarity\nNote: Refer to Clock Parity section. 11 1 read-write 0 The default level of SCLK is low #0 1 The default level of SCLK is high #1 DUALDIR Dual I/O Mode Direction Control\nRefer to Dual I/O Mode section. 28 1 read-write 0 Date read in the Dual I/O Mode function #0 1 Data write in the Dual I/O Mode function #1 DUALIOEN Dual I/O Mode EnableBit\nRefer to Dual I/O Mode section. 29 1 read-write 0 Dual I/O Mode function Disabled #0 1 Dual I/O Mode function Enabled #1 DWIDTH Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can be up to 32 bits. 3 5 read-write 0 32 bits are transmitted in one transaction #00000 8 8 bits are transmitted in one transaction #01000 9 9 bits are transmitted in one transaction #01001 10 10 bits are transmitted in one transaction #01010 30 30 bits are transmitted in one transaction #11110 31 31 bits are transmitted in one transaction #11111 FIFOM FIFO Mode EnableBit\nNote: Refer to FIFO Mode section. 21 1 read-write 0 FIFO mode Disabled (in Normal mode) #0 1 FIFO mode Enabled #1 GOBUSY SPI Transfer Control Bit and Busy Status If the FIFO mode is disabled, during the data transfer, this bit keeps the value of '1'. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status. In FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In slave mode, this bit always returns 1 when software reads this register. In master mode, this bit reflects the busy or idle status of SPI. Note: 1.When FIFO mode is disabled, all configurations should be set before writing 1 to the GOBUSY bit in the SPI_CTL register. 2. When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer. 0 1 read-write 0 Writing this bit 0 will stop data transfer if SPI is transferring #0 1 In Master mode, writing 1 to this bit will start the SPI data transfer In Slave mode, writing '1' to this bit indicates that the slave is ready to communicate with a master #1 LSB Send LSB First\nNote: Refer to LSB first section. 10 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH (SPI_CTL[7:3]), is transmitted/received first #0 1 The LSB, bit 0 of the SPI_TX0/1, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of theRX register (SPI_RX0/1) #1 REORDER Byte Reorder Function EnableBit\nNote: The suspend interval is defined in SUSPITV.Refer to Byte Reorder section.\nNote: Byte Suspend is only used in SPI Byte Reorder mode. 19 1 read-write 0 Byte reorderfunction Disabled #0 1 Enable byte reorder function and insert a byte suspend interval among each byte. The setting of DWIDTH must be configured as 00b ( 32 bits/ word) #1 RXNEG Receiveon Negative Edge\nNote: Refer to Edge section. 1 1 read-write 0 The received data is latched on the rising edge of SPI_SCLK #0 1 The received data is latched on the falling edge of SPI_SCLK #1 SLAVE Slave Mode Selection\nNote: Refer to Slave Selection section 18 1 read-write 0 SPI controller set as Master mode #0 1 SPI controller set as Slave mode #1 SUSPITV Suspend Interval (Master Only) 12 4 read-write TWOBIT 2-bit Transfer Mode Enable Bit\nRefer to Two Bit Transfer Mode section\nNote: automatically 22 1 read-write 0 2-bit transfer mode Disabled #0 1 2-bit transfer mode Enabled #1 TXNEG Transmit on Negative Edge\nNote: Refer to Edge section. 2 1 read-write 0 The transmitted data output is changed on the rising edge of SPI_SCLK #0 1 The transmitted data output is changed on the falling edge of SPI_SCLK #1 UNITIEN Unit Transfer Interrupt Enable Bit 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transferinterrupt Enabled #1 WKCLKEN Wake-up by SPI Clock EnableBit\nNote: When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_CLK port. After the system wake-up, this bit must be cleared by user to disable the wake-up requirement. 31 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 WKSSEN Wake-up by Slave Select EnableBit\nNote: The Slave select wake-up function is only available in SPI Slave mode. When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_SS port. After the system wake-up, this bit must be cleared by user to disable the wake-up requirement. 30 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 SPI_FIFOCTL SPI_FIFOCTL SPI FIFO Control Register 0x3C -1 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear Note:This bit is used to clear the receiver counter in FIFO Mode. This bit can be written 1 to clear the receiver counter and this bit will be cleared to 0 automatically after clearing receiving counter. After the clear operation, the flag of RXEMPTY in SPI_STATUS[0] will be set to 1 . 0 1 read-write 0 No clear the received FIFO #0 1 Clear the received FIFO #1 RXOVIEN ReceiveFIFO Overrun Interrupt Enable Bit 4 1 read-write 0 RXFIFO overrun interrupt Disabled #0 1 RX FIFO overrun interrupt Enabled #1 RXTH Received FIFO Threshold\nIf RX valid data counts are greater than RXTH, RXTHIF (SPI_STATUS[8])will be set to 1.. 24 3 read-write RXTHIEN Receive Threshold Interrupt Enable Bit 2 1 read-write 0 RX threshold interrupt Disabled #0 1 RX threshold interrupt Enabled #1 RXTOIEN RX Read Time Out Interrupt Enable Bit 7 1 read-write 0 RXread Time-out Interrupt Disabled #0 1 RX read Time-out Interrupt Enabled #1 TXFBCLR Transmit FIFO Buffer Clear Note:This bit is used to clear the transmit counter in FIFO Mode. This bit can be written 1 to clear the transmitting counter and this bit will be cleared to 0 automatically after clearing transmitting counter. After the clear operation, the flag of TXEMPTY in SPI_STATUS[2] will be set to 1 . 1 1 read-write 0 Not clear the transmitted FIFO #0 1 Clear the transmitted FIFO #1 TXTH Transmit FIFO Threshold\nIf TX valid data counts are smaller than or equal to TXTH, TXTHIF(SPI_STATUS[10])will be set to 1. 28 3 read-write TXTHIEN Transmit Threshold Interrupt Enable Bit 3 1 read-write 0 TX threshold interrupt Disabled #0 1 TX threshold interrupt Enabled #1 SPI_INTERNAL SPI_INTERNAL SPI INTERNAL Register 0x50 read-write n 0x0 0x0 SPI_PDMACTL SPI_PDMACTL SPI PDMA Control Register 0x38 read-write n 0x0 0x0 PDMARST PDMA Reset It is used to reset the SPI PDMA function into default state. Note:It is auto cleared to 0 after the reset function has done. 2 1 read-write 0 After reset PDMA function or in normal operation #0 1 Reset PDMA function #1 RXPDMAEN Receiving PDMA EnableBit Refer to PDMA section for more detail information. Note: Hardware will clear this bit to 0 automatically after PDMA transfer done. In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clock + 4 APB clock. 1 1 read-write 0 Receiver PDMA function Disabled #0 1 Receiver PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit\nRefer to PDMA section for more detailed information.\nSPI_CTLNote:\n1. Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode.\n2. If the 2-bit function is enabled, the requirement timing shall append 18 APB clock based on the above clock period.\nHardware will clear this bit to 0 automatically after PDMA transfer is done. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPI_RX0 SPI_RX0 SPI Receive Data FIFO Register 0 0x10 read-only n 0x0 0x0 RX Receive Data Register (Read Only)\nThe received data can be read on it. If the FIFO bit is set as 1, the user also checks the RXEMPTY, SPI_STATUS[0], to check if there is any more received data or not.\nNote:The SPI_RX1 is used only in TWOBIT bit (SPI_CTL[22])is set 1. The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode. SPI_RX0 shall be read first in TWOBIT mode.\nIn FIFO and two-bit mode, the first read back data in SPI_RX0 is the first channel data and the second read back data in SPI_RX0 is the second channel data. 0 32 read-only SPI_RX1 SPI_RX1 SPI Receive Data FIFO Register 1 0x14 read-write n 0x0 0x0 SPI_SSCTL SPI_SSCTL SPI Slave Select Control Register 0xC -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit (Master Only) 3 1 read-write 0 If this bit is set as 0 , slave select signals are asserted and de-asserted by setting and clearing related bits in SS[1:0] (SPI_CTL[1:0]) #0 1 If this bit is set as 1 , SPI_SS0 and SPI_SS1 signals are generated automatically. It means that device/slave select signal, which is set in SS[1:0] (SPI_CTL[1:0]) is asserted by the SPI controller when transmit/receive is started, and is de-asserted after each transaction is done #1 SLV3WIRE Slave 3-wire Mode Enable Bit This bit is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI when it is set as a slave device. Note 1:Refer to No Slave Select Mode. Note 2: In no slave select signal mode, hardware will set the SSLTRIG (SPI_SSCTL[4]) as 1 automatically. 5 1 read-write 0 The controller is 4-wire bi-direction interface #0 1 The controller is 3-wire bi-direction interface in Slave mode. When this bit is set as 1, the controller start to transmit/receive data after the GOBUSY bit active and the SPI clock input #1 SLVABORT Abort in Slave Mode with No Slave Selected Refer to No Slave Select Mode. Note: It is auto cleared to 0 by hardware when the abort event is active. 8 1 read-write 0 No force the slave abort #0 1 Force the current transfer done in no slave select mode #1 SLVTOCNT Slave Mode Time-out Period\nIn Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled. 20 10 read-write SLVTOIEN Slave Time-out Interrupt Enable Bit\nThis bit is used to enable the slave time-out function in slave mode and there will be an interrupt if slave time-out event occur 6 1 read-write 0 Slave time-out function and interrupt both Disabled #0 1 Slave time-out function and interrupt both Enabled #1 SS Slave SelectionControl (Master Only) If AUTOSS bit (SPI_SSCTL[3]) is cleared, writing 1 to SS[0] (SPI_CTL[0]) bit sets the SPI_SS0 line to an active state and writing 0 sets the line back to inactive state(the same as SPI_CTL[1] for SPI_SS1). Note: 1. This interface can only drive one device/slave at a given time. Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer. 2. SPI_SS0 is also defined as device/slave select input in Slave mode. And that the slave select input must be driven by edge active trigger which level depend on the SSACTPOL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software. 0 2 read-write 0 Both SPI_SS1 and SPI_SS0 are inactive #00 1 SPI_SS1 is inactive, SPI_SS0 is active.\nSPI_SS1 is inactive, SPI_SS0 is active on the duration of transaction #01 2 SPI_SS1 is active, SPI_SS0 is inactive.\nSPI_SS1 is active on the duration of transaction, SPI_SS0 is inactive #10 3 Both SPI_SS1 and SPI_SS0 are active..\nBoth SPI_SS1 and SPI_SS0 are active on the duration of transaction #11 SSACTPOL Slave Selection Active Polarity\nIt defines the active polarity of slave selection signal (SPI_SS[1:0]). 2 1 read-write 0 The SPI_SS slave select signal is active Low #0 1 The SPI_SS slave select signal is active High #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit\nIt is used to enable the interrupt when the transfer has done in slave mode. 16 1 read-write 0 No any interrupt, even there is slave select inactive event #0 1 There is interrupt event when the slave select becomes inactive from active condition. It is used to inform the user to know that the transaction has finished and the slave select into the inactive state #1 SSLTRIG Slave Select Level Trigger Control 4 1 read-write 0 The input slave select signal is edge-trigger #0 1 The slave select signal will be level-trigger. It depends on SSACTPOL to decide the signal is active low or active high #1 SSTAIEN Slave Start Interrupt EnableBit\nRefer to No Slave Select Mode. 9 1 read-write 0 Transfer start interrupt Disabled in no slave select mode #0 1 Transaction start interrupt Enabled in no slave select mode. It is cleared when the current transfer done or the SLVSTAIF bit cleared (write 1 clear) #1 SPI_STATUS SPI_STATUS SPI Status Register 0x4 -1 read-write n 0x0 0x0 LTRIGF Level Trigger Accomplish Flag(Read Only)\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only. As the software sets the GOBUSY bit to 1, the LTRIGF will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit is unmeaning. 4 1 read-only 0 The transferred bit length of one transaction does not meet the specified requirement #0 1 The transferred bit length meets the specified requirement which defined in DWIDTH #1 RXCNT Receive FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 16 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator(Read Only) 0 1 read-only 0 Received data FIFO is not empty in the FIFO mode #0 1 Received data FIFO is empty in the FIFO mode #1 RXFULL Receive FIFO Buffer Full Indicator(Read Only) 1 1 read-only 0 Received data FIFO is not full in FIFO mode #0 1 Received data FIFO is full in the FIFO mode #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nNote 1: If SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will be dropped.\nNote 2: This bit will be cleared by writing 1 to it. 9 1 read-write 0 No FIFO over run #0 1 Receive FIFO over run #1 RXTHIF RX FIFO Threshold Interrupt Flag(Read Only) 8 1 read-only 0 RX valid data counts small or equal than RXTH (SPI_FIFOCTL[27:24]) #0 1 RX valid data counts bigger than RXTH #1 RXTOIF Receive Time-outInterrupt Flag\nRefer to Time Out section.\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 There is not time-out event on the received buffer #0 1 Time out event active in RX FIFO is not empty #1 SLVSTAIF Slave Start Interrupt Flag\nIt is used to dedicate that the transfer has started in Slave mode with no slave select. 6 1 read-write 0 Slave started transfer no active #0 1 Transfer has started in Slave mode with no slave select. It is automatically cleared by transfer done or writing '1' #1 SLVTOIF Slave Time-out Interrupt Flag\nIf SLVTOIEN (SPI_SSCTL[6]) is set to 1, this bit will be asserted when slave time-out event occur. Software can clear this bit by setting RXFBCLR (SPI_FIFOCTL[0]) or writing 1 to clear this bit. 13 1 read-write 0 Slave time-out does not occur yet #0 1 Slave time-out has occurred #1 SLVTXSKE Slave Mode Transmit Skew Buffer Empty Status\nThis bit indicates the empty status of transmit skew buffer which is used in Slave mode. 15 1 read-write TXCNT Transmit FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 20 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator(Read Only) 2 1 read-only 0 Transmitted data FIFO is not empty in the FIFO mode #0 1 Transmitted data FIFO is empty in the FIFO mode #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 3 1 read-only 0 Transmitted data FIFO is not full in the FIFO mode #0 1 Transmitted data FIFO is full in the FIFO mode #1 TXTHIF Transmit FIFO Threshold Interrupt Flag(Read Only) 10 1 read-only 0 TX valid data counts bigger than TXTH (SPI_FIFOCTL[31:28]) #0 1 TX valid data counts small or equal than TXTH #1 UNITIF Unit Transfer Interrupt Flag Note 2: This bitcan be cleared by writing 1 to it. 7 1 read-write 0 No transaction has been finished since this bit was cleared to 0.\nTransfer is not finished yet #0 1 SPI controller has finished one unit transfer.\nTransfer is done. The interrupt is requested when the UNITIEN(SPI_CTL[17]) bit is enabled #1 WKCLKIF Wake-up by SPI Clock Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_CLK port, this bit is set to 1. This bit can be cleared by writing '1' to it. 31 1 read-write WKSSIF Wake-up by Slave Select Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_SS port, this bit is set to 1. This bit can be cleared by writing '1' to it. 30 1 read-write SPI_TX0 SPI_TX0 SPI Transmit Data FIFO Register 0 0x20 write-only n 0x0 0x0 TX Transmit Data Register (Write Only)\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example, if DWIDTH is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer. If DWIDTH is set to 0x0, the SPI controller will perform a 32-bit transfer.\nNote:\n1. The SPI_TX1 is used only when TWOBIT bit (SPI_CTL[22])is set 1. The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in two-bit mode. SPI_TX0 shall be written first in TWOBIT mode.\nIn FIFO and two-bit mode, the first written into data in SPI_TX0 is the first channel's transmitted data and the second written data in SPI_TX1 is the second channel's transmitted data.\n2.If the SPI controller operates as slave device and FIFO mode is disabled, software must update the transmit data register before setting the GOBUSY bit to 1. 0 32 write-only SPI_TX1 SPI_TX1 SPI Transmit Data FIFO Register 1 0x24 read-write n 0x0 0x0 SPI2 SPI Register Map SPI 0x0 0x0 0x18 registers n 0x20 0x8 registers n 0x38 0x8 registers n 0x50 0x4 registers n SPI_CLKDIV SPI_CLKDIV SPI Clock Divider Register 0x8 read-write n 0x0 0x0 DIVIDER Clock Divider\nThe value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation:\nWhere\n is the SPI peripheral clock source. It is defined in the CLK_SEL2[21:20] in Clock control section (CLK_BA + 0x18). 0 8 read-write SPI_CTL SPI_CTL SPI Control Register 0x0 -1 read-write n 0x0 0x0 CLKPOL Clock Polarity\nNote: Refer to Clock Parity section. 11 1 read-write 0 The default level of SCLK is low #0 1 The default level of SCLK is high #1 DUALDIR Dual I/O Mode Direction Control\nRefer to Dual I/O Mode section. 28 1 read-write 0 Date read in the Dual I/O Mode function #0 1 Data write in the Dual I/O Mode function #1 DUALIOEN Dual I/O Mode EnableBit\nRefer to Dual I/O Mode section. 29 1 read-write 0 Dual I/O Mode function Disabled #0 1 Dual I/O Mode function Enabled #1 DWIDTH Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can be up to 32 bits. 3 5 read-write 0 32 bits are transmitted in one transaction #00000 8 8 bits are transmitted in one transaction #01000 9 9 bits are transmitted in one transaction #01001 10 10 bits are transmitted in one transaction #01010 30 30 bits are transmitted in one transaction #11110 31 31 bits are transmitted in one transaction #11111 FIFOM FIFO Mode EnableBit\nNote: Refer to FIFO Mode section. 21 1 read-write 0 FIFO mode Disabled (in Normal mode) #0 1 FIFO mode Enabled #1 GOBUSY SPI Transfer Control Bit and Busy Status If the FIFO mode is disabled, during the data transfer, this bit keeps the value of '1'. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status. In FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In slave mode, this bit always returns 1 when software reads this register. In master mode, this bit reflects the busy or idle status of SPI. Note: 1.When FIFO mode is disabled, all configurations should be set before writing 1 to the GOBUSY bit in the SPI_CTL register. 2. When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer. 0 1 read-write 0 Writing this bit 0 will stop data transfer if SPI is transferring #0 1 In Master mode, writing 1 to this bit will start the SPI data transfer In Slave mode, writing '1' to this bit indicates that the slave is ready to communicate with a master #1 LSB Send LSB First\nNote: Refer to LSB first section. 10 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH (SPI_CTL[7:3]), is transmitted/received first #0 1 The LSB, bit 0 of the SPI_TX0/1, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of theRX register (SPI_RX0/1) #1 REORDER Byte Reorder Function EnableBit\nNote: The suspend interval is defined in SUSPITV.Refer to Byte Reorder section.\nNote: Byte Suspend is only used in SPI Byte Reorder mode. 19 1 read-write 0 Byte reorderfunction Disabled #0 1 Enable byte reorder function and insert a byte suspend interval among each byte. The setting of DWIDTH must be configured as 00b ( 32 bits/ word) #1 RXNEG Receiveon Negative Edge\nNote: Refer to Edge section. 1 1 read-write 0 The received data is latched on the rising edge of SPI_SCLK #0 1 The received data is latched on the falling edge of SPI_SCLK #1 SLAVE Slave Mode Selection\nNote: Refer to Slave Selection section 18 1 read-write 0 SPI controller set as Master mode #0 1 SPI controller set as Slave mode #1 SUSPITV Suspend Interval (Master Only) 12 4 read-write TWOBIT 2-bit Transfer Mode Enable Bit\nRefer to Two Bit Transfer Mode section\nNote: automatically 22 1 read-write 0 2-bit transfer mode Disabled #0 1 2-bit transfer mode Enabled #1 TXNEG Transmit on Negative Edge\nNote: Refer to Edge section. 2 1 read-write 0 The transmitted data output is changed on the rising edge of SPI_SCLK #0 1 The transmitted data output is changed on the falling edge of SPI_SCLK #1 UNITIEN Unit Transfer Interrupt Enable Bit 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transferinterrupt Enabled #1 WKCLKEN Wake-up by SPI Clock EnableBit\nNote: When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_CLK port. After the system wake-up, this bit must be cleared by user to disable the wake-up requirement. 31 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 WKSSEN Wake-up by Slave Select EnableBit\nNote: The Slave select wake-up function is only available in SPI Slave mode. When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_SS port. After the system wake-up, this bit must be cleared by user to disable the wake-up requirement. 30 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 SPI_FIFOCTL SPI_FIFOCTL SPI FIFO Control Register 0x3C -1 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear Note:This bit is used to clear the receiver counter in FIFO Mode. This bit can be written 1 to clear the receiver counter and this bit will be cleared to 0 automatically after clearing receiving counter. After the clear operation, the flag of RXEMPTY in SPI_STATUS[0] will be set to 1 . 0 1 read-write 0 No clear the received FIFO #0 1 Clear the received FIFO #1 RXOVIEN ReceiveFIFO Overrun Interrupt Enable Bit 4 1 read-write 0 RXFIFO overrun interrupt Disabled #0 1 RX FIFO overrun interrupt Enabled #1 RXTH Received FIFO Threshold\nIf RX valid data counts are greater than RXTH, RXTHIF (SPI_STATUS[8])will be set to 1.. 24 3 read-write RXTHIEN Receive Threshold Interrupt Enable Bit 2 1 read-write 0 RX threshold interrupt Disabled #0 1 RX threshold interrupt Enabled #1 RXTOIEN RX Read Time Out Interrupt Enable Bit 7 1 read-write 0 RXread Time-out Interrupt Disabled #0 1 RX read Time-out Interrupt Enabled #1 TXFBCLR Transmit FIFO Buffer Clear Note:This bit is used to clear the transmit counter in FIFO Mode. This bit can be written 1 to clear the transmitting counter and this bit will be cleared to 0 automatically after clearing transmitting counter. After the clear operation, the flag of TXEMPTY in SPI_STATUS[2] will be set to 1 . 1 1 read-write 0 Not clear the transmitted FIFO #0 1 Clear the transmitted FIFO #1 TXTH Transmit FIFO Threshold\nIf TX valid data counts are smaller than or equal to TXTH, TXTHIF(SPI_STATUS[10])will be set to 1. 28 3 read-write TXTHIEN Transmit Threshold Interrupt Enable Bit 3 1 read-write 0 TX threshold interrupt Disabled #0 1 TX threshold interrupt Enabled #1 SPI_INTERNAL SPI_INTERNAL SPI INTERNAL Register 0x50 read-write n 0x0 0x0 SPI_PDMACTL SPI_PDMACTL SPI PDMA Control Register 0x38 read-write n 0x0 0x0 PDMARST PDMA Reset It is used to reset the SPI PDMA function into default state. Note:It is auto cleared to 0 after the reset function has done. 2 1 read-write 0 After reset PDMA function or in normal operation #0 1 Reset PDMA function #1 RXPDMAEN Receiving PDMA EnableBit Refer to PDMA section for more detail information. Note: Hardware will clear this bit to 0 automatically after PDMA transfer done. In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clock + 4 APB clock. 1 1 read-write 0 Receiver PDMA function Disabled #0 1 Receiver PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit\nRefer to PDMA section for more detailed information.\nSPI_CTLNote:\n1. Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode.\n2. If the 2-bit function is enabled, the requirement timing shall append 18 APB clock based on the above clock period.\nHardware will clear this bit to 0 automatically after PDMA transfer is done. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPI_RX0 SPI_RX0 SPI Receive Data FIFO Register 0 0x10 read-only n 0x0 0x0 RX Receive Data Register (Read Only)\nThe received data can be read on it. If the FIFO bit is set as 1, the user also checks the RXEMPTY, SPI_STATUS[0], to check if there is any more received data or not.\nNote:The SPI_RX1 is used only in TWOBIT bit (SPI_CTL[22])is set 1. The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode. SPI_RX0 shall be read first in TWOBIT mode.\nIn FIFO and two-bit mode, the first read back data in SPI_RX0 is the first channel data and the second read back data in SPI_RX0 is the second channel data. 0 32 read-only SPI_RX1 SPI_RX1 SPI Receive Data FIFO Register 1 0x14 read-write n 0x0 0x0 SPI_SSCTL SPI_SSCTL SPI Slave Select Control Register 0xC -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit (Master Only) 3 1 read-write 0 If this bit is set as 0 , slave select signals are asserted and de-asserted by setting and clearing related bits in SS[1:0] (SPI_CTL[1:0]) #0 1 If this bit is set as 1 , SPI_SS0 and SPI_SS1 signals are generated automatically. It means that device/slave select signal, which is set in SS[1:0] (SPI_CTL[1:0]) is asserted by the SPI controller when transmit/receive is started, and is de-asserted after each transaction is done #1 SLV3WIRE Slave 3-wire Mode Enable Bit This bit is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI when it is set as a slave device. Note 1:Refer to No Slave Select Mode. Note 2: In no slave select signal mode, hardware will set the SSLTRIG (SPI_SSCTL[4]) as 1 automatically. 5 1 read-write 0 The controller is 4-wire bi-direction interface #0 1 The controller is 3-wire bi-direction interface in Slave mode. When this bit is set as 1, the controller start to transmit/receive data after the GOBUSY bit active and the SPI clock input #1 SLVABORT Abort in Slave Mode with No Slave Selected Refer to No Slave Select Mode. Note: It is auto cleared to 0 by hardware when the abort event is active. 8 1 read-write 0 No force the slave abort #0 1 Force the current transfer done in no slave select mode #1 SLVTOCNT Slave Mode Time-out Period\nIn Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled. 20 10 read-write SLVTOIEN Slave Time-out Interrupt Enable Bit\nThis bit is used to enable the slave time-out function in slave mode and there will be an interrupt if slave time-out event occur 6 1 read-write 0 Slave time-out function and interrupt both Disabled #0 1 Slave time-out function and interrupt both Enabled #1 SS Slave SelectionControl (Master Only) If AUTOSS bit (SPI_SSCTL[3]) is cleared, writing 1 to SS[0] (SPI_CTL[0]) bit sets the SPI_SS0 line to an active state and writing 0 sets the line back to inactive state(the same as SPI_CTL[1] for SPI_SS1). Note: 1. This interface can only drive one device/slave at a given time. Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer. 2. SPI_SS0 is also defined as device/slave select input in Slave mode. And that the slave select input must be driven by edge active trigger which level depend on the SSACTPOL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software. 0 2 read-write 0 Both SPI_SS1 and SPI_SS0 are inactive #00 1 SPI_SS1 is inactive, SPI_SS0 is active.\nSPI_SS1 is inactive, SPI_SS0 is active on the duration of transaction #01 2 SPI_SS1 is active, SPI_SS0 is inactive.\nSPI_SS1 is active on the duration of transaction, SPI_SS0 is inactive #10 3 Both SPI_SS1 and SPI_SS0 are active..\nBoth SPI_SS1 and SPI_SS0 are active on the duration of transaction #11 SSACTPOL Slave Selection Active Polarity\nIt defines the active polarity of slave selection signal (SPI_SS[1:0]). 2 1 read-write 0 The SPI_SS slave select signal is active Low #0 1 The SPI_SS slave select signal is active High #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit\nIt is used to enable the interrupt when the transfer has done in slave mode. 16 1 read-write 0 No any interrupt, even there is slave select inactive event #0 1 There is interrupt event when the slave select becomes inactive from active condition. It is used to inform the user to know that the transaction has finished and the slave select into the inactive state #1 SSLTRIG Slave Select Level Trigger Control 4 1 read-write 0 The input slave select signal is edge-trigger #0 1 The slave select signal will be level-trigger. It depends on SSACTPOL to decide the signal is active low or active high #1 SSTAIEN Slave Start Interrupt EnableBit\nRefer to No Slave Select Mode. 9 1 read-write 0 Transfer start interrupt Disabled in no slave select mode #0 1 Transaction start interrupt Enabled in no slave select mode. It is cleared when the current transfer done or the SLVSTAIF bit cleared (write 1 clear) #1 SPI_STATUS SPI_STATUS SPI Status Register 0x4 -1 read-write n 0x0 0x0 LTRIGF Level Trigger Accomplish Flag(Read Only)\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only. As the software sets the GOBUSY bit to 1, the LTRIGF will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit is unmeaning. 4 1 read-only 0 The transferred bit length of one transaction does not meet the specified requirement #0 1 The transferred bit length meets the specified requirement which defined in DWIDTH #1 RXCNT Receive FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 16 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator(Read Only) 0 1 read-only 0 Received data FIFO is not empty in the FIFO mode #0 1 Received data FIFO is empty in the FIFO mode #1 RXFULL Receive FIFO Buffer Full Indicator(Read Only) 1 1 read-only 0 Received data FIFO is not full in FIFO mode #0 1 Received data FIFO is full in the FIFO mode #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nNote 1: If SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will be dropped.\nNote 2: This bit will be cleared by writing 1 to it. 9 1 read-write 0 No FIFO over run #0 1 Receive FIFO over run #1 RXTHIF RX FIFO Threshold Interrupt Flag(Read Only) 8 1 read-only 0 RX valid data counts small or equal than RXTH (SPI_FIFOCTL[27:24]) #0 1 RX valid data counts bigger than RXTH #1 RXTOIF Receive Time-outInterrupt Flag\nRefer to Time Out section.\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 There is not time-out event on the received buffer #0 1 Time out event active in RX FIFO is not empty #1 SLVSTAIF Slave Start Interrupt Flag\nIt is used to dedicate that the transfer has started in Slave mode with no slave select. 6 1 read-write 0 Slave started transfer no active #0 1 Transfer has started in Slave mode with no slave select. It is automatically cleared by transfer done or writing '1' #1 SLVTOIF Slave Time-out Interrupt Flag\nIf SLVTOIEN (SPI_SSCTL[6]) is set to 1, this bit will be asserted when slave time-out event occur. Software can clear this bit by setting RXFBCLR (SPI_FIFOCTL[0]) or writing 1 to clear this bit. 13 1 read-write 0 Slave time-out does not occur yet #0 1 Slave time-out has occurred #1 SLVTXSKE Slave Mode Transmit Skew Buffer Empty Status\nThis bit indicates the empty status of transmit skew buffer which is used in Slave mode. 15 1 read-write TXCNT Transmit FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 20 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator(Read Only) 2 1 read-only 0 Transmitted data FIFO is not empty in the FIFO mode #0 1 Transmitted data FIFO is empty in the FIFO mode #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 3 1 read-only 0 Transmitted data FIFO is not full in the FIFO mode #0 1 Transmitted data FIFO is full in the FIFO mode #1 TXTHIF Transmit FIFO Threshold Interrupt Flag(Read Only) 10 1 read-only 0 TX valid data counts bigger than TXTH (SPI_FIFOCTL[31:28]) #0 1 TX valid data counts small or equal than TXTH #1 UNITIF Unit Transfer Interrupt Flag Note 2: This bitcan be cleared by writing 1 to it. 7 1 read-write 0 No transaction has been finished since this bit was cleared to 0.\nTransfer is not finished yet #0 1 SPI controller has finished one unit transfer.\nTransfer is done. The interrupt is requested when the UNITIEN(SPI_CTL[17]) bit is enabled #1 WKCLKIF Wake-up by SPI Clock Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_CLK port, this bit is set to 1. This bit can be cleared by writing '1' to it. 31 1 read-write WKSSIF Wake-up by Slave Select Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_SS port, this bit is set to 1. This bit can be cleared by writing '1' to it. 30 1 read-write SPI_TX0 SPI_TX0 SPI Transmit Data FIFO Register 0 0x20 write-only n 0x0 0x0 TX Transmit Data Register (Write Only)\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example, if DWIDTH is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer. If DWIDTH is set to 0x0, the SPI controller will perform a 32-bit transfer.\nNote:\n1. The SPI_TX1 is used only when TWOBIT bit (SPI_CTL[22])is set 1. The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in two-bit mode. SPI_TX0 shall be written first in TWOBIT mode.\nIn FIFO and two-bit mode, the first written into data in SPI_TX0 is the first channel's transmitted data and the second written data in SPI_TX1 is the second channel's transmitted data.\n2.If the SPI controller operates as slave device and FIFO mode is disabled, software must update the transmit data register before setting the GOBUSY bit to 1. 0 32 write-only SPI_TX1 SPI_TX1 SPI Transmit Data FIFO Register 1 0x24 read-write n 0x0 0x0 SPI3 SPI Register Map SPI 0x0 0x0 0x18 registers n 0x20 0x8 registers n 0x38 0x8 registers n 0x50 0x4 registers n SPI_CLKDIV SPI_CLKDIV SPI Clock Divider Register 0x8 read-write n 0x0 0x0 DIVIDER Clock Divider\nThe value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation:\nWhere\n is the SPI peripheral clock source. It is defined in the CLK_SEL2[21:20] in Clock control section (CLK_BA + 0x18). 0 8 read-write SPI_CTL SPI_CTL SPI Control Register 0x0 -1 read-write n 0x0 0x0 CLKPOL Clock Polarity\nNote: Refer to Clock Parity section. 11 1 read-write 0 The default level of SCLK is low #0 1 The default level of SCLK is high #1 DUALDIR Dual I/O Mode Direction Control\nRefer to Dual I/O Mode section. 28 1 read-write 0 Date read in the Dual I/O Mode function #0 1 Data write in the Dual I/O Mode function #1 DUALIOEN Dual I/O Mode EnableBit\nRefer to Dual I/O Mode section. 29 1 read-write 0 Dual I/O Mode function Disabled #0 1 Dual I/O Mode function Enabled #1 DWIDTH Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can be up to 32 bits. 3 5 read-write 0 32 bits are transmitted in one transaction #00000 8 8 bits are transmitted in one transaction #01000 9 9 bits are transmitted in one transaction #01001 10 10 bits are transmitted in one transaction #01010 30 30 bits are transmitted in one transaction #11110 31 31 bits are transmitted in one transaction #11111 FIFOM FIFO Mode EnableBit\nNote: Refer to FIFO Mode section. 21 1 read-write 0 FIFO mode Disabled (in Normal mode) #0 1 FIFO mode Enabled #1 GOBUSY SPI Transfer Control Bit and Busy Status If the FIFO mode is disabled, during the data transfer, this bit keeps the value of '1'. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status. In FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In slave mode, this bit always returns 1 when software reads this register. In master mode, this bit reflects the busy or idle status of SPI. Note: 1.When FIFO mode is disabled, all configurations should be set before writing 1 to the GOBUSY bit in the SPI_CTL register. 2. When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer. 0 1 read-write 0 Writing this bit 0 will stop data transfer if SPI is transferring #0 1 In Master mode, writing 1 to this bit will start the SPI data transfer In Slave mode, writing '1' to this bit indicates that the slave is ready to communicate with a master #1 LSB Send LSB First\nNote: Refer to LSB first section. 10 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH (SPI_CTL[7:3]), is transmitted/received first #0 1 The LSB, bit 0 of the SPI_TX0/1, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of theRX register (SPI_RX0/1) #1 REORDER Byte Reorder Function EnableBit\nNote: The suspend interval is defined in SUSPITV.Refer to Byte Reorder section.\nNote: Byte Suspend is only used in SPI Byte Reorder mode. 19 1 read-write 0 Byte reorderfunction Disabled #0 1 Enable byte reorder function and insert a byte suspend interval among each byte. The setting of DWIDTH must be configured as 00b ( 32 bits/ word) #1 RXNEG Receiveon Negative Edge\nNote: Refer to Edge section. 1 1 read-write 0 The received data is latched on the rising edge of SPI_SCLK #0 1 The received data is latched on the falling edge of SPI_SCLK #1 SLAVE Slave Mode Selection\nNote: Refer to Slave Selection section 18 1 read-write 0 SPI controller set as Master mode #0 1 SPI controller set as Slave mode #1 SUSPITV Suspend Interval (Master Only) 12 4 read-write TWOBIT 2-bit Transfer Mode Enable Bit\nRefer to Two Bit Transfer Mode section\nNote: automatically 22 1 read-write 0 2-bit transfer mode Disabled #0 1 2-bit transfer mode Enabled #1 TXNEG Transmit on Negative Edge\nNote: Refer to Edge section. 2 1 read-write 0 The transmitted data output is changed on the rising edge of SPI_SCLK #0 1 The transmitted data output is changed on the falling edge of SPI_SCLK #1 UNITIEN Unit Transfer Interrupt Enable Bit 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transferinterrupt Enabled #1 WKCLKEN Wake-up by SPI Clock EnableBit\nNote: When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_CLK port. After the system wake-up, this bit must be cleared by user to disable the wake-up requirement. 31 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 WKSSEN Wake-up by Slave Select EnableBit\nNote: The Slave select wake-up function is only available in SPI Slave mode. When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_SS port. After the system wake-up, this bit must be cleared by user to disable the wake-up requirement. 30 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 SPI_FIFOCTL SPI_FIFOCTL SPI FIFO Control Register 0x3C -1 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear Note:This bit is used to clear the receiver counter in FIFO Mode. This bit can be written 1 to clear the receiver counter and this bit will be cleared to 0 automatically after clearing receiving counter. After the clear operation, the flag of RXEMPTY in SPI_STATUS[0] will be set to 1 . 0 1 read-write 0 No clear the received FIFO #0 1 Clear the received FIFO #1 RXOVIEN ReceiveFIFO Overrun Interrupt Enable Bit 4 1 read-write 0 RXFIFO overrun interrupt Disabled #0 1 RX FIFO overrun interrupt Enabled #1 RXTH Received FIFO Threshold\nIf RX valid data counts are greater than RXTH, RXTHIF (SPI_STATUS[8])will be set to 1.. 24 3 read-write RXTHIEN Receive Threshold Interrupt Enable Bit 2 1 read-write 0 RX threshold interrupt Disabled #0 1 RX threshold interrupt Enabled #1 RXTOIEN RX Read Time Out Interrupt Enable Bit 7 1 read-write 0 RXread Time-out Interrupt Disabled #0 1 RX read Time-out Interrupt Enabled #1 TXFBCLR Transmit FIFO Buffer Clear Note:This bit is used to clear the transmit counter in FIFO Mode. This bit can be written 1 to clear the transmitting counter and this bit will be cleared to 0 automatically after clearing transmitting counter. After the clear operation, the flag of TXEMPTY in SPI_STATUS[2] will be set to 1 . 1 1 read-write 0 Not clear the transmitted FIFO #0 1 Clear the transmitted FIFO #1 TXTH Transmit FIFO Threshold\nIf TX valid data counts are smaller than or equal to TXTH, TXTHIF(SPI_STATUS[10])will be set to 1. 28 3 read-write TXTHIEN Transmit Threshold Interrupt Enable Bit 3 1 read-write 0 TX threshold interrupt Disabled #0 1 TX threshold interrupt Enabled #1 SPI_INTERNAL SPI_INTERNAL SPI INTERNAL Register 0x50 read-write n 0x0 0x0 SPI_PDMACTL SPI_PDMACTL SPI PDMA Control Register 0x38 read-write n 0x0 0x0 PDMARST PDMA Reset It is used to reset the SPI PDMA function into default state. Note:It is auto cleared to 0 after the reset function has done. 2 1 read-write 0 After reset PDMA function or in normal operation #0 1 Reset PDMA function #1 RXPDMAEN Receiving PDMA EnableBit Refer to PDMA section for more detail information. Note: Hardware will clear this bit to 0 automatically after PDMA transfer done. In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clock + 4 APB clock. 1 1 read-write 0 Receiver PDMA function Disabled #0 1 Receiver PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit\nRefer to PDMA section for more detailed information.\nSPI_CTLNote:\n1. Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode.\n2. If the 2-bit function is enabled, the requirement timing shall append 18 APB clock based on the above clock period.\nHardware will clear this bit to 0 automatically after PDMA transfer is done. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPI_RX0 SPI_RX0 SPI Receive Data FIFO Register 0 0x10 read-only n 0x0 0x0 RX Receive Data Register (Read Only)\nThe received data can be read on it. If the FIFO bit is set as 1, the user also checks the RXEMPTY, SPI_STATUS[0], to check if there is any more received data or not.\nNote:The SPI_RX1 is used only in TWOBIT bit (SPI_CTL[22])is set 1. The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode. SPI_RX0 shall be read first in TWOBIT mode.\nIn FIFO and two-bit mode, the first read back data in SPI_RX0 is the first channel data and the second read back data in SPI_RX0 is the second channel data. 0 32 read-only SPI_RX1 SPI_RX1 SPI Receive Data FIFO Register 1 0x14 read-write n 0x0 0x0 SPI_SSCTL SPI_SSCTL SPI Slave Select Control Register 0xC -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit (Master Only) 3 1 read-write 0 If this bit is set as 0 , slave select signals are asserted and de-asserted by setting and clearing related bits in SS[1:0] (SPI_CTL[1:0]) #0 1 If this bit is set as 1 , SPI_SS0 and SPI_SS1 signals are generated automatically. It means that device/slave select signal, which is set in SS[1:0] (SPI_CTL[1:0]) is asserted by the SPI controller when transmit/receive is started, and is de-asserted after each transaction is done #1 SLV3WIRE Slave 3-wire Mode Enable Bit This bit is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI when it is set as a slave device. Note 1:Refer to No Slave Select Mode. Note 2: In no slave select signal mode, hardware will set the SSLTRIG (SPI_SSCTL[4]) as 1 automatically. 5 1 read-write 0 The controller is 4-wire bi-direction interface #0 1 The controller is 3-wire bi-direction interface in Slave mode. When this bit is set as 1, the controller start to transmit/receive data after the GOBUSY bit active and the SPI clock input #1 SLVABORT Abort in Slave Mode with No Slave Selected Refer to No Slave Select Mode. Note: It is auto cleared to 0 by hardware when the abort event is active. 8 1 read-write 0 No force the slave abort #0 1 Force the current transfer done in no slave select mode #1 SLVTOCNT Slave Mode Time-out Period\nIn Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled. 20 10 read-write SLVTOIEN Slave Time-out Interrupt Enable Bit\nThis bit is used to enable the slave time-out function in slave mode and there will be an interrupt if slave time-out event occur 6 1 read-write 0 Slave time-out function and interrupt both Disabled #0 1 Slave time-out function and interrupt both Enabled #1 SS Slave SelectionControl (Master Only) If AUTOSS bit (SPI_SSCTL[3]) is cleared, writing 1 to SS[0] (SPI_CTL[0]) bit sets the SPI_SS0 line to an active state and writing 0 sets the line back to inactive state(the same as SPI_CTL[1] for SPI_SS1). Note: 1. This interface can only drive one device/slave at a given time. Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer. 2. SPI_SS0 is also defined as device/slave select input in Slave mode. And that the slave select input must be driven by edge active trigger which level depend on the SSACTPOL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software. 0 2 read-write 0 Both SPI_SS1 and SPI_SS0 are inactive #00 1 SPI_SS1 is inactive, SPI_SS0 is active.\nSPI_SS1 is inactive, SPI_SS0 is active on the duration of transaction #01 2 SPI_SS1 is active, SPI_SS0 is inactive.\nSPI_SS1 is active on the duration of transaction, SPI_SS0 is inactive #10 3 Both SPI_SS1 and SPI_SS0 are active..\nBoth SPI_SS1 and SPI_SS0 are active on the duration of transaction #11 SSACTPOL Slave Selection Active Polarity\nIt defines the active polarity of slave selection signal (SPI_SS[1:0]). 2 1 read-write 0 The SPI_SS slave select signal is active Low #0 1 The SPI_SS slave select signal is active High #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit\nIt is used to enable the interrupt when the transfer has done in slave mode. 16 1 read-write 0 No any interrupt, even there is slave select inactive event #0 1 There is interrupt event when the slave select becomes inactive from active condition. It is used to inform the user to know that the transaction has finished and the slave select into the inactive state #1 SSLTRIG Slave Select Level Trigger Control 4 1 read-write 0 The input slave select signal is edge-trigger #0 1 The slave select signal will be level-trigger. It depends on SSACTPOL to decide the signal is active low or active high #1 SSTAIEN Slave Start Interrupt EnableBit\nRefer to No Slave Select Mode. 9 1 read-write 0 Transfer start interrupt Disabled in no slave select mode #0 1 Transaction start interrupt Enabled in no slave select mode. It is cleared when the current transfer done or the SLVSTAIF bit cleared (write 1 clear) #1 SPI_STATUS SPI_STATUS SPI Status Register 0x4 -1 read-write n 0x0 0x0 LTRIGF Level Trigger Accomplish Flag(Read Only)\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only. As the software sets the GOBUSY bit to 1, the LTRIGF will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit is unmeaning. 4 1 read-only 0 The transferred bit length of one transaction does not meet the specified requirement #0 1 The transferred bit length meets the specified requirement which defined in DWIDTH #1 RXCNT Receive FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 16 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator(Read Only) 0 1 read-only 0 Received data FIFO is not empty in the FIFO mode #0 1 Received data FIFO is empty in the FIFO mode #1 RXFULL Receive FIFO Buffer Full Indicator(Read Only) 1 1 read-only 0 Received data FIFO is not full in FIFO mode #0 1 Received data FIFO is full in the FIFO mode #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nNote 1: If SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will be dropped.\nNote 2: This bit will be cleared by writing 1 to it. 9 1 read-write 0 No FIFO over run #0 1 Receive FIFO over run #1 RXTHIF RX FIFO Threshold Interrupt Flag(Read Only) 8 1 read-only 0 RX valid data counts small or equal than RXTH (SPI_FIFOCTL[27:24]) #0 1 RX valid data counts bigger than RXTH #1 RXTOIF Receive Time-outInterrupt Flag\nRefer to Time Out section.\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 There is not time-out event on the received buffer #0 1 Time out event active in RX FIFO is not empty #1 SLVSTAIF Slave Start Interrupt Flag\nIt is used to dedicate that the transfer has started in Slave mode with no slave select. 6 1 read-write 0 Slave started transfer no active #0 1 Transfer has started in Slave mode with no slave select. It is automatically cleared by transfer done or writing '1' #1 SLVTOIF Slave Time-out Interrupt Flag\nIf SLVTOIEN (SPI_SSCTL[6]) is set to 1, this bit will be asserted when slave time-out event occur. Software can clear this bit by setting RXFBCLR (SPI_FIFOCTL[0]) or writing 1 to clear this bit. 13 1 read-write 0 Slave time-out does not occur yet #0 1 Slave time-out has occurred #1 SLVTXSKE Slave Mode Transmit Skew Buffer Empty Status\nThis bit indicates the empty status of transmit skew buffer which is used in Slave mode. 15 1 read-write TXCNT Transmit FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 20 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator(Read Only) 2 1 read-only 0 Transmitted data FIFO is not empty in the FIFO mode #0 1 Transmitted data FIFO is empty in the FIFO mode #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 3 1 read-only 0 Transmitted data FIFO is not full in the FIFO mode #0 1 Transmitted data FIFO is full in the FIFO mode #1 TXTHIF Transmit FIFO Threshold Interrupt Flag(Read Only) 10 1 read-only 0 TX valid data counts bigger than TXTH (SPI_FIFOCTL[31:28]) #0 1 TX valid data counts small or equal than TXTH #1 UNITIF Unit Transfer Interrupt Flag Note 2: This bitcan be cleared by writing 1 to it. 7 1 read-write 0 No transaction has been finished since this bit was cleared to 0.\nTransfer is not finished yet #0 1 SPI controller has finished one unit transfer.\nTransfer is done. The interrupt is requested when the UNITIEN(SPI_CTL[17]) bit is enabled #1 WKCLKIF Wake-up by SPI Clock Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_CLK port, this bit is set to 1. This bit can be cleared by writing '1' to it. 31 1 read-write WKSSIF Wake-up by Slave Select Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_SS port, this bit is set to 1. This bit can be cleared by writing '1' to it. 30 1 read-write SPI_TX0 SPI_TX0 SPI Transmit Data FIFO Register 0 0x20 write-only n 0x0 0x0 TX Transmit Data Register (Write Only)\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example, if DWIDTH is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer. If DWIDTH is set to 0x0, the SPI controller will perform a 32-bit transfer.\nNote:\n1. The SPI_TX1 is used only when TWOBIT bit (SPI_CTL[22])is set 1. The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in two-bit mode. SPI_TX0 shall be written first in TWOBIT mode.\nIn FIFO and two-bit mode, the first written into data in SPI_TX0 is the first channel's transmitted data and the second written data in SPI_TX1 is the second channel's transmitted data.\n2.If the SPI controller operates as slave device and FIFO mode is disabled, software must update the transmit data register before setting the GOBUSY bit to 1. 0 32 write-only SPI_TX1 SPI_TX1 SPI Transmit Data FIFO Register 1 0x24 read-write n 0x0 0x0 SYS SYS Register Map SYS 0x0 0x0 0x10 registers n 0x100 0x4 registers n 0x120 0x4 registers n 0x20 0x4 registers n 0x28 0x4 registers n 0x30 0x24 registers n 0x58 0x4 registers n 0x60 0x18 registers n 0x7C 0x10 registers n 0x90 0xC registers n 0xA0 0xC registers n BATDCTL SYS_BATDCTL Battery Voltage Divider Control Register 0x74 read-write n 0x0 0x0 BATDIV2EN Battery Voltageg Divide 2 Enable Bit\nThis bit is used to enable/disable battery voltageg divider function. 0 1 read-write 0 Battery voltageg divide 2 function Disabled (default) #0 1 Battery voltageg divide 2 function Enabled #1 BODCTL SYS_BODCTL Brown-out Detector Controller Register 0x64 -1 read-write n 0x0 0x0 BODDGSEL Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 24 3 read-write 0 BOD output is sampled by RC10K clock #000 1 4 system clock (HCLK) #001 2 8 system clock (HCLK) #010 3 16 system clock (HCLK) #011 4 32 system clock (HCLK) #100 5 64 system clock (HCLK) #101 6 128 system clock (HCLK) #110 7 256 system clock (HCLK) #111 BODEN Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (CONFIG0 []).This Brown-out Detecto only valid in Normal Mode.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: LIRC must be enabled before enable BOD. 0 1 read-write 0 Brown-out Detector function Disabled in Normal mode #0 1 Brown-out Detector function Enabled in Normal mode #1 BODIE BOD Interrupt Enable Control(Write Protect)\nNote1: While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 Interrupt does not issue when BOD occurs in Normal Mode #0 1 Interrupt issues when BOD occursi in Normal Mode #1 BODIF Brown-out DetectorInterrupt Flag\nNote: Write 1 to clear this bit to 0. 4 1 read-write 0 Brown-out Detector does not detect any voltage drift at VDD down through or up through the target detected voltage after interrupt is enabled #0 1 When Brown-out Detectordetects the VDD is dropped down through the target detected voltage or the VDD is raised up through the target detected voltage, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled #1 BODOUT Brown-out DetectorOutuput Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled , this bit always responds 0.\nNote: This bit is ready-only. 6 1 read-write 0 Brown-out Detector output status is 0 #0 1 Brown-out Detector output status is 1 #1 BODREN Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBOV(CONFIG0[]) bit.\nNote1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 Brown-out RESET function Disabled in Normal Mode #0 1 Brown-out RESET function Enabled in Normal Mode #1 BODVL Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0[]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 12 4 read-write 0 Brown-Out Detector threshold voltageis 1.7V #0000 1 Brown-Out Detector threshold voltageis 1.8V #0001 2 Brown-Out Detector threshold voltageis 1.9V #0010 3 Brown-Out Detector threshold voltageis 2.0V #0011 4 Brown-Out Detector threshold voltageis 2.1V #0100 5 Brown-Out Detector threshold voltageis 2.2V #0101 6 Brown-Out Detector threshold voltageis 2.3V #0110 7 Brown-Out Detector threshold voltageis 2.4V #0111 8 Brown-Out Detector threshold voltageis 2.5V #1000 9 Brown-Out Detector threshold voltageis 2.6V #1001 10 Brown-Out Detector threshold voltageis 2.7V #1010 11 Brown-Out Detector threshold voltageis 2.8V #1011 12 Brown-Out Detector threshold voltageis 2.9V #1100 13 Brown-Out Detector threshold voltageis 3.0V #1101 14 Brown-Out Detector threshold voltageis 3.1V #1110 15 Reserved #1111 LPBOD20TRIM Low Power BOD 2.0 TRIM Value(Write Protect) This value is used to control BOD20 detect voltage level in power-down mode, nominal 2.0 V. Higher trim value, higher detection voltage. Note: These bits are write protected. Refer to the SYS_REGLCTL register. 16 4 read-write LPBOD25TRIM Low Power BOD 2.5 TRIM Value(Write Protect) This value is used to control LPBOD25 detect voltage level in power-down mode, nominal 2.5 V. Higher trim value, higher detection voltage. Note: These bits are write protected. Refer to the SYS_REGLCTL register. 20 4 read-write LPBODEN Low Power Brown-out Detector Enable Bit (Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: LIRC must be enabled before enable BOD. 8 1 read-write 0 Low Power Brown-out Detector function Disabled in Power-down mode #0 1 Low Power Brown-out Detector function Enabled in Power-down mode #1 LPBODIE Low Power BOD Interrupt Enable Control(Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: While the LPBOD function is enabled (LPBODEN high) and LPBOD interrupt function is enabled (LPBODIEhigh), LPBOD will assert an interrupt if BODOUT is high. Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 10 1 read-write 0 Interrupt does not issue when LPBOD occurs in Power-down mode #0 1 Interrupt issues when LPBOD occurs in Power-down mode #1 LPBODREN Low Power Brown-out Reset Enable Bit (Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: While the Low power Brown-out Detector function is enabled (LPBODEN high) and LPBOD reset function is enabled (LPBODREN high), LPBOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 11 1 read-write 0 Low power Brown-out dector RESET function Disabled in Power-down mode #0 1 Low Power Brown-out dector RESET function Enabled in Power-down mode #1 LPBODVL Low Power Brown-out Detector Threshold Voltage Selection(Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register. 9 1 read-write 0 Low Power Brown-Out Detector threshold voltageis 2.0V in Power-down mode #0 1 Low Power Brown-Out Detector threshold voltageis 2.5V in Power-down mode #1 LVRDGSEL LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 28 3 read-write 0 Without de-glitch function #000 1 4 system clock (HCLK) #001 2 8 system clock (HCLK) #010 3 16 system clock (HCLK) #011 4 32 system clock (HCLK) #100 5 64 system clock (HCLK) #101 6 128 system clock (HCLK) #110 7 256 system clock (HCLK) #111 LVREN Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote3: LIRC must be enabled before enable LVR. 7 1 read-write 0 Low Voltage Reset function Disabled #0 1 Low Voltage Reset function Enabled #1 BODSTS SYS_BODSTS Brown-out Detector Status Register 0x68 read-only n 0x0 0x0 GPA_MFPH SYS_GPA_MFPH GPIOA High Byte Multiple Function Control Register 0x34 read-write n 0x0 0x0 PA10MFP PA.10 Multi-function Pin Selection 8 4 read-write 0 GPIOA[10] #0000 1 I2C1 data input/output pin #0001 2 Timer2 external counter input #0010 3 SmartCard0 power pin #0011 4 SPI21stMISO (Master In, Slave Out) pin #0100 5 Timer2 toggle output #0101 PA11MFP PA.11 Multi-function Pin Selection 12 4 read-write 0 GPIOA[11] #0000 1 I2C1 clock pin #0001 2 Timer3 external counter input #0010 3 SmartCard0 reset pin #0011 4 SPI21stMOSI (Master Out, Slave In) pin #0100 5 Timer3 toggle output #0101 PA12MFP PA.12 Multi-function Pin Selection 16 4 read-write 0 GPIOA[12] #0000 1 PWM0 channel0 output/capture input #0001 3 Timer0 capture input #0011 5 I2C0 data input/output pin #0101 PA13MFP PA.13 Multi-function Pin Selection 20 4 read-write 0 GPIOA[13] #0000 1 PWM0 channel1 output/capture input #0001 3 Timer1 capture input #0011 5 I2C0 clock pin #0101 PA14MFP PA.14 Multi-function Pin Selection 24 4 read-write 0 GPIOA[14] #0000 1 PWM0 channel2 output/capture input #0001 2 I2C1 data input/output pin #0010 3 I2C1 data input/output pin #0011 5 Timer2 external counter input #0101 6 Data receiver input pin for UART0 #0110 7 Timer2 toggle output #0111 PA15MFP PA.15 Multi-function Pin Selection 28 4 read-write 0 GPIOA[15] #0000 1 PWM0 channel3 output/capture input #0001 2 I2C1 clock pin #0010 3 Timer1 capture input #0011 4 SmartCard0 power pin #0100 6 Data transmitter output pin for UART0 #0110 7 Timer3 toggle output #0111 PA8MFP PA.8 Multi-function Pin Selection 0 4 read-write 0 GPIOA[8] #0000 1 I2C0 data input/output pin #0001 2 Timer0 external counter input #0010 3 SmartCard0 clock pin #0011 4 SPI2 slave select pin #0100 5 Timer0 toggle output #0101 6 UART0 Clear to Send input pin #0110 PA9MFP PA.9 Multi-function Pin Selection 4 4 read-write 0 GPIOA[9] #0000 1 I2C0 clock pin #0001 2 Timer1 external counter input #0010 3 SmartCard0 data pin #0011 4 SPI0 serial clock pin #0100 5 Timer1 toggle output #0101 6 UART1 Request to Send output pin #0110 7 Snooper pin #0111 GPA_MFPL SYS_GPA_MFPL GPIOA Low Byte Multiple Function Control Register 0x30 read-write n 0x0 0x0 PA0MFP PA.0 Multi-function Pin Selection 0 4 read-write 0 GPIOA[0] #0000 1 ADC analog input0 #0001 2 Comparator1 P-end input #0010 3 Timer0 capture input #0011 5 PWM0 channel2 output/capture input #0101 PA1MFP PA.1 Multi-function Pin Selection 4 4 read-write 0 GPIOA[1] #0000 1 ADC analog input1 #0001 2 Comparator1 N-end input #0010 6 SPI0 2ndMISO (Master In, Slave Out) pin #0110 PA2MFP PA.2 Multi-function Pin Selection 8 4 read-write 0 GPIOA[2] #0000 1 ADC analog input2 #0001 5 Data receiver input pin for UART1 #0101 PA3MFP PA.3 Multi-function Pin Selection 12 4 read-write 0 GPIOA[3] #0000 1 ADC analog input3 #0001 5 Data transmitter output pin for UART1 #0101 6 SPI31stMOSI (Master Out, Slave In) pin #0110 PA4MFP PA.4 Multi-function Pin Selection 16 4 read-write 0 GPIOA[4] #0000 1 ADC analog input4 #0001 5 I2C0 data input/output pin #0101 6 SPI31stMISO (Master In, Slave Out) pin #0110 PA5MFP PA.5 Multi-function Pin Selection 20 4 read-write 0 GPIOA[5] #0000 1 ADC analog input5 #0001 5 I2C0 clock pin #0101 6 SPI3 serial clock pin #0110 PA6MFP PA.6 Multi-function Pin Selection 24 4 read-write 0 GPIOA[6] #0000 1 ADC analog input6 #0001 2 Comparator1 output #0010 3 Timer3 capture input #0011 4 Timer3 external counter input #0100 5 PWM0 channel3 output/capture input #0101 7 Timer3 toggle output #0111 GPB_MFPH SYS_GPB_MFPH GPIOB High Byte Multiple Function Control Register 0x3C read-write n 0x0 0x0 PB10MFP PB.10 Multi-function Pin Selection 8 4 read-write 0 GPIOB[10] #0000 1 SPI0 1stMOSI (Master Out, Slave In) pin #0001 4 Timer2 toggle output #0100 5 SPI0 slave select pin #0101 PB11MFP PB.11 Multi-function Pin Selection 12 4 read-write 0 GPIOB[11] #0000 1 PWM0 channel4 output/capture input #0001 2 Timer3 external counter input #0010 4 Timer3 toggle output #0100 5 SPI0 1stMISO (Master In, Slave Out) pin #0101 PB13MFP PB.13 Multi-function Pin Selection 20 4 read-write 0 GPIOB[13] #0000 3 SPI22ndMISO (Master In, Slave Out) pin #0011 7 Snooper pin #0111 PB14MFP PB.14 Multi-function Pin Selection 24 4 read-write 0 GPIOB[14] #0000 1 External interrupt0 input pin #0001 3 SPI22ndMOSI (Master Out, Slave In) pin #0011 4 SPI2 slave select pin #0100 PB15MFP PB.15 Multi-function Pin Selection 28 4 read-write 0 GPIOB[15] #0000 1 External interrupt1 input pin #0001 3 Snooper pin #0011 4 SmartCard1 card detect pin #0100 PB8MFP PB.8 Multi-function Pin Selection 0 4 read-write 0 GPIOB[8] #0000 1 ADC external trigger input #0001 2 Timer0 external counter input #0010 3 External interrupt0 input pin #0011 4 Timer0 toggle output #0100 7 Snooper pin #0111 PB9MFP PB.9 Multi-function Pin Selection 4 4 read-write 0 GPIOB[9] #0000 1 SPI1 slave select pin #0001 2 Timer2 external counter input #0010 4 Timer2 toggle output #0100 5 External interrupt0 input pin #0101 GPB_MFPL SYS_GPB_MFPL GPIOB Low Byte Multiple Function Control Register 0x38 read-write n 0x0 0x0 PB0MFP PB.0 Multi-function Pin Selection 0 4 read-write 0 GPIOB[0] #0000 1 Data receiver input pin for UART0 #0001 3 SPI11stMOSI (Master Out, Slave In) pin #0011 PB1MFP PB.1 Multi-function Pin Selection 4 4 read-write 0 GPIOB[1] #0000 1 Data transmitter output pin for UART0 #0001 3 SPI11stMISO (Master In, Slave Out) pin #0011 PB2MFP PB.2 Multi-function Pin Selection 8 4 read-write 0 GPIOB[2] #0000 1 UART0 Request to Send output pin #0001 3 SPI1 serial clock pin #0011 4 Frequency Divider output pin #0100 PB3MFP PB.3 Multi-function Pin Selection 12 4 read-write 0 GPIOB[3] #0000 1 UART0 Clear to Send input pin #0001 3 SPI1 slave select pin #0011 4 SmartCard1 card detect pin #0100 PB4MFP PB.4 Multi-function Pin Selection 16 4 read-write 0 GPIOB[4] #0000 1 Data receiver input pin for UART1 #0001 3 SmartCard0 card detect pin #0011 4 SPI2 slave select pin #0100 6 RTC 1Hz output #0110 PB5MFP PB.5 Multi-function Pin Selection 20 4 read-write 0 GPIOB[5] #0000 1 Data transmitter output pin for UART1 #0001 3 SmartCard0 reset pin #0011 4 SPI2 serial clock pin #0100 PB6MFP PB.6 Multi-function Pin Selection 24 4 read-write 0 GPIOB[6] #0000 1 UART1 Request to Send output pin #0001 4 SPI21stMISO (Master In, Slave Out) pin #0100 PB7MFP PB.7 Multi-function Pin Selection 28 4 read-write 0 GPIOB[7] #0000 1 UART1 Clear to Send input pin #0001 GPC_MFPH SYS_GPC_MFPH GPIOC High Byte Multiple Function Control Register 0x44 read-write n 0x0 0x0 PC10MFP PC.10 Multi-function Pin Selection 8 4 read-write 0 GPIOC[10] #0000 1 SPI0 1stMISO (Master In, Slave Out) pin #0001 5 Data receiver input pin for UART1 #0101 PC11MFP PC.11 Multi-function Pin Selection 12 4 read-write 0 GPIOC[11] #0000 1 SPI1 1stMOSI (Master Out, Slave In) pin #0001 5 Data transmitter output pin for UART1 #0101 PC14MFP PC.14 Multi-function Pin Selection 24 4 read-write 0 GPIOC[14] #0000 1 UART0 Clear to Send input pin #0001 PC15MFP PC.15 Multi-function Pin Selection 28 4 read-write 0 GPIOC[15] #0000 1 UART1 Request to Send output pin #0001 3 Timer0 capture input #0011 PC8MFP PC.8 Multi-function Pin Selection 0 4 read-write 0 GPIOC[8] #0000 1 SPI1 slave select pin #0001 5 I2C1 data input/output pin #0101 PC9MFP PC.9 Multi-function Pin Selection 4 4 read-write 0 GPIOC[9] #0000 1 SPI1 serial clock pin #0001 5 I2C1 clock pin #0101 GPC_MFPL SYS_GPC_MFPL GPIOC Low Byte Multiple Function Control Register 0x40 read-write n 0x0 0x0 PC0MFP PC.0 Multi-function Pin Selection 0 4 read-write 0 GPIOC[0] #0000 1 SPI0 slave select pin #0001 4 SmartCard1 clock pin #0100 5 PWM0 break1 input 1 #0101 PC1MFP PC.1 Multi-function Pin Selection 4 4 read-write 0 GPIOC[1] #0000 1 SPI0 serial clock pin #0001 4 SmartCard1 data pin #0100 5 PWM0 break1 input 0 #0101 PC2MFP PC.2 Multi-function Pin Selection 8 4 read-write 0 GPIOC[2] #0000 1 SPI0 1st MISO (Master In, Slave Out) pin #0001 4 SmartCard1 power pin #0100 5 PWM0 break0 input 1 #0101 PC3MFP PC.3 Multi-function Pin Selection 12 4 read-write 0 GPIOC[3] #0000 1 SPI0 1stMOSI (Master Out, Slave In) pin #0001 4 SmartCard1 reset pin #0100 5 PWM0 break0 input 0 #0101 PC6MFP PC.6 Pin Fuction Selection 24 4 read-write 0 GPIOC[6] #0000 1 Data receiver input pin for UART1 #0001 3 Timer0 capture input #0011 4 SmartCard1 card detect pin #0100 5 PWM0 channel0 output/capture input #0101 PC7MFP PC.7 Multi-function Pin Selection 28 4 read-write 0 GPIOC[7] #0000 1 Data transmitter output pin for UART1 #0001 2 ADC analog input7 #0010 3 Timer1 capture input #0011 5 PWM0 channel1 output/capture input #0101 GPD_MFPH SYS_GPD_MFPH GPIOD High Byte Multiple Function Control Register 0x4C read-write n 0x0 0x0 PD14MFP PD.14 Multi-function Pin Selection 24 4 read-write 0 GPIOD[14] #0000 1 SPI0 2ndMOSI (Master Out, Slave In) pin #0001 PD15MFP PD.15 Multi-function Pin Selection 28 4 read-write 0 GPIOD[15] #0000 1 SPI0 2ndMISO (Master In, Slave Out) pin #0001 100 SmartCard1 clock pin #0100 GPD_MFPL SYS_GPD_MFPL GPIOD Low Byte Multiple Function Control Register 0x48 read-write n 0x0 0x0 PD6MFP PD.6 Multi-function Pin Selection 24 4 read-write 0 GPIOD[6] #0000 3 SPI12ndMOSI (Master Out, Slave In) pin #0011 4 SmartCard1 reset pin #0100 PD7MFP PD.7 Multi-function Pin Selection 28 4 read-write 0 GPIOD[7] #0000 3 SPI12ndMISO (Master In, Slave Out) pin #0011 4 SmartCard1 power pin #0100 GPE_MFPL SYS_GPE_MFPL GPIOE Low Byte Multiple Function Control Register 0x50 read-write n 0x0 0x0 PE5MFP PE.5 Multi-function Pin Selection 20 4 read-write 0 GPIOE[5] #0000 1 PWM0 channel5 output/capture input #0001 6 RTC 1Hz output #0110 GPF_MFPL SYS_GPF_MFPL GPIOF Low Byte Multiple Function Control Register 0x58 -1 read-write n 0x0 0x0 PF0MFP PF.0 Multi-function Pin Selection 0 4 read-write 0 GPIOF[1].\nSerial wired debugger data pin #0000 5 External interrupt0 input pin #0101 PF1MFP PF.1 Multi-function Pin Selection 4 4 read-write 0 GPIOF[1].\nSerial wired debugger clock pin #0000 4 Frequency Divider output pin #0100 5 External interrupt1 input pin #0101 PF2MFP PF.2 Multi-function Pin Selection 8 4 read-write 0 GPIOF[2].\nExternal 4~36 MHz (high speed) crystal output pin #0000 PF3MFP PF.3 Multi-function Pin Selection 12 4 read-write 0 GPIOF[3].\nExternal 4~36 MHz (high speed) crystal input pin #0000 PF6MFP PF.6 Multi-function Pin Selection 24 4 read-write 0 GPIOF[6].\nExternal 32.768 kHz crystal output pin(default) #0000 1 I2C1 data input/output pin #0001 PF7MFP PF.7 Multi-function Pin Selection 28 4 read-write 0 GPIOF[7].\nExternal 32.768 kHz crystal input pin(default) #0000 1 I2C1 clock pin #0001 3 SmartCard0 card detect pin #0011 IPRST1 SYS_IPRST1 Peripheral Reset Control Resister1 0x8 read-write n 0x0 0x0 CHIPRST Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\nAbout the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2\nNote:This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Chip normal operation #0 1 Chip one-shot reset #1 CPURST Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Processor core normal operation #0 1 Processor core one-shot reset #1 PDMARST PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 PDMA controller normal operation #0 1 PDMA controllerreset #1 IPRST2 SYS_IPRST2 Peripheral Reset Control Resister2 0xC read-write n 0x0 0x0 ACMP01RST Comparator Controller Reset 22 1 read-write 0 Comparatormodule normal operation #0 1 Comparatormodule reset #1 ADCRST ADC Controller Reset 28 1 read-write 0 ADC module normal operation #0 1 ADC module reset #1 DSRCRST DSRC Controller Reset 7 1 read-write 0 DSRCmodule normal operation #0 1 DSRCmodule reset #1 GPIORST GPIO Controller Reset 1 1 read-write 0 GPIO module normal operation #0 1 GPIO module reset #1 I2C0RST I2C0 Controller Reset 8 1 read-write 0 I2C0 module normal operation #0 1 I2C0 module reset #1 I2C1RST I2C1 Controller Reset 9 1 read-write 0 I2C1 module normal operation #0 1 I2C1 module reset #1 PWM0RST PWM0 Controller Reset 20 1 read-write 0 PWM0 module normal operation #0 1 PWM0 module reset #1 SC0RST SmartCard0 Controller Reset 30 1 read-write 0 SmartCardmodule normal operation #0 1 SmartCardmodule reset #1 SC1RST SmartCard1 Controller Reset 31 1 read-write 0 SmartCardmodule normal operation #0 1 SmartCardmodule reset #1 SPI0RST SPI0 Controller Reset 12 1 read-write 0 SPI0 module normal operation #0 1 SPI0 module reset #1 SPI1RST SPI1 Controller Reset 13 1 read-write 0 SPI1 module normal operation #0 1 SPI1 modulereset #1 SPI2RST SPI2 Controller Reset 14 1 read-write 0 SPI2module normal operation #0 1 SPI2modulereset #1 SPI3RST SPI3 Controller Reset 15 1 read-write 0 SPI3module normal operation #0 1 SPI3modulereset #1 TMR0RST Timer0 Controller Reset 2 1 read-write 0 Timer0 module normal operation #0 1 Timer0 module reset #1 TMR1RST Timer1 Controller Reset 3 1 read-write 0 Timer1 module normal operation #0 1 Timer1 module reset #1 TMR2RST Timer2 Controller Reset 4 1 read-write 0 Timer2 module normal operation #0 1 Timer2 module reset #1 TMR3RST Timer3 Controller Reset 5 1 read-write 0 Timer3 module normal operation #0 1 Timer3 module reset #1 UART0RST UART0 Controller Reset 16 1 read-write 0 UART0 module normal operation #0 1 UART0 module reset #1 UART1RST UART1 Controller Reset 17 1 read-write 0 UART1 module normal operation #0 1 UART1 module reset #1 IVREFCTL SYS_IVREFCTL Internal Voltage Reference Control Register 0x6C -1 read-write n 0x0 0x0 BGPEN Band-gap Enable Control(Write Protect)\nBand-gap is the reference voltage of internal reference voltage. User must enable band-gap if want to enable internal 1.5, 1.8V or 2.5V reference voltage.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Band-gap Disabled #0 1 Band-gap Enabled #1 EXTMODE Regulator External Mode(Write Protect)\nUsers can output regulator output voltage in VREF pin if EXT_MODE is high.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 No connection with external VREF pin #0 1 Connet to external VREF pin. Connect a 1uF to 10uF capacitor to AVSS will let internal voltage reference be more stable #1 REGEN Regulator Enable Control(Write Protect)\nEnable internal 1.5, 1.8V or 2.5V reference voltage.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Regulator Disabled #0 1 Regulator Enabled #1 SEL25 Regulator Output Voltage Selection(Write Protect)\nSelect internal reference voltage level.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 2 read-write 0 1.5V #00 1 1.8V #01 2 2.5V #10 3 2.5V #11 VREFTRIM Internal Voltage Reference Trim(Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 8 4 read-write LDOCTL SYS_LDOCTL LDO Control Register 0x70 -1 read-write n 0x0 0x0 FASTWK Fast Wake-up Control Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Fast Wake-up from Power-Down mode Disabled #0 1 Fast Wake-up from Power-Down mode Enabled #1 FMCLVEN Flash Memory Low Voltage Mode Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 Flash memory low voltage(1.2V) mode Enabled #0 1 Flash memory low voltage(1.2V) mode Disabled #1 LDOLVL LDO Output Voltage Select(Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 2 read-write 0 1.2V #00 1 1.6V #01 2 1.8V #10 3 1.8V #11 LPRMEN Low-power Run Mode Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 Low-Power runmode Enabled #0 1 Low-Power runmode Disabled #1 MRCTCTL SYS_MRCTCTL MIRC Trim Control Register 0xA0 read-write n 0x0 0x0 CESTOPEN Clock Error Stop Enable Bit\nThis bit is used to control if stop the MIRC trim operation when 32.768 kHz clock error is detected.\nIf set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_MIRCTISTS[2]) would be set high and MIRC trim operation was stopped. If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_MIRCTISTS[2]) would be set high and MIRC trim operation is continuously. 8 1 read-write 0 The trim operation is keep going if clock is inaccuracy #0 1 The trim operation is stopped if clock is inaccuracy #1 FREQSEL Trim Frequency Selection\nThis field indicates the target frequency of 4 MHz internal medium speed RC oscillator (MIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN (SYS_MIRCTCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.\nNote:MIRC auto trim cannot work normally inPower downn mode. These bits must be cleared before entering Power-down mode. 0 2 read-write 0 Disable MIRC auto trim function #00 1 Reserved #01 2 Enable MIRC auto trim function and trim HIRC to 4 MHz #10 3 Reserved #11 LOOPSEL Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock. 4 2 read-write 0 Trim value calculation is based on average difference in 4 32.768 kHz clock #00 1 Trim value calculation is based on average difference in 8 32.768 kHz clock #01 2 Trim value calculation is based on average difference in 16 32.768 kHz clock #10 3 Trim value calculation is based on average difference in 32 32.768 kHz clock #11 RETRYCNT Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the MIRC trim value before the frequency of MIRC locked.\nOnce the MIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of MIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_MIRCTCTL[1:0]) will be cleared to 00. 6 2 read-write 0 Trim retry count limitation is 64 loops #00 1 Trim retry count limitation is 128 loops #01 2 Trim retry count limitation is 256 loops #10 3 Trim retry count limitation is 512 loops #11 MRCTIEN SYS_MRCTIEN MIRC Trim Interrupt Enable Register 0xA4 read-write n 0x0 0x0 CLKEIEN Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_MIRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 2 1 read-write 0 Disable CLKERRIF(SYS_MIRCTSTS[2]) status to trigger an interrupt to CPU #0 1 Enable CLKERRIF(SYS_MIRCTSTS[2]) status to trigger an interrupt to CPU #1 TFAILIEN Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while MIRC trim value update limitation count reached and MIRC frequency still not locked on target frequency set by FREQSEL(SYS_MIRCTCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_MIRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached. 1 1 read-write 0 Disable TFAILIF(SYS_MIRCTSTS[1]) status to trigger an interrupt to CPU #0 1 Enable TFAILIF(SYS_MIRCTSTS[1]) status to trigger an interrupt to CPU #1 MRCTISTS SYS_MRCTISTS MIRC Trim Interrupt Status Register 0xA8 read-write n 0x0 0x0 CLKERRIF Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 4 MHz internal medium speed RC oscillator (MIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_MIRCTCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_MIRCTCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_MIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0. 2 1 read-write 0 Clock frequency is accuracy #0 1 Clock frequency is inaccuracy #1 FREQLOCK MIRC Frequency Lock Status\nThis bit indicates the MIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt. 0 1 read-write 0 The internal medium-speed oscillator frequency doesn't lock at 4 MHz yet #0 1 The internal medium-speed oscillator frequency locked at 4 MHz #1 TFAILIF Trim Failure Interrupt Status\nThis bit indicates that MIRC trim value update limitation count reached and the MIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_MIRCTCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_MIRCTIEN[1]) is high, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached. Write 1 to clear this to 0. 1 1 read-write 0 Trim value update limitation count does not reach #0 1 Trim value update limitation count reached and MIRC frequency still not locked #1 PDID SYS_PDID Part Device Identification Number Register 0x0 -1 read-only n 0x0 0x0 PDID Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used. 0 32 read-only PORCTL SYS_PORCTL Power-on-Reset Controller Register 0x60 read-write n 0x0 0x0 POROFF Power-on Reset Enable Bit (Write Protect)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will be active again when this field is set to another value or chip is reset by other reset source, including:\nnRESET, Watchdog, BOD reset, ICE reset command and the software-chip reset function.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register. 0 16 read-write RC0TCTL SYS_RC0TCTL HIRC0 Trim Control Register 0x80 read-write n 0x0 0x0 CESTOPEN Clock Error Stop Enable Bit\nThis bit is used to control if stop the HIRC0 trim operation when 32.768 kHz clock error is detected.\nIf set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC0TISTS[2]) would be set high and HIRC0 trim operation was stopped. If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC0TISTS[2]) would be set high and HIRC0 trim operation is continuously. 8 1 read-write 0 The trim operation is keep going if clock is inaccuracy #0 1 The trim operation is stopped if clock is inaccuracy #1 FREQSEL Trim Frequency Selection\nThis field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC0) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN (SYS_IRC0TCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 000 automatically.\nNote: HIRC0 auto trim cannot work normally inPower-down mode. These bits must be cleared before entering Power-down mode. 0 3 read-write 0 Disable HIRC0 auto trim function #000 1 Enable HIRC0 auto trim function and trim HIRC to 11.0592 MHz #001 2 Enable HIRC0 auto trim function and trim HIRC to 12 MHz #010 3 Enable HIRC0 auto trim function and trim HIRC to 12.288 MHz #011 4 Enable HIRC0 auto trim function and trim HIRC to 16 MHz #100 LOOPSEL Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock. 4 2 read-write 0 Trim value calculation is based on average difference in 4 32.768 kHz clock #00 1 Trim value calculation is based on average difference in 8 32.768 kHz clock #01 2 Trim value calculation is based on average difference in 16 32.768 kHz clock #10 3 Trim value calculation is based on average difference in 32 32.768 kHz clock #11 RETRYCNT Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC0 trim value before the frequency of HIRC0 locked.\nOnce the HIRC0 locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC0 still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_IRC0TCTL[1:0]) will be cleared to 00. 6 2 read-write 0 Trim retry count limitation is 64 loops #00 1 Trim retry count limitation is 128 loops #01 2 Trim retry count limitation is 256 loops #10 3 Trim retry count limitation is 512 loops #11 RC0TIEN SYS_RC0TIEN HIRC0 Trim Interrupt Enable Register 0x84 read-write n 0x0 0x0 CLKEIEN Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRC0TSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 2 1 read-write 0 Disable CLKERRIF(SYS_IRC0TSTS[2]) status to trigger an interrupt to CPU #0 1 Enable CLKERRIF(SYS_IRC0TSTS[2]) status to trigger an interrupt to CPU #1 TFAILIEN Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC0 trim value update limitation count reached and HIRC0 frequency still not locked on target frequency set by FREQSEL(SYS_IRC0TCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_IRC0TSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached. 1 1 read-write 0 Disable TFAILIF(SYS_IRC0TSTS[1]) status to trigger an interrupt to CPU #0 1 Enable TFAILIF(SYS_IRC0TSTS[1]) status to trigger an interrupt to CPU #1 RC0TISTS SYS_RC0TISTS HIRC0 Trim Interrupt Status Register 0x88 read-write n 0x0 0x0 CLKERRIF Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal high speed RC oscillator (HIRC0) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRC0TCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRC0TCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRC0TIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0. 2 1 read-write 0 Clock frequency is accuracy #0 1 Clock frequency is inaccuracy #1 FREQLOCK HIRC0 Frequency Lock Status\nThis bit indicates the HIRC0 frequency is locked.\nThis is a status bit and doesn't trigger any interrupt. 0 1 read-write 0 The internal high-speed oscillator frequency doesn't lock at frequency set by FREQSEL (SYS_IRC0TCTL[2:0]) #0 1 The internal high-speed oscillator frequency locked at frequency set by FREQSEL (SYS_IRC0TCTL[2:0]) #1 TFAILIF Trim Failure Interrupt Status\nThis bit indicates that HIRC0 trim value update limitation count reached and the HIRC0 clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRC0TCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRC0TIEN[1]) is high, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached. Write 1 to clear this to 0. 1 1 read-write 0 Trim value update limitation count does not reach #0 1 Trim value update limitation count reached and HIRC frequency still not locked #1 RC1TCTL SYS_RC1TCTL HIRC1 Trim Control Register 0x90 read-write n 0x0 0x0 CESTOPEN Clock Error Stop Enable Bit\nThis bit is used to control if stop the HIRC1 trim operation when 32.768 kHz clock error is detected.\nIf set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC1TISTS[2]) would be set high and HIRC1 trim operation was stopped. If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC1TISTS[2]) would be set high and HIRC1 trim operation is continuously. 8 1 read-write 0 The trim operation is keep going if clock is inaccuracy #0 1 The trim operation is stopped if clock is inaccuracy #1 FREQSEL Trim Frequency Selection\nThis field indicates the target frequency of 36 MHz internal high speed RC oscillator (HIRC1) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN (SYS_IRC1TCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.\nNote: HIRC1 auto trim cannot work normally inPower-down mode. These bits must be cleared before entering Power-down mode. 0 2 read-write 0 Disable HIRC1 auto trim function #00 1 Reserved #01 2 Enable HIRC1 auto trim function and trim HIRC to 36 MHz #10 3 Reserved #11 LOOPSEL Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock. 4 2 read-write 0 Trim value calculation is based on average difference in 4 32.768 kHz clock #00 1 Trim value calculation is based on average difference in 8 32.768 kHz clock #01 2 Trim value calculation is based on average difference in 16 32.768 kHz clock #10 3 Trim value calculation is based on average difference in 32 32.768 kHz clock #11 RETRYCNT Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC1 trim value before the frequency of HIRC1 locked.\nOnce the HIRC1 locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC1 still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_IRC1TCTL[1:0]) will be cleared to 00. 6 2 read-write 0 Trim retry count limitation is 64 loops #00 1 Trim retry count limitation is 128 loops #01 2 Trim retry count limitation is 256 loops #10 3 Trim retry count limitation is 512 loops #11 RC1TIEN SYS_RC1TIEN HIRC1 Trim Interrupt Enable Register 0x94 read-write n 0x0 0x0 CLKEIEN Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRC1TSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 2 1 read-write 0 Disable CLKERRIF(SYS_IRC1TSTS[2]) status to trigger an interrupt to CPU #0 1 Enable CLKERRIF(SYS_IRC1TSTS[2]) status to trigger an interrupt to CPU #1 TFAILIEN Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC1 trim value update limitation count reached and HIRC1 frequency still not locked on target frequency set by FREQSEL(SYS_IRC1TCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_IRC1TSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached. 1 1 read-write 0 Disable TFAILIF(SYS_IRC1TSTS[1]) status to trigger an interrupt to CPU #0 1 Enable TFAILIF(SYS_IRC1TSTS[1]) status to trigger an interrupt to CPU #1 RC1TISTS SYS_RC1TISTS HIRC1 Trim Interrupt Status Register 0x98 read-write n 0x0 0x0 CLKERRIF Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 36 MHz internal high speed RC oscillator (HIRC1) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRC1TCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRC1TCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRC1TIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0. 2 1 read-write 0 Clock frequency is accuracy #0 1 Clock frequency is inaccuracy #1 FREQLOCK HIRC1 Frequency Lock Status\nThis bit indicates the HIRC1 frequency is locked.\nThis is a status bit and doesn't trigger any interrupt. 0 1 read-write 0 The internal high-speed oscillator frequency doesn't lock at 36 MHz yet #0 1 The internal high-speed oscillator frequency locked at 36 MHz #1 TFAILIF Trim Failure Interrupt Status\nThis bit indicates that HIRC1 trim value update limitation count reached and the HIRC1 clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRC1TCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRC1TIEN[1]) is high, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached. Write 1 to clear this to 0. 1 1 read-write 0 Trim value update limitation count does not reach #0 1 Trim value update limitation count reached and HIRC1 frequency still not locked #1 RCCFCTL SYS_RCCFCTL RC Clock Filter Control Register 0x28 -1 read-write n 0x0 0x0 HIRC0FEN HIRC0 Clock Filter Enable Bit\nThis bit is used to enable/disable HIRC0clock filter function. 0 1 read-write 0 HIRC0clock filter function Disabled #0 1 HIRC0clock filter function Enabled (default) #1 HIRC1FEN HIRC1 Clock Filter Enable Bit\nThis bit is used to enable/disable HIRC1clock filter function. 1 1 read-write 0 HIRC1clock filter function Disabled #0 1 HIRC1clock filter function Enabled (default) #1 MRCFEN MRC Clock Filter Enable Bit\nThis bit is used to enable/disable MRC clock filter function. 2 1 read-write 0 4MHz MRC clock filter function Disabled #0 1 4MHz MRC clock filter function Enabled (default) #1 REGLCTL SYS_REGLCTL Register Lock Control Register 0x100 read-write n 0x0 0x0 REGLCTL Register Lock Control Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. Register Lock Control Disable Index (Read Only) 0 8 read-write 0 Write-protection Enabled for writing protected registers. Any write to the protected register is ignored 0 1 Write-protection Disabled for writing protected registers 1 RPDBCLK SYS_RPDBCLK Reset Pin Debounce Clock Selection Register 0x120 read-write n 0x0 0x0 RSTPDBCLK Reset Pin Debounce Clock Selection Bit\nBefore swtch clock, both clock sources must be enabled. 6 1 read-write 0 HIRC2 is slected as reset pin debounce clock #0 1 HIRC0 is slected as reset pin debounce clock.(.default) #1 RSTSTS SYS_RSTSTS System Reset Status Register 0x4 read-write n 0x0 0x0 BODRF BOD Reset Flag The BOD reset flag is set by the Reset Signal from the Brown-Out Detector to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 4 1 read-write 0 No reset from BOD #0 1 The BOD had issued the reset signal to reset the system #1 CPURF CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0. 7 1 read-write 0 No reset from CPU #0 1 The Cortex-M0 Core and FMC are reset by software setting CPURST to 1 #1 LOCKRF Lockup Reset Flag 8 1 read-write 0 No reset from Cortex-M0 #0 1 The Cortex-M0 had issued the reset signal to reset the system by Cortex-M0 lockup event #1 LVRF LVR Reset Flag The LVR reset flag is set by the Reset Signal from the Low-VoltageReset controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 3 1 read-write 0 No reset from LVR #0 1 The LVR had issued the reset signal to reset the system #1 PINRF NRESET Pin Reset Flag The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 1 1 read-write 0 No reset from nRESET pin #0 1 Pin nRESET had issued the reset signal to reset the system #1 PORF POR Reset Flag The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 0 1 read-write 0 No reset from POR or CHIPRST #0 1 Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system #1 SYSRF System Reset Flag The system reset flag is set by the Reset Signal from the Cortex-M0 Core to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 5 1 read-write 0 No reset from Cortex-M0 #0 1 The Cortex-M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core #1 WDTRF WDT Reset Flag The WDT reset flag is set by the Reset Signal from the Watchdog Timer to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 2 1 read-write 0 No reset from watchdog timer or window watchdog timer #0 1 The watchdog timer had issued the reset signal to reset the system #1 TEMPCTL SYS_TEMPCTL Temperature Sensor Control Register 0x20 read-write n 0x0 0x0 VTEMPEN Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function. 0 1 read-write 0 Temperature sensor function Disabled (default) #0 1 Temperature sensor function Enabled #1 WKSTS SYS_WKSTS System Wake-up Status Register 0x7C read-only n 0x0 0x0 ACMPWK ACMP Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with ACMP wake-up event. This flag is cleared when Power-down mode is entered. 0 1 read-only BODWK BOD Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with BOD wake-up event. This flag is cleared when Power-down mode is entered. 8 1 read-only GPIOWK GPIO Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with GPIO wake-up event. This flag is cleared when Power-down mode is entered. 16 1 read-only I2C0WK I2C0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with I2C0 wake-up event. This flag is cleared when Power-down mode is entered. 2 1 read-only I2C1WK I2C1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with I2C1 wake-up event. This flag is cleared when Power-down mode is entered. 1 1 read-only RTCWK RTC Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with a RTCalarm or tick time happened. This flag is cleared when Power-down mode is entered. 15 1 read-only SPI0WK SPI0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI0 wake-up event. This flag is cleared when Power-down mode is entered. 12 1 read-only SPI1WK SPI1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI1 wake-up event. This flag is cleared when Power-down mode is entered. 11 1 read-only SPI2WK SPI2 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI2 wake-up event. This flag is cleared when Power-down mode is entered. 10 1 read-only SPI3WK SPI3 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI3 wake-up event. This flag is cleared when Power-down mode is entered. 9 1 read-only TMR0WK TMR0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR0 wake-up event. This flag is cleared when Power-down mode is entered. 6 1 read-only TMR1WK TMR1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR1 wake-up event. This flag is cleared when Power-down mode is entered. 5 1 read-only TMR2WK TMR2 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR2 wake-up event. This flag is cleared when Power-down mode is entered. 4 1 read-only TMR3WK TMR3 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR3 wake-up event. This flag is cleared when Power-down mode is entered. 3 1 read-only UART0WK UART0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with UART0 wake-up event. This flag is cleared when Power-down mode is entered. 14 1 read-only UART1WK UART1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with UART1 wake-up event. This flag is cleared when Power-down mode is entered. 13 1 read-only WDTWK WDT Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with WDT wake-up event. This flag is cleared when Power-down mode is entered. 7 1 read-only TMR01 TMR Register Map TMR 0x0 0x0 0x1C registers n 0x100 0x1C registers n 0x120 0x4 registers n 0x20 0x4 registers n 0x200 0x18 registers n GPA_SHADOW GPA_SHADOW GPIO Port A Pin Value Shadow Register 0x200 read-only n 0x0 0x0 PIN0 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 0 1 read-only PIN1 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 1 1 read-only PIN10 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 10 1 read-only PIN11 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 11 1 read-only PIN12 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 12 1 read-only PIN13 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 13 1 read-only PIN14 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 14 1 read-only PIN15 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 15 1 read-only PIN2 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 2 1 read-only PIN3 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 3 1 read-only PIN4 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 4 1 read-only PIN5 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 5 1 read-only PIN6 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 6 1 read-only PIN7 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 7 1 read-only PIN8 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 8 1 read-only PIN9 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW, bits [15:10] are reserved.\nNote2: For GPF_SHADOW, bits [15:6] are reserved. 9 1 read-only GPB_SHADOW GPB_SHADOW GPIO Port B Pin Value Shadow Register 0x204 read-write n 0x0 0x0 GPC_SHADOW GPC_SHADOW GPIO Port C Pin Value Shadow Register 0x208 read-write n 0x0 0x0 GPD_SHADOW GPD_SHADOW GPIO Port D Pin Value Shadow Register 0x20C read-write n 0x0 0x0 GPE_SHADOW GPE_SHADOW GPIO Port E Pin Value Shadow Register 0x210 read-write n 0x0 0x0 GPF_SHADOW GPF_SHADOW GPIO Port F Pin Value Shadow Register 0x214 read-write n 0x0 0x0 TIMER0_CAP TIMER0_CAP Timer 0 Capture Data Register 0x18 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register\nWhen CAPEN (TIMERx_CTL[16]) bit is set, CAPFUNCS (TIMERx_CTL[17]) bit is 0, CAPCNTMD (TIMERx_CTL[20]) bit is 0, and the transition on Tx_EXT pin matched the CAPEDGE (TIMERx_CTL[19:18]) setting, CAPIF (TIMERx_INTSTS[1]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.\nWhen CAPEN (TIMERx_CTL[16]) bit is set, CAPFUNCS (TIMERx_CTL[17]) bit is 0, CAPCNTMD (TIMERx_CTL[20]) bit is 1, and the transition on Tx_EXT pin matched the 2nd transition of CAPEDGE (TIMERx_CTL[19:18]) setting, CAPIF (TIMERx_INTSTS[1]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 0 24 read-only TIMER0_CMP TIMER0_CMP Timer 0 Compare Register 0x8 read-write n 0x0 0x0 CMPDAT Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT, or the core will run into unknown state.\nNote2:When the timer is operating in Continuous Counting mode (OPMODE (TIMERx_CTL[5:4] is 11), the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. \nNote3: Whenthe timer is not operating inContinuous Counting mode (OPMODE (TIMERx_CTL[5:4] is not 11), the 24-bit up counter will restart counting from 0 and usethe newest CMPDAT value as the timer compared value when user writes a new value into the CMPDAT field.In addition, the prescale counter will be reloaded. 0 24 read-write TIMER0_CNT TIMER0_CNT Timer 0Counter Data Register 0x14 read-write n 0x0 0x0 CNT Timer Counter Data (Read)\nCounter Reset (Write)\nUser can write any value to TIEMRx_CNT to reset internal 24-bit timer up-counter and 8-bit pre-scale counter. This reset operation wouldn't affect any other timer control registers and circuit. After reset completed, the 24-bit timer up-counter and 8-bit pre-scale counter restart the counting based on the TIMERx_CTL register setting. 0 24 read-write RSTACT Reset Active\nThis bit indicates if the counter reset operation active.\nWhen user write this register, timer starts to reset its internal 24-bit timer up-counter and 8-bit pre-scale counter to 0. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically.\nNote: This bit is read only. Write operation wouldn't take any effect. 31 1 read-write 0 Reset operation is done #0 1 Reset operation triggered by writing TIMERx_CNT is in progress #1 TIMER0_CTL TIMER0_CTL Timer 0 Control and Status Register 0x0 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status. 7 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CAPCNTMD Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while CAPEN (TIMERx_CTL[16]) is set to high.\nIf this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by OPMODE (TIMERx_CTL[5:4]) field. When CAPEN (TIMERx_CTL[16]) is set, CAPFUNCS (TIMERx_CTL[17]) is 0, and the transition of TC pin matches the CAPEDGE (TIMERx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TIMERx_CAP.\nIf this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at 0. When CAPEN (TIMERx_CTL[16]) is set, CAPFUNCS (TIMERx_CTL[17]) is 0, and once the transition of external pin matches the 1st transition of CAPEDGE (TIMERx_CTL[19:18]) setting, the 24-bit up-counting timer will start counting. And then if the transition of external pin matches the 2nd transition of CAPEDGE (TIMERx_CTL[19:18]) setting, the 24-bit up-counting timer will stop counting. And its value will be saved into register TIMERx_CAP. 20 1 read-write 0 Capture with free-counting timer mode #0 1 Capture with trigger-counting timer mode #1 CAPDBEN Timer External Capture Pin De-bounce Enable Bit\nNote1: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit.\nNote2: For Timer 1 and 3, when INTRTGEN (TIMERx_CTL[24]) is high, the capture signal is from internal of chip and the de-bounce circuit would not take effect no matter this bit is high or low. 22 1 read-write 0 Tx_EXT (x= 0~3) pin de-bounce Disabled #0 1 Tx_EXT (x= 0~3) pin de-bounce Enabled #1 CAPEDGE Timer External Capture Pin Edge Detection\nFor timer counter reset function and free-counting mode of timer capture function, the configurations are: 18 2 read-write 0 A Falling edge on Tx_EXT (x= 0~3) pin will be detected.\n1stfalling edge on TC pin triggers 24-bit timer to start counting, while 2nd falling edge triggers 24-bit timer to stop counting #00 1 A Rising edge on Tx_EXT (x= 0~3) pin will be detected.\n1st rising edge on TC pin triggers 24-bit timer to start counting, while 2nd rising edge triggers 24-bit timer to stop counting #01 2 Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected.\nFalling edge on TC pin triggers 24-bit timer to start counting, while rising edge triggers 24-bit timer to stop counting #10 3 Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected.\nRising edge on TC pin triggers 24-bit timer to start counting, while falling edge triggers 24-bit timer to stop counting #11 CAPEN Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT pin. 16 1 read-write 0 Tx_EXT (x= 0~3) pin Disabled #0 1 Tx_EXT (x= 0~3) pin Enabled #1 CAPFUNCS Capture Function Selection 17 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 CMPCTL Timer Compared Mode Selection If updated CMPDAT (TIMERx_CMP) value CNT (TIMERx_CNT), CNT (TIMERx_CNT) will be reset to default value. At the same time, prescale counter reloaded. 23 1 read-write 0 The behavior selection in one-shot, periodic or Toggle-output mode Disabled #0 1 The behavior selection in one-shot, periodic or Toggle-output mode Enabled #1 CNTDBEN Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is set to 1, the edge detection of Tx pin is detected with de-bounce circuit. 14 1 read-write 0 Tx (x= 0~3) pin de-bounce Disabled #0 1 Tx (x= 0~3) pin de-bounce Enabled #1 CNTEN Timer Counting Enable Bit\nNote3: Writing this bit 1 will not take any effect if RSTCNT (TIMERx_CTL[1]) is also set to 1 at the same time. 0 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 CNTPHASE Timer External Count Phase 13 1 read-write 0 A Falling edge of external counting pin will be counted #0 1 A Rising edge of external counting pin will be counted #1 DSRCCTLF DSRC Control Timer Flag (Read Only)\nThis flag high indicates this timer is being controlled by DSRC. When DSRCCTLF is 1, write operation to register of this timer wouldn't take any effect.\nNote1:This bit is read only. Write operation wouldn't take any effect.\nNote2: This bit is only valid in Timer2. In Timer0, Timer1 and Timer3, read this bit always get 0. 31 1 read-only 0 DSRC control Timer Disabled #0 1 DSRC control Timer Enabled #1 EXTCNTEN Event Counter Mode Enable Bit\nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter, this bit should be set to 1 and HCLK as timer clock source. 12 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 ICEDEBUG ICE Debug Mode Acknowledge Disable Bit\nTimer counter will keep going no matter CPU is held by ICE or not. 3 1 read-write 0 ICE debug mode acknowledgement affects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTRTGEN Inter-timer Trigger Function EnableBit\nNote:In TIMERx+1_CTL, this bit is always 0. 24 1 read-write 0 Inter-timer trigger function Disabled #0 1 Inter-timer trigger function Enabled #1 INTRTGMD Inter-timer Trigger Mode Selection\nNote:In TIMERx+1_CTL, this bit is always 0. 25 1 read-write 0 TIMERx count the all input events from Tx pin #0 1 TIMERx ignored the number of first incoming events based on EVNTDPCNT (TIMERx_ECTL[31:24]) #1 OPMODE Timer Counting Mode Selection 4 2 read-write 0 The Timer controller is operated in One-shot mode #00 1 The Timer controller is operated in Periodic mode #01 2 The Timer controller is operated in Toggle-output mode #10 3 The Timer controller is operated in Continuous Counting mode #11 RSTCNT Timer Counter Reset Bit\nSetting this bit will reset the internal 8-bit prescale counter, 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[0]) to 0.\nNote: This bit will be auto cleared and takes at least 3 TIMERx_CLK clock cycles. 1 1 read-write 0 No effect #0 1 Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit #1 TRGADC Trigger ADC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.\nNote: If TRGSSEL (TIMERx_CTL[11]) is set to 0, the time-out interrupt signal will trigger ADC.\nIf TRGSSEL (TIMERx_CTL[11]) is set to 1, the capture interrupt signal will trigger ADC. 8 1 read-write 0 Timer interrupt trigger ADC Disabled #0 1 Timer interrupt trigger ADC Enabled #1 TRGPDMA Timer Trigger PDMA EnableBit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.\nNote: If TRGSSEL (TIMERx_CTL[11]) is set to 0, the time-out interrupt signal will trigger PDMA.\nIf TRGSSEL (TIMERx_CTL[11]) is set to 1, the capture interrupt signal will trigger PDMA. 10 1 read-write 0 Timer interrupt trigger PDMADisabled #0 1 Timer interrupt trigger PDMAEnabled #1 TRGPWM Trigger PWM EnableBit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM. 28 1 read-write 0 Timer interrupt trigger PWM Disabled #0 1 Timer interrupt trigger PWM Enabled #1 TRGSSEL Trigger Source Selection\nIf this bit is set to 1, capture interrupt can trigger ADC, PDMA and PWM. Otherwise, time-out interrupt can trigger ADC, PDMA and PWM. 11 1 read-write 0 Time-out interrupt is used to trigger ADC, PDMA and PWM #0 1 Capture interrupt is used to trigger ADC, PDMA and PWM #1 WKEN Wake-up Function Enable Bit\nIf this bit is set to 1, while CNTIF (TIMERx_INTSTS[0]) or CAPIF (TIMERx_INTSTS[1]) is 1, the timer interrupt signal will generate a wake-up trigger event to CPU. 2 1 read-write 0 Wake-up function Disabled if timer interrupt signal generated #0 1 Wake-up function Enabled if timer interrupt signal generated #1 TIMER0_ECTL TIMER0_ECTL Timer 0Extended Control Register 0x20 read-write n 0x0 0x0 EVNTDPCNT Event Drop Count\nThis field indicates timer how many events dropped after inter-timer trigger function enable.\nFor example, if user configured EVNTDPCNT to 7, timer would drop 7 first incoming events and starts the inter-timer trigger operation when it get 8th event.\nNote: ECNTDPCNT only takes effect when INTRTGEN (TIMERx_CTL[24]) INTRTGMD (TIMERx_CTL[25]) are both set to 1. 24 8 read-write TIMER0_INTEN TIMER0_INTEN Timer 0 Interrupt Enable Register 0xC read-write n 0x0 0x0 CAPIEN Timer External Capture Interrupt Enable Bit\nNote:CAPIEN is used to enable timer external interrupt. If CAPIEN is enabled, the timer will rise an interrupt when CAPIF (TIMERx_INTSTS[1]) is 1. 1 1 read-write 0 Tx_EXT (x= 0~3) pin detection Interrupt Disabled #0 1 Tx_EXT (x= 0~3) pin detection Interrupt Enabled #1 CNTIEN Timer Interrupt EnableBit\nNote:If this bit is enabled, when the timer interrupt flag CNTIF(TIMERx_INTSTS[0]) is set to 1, the timer interrupt signal is generated and informed to CPU. 0 1 read-write 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 TIMER0_INTSTS TIMER0_INTSTS Timer 0 Interrupt Status Register 0x10 read-write n 0x0 0x0 CAPDATOF Capture Data Overflow Flag\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status.\nIf the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.\nNote: This bit is cleared by writing 1 to it. 5 1 read-write 0 New incoming capture event didn't detect before CPU clearing CAPIF (TIMERx_INTSTS[1]) status #0 1 New incoming capture event detected before CPU clearing CAPIF (TIMERx_INTSTS[1]) status #1 CAPFEDF Capture Falling Edge Detected Flag\nThis flag indicates theedge detected on Tx_EXT pin is rising edge or falling edge.\nNote1: The timer updates this flag when it updates the Timer Capture Data (TMR_CAP[23:0]) value.\nNote2:When a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status, Timer will keep this bit unchanged. 6 1 read-write 0 Rising edge detected on Tx_EXT pin #0 1 Falling edge detected on Tx_EXT pin #1 CAPIF Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: If a new incoming capture event detected before CPU clearing the CAPIF status, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 1 1 read-write 0 Tx_EXT (x= 0~3) pin interrupt did not occur #0 1 Tx_EXT (x= 0~3) pin interrupt occurred #1 CNTIF Timer Interrupt Status\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT (TIMERx_CNT[23:0])value matches the CMPDAT (TIMERx_CMP[23:0]) value #1 TWKF Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it. 4 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated #1 TIMER0_PRECNT TIMER0_PRECNT Timer 0 Pre-Scale Counter Register 0x4 read-write n 0x0 0x0 PSC Prescale Counter\nNote: If the PSC value is changed, CNT (TIMERx_CNT) is reset to 0 and prescale counter is reloaded. 0 8 read-write TIMER1_CAP TIMER1_CAP Timer 1 Capture Data Register 0x118 read-write n 0x0 0x0 TIMER1_CMP TIMER1_CMP Timer 1 Compare Register 0x108 read-write n 0x0 0x0 TIMER1_CNT TIMER1_CNT Timer 1 Counter Data Register 0x114 read-write n 0x0 0x0 TIMER1_CTL TIMER1_CTL Timer 1 Control and Status Register 0x100 read-write n 0x0 0x0 TIMER1_ECTL TIMER1_ECTL Timer 1 Extended Control Register 0x120 read-write n 0x0 0x0 TIMER1_INTEN TIMER1_INTEN Timer 1 Interrupt Enable Register 0x10C read-write n 0x0 0x0 TIMER1_INTSTS TIMER1_INTSTS Timer 1 Interrupt Status Register 0x110 read-write n 0x0 0x0 TIMER1_PRECNT TIMER1_PRECNT Timer 1 Pre-Scale Counter Register 0x104 read-write n 0x0 0x0 TMR23 TMR Register Map TMR 0x0 0x0 0x1C registers n 0x100 0x1C registers n 0x120 0x4 registers n 0x20 0x4 registers n TIMER2_CAP TIMER2_CAP Timer 2 Capture Data Register 0x18 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register\nWhen CAPEN (TIMERx_CTL[16]) bit is set, CAPFUNCS (TIMERx_CTL[17]) bit is 0, CAPCNTMD (TIMERx_CTL[20]) bit is 0, and the transition on Tx_EXT pin matched the CAPEDGE (TIMERx_CTL[19:18]) setting, CAPIF (TIMERx_INTSTS[1]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.\nWhen CAPEN (TIMERx_CTL[16]) bit is set, CAPFUNCS (TIMERx_CTL[17]) bit is 0, CAPCNTMD (TIMERx_CTL[20]) bit is 1, and the transition on Tx_EXT pin matched the 2nd transition of CAPEDGE (TIMERx_CTL[19:18]) setting, CAPIF (TIMERx_INTSTS[1]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 0 24 read-only TIMER2_CMP TIMER2_CMP Timer 2 Compare Register 0x8 read-write n 0x0 0x0 CMPDAT Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT, or the core will run into unknown state.\nNote2:When the timer is operating in Continuous Counting mode (OPMODE (TIMERx_CTL[5:4] is 11), the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. \nNote3: Whenthe timer is not operating inContinuous Counting mode (OPMODE (TIMERx_CTL[5:4] is not 11), the 24-bit up counter will restart counting from 0 and usethe newest CMPDAT value as the timer compared value when user writes a new value into the CMPDAT field.In addition, the prescale counter will be reloaded. 0 24 read-write TIMER2_CNT TIMER2_CNT Timer 2Counter Data Register 0x14 read-write n 0x0 0x0 CNT Timer Counter Data (Read)\nCounter Reset (Write)\nUser can write any value to TIEMRx_CNT to reset internal 24-bit timer up-counter and 8-bit pre-scale counter. This reset operation wouldn't affect any other timer control registers and circuit. After reset completed, the 24-bit timer up-counter and 8-bit pre-scale counter restart the counting based on the TIMERx_CTL register setting. 0 24 read-write RSTACT Reset Active\nThis bit indicates if the counter reset operation active.\nWhen user write this register, timer starts to reset its internal 24-bit timer up-counter and 8-bit pre-scale counter to 0. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically.\nNote: This bit is read only. Write operation wouldn't take any effect. 31 1 read-write 0 Reset operation is done #0 1 Reset operation triggered by writing TIMERx_CNT is in progress #1 TIMER2_CTL TIMER2_CTL Timer 2 Control and Status Register 0x0 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status. 7 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CAPCNTMD Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while CAPEN (TIMERx_CTL[16]) is set to high.\nIf this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by OPMODE (TIMERx_CTL[5:4]) field. When CAPEN (TIMERx_CTL[16]) is set, CAPFUNCS (TIMERx_CTL[17]) is 0, and the transition of TC pin matches the CAPEDGE (TIMERx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TIMERx_CAP.\nIf this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at 0. When CAPEN (TIMERx_CTL[16]) is set, CAPFUNCS (TIMERx_CTL[17]) is 0, and once the transition of external pin matches the 1st transition of CAPEDGE (TIMERx_CTL[19:18]) setting, the 24-bit up-counting timer will start counting. And then if the transition of external pin matches the 2nd transition of CAPEDGE (TIMERx_CTL[19:18]) setting, the 24-bit up-counting timer will stop counting. And its value will be saved into register TIMERx_CAP. 20 1 read-write 0 Capture with free-counting timer mode #0 1 Capture with trigger-counting timer mode #1 CAPDBEN Timer External Capture Pin De-bounce Enable Bit\nNote1: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit.\nNote2: For Timer 1 and 3, when INTRTGEN (TIMERx_CTL[24]) is high, the capture signal is from internal of chip and the de-bounce circuit would not take effect no matter this bit is high or low. 22 1 read-write 0 Tx_EXT (x= 0~3) pin de-bounce Disabled #0 1 Tx_EXT (x= 0~3) pin de-bounce Enabled #1 CAPEDGE Timer External Capture Pin Edge Detection\nFor timer counter reset function and free-counting mode of timer capture function, the configurations are: 18 2 read-write 0 A Falling edge on Tx_EXT (x= 0~3) pin will be detected.\n1stfalling edge on TC pin triggers 24-bit timer to start counting, while 2nd falling edge triggers 24-bit timer to stop counting #00 1 A Rising edge on Tx_EXT (x= 0~3) pin will be detected.\n1st rising edge on TC pin triggers 24-bit timer to start counting, while 2nd rising edge triggers 24-bit timer to stop counting #01 2 Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected.\nFalling edge on TC pin triggers 24-bit timer to start counting, while rising edge triggers 24-bit timer to stop counting #10 3 Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected.\nRising edge on TC pin triggers 24-bit timer to start counting, while falling edge triggers 24-bit timer to stop counting #11 CAPEN Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT pin. 16 1 read-write 0 Tx_EXT (x= 0~3) pin Disabled #0 1 Tx_EXT (x= 0~3) pin Enabled #1 CAPFUNCS Capture Function Selection 17 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 CMPCTL Timer Compared Mode Selection If updated CMPDAT (TIMERx_CMP) value CNT (TIMERx_CNT), CNT (TIMERx_CNT) will be reset to default value. At the same time, prescale counter reloaded. 23 1 read-write 0 The behavior selection in one-shot, periodic or Toggle-output mode Disabled #0 1 The behavior selection in one-shot, periodic or Toggle-output mode Enabled #1 CNTDBEN Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is set to 1, the edge detection of Tx pin is detected with de-bounce circuit. 14 1 read-write 0 Tx (x= 0~3) pin de-bounce Disabled #0 1 Tx (x= 0~3) pin de-bounce Enabled #1 CNTEN Timer Counting Enable Bit\nNote3: Writing this bit 1 will not take any effect if RSTCNT (TIMERx_CTL[1]) is also set to 1 at the same time. 0 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 CNTPHASE Timer External Count Phase 13 1 read-write 0 A Falling edge of external counting pin will be counted #0 1 A Rising edge of external counting pin will be counted #1 DSRCCTLF DSRC Control Timer Flag (Read Only)\nThis flag high indicates this timer is being controlled by DSRC. When DSRCCTLF is 1, write operation to register of this timer wouldn't take any effect.\nNote1:This bit is read only. Write operation wouldn't take any effect.\nNote2: This bit is only valid in Timer2. In Timer0, Timer1 and Timer3, read this bit always get 0. 31 1 read-only 0 DSRC control Timer Disabled #0 1 DSRC control Timer Enabled #1 EXTCNTEN Event Counter Mode Enable Bit\nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter, this bit should be set to 1 and HCLK as timer clock source. 12 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 ICEDEBUG ICE Debug Mode Acknowledge Disable Bit\nTimer counter will keep going no matter CPU is held by ICE or not. 3 1 read-write 0 ICE debug mode acknowledgement affects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTRTGEN Inter-timer Trigger Function EnableBit\nNote:In TIMERx+1_CTL, this bit is always 0. 24 1 read-write 0 Inter-timer trigger function Disabled #0 1 Inter-timer trigger function Enabled #1 INTRTGMD Inter-timer Trigger Mode Selection\nNote:In TIMERx+1_CTL, this bit is always 0. 25 1 read-write 0 TIMERx count the all input events from Tx pin #0 1 TIMERx ignored the number of first incoming events based on EVNTDPCNT (TIMERx_ECTL[31:24]) #1 OPMODE Timer Counting Mode Selection 4 2 read-write 0 The Timer controller is operated in One-shot mode #00 1 The Timer controller is operated in Periodic mode #01 2 The Timer controller is operated in Toggle-output mode #10 3 The Timer controller is operated in Continuous Counting mode #11 RSTCNT Timer Counter Reset Bit\nSetting this bit will reset the internal 8-bit prescale counter, 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[0]) to 0.\nNote: This bit will be auto cleared and takes at least 3 TIMERx_CLK clock cycles. 1 1 read-write 0 No effect #0 1 Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit #1 TRGADC Trigger ADC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.\nNote: If TRGSSEL (TIMERx_CTL[11]) is set to 0, the time-out interrupt signal will trigger ADC.\nIf TRGSSEL (TIMERx_CTL[11]) is set to 1, the capture interrupt signal will trigger ADC. 8 1 read-write 0 Timer interrupt trigger ADC Disabled #0 1 Timer interrupt trigger ADC Enabled #1 TRGPDMA Timer Trigger PDMA EnableBit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.\nNote: If TRGSSEL (TIMERx_CTL[11]) is set to 0, the time-out interrupt signal will trigger PDMA.\nIf TRGSSEL (TIMERx_CTL[11]) is set to 1, the capture interrupt signal will trigger PDMA. 10 1 read-write 0 Timer interrupt trigger PDMADisabled #0 1 Timer interrupt trigger PDMAEnabled #1 TRGPWM Trigger PWM EnableBit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM. 28 1 read-write 0 Timer interrupt trigger PWM Disabled #0 1 Timer interrupt trigger PWM Enabled #1 TRGSSEL Trigger Source Selection\nIf this bit is set to 1, capture interrupt can trigger ADC, PDMA and PWM. Otherwise, time-out interrupt can trigger ADC, PDMA and PWM. 11 1 read-write 0 Time-out interrupt is used to trigger ADC, PDMA and PWM #0 1 Capture interrupt is used to trigger ADC, PDMA and PWM #1 WKEN Wake-up Function Enable Bit\nIf this bit is set to 1, while CNTIF (TIMERx_INTSTS[0]) or CAPIF (TIMERx_INTSTS[1]) is 1, the timer interrupt signal will generate a wake-up trigger event to CPU. 2 1 read-write 0 Wake-up function Disabled if timer interrupt signal generated #0 1 Wake-up function Enabled if timer interrupt signal generated #1 TIMER2_ECTL TIMER2_ECTL Timer 2Extended Control Register 0x20 read-write n 0x0 0x0 EVNTDPCNT Event Drop Count\nThis field indicates timer how many events dropped after inter-timer trigger function enable.\nFor example, if user configured EVNTDPCNT to 7, timer would drop 7 first incoming events and starts the inter-timer trigger operation when it get 8th event.\nNote: ECNTDPCNT only takes effect when INTRTGEN (TIMERx_CTL[24]) INTRTGMD (TIMERx_CTL[25]) are both set to 1. 24 8 read-write TIMER2_INTEN TIMER2_INTEN Timer 2 Interrupt Enable Register 0xC read-write n 0x0 0x0 CAPIEN Timer External Capture Interrupt Enable Bit\nNote:CAPIEN is used to enable timer external interrupt. If CAPIEN is enabled, the timer will rise an interrupt when CAPIF (TIMERx_INTSTS[1]) is 1. 1 1 read-write 0 Tx_EXT (x= 0~3) pin detection Interrupt Disabled #0 1 Tx_EXT (x= 0~3) pin detection Interrupt Enabled #1 CNTIEN Timer Interrupt EnableBit\nNote:If this bit is enabled, when the timer interrupt flag CNTIF(TIMERx_INTSTS[0]) is set to 1, the timer interrupt signal is generated and informed to CPU. 0 1 read-write 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 TIMER2_INTSTS TIMER2_INTSTS Timer 2 Interrupt Status Register 0x10 read-write n 0x0 0x0 CAPDATOF Capture Data Overflow Flag\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status.\nIf the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.\nNote: This bit is cleared by writing 1 to it. 5 1 read-write 0 New incoming capture event didn't detect before CPU clearing CAPIF (TIMERx_INTSTS[1]) status #0 1 New incoming capture event detected before CPU clearing CAPIF (TIMERx_INTSTS[1]) status #1 CAPFEDF Capture Falling Edge Detected Flag\nThis flag indicates theedge detected on Tx_EXT pin is rising edge or falling edge.\nNote1: The timer updates this flag when it updates the Timer Capture Data (TMR_CAP[23:0]) value.\nNote2:When a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status, Timer will keep this bit unchanged. 6 1 read-write 0 Rising edge detected on Tx_EXT pin #0 1 Falling edge detected on Tx_EXT pin #1 CAPIF Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: If a new incoming capture event detected before CPU clearing the CAPIF status, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 1 1 read-write 0 Tx_EXT (x= 0~3) pin interrupt did not occur #0 1 Tx_EXT (x= 0~3) pin interrupt occurred #1 CNTIF Timer Interrupt Status\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT (TIMERx_CNT[23:0])value matches the CMPDAT (TIMERx_CMP[23:0]) value #1 TWKF Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it. 4 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated #1 TIMER2_PRECNT TIMER2_PRECNT Timer 2 Pre-Scale Counter Register 0x4 read-write n 0x0 0x0 PSC Prescale Counter\nNote: If the PSC value is changed, CNT (TIMERx_CNT) is reset to 0 and prescale counter is reloaded. 0 8 read-write TIMER3_CAP TIMER3_CAP Timer 3 Capture Data Register 0x118 read-write n 0x0 0x0 TIMER3_CMP TIMER3_CMP Timer 3 Compare Register 0x108 read-write n 0x0 0x0 TIMER3_CNT TIMER3_CNT Timer 3 Counter Data Register 0x114 read-write n 0x0 0x0 TIMER3_CTL TIMER3_CTL Timer 3 Control and Status Register 0x100 read-write n 0x0 0x0 TIMER3_ECTL TIMER3_ECTL Timer 3 Extended Control Register 0x120 read-write n 0x0 0x0 TIMER3_INTEN TIMER3_INTEN Timer 3 Interrupt Enable Register 0x10C read-write n 0x0 0x0 TIMER3_INTSTS TIMER3_INTSTS Timer 3 Interrupt Status Register 0x110 read-write n 0x0 0x0 TIMER3_PRECNT TIMER3_PRECNT Timer 3 Pre-Scale Counter Register 0x104 read-write n 0x0 0x0 UART0 UART Register Map UART 0x0 0x0 0x28 registers n 0x30 0x18 registers n UART_ATLCTL UART_ATLCTL UART Alternate Control State Register. 0x34 read-write n 0x0 0x0 ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 19 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADRMPID Address / PID Match Value Register\nWhen in the RS-485 Function Mode, this field contains the RS-485 address match values.\nWhen in the LIN Function mode, this field contains the LIN protected identifier field, software fills ID0~ID5 (PID [5:0]), hardware will calculate P0 and P1.\n\nNote: This field is used for RS-485 auto address detection mode or used for LIN protected identifier field (PID). 24 8 read-write BITERREN Bit Error Detect EnableBit 8 1 read-write 0 Bit error detection Disabled #0 1 Bit error detection Enabled #1 BRKFL LIN TX Break Field Count \nThe field contains 3-bit LIN TX break field count.\nNote: The break field length is BRKFL + 8. 0 3 read-write LINHSEL LIN Header Selection 4 2 read-write 0 The LIN header includes break field #00 1 The LIN header includes break field + sync field #01 2 The LIN header includes break field + sync field + PID field #10 3 Reserved #11 LINRXEN LIN RX Enable Control\nWhen LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL), the controller will generator a interrupt to CPU (LININT) 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Header Trigger EnableBit The LIN TX header can be break field or break and sync field or break, sync and frame ID field , it is depend on setting LINHSEL (UART_ATLCTL[5:4]). Note1: This bit will be cleared automatically and generate a interrupt to CPU (LININT). Note2:When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by LINHSEL (UART_ATLCTL[5:4]) field) transfer operation finished, this bit will be cleared automatically. Note3: If user wants to receive transmit data, it recommended to enable LINRXEN bit. 7 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS485NMM operation mode. 17 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD)\nNote: It can be active with RS485AAD or RS485NMM operation mode. 18 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It cannot be active with RS-485_AAD operation mode. 16 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divisor Register. 0x24 read-write n 0x0 0x0 BRD Baud Rate Divider \nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown inUART Controller Baud Rate Generation. 0 16 read-write DIV16EN Divider 16 Enable Control Note: In IrDA mode, this bit must clear to 0 . 31 1 read-write 0 The equation of baud rate is UART_CLK / [(BRD+1)] #0 1 The equation of baud rate is UART_CLK / [16 * (BRD+1)] #1 UART_BRCOMPAT UART_BRCOMPAT UART Baud Rate Compensation Register. 0x3C read-write n 0x0 0x0 BRCOMPAT Baud Rate Compensation Patten\nThese 9bits are used to define the relative bit is compensated or not. BRCOMPAT[7:0] is used to define the compensation of D[7:0] and BRCOMPAT{[8] is used to define the parity bit. 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_CTRL UART_CTRL UART Control Register. 0x4 -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length\nNote: The calculation of bit number includes the START bit. 13 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect EnableBit\nNote: When the auto-baud rate detect operation finishes, hardware will clear this bit and the associated interrupt (ABRIF) will be generated (If ABRIEN (UART_INTEN [7]) be enabled). 12 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote:When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 5 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_LINE[13:12]), the UART will de-assert nRTS signal. 4 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 FTOEN Frame Time Out Enable Bit\nThis bit is used to enable the timer counter even the FIFO is still empty. 8 1 read-write 0 Frame time out Disabled #0 1 Frame time out Enabled #1 RXDMAEN RX DMA Enable Bit\nThis bit can enable or disable RX DMA service. 6 1 read-write 0 RX DMA Disabled #0 1 RX DMA Enabled #1 RXOFF Receiver Disable Bit Note1:In RS-485 NMM mode, user can set this bit to receive data before detecting address byte. Note2: In RS-485 AAD mode, this bit will be setting to 1 automatically. Note3: In RS-485 AUD mode and LIN break + sync +PID header mode, hardware will control data automatically, so don't fill any value to this bit. 2 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_CTRL[0]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles. 0 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXDMAEN TX DMA Enable Bit\nThis bit can enable or disable TX DMA service. 7 1 read-write 0 TX DMA Disabled #0 1 TX DMA Enabled #1 TXOFF Transfer Disable Bit 3 1 read-write 0 Transfer Enabled #0 1 Transfer Disabled #1 TXRST TX Field Software Reset\nWhen TXRST (UART_CTRL[1]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles 1 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register. 0x0 read-only n 0x0 0x0 DAT Receive /Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_DAT.\nRead Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO. 0 8 read-only UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register. 0x18 -1 read-write n 0x0 0x0 BIF Break Interrupt Flag( Read Only) This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). Note: This bit is read only, but can be cleared by writing '1' to it. 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note: This bit is read only, but can be cleared by writing '1' to it. 5 1 read-only 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error State Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note: This bit is read only, but can be cleared by writing '1' to it. 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 1 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 2 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXOVIF RX Overflow Error Status Flag (Read Only) This bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, this bit will be set. Note:This bit is read only, but can be cleared by writing 1 to it. 0 1 read-only 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 16 5 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty). 9 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXENDF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote:This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 11 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only) This bit indicates TX FIFO full or not. Note:This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 10 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Status Flag (Read Only) If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. Note:This bit is read only, but can be cleared by writing 1 to it. 8 1 read-only 0 TX FIFO did not overflow #0 1 TX FIFO overflowed #1 TXPTR TX-fIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 24 5 read-only UART_FUNCSEL UART_FUNCSEL UART Function Select Register. 0x38 read-write n 0x0 0x0 FUNCSEL Function Selection 0 2 read-write 0 UART function mode #00 1 LIN function mode #01 2 IrDA function mode #10 3 RS-485 function mode #11 UART_INTEN UART_INTEN UART Interrupt Enable Register. 0xC read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 7 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit\nNote:This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem statusinterrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-outinterrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TXENDIEN Transmitter Empty FInterrupt Enable Bit\nNote: If the bit is enabled, there is interrupt event when the TXENDF (UART_FIFOSTS[11]) is actived. 9 1 read-write 0 Transmit Empty interrupt Disabled #0 1 Transmit Empty interrupt Enabled #1 WKUPIEN Wake-up Interrupt EnableBit Note: Hardware will clear one of the wake-up status bits in UART_WKUPSTS when the wake-up operation finishes and system clock work stable. 6 1 read-write 0 Wake-up system function Disabled #0 1 Wake-up system function Enabled, when the system is in Power-down mode, one of the wake-up event will wake-up system from Power-down mode. #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register. 0x10 -1 read-write n 0x0 0x0 ABRIF Auto-baud Rate Interrupt Status Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[7]) is set then the auto-baud rate interrupt will be generated. Note1: This bit is read only, but can be cleared by writing 1 to ABRDTOIF (UART_TRSR[2]) or ABRDIF (UART_TRSR[1]). Note2: This bit is cleared when both the ABRDTOIF and ABRDIF are cleared. 7 1 read-only 0 No Auto-Baud Rate interrupt is generated #0 1 Auto-Baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[8]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5])is set, the transfer is not correct. If BFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote:This bit is read only. This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[8]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[8]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 LINIF LIN Interrupt Status Flag (Read Only) This bit is set when the LIN TX header transmitted, RX header received or the SIN does not equal SOUT and if LINIEN(UART_INTEN[8]) is set then the LIN interrupt will be generated. Note1: This bit is read only, but can be cleared by it by writing 1 to BITEF (UART_TRSR[5]), LINTXIF (UART_TRSR[3]) or LINRXIF (UART_TRSR[4]). Note2: This bit is cleared when both the BITEF, LINTXIF and LINRXIF are cleared. 8 1 read-only 0 No LIN interrupt is generated #0 1 LIN interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only) Channel \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEM[18]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 RDAIF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_LINE[9:8]) 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RLSIF Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_TRSR[0]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RXTOIF Rime-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RXTOIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty) 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 WKUPIF Wake-up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by one of UART controller wake-up event.\nNote1: If WKDATEN (UART_INTEN[6]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to one of UART_WKUPSTS[4:0] (THRTOWKSTS or THRWKSTS or CTSWKSTS or DATWKSTS or ADRWKSTS). 6 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by one of UART controller wake-up event #1 UART_IRDA UART_IRDA UART IrDA Control Register. 0x30 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINE UART_LINE UART Transfer Line Control Register. 0x8 read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity EnableBit\nNote:This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of STOP Bit 2 1 read-write 0 One STOP bit is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 STOP bit is generated in the transmitted data #1 PBE Parity Bit EnableBit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 No parity bit generated Disabled #0 1 Parity bit generated Enabled #1 RFITL RX FIFO Interrupt Trigger Level When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). Note: When operating in IrDA mode or RS-485 mode, the RFITL must be set to 0 . 8 2 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #00 1 RX FIFO Interrupt Trigger Level is 4 bytes #01 10 RX FIFO Interrupt Trigger Level is 8 bytes #10 11 RX FIFO Interrupt Trigger Level is 14 bytes #11 RTSTRGLV nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control. 12 2 read-write 0 nRTS Trigger Level is 1 byte #00 1 nRTS Trigger Level is 4 bytes #01 2 nRTS Trigger Level is 8 bytes #10 3 nRTS Trigger Level is 14 bytes #11 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 WLS Word Length Selection\nThis field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_MODE UART_MODE UART Modem Control Status Register. 0x1C -1 read-write n 0x0 0x0 CTSACTLV nCTS Trigger Level\nThis bit defines the active level state of nCTS pin input. 16 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag (Read Only) This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]). Note: This bit is read only, but it can be cleared by writing 1 to it. 18 1 read-only 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected. 17 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output. 0 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin State (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status. 1 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-Out Control Register. 0x20 -1 read-write n 0x0 0x0 DLY TX Delay Time Value This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. Note1: Fill all 0 to this field indicates to disable this function. Note2: The real delay value is DLY. Note3:The counting clock is baud rate clock. 16 8 read-write TOIC Time-out Comparator Note1: Fill all 0 to this field indicates to disable this function. Note2: The real time-out value is TOIC + 1. Note3: The counting clock is baud rate clock. Note4: The UART data format is start bit + 8 data bits + parity bit + stop bit, although software can configure this field by any value but it is recommend to fill this field great than 0xA. 0 9 read-write UART_TRSR UART_TRSR UART Transfer Status Register. 0x14 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Interrupt (Read Only) This bit is set to logic 1 when auto-baud rate detect function finished. Note: This bit is read only, but can be cleared by writing 1 to it. 1 1 read-only 0 No Auto- Baud Rate interrupt is generated #0 1 Auto-Baud Rate interrupt is generated #1 ABRDTOIF Auto-baud Rate Time-out Interrupt(Read Only) Note1:This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow. Note2: This bit is read only, but can be cleared by writing 1 to it. 2 1 read-only 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detection Status Flag (Read Only)\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ATLCTL[19]) is set to 1 to enable Address detection mode .\nNote2: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BITEF Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state is not equal to the output pin (SOUT) state, BITEF will be set.\nWhen occur bit error, hardware will generate an interrupt to CPU (LININT). 5 1 read-only 0 No Bit error interrupt is generated #0 1 Bit error interrupt is generated #1 LINRXIF LIN RX Interrupt Flag (Read Only) This bit is set to logic 1 when received LIN header field. The header may be break field or break field + sync field or break field + sync field + PID field , and it can be choose by setting LINHSEL (UART_ATLCTL[5:4]) register. Note: This bit is read only, but can be cleared by writing 1 to it. 4 1 read-only 0 No LIN Rx interrupt is generated #0 1 LIN Rx interrupt is generated #1 LINTXIF LIN TX Interrupt Flag (Read Only) This bit is set to logic 1 when LIN transmitted header field. The header may be break field or break field + sync field or break field + sync field + PID field , it can be choose by setting LINHSEL (UART_ATLCTL[5:4]) register. Note: This bit is read only, but can be cleared by writing 1 to it. 3 1 read-only 0 No LIN Transmit interrupt is generated #0 1 LIN Transmit interrupt is generated #1 RXBUSY Receive Busy Status(Read Only)\nNote: The user can use this to check the busy status in receiver mode. If the user wants to enter power down, this bit shall be confirm in Idle state and there is 2 UART clock latency for receiver pin. 7 1 read-only 0 The receiver machine stays in idle state #0 1 The receiver machine stays in no Idle state #1 SLVSYNCF LIN RX SYNC Error Flag (Read Only) This bit is set to logic 1 when LIN received incorrect SYNC field. User can choose the header by setting LINHSEL (UART_ATLCTL[5:4]) register. Note: This bit is read only, but can be cleared by writing 1 to LINRXIF. 8 1 read-only 0 No LIN Rx sync error is generated #0 1 LIN Rx sync error is generated #1 UART_WKUPEN UART_WKUPEN UART Wake-up Enable Register. 0x40 read-write n 0x0 0x0 WKADRMEN RS-485 Address Match Wake-up Enable Bit 4 1 read-write 0 RS-485 ADD mode address match wake-up function Disabled #0 1 RS-485 AAD mode address match wake-up function Enabled when the system is in power-down mode #1 WKCTSEN CTSn Wake-up Enable Bit\nWhen the system is in power-down mode, an external nCTS change will wake-up system from power-down mode. 0 1 read-write 0 nCTS wake-up function Disabled #0 1 nCTS wake-up function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit Note: Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable. 1 1 read-write 0 Incoming data wake-up function Disabled #0 1 Incoming data wake-up function Enabled when the system is in power-down mode, incoming data will wake-up system from power-down mode #1 WKTHREN FIFO Threshold Reach Wake-up Enable Bit\nNote: It is suggest the function is enabled in UART mode and the UART clock is selected in 32K. 2 1 read-write 0 Received FIFO threshold reach wake-up function Disabled #0 1 Received FIFO threshold reach wake-up function Enabled when the system is in power-down mode #1 WKTHRTOEN FIFO Threshold Reach Time Out Wake-up Enable Bit\nNote: It is suggest the function is enabled when the WKTHREN (UART_WKUPEN[2]) is set to 1. 3 1 read-write 0 Received FIFO threshold no reach and time out wake-up function Disabled #0 1 Received FIFO threshold no reach and time out wake-up function Enabled when the system is in power-down mode #1 UART_WKUPSTS UART_WKUPSTS UART Wake-up Status Register. 0x44 read-write n 0x0 0x0 ADRWKSTS RS-485 Address Byte Detection Wake-up Flag (Read Only)\nNote1: If WKADRMEN (UART_WKUPEN[4])is enabled, the wake-up function is generated.\nNote2: This field is used for RS-485 function mode and ADDRDEN (UART_ATLCTL[19]) is set to 1 to enable Address detection mode .\nNote2: This bit is read only, but can be cleared by writing '1' to it. 4 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Receiver detects a data that is an address bit (bit 9 ='1') #1 CTSWKSTS nCTS Wake-up Flag (Read Only)\nNote1: If WKCTSEN (UART_ WKUPEN [0])is enabled, the wake-up function is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKSTS Data Wake-up Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_ WKUPEN [1]) is enabled, the wake-up function is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it 1 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by data wake-up #1 THRTOWKSTS Threshold Wake-up Time Out Flag (Read Only)\nNote1: If WKTHRTOEN (UART_ WKUPEN [3])is enabled, the wake-up function is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by FIFO threshold time out wake-up #1 THRWKSTS Threshold Wake-up Flag (Read Only)\nNote1: If WKTHREN (UART_ WKUPEN [2])is enabled, the wake-up function is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 2 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by FIFO threshold wake-up #1 UART1 UART Register Map UART 0x0 0x0 0x28 registers n 0x30 0x18 registers n UART_ATLCTL UART_ATLCTL UART Alternate Control State Register. 0x34 read-write n 0x0 0x0 ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 19 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADRMPID Address / PID Match Value Register\nWhen in the RS-485 Function Mode, this field contains the RS-485 address match values.\nWhen in the LIN Function mode, this field contains the LIN protected identifier field, software fills ID0~ID5 (PID [5:0]), hardware will calculate P0 and P1.\n\nNote: This field is used for RS-485 auto address detection mode or used for LIN protected identifier field (PID). 24 8 read-write BITERREN Bit Error Detect EnableBit 8 1 read-write 0 Bit error detection Disabled #0 1 Bit error detection Enabled #1 BRKFL LIN TX Break Field Count \nThe field contains 3-bit LIN TX break field count.\nNote: The break field length is BRKFL + 8. 0 3 read-write LINHSEL LIN Header Selection 4 2 read-write 0 The LIN header includes break field #00 1 The LIN header includes break field + sync field #01 2 The LIN header includes break field + sync field + PID field #10 3 Reserved #11 LINRXEN LIN RX Enable Control\nWhen LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL), the controller will generator a interrupt to CPU (LININT) 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Header Trigger EnableBit The LIN TX header can be break field or break and sync field or break, sync and frame ID field , it is depend on setting LINHSEL (UART_ATLCTL[5:4]). Note1: This bit will be cleared automatically and generate a interrupt to CPU (LININT). Note2:When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by LINHSEL (UART_ATLCTL[5:4]) field) transfer operation finished, this bit will be cleared automatically. Note3: If user wants to receive transmit data, it recommended to enable LINRXEN bit. 7 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS485NMM operation mode. 17 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD)\nNote: It can be active with RS485AAD or RS485NMM operation mode. 18 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It cannot be active with RS-485_AAD operation mode. 16 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divisor Register. 0x24 read-write n 0x0 0x0 BRD Baud Rate Divider \nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown inUART Controller Baud Rate Generation. 0 16 read-write DIV16EN Divider 16 Enable Control Note: In IrDA mode, this bit must clear to 0 . 31 1 read-write 0 The equation of baud rate is UART_CLK / [(BRD+1)] #0 1 The equation of baud rate is UART_CLK / [16 * (BRD+1)] #1 UART_BRCOMPAT UART_BRCOMPAT UART Baud Rate Compensation Register. 0x3C read-write n 0x0 0x0 BRCOMPAT Baud Rate Compensation Patten\nThese 9bits are used to define the relative bit is compensated or not. BRCOMPAT[7:0] is used to define the compensation of D[7:0] and BRCOMPAT{[8] is used to define the parity bit. 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_CTRL UART_CTRL UART Control Register. 0x4 -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length\nNote: The calculation of bit number includes the START bit. 13 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect EnableBit\nNote: When the auto-baud rate detect operation finishes, hardware will clear this bit and the associated interrupt (ABRIF) will be generated (If ABRIEN (UART_INTEN [7]) be enabled). 12 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote:When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 5 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_LINE[13:12]), the UART will de-assert nRTS signal. 4 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 FTOEN Frame Time Out Enable Bit\nThis bit is used to enable the timer counter even the FIFO is still empty. 8 1 read-write 0 Frame time out Disabled #0 1 Frame time out Enabled #1 RXDMAEN RX DMA Enable Bit\nThis bit can enable or disable RX DMA service. 6 1 read-write 0 RX DMA Disabled #0 1 RX DMA Enabled #1 RXOFF Receiver Disable Bit Note1:In RS-485 NMM mode, user can set this bit to receive data before detecting address byte. Note2: In RS-485 AAD mode, this bit will be setting to 1 automatically. Note3: In RS-485 AUD mode and LIN break + sync +PID header mode, hardware will control data automatically, so don't fill any value to this bit. 2 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_CTRL[0]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles. 0 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXDMAEN TX DMA Enable Bit\nThis bit can enable or disable TX DMA service. 7 1 read-write 0 TX DMA Disabled #0 1 TX DMA Enabled #1 TXOFF Transfer Disable Bit 3 1 read-write 0 Transfer Enabled #0 1 Transfer Disabled #1 TXRST TX Field Software Reset\nWhen TXRST (UART_CTRL[1]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles 1 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register. 0x0 read-only n 0x0 0x0 DAT Receive /Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_DAT.\nRead Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO. 0 8 read-only UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register. 0x18 -1 read-write n 0x0 0x0 BIF Break Interrupt Flag( Read Only) This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). Note: This bit is read only, but can be cleared by writing '1' to it. 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note: This bit is read only, but can be cleared by writing '1' to it. 5 1 read-only 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error State Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note: This bit is read only, but can be cleared by writing '1' to it. 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 1 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 2 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXOVIF RX Overflow Error Status Flag (Read Only) This bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, this bit will be set. Note:This bit is read only, but can be cleared by writing 1 to it. 0 1 read-only 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 16 5 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty). 9 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXENDF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote:This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 11 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only) This bit indicates TX FIFO full or not. Note:This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 10 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Status Flag (Read Only) If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. Note:This bit is read only, but can be cleared by writing 1 to it. 8 1 read-only 0 TX FIFO did not overflow #0 1 TX FIFO overflowed #1 TXPTR TX-fIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 24 5 read-only UART_FUNCSEL UART_FUNCSEL UART Function Select Register. 0x38 read-write n 0x0 0x0 FUNCSEL Function Selection 0 2 read-write 0 UART function mode #00 1 LIN function mode #01 2 IrDA function mode #10 3 RS-485 function mode #11 UART_INTEN UART_INTEN UART Interrupt Enable Register. 0xC read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 7 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit\nNote:This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem statusinterrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-outinterrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TXENDIEN Transmitter Empty FInterrupt Enable Bit\nNote: If the bit is enabled, there is interrupt event when the TXENDF (UART_FIFOSTS[11]) is actived. 9 1 read-write 0 Transmit Empty interrupt Disabled #0 1 Transmit Empty interrupt Enabled #1 WKUPIEN Wake-up Interrupt EnableBit Note: Hardware will clear one of the wake-up status bits in UART_WKUPSTS when the wake-up operation finishes and system clock work stable. 6 1 read-write 0 Wake-up system function Disabled #0 1 Wake-up system function Enabled, when the system is in Power-down mode, one of the wake-up event will wake-up system from Power-down mode #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register. 0x10 -1 read-write n 0x0 0x0 ABRIF Auto-baud Rate Interrupt Status Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[7]) is set then the auto-baud rate interrupt will be generated. Note1: This bit is read only, but can be cleared by writing 1 to ABRDTOIF (UART_TRSR[2]) or ABRDIF (UART_TRSR[1]). Note2: This bit is cleared when both the ABRDTOIF and ABRDIF are cleared. 7 1 read-only 0 No Auto-Baud Rate interrupt is generated #0 1 Auto-Baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[8]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5])is set, the transfer is not correct. If BFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote:This bit is read only. This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[8]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[8]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 LINIF LIN Interrupt Status Flag (Read Only) This bit is set when the LIN TX header transmitted, RX header received or the SIN does not equal SOUT and if LINIEN(UART_INTEN[8]) is set then the LIN interrupt will be generated. Note1: This bit is read only, but can be cleared by it by writing 1 to BITEF (UART_TRSR[5]), LINTXIF (UART_TRSR[3]) or LINRXIF (UART_TRSR[4]). Note2: This bit is cleared when both the BITEF, LINTXIF and LINRXIF are cleared. 8 1 read-only 0 No LIN interrupt is generated #0 1 LIN interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only) Channel \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEM[18]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 RDAIF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_LINE[9:8]) 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RLSIF Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_TRSR[0]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RXTOIF Rime-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RXTOIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty) 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 WKUPIF Wake-up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by one of UART controller wake-up event.\nNote1: If WKDATEN (UART_INTEN[6]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to one of UART_WKUPSTS[4:0] (THRTOWKSTS or THRWKSTS or CTSWKSTS or DATWKSTS or ADRWKSTS). 6 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by one of UART controller wake-up event #1 UART_IRDA UART_IRDA UART IrDA Control Register. 0x30 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINE UART_LINE UART Transfer Line Control Register. 0x8 read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity EnableBit\nNote:This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of STOP Bit 2 1 read-write 0 One STOP bit is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 STOP bit is generated in the transmitted data #1 PBE Parity Bit EnableBit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 No parity bit generated Disabled #0 1 Parity bit generated Enabled #1 RFITL RX FIFO Interrupt Trigger Level When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). Note: When operating in IrDA mode or RS-485 mode, the RFITL must be set to 0 . 8 2 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #00 1 RX FIFO Interrupt Trigger Level is 4 bytes #01 10 RX FIFO Interrupt Trigger Level is 8 bytes #10 11 RX FIFO Interrupt Trigger Level is 14 bytes #11 RTSTRGLV nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control. 12 2 read-write 0 nRTS Trigger Level is 1 byte #00 1 nRTS Trigger Level is 4 bytes #01 2 nRTS Trigger Level is 8 bytes #10 3 nRTS Trigger Level is 14 bytes #11 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 WLS Word Length Selection\nThis field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_MODE UART_MODE UART Modem Control Status Register. 0x1C -1 read-write n 0x0 0x0 CTSACTLV nCTS Trigger Level\nThis bit defines the active level state of nCTS pin input. 16 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag (Read Only) This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]). Note: This bit is read only, but it can be cleared by writing 1 to it. 18 1 read-only 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected. 17 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output. 0 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin State (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status. 1 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-Out Control Register. 0x20 -1 read-write n 0x0 0x0 DLY TX Delay Time Value This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. Note1: Fill all 0 to this field indicates to disable this function. Note2: The real delay value is DLY. Note3:The counting clock is baud rate clock. 16 8 read-write TOIC Time-out Comparator Note1: Fill all 0 to this field indicates to disable this function. Note2: The real time-out value is TOIC + 1. Note3: The counting clock is baud rate clock. Note4: The UART data format is start bit + 8 data bits + parity bit + stop bit, although software can configure this field by any value but it is recommend to fill this field great than 0xA. 0 9 read-write UART_TRSR UART_TRSR UART Transfer Status Register. 0x14 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Interrupt (Read Only) This bit is set to logic 1 when auto-baud rate detect function finished. Note: This bit is read only, but can be cleared by writing 1 to it. 1 1 read-only 0 No Auto- Baud Rate interrupt is generated #0 1 Auto-Baud Rate interrupt is generated #1 ABRDTOIF Auto-baud Rate Time-out Interrupt(Read Only) Note1:This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow. Note2: This bit is read only, but can be cleared by writing 1 to it. 2 1 read-only 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detection Status Flag (Read Only)\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ATLCTL[19]) is set to 1 to enable Address detection mode .\nNote2: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BITEF Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state is not equal to the output pin (SOUT) state, BITEF will be set.\nWhen occur bit error, hardware will generate an interrupt to CPU (LININT). 5 1 read-only 0 No Bit error interrupt is generated #0 1 Bit error interrupt is generated #1 LINRXIF LIN RX Interrupt Flag (Read Only) This bit is set to logic 1 when received LIN header field. The header may be break field or break field + sync field or break field + sync field + PID field , and it can be choose by setting LINHSEL (UART_ATLCTL[5:4]) register. Note: This bit is read only, but can be cleared by writing 1 to it. 4 1 read-only 0 No LIN Rx interrupt is generated #0 1 LIN Rx interrupt is generated #1 LINTXIF LIN TX Interrupt Flag (Read Only) This bit is set to logic 1 when LIN transmitted header field. The header may be break field or break field + sync field or break field + sync field + PID field , it can be choose by setting LINHSEL (UART_ATLCTL[5:4]) register. Note: This bit is read only, but can be cleared by writing 1 to it. 3 1 read-only 0 No LIN Transmit interrupt is generated #0 1 LIN Transmit interrupt is generated #1 RXBUSY Receive Busy Status(Read Only)\nNote: The user can use this to check the busy status in receiver mode. If the user wants to enter power down, this bit shall be confirm in Idle state and there is 2 UART clock latency for receiver pin. 7 1 read-only 0 The receiver machine stays in idle state #0 1 The receiver machine stays in no Idle state #1 SLVSYNCF LIN RX SYNC Error Flag (Read Only) This bit is set to logic 1 when LIN received incorrect SYNC field. User can choose the header by setting LINHSEL (UART_ATLCTL[5:4]) register. Note: This bit is read only, but can be cleared by writing 1 to LINRXIF. 8 1 read-only 0 No LIN Rx sync error is generated #0 1 LIN Rx sync error is generated #1 UART_WKUPEN UART_WKUPEN UART Wake-up Enable Register. 0x40 read-write n 0x0 0x0 WKADRMEN RS-485 Address Match Wake-up Enable Bit 4 1 read-write 0 RS-485 ADD mode address match wake-up function Disabled #0 1 RS-485 AAD mode address match wake-up function Enabled when the system is in power-down mode #1 WKCTSEN CTSn Wake-up Enable Bit\nWhen the system is in power-down mode, an external nCTS change will wake-up system from power-down mode. 0 1 read-write 0 nCTS wake-up function Disabled #0 1 nCTS wake-up function Enabled #1 WKDATEN Incoming Data Wake-up Enable Bit Note: Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable. 1 1 read-write 0 Incoming data wake-up function Disabled #0 1 Incoming data wake-up function Enabled when the system is in power-down mode, incoming data will wake-up system from power-down mode #1 WKTHREN FIFO Threshold Reach Wake-up Enable Bit\nNote: It is suggest the function is enabled in UART mode and the UART clock is selected in 32K. 2 1 read-write 0 Received FIFO threshold reach wake-up function Disabled #0 1 Received FIFO threshold reach wake-up function Enabled when the system is in power-down mode #1 WKTHRTOEN FIFO Threshold Reach Time Out Wake-up Enable Bit\nNote: It is suggest the function is enabled when the WKTHREN (UART_WKUPEN[2]) is set to 1. 3 1 read-write 0 Received FIFO threshold no reach and time out wake-up function Disabled #0 1 Received FIFO threshold no reach and time out wake-up function Enabled when the system is in power-down mode #1 UART_WKUPSTS UART_WKUPSTS UART Wake-up Status Register. 0x44 read-write n 0x0 0x0 ADRWKSTS RS-485 Address Byte Detection Wake-up Flag (Read Only)\nNote1: If WKADRMEN (UART_WKUPEN[4])is enabled, the wake-up function is generated.\nNote2: This field is used for RS-485 function mode and ADDRDEN (UART_ATLCTL[19]) is set to 1 to enable Address detection mode .\nNote2: This bit is read only, but can be cleared by writing '1' to it. 4 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Receiver detects a data that is an address bit (bit 9 ='1') #1 CTSWKSTS nCTS Wake-up Flag (Read Only)\nNote1: If WKCTSEN (UART_ WKUPEN [0])is enabled, the wake-up function is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKSTS Data Wake-up Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_ WKUPEN [1]) is enabled, the wake-up function is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it 1 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by data wake-up #1 THRTOWKSTS Threshold Wake-up Time Out Flag (Read Only)\nNote1: If WKTHRTOEN (UART_ WKUPEN [3])is enabled, the wake-up function is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by FIFO threshold time out wake-up #1 THRWKSTS Threshold Wake-up Flag (Read Only)\nNote1: If WKTHREN (UART_ WKUPEN [2])is enabled, the wake-up function is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 2 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by FIFO threshold wake-up #1 WDT WDT Register Map WDT 0x0 0x0 0xC registers n CTL WDT_CTL Watchdog Timer Control Register 0x0 -1 read-write n 0x0 0x0 DBGEN WDT Debug Mode Enable Control (Write Protect) 31 1 read-write 0 WDT stopped counting if system is in Debug mode #0 1 WDT still counted even system is in Debug mode #1 RSTCNT Reset Watchdog TimerCounter (Write Protect)\nPlease refer to open lock sequence to program it.\nSetting this bit will reset the Watchdog timer counter.\nNote: This bit will be auto cleared after 1 PCLK clock cycle. 0 1 read-write 0 No effect #0 1 Reset the contents of the Watchdog timer #1 RSTEN Watchdog Timer Reset Function EnableBit (Write Protect)\nPlease refer to open lock sequence to program it.\nSetting this bit will enable the Watchdog timer reset function. 1 1 read-write 0 Watchdog timer reset function Disabled #0 1 Watchdog timer reset function Enabled #1 WDTEN Watchdog Timer EnableBit(Write Protect)\nPlease refer to open lock sequence to program it. 3 1 read-write 0 Watchdog timer Disabled (this action will reset the internal counter) #0 1 Watchdog timer Enabled #1 WKEN Watchdog Timer Wake-up Function EnableBit(Write Protect)\nPlease refer to open lock sequence to program it. 2 1 read-write 0 Watchdog timer Wake-up CPU function Disabled #0 1 Wake-up function Enabled so that Watchdog timer time-out can wake up CPU from Power-down mode #1 WTIS Watchdog Timer Interval Selection(Write Protect)\nPlease refer to open lock sequence to program it.\nThe three bits select the time-out interval for the Watchdog timer. This count is free running counter.\nPlease refer toTable6.111. 4 3 read-write WTRDSEL Watchdog Timer Reset Delay Selection\nWhen watchdog time-out happened, software has a time named watchdog reset delay period to clear watchdog timer to prevent watchdog reset happened. Software can select a suitable value of watchdog reset delay period for different watchdog time-out period.\nNote: This bit will be reset if watchdog reset happened 8 2 read-write 0 Watchdog reset delay period is 1026 watchdog clock #00 1 Watchdog reset delay period is 130 watchdog clock #01 2 Watchdog reset delay period is 18 watchdog clock #10 3 Watchdog reset delay period is 3 watchdog clock #11 INTEN WDT_INTEN Watchdog Timer Interrupt Enable Register 0x4 read-write n 0x0 0x0 WDTIEN Watchdog Timer Time-out Interrupt EnableBit 0 1 read-write 0 Watchdog timer time-out interrupt Disabled #0 1 Watchdog timer time-out interrupt Enabled #1 STATUS WDT_STATUS Watchdog Timer Status Register 0x8 read-write n 0x0 0x0 RSTF Watchdog Timer Reset StatusFlag When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is disabled, then the Watchdog timer has no effect on this bit. Note: This bit is read only, but can be cleared by writing 1 to it. 1 1 read-write 0 Watchdog timer reset did not occur #0 1 Watchdog timer reset occurred #1 WDTIF Watchdog Timer Time-out Interrupt StatusFlag If the Watchdog timer time-out interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer time-out interrupt has occurred. If the Watchdog timer time-out interrupt is not enabled, then this bit indicates that a time-out period has elapsed. Note:This bit is read only, but can be cleared by writing 1 to it. 0 1 read-write 0 Watchdog timer time-out interrupt did not occur #0 1 Watchdog timer time-out interrupt occurred #1 WKF Watchdog Timer Wake-up StatusFlag If Watchdog timer causes system to wake up from Power-down mode, this bit will be set to 1. It must be cleared by software with a write 1 to this bit. Note1: When system in Power-down mode and watchdog time-out, hardware will set WKF and WDTIF. Note2: After one engine clock, this bit can be cleared by writing 1 to it 2 1 read-write 0 Watchdog timer does not cause system wake-up #0 1 Wake system up from Power-down mode by Watchdog time-out #1 WWDT WWDT Register Map WWDT 0x0 0x0 0x14 registers n CNT WWDT_CNT Window Watchdog Timer Counter Value Register 0x10 -1 read-only n 0x0 0x0 CNTDAT WWDT Counter Value\nThis register reflects the current counter value of window watchdog. 0 6 read-only CTL WWDT_CTL Window Watchdog Timer Control Register 0x4 -1 read-write n 0x0 0x0 DBGEN WWDT Debug EnableBit 31 1 read-write 0 WWDT stopped count if system is in Debug mode #0 1 WWDT still counted even system is in Debug mode #1 PERIODSEL WWDT Pre-scale Period Select\nThese three bits select the pre-scale for the WWDT counter period.\nPlease refer toTable 6.121WWDT Prescaler Value Selection. 8 4 read-write WINCMP WWDT Window Compare Bits\nSet this register to adjust the valid reload window.\nNote:WWDT_RLDCNTregistercan only be written when WWDT counter value between 0 and WINCMP, otherwise WWDT will generate RESET signal. 16 6 read-write WWDTEN Window Watchdog EnableBit\nSet this bit to enable Window Watchdog timer. 0 1 read-write 0 Window Watchdog timer function Disabled #0 1 Window Watchdog timer function Enabled #1 INTEN WWDT_INTEN Window Watchdog Timer Interrupt Enable Register 0x8 read-write n 0x0 0x0 WWDTIEN WWDT Interrupt Enable Bit\nSetting this bit will enable the Window Watchdog timer interrupt function. 0 1 read-write 0 Watchdog timer interrupt function Disabled #0 1 Watchdog timer interrupt function Enabled #1 RLDCNT WWDT_RLDCNT Window Watchdog Timer Reload Counter Register 0x0 write-only n 0x0 0x0 RLDCNT Window Watchdog Timer Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F.\nNote:This registercan only be written when WWDT counter value between 0 and WINCMP, otherwise WWDT will generate RESET signal. 0 32 write-only STATUS WWDT_STATUS Window Watchdog Timer Status Register 0xC read-write n 0x0 0x0 WWDTIF WWDT Compare Match Interrupt Flag\nWhen WWCMP matches the WWDT counter, this bit is set to 1. This bit can be cleared by writing '1' to it. 0 1 read-write WWDTRF WWDT Reset Flag\nWhen the WWDT counter down counts to 0 or writes WWDT_RLDCNT during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1. This bit can be cleared by writing '1' to it. 1 1 read-write