nuvoTon NM1240 2024.04.27 NM1240 8 32 ACMP ACMP Register Map ACMP 0x0 0x0 0x4 registers n 0x10 0xC registers n 0x8 0x4 registers n CTL0 ACMP_CTL0 Analog Comparator 0 Control Register 0x0 -1 read-write n 0x0 0x0 ACMPEN Comparator Enable Control Note: Comparator output needs to wait 2 us stable time after ACMPEN is set. 0 1 read-write 0 Comparator Disabled #0 1 Comparator Enabled #1 ACMPHYSEN Comparator0 Hysteresis Enable Control 2 2 read-write 0 ACMP0 Hysteresis function Disabled (Default) #00 1 ACMP0 Hysteresis function at comparator0 that the typical range is 20mV #01 2 ACMP0 Hysteresis function at comparator0 that the typical range is 90mV #10 3 ACMP0 Hysteresis function at comparator0 that the typical range is 150mV #11 ACMPIE Comparator Interrupt Enable Control Note1: Interrupt is generated if ACMPIE bit is set to '1' after ACMP conversion is finished. 1 1 read-write 0 ACMP interrupt function Disabled #0 1 ACMP interrupt function Enabled #1 CPNSEL Comparator Negative Input Select 24 2 read-write 0 ACMP0_N (PB.4) #00 1 Band_Gap #01 2 DAC1 #10 3 DAC0 #11 CPPSEL Comparator Positive Input Select 28 3 read-write 0 ACMP0_P0 (PB.0) #000 1 ACMP0_P1 (PB.1) #001 2 ACMP0_P2 (PB.2) #010 3 ACMP0_P3 (PC.1) #011 4 OP1_O (PE.2) #100 DLYEDGESEL PWM Delay Trigger Interrupt Flag Trigger Edge Detection 14 2 read-write 0 Interrupt Flag Trigger Edge Disabled #00 1 Rising #01 2 Falling #10 3 Rising/Falling #11 DLYTRGEN Analog Comparator Delay Trigger Mode Enable Control 12 1 read-write 0 Analog Comparator Delay Trigger Mode Disabled #0 1 Analog Comparator Delay Trigger Mode Enabled #1 DLYTRGIE Analog Comparator Delay Trigger Mode Interrupt Enable Control 13 1 read-write 0 Analog Comparator Delay Trigger Mode Interrupt Disabled #0 1 Analog Comparator Delay Trigger Mode Interrupt Enabled #1 DLYTRGSEL Analog Comparator Delay Trigger Mode Trigger Level Selection 8 2 read-write 0 Analog Comparator Delay Trigger Mode Trigger Disabled #00 1 High #01 2 Low #10 3 High/Low #11 DLYTRGSOR Analog Comparator Delay Trigger Mode Trigger Source Selection 10 2 read-write 0 EPWM_CH0 #00 1 EPWM_CH2 #01 2 EPWM_CH4 #10 3 TMR2_MATCH #11 EDGESEL Interrupt Flag Trigger Edge Detection 4 2 read-write 0 Interrupt Flag Trigger Edge Disabled #00 1 Rising #01 2 Falling #10 3 Rising/Falling #11 NFCLKS Noise Filter Clock Pre-divided Selection To determine the sampling frequency of the Noise Filter clock 20 3 read-write 0 PCLK #000 1 PCLK / 2 #001 2 PCLK / 4 #010 3 PCLK / 8 #011 4 PCLK/ 16 #100 5 PCLK / 32 #101 6 PCLK / 64 #110 7 PCLK / 256 #111 NFDIS Disable Comparator Noise Filter 23 1 read-write 0 Noise filter Enabled #0 1 Noise filter Disabled #1 PBRKSEL ACMP to EPWM Brake Selection 6 1 read-write 0 ACMP Result direct output #0 1 ACMP Delay Trigger Result output #1 POLARITY Analog Comparator Polarity Control 19 1 read-write 0 Analog Comparator normal output #0 1 Analog Comparator invert output #1 PRESET Comparator Result Preset Value 31 1 read-write 0 0 for ACMP0 preset value #0 1 1 for ACMP0 preset value #1 DACCTL ACMP_DACCTL DAC Buffer Control Register 0x18 -1 read-write n 0x0 0x0 DAC0BUFEN DAC0 Output Amplifier Enable Control 0 1 read-write 0 Amplifier Disabled #0 1 Amplifier Enabled #1 DAC1BUFEN DAC1 Output Amplifier Enable Control 1 1 read-write 0 Amplifier Disabled #0 1 Amplifier Enabled #1 DACVAL ACMP_DACVAL DAC Register 0x14 -1 read-write n 0x0 0x0 DAC0 DAC0 Referance Voltage (VDD x DAC0[11:0]/4096) 0 12 read-write DAC1 DAC1 Referance Voltage (VDD x DAC1[11:0]/4096) 16 12 read-write STATUS ACMP_STATUS Analog Comparator Status Register 0x8 -1 read-write n 0x0 0x0 ACMPF0 Comparator0 Flag This bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if ACMPIE set. Write '1' to clear this bit to 0. 0 1 read-write ACMPO0 Comparator0 Output 2 1 read-write DLYTRGF0 Comparator0 Flag This bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if DLYTRGIEN set. Write '1' to clear this bit to 0. 4 1 read-write DLYTRGO0 Analog Comparator0 Delay Trigger Mode Comparator Output 6 1 read-write TRGDLY ACMP_TRGDLY Analog Comparator Delay Trigger Mode Dleay Register 0x10 -1 read-write n 0x0 0x0 DELAY Analog Comparator Delay Trigger Mode Delay cycle(PCLK*cycle) 0 9 read-write ADC ADC Register Map ADC 0x0 0x10 0x4 registers n 0x20 0x14 registers n 0x40 0x4 registers n 0x80 0x80 registers n ADC0_DAT0 ADC0_DAT0 ADC0 Data Register n 0x80 -1 read-only n 0x0 0x0 ADC0DAT ADC0 Conversion Result This field contains conversion result of ADC0_CHn. 0 12 read-only ADC0_DAT1 ADC0_DAT1 ADC0 Data Register n 0x84 -1 read-write n 0x0 0x0 ADC0_DAT10 ADC0_DAT10 ADC0 Data Register n 0xA8 -1 read-write n 0x0 0x0 ADC0_DAT11 ADC0_DAT11 ADC0 Data Register n 0xAC -1 read-write n 0x0 0x0 ADC0_DAT12 ADC0_DAT12 ADC0 Data Register n 0xB0 -1 read-write n 0x0 0x0 ADC0_DAT13 ADC0_DAT13 ADC0 Data Register n 0xB4 -1 read-write n 0x0 0x0 ADC0_DAT14 ADC0_DAT14 ADC0 Data Register n 0xB8 -1 read-write n 0x0 0x0 ADC0_DAT15 ADC0_DAT15 ADC0 Data Register n 0xBC -1 read-write n 0x0 0x0 ADC0_DAT2 ADC0_DAT2 ADC0 Data Register n 0x88 -1 read-write n 0x0 0x0 ADC0_DAT3 ADC0_DAT3 ADC0 Data Register n 0x8C -1 read-write n 0x0 0x0 ADC0_DAT4 ADC0_DAT4 ADC0 Data Register n 0x90 -1 read-write n 0x0 0x0 ADC0_DAT5 ADC0_DAT5 ADC0 Data Register n 0x94 -1 read-write n 0x0 0x0 ADC0_DAT6 ADC0_DAT6 ADC0 Data Register n 0x98 -1 read-write n 0x0 0x0 ADC0_DAT7 ADC0_DAT7 ADC0 Data Register n 0x9C -1 read-write n 0x0 0x0 ADC0_DAT8 ADC0_DAT8 ADC0 Data Register n 0xA0 -1 read-write n 0x0 0x0 ADC0_DAT9 ADC0_DAT9 ADC0 Data Register n 0xA4 -1 read-write n 0x0 0x0 ADC1_DAT0 ADC1_DAT0 ADC1 Data Register n 0xC0 -1 read-only n 0x0 0x0 ADC1DAT ADC1 Conversion Result This field contains conversion result of ADC1_CHn. 0 12 read-only ADC1_DAT1 ADC1_DAT1 ADC1 Data Register n 0xC4 -1 read-write n 0x0 0x0 ADC1_DAT10 ADC1_DAT10 ADC1 Data Register n 0xE8 -1 read-write n 0x0 0x0 ADC1_DAT11 ADC1_DAT11 ADC1 Data Register n 0xEC -1 read-write n 0x0 0x0 ADC1_DAT12 ADC1_DAT12 ADC1 Data Register n 0xF0 -1 read-write n 0x0 0x0 ADC1_DAT13 ADC1_DAT13 ADC1 Data Register n 0xF4 -1 read-write n 0x0 0x0 ADC1_DAT14 ADC1_DAT14 ADC1 Data Register n 0xF8 -1 read-write n 0x0 0x0 ADC1_DAT15 ADC1_DAT15 ADC1 Data Register n 0xFC -1 read-write n 0x0 0x0 ADC1_DAT2 ADC1_DAT2 ADC1 Data Register n 0xC8 -1 read-write n 0x0 0x0 ADC1_DAT3 ADC1_DAT3 ADC1 Data Register n 0xCC -1 read-write n 0x0 0x0 ADC1_DAT4 ADC1_DAT4 ADC1 Data Register n 0xD0 -1 read-write n 0x0 0x0 ADC1_DAT5 ADC1_DAT5 ADC1 Data Register n 0xD4 -1 read-write n 0x0 0x0 ADC1_DAT6 ADC1_DAT6 ADC1 Data Register n 0xD8 -1 read-write n 0x0 0x0 ADC1_DAT7 ADC1_DAT7 ADC1 Data Register n 0xDC -1 read-write n 0x0 0x0 ADC1_DAT8 ADC1_DAT8 ADC1 Data Register n 0xE0 -1 read-write n 0x0 0x0 ADC1_DAT9 ADC1_DAT9 ADC1 Data Register n 0xE4 -1 read-write n 0x0 0x0 CS_CTL ADC_CS_CTL ADC Channel Select Control Register 0x10 -1 read-write n 0x0 0x0 ADC0CSEN ADC0(SH0) Channel Select Enable 0 16 read-write ADC1CSEN ADC1(SH1) Channel Select Enable 16 16 read-write CTL ADC_CTL ADC Control Register 0x20 -1 read-write n 0x0 0x0 ADC0HWTRGEN Hardware Trigger ADC Convertion Enable Bit Enable or disable triggering of A/D conversion by Hardware (PWM, Timer, ECAP and ADC self) 2 1 read-write 0 Disable ADC0 hardware trigger function #0 1 Enable ADC0 hardware trigger function #1 ADC0IEN ADC0 Interrupt Enable Bit Note: If ADC0IEN bit is set to 1 the ADC0_INT is requested by the end of ADC conversion. 1 1 read-write 0 Disable ADC0 interrupt #0 1 Enable ADC0 interrupt #1 ADC0SWTRG ADC0 Conversion Start Note: ADC0SWTRG will be set to '1' when any of ADC0 trigger event happen or user also can write '1' to this bit to demand a software ADC0 trigger, when hardware finish the conversion it will be cleared to '0' automatically. 3 1 read-write 0 Conversion stopped and A/D converter entered idle state #0 1 Start ADC0 and indicate there has ADC0 conversion request #1 ADC1HWTRGEN Hardware Trigger ADC Conversion Enable Control Enable or disable triggering of A/D conversion by Hardware (PWM, Timer, ECAP and ADC self) 10 1 read-write 0 Disable ADC1 hardware trigger function #0 1 Enable ADC1 hardware trigger function #1 ADC1IEN ADC1 Interrupt Enable Control Note: If ADC1IEN bit is set to 1 the ADC1_INT is requested by the end of ADC conversion. 9 1 read-write 0 Disable ADC1 interrupt #0 1 Enable ADC1 interrupt #1 ADC1SWTRG ADC1 Conversion Start Note: ADC1SWTRG will be set to '1' when any of ADC1 trigger event happen or user also can write '1' to this bit to demand a software ADC1 trigger, when hardware finish the conversion it will be cleared to '0' automatically. 11 1 read-write 0 Conversion stopped and A/D converter entered idle state #0 1 Start ADC1 and indicate there has ADC1 conversion request #1 ADCEN ADC Converter Enable Bit Note: Before starting the A/D conversion function, this bit should be set to '1'. Clear it to '0' to disable A/D converter analog circuit power consumption. 0 1 read-write 0 Disable ADC Converter #0 1 Enable ADC Converter #1 ADCMODE A/D Conversion Mode 6 2 read-write 0 Independent Mode, independent trigger function and independent interrupt #00 1 Reserved. #01 2 Simultaneous Mode, simultaneously triggered by ADC0, ADC0 and ADC1 convert sequentially then only interrupt ADC0IF is generated #10 3 Simultaneous Mode, simultaneously triggered by ADC0, ADC0 and ADC1 convert sequentially then only interrupt ADC0IF is generated #11 SMPCNT ADC_SMPCNT ADC Sampling Time Counter Register 0x2C -1 read-write n 0x0 0x0 ADCSMPCNT ADC Sampling Counter For normal channel: 0 4 read-write STATUS ADC_STATUS ADC Status Register 0x30 -1 read-write n 0x0 0x0 ADC0BUSY BUSY/IDLE 3 1 read-write 0 A/D converter is in idle state #0 1 A/D converter is busy at conversion #1 ADC0CH Current Conversion Channel It is read only. 4 4 read-write ADC0EOC ADC0 end of convert. 23 1 read-write ADC0IF A/D Conversion End Flag A status flag that indicates the end of A/D conversion. ADF is set to '1' When A/D conversion ends. This flag can be cleared by writing '1' to itself. 0 1 read-write ADC1BUSY BUSY/IDLE 11 1 read-write 0 A/D converter is in idle state #0 1 A/D converter is busy at conversion #1 ADC1CH Current Conversion Channel It is read only. 12 4 read-write ADC1EOC ADC1 end of convert. 31 1 read-write ADC1IF ADC1 Conversion End Flag A status flag that indicates the end of A/D conversion. ADF is set to '1' When A/D conversion ends. This flag can be cleared by writing '1' to itself. 8 1 read-write TRGDLY ADC_TRGDLY ADC Trigger Delay Control Register 0x28 -1 read-write n 0x0 0x0 ADC0DELAY ADC0 Trigger Delay Timer Setting this field will insert a delay time from H/W tirgger condition happens to conversion starts Delay time is (4 * ADC0DELAY) * system clock Note: Software trigger does not support delay-time insertion. 0 8 read-write ADC1DELAY ADC1 Trigger Delay Timer Setting this field will insert a delay time from H/W tirgger condition happens to conversion starts Delay time is (4 * ADC1DELAY) * system clock Note: Software trigger does not support delay-time insertion. 16 8 read-write TRGSOR ADC_TRGSOR ADC Hardware Trigger Source Control Register 0x24 -1 read-write n 0x0 0x0 ADC0PWMTRGSEL PWM Trigger Selection for ADC0 4 2 read-write 0 EPWM Signal Falling. (Not available in edge-aligned type) #00 1 EPWM Counter Central. (Not available in edge-aligned type) #01 2 EPWM signal Rising #10 3 Period #11 ADC0STADCSEL ADC0 External Trigger Pin (STADC) Trigger Selection 6 2 read-write 0 Rising #00 1 Falling #01 2 Rising or Falling #10 3 Reserved. #11 ADC0TRGSOR ADC0 Trigger Source 0 4 read-write 0 STADC #0000 1 PWM0 #0001 2 PWM1 #0010 3 PWM2 #0011 4 PWM3 #0100 5 PWM4 #0101 6 PWM5 #0110 7 TMR0_MATCH. (refer to Figure 6.61 Timer Controller Block Diagram) #0111 8 TMR1_MATCH. (refer to Figure 6.61 Timer Controller Block Diagram) #1000 9 ECAPPHG_TRG. (From ECAP, CPAEN (CAPTF0| CAPTF1| CAPTF2) #1001 10 ADC0IF #1010 11 ADC1IF #1011 ADC1PWMTRGSEL PWM Trigger Selection for ADC1 20 2 read-write 0 EPWM Signal Falling. (Not available in edge-aligned type) #00 1 EPWM Counter Central. (Not available in edge-aligned type) #01 2 EPWM signal Rising #10 3 Period #11 ADC1STADCSEL ADC1 External Trigger Pin (STADC) Trigger Selection 22 2 read-write 0 Rising #00 1 Falling #01 2 Rising or Falling #10 3 Reserved. #11 ADC1TRGSOR ADC1 Trigger Source 16 4 read-write 0 STADC #0000 1 PWM0 #0001 2 PWM1 #0010 3 PWM2 #0011 4 PWM3 #0100 5 PWM4 #0101 6 PWM5 #0110 7 TMR0_MATCH. (refer to Figure 6.61 Timer Controller Block Diagram) #0111 8 TMR1_MATCH. (refer to Figure 6.61 Timer Controller Block Diagram) #1000 9 ECAPPHG_TRG. (From ECAP, CPAEN (CAPTF0| CAPTF1| CAPTF2) #1001 10 ADC0IF #1010 11 ADC1IF #1011 VALSTS ADC_VALSTS ADC Valid Status Register 0x40 -1 read-write n 0x0 0x0 ADC0VALID Bits set 1 when ADC0 CHn convertion is finished, and it is automatically cleared when ADC0_DATn is read. 0 16 read-write ADC1VALID Bits set 1 when ADC1 CHn convertion is finished, and it is automatically cleared when ADC1_DATn is read. 16 16 read-write BPWM BPWM Register Map BPWM 0x0 0x0 0x24 registers n 0x40 0x8 registers n CLKDIV BPWM_CLKDIV Basic PWM Clock Source Divider Select Register 0x4 -1 read-write n 0x0 0x0 CLKDIV0 PWM Timer 0 Clock Source Divider Selection Select clock source divider for PWM timer 0. (Table is the same as CLKDIV1) 0 3 read-write CLKDIV1 PWM Timer 1 Clock Source Divider Selection Select clock source divider for PWM timer 1. 4 3 read-write 0 1/2 #000 1 1/4 #001 2 1/8 #010 3 1/16 #011 4 1 #100 CLKPSC BPWM_CLKPSC Basic PWM Pre-scalar Register 0x0 -1 read-write n 0x0 0x0 CLKPSC01 Clock Prescaler Clock input is divided by (CLKPSC01 + 1) before it is fed to the corresponding PWM-timer 0 8 read-write DTI01 Dead-zone Interval for Pair of Channel 0 and Channel 1 These 8-bit determine the Dead-zone length. 16 8 read-write CMPDAT0 BPWM_CMPDAT0 Basic PWM Comparator Register 0 0x10 -1 read-write n 0x0 0x0 CMP PWM Comparator Register CMP determines the PWM duty. Note: Any write to PERIOD will take effect in next PWM cycle. 0 16 read-write CMPDAT1 BPWM_CMPDAT1 Basic PWM Comparator Register 1 0x1C -1 read-write n 0x0 0x0 CNT0 BPWM_CNT0 Basic PWM Data Register 0 0x14 -1 read-only n 0x0 0x0 CNT PWM Data Register User can monitor CNT to know the current value in 16-bit counter. 0 16 read-only CNT1 BPWM_CNT1 Basic PWM Data Register 1 0x20 -1 read-write n 0x0 0x0 CTL BPWM_CTL Basic PWM Control Register 0x8 -1 read-write n 0x0 0x0 BKODB0 BPWM Channel 1 Brake Output Selection Note: This bit effects BPWM0 only when BP0SYNEPWM is set 16 1 read-write 0 BPWM0 output low when fault brake conditions asserted #0 1 BPWM0 output high when fault brake conditions asserted #1 BKODB1 BPWM Channel 1 Brake Output Selection Note: This bit effects BPWM1 only when BP1SYNEPWM is set 17 1 read-write 0 BPWM1 output low when fault brake conditions asserted #0 1 BPWM1 output high when fault brake conditions asserted #1 BP0SYNEPWM 24 1 read-write 1 When EPWM enable will also enable BPWM0 at the same time #1 BP1SYNEPWM 25 1 read-write 1 When EPWM enable will also enable BPWM1 at the same time #1 CMPINV0 PWM-timer 0 Output Inverter Enable Control 2 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 CMPINV1 PWM-timer 1 Output Inverter Enable Control 10 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 CNTEN0 PWM-timer 0 Enable Control 0 1 read-write 0 The corresponding PWM-Timer stops running #0 1 The corresponding PWM-Timer starts running #1 CNTEN1 PWM-timer 1 Enable Control 8 1 read-write 0 Corresponding PWM-Timer Stopped #0 1 Corresponding PWM-Timer Start Running #1 CNTMODE0 PWM-timer 0 Auto-reload/One-shot Mode Note: If there is a transition at this bit, it will cause BPWM_PERIOD0 and BPWM_CMPDAT0 be cleared. 3 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CNTMODE1 PWM-timer 1 Auto-reload/One-shot Mode Note: If there is a transition at this bit, it will cause BPWM_PERIOD1 and BPWM_CMPDAT1 be cleared. 11 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CNTTYPE01 PWM01 Aligned Type Selection 30 1 read-write 0 Edge-aligned type #0 1 Center-aligned type #1 DTCNT01 Dead-zone 0 Generator Enable Control Note: When Dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair. 4 1 read-write 0 Dead-zone 0 Generator Disabled #0 1 Dead-zone 0 Generator Enabled #1 PINV0 PWM-timer 0 Output Polar Inverse Enable Control 1 1 read-write 0 PWM0 output polar inverse Disabled #0 1 PWM0 output polar inverse Enabled #1 PINV1 PWM-timer 1 Output Polar Inverse Enable Control 9 1 read-write 0 PWM1 output polar inverse Disabled #0 1 PWM1 output polar inverse Enabled #1 INTEN BPWM_INTEN Basic PWM Interrupt Enable Register 0x40 -1 read-write n 0x0 0x0 DIEN0 BPWM Channel 0 Duty Interrupt Enable Control 8 1 read-write 0 BPWM Channel 0 Duty Interrupt Disabled #0 1 BPWM Channel 0 Duty Interrupt Enabled #1 DIEN1 BPWM Channel 1 Duty Interrupt Enable Control 9 1 read-write 0 BPWM Channel 1 Duty Interrupt Disabled #0 1 BPWM Channel 1 Duty Interrupt Enabled #1 PIEN0 BPWM Channel 0 Period Interrupt Enable Control 0 1 read-write 0 BPWM Channel 0 Period Interrupt Disabled #0 1 BPWM Channel 0 Period Interrupt Enabled #1 PIEN1 BPWM Channel 1 Period Interrupt Enable Control 1 1 read-write 0 BPWM Channel 1 Period Interrupt Disabled #0 1 BPWM Channel 1 Period Interrupt Enabled #1 PINTTYPE BPWM Interrupt Period Type Selection Note: This bit is effective when BPWM in Center-aligned type only. 16 1 read-write 0 PIFn will be set if BPWM counter underflow #0 1 PIFn will be set if BPWM counter matches PERIODn register #1 INTSTS BPWM_INTSTS Basic PWM Interrupt Indication Register 0x44 -1 read-write n 0x0 0x0 DIF0 BPWM Channel 0 Duty Interrupt Flag Flag is set by hardware when channel 0 BPWM counter down count and reaches BPWM_CMPDAT 0, software can clear this bit by writing a one to it. Note: If CMP equal to PERIOD, this flag is not working in Edge-aligned type selection 8 1 read-write DIF1 BPWM Channel 1 Duty Interrupt Flag Flag is set by hardware when channel 1 BPWM counter down count and reaches BPWM_CMPDAT 1, software can clear this bit by writing a one to it. Note: If CMP equal to PERIOD, this flag is not working in Edge-aligned type selection 9 1 read-write PIF0 BPWM Channel 0 Period Interrupt Status This bit is set by hardware when BPWM0 counter reaches the requirement of interrupt (depend on PINTTYPE bit of PWM_INTEN register), software can write 1 to clear this bit to 0. 0 1 read-write PIF1 BPWM Channel 1 Period Interrupt Status This bit is set by hardware when BPWM1 counter reaches the requirement of interrupt (depend on PINTTYPE bit of PWM_INTEN register), software can write 1 to clear this bit to 0. 1 1 read-write PERIOD0 BPWM_PERIOD0 Basic PWM Period Counter Register 0 0xC -1 read-write n 0x0 0x0 PERIOD Basic PWM Period Counter Register PERIOD data determines the PWM period. For Edge-aligned type: Note: Any write to PERIOD will take effect in next PWM cycle. Note: When PWM operating at Center-aligned type, PERIOD value should be set between 0x0000 to 0xFFFE. If PERIOD equal to 0xFFFF, the PWM will work unpredictable. Note: When PERIOD value is set to 0, PWM output is always high. 0 16 read-write PERIOD1 BPWM_PERIOD1 Basic PWM Period Counter Register 1 0x18 -1 read-write n 0x0 0x0 CLK CLK Register Map CLK 0x0 0x0 0xC registers n 0x10 0x8 registers n 0x20 0x4 registers n 0x50 0x4 registers n 0x60 0x4 registers n AHBCLK CLK_AHBCLK AHB Devices Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 GDMACKEN Gereral Direct Memory Access Controller Clock Enable Control 8 1 read-write 0 GDMA clock Disabled #0 1 GDMA clock Enabled #1 HDIVCKEN Hardware Divider Controller Clock Enable Control 4 1 read-write 0 HDIV peripheral clock Disabled #0 1 HDIV peripheral clock Enabled #1 ISPCKEN Flash ISP Controller Clock Enable Control 2 1 read-write 0 Flash ISP peripheral clock Disabled #0 1 Flash ISP peripheral clock Enabled #1 APBCLK CLK_APBCLK APB Devices Clock Enable Control Register 0x8 -1 read-write n 0x0 0x0 ACMPCKEN Analog Comparator Clock Enable Control 30 1 read-write 0 Analog comparator clock Disabled #0 1 Analog comparator clock Enabled #1 ADCCKEN Analog-digital-converter (ADC) Clock Enable Control 28 1 read-write 0 ADC clock Disabled #0 1 ADC clock Enabled #1 BPWMCKEN Basic PWM Channel 0/1 Clock Enable Control 23 1 read-write 0 BBPWM channel 0/1 clock Disabled #0 1 BPWM channel 0/1 clock Enabled #1 CLKOCKEN CLKO Clock Enable Control 6 1 read-write 0 CLKO clock Disabled #0 1 CLKO clock Enabled #1 ECAPCKEN Input Capture Clock Enable Control 8 1 read-write 0 CAP clock Disabled #0 1 CAP clock Enabled #1 EPWMCKEN Enhanced PWM Clock Enable Control 20 1 read-write 0 EPWM channel 0/1 clock Disabled #0 1 EPWM channel 0/1 clock Enabled #1 OPCKEN OP Clock Enable Control 12 1 read-write 0 OP clock Disabled #0 1 OP clock Enabled #1 TMR0CKEN Timer0 Clock Enable Control 2 1 read-write 0 Timer0 clock Disabled #0 1 Timer0 clock Enabled #1 TMR1CKEN Timer1 Clock Enable Control 3 1 read-write 0 Timer1 clock Disabled #0 1 Timer1 clock Enabled #1 TMR2CKEN Timer2 Clock Enable Control 4 1 read-write 0 Timer2 clock Disabled #0 1 Timer2 clock Enabled #1 USCI1CKEN USCI1 Clock Enable Control 25 1 read-write 0 USCI1 clock Disabled #0 1 USCI1 clock Enabled #1 USCI2CKEN USCI2 Clock Enable Control 26 1 read-write 0 USCI2 clock Disabled #0 1 USCI2 clock Enabled #1 WDTCKEN Watchdog Timer Clock Enable Control (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Watchdog timer clock Disabled #0 1 Watchdog timer clock Enabled #1 CLKDIV CLK_CLKDIV Clock Divider Number Register 0x20 -1 read-write n 0x0 0x0 HCLKDIV HCLK Clock Divide Number From HCLK Clock Source 0 4 read-write CLKOCTL CLK_CLKOCTL Clock Output Control Register 0x60 -1 read-write n 0x0 0x0 CLKOEN Clock Output Enable Control 4 1 read-write 0 Clock Output function Disabled #0 1 Clock Output function Enabled #1 DIV1EN Clock Output Divide One Enable Control 5 1 read-write 0 Clock Output will output clock with source frequency divided by FREQSEL #0 1 Clock Output will output clock with source frequency #1 FREQSEL Clock Output Frequency Selection The formula of output frequency is Fin is the input clock frequency. Fout is the frequency of divider output clock. N is the 4-bit value of FREQSEL[3:0]. 0 4 read-write CLKSEL0 CLK_CLKSEL0 Clock Source Select Control Register 0 0x10 -1 read-write n 0x0 0x0 HCLKSEL HCLK Clock Source Selection (Write Protect) Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 2 read-write 0 Clock source from EXT_CLK #00 1 Clock source from LIRC #01 2 Reserved. #10 3 Clock source from HIRC #11 STCLKSEL Cortex-M0 SysTick Clock Source Selection (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3 2 read-write 0 Clock source from EXT_CLK #00 1 Clock source from EXT_CLK/2 #01 2 Clock source from HCLK/2 #10 3 Clock source from HIRC/2 #11 CLKSEL1 CLK_CLKSEL1 Clock Source Select Control Register 1 0x14 -1 read-write n 0x0 0x0 CLKOSEL Clock Divider Clock Source Selection 30 2 read-write 0 Clock source from external clock input (EXT_CLK) #00 1 Reserved. #01 2 Clock source from HCLK #10 3 Clock source from 48(60) MHz internal high speed RC oscillator (HIRC) #11 TMR0SEL TIMER0 Clock Source Selection 8 3 read-write 0 Clock source from external clock input (EXT_CLK) #000 1 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #001 2 Clock source from HCLK #010 3 Clock source from external clock T0 pin #011 4 Clock source from 48(60) MHz internal high speed RC oscillator (HIRC) #100 TMR1SEL TIMER1 Clock Source Selection 12 3 read-write 0 Clock source from external clock input (EXT_CLK) #000 1 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #001 2 Clock source from HCLK #010 3 Clock source from external clock T1 pin #011 4 Clock source from 48(60) MHz internal high speed RC oscillator (HIRC) #100 TMR2SEL TIMER2 Clock Source Selection 16 3 read-write 0 Clock source from external clock input (EXT_CLK) #000 1 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #001 2 Clock source from HCLK #010 3 Clock source from external clock T2 pin #011 4 Clock source from 48(60) MHz internal high speed RC oscillator (HIRC) #100 WDTSEL Watchdog Timer Clock Source Selection (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 2 read-write 0 Clock source from external clock input (EXT_CLK) #00 1 Reserved. #01 2 Clock source from HCLK0/2048 #10 3 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #11 PWRCTL CLK_PWRCTL System Power-down Control Register 0x0 -1 read-write n 0x0 0x0 EXTCLKEN External Clock Enable Control (Write Protect) These two bits are default set to '00' and EXT_CLK(PC.3) pins are GPIO. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 2 read-write 0 Disable external EXT_CLK #00 1 Reserved. #01 2 Reserved. #10 3 Enable external EXT_CLK #11 HIRCEN HIRC Enable Control (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 48(60) MHz internal high speed RC oscillator (HIRC) Disabled #0 1 48(60) MHz internal high speed RC oscillator (HIRC) Enabled #1 HIRCSEL 0: Internal High Speed RC Oscillator Clock Will Output 48MHz 1: Internal high speed RC oscillator clock will output 60MHz 24 1 read-write LIRCEN LIRC Enable Control (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 10 kHz internal low speed RC oscillator (LIRC) Disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) Enabled #1 PDEN System Power-down Enable Control (Write Protect) When this bit is set to 1, Power-down mode is enabled. When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down. In Power-down mode, EXT_CLK and HIRC will be disabled. In Power-down mode, the system clocks are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode if the peripheral clock source is from LIRC. LIRC is controlled by bit LIRCEN. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Chip operating normally or chip in idle mode because of WFI/WFE command #0 1 Chip enters Power-down mode when CPU sleep command WFI/WFE #1 PDMODE 00: LDO Off When Power Down Mode 01: LDO on when power down node 14 2 read-write PDWKDLY Wake-up Delay Counter Enable Control (Write Protect) When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip works at external clock input(EXT_CLK), and 256 clock cycles when chip works at 48(60) MHz internal high speed RC oscillator (HIRC). Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 Clock cycles delay Disabled #0 1 Clock cycles delay Enabled #1 PDWKIEN Power-down Mode Wake-up Interrupt Enable Control (Write Protect) Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high. Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 Power-down mode wake-up interrupt Disabled #0 1 Power-down mode wake-up interrupt Enabled #1 PDWKIF Power-down Mode Wake-up Interrupt Status Set by 'Power-down wake-up event', it indicates that resume from 'Power-down mode' The flag is set if the GPIO, USCIx, WDT, ACMPx, BOD, TMRx wake-up occurred. Note1: Write 1 to clear the bit to 0. Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. 6 1 read-write STATUS CLK_STATUS Clock Status Monitor Register 0x50 -1 read-only n 0x0 0x0 CLKSFAIL Clock Switching Fail Flag (Read Only) This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1. Note: Write 1 to clear the bit to 0. 7 1 read-only 0 Clock switching success #0 1 Clock switching failure #1 HIRCSTB HIRC Clock Source Stable Flag (Read Only) 4 1 read-only 0 48(60) MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled #0 1 48(60) MHz internal high speed RC oscillator (HIRC) clock is stable and enabled #1 LIRCSTB LIRC Clock Source Stable Flag (Read Only) 3 1 read-only 0 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled #1 REXCLKSTB External Clock Source Stable Flag (Read Only) 0 1 read-only 0 External clock is not stable or disabled #0 1 External clock is stable and enabled #1 ECAP ECAP Register Map ECAP 0x0 0x0 0x24 registers n CNT ECAP_CNT Input Capture Counter 0x0 -1 read-write n 0x0 0x0 CNT Input Capture Timer/Counter (24-bit Up Counter) The input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider output which the ECAP_CLK is divided by 1, 4, 16, 32, 64, 96, 112 or 128. 0 24 read-write CNTCMP ECAP_CNTCMP Input Capture Counter Compare Register 0x10 -1 read-write n 0x0 0x0 CNTCMP Input Capture Counter Compare Register 0 24 read-write CTL0 ECAP_CTL0 Input Capture Control Register 0 0x14 -1 read-write n 0x0 0x0 CAP0SEL CAP0 Input Source Selection 8 2 read-write 0 CAP0 input is from port pin ECAP_P0 #00 1 CAP0 input is from signal ACMP_CO0 (Analog comparator 0 output) #01 2 Reserved. #10 3 Reserved. #11 CAP1SEL CAP1 Input Source Selection 10 2 read-write 0 CAP1 input is from port pin ECAP_P1 #00 1 CAP1 input is from signal ACMP_CO0 (Analog comparator 0 output) #01 2 Reserved. #10 3 Reserved. #11 CAP2SEL CAP2 Input Source Selection 12 2 read-write 0 CAP2 input is from port pin ECAP_P2 #00 1 CAP2 input is from signal ACMP_CO0 (Analog comparator 0 output) #01 2 Reserved. #10 3 Reserved. #11 CAPCMPIEN Enable CAPCMPF Trigger Input Capture Interrupt 21 1 read-write 0 Disabling flag CAPCMPF can trigger Input Capture interrupt #0 1 Enabling flag CAPCMPF can trigger Input Capture interrupt #1 CAPEN Input Capture Timer/Counter Enable Control 29 1 read-write 0 Input Capture function Disabled #0 1 Input Capture function Enabled #1 CAPNFDIS Disable Input Capture Noise Filter 3 1 read-write 0 Noise filter of Input Capture Enabled #0 1 The noise filter of Input Capture Disabled #1 CAPOVIEN Enable CAPOVF Trigger Input Capture Interrupt 20 1 read-write 0 Disabling flag CAPOVF can trigger Input Capture interrupt #0 1 Enabling flag CAPOVF can trigger Input Capture interrupt #1 CAPPHGEN Input Capture Flag Trigger PWM Phase Change Function Enable Control 30 1 read-write 0 CAPTF2 or CAPTF1 or CAPTF0 trigger PWM phase change function Disabled #0 1 CAPTF2 or CAPTF1 or CAPTF0 trigger PWM phase change function Enabled #1 CAPTF0IEN Enable Input Capture Channel 0 Interrupt 16 1 read-write 0 Disabling flag CAPTF0 can trigger Input Capture interrupt #0 1 Enabling flag CAPTF0 can trigger Input Capture interrupt #1 CAPTF1IEN Enable Input Capture Channel 1 Interrupt 17 1 read-write 0 Disabling flag CAPTF1 can trigger Input Capture interrupt #0 1 Enabling flag CAPTF1 can trigger Input Capture interrupt #1 CAPTF2IEN Enable Input Capture Channel 2 Interrupt 18 1 read-write 0 Disabling flag CAPTF2 can trigger Input Capture interrupt #0 1 Enabling flag CAPTF2 can trigger Input Capture interrupt #1 CMPCLR Input Capture Counter Clear by Compare-match Control 25 1 read-write 0 Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Disabled #0 1 Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Enabled #1 CMPEN The Compare Function Enable Control The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set. 28 1 read-write 0 Compare function Disabled #0 1 Compare function Enabled #1 CPTCLR Input Capture Counter Clear by Capture Events Control If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when any one of capture events (CAPTF0~3) occurs. 26 1 read-write 0 Capture events (CAPTF0~3) can clear capture counter (ECAP_CNT) Disabled #0 1 Capture events (CAPTF0~3) can clear capture counter (ECAP_CNT) Enabled #1 CPTST Input Capture Counter Start Bit Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (ECAP_CLK). 24 1 read-write 0 ECAP_CNT stop counting #0 1 ECAP_CNT starts up-counting #1 IC0EN Enable Port Pin IC0 Input to Input Capture Unit 4 1 read-write 0 IC0 input to Input Capture Unit Disabled #0 1 IC0 input to Input Capture Unit Enabled #1 IC1EN Enable Port Pin IC1 Input to Input Capture Unit 5 1 read-write 0 IC1 input to Input Capture Unit Disabled #0 1 IC1 input to Input Capture Unit Enabled #1 IC2EN Enable Port Pin IC2 Input to Input Capture Unit 6 1 read-write 0 IC2 input to Input Capture Unit Disabled #0 1 IC2 input to Input Capture Unit Enabled #1 NFCLKS Noise Filter Clock Pre-divided Selection To determine the sampling frequency of the Noise Filter clock 0 3 read-write 0 ECAP_CLK #000 1 ECAP_CLK / 2 #001 2 ECAP_CLK / 4 #010 3 ECAP_CLK / 16 #011 4 ECAP_CLK / 32 #100 5 ECAP_CLK / 64 #101 6 ECAP_CLK / 128 #110 7 ECAP_CLK / 256 #111 RLDEN The Reload Function Enable Control Setting this bit to enable reload function. If the reload control is enabled, an overflow event (CAPOVF) or capture events (CAPTFx) will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT. 27 1 read-write 0 Reload function Disabled #0 1 Reload function Enabled #1 CTL1 ECAP_CTL1 Input Capture Control Register 1 0x18 -1 read-write n 0x0 0x0 CAPDIV Capture Timer Clock Divide Selection The capture timer clock has a pre-divider with eight divided options controlled by CAPDIV[2:0]. 12 3 read-write 0 ECAP_CLK / 1 #000 1 ECAP_CLK / 4 #001 2 ECAP_CLK / 16 #010 3 ECAP_CLK / 32 #011 4 ECAP_CLK / 64 #100 5 ECAP_CLK / 96 #101 6 ECAP_CLK / 112 #110 7 ECAP_CLK / 128 #111 CAPEDG0 Channel 0 Captured Edge Selection Input capture can detect falling edge change only, rising edge change only or one of both edge change 0 2 read-write 0 Detect rising edge #00 1 Detect falling edge #01 2 Detect either rising or falling edge #10 3 Detect either rising or falling edge #11 CAPEDG1 Channel 1 Captured Edge Selection Input capture can detect falling edge change only, rising edge change only or one of both edge change 2 2 read-write 0 Detect rising edge #00 1 Detect falling edge #01 2 Detect either rising or falling edge #10 3 Detect either rising or falling edge #11 CAPEDG2 Channel 2 Captured Edge Selection Input capture can detect falling edge change only, rising edge change only or one of both edge change 4 2 read-write 0 Detect rising edge #00 1 Detect falling edge #01 2 Detect either rising or falling edge #10 3 Detect either rising or falling edge #11 CNTSRC Capture Timer/Counter Clock Source Selection Select the capture timer/counter clock source 16 2 read-write 0 ECAP_CLK (Default) #00 1 CAP0 #01 2 CAP1 #10 3 CAP2 #11 CPRLDS ECAP_CNT Reload Trigger Source Selection 8 3 read-write 0 CAPTF0 #000 1 CAPTF1 #001 2 CAPTF2 #010 4 CAPOVF #100 CTL2 ECAP_CTL2 Input Capture Control Register 2 0x20 -1 read-write n 0x0 0x0 CLRS0EN CAPTF0 Event Trigger Enable for CPTCLR Event Source 8 1 read-write 0 Disabling flag CAPTF0 can trigger CPTCLR function #0 1 Enabling flag CAPTF0 can trigger CPTCLR function #1 CLRS1EN CAPTF1 Event Trigger Enable for CPTCLR Event Source 9 1 read-write 0 Disabling flag CAPTF1 can trigger CPTCLR function #0 1 Enabling flag CAPTF1 can trigger CPTCLR function #1 CLRS2EN CAPTF2 Event Trigger Enable for CPTCLR Event Source 10 1 read-write 0 Disabling flag CAPTF2 can trigger CPTCLR function #0 1 Enabling flag CAPTF2 can trigger CPTCLR function #1 CPTCLRMS CPTCLR Function Trigger Event Source Mode Selection 12 1 read-write 0 CPTCLR event source in normal mode #0 1 CPTCLR event source in enhanced mode #1 RLDMS RLD Function Trigger Event Source Mode Selection 4 1 read-write 0 RLD event source in normal mode #0 1 RLD event source in enhanced mode #1 RLDOVSEN CAPOVF Event Trigger Enable for RLD Event Source 3 1 read-write 0 Disabling flag CAPOVF can trigger RLD function #0 1 Enabling flag CAPOVF can trigger RLD function #1 RLDS0EN CATF0 Event Trigger Enable for RLD Event Source 0 1 read-write 0 Disabling flag CAPTF0 can trigger RLD function #0 1 Enabling flag CAPTF0 can trigger RLD function #1 RLDS1EN CAPTF1 Event Trigger Enable for RLD Event Source 1 1 read-write 0 Disabling flag CAPTF1 can trigger RLD function #0 1 Enabling flag CAPTF1 can trigger RLD function #1 RLDS2EN CAPTF2 Event Trigger Enable for RLD Event Source 2 1 read-write 0 Disabling flag CAPTF2 can trigger RLD function #0 1 Enabling flag CAPTF2 can trigger RLD function #1 HLD0 ECAP_HLD0 Input Capture Counter Hold Register 0 0x4 -1 read-write n 0x0 0x0 HOLD Input Capture Counter Hold Register When an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register. Each input channel has itself holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. 0 24 read-write HLD1 ECAP_HLD1 Input Capture Counter Hold Register 1 0x8 -1 read-write n 0x0 0x0 HLD2 ECAP_HLD2 Input Capture Counter Hold Register 2 0xC -1 read-write n 0x0 0x0 STS ECAP_STS Input Capture Status Register 0x1C -1 read-write n 0x0 0x0 CAPCMPF Input Capture Compare-match Flag If the input capture compare function is enabled, the flag is set by hardware while capture counter (CNT) up counts and reach to the CNTCMP value. Note: This bit is only cleared by writing 1 to itself through software. 4 1 read-write 0 CNT does not match with CNTCMP value #0 1 CNT counts to the same as CNTCMP value #1 CAPOVF Input Capture Counter Overflow Flag Flag is set by hardware when input capture up counter (CNT) overflows from 0x00FF_FFFF to 0. Note: This bit is only cleared by writing 1 to itself through software. 5 1 read-write 0 No overflow occurs in CNT #0 1 CNT overflows #1 CAPTF0 Input Capture Channel 0 Captured Flag When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. Note: This bit is only cleared by writing 1 to itself through software. 0 1 read-write 0 No valid edge change is detected at CAP0 input #0 1 A valid edge change is detected at CAP0 input #1 CAPTF1 Input Capture Channel 1 Captured Flag When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. Note: This bit is only cleared by writing 1 to itself through software. 1 1 read-write 0 No valid edge change is detected at CAP1 input #0 1 A valid edge change is detected at CAP1 input #1 CAPTF2 Input Capture Channel 2 Captured Flag When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. Note: This bit is only cleared by writing 1 to itself through software. 2 1 read-write 0 No valid edge change is detected at CAP2 input #0 1 A valid edge change is detected at CAP2 input #1 ECAP0 Input Capture Source 0 Status (Read Only) Input capture Source 0 (ECAP_P0) status. It is read only. (The bit is read only and write is ignored) 8 1 read-only ECAP1 Input Capture Source 1 Status (Read Only) Input capture Source 1 (ECAP_P1) status. It is read only. (The bit is read only and write is ignored) 9 1 read-only ECAP2 Input Capture Source 2 Status (Read Only) Input captureSource 2 (ECAP_P2) status. It is read only. (The bit is read only and write is ignored) 10 1 read-only EPWM EPWM Register Map EPWM 0x0 0x0 0x10 registers n 0x24 0x1C registers n 0x54 0x14 registers n 0x78 0x10 registers n BRKCTL EPWM_BRKCTL EPWM Fault Brake Control Register 0x60 -1 read-write n 0x0 0x0 BK0ADCEN BRK0 Source From ADC Enable Control 4 1 read-write 0 BRK0 Source From ADC Disabled #0 1 BRK0 Source From ADC Enabled #1 BK1ADCEN BRK1 Source From ADC Enable Control 12 1 read-write 0 BRK1 Source From ADC Disabled #0 1 BRK1 Source From ADC Enabled #1 BKOD0 PWM Channel 0 Brake Output Selection 24 1 read-write 0 PWM output low when fault brake conditions asserted #0 1 PWM output high when fault brake conditions asserted #1 BKOD1 PWM Channel 1 Brake Output Selection 25 1 read-write 0 PWM output low when fault brake conditions asserted #0 1 PWM output high when fault brake conditions asserted #1 BKOD2 PWM Channel 2 Brake Output Selection 26 1 read-write 0 PWM output low when fault brake conditions asserted #0 1 PWM output high when fault brake conditions asserted #1 BKOD3 PWM Channel 3 Brake Output Selection 27 1 read-write 0 PWM output low when fault brake conditions asserted #0 1 PWM output high when fault brake conditions asserted #1 BKOD4 PWM Channel 4 Brake Output Selection 28 1 read-write 0 PWM output low when fault brake conditions asserted #0 1 PWM output high when fault brake conditions asserted #1 BKOD5 PWM Channel 5 Brake Output Selection 29 1 read-write 0 PWM output low when fault brake conditions asserted #0 1 PWM output high when fault brake conditions asserted #1 BRK0A0EN BRK0 Source From ACMP0 Enable Control 2 1 read-write 0 BRK0 Source From ACMP0 Disabled #0 1 BRK0 Source From ACMP0 Enabled #1 BRK0EN Brake0 Function Enable Control 0 1 read-write 0 Brake0 detect function Disabled #0 1 Brake0 detect function Enabled #1 BRK0PEN BRK0 Source From External Pin Enable Control 5 1 read-write 0 BRK0 Source From External Pin Disabled #0 1 BRK0 Source From External Pin Enabled #1 BRK1A0EN BRK1 Source From ACMP0 Enable Control 10 1 read-write 0 BRK1 Source From ACMP0 Disabled #0 1 BRK1 Source From ACMP0 Enabled #1 BRK1EN Brake1 Function Enable Control 1 1 read-write 0 Brake1 detect function Disabled #0 1 Brake1 detect function Enabled #1 BRK1PEN BRK1 Source From External Pin Enable Control 13 1 read-write 0 BRK1 Source From External Pin Disabled #0 1 BRK1 Source From External Pin Enabled #1 BRKPIN0EN BRK Source From External Pin 0 Enable Control 6 1 read-write 0 BRK Source From External PWM_BRK_P0 Disabled #0 1 BRK Source From External PWM_BRK_P0 Enabled #1 BRKPIN1EN BRK Source From External Pin 1 Enable Control 7 1 read-write 0 BRK Source From External PWM_BRK_P1 Disabled #0 1 BRK Source From External PWM_BRK_P1 Enabled #1 BRKPIN2EN BRK Source From External Pin 2 Enable Control 8 1 read-write 0 BRK Source From External PWM_BRK_P2 Disabled #0 1 BRK Source From External PWM_BRK_P2 Enabled #1 LVDBKEN Low-level Detection Trigger PWM Brake Function 1 Enable Control 14 1 read-write 0 Brake Function 1 triggered by Low-level detection Disabled #0 1 Brake Function 1 triggered by Low-level detection Enabled #1 LVDTYPE Low-level Detection Resume Type 15 1 read-write 0 Brake resume at BRK resume delay counter counting to 0 #0 1 Brake resume at period edge #1 NFCLKSEL Noise Filter Clock Pre-divide Selection To determine the sampling frequency of the Noise Filter clock. 20 3 read-write 0 EPWM_CLK #000 1 EPWM _CLK/2 #001 2 EPWM _CLK/4 #010 3 EPWM _CLK/8 #011 4 EPWM _CLK/16 #100 5 EPWM _CLK/32 #101 6 EPWM _CLK/64 #110 7 EPWM _CLK/128 #111 NFPEN Noise Filter for External Brake Input Pin (BRAKE) Enable Control 31 1 read-write 0 Noise Filter for External Brake Input Pin (BRAKE) Disabled #0 1 Noise Filter for External Brake Input Pin (BRAKE) Enabled #1 SWBRK Software Break 9 1 read-write 0 Software break and back to normal PWM function Disabled #0 1 Issue Software break Enabled #1 CLKDIV EPWM_CLKDIV EPWM Clock Select Register 0x4 -1 read-write n 0x0 0x0 CLKDIV EPWM Clock Divider (9 Step Divider) Select clock input for PWM timer 0 4 read-write 0 1 (HCLK / 2^0) #0000 1 1/2 (HCLK / 2^1) #0001 2 1/4 (HCLK / 2^2) #0010 3 1/8 (HCLK / 2^3) #0011 4 1/16 (HCLK / 2^4) #0100 5 1/32 (HCLK / 2^5) #0101 6 1/64 (HCLK / 2^6) #0110 7 1/128 (HCLK / 2^7) #0111 8 1/256 (HCLK / 2^8) #1000 CMPDAT0 EPWM_CMPDAT0 EPWM Comparator Register 0 0x24 -1 read-write n 0x0 0x0 CMP PWM Comparator Register CMP determines the PWM Duty. Edge-aligned mode: where xy, could be 01, 23, 45 depending on the selected PWM channel. Note: Any write to CMPn will take effect in next PWM cycle. 0 16 read-write CMPU PWM Comparator Register for UP Counter in Center-aligned Asymmetric Mode CMPU PERIOD: @ up counter PWM output is keep to Max. duty. 16 16 read-write CMPDAT1 EPWM_CMPDAT1 EPWM Comparator Register 1 0x28 -1 read-write n 0x0 0x0 CMPDAT2 EPWM_CMPDAT2 EPWM Comparator Register 2 0x2C -1 read-write n 0x0 0x0 CMPDAT3 EPWM_CMPDAT3 EPWM Comparator Register 3 0x30 -1 read-write n 0x0 0x0 CMPDAT4 EPWM_CMPDAT4 EPWM Comparator Register 4 0x34 -1 read-write n 0x0 0x0 CMPDAT5 EPWM_CMPDAT5 EPWM Comparator Register 5 0x38 -1 read-write n 0x0 0x0 CNT EPWM_CNT EPWM Data Register 0x3C -1 read-only n 0x0 0x0 CNT PWM Data Register User can monitor CNT to know the current value in 16-bit down counter. 0 16 read-only CNTDIR PWM Counter (Up/Down) Direction 31 1 read-only 0 PWM counter is down counting #0 1 PWM counter is up counting #1 CTL EPWM_CTL EPWM Control Register 0x8 -1 read-write n 0x0 0x0 ASYMEN Asymmetric Mode in Center-aligned Type 20 1 read-write 0 Symmetric mode in center-aligned type #0 1 Asymmetric mode in center-aligned type #1 CNTCLR Clear PWM Counter Control Bit Note: It is automatically cleared by hardware. 27 1 read-write 0 Do not clear PWM counter #0 1 16-bit PWM counter cleared to 0x000 #1 CNTEN0 PWM- Generator 0 Enable/Disable Start Run 0 1 read-write 0 Corresponding PWM-timer running Stopped #0 1 Corresponding PWM-timer start run Enabled #1 CNTEN1 PWM- Generator 1 Enable/Disable Start Run 1 1 read-write 0 Corresponding PWM-timer running Stopped #0 1 Corresponding PWM-timer start run Enabled #1 CNTEN2 PWM- Generator 2 Enable/Disable Start Run 2 1 read-write 0 Corresponding PWM-timer running Stopped #0 1 Corresponding PWM-timer start run Enabled #1 CNTEN3 PWM- Generator 3 Enable/Disable Start Run 3 1 read-write 0 Corresponding PWM-timer running Stopped #0 1 Corresponding PWM-timer start run Enabled #1 CNTEN4 PWM- Generator 4 Enable/Disable Start Run 4 1 read-write 0 Corresponding PWM-timer running Stopped #0 1 Corresponding PWM-timer start run Enabled #1 CNTEN5 PWM-generator 5 Enable/Disable Start Run 5 1 read-write 0 Corresponding PWM-timer running Stopped #0 1 Corresponding PWM-timer start run Enabled #1 CNTMODE PWM-timer Auto-reload/One-shot Mode 8 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CNTTYPE PWM Aligned Type Selection 31 1 read-write 0 Edge-aligned type #0 1 Center-aligned type #1 DTCNT01 Dead-zone 0 Generator Enable/Disable (PWM0 and PWM1 Pair for PWM Group) Note: When the dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group. 24 1 read-write 0 Dead-zone 0 Generator Disabled #0 1 Dead-zone 0 Generator Enabled #1 DTCNT23 Dead-zone 2 Generator Enable/Disable (PWM2 and PWM3 Pair for PWM Group) Note: When the dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group. 25 1 read-write 0 Dead-zone 2 Generator Disabled #0 1 Dead-zone 2 Generator Enabled #1 DTCNT45 Dead-zone 4 Generator Enable/Disable (PWM4 and PWM5 Pair for PWM Group) Note: When the dead-zone generator is enabled, the pair of PWM4 and PWM5 becomes a complementary pair for PWM group. 26 1 read-write 0 Dead-zone 4 Generator Disabled #0 1 Dead-zone 4 Generator Enabled #1 GROUPEN Group Bit 30 1 read-write 0 The signals timing of PWM0, PWM2 and PWM4 are independent #0 1 Unify the signals timing of PWM0, PWM2 and PWM4 in the same phase which is controlled by PWM0 #1 HCUPDT Half Cycle Update Enable for Center-aligned Type 16 2 read-write 0 Update PERIOD CMP at pwm_counter = PERIOD (Period) #00 1 Update PERIOD CMP at pwm_counter = 0 #01 2 Update PERIOD CMP at half cycle (counter = 0 PERIOD, both update) #10 3 Update PERIOD CMP at pwm_counter = PERIOD (Period) #11 MODE PWM Operating Mode Selection Note: If th complementary mode is selected, the deadtime insertion is active automatically. 28 2 read-write 0 Independent mode #00 1 Complementary mode #01 2 Reserved. #10 3 Reserved. #11 DTCTL EPWM_DTCTL EPWM Dead-zone Interval Register 0x64 -1 read-write n 0x0 0x0 DTCNT01 Dead-zone Interval Register for Pair of Channel0 and Channel1 (PWM0 and PWM1 Pair) These 8 bits determine dead-zone length. The unit time of dead-zone length is received from corresponding EPWM_CLKDIV bits. 0 8 read-write DTCNT23 Dead-zone Interval Register for Pair of Channel2 and Channel3 (PWM2 and PWM3 Pair) These 8 bits determine dead-zone length. The unit time of dead-zone length is received from corresponding EPWM_CLKDIV bits. 8 8 read-write DTCNT45 Dead-zone Interval Register for Pair of Channel4 and Channel5 (PWM4 and PWM5 Pair) These 8 bits determine dead-zone length. The unit time of dead-zone length is received from corresponding EPWM_CLKDIV bits. 16 8 read-write IFA EPWM_IFA EPWM Period Interrupt Accumulation Control Register 0x84 -1 read-write n 0x0 0x0 IFAEN Enable Period Interrupt Accumulation Function 0 1 read-write 0 Period Interrupt Accumulation Disabled #0 1 Period Interrupt Accumulation Enabled #1 IFCNT Period Interrupt Accumulation Counter Value Setting Register (Write Only) 16 step Down-Counter value setting register. When IFAEN is set, IFCNT value will load into IFDAT and decrase gradually. 4 4 write-only IFDAT Period Interrupt Down-counter Data Register (Read Only) When IFAEN is set, IFDAT will decrease when every PWM Interrupt flag is set, and when IFDAT reaches 0, the PWM interrupt will occurred and IFCNT will reload to IFDAT. 12 4 read-only INTEN EPWM_INTEN EPWM Interrupt Enable Register 0x54 -1 read-write n 0x0 0x0 BRK0IEN Fault Brake0 Interrupt Enable Control 16 1 read-write 0 BRK0IF trigger PWM interrupt Disabled #0 1 BRK0IF trigger PWM interrupt Enabled #1 BRK1IEN Fault Brake1 Interrupt Enable Control 17 1 read-write 0 BRK1IF trigger PWM interrupt Disabed #0 1 BRK1IF trigger PWM interrupt Enabled #1 CIEN PWM Central Interrupt Enable Control for Center-aligned only 18 1 read-write 0 Interruptwhen EPWM Central Enabled #0 1 Interruptwhen EPWM Central Enabled #1 CMPDIEN0 PWM Channel 0 DOWN Interrupt Enable Control DOWN for Edge-aligned and Center-aligned 24 1 read-write 0 Interruptcompare Disabled #0 1 interruptwhen EPWM_CH0 PWM DOWN counter reaches EPWM_CMPDAT0 Enabled #1 CMPDIEN1 PWM Channel 1 DOWN Interrupt Enable Control DOWN for Edge-aligned and Center-aligned 25 1 read-write 0 Interruptcompare Disabled #0 1 interruptwhen EPWM_CH1 PWM DOWN counter reaches EPWM_CMPDAT1 Enabled #1 CMPDIEN2 PWM Channel 2 DOWN Interrupt Enable Control DOWN for Edge-aligned and Center-aligned 26 1 read-write 0 Interruptcompare Disabled #0 1 interruptwhen EPWM_CH2 PWM DOWN counter reaches EPWM_CMPDAT2 Enabled #1 CMPDIEN3 PWM Channel 3 DOWN Interrupt Enable Control DOWN for Edge-aligned and Center-aligned 27 1 read-write 0 Interruptcompare Disabled #0 1 interruptwhen EPWM_CH3 PWM DOWN counter reaches EPWM_CMPDAT3 Enabled #1 CMPDIEN4 PWM Channel 4 DOWN Interrupt Enable Control DOWN for Edge-aligned and Center-aligned 28 1 read-write 0 Interruptcompare Disabled #0 1 interruptwhen EPWM_CH4 PWM DOWN counter reaches EPWM_CMPDAT4 Enabled #1 CMPDIEN5 PWM Channel 5 DOWN Interrupt Enable Control DOWN for Edge-aligned and Center-aligned 29 1 read-write 0 Interruptcompare Disabled #0 1 Interruptwhen EPWM_CH5 PWM DOWN counter reaches EPWM_CMPDAT5 Enabled #1 CMPUIEN0 PWM Channel 0 UP Interrupt Enable Control UP for Center-aligned only 8 1 read-write 0 EPWM_CH0 PWM UP counter reaches EPWM_CMPDAT0 interruptDisabled #0 1 EPWM_CH0 PWM UP counter reaches EPWM_CMPDAT0 interruptEnabled #1 CMPUIEN1 PWM Channel 1 UP Interrupt Enable Control UP for Center-aligned only 9 1 read-write 0 EPWM_CH1 PWM UP counter reaches EPWM_CMPDAT1 interruptDisabled #0 1 EPWM_CH1 PWM UP counter reaches EPWM_CMPDAT1 interruptEnabled #1 CMPUIEN2 PWM Channel 2 UP Interrupt Enable Control UP for Center-aligned only 10 1 read-write 0 EPWM_CH2 PWM UP counter reaches EPWM_CMPDAT2 interruptDisabled #0 1 EPWM_CH2 PWM UP counter reaches EPWM_CMPDAT2 interruptEnabled #1 CMPUIEN3 PWM Channel 3 UP Interrupt Enable Control UP for Center-aligned only 11 1 read-write 0 EPWM_CH3 PWM UP counter reaches EPWM_CMPDAT3 interruptDisabled #0 1 EPWM_CH3 PWM UP counter reaches EPWM_CMPDAT3 interruptEnabled #1 CMPUIEN4 PWM Channel 4 UP Interrupt Enable Control UP for Center-aligned only 12 1 read-write 0 EPWM_CH4 PWM UP counter reaches EPWM_CMPDAT4 interrupt Disabled #0 1 EPWM_CH4 PWM UP counter reaches EPWM_CMPDAT4 interrupt Enabled #1 CMPUIEN5 PWM Channel 5 UP Interrupt Enable Control UP for Center-aligned only 13 1 read-write 0 PWM Channel 5 UP Interrupt Disabled #0 1 Interruptwhen EPWM_CH5 PWM UP counter reaches EPWM_CMPDAT5 Enabled #1 PIEN PWM Channel 0 Period Interrupt Enable Control for Edge-aligned and Center-aligned 0 1 read-write 0 EPWM Period interruptDisabled #0 1 EPWM Period interruptEnabled #1 INTSTS EPWM_INTSTS EPWM Interrupt Status Register 0x58 -1 read-write n 0x0 0x0 BRK0IF PWM Brake0 Flag Note: Software can write 1 to clear this bit. 16 1 read-write 0 PWM Brake does not recognize a falling signal at BKP0 #0 1 When PWM Brake detects a falling signal at pin BKP0, this flag will be set to high #1 BRK0LOCK PWM Brake0 Locked Note: Software can write 1 to clear this bit. 19 1 read-write 0 PWM Brake does not recognize a falling signal at BKP0 #0 1 When PWM Brake detects a falling signal at pin BKP0, this flag will be set to high, when this bit set high, it helps breaking PWM output even interrupt flag BRK0IF was cleared by CPU before jumping out from sub-routine #1 BRK1IF PWM Brake1 Flag Note: Software can write 1 to clear this bit. 17 1 read-write 0 PWM Brake does not recognize a falling signal at BKP1 #0 1 When PWM Brake detects a falling signal at pin BKP1, this flag will be set to high #1 BRKP0IF BRK Pin0 Status Flag Flag is set by pin PWM_BRK_P0 with low pulse event. Software can write 1 to clear this bit. 20 1 read-write BRKP1IF BRK Pin1 Status Flag Flag is set by pin PWM_BRK_P1 with low pulse event. Software can write 1 to clear this bit. 21 1 read-write BRKP2IF BRK Pin2 Status Flag Flag is set by pin PWM_BRK_P2 with low pulse event. Software can write 1 to clear this bit. 22 1 read-write CIF PWM Channel 0 Central Interrupt Flag Flag is set by hardware when PWM down counter reaches zero point. Software can write 1 to clear this bit. 18 1 read-write CMPDIF0 PWM Channel 0 DOWN Interrupt Flag Flag is set by hardware when a channel 0 PWM DOWN counter reaches EPWM_CMPDAT0. Software can write 1 to clear this bit. 24 1 read-write CMPDIF1 PWM Channel 1 DOWN Interrupt Flag Flag is set by hardware when a channel 1 PWM DOWN counter reaches EPWM_CMPDAT1. Software can write 1 to clear this bit. 25 1 read-write CMPDIF2 PWM Channel 2 DOWN Interrupt Flag Flag is set by hardware when a channel 2 PWM DOWN counter reaches EPWM_CMPDAT2. Software can write 1 to clear this bit. 26 1 read-write CMPDIF3 PWM Channel 3 DOWN Interrupt Flag Flag is set by hardware when a channel 3 PWM DOWN counter reaches EPWM_CMPDAT3. Software can write 1 to clear this bit. 27 1 read-write CMPDIF4 PWM Channel 4 DOWN Interrupt Flag Flag is set by hardware when a channel 4 PWM DOWN counter reaches EPWM_CMPDAT4. Software can write 1 to clear this bit. 28 1 read-write CMPDIF5 PWM Channel 5 DOWN Interrupt Flag Flag is set by hardware when a channel 5 PWM DOWN counter reaches EPWM_CMPDAT5. Software can write 1 to clear this bit. 29 1 read-write CMPUIF0 PWM Channel 0 UP Interrupt Flag Flag is set by hardware when a channel 0 PWM UP counter reaches PWM_CMPDAT0. Software can write 1 to clear this bit. 8 1 read-write CMPUIF1 PWM Channel 1 UP Interrupt Flag Flag is set by hardware when a channel 1 PWM UP counter reaches PWM_CMPDAT1. Software can write 1 to clear this bit. 9 1 read-write CMPUIF2 PWM Channel 2 UP Interrupt Flag Flag is set by hardware when a channel 2 PWM UP counter reaches PWM_CMPDAT2. Software can write 1 to clear this bit. 10 1 read-write CMPUIF3 PWM Channel 3 UP Interrupt Flag Flag is set by hardware when a channel 3 PWMUP counter reaches PWM_CMPDAT3. Software can write 1 to clear this bit. 11 1 read-write CMPUIF4 PWM Channel 4 UP Interrupt Flag Flag is set by hardware when a channel 4 PWM UP counter reaches PWM_CMPDAT4. Software can write 1 to clear this bit. 12 1 read-write CMPUIF5 PWM Channel 5 UP Interrupt Flag Flag is set by hardware when a channel 5 PWM UP counter reaches PWM_CMPDAT5. Software can write 1 to clear this bit. 13 1 read-write PIF PWM Channel 0 Period Interrupt Flag Edge-aligned mode: Flag is set by hardware when PWM down counter reaches zero point. Center-aligned mode: Flag is set by hardware when PWM down counter reaches zero point and then up counter reaches EPWM_PERIOD. Software can write 1 to clear this bit. 0 1 read-write NPCTL EPWM_NPCTL EPWM Negative Polarity Control Register 0x0 -1 read-write n 0x0 0x0 NEGPOLAR0 PWM0 Negative Polarity Control The register bit controls polarity/active state of real PWM output. 0 1 read-write 0 PWM output is active high #0 1 PWM output is active low #1 NEGPOLAR1 PWM1 Negative Polarity Control The register bit controls polarity/active state of real PWM output. 1 1 read-write 0 PWM output is active high #0 1 PWM output is active low #1 NEGPOLAR2 PWM2 Negative Polarity Control The register bit controls polarity/active state of real PWM output. 2 1 read-write 0 PWM output is active high #0 1 PWM output is active low #1 NEGPOLAR3 PWM3 Negative Polarity Control The register bit controls polarity/active state of real PWM output. 3 1 read-write 0 PWM output is active high #0 1 PWM output is active low #1 NEGPOLAR4 PWM4 Negative Polarity Control The register bit controls polarity/active state of real PWM output. 4 1 read-write 0 PWM output is active high #0 1 PWM output is active low #1 NEGPOLAR5 PWM5 Negative Polarity Control The register bit controls polarity/active state of real PWM output. 5 1 read-write 0 PWM output is active high #0 1 PWM output is active low #1 PERIOD EPWM_PERIOD EPWM Period Counter Register 0xC -1 read-write n 0x0 0x0 PERIOD PWM Counter/Timer Loaded Value PERIODn determines the PWM Period. Edge-aligned mode: where xy, could be 01, 23, 45 depending on the selected PWM channel. Note: Any write to PERIODn will take effect in next PWM cycle. 0 16 read-write PHCHG EPWM_PHCHG EPWM Phase Changed Register 0x78 -1 read-write n 0x0 0x0 A0POSSEL Alternative Comparator 0 Positive Input Selection Select the positive input source of ACMP0. 24 2 read-write 0 Select ACMP0_P0 (PB.0) as the input of ACMP0 #00 1 Select ACMP0_P1 (PB.1) as the input of ACMP0 #01 2 Select ACMP0_P2 (PB.2) as the input of ACMP0 #10 3 Select ACMP0_P3 (PC.1) as the input of ACMP0 #11 ACMP0TEN ACMP0 Trigger Function Enable Control 28 1 read-write 0 ACMP0 trigger PWM function Disabled #0 1 ACMP0 trigger PWM function Enabled #1 BMSKDAT0 Enable BPWM0 Mask Data Note: This bit effects BPWM0 only when BPWM_CTL.BP0SYNEPWM is set 6 1 read-write 0 BPWM0 state is masked with zero #0 1 BPWM0 state is masked with one #1 BMSKDAT1 Enable BPWM1 Mask Data Note: This bit effects BPWM1 only when BPWM_CTL.BP1SYNEPWM is set 7 1 read-write 0 BPWM1 state is masked with zero #0 1 BPWM1 state is masked with one #1 BMSKEN0 Enable BPWM0 Mask Function Note: This bit effects BPWM0 only when BPWM_CTL.BP0SYNEPWM is set 14 1 read-write 0 BPWM0 Mask Function Disabled #0 1 BPWM0 Mask Function Enabled #1 BMSKEN1 Enable BPWM1 Mask Function Note: This bit effects BPWM1 only when BPWM_CTL.BP1SYNEPWM is set 15 1 read-write 0 BPWM1 Mask Function Disabled #0 1 BPWM1 Mask Function Enabled #1 MSKDAT0 Enable PWM0 Mask Data 0 1 read-write 0 PWM0 state is masked with zero #0 1 PWM0 state is masked with one #1 MSKDAT1 Enable PWM1 Mask Data 1 1 read-write 0 PWM1 state is masked with zero #0 1 PWM1 state is masked with one #1 MSKDAT2 Enable PWM2 Mask Data 2 1 read-write 0 PWM2 state is masked with zero #0 1 PWM2 state is masked with one #1 MSKDAT3 Enable PWM3 Mask Data 3 1 read-write 0 PWM3 state is masked with zero #0 1 PWM3 state is masked with one #1 MSKDAT4 Enable PWM4 Mask Data 4 1 read-write 0 PWM4 state is masked with zero #0 1 PWM4 state is masked with one #1 MSKDAT5 Enable PWM5 Mask Data 5 1 read-write 0 PWM5 state is masked with zero #0 1 PWM5 state is masked with one #1 MSKEN0 Enable PWM0 Mask Function 8 1 read-write 0 PWM0 Mask Function Disabled #0 1 PWM0 Mask Function Enabled #1 MSKEN1 Enable PWM1 Mask Function 9 1 read-write 0 PWM1 Mask Function Disabled #0 1 PWM1 Mask Function Enabled #1 MSKEN2 Enable PWM2 Mask Function 10 1 read-write 0 PWM2 Mask Function Disabled #0 1 PWM2 Mask Function Enabled #1 MSKEN3 Enable PWM3 Mask Function 11 1 read-write 0 PWM3 Mask Function Disabled #0 1 PWM3 Mask Function Enabled #1 MSKEN4 Enable PWM4 Mask Function 12 1 read-write 0 PWM4 Mask Function Disabled #0 1 PWM4 Mask Function Enabled #1 MSKEN5 Enable PWM5 Mask Function 13 1 read-write 0 PWM5 Mask Function Disabled #0 1 PWM5 Mask Function Enabled #1 TRGSEL Phase Change Trigger Selection Select the trigger condition to load PHCHG from PHCHG_NXT. When the trigger condition occurs it will load EPWM_PHCHG with PHCHG_NXT. Phase Change: PWM outputs are masked according with the definition of MSKENn and MSKDATn in EPWM_PHCHG. 20 3 read-write 0 Triggered by TMR0_MATCH event #000 1 Triggered by TMR1_MATCH event #001 2 Triggered by CAPPHG_TRG from ECAP. (CAPTF0 | CAPTF1 | CAPTF2) #010 3 Triggered by HALLSTS (EPWM_PHCHGNXT[18:16]) matched (CAP2, CAP1, CAP0) in ECAP.. #011 4 Triggered by ACMP0_PBRK event #100 5 Reserved. #101 6 Triggered by TMR2_MATCH event. #110 7 Auto Phase Change Function Disabled #111 PHCHGALT EPWM_PHCHGALT EPWM Phase Change Alternative Control Register 0x80 -1 read-write n 0x0 0x0 POSCTL0 Positive Input Control for ACMP0 Note: Register ACMP_CTL0 is describe in Comparator Controller chapter 0 1 read-write 0 The input of ACMP0 is controlled by ACMP_CTL0 #0 1 The input of ACMP0 is controlled by A0POSSEL in EPWM_PHCHG register #1 PHCHGNXT EPWM_PHCHGNXT EPWM Next Phase Change Register 0x7C -1 read-write n 0x0 0x0 A0POSSEL Alternative Comparator 0 Positive Input Selection Preset Bits This bit field will be load to bit field A0POSSEL in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. 24 2 read-write ACMP0TEN ACMP0 Trigger Function Control Preset Bit This bit will be load to bit ACMP0TEN in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. 28 1 read-write BMSKDAT0 Enable BPWM0 Mask Data Preset Bit This bit will be load to bit BMSKDAT0 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. Note: This bit effects BPWM0 only when BPWM_CTL.BP0SYNEPWM is set 6 1 read-write BMSKDAT1 Enable BPWM1 Mask Data Preset Bit This bit will be load to bit BMSKDAT1 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. Note: This bit effects BPWM1 only when BPWM_CTL.BP1SYNEPWM is set 7 1 read-write BMSKEN0 Enable BPWM0 Mask Function Preset Bit This bit will be load to bit MSKEN4 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. Note: This bit effects BPWM0 only when BPWM_CTL.BP0SYNEPWM is set 14 1 read-write BMSKEN1 Enable BPWM1 Mask Function Preset Bit This bit will be load to bit MSKEN5 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. Note: This bit effects BPWM1 only when BPWM_CTL.BP1SYNEPWM is set 15 1 read-write HALLSTS Predicted Next HALL State This bit field indicates the predicted hall state at next commutation. the hardware will compare bits (CAP2, CAP1, CAP0) in timer 2 with HALLSTS [2:0] when any hall state change occurs. If the comparison is matched it will trigger phase change function. 16 3 read-write MSKDAT0 Enable PWM0 Mask Data Preset Bit This bit will be load to bit MSKDAT0 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. 0 1 read-write MSKDAT1 Enable PWM1 Mask Data Preset Bit This bit will be load to bit MSKDAT1 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. 1 1 read-write MSKDAT2 Enable PWM2 Mask Data Preset Bit This bit will be load to bit MSKDAT2 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. 2 1 read-write MSKDAT3 Enable PWM3 Mask Data Preset Bit This bit will be load to bit MSKDAT3 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. 3 1 read-write MSKDAT4 Enable PWM4 Mask Data Preset Bit This bit will be load to bit MSKDAT4 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. 4 1 read-write MSKDAT5 Enable PWM5 Mask Data Preset Bit This bit will be load to bit MSKDAT5 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. 5 1 read-write MSKEN0 Enable PWM0 Mask Function Preset Bit This bit will be load to bit MSKEN0 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. 8 1 read-write MSKEN1 Enable PWM1 Mask Function Preset Bit This bit will be load to bit MSKEN1 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. 9 1 read-write MSKEN2 Enable PWM2 Mask Function Preset Bit This bit will be load to bit MSKEN2 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. 10 1 read-write MSKEN3 Enable PWM3 Mask Function Preset Bit This bit will be load to bit MSKEN3 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. 11 1 read-write MSKEN4 Enable PWM4 Mask Function Preset Bit This bit will be load to bit MSKEN4 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. 12 1 read-write MSKEN5 Enable PWM5 Mask Function Preset Bit This bit will be load to bit MSKEN5 in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. 13 1 read-write TRGSEL Phase Change Trigger Selection Preset Bits This bit field will be load to bit field TRGSEL in EPWM_PHCHG when load trigger condition occurs. Refer to register EPWM_PHCHG for detailed definition. 20 3 read-write 0 Triggered by TMR0_MATCH event #000 1 Triggered by TMR1_MATCH event #001 2 Triggered by CAPPHG_TRG from ECAP. (CAPTF0 | CAPTF1 | CAPTF2) #010 3 Triggered by HALLSTS (EPWM_PHCHGNXT[18:16]) matched (CAP2, CAP1, CAP0) in ECAP.. #011 4 Triggered by ACMP0_PBRK event #100 5 Reserved. #101 6 Triggered by TMR2_MATCH event. #110 7 Auto Phase Change Function Disabled #111 RESDLY EPWM_RESDLY EPWM BRK Low Voltage Detect Resume Delay 0x5C -1 read-write n 0x0 0x0 DELAY PWM BRK Low Voltage Detect Resume Delay 12 bits Down-Counter 0 12 read-write FMC FMC Register Map FMC 0x0 0x0 0x18 registers n 0x40 0x4 registers n 0x50 0x8 registers n CRCCV FMC_CRCCV ISP CRC Current Value Register 0x54 -1 read-only n 0x0 0x0 CRCCV CRC Current Value This register provided current value of CRC during calculation. 0 32 read-only CRCSEED FMC_CRCSEED ISP CRC Seed Register 0x50 -1 read-write n 0x0 0x0 CRCSEED CRC Seed Data This register was provided to be the initial value for CRC operation. Write data to this register before ISP CRC operation. Read data from this register after ISP CRC read operation. 0 32 read-write DFBA FMC_DFBA Data Flash Start Address 0x14 -1 read-only n 0x0 0x0 DFBA Data Flash Base Address This register indicates Data Flash start address. It is a read only register. The Data Flash start address is defined by user. Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0. 0 32 read-only ISPADDR FMC_ISPADDR ISP Address Register 0x4 -1 read-write n 0x0 0x0 ISPADR ISP Address The NM1240 series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation. 0 32 read-write ISPCMD FMC_ISPCMD ISP Command Register 0xC -1 read-write n 0x0 0x0 CMD ISP Command ISP commands are shown below: 0 6 read-write 0 Read 0x00 4 Read Unique ID 0x04 11 Read Company ID (0xDA) 0x0b 13 Read CRC32 Checksum Result After Calculating 0x0d 33 Program 0x21 34 Page Erase 0x22 45 Run Memory CRC32 Checksum Calculation 0x2d 46 Set Vector Page Re-Map 0x2e ISPCTL FMC_ISPCTL ISP Control Register 0x0 -1 read-write n 0x0 0x0 APUEN APROM Update Enable Control (Write Protect) 3 1 read-write 0 APROM cannot be updated when chip runs in APROM #0 1 APROM can be updated when chip runs in APROM #1 BS Boot Select (Write Protect) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (CPURF is 1) or system reset (SYSRF) is happened. 1 1 read-write 0 Boot from APROM #0 1 Boot from LDROM #1 CFGUEN CONFIG Update Enable Control (Write Protect) Writing this bit to 1 enables software to update CONFIG value by ISP register control procedure regardless of program code is running in APROM or LDROM. 4 1 read-write 0 ISP update User Configuration Disabled #0 1 ISP update User Configuration Enabled #1 ISPEN ISP Enable Control (Write Protect) Set this bit to enable ISP function. 0 1 read-write 0 ISP function Disabled #0 1 ISP function Enabled #1 ISPFF ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself if APUEN is set to 0. (2) LDROM writes to itself if LDUEN is set to 0. (3) SPROM writes to itself if SPUEN is set to 0. (4) CONFIG is erased/programmed if CFGUEN is set to 0. (5) Page Erase command at LOCK mode with ICE connection (6) Erase or Program command at brown-out detected (7) Destination address is illegal, such as over an available range. (8) Invalid ISP commands Note: Write 1 to clear this bit to 0. 6 1 read-write LDUEN LDROM Update Enable Control (Write Protect) 5 1 read-write 0 LDROM cannot be updated #0 1 LDROM can be updated when the MCU runs in APROM #1 SPUEN SPROM Update Enable Control (Write Protect) 2 1 read-write 0 SPROM cannot be updated #0 1 SPROM can be updated when the MCU runs in APROM #1 ISPDAT FMC_ISPDAT ISP Data Register 0x8 -1 read-write n 0x0 0x0 ISPDAT ISP Data Write data to this register before ISP program operation. Read data from this register after ISP read operation. 0 32 read-write ISPSTS FMC_ISPSTS ISP Status Register 0x40 -1 read-write n 0x0 0x0 CBS Config Boot Selection (Read Only) This is a mirror of CBS in CONFIG0. 1 2 read-only ISPBUSY ISP Start Trigger (Read Only) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. Note: This bit is the same with FMC_ISPTRG bit 0. 0 1 read-only 0 ISP operation is finished #0 1 ISP operation is progressed #1 ISPFF ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself if APUEN is set to 0. (2) LDROM writes to itself if LDUEN is set to 0. (3) SPROM writes to itself if SPUEN is set to 0. (4) CONFIG is erased/programmed if CFGUEN is set to 0. (5) Page Erase command at LOCK mode with ICE connection (6) Erase or Program command at brown-out detected (7) Destination address is illegal, such as over an available range. (8) Invalid ISP commands Note: Write 1 to clear this bit to 0. 6 1 read-write SCODE Security Code Active Flag This bit field set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active this bit is clear by SPROM page erase operation. 29 3 read-write 0 SPROM0/1/2 secured code are inactive #000 1 SPROM0 secured code is active #001 2 SPROM1 secured code is active #010 4 SPROM2 secured code is active #100 7 SPROM0/1/2 Secured code are active #111 VECMAP Vector Page Mapping Address (Read Only) The current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}. 9 12 read-only ISPTRG FMC_ISPTRG ISP Trigger Register 0x10 -1 read-write n 0x0 0x0 ISPGO ISP Start Trigger (Write Protect) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 0 1 read-write 0 ISP operation is finished #0 1 ISP operation is progressed #1 GDMA0 GDMA Register Map GDMA 0x0 0x0 0x1C registers n GDMA_CDST GDMA_CDST GDMA Current Destination Address Register 0x14 -1 read-only n 0x0 0x0 CurrentDst 32-bit Current Destination Address. Indicates the destination address where the GDMA transfer just occurred. During a block transfer, the GDMA determines the successive destination addresses by adding to or subtracting from the destination base address. Depending on the settings in the control register, the current destination address remains the same, is incremented or is decremented. 0 32 read-only GDMA_CSRC GDMA_CSRC GDMA Current Source Address Register 0x10 -1 read-only n 0x0 0x0 CurrentSrc 32-bit Current Source Address. Indicates the source address where the GDMA transfer just occurred. During a block transfer, the GDMA determines the successive source addresses by adding to or subtracting from the source base address. Depending on the settings in the control register, the current source address remains the same, is incremented or is decremented. 0 32 read-only GDMA_CTCNT GDMA_CTCNT GDMA Current Transfer Count Register 0x18 -1 read-only n 0x0 0x0 CurrentTfrCnt Current Transfer Count. 0 13 read-only GDMA_CTL GDMA_CTL GDMA Control Register 0x0 -1 read-write n 0x0 0x0 BME Burst Mode Enable. When this field is set to 1, TWS field must be set to '10' (32 bit double-word option), in addition the DMA initiation address must be 16-Bytes aligned. 0: Disables '4-data burst' mode. GDMA_TCNT is set to number of words to be transferred (default). 1: Enables '4-data burst' mode. GDMA_TCNT is set to number of words to be transferred, divided by 4. 9 1 read-write DADIR Destination Address Direction. 0: Destination address incremented successively (default). 1: Destination address decremented successively. Note: This bit must not be set to 1, if Burst Mode Enable (BME) bit is also set to 1. 4 1 read-write DAFIX Destination Address Fixed. 0: Change the Destination address during the GDMA operation (default). 1: Do not change the Destination address during the GDMA operation. This feature can be used when data is transferred from a single address source to a memory area destination. 6 1 read-write GDMAEN GDMA Enable. 0: Disables GDMA operation (default). 1: Enables GDMA operation this bit is cleared automatically when the transfer is complete to Disable mode. Note: The DMA transfer parameters must be programed before the module is enabled by this bit. 0 1 read-write GDMAERR GDMA Transfer Error. Indicates a transfer error occurred and generates the GDMA interrupt. 0: No error occurred (default). 1: The hardware sets this bit on a GDMA transfer failure. 20 1 read-write GDMAMS GDMA Mode Select 00: Software mode (Memory ( Memory APB ( Memory) (default). 01: External nXDREQ0 mode. USCI ( Memory. 10,11: Reserved 2 2 read-write GIEN GDMA Interrupt Enable. 0: Do not generate an interrupt when the GDMA operation is finished (default). 1: An interrupt is generated when the GDMA operation is finished. 8 1 read-write SADIR Source Address Direction. 0: Source address incremented successively (default). 1: Source address decremented successively. Note: This bit must not be set to 1, if Burst Mode Enable (BME) bit is also set to 1. 5 1 read-write SAFIX Source Address Fixed. 0: Change the source address during the GDMA operation (default). 1: Do not change the source address during the GDMA operation. This feature can be used when data is transferred from a single address source to a memory area destination. 7 1 read-write SOFTTRG Software Triggered GDMA. The firmware can request the GDMA transfer service by setting this bit to 1. This bit is cleared automatically by hardware when the transfer is complete. This bit is available only when GDMAMS field is 0. Note: When a GDMA transaction is in progress, writing to this field is illegal. 0: Ignored (default). 1: Request the GDMA transfer service. 16 1 read-write TCIF Transfer complete Interrupt Flag. TCIF and GDMAERR can generate the GDMA interrupt. 0: The channel operation is in progress (default). 1: The channel operation ended this bit is set only by the GDMA hardware and is cleared by the firmware writing 0 to it. 18 1 read-write TWS Transfer Width Select. The GDMA_SCRB and GDMA_DSTB must be set to be aligned with thedata width selected by this field. 00: One byte (8 bits) is transferred for every GDMA operation (default). 01: One word (16 bits) is transferred for every GDMA operation. 10: One double-word (32 bits) is transferred for every GDMA operation. 11: Reserved. 12 2 read-write GDMA_DSTB GDMA_DSTB GDMA Destination Base Address Register 0x8 -1 read-write n 0x0 0x0 DstBaseAddr 32-bit Destination Base Address. The GDMA channel starts writing its data to the destination address, as defined in this register. During a block transfer, the GDMA determines successive destination addresses by adding to or subtracting from the destination base address. 0 32 read-write GDMA_SRCB GDMA_SRCB GDMA Source Base Address Register 0x4 -1 read-write n 0x0 0x0 SrcBaseAddr 32-bit Source Base Address. The GDMA channel starts reading its data from the source address as defined in this source base address register. During a block transfer, the GDMA determines successive destination addresses by adding to or subtracting from the source base address. 0 32 read-write GDMA_TCNT GDMA_TCNT GDMA Transfer Count Register 0xC -1 read-write n 0x0 0x0 TfrCnt 13-bit Transfer Count. Represents the required number of GDMA transfers. The maximum transfer count is 8K - 1. 0 13 read-write GDMA1 GDMA Register Map GDMA 0x0 0x0 0x1C registers n GDMA_CDST GDMA_CDST GDMA Current Destination Address Register 0x14 -1 read-only n 0x0 0x0 CurrentDst 32-bit Current Destination Address. Indicates the destination address where the GDMA transfer just occurred. During a block transfer, the GDMA determines the successive destination addresses by adding to or subtracting from the destination base address. Depending on the settings in the control register, the current destination address remains the same, is incremented or is decremented. 0 32 read-only GDMA_CSRC GDMA_CSRC GDMA Current Source Address Register 0x10 -1 read-only n 0x0 0x0 CurrentSrc 32-bit Current Source Address. Indicates the source address where the GDMA transfer just occurred. During a block transfer, the GDMA determines the successive source addresses by adding to or subtracting from the source base address. Depending on the settings in the control register, the current source address remains the same, is incremented or is decremented. 0 32 read-only GDMA_CTCNT GDMA_CTCNT GDMA Current Transfer Count Register 0x18 -1 read-only n 0x0 0x0 CurrentTfrCnt Current Transfer Count. 0 13 read-only GDMA_CTL GDMA_CTL GDMA Control Register 0x0 -1 read-write n 0x0 0x0 BME Burst Mode Enable. When this field is set to 1, TWS field must be set to '10' (32 bit double-word option), in addition the DMA initiation address must be 16-Bytes aligned. 0: Disables '4-data burst' mode. GDMA_TCNT is set to number of words to be transferred (default). 1: Enables '4-data burst' mode. GDMA_TCNT is set to number of words to be transferred, divided by 4. 9 1 read-write DADIR Destination Address Direction. 0: Destination address incremented successively (default). 1: Destination address decremented successively. Note: This bit must not be set to 1, if Burst Mode Enable (BME) bit is also set to 1. 4 1 read-write DAFIX Destination Address Fixed. 0: Change the Destination address during the GDMA operation (default). 1: Do not change the Destination address during the GDMA operation. This feature can be used when data is transferred from a single address source to a memory area destination. 6 1 read-write GDMAEN GDMA Enable. 0: Disables GDMA operation (default). 1: Enables GDMA operation this bit is cleared automatically when the transfer is complete to Disable mode. Note: The DMA transfer parameters must be programed before the module is enabled by this bit. 0 1 read-write GDMAERR GDMA Transfer Error. Indicates a transfer error occurred and generates the GDMA interrupt. 0: No error occurred (default). 1: The hardware sets this bit on a GDMA transfer failure. 20 1 read-write GDMAMS GDMA Mode Select 00: Software mode (Memory ( Memory APB ( Memory) (default). 01: External nXDREQ0 mode. USCI ( Memory. 10,11: Reserved 2 2 read-write GIEN GDMA Interrupt Enable. 0: Do not generate an interrupt when the GDMA operation is finished (default). 1: An interrupt is generated when the GDMA operation is finished. 8 1 read-write SADIR Source Address Direction. 0: Source address incremented successively (default). 1: Source address decremented successively. Note: This bit must not be set to 1, if Burst Mode Enable (BME) bit is also set to 1. 5 1 read-write SAFIX Source Address Fixed. 0: Change the source address during the GDMA operation (default). 1: Do not change the source address during the GDMA operation. This feature can be used when data is transferred from a single address source to a memory area destination. 7 1 read-write SOFTTRG Software Triggered GDMA. The firmware can request the GDMA transfer service by setting this bit to 1. This bit is cleared automatically by hardware when the transfer is complete. This bit is available only when GDMAMS field is 0. Note: When a GDMA transaction is in progress, writing to this field is illegal. 0: Ignored (default). 1: Request the GDMA transfer service. 16 1 read-write TCIF Transfer complete Interrupt Flag. TCIF and GDMAERR can generate the GDMA interrupt. 0: The channel operation is in progress (default). 1: The channel operation ended this bit is set only by the GDMA hardware and is cleared by the firmware writing 0 to it. 18 1 read-write TWS Transfer Width Select. The GDMA_SCRB and GDMA_DSTB must be set to be aligned with thedata width selected by this field. 00: One byte (8 bits) is transferred for every GDMA operation (default). 01: One word (16 bits) is transferred for every GDMA operation. 10: One double-word (32 bits) is transferred for every GDMA operation. 11: Reserved. 12 2 read-write GDMA_DSTB GDMA_DSTB GDMA Destination Base Address Register 0x8 -1 read-write n 0x0 0x0 DstBaseAddr 32-bit Destination Base Address. The GDMA channel starts writing its data to the destination address, as defined in this register. During a block transfer, the GDMA determines successive destination addresses by adding to or subtracting from the destination base address. 0 32 read-write GDMA_SRCB GDMA_SRCB GDMA Source Base Address Register 0x4 -1 read-write n 0x0 0x0 SrcBaseAddr 32-bit Source Base Address. The GDMA channel starts reading its data from the source address as defined in this source base address register. During a block transfer, the GDMA determines successive destination addresses by adding to or subtracting from the source base address. 0 32 read-write GDMA_TCNT GDMA_TCNT GDMA Transfer Count Register 0xC -1 read-write n 0x0 0x0 TfrCnt 13-bit Transfer Count. Represents the required number of GDMA transfers. The maximum transfer count is 8K - 1. 0 13 read-write GPIO GPIO Register Map GPIO 0x0 0x0 0x34 registers n 0x100 0x34 registers n 0x140 0x34 registers n 0x40 0x34 registers n 0x440 0x4 registers n 0x80 0x34 registers n 0x800 0x20 registers n 0x840 0x20 registers n 0x880 0x20 registers n 0x8C4 0x1C registers n 0x900 0x20 registers n 0x940 0x14 registers n 0xC0 0x34 registers n DBCTL GPIO_DBCTL Interrupt De-bounce Control Register 0x440 -1 read-write n 0x0 0x0 DBCLKSEL De-bounce Sampling Cycle Selection 0 4 read-write 0 Sample interrupt input once per 1 clocks #0000 1 Sample interrupt input once per 2 clocks #0001 2 Sample interrupt input once per 4 clocks #0010 3 Sample interrupt input once per 8 clocks #0011 4 Sample interrupt input once per 16 clocks #0100 5 Sample interrupt input once per 32 clocks #0101 6 Sample interrupt input once per 64 clocks #0110 7 Sample interrupt input once per 128 clocks #0111 8 Sample interrupt input once per 256 clocks #1000 9 Sample interrupt input once per 2*256 clocks #1001 10 Sample interrupt input once per 4*256 clocks #1010 11 Sample interrupt input once per 8*256 clocks #1011 12 Sample interrupt input once per 16*256 clocks #1100 13 Sample interrupt input once per 32*256 clocks #1101 14 Sample interrupt input once per 64*256 clocks #1110 15 Sample interrupt input once per 128*256 clocks #1111 DBCLKSRC De-bounce Counter Clock Source Selection 4 1 read-write 0 De-bounce counter clock source is the HCLK #0 1 De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC) #1 ICLKON Interrupt Clock on Mode Note: It is recommended to disable this bit to save system power if no special application concern. 5 1 read-write 0 Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1 #0 1 All I/O pins edge detection circuit is always active after reset #1 PA0_PDIO PA0_PDIO GPIO PA.n Pin Data Input/Output Register 0x800 -1 read-write n 0x0 0x0 PDIO GPIO Px.n Pin Data Input/Output Writing this bit can control one GPIO pin output value. 0 1 read-write 0 Corresponding GPIO pin set to low #0 1 Corresponding GPIO pin set to high #1 PA1_PDIO PA1_PDIO GPIO PA.n Pin Data Input/Output Register 0x804 -1 read-write n 0x0 0x0 PA2_PDIO PA2_PDIO GPIO PA.n Pin Data Input/Output Register 0x808 -1 read-write n 0x0 0x0 PA3_PDIO PA3_PDIO GPIO PA.n Pin Data Input/Output Register 0x80C -1 read-write n 0x0 0x0 PA4_PDIO PA4_PDIO GPIO PA.n Pin Data Input/Output Register 0x810 -1 read-write n 0x0 0x0 PA5_PDIO PA5_PDIO GPIO PA.n Pin Data Input/Output Register 0x814 -1 read-write n 0x0 0x0 PA6_PDIO PA6_PDIO GPIO PA.n Pin Data Input/Output Register 0x818 -1 read-write n 0x0 0x0 PA7_PDIO PA7_PDIO GPIO PA.n Pin Data Input/Output Register 0x81C -1 read-write n 0x0 0x0 PA_DATMSK PA_DATMSK PA Data Output Write Mask 0xC -1 read-write n 0x0 0x0 DATMSK0 Port A-F Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. 0 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK1 Port A-F Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. 1 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK2 Port A-F Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. 2 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK3 Port A-F Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. 3 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK4 Port A-F Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. 4 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK5 Port A-F Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. 5 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK6 Port A-F Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. 6 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK7 Port A-F Pin[n] Data Output Write Mask These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored. 7 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 PA_DBEN PA_DBEN PA De-bounce Enable Control Register 0x14 -1 read-write n 0x0 0x0 DBEN0 Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 0 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN1 Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 1 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN2 Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 2 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN3 Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 3 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN4 Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 4 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN5 Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 5 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN6 Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 6 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN7 Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). 7 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 PA_DINOFF PA_DINOFF PA Digital Function Path Disable Control 0x4 -1 read-write n 0x0 0x0 DINOFF0 Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 16 1 read-write 0 Px.n Pin digital function Enabled #0 1 Px.n Pin digital function Disabled (digital input tied to low) #1 DINOFF1 Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 17 1 read-write 0 Px.n Pin digital function Enabled #0 1 Px.n Pin digital function Disabled (digital input tied to low) #1 DINOFF2 Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 18 1 read-write 0 Px.n Pin digital function Enabled #0 1 Px.n Pin digital function Disabled (digital input tied to low) #1 DINOFF3 Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 19 1 read-write 0 Px.n Pin digital function Enabled #0 1 Px.n Pin digital function Disabled (digital input tied to low) #1 DINOFF4 Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 20 1 read-write 0 Px.n Pin digital function Enabled #0 1 Px.n Pin digital function Disabled (digital input tied to low) #1 DINOFF5 Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 21 1 read-write 0 Px.n Pin digital function Enabled #0 1 Px.n Pin digital function Disabled (digital input tied to low) #1 DINOFF6 Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 22 1 read-write 0 Px.n Pin digital function Enabled #0 1 Px.n Pin digital function Disabled (digital input tied to low) #1 DINOFF7 Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 23 1 read-write 0 Px.n Pin digital function Enabled #0 1 Px.n Pin digital function Disabled (digital input tied to low) #1 PA_DOUT PA_DOUT PA Data Output Value 0x8 -1 read-write n 0x0 0x0 DOUT0 Port A-F Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 0 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT1 Port A-F Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 1 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT2 Port A-F Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 2 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT3 Port A-F Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 3 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT4 Port A-F Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 4 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT5 Port A-F Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 5 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT6 Port A-F Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 6 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT7 Port A-F Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 7 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 PA_INTEN PA_INTEN PA Interrupt Enable Control Register 0x1C -1 read-write n 0x0 0x0 FLIEN0 Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 0 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN1 Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 1 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN2 Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 2 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN3 Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 3 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN4 Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 4 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN5 Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 5 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN6 Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 6 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN7 Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 7 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 RHIEN0 Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 16 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN1 Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 17 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN2 Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 18 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN3 Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 19 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN4 Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 20 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN5 Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 21 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN6 Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 22 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN7 Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 23 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 PA_INTSRC PA_INTSRC PA Interrupt Source Flag 0x20 -1 read-write n 0x0 0x0 INTSRC0 Port A-F Pin[n] Interrupt Source Flag Write Operation : 0 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC1 Port A-F Pin[n] Interrupt Source Flag Write Operation : 1 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC2 Port A-F Pin[n] Interrupt Source Flag Write Operation : 2 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC3 Port A-F Pin[n] Interrupt Source Flag Write Operation : 3 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC4 Port A-F Pin[n] Interrupt Source Flag Write Operation : 4 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC5 Port A-F Pin[n] Interrupt Source Flag Write Operation : 5 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC6 Port A-F Pin[n] Interrupt Source Flag Write Operation : 6 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 INTSRC7 Port A-F Pin[n] Interrupt Source Flag Write Operation : 7 1 read-write 0 No action. No interrupt at Px.n #0 1 Clear the corresponding pending interrupt. Px.n generates an interrupt #1 PA_INTTYPE PA_INTTYPE PA Interrupt Trigger Type Control 0x18 -1 read-write n 0x0 0x0 TYPE0 Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 0 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE1 Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 1 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE2 Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 2 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE3 Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 3 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE4 Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 4 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE5 Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 5 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE6 Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 6 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE7 Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 7 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 PA_MODE PA_MODE PA I/O Mode Control 0x0 -1 read-write n 0x0 0x0 MODE0 Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. 0 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE1 Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. 2 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE2 Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. 4 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE3 Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. 6 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE4 Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. 8 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE5 Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. 10 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE6 Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. 12 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE7 Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. 14 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 PA_PHEN PA_PHEN PA Pull-high Control Register 0x30 -1 read-write n 0x0 0x0 PHEN0 Port A-F Pull-high Resistor Control 0 1 read-write 0 Pull-High Resistor Enabled #0 1 Pull-High Resistor Disabled #1 PHEN1 Port A-F Pull-high Resistor Control 1 1 read-write 0 Pull-High Resistor Enabled #0 1 Pull-High Resistor Disabled #1 PHEN2 Port A-F Pull-high Resistor Control 2 1 read-write 0 Pull-High Resistor Enabled #0 1 Pull-High Resistor Disabled #1 PHEN3 Port A-F Pull-high Resistor Control 3 1 read-write 0 Pull-High Resistor Enabled #0 1 Pull-High Resistor Disabled #1 PHEN4 Port A-F Pull-high Resistor Control 4 1 read-write 0 Pull-High Resistor Enabled #0 1 Pull-High Resistor Disabled #1 PHEN5 Port A-F Pull-high Resistor Control 5 1 read-write 0 Pull-High Resistor Enabled #0 1 Pull-High Resistor Disabled #1 PHEN6 Port A-F Pull-high Resistor Control 6 1 read-write 0 Pull-High Resistor Enabled #0 1 Pull-High Resistor Disabled #1 PHEN7 Port A-F Pull-high Resistor Control 7 1 read-write 0 Pull-High Resistor Enabled #0 1 Pull-High Resistor Disabled #1 PA_PIN PA_PIN PA Pin Value 0x10 -1 read-only n 0x0 0x0 PIN0 Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 0 1 read-only PIN1 Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 1 1 read-only PIN2 Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 2 1 read-only PIN3 Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 3 1 read-only PIN4 Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 4 1 read-only PIN5 Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 5 1 read-only PIN6 Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 6 1 read-only PIN7 Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: 7 1 read-only PA_PLEN PA_PLEN PA Pull-low Control Register 0x2C -1 read-write n 0x0 0x0 PLEN0 Port A-F Pull-low Resistor Control 0 1 read-write 0 Pull-Low Resistor Disabled #0 1 Pull-Low Resistor Enabled #1 PLEN1 Port A-F Pull-low Resistor Control 1 1 read-write 0 Pull-Low Resistor Disabled #0 1 Pull-Low Resistor Enabled #1 PLEN2 Port A-F Pull-low Resistor Control 2 1 read-write 0 Pull-Low Resistor Disabled #0 1 Pull-Low Resistor Enabled #1 PLEN3 Port A-F Pull-low Resistor Control 3 1 read-write 0 Pull-Low Resistor Disabled #0 1 Pull-Low Resistor Enabled #1 PLEN4 Port A-F Pull-low Resistor Control 4 1 read-write 0 Pull-Low Resistor Disabled #0 1 Pull-Low Resistor Enabled #1 PLEN5 Port A-F Pull-low Resistor Control 5 1 read-write 0 Pull-Low Resistor Disabled #0 1 Pull-Low Resistor Enabled #1 PLEN6 Port A-F Pull-low Resistor Control 6 1 read-write 0 Pull-Low Resistor Disabled #0 1 Pull-Low Resistor Enabled #1 PLEN7 Port A-F Pull-low Resistor Control 7 1 read-write 0 Pull-Low Resistor Disabled #0 1 Pull-Low Resistor Enabled #1 PA_SLEWCTL PA_SLEWCTL PA High Slew Rate Control Register 0x28 -1 read-write n 0x0 0x0 HSREN0 Port A-F Pin[n] High Slew Rate Control 0 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN1 Port A-F Pin[n] High Slew Rate Control 1 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN2 Port A-F Pin[n] High Slew Rate Control 2 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN3 Port A-F Pin[n] High Slew Rate Control 3 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN4 Port A-F Pin[n] High Slew Rate Control 4 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN5 Port A-F Pin[n] High Slew Rate Control 5 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN6 Port A-F Pin[n] High Slew Rate Control 6 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN7 Port A-F Pin[n] High Slew Rate Control 7 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 PA_SMTEN PA_SMTEN PA Input Schmitt Trigger Enable Register 0x24 -1 read-write n 0x0 0x0 SMTEN0 Port A-F Pin[n] Input Schmitt Trigger Enable Control 0 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN1 Port A-F Pin[n] Input Schmitt Trigger Enable Control 1 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN2 Port A-F Pin[n] Input Schmitt Trigger Enable Control 2 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN3 Port A-F Pin[n] Input Schmitt Trigger Enable Control 3 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN4 Port A-F Pin[n] Input Schmitt Trigger Enable Control 4 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN5 Port A-F Pin[n] Input Schmitt Trigger Enable Control 5 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN6 Port A-F Pin[n] Input Schmitt Trigger Enable Control 6 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN7 Port A-F Pin[n] Input Schmitt Trigger Enable Control 7 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 PB0_PDIO PB0_PDIO GPIO PB.n Pin Data Input/Output Register 0x840 -1 read-write n 0x0 0x0 PB1_PDIO PB1_PDIO GPIO PB.n Pin Data Input/Output Register 0x844 -1 read-write n 0x0 0x0 PB2_PDIO PB2_PDIO GPIO PB.n Pin Data Input/Output Register 0x848 -1 read-write n 0x0 0x0 PB3_PDIO PB3_PDIO GPIO PB.n Pin Data Input/Output Register 0x84C -1 read-write n 0x0 0x0 PB4_PDIO PB4_PDIO GPIO PB.n Pin Data Input/Output Register 0x850 -1 read-write n 0x0 0x0 PB5_PDIO PB5_PDIO GPIO PB.n Pin Data Input/Output Register 0x854 -1 read-write n 0x0 0x0 PB6_PDIO PB6_PDIO GPIO PB.n Pin Data Input/Output Register 0x858 -1 read-write n 0x0 0x0 PB7_PDIO PB7_PDIO GPIO PB.n Pin Data Input/Output Register 0x85C -1 read-write n 0x0 0x0 PB_DATMSK PB_DATMSK PB Data Output Write Mask 0x4C -1 read-write n 0x0 0x0 PB_DBEN PB_DBEN PB De-bounce Enable Control Register 0x54 -1 read-write n 0x0 0x0 PB_DINOFF PB_DINOFF PB Digital Function Path Disable Control 0x44 -1 read-write n 0x0 0x0 PB_DOUT PB_DOUT PB Data Output Value 0x48 -1 read-write n 0x0 0x0 PB_INTEN PB_INTEN PB Interrupt Enable Control Register 0x5C -1 read-write n 0x0 0x0 PB_INTSRC PB_INTSRC PB Interrupt Source Flag 0x60 -1 read-write n 0x0 0x0 PB_INTTYPE PB_INTTYPE PB Interrupt Trigger Type Control 0x58 -1 read-write n 0x0 0x0 PB_MODE PB_MODE PB I/O Mode Control 0x40 -1 read-write n 0x0 0x0 PB_PHEN PB_PHEN PB Pull-high Control Register 0x70 -1 read-write n 0x0 0x0 PB_PIN PB_PIN PB Pin Value 0x50 -1 read-write n 0x0 0x0 PB_PLEN PB_PLEN PB Pull-low Control Register 0x6C -1 read-write n 0x0 0x0 PB_SLEWCTL PB_SLEWCTL PB High Slew Rate Control Register 0x68 -1 read-write n 0x0 0x0 PB_SMTEN PB_SMTEN PB Input Schmitt Trigger Enable Register 0x64 -1 read-write n 0x0 0x0 PC0_PDIO PC0_PDIO GPIO PC.n Pin Data Input/Output Register 0x880 -1 read-write n 0x0 0x0 PC1_PDIO PC1_PDIO GPIO PC.n Pin Data Input/Output Register 0x884 -1 read-write n 0x0 0x0 PC2_PDIO PC2_PDIO GPIO PC.n Pin Data Input/Output Register 0x888 -1 read-write n 0x0 0x0 PC3_PDIO PC3_PDIO GPIO PC.n Pin Data Input/Output Register 0x88C -1 read-write n 0x0 0x0 PC4_PDIO PC4_PDIO GPIO PC.n Pin Data Input/Output Register 0x890 -1 read-write n 0x0 0x0 PC5_PDIO PC5_PDIO GPIO PC.n Pin Data Input/Output Register 0x894 -1 read-write n 0x0 0x0 PC6_PDIO PC6_PDIO GPIO PC.n Pin Data Input/Output Register 0x898 -1 read-write n 0x0 0x0 PC7_PDIO PC7_PDIO GPIO PC.n Pin Data Input/Output Register 0x89C -1 read-write n 0x0 0x0 PC_DATMSK PC_DATMSK PC Data Output Write Mask 0x8C -1 read-write n 0x0 0x0 PC_DBEN PC_DBEN PC De-bounce Enable Control Register 0x94 -1 read-write n 0x0 0x0 PC_DINOFF PC_DINOFF PC Digital Function Path Disable Control 0x84 -1 read-write n 0x0 0x0 PC_DOUT PC_DOUT PC Data Output Value 0x88 -1 read-write n 0x0 0x0 PC_INTEN PC_INTEN PC Interrupt Enable Control Register 0x9C -1 read-write n 0x0 0x0 PC_INTSRC PC_INTSRC PC Interrupt Source Flag 0xA0 -1 read-write n 0x0 0x0 PC_INTTYPE PC_INTTYPE PC Interrupt Trigger Type Control 0x98 -1 read-write n 0x0 0x0 PC_MODE PC_MODE PC I/O Mode Control 0x80 -1 read-write n 0x0 0x0 PC_PHEN PC_PHEN PC Pull-high Control Register 0xB0 -1 read-write n 0x0 0x0 PC_PIN PC_PIN PC Pin Value 0x90 -1 read-write n 0x0 0x0 PC_PLEN PC_PLEN PC Pull-low Control Register 0xAC -1 read-write n 0x0 0x0 PC_SLEWCTL PC_SLEWCTL PC High Slew Rate Control Register 0xA8 -1 read-write n 0x0 0x0 PC_SMTEN PC_SMTEN PC Input Schmitt Trigger Enable Register 0xA4 -1 read-write n 0x0 0x0 PD1_PDIO PD1_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C4 -1 read-write n 0x0 0x0 PD2_PDIO PD2_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C8 -1 read-write n 0x0 0x0 PD3_PDIO PD3_PDIO GPIO PD.n Pin Data Input/Output Register 0x8CC -1 read-write n 0x0 0x0 PD4_PDIO PD4_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D0 -1 read-write n 0x0 0x0 PD5_PDIO PD5_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D4 -1 read-write n 0x0 0x0 PD6_PDIO PD6_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D8 -1 read-write n 0x0 0x0 PD7_PDIO PD7_PDIO GPIO PD.n Pin Data Input/Output Register 0x8DC -1 read-write n 0x0 0x0 PD_DATMSK PD_DATMSK PD Data Output Write Mask 0xCC -1 read-write n 0x0 0x0 PD_DBEN PD_DBEN PD De-bounce Enable Control Register 0xD4 -1 read-write n 0x0 0x0 PD_DINOFF PD_DINOFF PD Digital Function Path Disable Control 0xC4 -1 read-write n 0x0 0x0 PD_DOUT PD_DOUT PD Data Output Value 0xC8 -1 read-write n 0x0 0x0 PD_INTEN PD_INTEN PD Interrupt Enable Control Register 0xDC -1 read-write n 0x0 0x0 PD_INTSRC PD_INTSRC PD Interrupt Source Flag 0xE0 -1 read-write n 0x0 0x0 PD_INTTYPE PD_INTTYPE PD Interrupt Trigger Type Control 0xD8 -1 read-write n 0x0 0x0 PD_MODE PD_MODE PD I/O Mode Control 0xC0 -1 read-write n 0x0 0x0 PD_PHEN PD_PHEN PD Pull-high Control Register 0xF0 -1 read-write n 0x0 0x0 PD_PIN PD_PIN PD Pin Value 0xD0 -1 read-write n 0x0 0x0 PD_PLEN PD_PLEN PD Pull-low Control Register 0xEC -1 read-write n 0x0 0x0 PD_SLEWCTL PD_SLEWCTL PD High Slew Rate Control Register 0xE8 -1 read-write n 0x0 0x0 PD_SMTEN PD_SMTEN PD Input Schmitt Trigger Enable Register 0xE4 -1 read-write n 0x0 0x0 PE0_PDIO PE0_PDIO GPIO PE.n Pin Data Input/Output Register 0x900 -1 read-write n 0x0 0x0 PE1_PDIO PE1_PDIO GPIO PE.n Pin Data Input/Output Register 0x904 -1 read-write n 0x0 0x0 PE2_PDIO PE2_PDIO GPIO PE.n Pin Data Input/Output Register 0x908 -1 read-write n 0x0 0x0 PE3_PDIO PE3_PDIO GPIO PE.n Pin Data Input/Output Register 0x90C -1 read-write n 0x0 0x0 PE4_PDIO PE4_PDIO GPIO PE.n Pin Data Input/Output Register 0x910 -1 read-write n 0x0 0x0 PE5_PDIO PE5_PDIO GPIO PE.n Pin Data Input/Output Register 0x914 -1 read-write n 0x0 0x0 PE6_PDIO PE6_PDIO GPIO PE.n Pin Data Input/Output Register 0x918 -1 read-write n 0x0 0x0 PE7_PDIO PE7_PDIO GPIO PE.n Pin Data Input/Output Register 0x91C -1 read-write n 0x0 0x0 PE_DATMSK PE_DATMSK PE Data Output Write Mask 0x10C -1 read-write n 0x0 0x0 PE_DBEN PE_DBEN PE De-bounce Enable Control Register 0x114 -1 read-write n 0x0 0x0 PE_DINOFF PE_DINOFF PE Digital Function Path Disable Control 0x104 -1 read-write n 0x0 0x0 PE_DOUT PE_DOUT PE Data Output Value 0x108 -1 read-write n 0x0 0x0 PE_INTEN PE_INTEN PE Interrupt Enable Control Register 0x11C -1 read-write n 0x0 0x0 PE_INTSRC PE_INTSRC PE Interrupt Source Flag 0x120 -1 read-write n 0x0 0x0 PE_INTTYPE PE_INTTYPE PE Interrupt Trigger Type Control 0x118 -1 read-write n 0x0 0x0 PE_MODE PE_MODE PE I/O Mode Control 0x100 -1 read-write n 0x0 0x0 PE_PHEN PE_PHEN PE Pull-high Control Register 0x130 -1 read-write n 0x0 0x0 PE_PIN PE_PIN PE Pin Value 0x110 -1 read-write n 0x0 0x0 PE_PLEN PE_PLEN PE Pull-low Control Register 0x12C -1 read-write n 0x0 0x0 PE_SLEWCTL PE_SLEWCTL PE High Slew Rate Control Register 0x128 -1 read-write n 0x0 0x0 PE_SMTEN PE_SMTEN PE Input Schmitt Trigger Enable Register 0x124 -1 read-write n 0x0 0x0 PF0_PDIO PF0_PDIO GPIO PF.n Pin Data Input/Output Register 0x940 -1 read-write n 0x0 0x0 PF1_PDIO PF1_PDIO GPIO PF.n Pin Data Input/Output Register 0x944 -1 read-write n 0x0 0x0 PF2_PDIO PF2_PDIO GPIO PF.n Pin Data Input/Output Register 0x948 -1 read-write n 0x0 0x0 PF3_PDIO PF3_PDIO GPIO PF.n Pin Data Input/Output Register 0x94C -1 read-write n 0x0 0x0 PF4_PDIO PF4_PDIO GPIO PF.n Pin Data Input/Output Register 0x950 -1 read-write n 0x0 0x0 PF_DATMSK PF_DATMSK PF Data Output Write Mask 0x14C -1 read-write n 0x0 0x0 PF_DBEN PF_DBEN PF De-bounce Enable Control Register 0x154 -1 read-write n 0x0 0x0 PF_DINOFF PF_DINOFF PF Digital Function Path Disable Control 0x144 -1 read-write n 0x0 0x0 PF_DOUT PF_DOUT PF Data Output Value 0x148 -1 read-write n 0x0 0x0 PF_INTEN PF_INTEN PF Interrupt Enable Control Register 0x15C -1 read-write n 0x0 0x0 PF_INTSRC PF_INTSRC PF Interrupt Source Flag 0x160 -1 read-write n 0x0 0x0 PF_INTTYPE PF_INTTYPE PF Interrupt Trigger Type Control 0x158 -1 read-write n 0x0 0x0 PF_MODE PF_MODE PF I/O Mode Control 0x140 -1 read-write n 0x0 0x0 PF_PHEN PF_PHEN PF Pull-high Control Register 0x170 -1 read-write n 0x0 0x0 PF_PIN PF_PIN PF Pin Value 0x150 -1 read-write n 0x0 0x0 PF_PLEN PF_PLEN PF Pull-low Control Register 0x16C -1 read-write n 0x0 0x0 PF_SLEWCTL PF_SLEWCTL PF High Slew Rate Control Register 0x168 -1 read-write n 0x0 0x0 PF_SMTEN PF_SMTEN PF Input Schmitt Trigger Enable Register 0x164 -1 read-write n 0x0 0x0 HDIV HDIV Register Map HDIV 0x0 0x0 0x14 registers n 0x20 0x10 registers n 0x40 0x10 registers n DIVIDEND0 HDIV_DIVIDEND0 Dividend Source Register 0x0 -1 read-write n 0x0 0x0 DIVIDEND Dividend Source This register is given the dividend of divider before calculation is started. 0 32 read-write DIVIDEND1 HDIV_DIVIDEND1 Dividend Source Register 0x20 -1 read-write n 0x0 0x0 DIVIDEND2 HDIV_DIVIDEND2 Dividend Source Register 0x40 -1 read-write n 0x0 0x0 DIVISOR0 HDIV_DIVISOR0 Divisor Source Resister 0x4 -1 read-write n 0x0 0x0 DIVISOR Divisor Source This register is given the divisor of divider before calculation starts. Note: When this register is written, hardware divider will start calculation. 0 16 read-write DIVISOR1 HDIV_DIVISOR1 Divisor Source Resister 0x24 -1 read-write n 0x0 0x0 DIVISOR2 HDIV_DIVISOR2 Divisor Source Resister 0x44 -1 read-write n 0x0 0x0 QUOTIENT0 HDIV_QUOTIENT0 Quotient Result Resister 0x8 -1 read-write n 0x0 0x0 QUOTIENT Quotient Result This register holds the quotient result of divider after calculation is completed. 0 32 read-write QUOTIENT1 HDIV_QUOTIENT1 Quotient Result Resister 0x28 -1 read-write n 0x0 0x0 QUOTIENT2 HDIV_QUOTIENT2 Quotient Result Resister 0x48 -1 read-write n 0x0 0x0 REM0 HDIV_REM0 Remainder Result Register 0xC -1 read-write n 0x0 0x0 REM Remainder Result The remainder of hardware divider is 16-bit sign integer (REM[15:0]) with sign extension (REM[31:16]) to 32-bit integer. 0 32 read-write REM1 HDIV_REM1 Remainder Result Register 0x2C -1 read-write n 0x0 0x0 REM2 HDIV_REM2 Remainder Result Register 0x4C -1 read-write n 0x0 0x0 STATUS HDIV_STATUS Divider Status Register 0x10 -1 read-only n 0x0 0x0 DIVBYZERO0 Divisor Zero Warning (Read Only) Note: The DIVBYZERO flag is used to indicate divide-by-zero situation and updated whenever HDIV_DIVISOR is written. This bit is read only. 1 1 read-only 0 The divisor0 is not 0 #0 1 The divisor0 is 0 #1 DIVBYZERO1 Divisor Zero Warning (Read Only) Note: The DIVBYZERO flag is used to indicate divide-by-zero situation and updated whenever HDIV_DIVISOR is written. This bit is read only. 2 1 read-only 0 The divisor1 is not 0 #0 1 The divisor1 is 0 #1 DIVBYZERO2 Divisor Zero Warning (Read Only) Note: The DIVBYZERO flag is used to indicate divide-by-zero situation and updated whenever HDIV_DIVISOR is written. This bit is read only. 3 1 read-only 0 The divisor2 is not 0 #0 1 The divisor2 is 0 #1 INT INT Register Map INT 0x0 0x80 0x8 registers n IRQSTS INT_IRQSTS MCU IRQ Number Identity Register 0x84 -1 read-write n 0x0 0x0 IRQ MCU IRQ Source Register The IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. There is one mode to generate interrupt to Cortex-M0 - the normal mode. The IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0. When the IRQ[n] is 0, setting IRQ[n] to 1 will generate an interrupt to Cortex-M0 NVIC[n]. When the IRQ[n] is 1 (i.e. an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting IRQ[n] 0 has no effect. 0 32 read-write NMICTL INT_NMICTL NMI Source Interrupt Select Control Register 0x80 -1 read-write n 0x0 0x0 NMISEL NMI Interrupt Source Selection The NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMTSEL. 0 5 read-write NMISELEN NMI Interrupt Enable Control (Write Protected) Note: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address SYS_BA+0x100. 8 1 read-write 0 NMI interrupt Disabled #0 1 NMI interrupt Enabled #1 OP OP Register Map OP 0x0 0x4 0x4 registers n CTL OP_CTL OP Amplifier Control Register 0x4 -1 read-write n 0x0 0x0 OP1EN Output Amplifier1 Enable Control Note: The OP output needs to wait stable 20s after OPEN is first set. 1 1 read-write 0 Amplifier Disabled #0 1 Amplifier Enabled #1 SCS SCS Register Map SCS 0x0 0x10 0xC registers n 0x100 0x4 registers n 0x180 0x4 registers n 0x200 0x4 registers n 0x280 0x4 registers n 0x400 0x20 registers n 0xD00 0x8 registers n 0xD0C 0x8 registers n 0xD1C 0x8 registers n AIRCR SCS_AIRCR Application Interrupt and Reset Control Register 0xD0C -1 read-write n 0x0 0x0 SYSRESETREQ System Reset Request Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested. The bit is a write only bit and self-clears as part of the reset sequence. 2 1 read-write VECTCLRACTIVE Exception Active Status Clear Bit Reserved for debug use. When writing to the register, user must write 0 to this bit, otherwise behavior is unpredictable. 1 1 read-write VECTORKEY Register Access Key Write Operation: When writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status. Read Operation: Read as 0xFA05. 16 16 read-write CPUID SCS_CPUID CPUID Base Register 0xD00 -1 read-only n 0x0 0x0 IMPLEMENTER Implementer Code 24 8 read-only PART Architecture of the Processor Reads as 0xC for ARMv6-M parts 16 4 read-only PARTNO Part Number of the Processor Reads as 0xC20. 4 12 read-only REVISION Revision Number Reads as 0x0 0 4 read-only ICSR SCS_ICSR Interrupt Control State Register 0xD04 -1 read-write n 0x0 0x0 ISRPENDING Interrupt Pending Flag,Excluding NMI and Faults (Read Only) 22 1 read-only 0 Interrupt not pending #0 1 Interrupt pending #1 ISRPREEMPT Interrupt Preempt Bit(Read Only) If set, a pending exception will be serviced on exit from the debug halt state 23 1 read-only NMIPENDSET NMI Set-pending Bit Write Operation: Note: Because NMI is the highest-priority exception, normally the processor entersthe NMI exception handler as soon as it detects a write of 1 to this bit. Entering thehandler then clears this bit to 0. This means a read of this bit by the NMI exceptionhandler returns 1 only if the NMI signal is reasserted while the processor is executingthat handler. 31 1 read-write 0 No effect. NMI exception not pending #0 1 Changes NMI exception state to pending. NMI exception pending #1 PENDSTCLR SysTick Exception Clear-pending Bit Write Operation: Note: This bit is write-only. When you want to clear PENDST bit, you must 'write 0 toPENDSTSET and write 1 to PENDSTCLR' at the same time. 25 1 read-write 0 No effect #0 1 Removes the pending state from the SysTick exception #1 PENDSTSET SysTick Exception Set-pending Bit Write Operation: 26 1 read-write 0 No effect. SysTick exception is not pending #0 1 Changes SysTick exception state to pending. SysTick exception is pending #1 PENDSVCLR PendSV Clear-pending Bit Write Operation: This bit is write-only. To clear the PENDSV bit, you must 'write 0 to PENDSVSET andwrite 1 to PENDSVCLR' at the same time. 27 1 read-write 0 No effect #0 1 Removes the pending state from the PendSV exception #1 PENDSVSET PendSV Set-pending Bit Write Operation: Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending 28 1 read-write 0 No effect. PendSV exception is not pending #0 1 Changes PendSV exception state to pending. PendSV exception is pending #1 VECTACTIVE Contains the Active Exception Number 0 9 read-write 0 Thread mode 0 VECTPENDING Exception Number of the Highest Priority Pending Enabled Exception 12 9 read-write 0 No pending exceptions 0 NVIC_ICER NVIC_ICER IRQ0 ~ IRQ31 Clear-enable Control Register 0x180 -1 read-write n 0x0 0x0 CLRENA Interrupt Disable Register Disable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Write operation: Note: Read value indicates the current enable status. 0 32 read-write 0 No effect. Associated interrupt status Disabled 0 1 Write 1 to disable associated interrupt. Associated interrupt status Enabled 1 NVIC_ICPR NVIC_ICPR IRQ0 ~ IRQ31 Clear-pending Control Register 0x280 -1 read-write n 0x0 0x0 CLRPEND Clear Interrupt Pending Register Write operation: Note: Read value indicates the current pending status. 0 32 read-write 0 No effect. Associated interrupt in not in pending status 0 1 Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Associated interrupt is in pending status 1 NVIC_IPR0 NVIC_IPR0 IRQ0 ~ IRQ3 Interrupt Priority Control Register 0x400 -1 read-write n 0x0 0x0 PRI0 Priority of IRQ0 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI1 Priority of IRQ1 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI2 Priority of IRQ2 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI3 Priority of IRQ3 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR1 NVIC_IPR1 IRQ4 ~ IRQ7 Interrupt Priority Control Register 0x404 -1 read-write n 0x0 0x0 PRI4 Priority of IRQ4 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI5 Priority of IRQ5 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI6 Priority of IRQ6 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI7 Priority of IRQ7 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR2 NVIC_IPR2 IRQ8 ~ IRQ11 Interrupt Priority Control Register 0x408 -1 read-write n 0x0 0x0 PRI10 Priority of IRQ10 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI11 Priority of IRQ11 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write PRI8 Priority of IRQ8 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI9 Priority of IRQ9 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write NVIC_IPR3 NVIC_IPR3 IRQ12 ~ IRQ15 Interrupt Priority Control Register 0x40C -1 read-write n 0x0 0x0 PRI12 Priority of IRQ12 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI13 Priority of IRQ13 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI14 Priority of IRQ14 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI15 Priority of IRQ15 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR4 NVIC_IPR4 IRQ16 ~ IRQ19 Interrupt Priority Control Register 0x410 -1 read-write n 0x0 0x0 PRI16 Priority of IRQ16 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI17 Priority of IRQ17 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI18 Priority of IRQ18 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI19 Priority of IRQ19 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR5 NVIC_IPR5 IRQ20 ~ IRQ23 Interrupt Priority Control Register 0x414 -1 read-write n 0x0 0x0 PRI20 Priority of IRQ20 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI21 Priority of IRQ21 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI22 Priority of IRQ22 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI23 Priority of IRQ23 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR6 NVIC_IPR6 IRQ24 ~ IRQ27 Interrupt Priority Control Register 0x418 -1 read-write n 0x0 0x0 PRI24 Priority of IRQ24 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI25 Priority of IRQ25 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI26 Priority of IRQ26 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI27 Priority of IRQ27 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR7 NVIC_IPR7 IRQ28 ~ IRQ31 Interrupt Priority Control Register 0x41C -1 read-write n 0x0 0x0 PRI28 Priority of IRQ28 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI29 Priority of IRQ29 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI30 Priority of IRQ30 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI31 Priority of IRQ31 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_ISER NVIC_ISER IRQ0 ~ IRQ31 Set-enable Control Register 0x100 -1 read-write n 0x0 0x0 SETENA Interrupt Enable Register Enable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Write operation: Read value indicates the current enable status. 0 32 read-write 0 No effect. Associated interrupt status is Disabled 0 1 Write 1 to enable associated interrupt. Associated interrupt status is Enabled 1 NVIC_ISPR NVIC_ISPR IRQ0 ~ IRQ31 Set-pending Control Register 0x200 -1 read-write n 0x0 0x0 SETPEND Set Interrupt Pending Register Write operation: Note: Read value indicates the current pending status. 0 32 read-write 0 No effect. Associated interrupt in not in pending status 0 1 Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Associated interrupt is in pending status 1 SCR SCS_SCR System Control Register 0xD10 -1 read-write n 0x0 0x0 SEVONPEND Send Event on Pending Bit When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. 4 1 read-write 0 Only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded #0 1 Enabled events and all interrupts, including disabled interrupts, can wake-up theprocessor #1 SLEEPDEEP Processor Deep Sleep and Sleep Mode Selection Controls whether the processor uses sleep or deep sleep as its low power mode: 2 1 read-write 0 Sleep mode #0 1 Deep Sleep mode #1 SLEEPONEXIT Sleep-on-exit Enable Control This bit indicates sleep-on-exit when returning from Handler mode to Thread mode. 1 1 read-write 0 Do not sleep when returning to Thread mode #0 1 Enter Sleep or Deep Sleep when returning from ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application #1 SHPR2 SCS_SHPR2 System Handler Priority Register 2 0xD1C -1 read-write n 0x0 0x0 PRI11 Priority of System Handler 11 - SVCall '0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write SHPR3 SCS_SHPR3 System Handler Priority Register 3 0xD20 -1 read-write n 0x0 0x0 PRI14 Priority of System Handler 14 - PendSV '0' denotes the highest priority and '3' denotes the lowest priority. 22 2 read-write PRI15 Priority of System Handler 15 - SysTick '0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write SYST_CTL SYST_CTL SysTick Control and Status 0x10 -1 read-write n 0x0 0x0 CLKSRC System Tick Clock Source Select Bit 2 1 read-write 0 Clock source is optional, refer to STCLKSEL #0 1 Core clock used for SysTick timer #1 COUNTFLAG System Tick Counter Flag Return 1 If Timer Counted to 0 Since Last Time this Register Was Read 16 1 read-write 0 COUNTFLAG is cleared on read or by a write to the Current Value register #0 1 COUNTFLAG is set by a count transition from 1 to 0 #1 ENABLE System Tick Counter Enable Control 0 1 read-write 0 System Tick counter Disabled #0 1 System Tick counter will operate in a multi-shot manner #1 TICKINT System Tick Interrupt Enable Control 1 1 read-write 0 Counting down to 0 will not cause the SysTick exception to be pended. User can use COUNTFLAG to determine if a count to zero has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended #1 SYST_CVR SYST_CVR SysTick Current Value Register 0x18 -1 read-write n 0x0 0x0 CURRENT System Tick Current Value Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. 0 24 read-write SYST_RVR SYST_RVR SysTick Reload Value Register 0x14 -1 read-write n 0x0 0x0 RELOAD System Tick Reload Value Value to load into the Current Value register when the counter reaches 0. 0 24 read-write SYS SYS Register Map SYS 0x0 0x0 0x14 registers n 0x100 0x4 registers n 0x114 0x4 registers n 0x18 0x8 registers n 0x24 0x4 registers n 0x30 0x18 registers n BODCTL SYS_BODCTL Brown-out Detector Control Register 0x18 -1 read-write n 0x0 0x0 BODEN Brown-out Detector Enable Control (Write Protect) The default value is set by flash controller user configuration register CBODEN (CONFIG0 [11]). Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Brown-out Detector function Disabled #0 1 Brown-out Detector function Enabled #1 BODIF Brown-out Detector Interrupt Flag Note: Write 1 to clear this bit to 0. 5 1 read-write 0 Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting #0 1 When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled #1 BODOUT Brown-out Detector Output Status 7 1 read-write 0 Brown-out Detector output status is 0. It means the detected voltage is higher than BODVL setting or BODEN is 0 #0 1 Brown-out Detector output status is 1. It means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled , this bit always responds 0000 #1 BODRSTEN Brown-out Reset Enable Control (Write Protect) The default value is set by flash controller user configuration register CBORST(CONFIG0[19]) bit . Note1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). BOD will wake CPU up when BODOUT is high in power-down mode. Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 Brown-out 'INTERRUPT' function Enabled #0 1 Brown-out 'RESET' function Enabled #1 BODVL Brown-out Detector Threshold Voltage Selection (Write Protect) The default value is set by flash controller user configuration register CBOV (CONFIG0 [15:13]). Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1 3 read-write 0 Brown-Out Detector threshold voltage is 2.0V #000 1 Brown-Out Detector threshold voltage is 2.2V #001 2 Brown-Out Detector threshold voltage is 2.4V #010 3 Brown-Out Detector threshold voltage is 2.7V #011 4 Brown-Out Detector threshold voltage is 3.0V #100 5 Brown-Out Detector threshold voltage is 3.7V #101 6 Brown-Out Detector threshold voltage is 4.0V #110 7 Brown-Out Detector threshold voltage is 4.3V #111 LVREN Low Voltage Reset Enable Control (Write Protect) The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 15 1 read-write 0 Low Voltage Reset function Disabled #0 1 Low Voltage Reset function Enabled #1 LVRLPM Low Voltage Reset Low Power Mode (Write Protect) Note1: The LVR consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the LVR response. Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 LVR operate in normal mode (default) #0 1 LVR Low Power mode Enabled #1 GPA_MFP SYS_GPA_MFP GPIOA Multiple Function Control Register 0x30 -1 read-write n 0x0 0x0 PA0MFP PA.0 Multi-function Pin Selection 0 4 read-write PA1MFP PA.1 Multi-function Pin Selection 4 4 read-write PA2MFP PA.2 Multi-function Pin Selection 8 4 read-write PA3MFP PA.3 Multi-function Pin Selection 12 4 read-write PA4MFP PA.4 Multi-function Pin Selection 16 4 read-write PA5MFP PA.5 Multi-function Pin Selection 20 4 read-write PA6MFP PA.6 Multi-function Pin Selection 24 4 read-write PA7MFP PA.7 Multi-function Pin Selection 28 4 read-write GPB_MFP SYS_GPB_MFP GPIOB Multiple Function Control Register 0x34 -1 read-write n 0x0 0x0 PB0MFP PB.0 Multi-function Pin Selection 0 4 read-write PB1MFP PB.1 Multi-function Pin Selection 4 4 read-write PB2MFP PB.2 Multi-function Pin Selection 8 4 read-write PB3MFP PB.3 Multi-function Pin Selection 12 4 read-write PB4MFP PB.4 Multi-function Pin Selection 16 4 read-write PB5MFP PB.5 Multi-function Pin Selection 20 4 read-write PB6MFP PB.6 Multi-function Pin Selection 24 4 read-write PB7MFP PB.7 Multi-function Pin Selection 28 4 read-write GPC_MFP SYS_GPC_MFP GPIOC Multiple Function Control Register 0x38 -1 read-write n 0x0 0x0 PC0MFP PC.0 Multi-function Pin Selection 0 4 read-write PC1MFP PC.1 Multi-function Pin Selection 4 4 read-write PC2MFP PC.2 Multi-function Pin Selection 8 4 read-write PC3MFP PC.3 Multi-function Pin Selection 12 4 read-write PC4MFP PC.4 Multi-function Pin Selection 16 4 read-write PC5MFP PC.5 Multi-function Pin Selection 20 4 read-write PC6MFP PC.6 Multi-function Pin Selection 24 4 read-write PC7MFP PC.7 Multi-function Pin Selection 28 4 read-write GPD_MFP SYS_GPD_MFP GPIOD Multiple Function Control Register 0x3C -1 read-write n 0x0 0x0 PD1MFP PD.1 Multi-function Pin Selection 4 4 read-write PD2MFP PD.2 Multi-function Pin Selection 8 4 read-write PD3MFP PD.3 Multi-function Pin Selection 12 4 read-write PD4MFP PD.4 Multi-function Pin Selection 16 4 read-write PD5MFP PD.5 Multi-function Pin Selection 20 4 read-write PD6MFP PD.6 Multi-function Pin Selection 24 4 read-write PD7MFP PD.7 Multi-function Pin Selection 28 4 read-write GPE_MFP SYS_GPE_MFP GPIOE Multiple Function Control Register 0x40 -1 read-write n 0x0 0x0 PE0MFP PE.0 Multi-function Pin Selection 0 4 read-write PE1MFP PE.1 Multi-function Pin Selection 4 4 read-write PE2MFP PE.2 Multi-function Pin Selection 8 4 read-write PE3MFP PE.3 Multi-function Pin Selection 12 4 read-write PE4MFP PE.4 Multi-function Pin Selection 16 4 read-write PE5MFP PE.5 Multi-function Pin Selection 20 4 read-write PE6MFP PE.6 Multi-function Pin Selection 24 4 read-write PE7MFP PE.7 Multi-function Pin Selection 28 4 read-write GPF_MFP SYS_GPF_MFP GPIOF Multiple Function Control Register 0x44 -1 read-write n 0x0 0x0 PF0MFP PF.0 Multi-function Pin Selection 0 4 read-write PF1MFP PF.1 Multi-function Pin Selection 4 4 read-write PF2MFP PF.2 Multi-function Pin Selection 8 4 read-write PF3MFP PF.3 Multi-function Pin Selection 12 4 read-write PF4MFP PF.4 Multi-function Pin Selection 16 4 read-write IPRST0 SYS_IPRST0 Peripheral Reset Control Register 0 0x8 -1 read-write n 0x0 0x0 CHIPRST Chip One-shot Reset (Write Protect) Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2 Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Chip normal operation #0 1 Chip one-shot reset #1 CPURST Processor Core One-shot Reset (Write Protect) Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Processor core normal operation #0 1 Processor core one-shot reset #1 GDMARST GDMA One-shot Reset (Write Protect) Setting this bit will only reset the GDMA, and this bit will automatically return to 0 after the 2 clock cycles. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 GDMA normal operation #0 1 GDMA one-shot reset #1 IPRST1 SYS_IPRST1 Peripheral Reset Control Register 1 0xC -1 read-write n 0x0 0x0 ACMPRST ACMP Controller Reset 30 1 read-write 0 ACMP controller normal operation #0 1 ACMP controller reset #1 ADCRST ADC Controller Reset 28 1 read-write 0 ADC controller normal operation #0 1 ADC controller reset #1 BPWMRST Basic PWM Controller Reset 16 1 read-write 0 BPWM controller normal operation #0 1 BPWM controller reset #1 CAPRST CAP Controller Reset 8 1 read-write 0 CAP controller normal operation #0 1 CAP controller reset #1 EPWMRST Enhanced PWM Controller Reset 20 1 read-write 0 EPWM controller normal operation #0 1 EPWM controller reset #1 GPIORST GPIO Controller Reset 1 1 read-write 0 GPIO controller normal operation #0 1 GPIO controller reset #1 OPRST OP Controller Reset 12 1 read-write 0 OP controller normal operation #0 1 OP controller reset #1 TMR0RST Timer0 Controller Reset 2 1 read-write 0 Timer0 controller normal operation #0 1 Timer0 controller reset #1 TMR1RST Timer1 Controller Reset 3 1 read-write 0 Timer1 controller normal operation #0 1 Timer1 controller reset #1 TMR2RST Timer2 Controller Reset 4 1 read-write 0 Timer2 controller normal operation #0 1 Timer2 controller reset #1 USCI1RST USCI1 Controller Reset 25 1 read-write 0 USCI1 controller normal operation #0 1 USCI1 controller reset #1 USCI2RST USCI2 Controller Reset 26 1 read-write 0 USCI2 controller normal operation #0 1 USCI2 controller reset #1 IVSCTL SYS_IVSCTL Internal Voltage Source Control Register 0x1C -1 read-write n 0x0 0x0 VTEMPEN Temperature Sensor Enable Control This bit is used to enable/disable temperature sensor function. Note: After this bit is set to 1, the value of temperature sensor output can be obtained from A/D conversion result. Please refer to ADC function chapter for details. 0 1 read-write 0 Temperature sensor function Disabled (default) #0 1 Temperature sensor function Enabled #1 PDID SYS_PDID Part Device Identification Number Register 0x0 -1 read-only n 0x0 0x0 PDID Part Device Identification Number (Read Only) This register reflects device part number code. Software can read this register to identify which device is used. 0 32 read-only PORCTL SYS_PORCTL Power-On-reset Controller Register 0x24 -1 read-write n 0x0 0x0 POROFF Power-on Reset Enable Control (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 16 read-write REGLCTL SYS_REGLCTL Register Write-protection Control Register 0x100 -1 read-write n 0x0 0x0 REGLCTL Register Lock Control Disable Index (Read Only) The Protected registers are: SYS_IPRST0 SYS_IPRST0 SYS_BODCTL LDOCR SYS_PORCTL CLK_PWRCTL CLK_APBCLK bit[0] CLK_CLKSEL0 CLK_CLKSEL1 bit[1:0] NMI_SEL bit[8] FMC_ISPCTL FMC_ISPTRG WDT_CTL Note: The bits which are write-protected will be noted as' (Write Protect)' beside the description. 0 1 read-only 0 Write-protection Enabled for writing protected registers. Any write to the protected register is ignored #0 1 Write-protection Disabled for writing protected registers #1 REGPROTDIS Register Write-protection Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field. After this sequence is completed, the SYS_REGLCTL bit will be set to 1 and write-protection registers can be normal write. 1 7 write-only RSTSTS SYS_RSTSTS System Reset Status Register 0x4 -1 read-write n 0x0 0x0 BODRF BOD Reset Flag The BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 4 1 read-write 0 No reset from BOD #0 1 The BOD had issued the reset signal to reset the system #1 CPURF CPU Reset Flag The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC). Note: Write 1 to clear this bit to 0. 7 1 read-write 0 No reset from CPU #0 1 The Cortex-M0 Core and FMC are reset by software setting CPURST to 1 #1 HFAULTRF Hard Fault Reset Flag Note: Write 1 to clear this bit to 0. 11 1 read-write 0 No reset from Hardfault #0 1 The Cortex-M0 Core and FMC are reset by software setting HARDFAULTRST to 1 #1 LVRF LVR Reset Flag The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 3 1 read-write 0 No reset from LVR #0 1 LVR controller had issued the reset signal to reset the system #1 PINRF NRESET Pin Reset Flag The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 1 1 read-write 0 No reset from nRESET pin #0 1 Pin nRESET had issued the reset signal to reset the system #1 PORF POR Reset Flag The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 0 1 read-write 0 No reset from POR or CHIPRST #0 1 Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system #1 SYSRF System Reset Flag The system reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 5 1 read-write 0 No reset from Cortex-M0 #0 1 The Cortex-M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core #1 WDTRF WDT Reset Flag The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. Note1: Write 1 to clear this bit to 0. Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. 2 1 read-write 0 No reset from watchdog timer or window watchdog timer #0 1 The watchdog timer or window watchdog timer had issued the reset signal to reset the system #1 TSOFFSET SYS_TSOFFSET Temperature Sensor Offset Register 0x114 -1 read-only n 0x0 0x0 BGVAL BGVAL 16 8 read-only VTEMP125 8 8 read-only VTEMP25 0 8 read-only WAIT SYS_WAIT HCLK Wait State Cycle Control Register 0x10 -1 read-write n 0x0 0x0 HCLKWS HCLK Wait State Cycle Control Bit This bit is used to enable/disable HCLK wait state when access Flash. Note: When HCLK frequency is faster than 48M(60)Hz, insert one wait state is necessary. 0 1 read-write 0 No wait state #0 1 One wait state inserted when CPU access Flash #1 TMR TMR Register Map TMR 0x0 0x0 0x1C registers n 0x20 0x1C registers n 0x40 0x14 registers n 0x80 0x1C registers n TIMER0_CAP TIMER0_CAP Timer0 Capture Data Register 0x10 -1 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on ACMPOx matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 0 24 read-only TIMER0_CMP TIMER0_CMP Timer0 Compare Register 0x4 -1 read-write n 0x0 0x0 CMPDAT Timer Compared Value CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF flag will set to 1. Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. Note2: When Timer is operating at Continuous Counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into CMPDAT field. But if Timer is operating at other modes except Periodic mode on M05xxDN/DE, the 24-bit up counter will restart counting and using newest CMPDAT value to be the timer compared value if software writes a new value into CMPDAT field. 0 24 read-write TIMER0_CNT TIMER0_CNT Timer0 Data Register 0xC -1 read-only n 0x0 0x0 CNT Timer Data Register If CNTEN is set to 1, CNT register value will be updated continuously to monitor 24-bit up counter value. 0 24 read-only TIMER0_CTL TIMER0_CTL Timer0 Control and Status Register 0x0 -1 read-write n 0x0 0x0 ACTSTS Timer Active Status (Read Only) This bit indicates the 24-bit up counter status. 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CMPCTL TIMERx_CMP Mode Control 17 1 read-write 0 In One-shot or Periodic mode, when write new CMPDAT, timer counter will reset #0 1 In One-shot or Periodic mode, when write new CMPDAT if new CMPDAT CNT (TIMERx_CNT[23:0])(current counter) , timer counter keep counting and will not reset. If new CMPDAT = CNT(current counter) , timer counter will reset #1 CNTEN Timer Enable Control 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 EXTCNTEN Counter Mode Enable Control This bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 'Event Counting Mode' for detail description. 24 1 read-write 0 External event counter mode Disabled #0 1 External event counter mode Enabled #1 ICEDEBUG ICE Debug Mode Acknowledge Disable Control (Write Protect) Timer counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN Interrupt Enable Control Note: If this bit is enabled, when the timer interrupt flag (TIF) is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer Interrupt function Disabled #0 1 Timer Interrupt function Enabled #1 OPMODE Timer Operating Mode 27 2 read-write 0 The timer is operating in One-shot mode. The associated interrupt signal is generated once (if INTEN is enabled) and CNTEN is automatically cleared by hardware #00 1 The timer is operating in Periodic mode. The associated interrupt signal is generated periodically (if INTEN is enabled) #01 2 The timer is operating in Toggle mode. The interrupt signal is generated periodically (if INTEN is enabled). The associated signal (tout) is changing back and forth with 50 percent duty cycle #10 3 The timer is operating in Continuous Counting mode. The associated interrupt signal is generated when TIMERx_CNT = TIMERx_CMP (if INTEN is enabled). However, the 24-bit up-timer counts continuously. Please refer to 6.6.5.6 for detailed description about Continuous Counting mode operation #11 PSC Prescale Counter 0 8 read-write RSTCNT Timer Reset 26 1 read-write 0 No effect #0 1 Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit if ACTSTS is 1 #1 WKEN Wake-up Enable Control When WKEN is set and the TIF or CAPIF is set, the timer controller will generator a wake-up trigger event to CPU. 23 1 read-write 0 Wake-up trigger event Disabled #0 1 Wake-up trigger event Enabled #1 TIMER0_EINTSTS TIMER0_EINTSTS Timer0 Extended Event Interrupt Status Register 0x18 -1 read-write n 0x0 0x0 CAPIF Timer Capture Interrupt Flag This bit indicates the timer external capture interrupt flag status. Note1: This bit is cleared by writing 1 to it. Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on ACMPOx matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 0 1 read-write 0 Timer Capture interrupt did not occur #0 1 Timer Capture interrupt occurred #1 TIMER0_EXTCTL TIMER0_EXTCTL Timer0 Extended Event Control Register 0x14 -1 read-write n 0x0 0x0 CAPEDGE Timer Capture Pin Edge Detection 1 2 read-write 0 A falling edge on ACMP_CO0 will be detected #00 1 A rising edge on ACMP_CO0 will be detected #01 2 Either rising or falling edge on ACMP_CO0 will be detected #10 3 Reserved. #11 CAPEN Timer Capture Function Enable Control This bit enables the Timer Capture Function 3 1 read-write 0 Timer Capture Function Disabled #0 1 Timer Capture Function Enabled #1 CAPFUNCS Capture Function Select Bit Note1: When CAPFUNCS is 0, transition on ACMPOx is using to save the 24-bit timer counter value to CAPDAT register. Note2: When CAPFUNCS is 1, transition on ACMPOx is using to reset the 24-bit timer counter value. 4 1 read-write 0 Capture Mode Enabled #0 1 Reset Mode Enabled #1 CAPIEN Timer Capture Interrupt Enable Control 5 1 read-write 0 Timer Capture Interrupt Disabled #0 1 Timer Capture Interrupt Enabled #1 CAPMODE Capture Mode Select Bit 8 1 read-write 0 Timer counter reset function or free-counting mode of timer capture function #0 1 Trigger-counting mode of timer capture function #1 CNTPHASE Timer External Count Pin Phase Detect Selection 0 1 read-write 0 A falling edge of TMx (x = 0~2) pin will be counted #0 1 A rising edge of TMx (x = 0~2) pin will be counted #1 ECNTDBEN Timer Counter Input Pin De-bounce Enable Control 7 1 read-write 0 TMx (x = 0~2) pin de-bounce Disabled #0 1 TMx (x = 0~2) pin de-bounce Enabled #1 TIMER0_INTSTS TIMER0_INTSTS Timer0 Interrupt Status Register 0x8 -1 read-write n 0x0 0x0 TIF Timer Interrupt Flag This bit indicates the interrupt flag status of Timer while CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT value. Note: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT value matches the CMPDAT value #1 TWKF Timer Wake-up Flag This bit indicates the interrupt wake-up flag status of Timer. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated #1 TIMER1_CAP TIMER1_CAP Timer1 Capture Data Register 0x30 -1 read-write n 0x0 0x0 TIMER1_CMP TIMER1_CMP Timer1 Compare Register 0x24 -1 read-write n 0x0 0x0 TIMER1_CNT TIMER1_CNT Timer1 Data Register 0x2C -1 read-write n 0x0 0x0 TIMER1_CTL TIMER1_CTL Timer1 Control and Status Register 0x20 -1 read-write n 0x0 0x0 TIMER1_EINTSTS TIMER1_EINTSTS Timer1 Extended Event Interrupt Status Register 0x38 -1 read-write n 0x0 0x0 TIMER1_EXTCTL TIMER1_EXTCTL Timer1 Extended Event Control Register 0x34 -1 read-write n 0x0 0x0 TIMER1_INTSTS TIMER1_INTSTS Timer1 Interrupt Status Register 0x28 -1 read-write n 0x0 0x0 TIMER2_CAP TIMER2_CAP Timer2 Capture Data Register 0x90 -1 read-write n 0x0 0x0 TIMER2_CMP TIMER2_CMP Timer2 Compare Register 0x84 -1 read-write n 0x0 0x0 TIMER2_CNT TIMER2_CNT Timer2 Data Register 0x8C -1 read-write n 0x0 0x0 TIMER2_CTL TIMER2_CTL Timer2 Control and Status Register 0x80 -1 read-write n 0x0 0x0 TIMER2_EINTSTS TIMER2_EINTSTS Timer2 Extended Event Interrupt Status Register 0x98 -1 read-write n 0x0 0x0 TIMER2_EXTCTL TIMER2_EXTCTL Timer2 Extended Event Control Register 0x94 -1 read-write n 0x0 0x0 TIMER2_INTSTS TIMER2_INTSTS Timer2 Interrupt Status Register 0x88 -1 read-write n 0x0 0x0 TIMER_CCAP0 TIMER_CCAP0 Timer Continuous Capture Data Register 0 0x44 -1 read-only n 0x0 0x0 CAPDAT Timer Continuous Capture Data Register TIMER_CCAP0 store the timer count value of first rising edge TIMER_CCAP1 store the timer count value of first falling edge TIMER_CCAP2 store the timer count value of second rising edge TIMER_CCAP3 store the timer count value of second falling edge 0 24 read-only TIMER_CCAP1 TIMER_CCAP1 Timer Continuous Capture Data Register 1 0x48 -1 read-write n 0x0 0x0 TIMER_CCAP2 TIMER_CCAP2 Timer Continuous Capture Data Register 2 0x4C -1 read-write n 0x0 0x0 TIMER_CCAP3 TIMER_CCAP3 Timer Continuous Capture Data Register 3 0x50 -1 read-write n 0x0 0x0 TIMER_CCAPCTL TIMER_CCAPCTL Timer Continuous Capture Control Register 0x40 -1 read-write n 0x0 0x0 CAPCHSEL Capture Timer Channel Selection Select the channel to be the continuous capture event. 4 1 read-write 0 CCAP_P0 #0 1 CCAP_P1 #1 CAPF1F Capture Falling Edge 1 Flag First falling edge already captured, this bit will be set to 1. Note: This bit is cleared by hardware automatically when writing 1 to this bit. 9 1 read-write 0 None #0 1 CAPDAT(TIMER_CCAP1[23:0]) data is ready for read #1 CAPF2F Capture Falling Edge 2 Flag Second falling edge already captured, this bit will be set to 1 Note: This bit is cleared by hardware automatically when writing 1 to this bit. 11 1 read-write 0 None #0 1 CAPDAT(TIMER_CCAP3[23:0]) data is ready for read #1 CAPR1F Capture Rising Edge 1 Flag First rising edge already captured, this bit will be set to 1. Note: This bit is cleared by hardware automatically when writing 1 to this bit. 8 1 read-write 0 None #0 1 CAPDAT(TIMER_CCAP0[23:0]) data is ready for read #1 CAPR2F Capture Rising Edge 2 Flag Second rising edge already captured, this bit will be set to 1. Note: This bit is cleared by hardware automatically when writing 1 to this bit. 10 1 read-write 0 None #0 1 CAPDAT(TIMER_CCAP2[23:0]) data is ready for read #1 CCAPEN Continuous Capture Enable Control This bit is to be enabled the continuous capture function. Note: This bit is cleared by hardware automatically when capture operation finish or writing 0 to it 0 1 read-write 0 Disabled Continuous capture function #0 1 Enabled Continuous capture function #1 CCAPIEN Capture Interrupt Enable Control 16 2 read-write 0 Interrupt Disabled #00 1 Capture Rising Edge 1 and Falling Edge 1 interrupt Enabled #01 2 Capture Rising Edge 1, Falling dege1 and Rising Edge 2 interrupt Enabled #10 3 Capture Rising Edge 1, Falling dege1, Rising Edge 2 and Falling Edge 2 interrupt Enabled #11 CNTSEL Capture Timer Selection Select the timer to continuous capture the input signal. 2 2 read-write 0 TIMER0 #00 1 TIMER1 #01 2 SysTick #10 3 See CNTSEL2 #11 CNTSEL2 Capture Timer2 Selection 5 3 read-write 0 TIMER2 #000 1 Disable #001 INV Input Signal Inverse Invert the input signal which be captured. 1 1 read-write 0 None #0 1 Inverse #1 NFCLKS Noise Filter Clock Pre-divided Selection To determine the sampling frequency of the Noise Filter clock 25 2 read-write 0 CAPCLK #00 1 CAPCLK / 2 #01 2 CAPCLK / 4 #10 3 CAPCLK / 16 #11 NFDIS Disable Input Capture Noise Filter 24 1 read-write 0 Noise filter of Input Capture Enabled #0 1 The noise filter of Input Capture Disabled #1 UI2C1 UI2C Register Map UI2C 0x0 0x0 0x4 registers n 0x2C 0xC registers n 0x3C 0xC registers n 0x4C 0x4 registers n 0x54 0x14 registers n 0x8 0x4 registers n 0x8C 0x4 registers n UI2C_ADDRMSK0 UI2C_ADDRMSK0 USCI Device Address Mask Register 0 0x4C -1 read-write n 0x0 0x0 ADDRMSK USCI Device Address Mask USCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to 0, that means the received corresponding register bit should be exact the same as address register. 0 10 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 UI2C_BRGEN UI2C_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write PTCLKSEL Protocol Clock Source Selection This bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection This bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 External input clock #1 SPCLKSEL Sample Clock Source Selection This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit This bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter for timeout function is Disabled #0 1 Time measurement counter for timeout function is Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection In I2C mode, this bit need clear to 0 to do timeout measurement counter with fPCLK. 5 1 read-write UI2C_BUFSTS UI2C_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-only n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 TXEMPTY Transmit Buffer Empty Indicator 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 TXFULL Transmit Buffer Full Indicator 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 UI2C_CTL UI2C_CTL USCI Control Register 0x0 -1 read-write n 0x0 0x0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE. Note: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UI2C_DEVADDR0 UI2C_DEVADDR0 USCI Device Address Register 0 0x44 -1 read-write n 0x0 0x0 DEVADDR Device Address In I2C protocol, this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0]. Note: When I2C operating in 7-bit address mode, only use DEVADDR[6:0] 0 10 read-write UI2C_DMACTL UI2C_DMACTL USCI DMA Control Register 0x40 -1 read-write n 0x0 0x0 DMAEN DMA Mode Enable Bit 3 1 read-write 0 DMA function Disabled #0 1 DMA function Enabled #1 DMARST DMA Reset 0 1 read-write 0 No effect #0 1 Reset the USCI's DMA control logic. This bit will be cleared to 0 automatically #1 NACKEN 1: When finish of RXDAM in slave mode, hardware will auto NACK the last byte. 4 1 read-write RXDMAEN DMA Receive Channel Request Enable 2 1 read-write 0 Receive DMA function Disabled #0 1 Receive DMA function Enabled #1 STOPEN 1: When finish of RXDAM in master mode, hardware will auto generate STOP condition 5 1 read-write TXDMAEN DMA Transmit Channel Request Enable 1 1 read-write 0 Transmit DMA function Disabled #0 1 Transmit DMA function Enabled #1 UI2C_LINECTL UI2C_LINECTL USCI Line Control Register 0x2C -1 read-write n 0x0 0x0 DWIDTH Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits. 0x0: The data word contains 16 bits located at bit positions [15:0]. 0x1: Reserved. 0x2: Reserved. 0x3: Reserved. 0x4: The data word contains 4 bits located at bit positions [3:0]. 0x5: The data word contains 5 bits located at bit positions [4:0]. ... 0xF: The data word contains 15 bits located at bit positions [14:0]. Note: In I2C protocol, the length must be configured as 8 bits. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UI2C_PROTCTL UI2C_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 AA Assert Acknowledge Control 1 1 read-write ADDR10EN Address 10-bit Function Enable Bit 4 1 read-write 0 Address match 10 bit function is disabled #0 1 Address match 10 bit function is enabled #1 GCFUNC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 MONEN I2C Monitor Enable Bit 9 1 read-write 0 I2C Monitor disable #0 1 I2C Monitor enable #1 PROTEN I2C Protocol Enable Bit 31 1 read-write 0 I2C Protocol disable #0 1 I2C Protocol enable #1 PTRG I2C Protocol Trigger When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. 5 1 read-write 0 I2C's stretch disabled and the I2C protocol function will go ahead #0 1 I2C's stretch active #1 SCLOUTEN SCL Output Enable Bit 8 1 read-write 0 SCL output force high disable #0 1 SCL output force high enable #1 STA I2C START Control Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 3 1 read-write STO I2C STOP Control 2 1 read-write TOCNT Time-out Clock Cycle This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode. 16 10 read-write UI2C_PROTIEN UI2C_PROTIEN USCI Protocol Interrupt Enable Register 0x60 -1 read-write n 0x0 0x0 ACKIEN Acknowledge Interrupt Enable Control This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. 6 1 read-write 0 The acknowledge interrupt is disabled #0 1 The acknowledge interrupt is enabled #1 ARBLOIEN Arbitration Lost Interrupt Enable Control This bit enables the generation of a protocol interrupt if an arbitration lost event is detected. 4 1 read-write 0 The arbitration lost interrupt is disabled #0 1 The arbitration lost interrupt is enabled #1 ERRIEN Error Interrupt Enable Control This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])). 5 1 read-write 0 The error interrupt is disabled #0 1 The error interrupt is enabled #1 NACKIEN Non - Acknowledge Interrupt Enable Control This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master. 3 1 read-write 0 The non - acknowledge interrupt is disabled #0 1 The non - acknowledge interrupt is enabled #1 STARIEN Start Condition Received Interrupt Enable Control This bit enables the generation of a protocol interrupt if a start condition is detected. 1 1 read-write 0 The start condition interrupt is disabled #0 1 The start condition interrupt is enabled #1 STORIEN Stop Condition Received Interrupt Enable Control This bit enables the generation of a protocol interrupt if a stop condition is detected. 2 1 read-write 0 The stop condition interrupt is disabled #0 1 The stop condition interrupt is enabled #1 TOIEN Time-out Interrupt Enable Control In I2C protocol, this bit enables the interrupt generation in case of a time-out event. 0 1 read-write 0 The time-out interrupt is disabled #0 1 The time-out interrupt is enabled #1 UI2C_PROTSTS UI2C_PROTSTS USCI Protocol Status Register 0x64 -1 read-write n 0x0 0x0 ACKIF Acknowledge Received Interrupt Flag It is cleared by software writing one into this bit 13 1 read-write 0 An acknowledge has not been received #0 1 An acknowledge has been received #1 ARBLOIF Arbitration Lost Interrupt Flag It is cleared by software writing one into this bit 11 1 read-write 0 An arbitration has not been lost #0 1 An arbitration has been lost #1 BUSHANG Bus Hang-up This bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. 18 1 read-write 0 The bus is normal status for transmission #0 1 The bus is hang-up status for transmission #1 ERRIF Error Interrupt Flag It is cleared by software writing one into this bit Note: This bit is set when slave mode, user must write one into STO register to the defined 'not addressed' slave mode. 12 1 read-write 0 An I2C error has not been detected #0 1 An I2C error has been detected #1 NACKIF Non - Acknowledge Received Interrupt Flag It is cleared by software writing one into this bit Note: When this bit is set, the master will generate a stop bit in next transmation, so MCU needs to clear it before transmition. 10 1 read-write 0 A non - acknowledge has not been received #0 1 A non - acknowledge has been received #1 ONBUSY On Bus Busy Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 6 1 read-write 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 SLAREAD Slave Read Request Status This bit indicates that a slave read request has been detected. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. 15 1 read-write 0 A slave read request has not been detected #0 1 A slave read request has been detected #1 SLASEL Slave Select Status This bit indicates that this device has been selected as slave. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. 14 1 read-write 0 The device is not selected as slave #0 1 The device is selected as slave #1 STARIF Start Condition Received Interrupt Flag This bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode. It is cleared by software writing one into this bit 8 1 read-write 0 A start condition has not yet been detected #0 1 A start condition has been detected #1 STORIF Stop Condition Received Interrupt Flag It is cleared by software writing one into this bit 9 1 read-write 0 A stop condition has not yet been detected #0 1 A stop condition has been detected #1 TOIF Time-out Interrupt Flag Note: It is cleared by software writing one into this bit 5 1 read-write 0 A time-out interrupt status has not occurred #0 1 A time-out interrupt status has occurred #1 WKAKDONE Wakeup Address Frame Acknowledge Bit Done Note: This bit can't release when WKUPIF is set. 16 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WRSTSWK Read/Write Status Bit in Address Wakeup Frame 17 1 read-write 0 Write command be record on the address match wakeup frame #0 1 Read command be record on the address match wakeup frame #1 UI2C_RXDAT UI2C_RXDAT USCI Receive Data Register 0x34 -1 read-only n 0x0 0x0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer. Note 1: In I2C protocol, only use RXDAT[7:0]. 0 16 read-only UI2C_TMCTL UI2C_TMCTL I2C Timing Configure Control Register 0x8C -1 read-write n 0x0 0x0 HTCTL Hold Time Configure Control Register This field is used to generate the delay timing between SCL falling edge SDA edge in transmission mode. 6 6 read-write STCTL Setup Time Configure Control Register This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode. 0 6 read-write UI2C_TXDAT UI2C_TXDAT USCI Transmit Data Register 0x30 -1 write-only n 0x0 0x0 GDMASTA I2C START Control (for GDMA only) Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 15 1 write-only GDMASTO I2C STOP Control (for GDMA only) 14 1 write-only TXDAT Transmit Data Software can use this bit field to write 8-bit transmit data for transmission. 0 8 write-only UI2C_WKCTL UI2C_WKCTL USCI Wake-up Control Register 0x54 -1 read-write n 0x0 0x0 WKADDREN Wake-up Address Match Enable Bit 1 1 read-write 0 The chip is woken up according to data toggle #0 1 The chip is woken up according to address match #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UI2C_WKSTS UI2C_WKSTS USCI Wake-up Status Register 0x58 -1 read-write n 0x0 0x0 WKF Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write UI2C2 UI2C Register Map UI2C 0x0 0x0 0x4 registers n 0x2C 0xC registers n 0x3C 0xC registers n 0x4C 0x4 registers n 0x54 0x14 registers n 0x8 0x4 registers n 0x8C 0x4 registers n UI2C_ADDRMSK0 UI2C_ADDRMSK0 USCI Device Address Mask Register 0 0x4C -1 read-write n 0x0 0x0 ADDRMSK USCI Device Address Mask USCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to 0, that means the received corresponding register bit should be exact the same as address register. 0 10 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 UI2C_BRGEN UI2C_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write PTCLKSEL Protocol Clock Source Selection This bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection This bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 External input clock #1 SPCLKSEL Sample Clock Source Selection This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit This bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter for timeout function is Disabled #0 1 Time measurement counter for timeout function is Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection In I2C mode, this bit need clear to 0 to do timeout measurement counter with fPCLK. 5 1 read-write UI2C_BUFSTS UI2C_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-only n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 TXEMPTY Transmit Buffer Empty Indicator 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 TXFULL Transmit Buffer Full Indicator 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 UI2C_CTL UI2C_CTL USCI Control Register 0x0 -1 read-write n 0x0 0x0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE. Note: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UI2C_DEVADDR0 UI2C_DEVADDR0 USCI Device Address Register 0 0x44 -1 read-write n 0x0 0x0 DEVADDR Device Address In I2C protocol, this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0]. Note: When I2C operating in 7-bit address mode, only use DEVADDR[6:0] 0 10 read-write UI2C_DMACTL UI2C_DMACTL USCI DMA Control Register 0x40 -1 read-write n 0x0 0x0 DMAEN DMA Mode Enable Bit 3 1 read-write 0 DMA function Disabled #0 1 DMA function Enabled #1 DMARST DMA Reset 0 1 read-write 0 No effect #0 1 Reset the USCI's DMA control logic. This bit will be cleared to 0 automatically #1 NACKEN 1: When finish of RXDAM in slave mode, hardware will auto NACK the last byte. 4 1 read-write RXDMAEN DMA Receive Channel Request Enable 2 1 read-write 0 Receive DMA function Disabled #0 1 Receive DMA function Enabled #1 STOPEN 1: When finish of RXDAM in master mode, hardware will auto generate STOP condition 5 1 read-write TXDMAEN DMA Transmit Channel Request Enable 1 1 read-write 0 Transmit DMA function Disabled #0 1 Transmit DMA function Enabled #1 UI2C_LINECTL UI2C_LINECTL USCI Line Control Register 0x2C -1 read-write n 0x0 0x0 DWIDTH Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits. 0x0: The data word contains 16 bits located at bit positions [15:0]. 0x1: Reserved. 0x2: Reserved. 0x3: Reserved. 0x4: The data word contains 4 bits located at bit positions [3:0]. 0x5: The data word contains 5 bits located at bit positions [4:0]. ... 0xF: The data word contains 15 bits located at bit positions [14:0]. Note: In I2C protocol, the length must be configured as 8 bits. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UI2C_PROTCTL UI2C_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 AA Assert Acknowledge Control 1 1 read-write ADDR10EN Address 10-bit Function Enable Bit 4 1 read-write 0 Address match 10 bit function is disabled #0 1 Address match 10 bit function is enabled #1 GCFUNC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 MONEN I2C Monitor Enable Bit 9 1 read-write 0 I2C Monitor disable #0 1 I2C Monitor enable #1 PROTEN I2C Protocol Enable Bit 31 1 read-write 0 I2C Protocol disable #0 1 I2C Protocol enable #1 PTRG I2C Protocol Trigger When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. 5 1 read-write 0 I2C's stretch disabled and the I2C protocol function will go ahead #0 1 I2C's stretch active #1 SCLOUTEN SCL Output Enable Bit 8 1 read-write 0 SCL output force high disable #0 1 SCL output force high enable #1 STA I2C START Control Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 3 1 read-write STO I2C STOP Control 2 1 read-write TOCNT Time-out Clock Cycle This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode. 16 10 read-write UI2C_PROTIEN UI2C_PROTIEN USCI Protocol Interrupt Enable Register 0x60 -1 read-write n 0x0 0x0 ACKIEN Acknowledge Interrupt Enable Control This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. 6 1 read-write 0 The acknowledge interrupt is disabled #0 1 The acknowledge interrupt is enabled #1 ARBLOIEN Arbitration Lost Interrupt Enable Control This bit enables the generation of a protocol interrupt if an arbitration lost event is detected. 4 1 read-write 0 The arbitration lost interrupt is disabled #0 1 The arbitration lost interrupt is enabled #1 ERRIEN Error Interrupt Enable Control This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])). 5 1 read-write 0 The error interrupt is disabled #0 1 The error interrupt is enabled #1 NACKIEN Non - Acknowledge Interrupt Enable Control This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master. 3 1 read-write 0 The non - acknowledge interrupt is disabled #0 1 The non - acknowledge interrupt is enabled #1 STARIEN Start Condition Received Interrupt Enable Control This bit enables the generation of a protocol interrupt if a start condition is detected. 1 1 read-write 0 The start condition interrupt is disabled #0 1 The start condition interrupt is enabled #1 STORIEN Stop Condition Received Interrupt Enable Control This bit enables the generation of a protocol interrupt if a stop condition is detected. 2 1 read-write 0 The stop condition interrupt is disabled #0 1 The stop condition interrupt is enabled #1 TOIEN Time-out Interrupt Enable Control In I2C protocol, this bit enables the interrupt generation in case of a time-out event. 0 1 read-write 0 The time-out interrupt is disabled #0 1 The time-out interrupt is enabled #1 UI2C_PROTSTS UI2C_PROTSTS USCI Protocol Status Register 0x64 -1 read-write n 0x0 0x0 ACKIF Acknowledge Received Interrupt Flag It is cleared by software writing one into this bit 13 1 read-write 0 An acknowledge has not been received #0 1 An acknowledge has been received #1 ARBLOIF Arbitration Lost Interrupt Flag It is cleared by software writing one into this bit 11 1 read-write 0 An arbitration has not been lost #0 1 An arbitration has been lost #1 BUSHANG Bus Hang-up This bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. 18 1 read-write 0 The bus is normal status for transmission #0 1 The bus is hang-up status for transmission #1 ERRIF Error Interrupt Flag It is cleared by software writing one into this bit Note: This bit is set when slave mode, user must write one into STO register to the defined 'not addressed' slave mode. 12 1 read-write 0 An I2C error has not been detected #0 1 An I2C error has been detected #1 NACKIF Non - Acknowledge Received Interrupt Flag It is cleared by software writing one into this bit Note: When this bit is set, the master will generate a stop bit in next transmation, so MCU needs to clear it before transmition. 10 1 read-write 0 A non - acknowledge has not been received #0 1 A non - acknowledge has been received #1 ONBUSY On Bus Busy Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 6 1 read-write 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 SLAREAD Slave Read Request Status This bit indicates that a slave read request has been detected. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. 15 1 read-write 0 A slave read request has not been detected #0 1 A slave read request has been detected #1 SLASEL Slave Select Status This bit indicates that this device has been selected as slave. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. 14 1 read-write 0 The device is not selected as slave #0 1 The device is selected as slave #1 STARIF Start Condition Received Interrupt Flag This bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode. It is cleared by software writing one into this bit 8 1 read-write 0 A start condition has not yet been detected #0 1 A start condition has been detected #1 STORIF Stop Condition Received Interrupt Flag It is cleared by software writing one into this bit 9 1 read-write 0 A stop condition has not yet been detected #0 1 A stop condition has been detected #1 TOIF Time-out Interrupt Flag Note: It is cleared by software writing one into this bit 5 1 read-write 0 A time-out interrupt status has not occurred #0 1 A time-out interrupt status has occurred #1 WKAKDONE Wakeup Address Frame Acknowledge Bit Done Note: This bit can't release when WKUPIF is set. 16 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WRSTSWK Read/Write Status Bit in Address Wakeup Frame 17 1 read-write 0 Write command be record on the address match wakeup frame #0 1 Read command be record on the address match wakeup frame #1 UI2C_RXDAT UI2C_RXDAT USCI Receive Data Register 0x34 -1 read-only n 0x0 0x0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer. Note 1: In I2C protocol, only use RXDAT[7:0]. 0 16 read-only UI2C_TMCTL UI2C_TMCTL I2C Timing Configure Control Register 0x8C -1 read-write n 0x0 0x0 HTCTL Hold Time Configure Control Register This field is used to generate the delay timing between SCL falling edge SDA edge in transmission mode. 6 6 read-write STCTL Setup Time Configure Control Register This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode. 0 6 read-write UI2C_TXDAT UI2C_TXDAT USCI Transmit Data Register 0x30 -1 write-only n 0x0 0x0 GDMASTA I2C START Control (for GDMA only) Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 15 1 write-only GDMASTO I2C STOP Control (for GDMA only) 14 1 write-only TXDAT Transmit Data Software can use this bit field to write 8-bit transmit data for transmission. 0 8 write-only UI2C_WKCTL UI2C_WKCTL USCI Wake-up Control Register 0x54 -1 read-write n 0x0 0x0 WKADDREN Wake-up Address Match Enable Bit 1 1 read-write 0 The chip is woken up according to data toggle #0 1 The chip is woken up according to address match #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UI2C_WKSTS UI2C_WKSTS USCI Wake-up Status Register 0x58 -1 read-write n 0x0 0x0 WKF Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write USPI1 USPI Register Map USPI 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x1C registers n 0x54 0x14 registers n USPI_BRGEN USPI_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider Note: For I2C function, the minimum value of CLKDIV is 8. 16 10 read-write PTCLKSEL Protocol Clock Source Selection This bit selects the source of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection This bit selects the source of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 External input clock #1 SPCLKSEL Sample Clock Source Selection This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fDIV_CLK #00 1 fPROT_CLK #01 2 fSCLK #10 3 fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit This bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter is Disabled #0 1 Time measurement counter is Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection 5 1 read-write 0 Time measurement counter with fPROT_CLK., #0 1 Time measurement counter with fDIV_CLK., #1 USPI_BUFCTL USPI_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 -1 read-write n 0x0 0x0 RXCLR Clear Receive Buffer Note: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Interrupt Enable Control 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset Note: It is cleared automatically after one PCLK cycle. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer Note: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset Note: It is cleared automatically after one PCLK cycle. 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 TXUDRIEN Slave Transmit Under-run Interrupt Enable Bit 6 1 read-write 0 Transmit under-run interrupt Disabled #0 1 Transmit under-run interrupt Enabled #1 USPI_BUFSTS USPI_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-write n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator 0 1 read-write 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator 1 1 read-write 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Overrun Interrupt Status This bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit. 3 1 read-write 0 A receive buffer overrun event has not been detected #0 1 A receive buffer overrun event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator 8 1 read-write 0 Transmit buffer is not empty #0 1 Transmit buffer is empty and available for the next transmission datum #1 TXFULL Transmit Buffer Full Indicator 9 1 read-write 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 TXUDRIF Transmit Buffer Under-run Interrupt Status This bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit 11 1 read-write 0 A transmit buffer under-run event has not been detected #0 1 A transmit buffer under-run event has been detected #1 USPI_CLKIN USPI_CLKIN USCI Input Clock Signal Configuration Register 0x28 -1 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. Note: In SPI protocol, it is suggested that the bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_CTL USPI_CTL USCI Control Register 0x0 -1 read-write n 0x0 0x0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE. Note: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 USPI_CTLIN0 USPI_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 -1 read-write n 0x0 0x0 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. Note: In SPI protocol, it is suggested that the bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_DATIN0 USPI_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 -1 read-write n 0x0 0x0 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. Note: In SPI protocol, it is suggested that the bit should be set as 0. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. Note: In SPI protocol, it is suggested that the bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_DMACTL USPI_DMACTL USCI DMA Control Register 0x40 -1 read-write n 0x0 0x0 DMAEN DMA Mode Enable Bit 3 1 read-write 0 DMA function Disabled #0 1 DMA function Enabled #1 DMARST DMA Reset 0 1 read-write 0 No effect #0 1 Reset the USCI's DMA control logic. This bit will be cleared to 0 automatically #1 RXDMAEN DMA Receive Channel Request Enable 2 1 read-write 0 Receive DMA function Disabled #0 1 Receive DMA function Enabled #1 TXDMAEN DMA Transmit Channel Request Enable 1 1 read-write 0 Transmit DMA function Disabled #0 1 Transmit DMA function Enabled #1 USPI_INTEN USPI_INTEN USCI Interrupt Enable Register 0x4 -1 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit This bit enables the interrupt generation in case of a receive finish event. 4 1 read-write 0 The receive end interrupt is disabled #0 1 The receive end interrupt is enabled #1 RXSTIEN Receive Start Interrupt Enable Bit This bit enables the interrupt generation in case of a receive start event. 3 1 read-write 0 The receive start interrupt is disabled #0 1 The receive start interrupt is enabled #1 TXENDIEN Transmit End Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit finish event. 2 1 read-write 0 The transmit finish interrupt is disabled #0 1 The transmit finish interrupt is enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit start event. 1 1 read-write 0 The transmit start interrupt is disabled #0 1 The transmit start interrupt is enabled #1 USPI_LINECTL USPI_LINECTL USCI Line Control Register 0x2C -1 read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection This bit defines the relation between the internal control signal and the output control signal. Note: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin. 5 1 read-write 0 Data output level is not inverted #0 1 Data output level is inverted #1 DWIDTH Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits. 0x0: The data word contains 16 bits located at bit positions [15:0]. 0x1: Reserved. 0x2: Reserved. 0x3: Reserved. 0x4: The data word contains 4 bits located at bit positions [3:0]. 0x5: The data word contains 5 bits located at bit positions [4:0]. ... 0xF: The data word contains 15 bits located at bit positions [14:0]. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 USPI_PROTCTL USPI_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable (Master Only) 3 1 read-write 0 Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit #0 1 Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 PROTEN SPI Protocol Enable Bit 31 1 read-write 0 SPI Protocol Disabled #0 1 SPI Protocol Enabled #1 SCLKMODE Serial Bus Clock Mode This bit field defines the SCLK idle status, data transmit, and data receive edge. 6 2 read-write SLAVE Slave Mode Selection 0 1 read-write 0 Master mode #0 1 Slave mode #1 SLV3WIRE Slave 3-wire Mode Selection (Slave Only) The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. 1 1 read-write 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 SLVTOCNT Slave Mode Time-out Period (Slave Only) In Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function. Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. 16 10 read-write SS Slave Select Control (Master Only) If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state. Note: In SPI protocol, the internal slave select signal is active high. 2 1 read-write SUSPITV Suspend Interval (Master Only) This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation. (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle Example: 8 4 read-write TSMSEL Transmit Data Mode Selection This bit field describes how receive and transmit data is shifted in and out. Other values are reserved. Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. 12 3 read-write TXUDRPOL Transmit Under-run Data Polarity (for Slave) This bit defines the transmitting data level when no data is available for transferring. 28 1 read-write 0 The output data level is 0 if TX under-run event occurs #0 1 The output data level is 1 if TX under-run event occurs #1 USPI_PROTIEN USPI_PROTIEN USCI Protocol Interrupt Enable Register 0x60 -1 read-write n 0x0 0x0 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Control If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]). Bit count error event occurs. 3 1 read-write 0 Slave mode bit count error interrupt Disabled #0 1 Slave mode bit count error interrupt Enabled #1 SLVTOIEN Slave Time-out Interrupt Enable Control In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. 2 1 read-write 0 Slave time-out interrupt Disabled #0 1 Slave time-out interrupt Enabled #1 SSACTIEN Slave Select Active Interrupt Enable Control This bit enables/disables the generation of a slave select interrupt if the slave select changes to active. 1 1 read-write 0 Slave select active interrupt generation Disabled #0 1 Slave select active interrupt generation Enabled #1 SSINAIEN Slave Select Inactive Interrupt Enable Control This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. 0 1 read-write 0 Slave select inactive interrupt generation Disabled #0 1 Slave select inactive interrupt generation Enabled #1 USPI_PROTSTS USPI_PROTSTS USCI Protocol Status Register 0x64 -1 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 17 1 read-only 0 SPI is in idle state #0 1 SPI is in busy state #1 RXENDIF Receive End Interrupt Flag Note: It is cleared by software writes 1 to this bit 4 1 read-write 0 Receive end event does not occur #0 1 Receive end event occurs #1 RXSTIF Receive Start Interrupt Flag Note: It is cleared by software writes 1 to this bit 3 1 read-write 0 Receive start event does not occur #0 1 Receive start event occurs #1 SLVBEIF Slave Bit Count Error Interrupt Flag (for Slave Only) Note: It is cleared by software writes 1 to this bit. 6 1 read-write 0 Slave bit count error event does not occur #0 1 Slave bit count error event occurs #1 SLVTOIF Slave Time-out Interrupt Flag (for Slave Only) Note: It is cleared by software writes 1 to this bit 5 1 read-write 0 Slave time-out event does not occur #0 1 Slave time-out event occurs #1 SLVUDR Slave Mode Transmit Under-run Status (Read Only) In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. 18 1 read-only 0 Slave transmit under-run event does not occur #0 1 Slave transmit under-run event occurs #1 SSACTIF Slave Select Active Interrupt Flag (for Slave Only) This bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit Note: The internal slave select signal is active high. 9 1 read-write 0 The slave select signal has not changed to active #0 1 The slave select signal has changed to active #1 SSINAIF Slave Select Inactive Interrupt Flag (for Slave Only) This bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit Note: The internal slave select signal is active high. 8 1 read-write 0 The slave select signal has not changed to inactive #0 1 The slave select signal has changed to inactive #1 SSLINE Slave Select Line Bus Status (Read Only) This bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus. 16 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXENDIF Transmit End Interrupt Flag Note: It is cleared by software writes 1 to this bit 2 1 read-write 0 Transmit end event does not occur #0 1 Transmit end event occurs #1 TXSTIF Transmit Start Interrupt Flag Note: It is cleared by software writes 1 to this bit 1 1 read-write 0 Transmit start event does not occur #0 1 Transmit start event occurs #1 USPI_RXDAT USPI_RXDAT USCI Receive Data Register 0x34 -1 read-only n 0x0 0x0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer. 0 16 read-only USPI_TXDAT USPI_TXDAT USCI Transmit Data Register 0x30 -1 write-only n 0x0 0x0 PORTDIR Port Direction Control 16 1 write-only 0 The data pin is configured as output mode #0 1 The data pin is configured as input mode #1 TXDAT Transmit Data Software can use this bit field to write 16-bit transmit data for transmission.To avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. 0 16 write-only USPI_WKCTL USPI_WKCTL USCI Wake-up Control Register 0x54 -1 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 USPI_WKSTS USPI_WKSTS USCI Wake-up Status Register 0x58 -1 read-write n 0x0 0x0 WKF Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write UUART1 UUART Register Map UUART 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x1C registers n 0x54 0x14 registers n UUART_BRGEN UUART_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write DSCNT Denominator for Sample Counter This bit field defines the divide ratio of the sample clock fSAMP_CLK. Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection This bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection This bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 External input clock #1 SPCLKSEL Sample Clock Source Selection This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Timing Measurement Counter Enable Bit This bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Timing measurement counter for auto baudrate is Disabled #0 1 Timing measurement counter for auto baudrate is Enabled #1 TMCNTSRC Timing Measurement Counter Clock Source Selection 5 1 read-write 0 Timing measurement counter with fPROT_CLK #0 1 Timing measurement counter with fDIV_CLK #1 UUART_BUFCTL UUART_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 -1 read-write n 0x0 0x0 RXCLR Clear Receive Buffer Note: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Error Interrupt Enable Control 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset Note 1: It is cleared automatically after one PCLK cycle. Note 2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer Note: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset Note: It is cleared automatically after one PCLK cycle. 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 UUART_BUFSTS UUART_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-write n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator 0 1 read-write 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator 1 1 read-write 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Over-run Error Interrupt Status This bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit. 3 1 read-write 0 A receive buffer overrun error event has not been detected #0 1 A receive buffer overrun error event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator 8 1 read-write 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 TXFULL Transmit Buffer Full Indicator 9 1 read-write 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 UUART_CLKIN UUART_CLKIN USCI Input Clock Signal Configuration Register 0x28 -1 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_CTL UUART_CTL USCI Control Register 0x0 -1 read-write n 0x0 0x0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE. Note: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UUART_CTLIN0 UUART_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 -1 read-write n 0x0 0x0 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_DATIN0 UUART_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 -1 read-write n 0x0 0x0 EDGEDET Input Signal Edge Detection Mode This bit field selects which edge actives the trigger event of input data signal. Note: In UART function mode, it is suggested to set this bit field as 10. 3 2 read-write 0 The trigger event activation is disabled #00 1 A rising edge activates the trigger event of input data signal #01 2 A falling edge activates the trigger event of input data signal #10 3 Both edges activate the trigger event of input data signal #11 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_DMACTL UUART_DMACTL USCI DMA Control Register 0x40 -1 read-write n 0x0 0x0 DMAEN DMA Mode Enable Bit 3 1 read-write 0 DMA function Disabled #0 1 DMA function Enabled #1 DMARST DMA Reset 0 1 read-write 0 No effect #0 1 Reset the USCI's DMA control logic. This bit will be cleared to 0 automatically #1 RXDMAEN DMA Receive Channel Request Enable 2 1 read-write 0 Receive DMA function Disabled #0 1 Receive DMA function Enabled #1 TXDMAEN DMA Transmit Channel Request Enable 1 1 read-write 0 Transmit DMA function Disabled #0 1 Transmit DMA function Enabled #1 UUART_INTEN UUART_INTEN USCI Interrupt Enable Register 0x4 -1 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit This bit enables the interrupt generation in case of a receive finish event. 4 1 read-write 0 The receive end interrupt is disabled #0 1 The receive end interrupt is enabled #1 RXSTIEN Receive Start Interrupt Enable Bit This bit enables the interrupt generation in case of a receive start event. 3 1 read-write 0 The receive start interrupt is disabled #0 1 The receive start interrupt is enabled #1 TXENDIEN Transmit End Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit finish event. 2 1 read-write 0 The transmit finish interrupt is disabled #0 1 The transmit finish interrupt is enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit start event. 1 1 read-write 0 The transmit start interrupt is disabled #0 1 The transmit start interrupt is enabled #1 UUART_LINECTL UUART_LINECTL USCI Line Control Register 0x2C -1 read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection This bit defines the relation between the internal control signal and the output control signal. Note: In UART protocol, the control signal means nRTS signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. 5 1 read-write 0 The value of USCIx_DAT1 is equal to the data shift register #0 1 The value of USCIx_DAT1 is the inversion of data shift register #1 DWIDTH Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits. 0x0: The data word contains 16 bits located at bit positions [15:0]. 0x1: Reserved. 0x2: Reserved. 0x3: Reserved. 0x4: The data word contains 4 bits located at bit positions [3:0]. 0x5: The data word contains 5 bits located at bit positions [4:0]. ... 0xF: The data word contains 15 bits located at bit positions [14:0]. Note: In UART protocol, the length can be configured as 6~13 bits. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UUART_PROTCTL UUART_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 ABREN Auto-baud Rate Detect Enable Bit Note: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled). 6 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 BCEN Transmit Break Control Enable Bit Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 29 1 read-write 0 Transmit Break Control Disabled #0 1 Transmit Break Control Enabled #1 BRDETITV Baud Rate Detection Interval This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set. Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV. 16 9 read-write DATWKEN Data Wake-up Mode Enable Bit 9 1 read-write 0 Data wake-up mode Disabled #0 1 Data wake-up mode Enabled #1 EVENPARITY Even Parity Enable Bit Note: This bit has effect only when PARITYEN is set. 2 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 LINBRKEN LIN TX Break Mode Enable Control Note 1: When TX break field transfer operation is finished, this bit will be cleared automatically. Note 2: 13-bit level 0 and 1-bit level 1 were sent out before the 1st data be transmitted. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 LINRXEN LIN RX Duplex Mode Enable Control Note: This bit is used to check the break duration for incoming data when the LIN operation is active. 8 1 read-write 0 LIN RX Duplex mode Disabled #0 1 LIN RX Duplex mode Enabled. The LIN can be play as Slave to receive the LIN frame #1 PARITYEN Parity Enable Bit This bit defines the parity bit is enabled in an UART frame. 1 1 read-write 0 The parity bit Disabled #0 1 The parity bit Enabled #1 PROTEN UART Protocol Enable Bit 31 1 read-write 0 UART Protocol Disabled #0 1 UART Protocol Enabled #1 STICKEN Stick Parity Enable Bit 26 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 STOPB Stop Bits This bit defines the number of stop bits in an UART frame. 0 1 read-write 0 The number of stop bits is 1 #0 1 The number of stop bits is 2 #1 WAKECNT Wake-up Counter These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. 11 4 read-write UUART_PROTIEN UUART_PROTIEN USCI Protocol Interrupt Enable Register 0x60 -1 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 1 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 BRKIEN LIN Break Detected Interrupt Enable Control 0 1 read-write 0 The LIN break detected interrupt generation is Disabled #0 1 The LIN break detected interrupt generation is Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. 2 1 read-write 0 Receive line status interrupt Disabled #0 1 Receive line status interrupt Enabled #1 UUART_PROTSTS UUART_PROTSTS USCI Protocol Status Register 0x64 -1 read-write n 0x0 0x0 ABERRSTS Auto-baud Rate Error Status This bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again. Note 1: This bit is set at the same time of ABRDETIF. Note 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS. 11 1 read-write 0 Auto-baud rate detect counter is not overrun #0 1 Auto-baud rate detect counter is overrun #1 ABRDETIF Auto-baud Rate Interrupt Flag This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 3 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. Note: This bit can be cleared by writing '1' to it. 9 1 read-write 0 Auto-baud rate detect function is not done #0 1 One Bit auto-baud rate detect function is done #1 BREAK Break Flag This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits). Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 7 1 read-write 0 No Break is generated #0 1 Break is generated in the receiver bus #1 BRKDETIF LIN Break Detected Interrupt Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than 12-bit transmission time in LIN mode function. Note: This bit is read only, but can be cleared by writing '1' to it. 8 1 read-only 0 LIN Break is no detected #0 1 LIN Break is detected #1 FRMERR Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 6 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PARITYERR Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 5 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXBUSY RX Bus Status Flag (Read Only) This bit indicates the busy status of the receiver. 10 1 read-only 0 The receiver is Idle #0 1 The receiver is BUSY #1 RXENDIF Receive End Interrupt Flag Note: It is cleared by software writing one into this bit. 4 1 read-write 0 A receive finish interrupt status has not occurred #0 1 A receive finish interrupt status has occurred #1 RXSTIF Receive Start Interrupt Flag Note: It is cleared by software writing one into this bit. 3 1 read-write 0 A receive start interrupt status has not occurred #0 1 A receive start interrupt status has occurred #1 TXENDIF Transmit End Interrupt Flag Note: It is cleared by software writing one into this bit. 2 1 read-write 0 A transmit end interrupt status has not occurred #0 1 A transmit end interrupt status has occurred #1 TXSTIF Transmit Start Interrupt Flag Note 1: It is cleared by software writing one into this bit. Note 2: Used for user to load next transmit data when there is no data in transmit buffer. 1 1 read-write 0 A transmit start interrupt status has not occurred #0 1 A transmit start interrupt status has occurred #1 UUART_RXDAT UUART_RXDAT USCI Receive Data Register 0x34 -1 read-only n 0x0 0x0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer. Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]). 0 16 read-only UUART_TXDAT UUART_TXDAT USCI Transmit Data Register 0x30 -1 write-only n 0x0 0x0 TXDAT Transmit Data Software can use this bit field to write 16-bit transmit data for transmission. 0 16 write-only UUART_WKCTL UUART_WKCTL USCI Wake-up Control Register 0x54 -1 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UUART_WKSTS UUART_WKSTS USCI Wake-up Status Register 0x58 -1 read-write n 0x0 0x0 WKF Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write UUART2 UUART Register Map UUART 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x1C registers n 0x54 0x14 registers n UUART_BRGEN UUART_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write DSCNT Denominator for Sample Counter This bit field defines the divide ratio of the sample clock fSAMP_CLK. Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection This bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection This bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 External input clock #1 SPCLKSEL Sample Clock Source Selection This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Timing Measurement Counter Enable Bit This bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Timing measurement counter for auto baudrate is Disabled #0 1 Timing measurement counter for auto baudrate is Enabled #1 TMCNTSRC Timing Measurement Counter Clock Source Selection 5 1 read-write 0 Timing measurement counter with fPROT_CLK #0 1 Timing measurement counter with fDIV_CLK #1 UUART_BUFCTL UUART_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 -1 read-write n 0x0 0x0 RXCLR Clear Receive Buffer Note: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Error Interrupt Enable Control 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset Note 1: It is cleared automatically after one PCLK cycle. Note 2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer Note: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset Note: It is cleared automatically after one PCLK cycle. 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 UUART_BUFSTS UUART_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-write n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator 0 1 read-write 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator 1 1 read-write 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Over-run Error Interrupt Status This bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit. 3 1 read-write 0 A receive buffer overrun error event has not been detected #0 1 A receive buffer overrun error event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator 8 1 read-write 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 TXFULL Transmit Buffer Full Indicator 9 1 read-write 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 UUART_CLKIN UUART_CLKIN USCI Input Clock Signal Configuration Register 0x28 -1 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_CTL UUART_CTL USCI Control Register 0x0 -1 read-write n 0x0 0x0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE. Note: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UUART_CTLIN0 UUART_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 -1 read-write n 0x0 0x0 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_DATIN0 UUART_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 -1 read-write n 0x0 0x0 EDGEDET Input Signal Edge Detection Mode This bit field selects which edge actives the trigger event of input data signal. Note: In UART function mode, it is suggested to set this bit field as 10. 3 2 read-write 0 The trigger event activation is disabled #00 1 A rising edge activates the trigger event of input data signal #01 2 A falling edge activates the trigger event of input data signal #10 3 Both edges activate the trigger event of input data signal #11 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_DMACTL UUART_DMACTL USCI DMA Control Register 0x40 -1 read-write n 0x0 0x0 DMAEN DMA Mode Enable Bit 3 1 read-write 0 DMA function Disabled #0 1 DMA function Enabled #1 DMARST DMA Reset 0 1 read-write 0 No effect #0 1 Reset the USCI's DMA control logic. This bit will be cleared to 0 automatically #1 RXDMAEN DMA Receive Channel Request Enable 2 1 read-write 0 Receive DMA function Disabled #0 1 Receive DMA function Enabled #1 TXDMAEN DMA Transmit Channel Request Enable 1 1 read-write 0 Transmit DMA function Disabled #0 1 Transmit DMA function Enabled #1 UUART_INTEN UUART_INTEN USCI Interrupt Enable Register 0x4 -1 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit This bit enables the interrupt generation in case of a receive finish event. 4 1 read-write 0 The receive end interrupt is disabled #0 1 The receive end interrupt is enabled #1 RXSTIEN Receive Start Interrupt Enable Bit This bit enables the interrupt generation in case of a receive start event. 3 1 read-write 0 The receive start interrupt is disabled #0 1 The receive start interrupt is enabled #1 TXENDIEN Transmit End Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit finish event. 2 1 read-write 0 The transmit finish interrupt is disabled #0 1 The transmit finish interrupt is enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit start event. 1 1 read-write 0 The transmit start interrupt is disabled #0 1 The transmit start interrupt is enabled #1 UUART_LINECTL UUART_LINECTL USCI Line Control Register 0x2C -1 read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection This bit defines the relation between the internal control signal and the output control signal. Note: In UART protocol, the control signal means nRTS signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. 5 1 read-write 0 The value of USCIx_DAT1 is equal to the data shift register #0 1 The value of USCIx_DAT1 is the inversion of data shift register #1 DWIDTH Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits. 0x0: The data word contains 16 bits located at bit positions [15:0]. 0x1: Reserved. 0x2: Reserved. 0x3: Reserved. 0x4: The data word contains 4 bits located at bit positions [3:0]. 0x5: The data word contains 5 bits located at bit positions [4:0]. ... 0xF: The data word contains 15 bits located at bit positions [14:0]. Note: In UART protocol, the length can be configured as 6~13 bits. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UUART_PROTCTL UUART_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 ABREN Auto-baud Rate Detect Enable Bit Note: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled). 6 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 BCEN Transmit Break Control Enable Bit Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 29 1 read-write 0 Transmit Break Control Disabled #0 1 Transmit Break Control Enabled #1 BRDETITV Baud Rate Detection Interval This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set. Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV. 16 9 read-write DATWKEN Data Wake-up Mode Enable Bit 9 1 read-write 0 Data wake-up mode Disabled #0 1 Data wake-up mode Enabled #1 EVENPARITY Even Parity Enable Bit Note: This bit has effect only when PARITYEN is set. 2 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 LINBRKEN LIN TX Break Mode Enable Control Note 1: When TX break field transfer operation is finished, this bit will be cleared automatically. Note 2: 13-bit level 0 and 1-bit level 1 were sent out before the 1st data be transmitted. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 LINRXEN LIN RX Duplex Mode Enable Control Note: This bit is used to check the break duration for incoming data when the LIN operation is active. 8 1 read-write 0 LIN RX Duplex mode Disabled #0 1 LIN RX Duplex mode Enabled. The LIN can be play as Slave to receive the LIN frame #1 PARITYEN Parity Enable Bit This bit defines the parity bit is enabled in an UART frame. 1 1 read-write 0 The parity bit Disabled #0 1 The parity bit Enabled #1 PROTEN UART Protocol Enable Bit 31 1 read-write 0 UART Protocol Disabled #0 1 UART Protocol Enabled #1 STICKEN Stick Parity Enable Bit 26 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 STOPB Stop Bits This bit defines the number of stop bits in an UART frame. 0 1 read-write 0 The number of stop bits is 1 #0 1 The number of stop bits is 2 #1 WAKECNT Wake-up Counter These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. 11 4 read-write UUART_PROTIEN UUART_PROTIEN USCI Protocol Interrupt Enable Register 0x60 -1 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 1 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 BRKIEN LIN Break Detected Interrupt Enable Control 0 1 read-write 0 The LIN break detected interrupt generation is Disabled #0 1 The LIN break detected interrupt generation is Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. 2 1 read-write 0 Receive line status interrupt Disabled #0 1 Receive line status interrupt Enabled #1 UUART_PROTSTS UUART_PROTSTS USCI Protocol Status Register 0x64 -1 read-write n 0x0 0x0 ABERRSTS Auto-baud Rate Error Status This bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again. Note 1: This bit is set at the same time of ABRDETIF. Note 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS. 11 1 read-write 0 Auto-baud rate detect counter is not overrun #0 1 Auto-baud rate detect counter is overrun #1 ABRDETIF Auto-baud Rate Interrupt Flag This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 3 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. Note: This bit can be cleared by writing '1' to it. 9 1 read-write 0 Auto-baud rate detect function is not done #0 1 One Bit auto-baud rate detect function is done #1 BREAK Break Flag This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits). Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 7 1 read-write 0 No Break is generated #0 1 Break is generated in the receiver bus #1 BRKDETIF LIN Break Detected Interrupt Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than 12-bit transmission time in LIN mode function. Note: This bit is read only, but can be cleared by writing '1' to it. 8 1 read-only 0 LIN Break is no detected #0 1 LIN Break is detected #1 FRMERR Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 6 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PARITYERR Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 5 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXBUSY RX Bus Status Flag (Read Only) This bit indicates the busy status of the receiver. 10 1 read-only 0 The receiver is Idle #0 1 The receiver is BUSY #1 RXENDIF Receive End Interrupt Flag Note: It is cleared by software writing one into this bit. 4 1 read-write 0 A receive finish interrupt status has not occurred #0 1 A receive finish interrupt status has occurred #1 RXSTIF Receive Start Interrupt Flag Note: It is cleared by software writing one into this bit. 3 1 read-write 0 A receive start interrupt status has not occurred #0 1 A receive start interrupt status has occurred #1 TXENDIF Transmit End Interrupt Flag Note: It is cleared by software writing one into this bit. 2 1 read-write 0 A transmit end interrupt status has not occurred #0 1 A transmit end interrupt status has occurred #1 TXSTIF Transmit Start Interrupt Flag Note 1: It is cleared by software writing one into this bit. Note 2: Used for user to load next transmit data when there is no data in transmit buffer. 1 1 read-write 0 A transmit start interrupt status has not occurred #0 1 A transmit start interrupt status has occurred #1 UUART_RXDAT UUART_RXDAT USCI Receive Data Register 0x34 -1 read-only n 0x0 0x0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer. Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]). 0 16 read-only UUART_TXDAT UUART_TXDAT USCI Transmit Data Register 0x30 -1 write-only n 0x0 0x0 TXDAT Transmit Data Software can use this bit field to write 16-bit transmit data for transmission. 0 16 write-only UUART_WKCTL UUART_WKCTL USCI Wake-up Control Register 0x54 -1 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UUART_WKSTS UUART_WKSTS USCI Wake-up Status Register 0x58 -1 read-write n 0x0 0x0 WKF Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write WDT WDT Register Map WDT 0x0 0x0 0x4 registers n CTL WDT_CTL Watchdog Timer Control Register 0x0 -1 read-write n 0x0 0x0 ICEDEBUG ICE Debug Mode Acknowledge Disable Control (Write Protect) WDT up counter will keep going no matter CPU is hanging by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects WDT counting #0 1 ICE debug mode acknowledgement Disabled #1 IF Watchdog Timer Time-out Interrupt Flag This bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval and INTEN is enabled. Note: This bit is cleared by writing 1 to it. 3 1 read-write 0 WDT time-out interrupt did not occur #0 1 WDT time-out interrupt occurred #1 INTEN Watchdog Timer Time-out Interrupt Enable Control (Write Protect) If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. 6 1 read-write 0 WDT time-out interrupt Disabled #0 1 WDT time-out interrupt Enabled #1 RSTCNT Reset Watchdog Timer Up Counter (Write Protect) Note: This bit will be automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Reset the internal 18-bit WDT up counter value #1 RSTEN Watchdog Timer Time-out Reset Enable Control (Write Protect) Setting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period (1024 * TWDT) expires. 1 1 read-write 0 WDT time-out reset function Disabled #0 1 WDT time-out reset function Enabled #1 RSTF Watchdog Timer Time-out Reset Flag This bit indicates the system has been reset by WDT time-out reset or not. Note: This bit is cleared by writing 1 to it. 2 1 read-write 0 WDT time-out reset did not occur #0 1 WDT time-out reset occurred #1 TOUTSEL Watchdog Timer Interval Selection(Write Protect) These three bits select the time-out interval for the Watchdog Timer. 8 3 read-write 0 24 * TWDT #000 1 26 * TWDT #001 2 28 * TWDT #010 3 210 * TWDT #011 4 212 * TWDT #100 5 214 * TWDT #101 6 216 * TWDT #110 7 218 * TWDT #111 WDTEN Watchdog Timer Enable Control (Write Protect) 7 1 read-write 0 WDT Disabled. (This action will reset the internal up counter value.) #0 1 WDT Enabled #1 WKEN Watchdog Timer Time-out Wake-up Function Control (Write Protect) If this bit is set to 1, while IF is generated to 1 and INTEN enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. Note: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator. 4 1 read-write 0 Wake-up trigger event Disabled if WDT time-out interrupt signal generated #0 1 Wake-up trigger event Enabled if WDT time-out interrupt signal generated #1 WKF Watchdog Timer Time-out Wake-up Flag This bit indicates the interrupt wake-up flag status of WDT. Note: This bit is cleared by writing 1 to it. 5 1 read-write 0 WDT does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated #1 WTTOF Watchdog Timer Time-out Flag This bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval. Note: This bit is cleared by writing 1 to it. 12 1 read-write 0 WDT time-out did not occur #0 1 WDT time-out occurred #1