nuvoTon
NM1810AE_v1
2024.04.29
NM1810AE_v1 SVD file
8
32
ACMP
ACMP Register Map
ACMP
0x0
0x0
0x14
registers
n
ACMP0_CTL
ACMP0_CTL
Analog Comparator0 Control Register
0x0
read-write
n
0x0
0x0
ACMPEN
Comparator Enable Bit\nComparator output needs to wait 2 us stable time after CMPEN is set.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
ACMPHYSEN
Comparator0 Hysteresis Enable (Only 20mV)\n
2
2
read-write
0
ACMP0 Hysteresis function Disabled (Default)
#00
1
ACMP0 Hysteresis function at comparator 0 Enabled that the typical range is 20mV
#01
ACMPIE
Comparator Interrupt Enable Bit
Note1: Interrupt is generated if ACMPIE bit is set to 1 after ACMP conversion finished.
Note2: ACMP interrupt will wake CPU up in power-down mode.
1
1
read-write
0
ACMP interrupt function Disabled
#0
1
ACMP interrupt function Enabled
#1
CPNSEL
Comparator Negative Input Select\n
24
2
read-write
0
ACMP0_N (PB.4)
#00
1
Band_Gap
#01
2
CRV
#10
3
Reserved
#11
CPPSEL
Comparator Positive Input Select\n
28
3
read-write
0
ACMP0_P0 (PB.0)
#000
1
ACMP0_P1 (PB.1)
#001
2
ACMP0_P2 (PB.2)
#010
3
ACMP0_P3 (PC.1)
#011
4
PGA_CMP
#100
DLYTRGEN
Analog Comparator Delay Trigger Mode Enable\n
12
1
read-write
0
Disable
#0
1
Enable
#1
DLYTRGIE
Analog Comparator Delay Trigger Mode Interrupt Enable\n
13
1
read-write
0
Disable
#0
1
Enable
#1
DLYTRGSEL
Analog Comparator Delay Trigger Mode Trigger Level Selection\n
8
2
read-write
0
Disable
#00
1
Rising
#01
2
Falling
#10
3
Rising/Falling
#11
DLYTRGSOR
Analog Comparator Delay Trigger Mode Trigger Source Selection\n
10
2
read-write
0
PWM0
#00
1
PWM2
#01
2
PWM4
#10
3
Reserved
#11
EDGESEL
Interrupt Flag Trigger Edge Detection\n
4
2
read-write
0
Disable
#00
1
Rising
#01
2
Falling
#10
3
Rising/Falling
#11
NFCLKS
Noise Filter Clock Pre-divided Selection\nTo determine the sampling frequency of the Noise Filter clock\n
20
2
read-write
0
PCLK
#00
1
PCLK / 2
#01
2
PCLK / 4
#10
3
PCLK / 16
#11
NFDIS
Disable Comparator Noise Filter\n
23
1
read-write
0
Noise filter Enable
#0
1
Noise filter Disable
#1
PBRKSEL
ACMP to EPWM Brake Selection\n
6
1
read-write
0
ACMP Result direct output
#0
1
ACMP Delay Trigger Result output
#1
POLARITY
Analog Comparator Polarity Control\n
19
1
read-write
0
Analog Comparator normal output
#0
1
Analog Comparator invert output
#1
PRESET
Comparator Result Preset Value\n
31
1
read-write
0
0 for preset value
#0
1
1 for preset value
#1
ACMP1_CTL
ACMP1_CTL
Analog Comparator1 Control Register
0x4
read-write
n
0x0
0x0
ACMPEN
Comparator Enable Bit\nComparator output needs to wait 2 us stable time after CMPEN is set.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
ACMPHYSEN
Comparator1 Hysteresis Enable (Only 20mV)\n
2
2
read-write
0
ACMP1 Hysteresis function Disabled (Default)
#00
1
ACMP1 Hysteresis function at comparator 0 Enabled that the typical range is 20mV
#01
ACMPIE
Comparator Interrupt Enable Bit
Note1: Interrupt is generated if ACMPIE bit is set to 1 after ACMP conversion finished.
Note2: ACMP interrupt will wake CPU up in power-down mode.
1
1
read-write
0
ACMP interrupt function Disabled
#0
1
ACMP interrupt function Enabled
#1
CPNSEL
Comparator Negative Input Select\n
24
2
read-write
0
ACMP1_N (PB.3)
#00
1
Band_Gap
#01
2
CRV
#10
3
Reserved
#11
CPPSEL
Comparator Positive Input Select\n
28
3
read-write
0
ACMP0_P0 (PB.0)
#000
1
ACMP0_P1 (PB.1)
#001
10
ACMP0_P2 (PB.2)
#010
11
ACMP0_P3 (PC.1)
#011
100
PGA_CMP
#100
DLYTRGEN
Analog Comparator Delay Trigger Mode Enable\n
12
1
read-write
0
Disable
#0
1
Enable
#1
DLYTRGIE
Analog Comparator Delay Trigger Mode Interrupt Enable\n
13
1
read-write
0
Disable
#0
1
Enable
#1
DLYTRGSEL
Analog Comparator Delay Trigger Mode Trigger Level Selection\n
8
2
read-write
0
Disable
#00
1
Rising
#01
2
Falling
#10
3
Rising/Falling
#11
DLYTRGSOR
Analog Comparator Delay Trigger Mode Trigger Source Selection\n
10
2
read-write
0
PWM0
#00
1
PWM2
#01
2
PWM4
#10
3
Reserved
#11
EDGESEL
Interrupt Flag Trigger Edge Detection\n
4
2
read-write
0
Disable
#00
1
Rising
#01
2
Falling
#10
3
Rising/Falling
#11
NFCLKS
Noise Filter Clock Pre-divided Selection\nTo determine the sampling frequency of the Noise Filter clock\n
20
2
read-write
0
PCLK
#00
1
PCLK / 2
#01
2
PCLK / 4
#10
3
PCLK / 16
#11
NFDIS
Disable Comparator Noise Filter\n
23
1
read-write
0
Noise filter Enable
#0
1
Noise filter Disable
#1
PBRKSEL
ACMP to EPWM Brake Selection\n
6
1
read-write
0
ACMP Result direct output
#0
1
ACMP Delay Trigger Result output
#1
POLARITY
Analog Comparator Polarity Control\n
19
1
read-write
0
Analog Comparator normal output
#0
1
Analog Comparator invert output
#1
PRESET
Comparator Result Preset Value\n
31
1
read-write
0
0 for preset value
#0
1
1 for preset value
#1
STATUS
ACMP_STATUS
Analog Comparator Status Register
0x8
read-write
n
0x0
0x0
ACMPF0
Comparator0 Flag
This bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if ACMPIE set.
Write 1 to clear this bit to zero.
0
1
read-write
ACMPF1
Comparator1 Flag
This bit is set by hardware whenever the comparator1 output changes state. This will cause an interrupt if ACMPIE set.
Write 1 to clear this bit to zero.
1
1
read-write
ACMPO0
Comparator0 Output\n
2
1
read-write
ACMPO1
Comparator1 Output\n
3
1
read-write
DLYTRGF0
Comparator0 Flag
This bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if DLYTRGIEN set.
Write 1 to clear this bit to zero.
4
1
read-write
DLYTRGF1
Comparator1 Flag
This bit is set by hardware whenever the comparator1 output changes state. This will cause an interrupt if DLYTRGIEN set.
Write 1 to clear this bit to zero.
5
1
read-write
DLYTRGO0
Analog Comparator0 Delay Trigger Mode Comparator Output\n
6
1
read-write
DLYTRGO1
Analog Comparator1 Delay Trigger Mode Comparator Output\n
7
1
read-write
TRGDLY
ACMP_TRGDLY
Analog Comparator Delay Trigger Mode Dleay Register
0x10
read-write
n
0x0
0x0
DELAY
Analog Comparator Delay Trigger Mode Dleay cycle
0
9
read-write
VREF
ACMP_VREF
Analog Comparator Reference Voltage Control Register
0xC
read-write
n
0x0
0x0
CRVCTL
Comparator Reference Voltage Setting\n
0
4
read-write
ADC
ADC Register Map
ADC
0x0
0x0
0x8
registers
n
0x20
0x1C
registers
n
CTL
ADC_CTL
ADC Control Register
0x20
read-write
n
0x0
0x0
ADC0CHSEL
ADC1 Channel Select
16
3
read-write
0
ADC0_CH0
#000
1
ADC0_CH1
#001
2
ADC0_CH2
#010
3
ADC0_CH3
#011
4
ADC0_CH4
#100
5
PGA_ADC
#101
6
BAND_GAP
#110
7
VSS
#111
ADC0HWTRGEN
Hardware Trigger ADC Convertion Enable\nEnable or disable triggering of A/D conversion by Hardware (PWM, Timer, ADC self)\n
2
1
read-write
0
Disabled
#0
1
Enabled
#1
ADC0IEN
ADC0 Interrupt Enable
A/D conversion end interrupt request is generated if ADC0IEN bit is set to 1 .
1
1
read-write
0
ADC0 interrupt function Disabled
#0
1
ADC0 interrupt function Enabled
#1
ADC0SEQSEL
ADC0 Sequential Input Pin Selection\n
20
3
read-write
0
ADC0_CH0
#000
1
ADC0_CH1
#001
2
ADC0_CH2
#010
3
ADC0_CH3
#011
4
ADC0_CH4
#100
5
PGA_ADC
#101
6
BAND_GAP
#110
7
VSS
#111
ADC0SWTRG
ADC0 Conversion Start
ADC0SWTRG bit can be set to 1 from two sources: software and external pin STADC.
ADC0SWTRG will be cleared to 0 by hardware automatically.
3
1
read-write
0
Conversion stopped and A/D converter entered idle state
#0
1
Conversion start
#1
ADC1CHSEL
ADC1 Channel Select
24
3
read-write
0
ADC1_CH0
#000
1
ADC1_CH1
#001
2
ADC1_CH2
#010
3
ADC0_CH0
#011
4
ADC0_CH4
#100
5
PGA_ADC
#101
6
Temp Sensor
#110
7
VSS
#111
ADC1HWTRGEN
Hardware Trigger ADC Convertion Enable Bit\nEnable or disable triggering of A/D conversion by Hardware (PWM, Timer, ADC self)\n
10
1
read-write
0
Hardware Trigger ADC Convertion Disabled
#0
1
Hardware Trigger ADC Convertion Enabled
#1
ADC1IEN
ADC1 Interrupt Enable Bit
A/D conversion end interrupt request is generated if ADC1IEN bit is set to 1 .
9
1
read-write
0
ADC1 interrupt function Disabled
#0
1
ADC1 interrupt function Enabled
#1
ADC1SEQSEL
ADC1 Sequential Input Pin Selection (Second Input)\n
28
3
read-write
0
ADC1_CH0
#000
1
ADC1_CH1
#001
2
ADC1_CH2
#010
3
ADC0_CH0
#011
4
ADC0_CH4
#100
5
PGA_ADC
#101
6
Temp Sensor
#110
7
VSS
#111
ADC1SWTRG
ADC1 Conversion Start
ADC1SWTRG bit can be set to 1 from two sources: software and external pin STADC.
ADC1SWTRG will be cleared to 0 by hardware automatically.
11
1
read-write
0
Conversion stopped and A/D converter entered idle state
#0
1
Conversion start
#1
ADCEN
ADC Converter Enable
Before starting the A/D conversion function, this bit should be set to 1 .
Clear it to 0 to disable A/D converter analog circuit power consumption.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
ADCMODE
ADC Conversion Mode\n
6
2
read-write
0
Independent simple independent function and independent interrupt by themselves
#00
1
Independent 2SH independent trigger function, ADC0 with ADC1 both convert finish then only generate interrupt ADC0IF
#01
2
Simultaneous Simple simultaneous trigger function by ADC0, ADC0 with ADC1 both convert finish then generate interrupt ADC0IF
#10
3
Simultaneous Sequential simultaneous trigger function by ADC0, this mode converts sequential is ADC0 - ADC1 - ADC0 - ADC1 4 times, then generate interrupt ADC0IF
#11
ADCSS3R
None
5
1
read-write
0
convert sequential is ADC0 - ADC1 - ADC0 - ADC1, four datas at ADCMODE=11
#0
1
convert sequential is ADC0 - ADC1 - ADC0, three datas at ADCMODE=11
#1
DAT0
ADC_DAT0
ADC data register 0
0x0
read-only
n
0x0
0x0
ADC0DAT0
ADC0 Conversion Result\nThis field contains conversion result of ADC.
0
12
read-only
ADC0OV
ADC0 over Run Flag
If converted data in ADC0DAT0[11:0] has not been read before
the new conversion result is loaded to this register, OV is set to 1 .
It is cleared by hardware after the ADC_DAT0 register is read.
14
1
read-only
0
Data in ADC0DAT0[11:0] is recent conversion result
#0
1
Data in ADC0DAT0[11:0] overwritten
#1
ADC0VALID
ADC0 Valid Flag
This bit is set to 1 when ADC conversion is completed
and cleared by hardware after the ADC_DAT0 register is read.
15
1
read-only
0
Data in ADC0DAT0[11:0] bits not valid
#0
1
Data in ADC0DAT0[11:0] bits valid
#1
ADC1DAT0
ADC1 Conversion Result\nThis field contains conversion result of ADC.
16
12
read-only
ADC1OV
ADC1 over Run Flag
If converted data in ADC1DAT0[27:16] has not been read before
the new conversion result is loaded to this register, OV is set to 1 .
It is cleared by hardware after the ADC_DAT0 register is read.
30
1
read-only
0
Data in ADC1DAT0[27:16] is recent conversion result
#0
1
Data in ADC1DAT0[27:16] overwritten
#1
ADC1VALID
ADC1 Valid Flag
This bit is set to 1 when ADC conversion is completed
and cleared by hardware after the ADC_DAT0 register is read.
31
1
read-only
0
Data in ADC1DAT0[27:16] bits not valid
#0
1
Data in ADC1DAT0[27:16] bits valid
#1
DAT1
ADC_DAT1
ADC Data Register 1
0x4
read-only
n
0x0
0x0
ADC0DAT1
ADC0 Conversion Result for FIFO1\nThis field contains conversion result of ADC.
0
12
read-only
ADC0OV
ADC0Over Run Flag
If converted data in ADC0DAT1[11:0] has not been read before
the new conversion result is loaded to this register, OV is set to 1 .
It is cleared by hardware after the ADC_DAT1 register is read.
14
1
read-only
0
Data in ADC0DAT1[11:0] is recent conversion result
#0
1
Data in ADC0DAT1[11:0]] overwritten
#1
ADC0VALID
ADC0 Valid Flag
This bit is set to 1 when ADC conversion is completed
and cleared by hardware after the ADC_DAT1 register is read.
15
1
read-only
0
Data in ADC0DAT1[11:0] bits not valid
#0
1
Data in ADC0DAT1[11:0] bits valid
#1
ADC1DAT1
ADC1 Conversion Result for FIFO1\nThis field contains conversion result of ADC.
16
12
read-only
ADC1OV
ADC1 over Run Flag
If converted data in ADC1DAT1[27:16] has not been read before
the new conversion result is loaded to this register, OV is set to 1 .
It is cleared by hardware after the ADC_DAT1 register is read.
30
1
read-only
0
Data in ADC1DAT1[27:16] is recent conversion result
#0
1
Data in ADC1DAT1[27:16] overwritten
#1
ADC1VALID
ADC1 Valid Flag
This bit is set to 1 when ADC conversion is completed
and cleared by hardware after the ADC_DAT1 register is read.
31
1
read-only
0
Data in ADC1DAT1[27:16] bits not valid
#0
1
Data in ADC1DAT1[27:16] bits valid
#1
SMPCNT
ADC_SMPCNT
ADC Sampling Time Counter Register
0x2C
-1
read-write
n
0x0
0x0
ADCSMPCNT
ADC Sampling Counter\nADC sampling counters are 6 ADC clock is suggestion\n
0
4
read-write
0
1 * ADC Clock
0
1
2 * ADC Clock
1
10
64 * ADC Clock
10
11
128 * ADC Clock
11
12
256 * ADC Clock
12
13
512 * ADC Clock
13
14
1024 * ADC Clock
14
15
1024 * ADC Clock
15
2
3 * ADC Clock
2
3
4 * ADC Clock
3
4
5 * ADC Clock
4
5
6 * ADC Clock
5
6
7 * ADC Clock
6
7
8 * ADC Clock
7
8
16 * ADC Clock
8
9
32 * ADC Clock
9
STATUS
ADC_STATUS
ADC Status Register
0x30
read-write
n
0x0
0x0
ADC0BUSY
BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.
3
1
read-write
0
A/D converter is in idle state
#0
1
A/D converter is busy at conversion
#1
ADC0CH
Current Conversion Channel\nIt is read only.
4
4
read-write
ADC0IF
A/D Conversion End Flag
A status flag that indicates the end of A/D conversion.
ADF is set to 1 When A/D conversion ends.
This flag can be cleared by writing 1 to itself.
0
1
read-write
ADC0OV
Over Run Flag\nIt is a mirror to OV bit in ADDR.
1
1
read-write
ADC1BUSY
BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.
11
1
read-write
0
A/D converter is in idle state
#0
1
A/D converter is busy at conversion
#1
ADC1CH
Current Conversion Channel\nIt is read only.
12
4
read-write
ADC1IF
ADC1 Conversion End Flag
A status flag that indicates the end of A/D conversion.
ADF is set to 1 When A/D conversion ends.
This flag can be cleared by writing 1 to itself.
8
1
read-write
ADC1OV
Over Run Flag\nIt is a mirror to OV bit in ADDR.
9
1
read-write
HIGHFG
Window Comparator High Bund Flag
When ADC conversion result high than the setting condition in High Bund (WCMPHIGHDAT), this bit is set to 1 .
Then it is cleared by writing 1 to ifself.
19
1
read-write
0
Conversion result in ADC_DAT1 does not meets the WCMPHIGHDAT setting
#0
1
Conversion result in ADC_DAT1 meets the WCMPHIGHDAT setting
#1
LOWFG
Window Comparator Low Bund Flag
When ADC conversion result low than the setting condition in Low Bund (WCMPLOWDAT), this bit is set to 1 .
Then it is cleared by writing 1 to ifself.
17
1
read-write
0
Conversion result in ADC_DAT1 does not meets the WCMPLOWDAT setting
#0
1
Conversion result in ADC_DAT1 meets the WCMPLOWDAT setting
#1
MIDFG
Window Comparator Middle Bund Flag
When ADC conversion result is between High Bund (WCMPHIGHDAT) and Low Bund (WCMPLOWDAT), this bit is set to 1 .
Then it is cleared by writing 1 to ifself.
18
1
read-write
0
Conversion result in ADC_DAT1 isn't between High Bund (WCMPHIGHDAT) and Low Bund (WCMPLOWDAT)
#0
1
Conversion result in ADC_DAT1 is between High Bund (WCMPHIGHDAT) and Low Bund (WCMPLOWDAT)
#1
WCMPIF
Window Comparator Interrupt Flag
When Windows Comparator has generat a result output, this bit is set to 1 .
Then it is cleared by writing 1 to ifself.
16
1
read-write
0
Conversion result in ADC_DAT1 does not meets the WCMPLOWDAT setting
#0
1
Conversion result in ADC_DAT1 meets the WCMPLOWDAT setting
#1
TRGDLY
ADC_TRGDLY
ADC Trigger Delay Control Register
0x28
read-write
n
0x0
0x0
ADC0DELAY
ADC0 Trigger Delay Timer
Set this field will delay ADC start conversion time after ADCxTRGCTL trigger is coming. (x:0/1)
delay time is (4 * ADC0DELAY) * system clock
0
8
read-write
ADC1DELAY
ADC1 Trigger Delay Timer
Set this field will delay ADC start conversion time after ADCxTRGCTL trigger is coming. (x:0/1)
delay time is (4 * ADC1DELAY) * system clock
16
8
read-write
TRGSOR
ADC_TRGSOR
ADC Hardware Trigger Source Control Register
0x24
read-write
n
0x0
0x0
ADC0PWMTRGSEL
PWM Trigger Selection for ADC0\n
4
2
read-write
0
EPWM Signal Falling
#00
1
EPWM Counter Central
#01
2
EPWM signal Rising
#10
3
Period
#11
ADC0STADCSEL
ADC0 External Trigger Pin (STADC) Trigger Selection\n
6
2
read-write
0
Rising
#00
1
Falling
#01
2
Rising or Falling
#10
3
Reserved
#11
ADC0TRGSOR
ADC0 Trigger Source \n
0
4
read-write
0
STADC
#0000
1
PWM0
#0001
2
PWM1
#0010
3
PWM2
#0011
4
PWM3
#0100
5
PWM4
#0101
6
PWM5
#0110
7
TMR0
#0111
8
TMR1
#1000
9
TMR2
#1001
10
ADC0IF
#1010
11
ADC1IF
#1011
ADC1PWMTRGSEL
PWM Trigger Selection for ADC1\n
20
2
read-write
0
EPWM Signal Falling
#00
1
EPWM Counter Central
#01
2
EPWM signal Rising
#10
3
Period
#11
ADC1STADCSEL
ADC1 External Trigger Pin (STADC) Trigger Selection\n
22
2
read-write
0
Rising
#00
1
Falling
#01
2
Rising or Falling
#10
3
Reserved
#11
ADC1TRGSOR
ADC1 Trigger Source \n
16
4
read-write
0
STADC
#0000
1
PWM0
#0001
2
PWM1
#0010
3
PWM2
#0011
4
PWM3
#0100
5
PWM4
#0101
6
PWM5
#0110
7
TMR0
#0111
8
TMR1
#1000
9
TMR2
#1001
10
ADC0IF
#1010
11
ADC1IF
#1011
WCMPCTL
ADC_WCMPCTL
ADC Window Comparator Control Register
0x34
read-write
n
0x0
0x0
WCMPEN
Window Comparator Enable Bit\n
0
1
read-write
0
Disable
#0
1
Enable
#1
WCMPHIGHEN
Window Comparator High Flag Enable Bit\nset ADC conversion result high than compare condition High bund range\n
6
1
read-write
0
Disable
#0
1
Enable
#1
WCMPIEN
Window Comparator Interrupt Enable Bit\n
1
1
read-write
0
Disable
#0
1
Enable
#1
WCMPLOWEN
Window Comparator Low Flag Enable Bit\nset ADC conversion result low than compare condition Low bund range\n
4
1
read-write
0
Disable
#0
1
Enable
#1
WCMPMCNT
Window Compare Match Count\nWhen the ADC conversion result matches the compare condition\n defined by CMP Flag setting (CMPUPEN, CMPEQUEN, CMPLOWEN and WCFLAGCTL), the internal match counter will increase 1. \nWhen the internal counter reaches the value to (WCMPMCNT ), the CMPIF bit will be set.\n
8
4
read-write
WCMPMIDEN
Window Comparator Middle Flag Enable Bit\nset ADC conversion result equal compare condition at Low and High bund range\n
5
1
read-write
0
Disable
#0
1
Enable
#1
WFLAGCTL
Window Comparator Flag Control\nWhen the ADC conversion result matches the compare condition\n
7
1
read-write
0
auto-update
#0
1
none
#1
WCMPDAT
ADC_WCMPDAT
ADC Window Comparator Data Register
0x38
read-write
n
0x0
0x0
WCMPHIGHDAT
Window Comparator High Bund Data
16
12
read-write
WCMPLOWDAT
Window Comparator Low Bund Data
0
12
read-write
BPWM
BPWM Register Map
BPWM
0x0
0x0
0x24
registers
n
0x40
0x8
registers
n
0x50
0x4
registers
n
0x58
0x10
registers
n
0x78
0x8
registers
n
CAPCTL
BPWM_CAPCTL
Basic PWM Capture Control Register
0x50
read-write
n
0x0
0x0
CAPCH0EN
Channel 0 Capture Function Enable Bit\nWhen Enabled, Capture latched the BPWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable BPWM channel 0 Interrupt.
3
1
read-write
0
Capture function on BPWM channel 0 Disabled
#0
1
Capture function on BPWM channel 0 Enabled
#1
CAPCH1EN
Channel 1 Capture Function Enable Bit\nWhen Enabled, Capture latched the BPWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM channel 1 Interrupt.
19
1
read-write
0
Capture function on BPWM channel 1 Disabled
#0
1
Capture function on BPWM channel 1 Enabled
#1
CAPIF0
Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
4
1
read-write
CAPIF1
Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
20
1
read-write
CFLRI0
BPWM_CAPDRL0 Latched Indicator Bit\nWhen BPWM input channel 0 has a falling transition, BPWM_CAPDRL0 was latched with the value of BPWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to0.
7
1
read-write
CFLRI1
CFLR1 Latched Indicator Bit\nWhen BPWM input channel 1 has a falling transition, CFLR1 was latched with the value of BPWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to 0
23
1
read-write
CFL_IE0
Channel 0 Falling Latch Interrupt Enable BIt\nWhen Enabled, if Capture detects BPWM channel 0 has falling transition, Capture will issue an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE1
Channel 1 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects BPWM channel 1 has falling transition, Capture will issue an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI0
BPWM_CAPDRL0Latched Indicator Bit\nWhen BPWM input channel 0 has a rising transition, BPWM_CAPDRL0 was latched with the value of BPWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to 0.
6
1
read-write
CRLRI1
CRLR1 Latched Indicator Bit\nWhen BPWM input channel 1 has a rising transition, CRLR1 was latched with the value of BPWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to0.
22
1
read-write
CRL_IE0
Channel 0 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects BPWM channel 0 has rising transition, Capture will issue an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE1
Channel 1 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects BPWM channel 1 has rising transition, Capture will issue an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV0
Channel 0 Inverter Enable Bit\n
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV1
Channel 1 Inverter Enable Bit\n
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CAPDFL0
BPWM_CAPDFL0
Basic PWM Capture Falling Latch Register (Channel 0)
0x5C
read-only
n
0x0
0x0
CFLR
Capture Falling Latch Register\nLatch the BPWM counter when Channel 0/1 has Falling transition.
0
16
read-only
CAPDFL1
BPWM_CAPDFL1
0x64
read-write
n
0x0
0x0
CAPDRL0
BPWM_CAPDRL0
Basic PWM Capture Rising Latch Register (Channel 0)
0x58
read-only
n
0x0
0x0
CRLR
Capture Rising Latch Register\nLatch the BPWM counter when Channel 0/1 has rising transition.
0
16
read-only
CAPDRL1
BPWM_CAPDRL1
0x60
read-write
n
0x0
0x0
CAPEN
BPWM_CAPEN
Basic PWM Capture Input Enable Register
0x78
read-write
n
0x0
0x0
CINEN0
Channel 0 Capture Input Enable Bit\n
0
1
read-write
0
BPWM Channel 0 capture input path Disabled. The input of BPWM channel 0 capture function is always regarded as 0
#0
1
BPWM Channel 0 capture input path Enabled. The input of BPWM channel 0 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM20
#1
CINEN1
Channel 1 Capture Input Enable Bit\n
1
1
read-write
0
BPWM Channel 1 capture input path Disabled. The input of BPWM channel 1 capture function is always regarded as 0
#0
1
BPWM Channel 1 capture input path Enabled. The input of BPWM channel 1 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM21
#1
CLKDIV
BPWM_CLKDIV
Basic PWM Clock Source Divider Select Register
0x4
read-write
n
0x0
0x0
CLKDIV0
PWM Timer 0 Clock Source Divider Selection\nSelect clock source divider for PWM timer 0.\n(Table is the same as CLKDIV1)
0
3
read-write
CLKDIV1
PWM Timer 1 Clock Source Divider Selection\nSelect clock source divider for PWM timer 1.\n
4
3
read-write
0
1/2
#000
1
1/4
#001
2
1/8
#010
3
1/16
#011
4
1
#100
CLKPSC
BPWM_CLKPSC
Basic PWM Pre-scalar Register
0x0
read-write
n
0x0
0x0
CP01
Clock Prescaler\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer\n
0
8
read-write
DZI01
Dead-zone Interval for Pair of Channel 0 and Channel 1\nThese 8-bit determine the Dead-zone length.\n
16
8
read-write
CMPDAT0
BPWM_CMPDAT0
Basic PWM Comparator Register 0
0x10
read-write
n
0x0
0x0
CMP
PWM Comparator Register\nCMP determines the PWM duty.\nNote: Any write to PERIOD will take effect in next PWM cycle.
0
16
read-write
CMPDAT1
BPWM_CMPDAT1
0x1C
read-write
n
0x0
0x0
CTL
BPWM_CTL
Basic PWM Control Register
0x8
read-write
n
0x0
0x0
CH0EN
PWM-timer 0 Enable Bit\n
0
1
read-write
0
The corresponding PWM-Timer stops running
#0
1
The corresponding PWM-Timer starts running
#1
CH0INV
PWM-timer 0 Output Inverter Enable Bit\n
2
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH0MOD
PWM-timer 0 Auto-reload/One-shot Mode\nNote: If there is a transition at this bit, it will cause PWM_PERIOD0 and CMP0 be cleared.
3
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH0PINV
PWM-timer 0 Output Polar Inverse Enable Bit\n
1
1
read-write
0
PWM0 output polar inverse Disabled
#0
1
PWM0 output polar inverse Enabled
#1
CH1EN
PWM-timer 1 Enable Bit\n
8
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH1INV
PWM-timer 1 Output Inverter Enable\n
10
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH1MOD
PWM-timer 1 Auto-reload/One-shot Mode\nNote: If there is a transition at this bit, it will cause PERIOD1 and CMP1 be cleared.
11
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH1PINV
PWM-timer 1 Output Polar Inverse Enable Bit\n
9
1
read-write
0
PWM1 output polar inverse Disabled
#0
1
PWM1 output polar inverse Enabled
#1
DZEN01
Dead-zone 0 Generator Enable Bit\nNote: When Dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair.
4
1
read-write
0
Dead-zone 0 Generato Disabled
#0
1
Dead-zone 0 Generato Enabled
#1
PWM01TYPE
PWM01 Aligned Type Selection Bit \n
30
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
DAT0
BPWM_DAT0
Basic PWM Data Register 0
0x14
read-only
n
0x0
0x0
PDR
PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter.
0
16
read-only
DAT1
BPWM_DAT1
0x20
read-write
n
0x0
0x0
INTEN
BPWM_INTEN
Basic PWM Interrupt Enable Register
0x40
read-write
n
0x0
0x0
BPWMDIE0
BPWM Channel 0 Duty Interrupt Enable Bit\n
8
1
read-write
0
BPWM Channel 0 Duty Interrupt Disabled
#0
1
BPWM Channel 0 Duty Interrupt Enabled
#1
BPWMDIE1
BPWM Channel 1 Duty Interrupt Enable Bit\n
9
1
read-write
0
BPWM Channel 1 Duty Interrupt Disabled
#0
1
BPWM Channel 1 Duty Interrupt Enabled
#1
BPWMPIE0
BPWM Channel 0 Period Interrupt Enable Bit \n
0
1
read-write
0
BPWM Channel 0 Period Interrupt Disabled
#0
1
BPWM Channel 0 Period Interrupt Enabled
#1
BPWMPIE1
BPWM Channel 1 Period Interrupt Enable Bit\n
1
1
read-write
0
BPWM Channel 1 Period Interrupt Disabled
#0
1
BPWM Channel 1 Period Interrupt Enabled
#1
INTTYPE
BPWM Interrupt Period Type Selection Bit\nNote: This bit is effective when BPWM in Center-aligned type only.
16
1
read-write
0
BPWMIFn will be set if BPWM counter underflow
#0
1
BPWMIFn will be set if BPWM counter matches PERIODn register
#1
INTSTS
BPWM_INTSTS
Basic PWM Interrupt Indication Register
0x44
read-write
n
0x0
0x0
BPWMDIF0
BPWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 BPWM counter down count and reaches CMP0, software can clear this bit by writing a one to it.\nNote: If CMP equal to PERIOD, this flag is not working in Edge-aligned type selection
8
1
read-write
BPWMDIF1
BPWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 BPWM counter down count and reaches CMP1, software can clear this bit by writing a one to it.\nNote: If CMP equal to PERIOD, this flag is not working in Edge-aligned type selection
9
1
read-write
BPWMPIF0
BPWM Channel 0 Period Interrupt Status\nThis bit is set by hardware when BPWM0 counter reaches the requirement of interrupt (depend on INTTYPE bit of PWM_INTEN register), software can write 1 to clear this bit to 0.
0
1
read-write
BPWMPIF1
BPWM Channel 1 Period Interrupt Status\nThis bit is set by hardware when BPWM1 counter reaches the requirement of interrupt (depend on INTTYPE bit of PWM_INTEN register), software can write 1 to clear this bit to 0.
1
1
read-write
PERIOD0
BPWM_PERIOD0
Basic PWM Period Counter Register 0
0xC
read-write
n
0x0
0x0
PERIOD
Basic PWM Period Counter Register\nPERIOD data determines the PWM period.\nNote: Any write to PERIOD will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type, PERIOD value should be set between 0x0000 to 0xFFFE. If PERIOD equal to 0xFFFF, the PWM will work unpredictable.\nNote: When PERIOD value is set to 0, PWM output is always high.
0
16
read-write
PERIOD1
BPWM_PERIOD1
0x18
read-write
n
0x0
0x0
POEN
BPWM_POEN
Basic PWM Output Enable
0x7C
read-write
n
0x0
0x0
POE0
Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to BPWM function
0
1
read-write
0
BPWM channel 0 output to pin Disabled
#0
1
BPWM channel 0 output to pin Enabled
#1
POE1
Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to BPWM function
1
1
read-write
0
BPWM channel 1 output to pin Disabled
#0
1
BPWM channel 1 output to pin Enabled
#1
CLK
CLK Register Map
CLK
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x4
registers
n
0x50
0x4
registers
n
0x60
0x4
registers
n
AHBCLK
CLK_AHBCLK
AHB Devices Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
HDIVCKEN
Hardware Divider Controller Clock Enable Bit \n
4
1
read-write
0
HDIV peripheral clock Disabled
#0
1
HDIV peripheral clock Enabled
#1
ISPCKEN
Flash ISP Controller Clock Enable Bit\n
2
1
read-write
0
Flash ISP peripheral clock Disabled
#0
1
Flash ISP peripheral clock Enabled
#1
APBCLK
CLK_APBCLK
APB Devices Clock Enable Control Register
0x8
-1
read-write
n
0x0
0x0
ACMPCKEN
Analog Comparator Clock Enable Bit\n
30
1
read-write
0
Analog comparator clock Disabled
#0
1
Analog comparator clock Enabled
#1
ADCCKEN
Analog-digital-converter (ADC) Clock Enable Bit\n
28
1
read-write
0
ADC clock Disabled
#0
1
ADC clock Enabled
#1
BPWMCKEN
Basic PWM Channel 0/1 Clock Enable Bit\n
23
1
read-write
0
BBPWM channel 0/1 clock Disabled
#0
1
BPWM channel 0/1 clock Enabled
#1
CLKOCKEN
CLKO Clock Enable Bit\n
6
1
read-write
0
CLKO clock Disabled
#0
1
CLKO clock Enabled
#1
ECAPCKEN
Input Capture Clock Enable Bit\n
8
1
read-write
0
CAP clock Disabled
#0
1
CAP clock Enabled
#1
EPWMCKEN
Enhanced PWM Clock Enable Bit\n
20
1
read-write
0
EPWM channel 0/1 clock Disabled
#0
1
EPWM channel 0/1 clock Enabled
#1
PGACKEN
PGA Clock Enable Bit\n
12
1
read-write
0
PGA clock Disabled
#0
1
PGA clock Enabled
#1
TMR0CKEN
Timer0 Clock Enable Bit\n
2
1
read-write
0
Timer0 clock Disabled
#0
1
Timer0 clock Enabled
#1
TMR1CKEN
Timer1 Clock Enable Bit\n
3
1
read-write
0
Timer1 clock Disabled
#0
1
Timer1 clock Enabled
#1
USCI0CKEN
USCI0 Clock Enable Bit\n
24
1
read-write
0
USCI0 clock Disabled
#0
1
USCI0 clock Enabled
#1
USCI1CKEN
USCI1 Clock Enable Bit\n
25
1
read-write
0
USCI1 clock Disabled
#0
1
USCI1 clock Enabled
#1
WDTCKEN
Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
Watchdog timer clock Disabled
#0
1
Watchdog timer clock Enabled
#1
CLKDIV
CLK_CLKDIV
Clock Divider Number Register
0x20
read-write
n
0x0
0x0
ADCDIV
ADC Clock Divide Number From ADC Clock Source\n
16
8
read-write
HCLKDIV
HCLK Clock Divide Number From HCLK Clock Source\n
0
4
read-write
CLKOCTL
CLK_CLKOCTL
Clock Output Control Register
0x60
read-write
n
0x0
0x0
CLKOEN
Clock Output Enable Bit\n
4
1
read-write
0
Clock Output function Disabled
#0
1
Clock Output function Enabled
#1
DIV1EN
Clock Output Divide One Enable Bit\n
5
1
read-write
0
Clock Output will output clock with source frequency divided by FREQSEL
#0
1
Clock Output will output clock with source frequency
#1
FREQSEL
Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0].
0
4
read-write
CLKSEL0
CLK_CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLKSEL
HCLK Clock Source Selection (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turned on.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
2
read-write
0
Clock source from HXT/LXT
#00
1
Clock source from LIRC
#01
3
Clock source from HIRC
#11
STCLKSEL
Cortex-M0 SysTick Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
3
2
read-write
0
Clock source from HXT/LXT
#00
1
Clock source from (HXT or LXT)/2
#01
2
Clock source from HCLK/2
#10
3
Clock source from HIRC/2
#11
CLKSEL1
CLK_CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
ADCSEL
ADC Peripheral Clock Source Selection\n
4
2
read-write
0
Clock source from external crystal oscillator (HXT or LXT)
#00
1
Reserved
#01
2
Clock source is from HCLK
#10
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#11
CLKOSEL
Clock Divider Clock Source Selection\n
30
2
read-write
0
Clock source from external crystal oscillator (HXT or LXT)
#00
1
Reserved
#01
2
Clock source from HCLK
#10
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#11
TMR0SEL
TIMER0 Clock Source Selection\n
8
3
read-write
0
Clock source from external crystal oscillator (HXT or LXT)
#000
1
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
#001
2
Clock source from HCLK
#010
3
Clock source from external clock T0 pin
#011
7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#111
TMR1SEL
TIMER1 Clock Source Selection\n
12
3
read-write
0
Clock source from external crystal oscillator (HXT or LXT)
#000
1
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
#001
2
Clock source from HCLK
#010
3
Clock source from external clock T1 pin
#011
7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#111
WDTSEL
Watchdog Timer Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
2
read-write
0
Clock source from external crystal oscillator (HXT or LXT)
#00
1
Reserved
#01
2
Clock source from HCLK0/2048
#10
3
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
#11
PWRCTL
CLK_PWRCTL
System Power-down Control Register
0x0
-1
read-write
n
0x0
0x0
HIRCEN
HIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
48 MHz internal high speed RC oscillator (HIRC) Disabled
#0
1
48 MHz internal high speed RC oscillator (HIRC) Enabled
#1
HXTGAIN
HXT Gain Control Bit (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nGain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. \nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
10
2
read-write
0
HXT frequency is lower than from 8 MHz
#00
1
HXT frequency is from 8 MHz to 12 MHz
#01
2
HXT frequency is from 12 MHz to 16 MHz
#10
3
HXT frequency is higher than 16 MHz
#11
LIRCEN
LIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
3
1
read-write
0
10 kHz internal low speed RC oscillator (LIRC) Disabled
#0
1
10 kHz internal low speed RC oscillator (LIRC) Enabled
#1
PDEN
System Power-down Enable Bit (Write Protect)
When this bit is set to 1, Power-down mode is enabled.
When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.
In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.
In Power-down mode, the system clocks are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
Chip operating normally or chip in idle mode because of WFI/WFE command
#0
1
Chip enters Power-down mode when CPU sleep command WFI/WFE
#1
PDLXT
LXT Alive in Power-down\n
9
1
read-write
0
LXT will be turned off automatically when chip enters Power-down
#0
1
If XTLEN[1:0] are 0x2, LXT keeps active in Power-down
#1
PDWKDLY
Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 48 MHz internal high speed RC oscillator (HIRC).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
Clock cycles delay Disabled
#0
1
Clock cycles delay Enabled
#1
PDWKIEN
Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PDWKIF and PDWKIEN are high.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
Power-down mode wake-up interrupt Disabled
#0
1
Power-down mode wake-up interrupt Enabled
#1
PDWKIF
Power-down Mode Wake-up Interrupt Status
Set by Power-down wake-up event , it indicates that resume from Power-down mode
The flag is set if the GPIO, USCI01, WDT, ACMP01, BOD, TMR01 wake-up occurred.
Note1: Write 1 to clear the bit to 0.
Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
6
1
read-write
XTLEN
XTL Enable Bit (Write Protect)
These two bits are default set to 00 and the XT_IN and XT_OUT pins are GPIO.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
2
read-write
0
XT_IN and XT_OUT are GPIO, disable both LXT HXT (default)
#00
1
HXT Enabled
#01
2
LXT Enabled
#10
3
XT_IN is external clock input pin, XT_OUT is GPIO
#11
STATUS
CLK_STATUS
Clock Status Monitor Register
0x50
read-only
n
0x0
0x0
CLKSFAIL
Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote: Write 1 to clear the bit to 0.
7
1
read-only
0
Clock switching success
#0
1
Clock switching failure
#1
HIRCSTB
HIRC Clock Source Stable Flag (Read Only)\n
4
1
read-only
0
48 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled
#0
1
48 MHz internal high speed RC oscillator (HIRC) clock is stabe and enabled
#1
LIRCSTB
LIRC Clock Source Stable Flag (Read Only)\n
3
1
read-only
0
10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled
#0
1
10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled
#1
XTLSTB
XTL Clock Source Stable Flag (Read Only)\n
0
1
read-only
0
External crystal oscillator (HXT or LXT) clock is not stable or disabled
#0
1
External crystal oscillator (HXT or LXT) clock is stable and enabled
#1
ECAP
ECAP Register Map
ECAP
0x0
0x0
0x20
registers
n
CNT
ECAP_CNT
Input Capture Counter
0x0
read-write
n
0x0
0x0
CNT
Input Capture Timer/Counter (24-bit Up Counter)\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider output which the CAP_CLK is divided by 1, 4, 16, 32, 64, 96, 112 or 128.
0
24
read-write
CNTCMP
ECAP_CNTCMP
Input Capture Counter Compare Register
0x10
read-write
n
0x0
0x0
CNTCMP
Input Capture Counter Compare Register\n
0
24
read-write
CTL0
ECAP_CTL0
Input Capture Control Register 0
0x14
read-write
n
0x0
0x0
CAP0SEL
CAP0 Input Source Selection Bit\n
8
2
read-write
0
CAP0 input is from port pin ECAP_P0
#00
1
CAP0 input is from signal ACMP0_O (Analog comparator 0 output)
#01
2
CAP0 input is from signal ACMP1_O (Analog comparator 1 output)
#10
3
CAP0 input is from signal ADC_CPR (ADC compare output)
#11
CAP1SEL
CAP1 Input Source Selection Bit\n
10
2
read-write
0
CAP1 input is from port pin ECAP_P1
#00
1
CAP1 input is from signal ACMP0_O (Analog comparator 0 output)
#01
2
CAP1 input is from signal ACMP1_O (Analog comparator 1 output)
#10
3
CAP1 input is from signal ADC_CPR (ADC compare output)
#11
CAP2SEL
CAP2 Input Source Selection Bit\n
12
2
read-write
0
CAP2 input is from port pin ECAP_P2
#00
1
CAP2 input is from signal ACMP0_O (Analog comparator 0 output)
#01
2
CAP2 input is from signal ACMP1_O (Analog comparator 1 output)
#10
3
CAP2 input is from signal ADC_CPR (ADC compare output)
#11
CAPCMPIEN
Enable CAPCMPF Trigger Input Capture Interrupt\n
21
1
read-write
0
Disabling flag CAPCMPF can trigger Input Capture interrupt
#0
1
Enabling flag CAPCMPF can trigger Input Capture interrupt
#1
CAPEN
Input Capture Timer/Counter Enable Bit\n
29
1
read-write
0
Input Capture function Disabled
#0
1
Input Capture function Enabled
#1
CAPNFDIS
Disable Input Capture Noise Filter\n
3
1
read-write
0
Noise filter of Input Capture Enabled
#0
1
The noise filter of Input Capture Disabled
#1
CAPOVIEN
Enable CAPOVF Trigger Input Capture Interrupt\n
20
1
read-write
0
Disabling flag CAPOVF can trigger Input Capture interrupt
#0
1
Enabling flag CAPOVF can trigger Input Capture interrupt
#1
CAPPHGEN
Input Capture Flag Trigger PWM Phase Change Function Enable Bit\n
30
1
read-write
0
CAPTF2 or CAPTF1 or CAPTF0 trigger PWM phase change function Disabled
#0
1
CAPTF2 or CAPTF1 or CAPTF0 trigger PWM phase change function Enabled
#1
CAPTF0IEN
Enable Input Capture Channel 0 Interrupt\n
16
1
read-write
0
Disabling flag CAPTF0 can trigger Input Capture interrupt
#0
1
Enabling flag CAPTF0 can trigger Input Capture interrupt
#1
CAPTF1IEN
Enable Input Capture Channel 1 Interrupt\n
17
1
read-write
0
Disabling flag CAPTF1 can trigger Input Capture interrupt
#0
1
Enabling flag CAPTF1 can trigger Input Capture interrupt
#1
CAPTF2IEN
Enable Input Capture Channel 2 Interrupt\n
18
1
read-write
0
Disabling flag CAPTF2 can trigger Input Capture interrupt
#0
1
Enabling flag CAPTF2 can trigger Input Capture interrupt
#1
CMPCLR
Input Capture Counter Clear by Compare-match Control Bit\n
25
1
read-write
0
Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Disabled
#0
1
Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Enabled
#1
CMPEN
The Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.\n
28
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
CPTCLR
Input Capture Counter Clear by Capture Events Control Bit\nIf this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when any one of capture events (CAPTF0~3) occurs.\n
26
1
read-write
0
Capture events (CAPTF0~3) can clear capture counter (ECAP_CNT) Disabled
#0
1
Capture events (CAPTF0~3) can clear capture counter (ECAP_CNT) Enabled
#1
CPTST
Input Capture Counter Start Bit\nSetting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK). \n
24
1
read-write
0
ECAP_CNT stop counting
#0
1
ECAP_CNT starts up-counting
#1
IC0EN
Enable Port Pin IC0 Input to Input Capture Unit\n
4
1
read-write
0
IC0 input to Input Capture Unit Disabled
#0
1
IC0 input to Input Capture Unit Enabled
#1
IC1EN
Enable Port Pin IC1 Input to Input Capture Unit\n
5
1
read-write
0
IC1 input to Input Capture Unit Disabled
#0
1
IC1 input to Input Capture Unit Enabled
#1
IC2EN
Enable Port Pin IC2 Input to Input Capture Unit\n
6
1
read-write
0
IC2 input to Input Capture Unit Disabled
#0
1
IC2 input to Input Capture Unit Enabled
#1
NFCLKS
Noise Filter Clock Pre-divided Selection\nTo determine the sampling frequency of the Noise Filter clock \n
0
2
read-write
0
CAPCLK
#00
1
CAPCLK / 2
#01
2
CAPCLK / 4
#10
3
CAPCLK / 16
#11
RLDEN
The Reload Function Enable Bit\nSetting this bit to enable reload function. If the reload control is enabled, an overflow event (CAPOVF) or capture events (CAPTFx) will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT.\n
27
1
read-write
0
Reload function Disabled
#0
1
Reload function Enabled
#1
CTL1
ECAP_CTL1
Input Capture Control Register 1
0x18
read-write
n
0x0
0x0
CAPDIV
Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with four divided options controlled by CAPDIV[2:0].\n
12
3
read-write
0
CAPCLK / 1
#000
1
CAPCLK / 4
#001
2
CAPCLK / 16
#010
3
CAPCLK / 32
#011
4
CAPCLK / 64
#100
5
CAPCLK / 96
#101
6
CAPCLK / 112
#110
7
CAPCLK / 128
#111
CAPEDG0
Channel 0 Captured Edge Selection\nInput capture can detect falling edge change only, rising edge change only or one of both edge change \n
0
2
read-write
0
Detect rising edge
#00
1
Detect falling edge.\nDetect either rising or falling edge
#01
CAPEDG1
Channel 1 Captured Edge Selection\nInput capture can detect falling edge change only, rising edge change only or one of both edge change \n
2
2
read-write
0
Detect rising edge
#00
1
Detect falling edge.\nDetect either rising or falling edge
#01
CAPEDG2
Channel 2 Captured Edge Selection\nInput capture can detect falling edge change only, rising edge change only or one of both edge change \n
4
2
read-write
0
Detect rising edge
#00
1
Detect falling edge.\nDetect either rising or falling edge
#01
CNTSRC
Capture Timer/Counter Clock Source Select\nSelect the capture timer/counter clock source\n
16
2
read-write
0
CAPCLK (Default)
#00
1
CAP0
#01
2
CAP1
#10
3
CAP2
#11
CPRLDS
ECAP_CNT Reload Trigger Source Selection\n
8
3
read-write
0
CAPTF0
#000
1
CAPTF1
#001
2
CAPTF2
#010
4
CAPOVF
#100
HLD0
ECAP_HLD0
Input Capture Counter Hold Register 0
0x4
read-write
n
0x0
0x0
HOLD
Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register. Each input channel has itself holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
0
24
read-write
HLD1
ECAP_HLD1
0x8
read-write
n
0x0
0x0
HLD2
ECAP_HLD2
0xC
read-write
n
0x0
0x0
STS
ECAP_STS
Input Capture Status Register
0x1C
read-write
n
0x0
0x0
CAPCMPF
Input Capture Compare-match Flag\nIf the input capture compare function is enabled, the flag is set by hardware while capture counter (CNT) up counts and reach to the CNTCMP value.\nNote: This bit is only cleared by writing 1 to itself through software.
4
1
read-write
0
CNT does not match with CNTCMP value
#0
1
CNT counts to the same as CNTCMP value
#1
CAPOVF
Input Capture Counter Overflow Flag\nFlag is set by hardware when input capture up counter (CNT) overflows from 0x00FF_FFFF to 0.\nNote: This bit is only cleared by writing 1 to itself through software.
5
1
read-write
0
No overflow occurs in CNT
#0
1
CNT overflows
#1
CAPTF0
Input Capture Channel 0 Captured Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. \nNote: This bit is only cleared by writing 1 to itself through software.
0
1
read-write
0
No valid edge change is detected at CAP0 input
#0
1
A valid edge change is detected at CAP0 input
#1
CAPTF1
Input Capture Channel 1 Captured Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. \nNote: This bit is only cleared by writing 1 to itself through software.
1
1
read-write
0
No valid edge change is detected at CAP1 input
#0
1
A valid edge change is detected at CAP1 input
#1
CAPTF2
Input Capture Channel 2 Captured Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. \nNote: This bit is only cleared by writing 1 to itself through software.
2
1
read-write
0
No valid edge change is detected at CAP2 input
#0
1
A valid edge change is detected at CAP2 input
#1
ECAP0
Input Capture Pin 0 Status\nInput capture pin 0 (ECAP_P0) status. It is read only.
8
1
read-write
ECAP1
Input Capture Pin 1 Status\nInput capture pin 1 (ECAP_P1) status. It is read only.
9
1
read-write
ECAP2
Input Capture Pin 2 Status\nInput capture pin 2 (ECAP_P2) status. It is read only.
10
1
read-write
EPWM
EPWM Register Map
EPWM
0x0
0x0
0x10
registers
n
0x24
0x1C
registers
n
0x54
0x34
registers
n
ADCTCTL0
EPWM_ADCTCTL0
EPWM Trigger ADC Control Register 0
0x68
read-write
n
0x0
0x0
CDTRGEN0
Enable PWM Trigger ADC Function While Channel0's Counter Matching PWM_CMPDAT0in Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CDTRGEN1
Enable PWM Trigger ADC Function While Channel1's Counter Matching CMP1 in Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
8
1
read-write
0
Disabled
#0
1
Enabled
#1
CDTRGEN2
Enable PWM Trigger ADC Function While Channel2's Counter Matching CMP2 in Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
16
1
read-write
0
Disabled
#0
1
Enabled
#1
CDTRGEN3
Enable PWM Trigger ADC Function While Channel3's Counter Matching CMP3 in Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
24
1
read-write
0
Disabled
#0
1
Enabled
#1
CUTRGEN0
Enable PWM Trigger ADC Function While Channel0's Counter Matching PWM_CMPDAT0in Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
CUTRGEN1
Enable PWM Trigger ADC Function While Channel1's Counter Matching CMP1 In Up-count Direction
Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
10
1
read-write
0
Disabled
#0
1
Enabled
#1
CUTRGEN2
Enable PWM Trigger ADC Function While Channel2's Counter Matching CMP2 In Up-count Direction
Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
18
1
read-write
0
Disabled
#0
1
Enabled
#1
CUTRGEN3
Enable PWM Trigger ADC Function While Channel3's Counter Matching CMP3 in Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
26
1
read-write
0
Disabled
#0
1
Enabled
#1
PTRGEN
Enable PWM Trigger ADC Function While Channel0's Counter Matching Period\nNote: This bit is valid for both center aligned mode and edged aligned mode.
3
1
read-write
0
Disabled
#0
1
Enabled
#1
ZPTRGEN
Enable PWM Trigger ADC Function While Channel0's Counter Matching 0 (Zero Point)\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
ADCTCTL1
EPWM_ADCTCTL1
EPWM Trigger ADC Control Register 1
0x6C
read-write
n
0x0
0x0
CDTRGEN4
Enable PWM Trigger ADC Function While Channel4's Counter Matching CMP4 in Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CDTRGEN5
Enable PWM Trigger ADC Function While Channel5's Counter Matching CMP5 in Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
8
1
read-write
0
Disabled
#0
1
Enabled
#1
CUTRGEN4
Enable PWM Trigger ADC Function While Channel4's Counter Matching CMP4 in Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
CUTRGEN5
Enable PWM Trigger ADC Function While Channel5's Counter Matching CMP5 in Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
10
1
read-write
0
Disabled
#0
1
Enabled
#1
ADCTSTS0
EPWM_ADCTSTS0
EPWM Trigger ADC Status Register 0
0x70
read-write
n
0x0
0x0
CDTRGF0
ADC Trigger Flag by Counting Down to CMP\nNote: Software can write 1 to clear this bit.
0
1
read-write
CDTRGF1
ADC Trigger Flag by Counting Down to CMP\nNote: Software can write 1 to clear this bit.
8
1
read-write
CDTRGF2
ADC Trigger Flag by Counting Down to CMP \nNote: Software can write 1 to clear this bit.
16
1
read-write
CDTRGF3
ADC Trigger Flag by Counting Down to CMP\nNote: Software can write 1 to clear this bit.
24
1
read-write
CUTRGF0
ADC Trigger Flag by Counting Up to CMP\nNote: Software can write 1 to clear this bit.
2
1
read-write
CUTRGF1
ADC Trigger Flag by Counting Up to CMP\nNote: Software can write 1 to clear this bit.
10
1
read-write
CUTRGF2
ADC Trigger Flag by Counting Up to CMP\nNote: Software can write 1 to clear this bit.
18
1
read-write
CUTRGF3
ADC Trigger Flag by Counting Up to CMP\nNote: Software can write 1 to clear this bit.
26
1
read-write
PTRGF
ADC Trigger Flag by Period \nNote: Software can write 1 to clear this bit.
3
1
read-write
ZPTRGF
ADC Trigger Flag By Counting to 0 (Zero Point)
Note: Software can write 1 to clear this bit.
1
1
read-write
ADCTSTS1
EPWM_ADCTSTS1
EPWM Trigger ADC Status Register 1
0x74
read-write
n
0x0
0x0
BRKCTL
EPWM_BRKCTL
EPWM Fault Brake Control Register
0x60
read-write
n
0x0
0x0
BK0ADCEN
BRK0 Source From ADC Enable\n
4
1
read-write
0
Disabled
#0
1
Enabled
#1
BK0CMP0EN
BRK0 Source From ACMP0 Enable\n
2
1
read-write
0
Disabled
#0
1
Enabled
#1
BK0CMP1EN
BRK0 Source From ACMP1 Enable\n
3
1
read-write
0
Disabled
#0
1
Enabled
#1
BK0PEN
BRK0 Source From External Pin Enable\n
5
1
read-write
0
Disabled
#0
1
Enabled
#1
BK1ADCEN
BRK1 Source From ADC Enable\n
12
1
read-write
0
Disabled
#0
1
Enabled
#1
BK1CMP0EN
BRK1 Source From ACMP0 Enable\n
10
1
read-write
0
Disabled
#0
1
Enabled
#1
BK1CMP1EN
BRK1 Source From ACMP1 Enable\n
11
1
read-write
0
Disabled
#0
1
Enabled
#1
BK1PEN
BRK1 Source From External Pin Enable\n
13
1
read-write
0
Disabled
#0
1
Enabled
#1
BKOD0
PWM Channel 0 Brake Output Select Register\n
24
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
BKOD1
PWM Channel 1 Brake Output Select Register\n
25
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
BKOD2
PWM Channel 2 Brake Output Select Register\n
26
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
BKOD3
PWM Channel 3 Brake Output Select Register\n
27
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
BKOD4
PWM Channel 4 Brake Output Select Register\n
28
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
BKOD5
PWM Channel 5 Brake Output Select Register\n
29
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
BRK0EN
Enable BKP0 Pin Trigger Fault Brake Function 0\n
0
1
read-write
0
Disabling BKP1 pin can trigger brake function 1
#0
1
Enabling a falling at BKP1 pin can trigger brake function 1
#1
BRK1EN
Enable BKP1 Pin Trigger Fault Brake Function 1\n
1
1
read-write
0
Disabling BKP1 pin can trigger brake function 1
#0
1
Enabling a falling at BKP1 pin can trigger brake function 1
#1
LVDBKEN
Low-level Detection Trigger PWM Brake Function 1 Enable\n
14
1
read-write
0
Brake Function 1 triggered by Low-level detection Disabled
#0
1
Brake Function 1 triggered by Low-level detection Enabled
#1
LVDTYPE
Low-level Detection Resume Type\n
15
1
read-write
0
Brake resume at BRK resume delay counter counting to 0
#0
1
Brake resume at period edge
#1
NFPEN
Noise Filter for External Brake Input Pin (BRK_I) Enable\n
31
1
read-write
0
Disable
#0
1
Enable
#1
SWBRK
Software Break\n
9
1
read-write
0
disable Software break and back to normal PWM function
#0
1
issue Software break
#1
CLKDIV
EPWM_CLKDIV
EPWM Clock Select Register
0x4
read-write
n
0x0
0x0
CLKDIV
EPWM Clock Divider (9 Step Divider)\nSelect clock input for PWM timer\n
0
4
read-write
0
1 (HCLK / 2^0)
#0000
1
1/2 (HCLK / 2^1)
#0001
2
1/4 (HCLK / 2^2)
#0010
3
1/8 (HCLK / 2^3)
#0011
4
1/16 (HCLK / 2^4)
#0100
5
1/32 (HCLK / 2^5)
#0101
6
1/64 (HCLK / 2^6)
#0110
7
1/128 (HCLK / 2^7)
#0111
8
1/256 (HCLK / 2^8)
#1000
CMPDAT0
EPWM_CMPDAT0
EPWM Comparator Register 0
0x24
read-write
n
0x0
0x0
CMP
PWM Comparator Register
CMP determines the PWM Duty.
Edge-aligned mode: where xy, could be 01, 23, 45 depending on the selected PWM channel.
Note: Any write to CMPn will take effect in next PWM cycle.
0
16
read-write
CMPU
PWM Comparator Register for UP Counter in Center-aligned Asymmetric Mode
CMPU PERIOD: @ up counter PWM output is keep to Max. duty.
16
16
read-write
CMPDAT1
EPWM_CMPDAT1
0x28
read-write
n
0x0
0x0
CMPDAT2
EPWM_CMPDAT2
0x2C
read-write
n
0x0
0x0
CMPDAT3
EPWM_CMPDAT3
0x30
read-write
n
0x0
0x0
CMPDAT4
EPWM_CMPDAT4
0x34
read-write
n
0x0
0x0
CMPDAT5
EPWM_CMPDAT5
0x38
read-write
n
0x0
0x0
CNT
EPWM_CNT
EPWM Counter Register
0x3C
read-only
n
0x0
0x0
CNT
PWM Counter Register\nUser can monitor CNT to know the current value in 16-bit down counter.
0
16
read-only
CNTDIR
PWM Counter (Up/Down) Direction\n
31
1
read-only
0
PWM counter is down count
#0
1
PWM counter is up count
#1
CTL
EPWM_CTL
EPWM Control Register
0x8
read-write
n
0x0
0x0
ASYMEN
Asymmetric Mode in Center-aligned Type
20
1
read-write
0
symmetric mode in center-aligned type
#0
1
asymmetric mode in center-aligned type
#1
CNTCLR
Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware.
27
1
read-write
0
Do not clear PWM counter
#0
1
16-bit PWM counter cleared to 0x000
#1
CNTEN0
PWM-timer 0 Enable/Disable Start Run\n
0
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CNTEN1
PWM-timer 1 Enable/Disable Start Run\n
1
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CNTEN2
PWM-timer 2 Enable/Disable Start Run\n
2
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CNTEN3
PWM-timer 3 Enable/Disable Start Run\n
3
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CNTEN4
PWM-timer 4 Enable/Disable Start Run\n
4
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CNTEN5
PWM-timer 5 Enable/Disable Start Run\n
5
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CNTMODE
PWM-timer Auto-reload/One-shot Mode\n
8
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CNTTYPE
PWM Aligned Type Selection Bit\n
31
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
DBGTRIOFF
PWM Debug Mode Configuration Bit (Available in DEBUG Mode Only)\n
23
1
read-write
0
Safe mode: The timer is frozen and PWM outputs are shut down Safe state for the inverter. The timer can still be re-started from where it stops
#0
1
Normal mode: The timer continues to operate normally May be dangerous in some cases since a constant duty cycle is applied to the inverter (no more interrupts serviced)
#1
DTCNT01
Dead-zone 0 Generator Enable/Disable (PWM0 and PWM1 Pair for PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group.
24
1
read-write
0
Dead-zone 0 Generator Disabled
#0
1
Dead-zone 0 Generator Enabled
#1
DTCNT23
Dead-zone 2 Generator Enable/Disable (PWM2 and PWM3 Pair for PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group.
25
1
read-write
0
Dead-zone 2 Generator Disabled
#0
1
Dead-zone 2 Generator Enabled
#1
DTCNT45
Dead-zone 4 Generator Enable/Disable (PWM4 and PWM5 Pair for PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM4 and PWM5 becomes a complementary pair for PWM group.
26
1
read-write
0
Dead-zone 4 Generator Disabled
#0
1
Dead-zone 4 Generator Enabled
#1
GROUPEN
Group Bit\n
30
1
read-write
0
The signals timing of PWM0, PWM2 and PWM4 are independent
#0
1
Unify the signals timing of PWM0, PWM2 and PWM4 in the same phase which is controlled by PWM0
#1
HCUPDT
Half Cycle Update Enable for Center-aligned Type\n
16
2
read-write
0
update PERIOD CMP at pwm_counter = PERIOD (Period)
#00
1
update PERIOD CMP at pwm_counter = 0
#01
2
update PERIOD CMP at half cycle (counter = 0 PERIOD, both update)
#10
3
update PERIOD CMP at pwm_counter = PERIOD (Period)
#11
MODE
PWM Operating Mode Selection\n
28
2
read-write
0
Independent mode
#00
1
Complementary mode
#01
2
Synchronized mode
#10
3
Reserved
#11
DTCTL
EPWM_DTCTL
EPWM Dead-zone Interval Register
0x64
read-write
n
0x0
0x0
DTCNT01
Dead-zone Interval Register for Pair of Channel0 and Channel1 (PWM0 and PWM1 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding PWM_CLKDIV bits.
0
8
read-write
DTCNT23
Dead-zone Interval Register for Pair of Channel2 and Channel3 (PWM2 and PWM3 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding PWM_CLKDIV bits.
8
8
read-write
DTCNT45
Dead-zone Interval Register for Pair of Channel4 and Channel5 (PWM4 and PWM5 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding PWM_CLKDIV bits.
16
8
read-write
IFA
EPWM_IFA
EPWM Period Interrupt Accumulation Control Register
0x84
-1
read-write
n
0x0
0x0
IFACNTDAT
Period Interrupt Down-counter Data Register (Read Only)\nWhen IFAEN is set, IFACNTDAT will decrease when every PWM Interrupt flag is set,\n and when IFACNTDAT reach to zero, the PWM interrupt will occurred and IFACNTVAL will reload to IFACNTDAT.
12
4
read-only
IFACNTVAL
Period Interrupt Accumulation Counter Value Setting Register (Write Only)\n16 step Down-Counter value setting register.\nWhen IFAEN is set, IFACNTVAL value will load into IFACNTDAT and decrase gradually.
4
4
write-only
IFAEN
Enable Period Interrupt Accumulation Function\n
0
1
read-write
0
Period Interrupt Accumulation Disabled
#0
1
Period Interrupt Accumulation Enabled
#1
INTEN
EPWM_INTEN
EPWM Interrupt Enable Register
0x54
read-write
n
0x0
0x0
BRK0IEN
Enable Fault Brake0 Interrupt\n
16
1
read-write
0
Disabling flags BKF0 to trigger PWM interrupt
#0
1
Enabling flags BKF0 can trigger PWM interrupt
#1
BRK1IEN
Enable Fault Brake1 Interrupt\n
17
1
read-write
0
Disabling flags BKF1 to trigger PWM interrupt
#0
1
Enabling flags BKF1 can trigger PWM interrupt
#1
CIEN
PWM Central Interrupt Enable Bit\nfor Center-aligned only \n
18
1
read-write
0
Disable
#0
1
Enabled interrupt when EPWM Central
#1
CMPDIEN0
PWM Channel 0 DOWN Interrupt Enable Bit\nDOWN for Edge-aligned and Center-aligned\n
24
1
read-write
0
Disable
#0
1
Enabled interrupt when EPWM_CH0 PWM DOWN counter reaches CMPDAT0
#1
CMPDIEN1
PWM Channel 1 DOWN Interrupt Enable\nDOWN for Edge-aligned and Center-aligned\n
25
1
read-write
0
Disable
#0
1
Enabled interrupt when EPWM_CH1 PWM DOWN counter reaches CMPDAT1
#1
CMPDIEN2
PWM Channel 2 DOWN Interrupt Enable Bit\nDOWN for Edge-aligned and Center-aligned\n
26
1
read-write
0
Disable
#0
1
Enabled interrupt when EPWM_CH2 PWM DOWN counter reaches CMPDAT2
#1
CMPDIEN3
PWM Channel 3 DOWN Interrupt Enable Bit\nDOWN for Edge-aligned and Center-aligned\n
27
1
read-write
0
Disable
#0
1
Enabled interrupt when EPWM_CH3 PWM DOWN counter reaches CMPDAT3
#1
CMPDIEN4
PWM Channel 4 DOWN Interrupt Enable Bit\nDOWN for Edge-aligned and Center-aligned\n
28
1
read-write
0
Disable
#0
1
Enabled interrupt when EPWM_CH4 PWM DOWN counter reaches CMPDAT4
#1
CMPDIEN5
PWM Channel 5 DOWN Interrupt Enable Bit\nDOWN for Edge-aligned and Center-aligned\n
29
1
read-write
0
Disable
#0
1
Enabled interrupt when EPWM_CH5 PWM DOWN counter reaches CMPDAT5
#1
CMPUIEN0
PWM Channel 0 UP Interrupt Enable\nUP for Center-aligned only\n
8
1
read-write
0
Disable
#0
1
Enabled interrupt when EPWM_CH0 PWM UP counter reaches CMPDAT0
#1
CMPUIEN1
PWM Channel 1 UP Interrupt Enable\nUP for Center-aligned only\n
9
1
read-write
0
Disable
#0
1
Enabled interrupt when EPWM_CH1 PWM UP counter reaches CMPDAT1
#1
CMPUIEN2
PWM Channel 2 UP Interrupt Enable Bit \nUP for Center-aligned only\n
10
1
read-write
0
Disable
#0
1
Enabled interrupt when EPWM_CH2 PWM UP counter reaches CMPDAT2
#1
CMPUIEN3
PWM Channel 3 UP Interrupt Enable\nUP for Center-aligned only\n
11
1
read-write
0
Disable
#0
1
Enabled interrupt when EPWM_CH3 PWM UP counter reaches CMPDAT3
#1
CMPUIEN4
PWM Channel 4 UP Interrupt Enable Bit\nUP for Center-aligned only\n
12
1
read-write
0
Disable
#0
1
Enabled interrupt when EPWM_CH4 PWM UP counter reaches CMPDAT4
#1
CMPUIEN5
PWM Channel 5 UP Interrupt Enable Bit \nUP for Center-aligned only\n
13
1
read-write
0
Disable
#0
1
Enabled interrupt when EPWM_CH5 PWM UP counter reaches CMPDAT5
#1
PIEN
PWM Channel 0 Period Interrupt Enable Bit\nfor Edge-aligned and Center-aligned \n
0
1
read-write
0
Disable
#0
1
Enabled interrupt when EPWM Period
#1
INTSTS
EPWM_INTSTS
EPWM Interrupt Status Register
0x58
read-write
n
0x0
0x0
BRK0IF
PWM Brake0 Flag\nNote: Software can write 1 to clear this bit.
16
1
read-write
0
PWM Brake does not recognize a falling signal at BKP0
#0
1
When PWM Brake detects a falling signal at pin BKP0, this flag will be set to high
#1
BRK1IF
PWM Brake1 Flag\nNote: Software can write 1 to clear this bit.
17
1
read-write
0
PWM Brake does not recognize a falling signal at BKP0
#0
1
When PWM Brake detects a falling signal at pin BKP0, this flag will be set to high
#1
CIF
PWM Channel 0 Central Interrupt Flag\nFlag is set by hardware when a channel 0 PWM rise counter reaches PWM_PERIOD0. Software can write 1 to clear this bit.
18
1
read-write
CMPDIF0
PWM Channel 0 DOWN Interrupt Flag\nFlag is set by hardware when a channel 0 PWM DOWN counter reaches PWM_CMPDAT0. Software can write 1 to clear this bit.
24
1
read-write
CMPDIF1
PWM Channel 1 DOWN Interrupt Flag\nFlag is set by hardware when a channel 1 PWM DOWN counter reaches PWM_CMPDAT01. Software can write 1 to clear this bit.
25
1
read-write
CMPDIF2
PWM Channel 2 DOWN Interrupt Flag\nFlag is set by hardware when a channel 2 PWM DOWN counter reaches PWM_CMPDAT2. Software can write 1 to clear this bit.
26
1
read-write
CMPDIF3
PWM Channel 3 DOWN Interrupt Flag\nFlag is set by hardware when a channel 3 PWM DOWN counter reaches PWM_CMPDAT03. Software can write 1 to clear this bit.
27
1
read-write
CMPDIF4
PWM Channel 4 DOWN Interrupt Flag\nFlag is set by hardware when a channel 4 PWM DOWN counter reaches PWM_CMPDAT04. Software can write 1 to clear this bit.
28
1
read-write
CMPDIF5
PWM Channel 5 DOWN Interrupt Flag\nFlag is set by hardware when a channel 5 PWM DOWN counter reaches PWM_CMPDAT05. Software can write 1 to clear this bit.
29
1
read-write
CMPUIF0
PWM Channel 0 UP Interrupt Flag\nFlag is set by hardware when a channel 0 PWM UP counter reaches PWM_CMPDAT0. Software can write 1 to clear this bit.
8
1
read-write
CMPUIF1
PWM Channel 1 UP Interrupt Flag\nFlag is set by hardware when a channel 1 PWM UP counter reaches PWM_CMPDAT01. Software can write 1 to clear this bit.
9
1
read-write
CMPUIF2
PWM Channel 2 UP Interrupt Flag\nFlag is set by hardware when a channel 2 PWM UP counter reaches PWM_CMPDAT02. Software can write 1 to clear this bit.
10
1
read-write
CMPUIF3
PWM Channel 3 UP Interrupt Flag\nFlag is set by hardware when a channel 3 PWMUP counter reaches PWM_CMPDAT03. Software can write 1 to clear this bit.
11
1
read-write
CMPUIF4
PWM Channel 4 UP Interrupt Flag\nFlag is set by hardware when a channel 4 PWM UP counter reaches PWM_CMPDAT04. Software can write 1 to clear this bit.
12
1
read-write
CMPUIF5
PWM Channel 5 UP Interrupt Flag\nFlag is set by hardware when a channel 5 PWM UP counter reaches PWM_CMPDAT05. Software can write 1 to clear this bit.
13
1
read-write
PIF
PWM Channel 0 Period Interrupt Flag\nFlag is set by hardware when PWM_PERIOD0down counter reaches zero. Software can write 1 to clear this bit.
0
1
read-write
NPCTL
EPWM_NPCTL
EPWM Negative Polarity Control Register
0x0
read-write
n
0x0
0x0
NEGPOLAR
PWM Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n
0
6
read-write
0
PWM_CHn output is active high
0
1
PWM_CHn output is active low
1
PERIOD
EPWM_PERIOD
EPWM Period Counter Register
0xC
read-write
n
0x0
0x0
PERIOD
PWM Counter/Timer Loaded Value
PERIODn determines the PWM Period.
Edge-aligned mode: where xy, could be 01, 23, 45 depending on the selected PWM channel.
Note: Any write to PERIODn will take effect in next PWM cycle.
0
16
read-write
PHCHG
EPWM_PHCHG
EPWM Phase Changed Register
0x78
-1
read-write
n
0x0
0x0
CMP0SEL
Alternative Comparator 0 Positive Input Selection\nSelect the positive input source of ACMP0.\n
24
2
read-write
0
Select ACMP0_P0 (PB.0) as the input of ACMP0
#00
1
Select ACMP0_P1 (PB.1) as the input of ACMP0
#01
2
Select ACMP0_P2 (PB.2) as the input of ACMP0
#10
3
Reserved
#11
CMP0ST
Start CMP0 Compare Function\n
28
1
read-write
0
Disable CMP0
#0
1
Start CMP0
#1
CMP1SEL
Alternative Comparator 1 Positive Input Selection\nSelect the positive input source of ACMP1.\n
26
2
read-write
0
Select ACMP1_P0 (PC.0) as the input of ACMP1
#00
1
Select ACMP1_P1 (PC.1) as the input of ACMP1
#01
2
Select ACMP1_P2 (PD.1) as the input of ACMP1
#10
3
Reserved
#11
CMP1ST
Start CMP1 Compare Function\n
29
1
read-write
0
Disable CMP1
#0
1
Start CMP1
#1
PHCHGEN
Enable Auto Phase Change Function\n
31
1
read-write
0
Auto Phase Change Function Disabled
#0
1
Auto Phase Change Function Enabled
#1
PWM0MD
Enable PWM0 Mask Data\n
0
1
read-write
0
PWM0 state is masked with zero
#0
1
PWM0 state is masked with one
#1
PWM0ME
Enable PWM0 Mask Function\n
8
1
read-write
0
PWM0 Mask Function Disabled
#0
1
PWM0 Mask Function Enabled
#1
PWM1MD
Enable PWM1 Mask Data\n
1
1
read-write
0
PWM1 state is masked with zero
#0
1
PWM1 state is masked with one
#1
PWM1ME
Enable PWM1 Mask Function\n
9
1
read-write
0
PWM1 Mask Function Disabled
#0
1
PWM1 Mask Function Enabled
#1
PWM2MD
Enable PWM2 Mask Data\n
2
1
read-write
0
PWM2 state is masked with zero
#0
1
PWM2 state is masked with one
#1
PWM2ME
Enable PWM2 Mask Function\n
10
1
read-write
0
PWM2 Mask Function Disabled
#0
1
PWM2 Mask Function Enabled
#1
PWM3MD
Enable PWM3 Mask Data\n
3
1
read-write
0
PWM3 state is masked with zero
#0
1
PWM3 state is masked with one
#1
PWM3ME
Enable PWM3 Mask Function\n
11
1
read-write
0
PWM3 Mask Function Disabled
#0
1
PWM3 Mask Function Enabled
#1
PWM4MD
Enable PWM4 Mask Data\n
4
1
read-write
0
PWM4 state is masked with zero
#0
1
PWM4 state is masked with one
#1
PWM4ME
Enable PWM4 Mask Function\n
12
1
read-write
0
PWM4 Mask Function Disabled
#0
1
PWM4 Mask Function Enabled
#1
PWM5MD
Enable PWM5 Mask Data\n
5
1
read-write
0
PWM5 state is masked with zero
#0
1
PWM5 state is masked with one
#1
PWM5ME
Enable PWM5 Mask Function\n
13
1
read-write
0
PWM5 Mask Function Disabled
#0
1
PWM5 Mask Function Enabled
#1
TRGSEL
Phase Change Trigger Selection\nSelect the trigger condition to load PHCHG from PHCHG_NXT.\nWhen the trigger condition occurs it will load PHCHG_NOW with PHCHG_NXT.\nPhase Change: PWM outputs are masked according with\n the definition of PWMx_ME and PWMx_MD in PHCHG_NOW.\n
20
3
read-write
0
Triggered by Timer0 event
#000
1
Triggered by Timer1 event
#001
2
Triggered by Timer2 event
#010
3
Triggered by PHCHG_NXT.HALL_STATE matched hall sensor state
#011
4
Triggered by CMP0 event
#100
5
Triggered by CMP1 event
#101
PHCHGALT
EPWM_PHCHGALT
EPWM Phase Change Alternative Control Register
0x80
read-write
n
0x0
0x0
CMP0ALT
Alternative CMP0 Positive Input Source Select\nNote: Register CMP0CR is describe in Comparator Controller chapter
0
1
read-write
0
The input of CMP0 is controlled by CMP1CR
#0
1
The input of CMP0 is controlled by CMP1SEL in PHCHG_NOW register
#1
CMP1ALT
Alternative CMP1 Positive Input Source Select\nNote: Register CMP1CR is describe in Comparator Controller chapter
1
1
read-write
0
The input of CMP1 is controlled by CMP1CR
#0
1
The input of CMP1 is controlled by CMP1SEL in PHCHG_NOW register
#1
PHCHGNXT
EPWM_PHCHGNXT
EPWM Next Phase Change Register
0x7C
-1
read-write
n
0x0
0x0
CMP0SEL
Alternative Comparator 0 Positive Input Selection Preset Bits\nThis bit field will be load to bit field CMP0SEL in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
24
2
read-write
CMP0ST
Start CMP0 Compare Function Control Preset Bit\nThis bit will be load to bit CMP0_ST in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
28
1
read-write
CMP1SEL
Alternative Comparator 1 Positive Input Selection Preset Bitfs\nThis bit field will be load to bit field CMP1SEL in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
26
2
read-write
CMP1ST
Start CMP1 Compare Function Control Preset Bit\nThis bit will be load to bit CMP1_ST in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
29
1
read-write
HALLSTS
Predicted Next HALL State\nThis bit field indicates the predicted hall state at next commutation. \nthe hardware will compare bits (CAP2, CAP1, CAP0) in timer 2 with HALL_STATE[2:0] when any hall state change occurs.\n If the comparison is matched it will trigger phase change function.
16
3
read-write
PHCHGEN
Enable Auto Phase Change Function Preset Bit\nThis bit will be load to bit PHCHG_EN in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
31
1
read-write
PWM0MD
Enable PWM0 Mask Data Preset Bit\nThis bit will be load to bit PWM0_MD in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
0
1
read-write
PWM0ME
Enable PWM0 Mask Function Preset Bit\nThis bit will be load to bit PWM0_ME in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
8
1
read-write
PWM1MD
Enable PWM1 Mask Data Preset Bit\nThis bit will be load to bit PWM1_MD in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
1
1
read-write
PWM1ME
Enable PWM1 Mask Function Preset Bit\nThis bit will be load to bit PWM1_ME in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
9
1
read-write
PWM2MD
Enable PWM2 Mask Data Preset Bit\nThis bit will be load to bit PWM2_MD in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
2
1
read-write
PWM2ME
Enable PWM2 Mask Function Preset Bit\nThis bit will be load to bit PWM2_ME in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
10
1
read-write
PWM3MD
Enable PWM3 Mask Data Preset Bit\nThis bit will be load to bit PWM3_MD in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
3
1
read-write
PWM3ME
Enable PWM3 Mask Function Preset Bit\nThis bit will be load to bit PWM3_ME in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
11
1
read-write
PWM4MD
Enable PWM4 Mask Data Preset Bit\nThis bit will be load to bit PWM4_MD in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
4
1
read-write
PWM4ME
Enable PWM4 Mask Function Preset Bit\nThis bit will be load to bit PWM4_ME in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
12
1
read-write
PWM5MD
Enable PWM5 Mask Data Preset Bit\nThis bit will be load to bit PWM5_MD in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
5
1
read-write
PWM5ME
Enable PWM5 Mask Function Preset Bit\nThis bit will be load to bit PWM5_ME in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
13
1
read-write
TRGSEL
Phase Change Trigger Selection Preset Bits\nThis bit field will be load to bit field TRGSEL in PHCHG_NOW when load trigger condition occurs.\nRefer to register PWM_PHCHG for detailed definition.
20
3
read-write
0
Triggered by Timer0 event
#000
1
Triggered by Timer1 event
#001
2
Triggered by Timer2 event
#010
3
Triggered by PHCHG_NXT.HALL_STATE matched hall sensor state
#011
4
Triggered by CMP0 event
#100
5
Triggered by CMP1 event
#101
RESDLY
EPWM_RESDLY
EPWM BRK Low Voltage Detect Resume Delay
0x5C
read-write
n
0x0
0x0
DELAY
PWM BRK Low Voltage Detect Resume Delay\n12 bits Down-Counter
0
12
read-write
FMC
FMC Register Map
FMC
0x0
0x0
0x18
registers
n
0x40
0x4
registers
n
0x50
0x8
registers
n
CRCCV
FMC_CRCCV
ISP CRC Current Value Register
0x54
read-only
n
0x0
0x0
CRCCV
CRC Current Value\nThis register provided current value of CRC durning calculation..
0
32
read-only
CRCSEED
FMC_CRCSEED
ISP CRC Seed Register
0x50
-1
read-write
n
0x0
0x0
CRCSEED
CRC Seed Data\nThis register was provided to be the initial value for CRC operation.\nWrite data to this register before ISP CRC operation.\nRead data from this register after ISP CRC read operation.
0
32
read-write
DFBA
FMC_DFBA
Data Flash Start Address
0x14
-1
read-only
n
0x0
0x0
DFBA
Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash start address is defined by user. Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0.
0
32
read-only
ISPADDR
FMC_ISPADDR
ISP Address Register
0x4
read-write
n
0x0
0x0
ISPADR
ISP Address
The NuMicro NM1810 series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation.
0
32
read-write
ISPCMD
FMC_ISPCMD
ISP Command Register
0xC
read-write
n
0x0
0x0
CMD
ISP Command \nISP commands are shown below:\n
0
6
read-write
0
Read
0x00
4
Read Unique ID
0x04
11
Read Company ID (0xDA)
0x0b
13
Read CRC32 Checksum Result After Calculating
0x0d
33
Program
0x21
34
Page Erase
0x22
45
Run Memory CRC32 Checksum Calculation
0x2d
46
Set Vector Page Re-Map
0x2e
ISPCTL
FMC_ISPCTL
ISP Control Register
0x0
read-write
n
0x0
0x0
APUEN
APROM Update Enable Control (Write Protect)\n
3
1
read-write
0
APROM cannot be updated when chip runs in APROM
#0
1
APROM can be updated when chip runs in APROM
#1
BS
Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (CPURF is 1) or system reset (SYSRF) is happened.\n
1
1
read-write
0
Boot from APROM
#0
1
Boot from LDROM
#1
CFGUEN
CONFIG Update Enable Control (Write Protect)\nWriting this bit to 1 enables software to update CONFIG value by ISP register control procedure regardless of program code is running in APROM or LDROM.\n
4
1
read-write
0
ISP update User Configuration Disabled
#0
1
ISP update User Configuration Enabled
#1
ISPEN
ISP Enable Control (Write Protect)\nSet this bit to enable ISP function.\n
0
1
read-write
0
ISP function Disabled
#0
1
ISP function Enabled
#1
ISPFF
ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) SPROM writes to itself if SPUEN is set to 0.\n(4) CONFIG is erased/programmed if CFGUEN is set to 0.\n(5) Destination address is illegal, such as over an available range.\nNote: Write 1 to clear this bit to 0.
6
1
read-write
LDUEN
LDROM Update Enable Control (Write Protect)\n
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated when the MCU runs in APROM
#1
SPUEN
SPROM Update Enable Control (Write Protect)\n
2
1
read-write
0
SPROM cannot be updated
#0
1
SPROM can be updated when the MCU runs in APROM
#1
ISPDAT
FMC_ISPDAT
ISP Data Register
0x8
read-write
n
0x0
0x0
ISPDAT
ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
0
32
read-write
ISPSTS
FMC_ISPSTS
ISP Status Register
0x40
read-write
n
0x0
0x0
CBS
Config Boot Selection (Read Only)\nThis is a mirror of CBS in CONFIG0.
1
2
read-only
ISPBUSY
ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same with FMC_ISPTRG bit 0.
0
1
read-only
0
ISP operation is finished
#0
1
ISP operation is progressed
#1
ISPFF
ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) SPROM writes to itself if SPUEN is set to 0.\n(4) CONFIG is erased/programmed if CFGUEN is set to 0.\n(5) Destination address is illegal, such as over an available range.\nNote: Write 1 to clear this bit to 0.
6
1
read-write
SCODE
Security Code Active Flag
This bit field set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active this bit is clear by SPROM page erase operation.
29
3
read-write
0
SPROM0/1/2 secured code are inactive
#000
1
SPROM0 secured code is active
#001
2
SPROM1 secured code is active
#010
4
SPROM2 secured code is active
#100
7
SPROM0/1/2 Secured code are active
#111
VECMAP
Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}.
9
12
read-only
ISPTRG
FMC_ISPTRG
ISP Trigger Register
0x10
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n
0
1
read-write
0
ISP operation is finished
#0
1
ISP operation is progressed
#1
GPIO
GPIO Register Map
GPIO
0x0
0x0
0x30
registers
n
0x40
0x34
registers
n
0x440
0x4
registers
n
0x80
0x34
registers
n
0x800
0x18
registers
n
0x840
0x14
registers
n
0x880
0x10
registers
n
0x8C0
0xC
registers
n
0xC0
0x34
registers
n
DBCTL
GPIO_DBCTL
Interrupt De-bounce Control Register
0x440
-1
read-write
n
0x0
0x0
DBCLKSEL
De-bounce Sampling Cycle Selection\n
0
4
read-write
0
Sample interrupt input once per 1 clocks
#0000
1
Sample interrupt input once per 2 clocks
#0001
2
Sample interrupt input once per 4 clocks
#0010
3
Sample interrupt input once per 8 clocks
#0011
4
Sample interrupt input once per 16 clocks
#0100
5
Sample interrupt input once per 32 clocks
#0101
6
Sample interrupt input once per 64 clocks
#0110
7
Sample interrupt input once per 128 clocks
#0111
8
Sample interrupt input once per 256 clocks
#1000
9
Sample interrupt input once per 2*256 clocks
#1001
10
Sample interrupt input once per 4*256 clocks
#1010
11
Sample interrupt input once per 8*256 clocks
#1011
12
Sample interrupt input once per 16*256 clocks
#1100
13
Sample interrupt input once per 32*256 clocks
#1101
14
Sample interrupt input once per 64*256 clocks
#1110
15
Sample interrupt input once per 128*256 clocks
#1111
DBCLKSRC
De-bounce Counter Clock Source Selection\n
4
1
read-write
0
De-bounce counter clock source is the HCLK
#0
1
De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC)
#1
ICLKON
Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern.
5
1
read-write
0
Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1
#0
1
All I/O pins edge detection circuit is always active after reset
#1
PA0_PDIO
PA0_PDIO
GPIO PA.n Pin Data Input/Output Register
0x800
read-write
n
0x0
0x0
PDIO
GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n
0
1
read-write
0
Corresponding GPIO pin set to low
#0
1
Corresponding GPIO pin set to high
#1
PA1_PDIO
PA1_PDIO
0x804
read-write
n
0x0
0x0
PA2_PDIO
PA2_PDIO
0x808
read-write
n
0x0
0x0
PA3_PDIO
PA3_PDIO
0x80C
read-write
n
0x0
0x0
PA4_PDIO
PA4_PDIO
0x810
read-write
n
0x0
0x0
PA5_PDIO
PA5_PDIO
0x814
read-write
n
0x0
0x0
PA_DATMSK
PA_DATMSK
PA Data Output Write Mask
0xC
read-write
n
0x0
0x0
DATMSK0
Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
0
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK1
Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
1
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK2
Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
2
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK3
Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
3
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK4
Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
4
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK5
Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
5
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
PA_DBEN
PA_DBEN
PA De-Bounce Enable Control Register
0x14
read-write
n
0x0
0x0
DBEN0
Port A-f Pin[n] Input Signal De-bounce Enable Biit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN1
Port A-f Pin[n] Input Signal De-bounce Enable Biit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
1
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN2
Port A-f Pin[n] Input Signal De-bounce Enable Biit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
2
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN3
Port A-f Pin[n] Input Signal De-bounce Enable Biit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
3
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN4
Port A-f Pin[n] Input Signal De-bounce Enable Biit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
4
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN5
Port A-f Pin[n] Input Signal De-bounce Enable Biit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
5
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
PA_DINOFF
PA_DINOFF
PA Digital Input Path Disable Control
0x4
read-write
n
0x0
0x0
DINOFF0
Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
16
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF1
Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
17
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF2
Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
18
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF3
Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
19
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF4
Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
20
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF5
Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
21
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
PA_DOUT
PA_DOUT
PA Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
0
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
1
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
2
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
3
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
4
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
5
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
PA_INTEN
PA_INTEN
PA Interrupt Enable Control Register
0x1C
read-write
n
0x0
0x0
FLIEN0
Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Biit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
0
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN1
Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Biit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
1
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN2
Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Biit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
2
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN3
Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Biit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
3
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN4
Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Biit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
4
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN5
Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Biit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
5
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
RHIEN0
Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
16
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN1
Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
17
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN2
Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
18
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN3
Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
19
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN4
Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
20
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN5
Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
21
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
PA_INTSRC
PA_INTSRC
PA Interrupt Source Flag
0x20
read-write
n
0x0
0x0
INTSRC0
Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\n
0
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC1
Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\n
1
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC2
Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\n
2
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC3
Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\n
3
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC4
Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\n
4
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC5
Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\n
5
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
PA_INTTYPE
PA_INTTYPE
PA Interrupt Trigger Type Control
0x18
read-write
n
0x0
0x0
TYPE0
Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
0
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE1
Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
1
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE2
Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
2
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE3
Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
3
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE4
Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
4
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE5
Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
5
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
PA_MODE
PA_MODE
PA I/O Mode Control
0x0
read-write
n
0x0
0x0
MODE0
Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n
0
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE1
Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n
2
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE2
Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n
4
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE3
Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n
6
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE4
Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n
8
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE5
Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n
10
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE6
Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n
12
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE7
Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n
14
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
PA_PHEN
PA_PHEN
PA Pull-High Control Register
0x30
-1
read-write
n
0x0
0x0
PHEN0
Port a Pull-high Resistor Control\n
0
1
read-write
0
Pull-High Resistor Enable
#0
1
Pull-High Resistor Disable
#1
PHEN1
Port a Pull-high Resistor Control\n
1
1
read-write
0
Pull-High Resistor Enable
#0
1
Pull-High Resistor Disable
#1
PHEN2
Port a Pull-high Resistor Control\n
2
1
read-write
0
Pull-High Resistor Enable
#0
1
Pull-High Resistor Disable
#1
PHEN3
Port a Pull-high Resistor Control\n
3
1
read-write
0
Pull-High Resistor Enable
#0
1
Pull-High Resistor Disable
#1
PHEN4
Port a Pull-high Resistor Control\n
4
1
read-write
0
Pull-High Resistor Enable
#0
1
Pull-High Resistor Disable
#1
PHEN5
Port a Pull-high Resistor Control\n
5
1
read-write
0
Pull-High Resistor Enable
#0
1
Pull-High Resistor Disable
#1
PA_PIN
PA_PIN
PA Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port A-f Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
0
1
read-only
PIN1
Port A-f Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
1
1
read-only
PIN2
Port A-f Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
2
1
read-only
PIN3
Port A-f Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
3
1
read-only
PIN4
Port A-f Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
4
1
read-only
PIN5
Port A-f Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
5
1
read-only
PA_PLEN
PA_PLEN
PA Pull-Low Control Register
0x2C
read-write
n
0x0
0x0
PLEN0
Port Pull-low Resistor Control
0
1
read-write
0
Pull-Low Resistor Disable
#0
1
Pull-Low Resistor Enable
#1
PLEN1
Port Pull-low Resistor Control
1
1
read-write
0
Pull-Low Resistor Disable
#0
1
Pull-Low Resistor Enable
#1
PLEN2
Port Pull-low Resistor Control
2
1
read-write
0
Pull-Low Resistor Disable
#0
1
Pull-Low Resistor Enable
#1
PLEN3
Port Pull-low Resistor Control
3
1
read-write
0
Pull-Low Resistor Disable
#0
1
Pull-Low Resistor Enable
#1
PLEN4
Port Pull-low Resistor Control
4
1
read-write
0
Pull-Low Resistor Disable
#0
1
Pull-Low Resistor Enable
#1
PLEN5
Port Pull-low Resistor Control
5
1
read-write
0
Pull-Low Resistor Disable
#0
1
Pull-Low Resistor Enable
#1
PA_SLEWCTL
PA_SLEWCTL
PA High Slew Rate Control Register
0x28
read-write
n
0x0
0x0
HSREN0
Port A-f Pin[n] High Slew Rate Control\n
0
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN1
Port A-f Pin[n] High Slew Rate Control\n
1
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN2
Port A-f Pin[n] High Slew Rate Control\n
2
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN3
Port A-f Pin[n] High Slew Rate Control\n
3
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN4
Port A-f Pin[n] High Slew Rate Control\n
4
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN5
Port A-f Pin[n] High Slew Rate Control\n
5
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
PA_SMTEN
PA_SMTEN
PA Input Schmitt Trigger Enable Register
0x24
read-write
n
0x0
0x0
SMTEN0
Port A-f Pin[n] Input Schmitt Trigger Enable Bit\n
0
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN1
Port A-f Pin[n] Input Schmitt Trigger Enable Bit\n
1
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN2
Port A-f Pin[n] Input Schmitt Trigger Enable Bit\n
2
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN3
Port A-f Pin[n] Input Schmitt Trigger Enable Bit\n
3
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN4
Port A-f Pin[n] Input Schmitt Trigger Enable Bit\n
4
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN5
Port A-f Pin[n] Input Schmitt Trigger Enable Bit\n
5
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
PB0_PDIO
PB0_PDIO
0x840
read-write
n
0x0
0x0
PB1_PDIO
PB1_PDIO
0x844
read-write
n
0x0
0x0
PB2_PDIO
PB2_PDIO
0x848
read-write
n
0x0
0x0
PB3_PDIO
PB3_PDIO
0x84C
read-write
n
0x0
0x0
PB4_PDIO
PB4_PDIO
0x850
read-write
n
0x0
0x0
PB_DATMSK
PB_DATMSK
0x4C
read-write
n
0x0
0x0
PB_DBEN
PB_DBEN
0x54
read-write
n
0x0
0x0
PB_DINOFF
PB_DINOFF
0x44
read-write
n
0x0
0x0
PB_DOUT
PB_DOUT
0x48
read-write
n
0x0
0x0
PB_INTEN
PB_INTEN
0x5C
read-write
n
0x0
0x0
PB_INTSRC
PB_INTSRC
0x60
read-write
n
0x0
0x0
PB_INTTYPE
PB_INTTYPE
0x58
read-write
n
0x0
0x0
PB_MODE
PB_MODE
0x40
read-write
n
0x0
0x0
PB_PHEN
PB_PHEN
0x70
read-write
n
0x0
0x0
PB_PIN
PB_PIN
0x50
read-write
n
0x0
0x0
PB_PLEN
PB_PLEN
0x6C
read-write
n
0x0
0x0
PB_SLEWCTL
PB_SLEWCTL
0x68
read-write
n
0x0
0x0
PB_SMTEN
PB_SMTEN
0x64
read-write
n
0x0
0x0
PC0_PDIO
PC0_PDIO
0x880
read-write
n
0x0
0x0
PC1_PDIO
PC1_PDIO
0x884
read-write
n
0x0
0x0
PC2_PDIO
PC2_PDIO
0x888
read-write
n
0x0
0x0
PC3_PDIO
PC3_PDIO
0x88C
read-write
n
0x0
0x0
PC_DATMSK
PC_DATMSK
0x8C
read-write
n
0x0
0x0
PC_DBEN
PC_DBEN
0x94
read-write
n
0x0
0x0
PC_DINOFF
PC_DINOFF
0x84
read-write
n
0x0
0x0
PC_DOUT
PC_DOUT
0x88
read-write
n
0x0
0x0
PC_INTEN
PC_INTEN
0x9C
read-write
n
0x0
0x0
PC_INTSRC
PC_INTSRC
0xA0
read-write
n
0x0
0x0
PC_INTTYPE
PC_INTTYPE
0x98
read-write
n
0x0
0x0
PC_MODE
PC_MODE
0x80
read-write
n
0x0
0x0
PC_PHEN
PC_PHEN
0xB0
read-write
n
0x0
0x0
PC_PIN
PC_PIN
0x90
read-write
n
0x0
0x0
PC_PLEN
PC_PLEN
0xAC
read-write
n
0x0
0x0
PC_SLEWCTL
PC_SLEWCTL
0xA8
read-write
n
0x0
0x0
PC_SMTEN
PC_SMTEN
0xA4
read-write
n
0x0
0x0
PD0_PDIO
PD0_PDIO
0x8C0
read-write
n
0x0
0x0
PD1_PDIO
PD1_PDIO
0x8C4
read-write
n
0x0
0x0
PD2_PDIO
PD2_PDIO
0x8C8
read-write
n
0x0
0x0
PD_DATMSK
PD_DATMSK
0xCC
read-write
n
0x0
0x0
PD_DBEN
PD_DBEN
0xD4
read-write
n
0x0
0x0
PD_DINOFF
PD_DINOFF
0xC4
read-write
n
0x0
0x0
PD_DOUT
PD_DOUT
0xC8
read-write
n
0x0
0x0
PD_INTEN
PD_INTEN
0xDC
read-write
n
0x0
0x0
PD_INTSRC
PD_INTSRC
0xE0
read-write
n
0x0
0x0
PD_INTTYPE
PD_INTTYPE
0xD8
read-write
n
0x0
0x0
PD_MODE
PD_MODE
0xC0
read-write
n
0x0
0x0
PD_PHEN
PD_PHEN
0xF0
read-write
n
0x0
0x0
PD_PIN
PD_PIN
0xD0
read-write
n
0x0
0x0
PD_PLEN
PD_PLEN
0xEC
read-write
n
0x0
0x0
PD_SLEWCTL
PD_SLEWCTL
0xE8
read-write
n
0x0
0x0
PD_SMTEN
PD_SMTEN
0xE4
read-write
n
0x0
0x0
HDIV
HDIV Register Map
HDIV
0x0
0x0
0x14
registers
n
DIVIDEND
HDIV_DIVIDEND
Dividend Source Register
0x0
read-write
n
0x0
0x0
DIVIDEND
Dividend Source\nThis register is given the dividend of divider before calculation starting.
0
32
read-write
DIVISOR
HDIV_DIVISOR
Divisor Source Resister
0x4
-1
read-write
n
0x0
0x0
DIVISOR
Divisor Source\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written, hardware divider will start calculate.
0
16
read-write
QUOTIENT
HDIV_QUOTIENT
Quotient Result Resister
0x8
read-write
n
0x0
0x0
QUOTIENT
Quotient Result\nThis register holds the quotient result of divider after calculation complete.
0
32
read-write
REM
HDIV_REM
Remainder Result Register
0xC
read-write
n
0x0
0x0
REM
Remainder Result\nThe remainder of hardware divider is 16-bit sign integer (REM[15:0]) with sign extension (REM[31:16]) to 32-bit integer.
0
32
read-write
STATUS
HDIV_STATUS
Divider Status Register
0x10
-1
read-only
n
0x0
0x0
DIVBYZERO
Divisor Zero Warning\nNote: The DIVBYZERO flag is used to indicate divide-by-zero situation and updated whenever HDIV_DIVISOR is written. This register is read only.
1
1
read-only
0
The divisor is not 0
#0
1
The divisor is 0
#1
INT
INT Register Map
INT
0x0
0x80
0x8
registers
n
IRQSTS
INT_IRQSTS
MCU IRQ Number Identity Register
0x84
read-write
n
0x0
0x0
IRQ
MCU IRQ Source Register\nThe IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. There is one mode to generate interrupt to Cortex-M0 - the normal mode.\nThe IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0.\nWhen the IRQ[n] is 0, setting IRQ[n] to 1 will generate an interrupt to Cortex-M0 NVIC[n].\nWhen the IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting IRQ[n] 0 has no effect.
0
32
read-write
NMICTL
INT_NMICTL
NMI Source Interrupt Select Control Register
0x80
read-write
n
0x0
0x0
NMISEL
NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMTSEL.
0
5
read-write
NMISELEN
NMI Interrupt Enable Control (Write Protected)\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
8
1
read-write
0
NMI interrupt Disabled
#0
1
NMI interrupt Enabled
#1
PGA
PGA Register Map
PGA
0x0
0x0
0x4
registers
n
CTL
PGA_CTL
Programmable Gain Amplifier Control Register
0x0
read-write
n
0x0
0x0
GAIN
PGA Gain Selection\n
4
3
read-write
0
1
#000
1
2
#001
2
4
#010
3
6
#011
4
8
#100
5
10
#101
6
12
#110
7
16
#111
PGAADEN
PGA Output to ADC Enable Bit\n
1
1
read-write
0
PGA output to ADC Disabled
#0
1
PGA output to ADC Enabled
#1
PGACMPEN
PGA Output to ACMP Enable Bit\n
3
1
read-write
0
PGA output to ACMP Disabled
#0
1
PGA output to ACMP Enabled
#1
PGAEN
Programmable Gain Amplifier Enable Bit\nThe PGA output needs to wait stable 20 s after PGAEN is first set.
0
1
read-write
0
Programmable Gain Amplifier Disabled
#0
1
Programmable Gain Amplifier Enabled
#1
PGAOUTEN
PGA Output Enable Bit\n
2
1
read-write
0
PGA output Disabled
#0
1
PGA output Enabled
#1
SCS
SCS Register Map
SCS
0x0
0x10
0xC
registers
n
0x100
0x4
registers
n
0x180
0x4
registers
n
0x200
0x4
registers
n
0x280
0x4
registers
n
0x400
0x20
registers
n
0xD00
0x8
registers
n
0xD10
0x4
registers
n
0xD1C
0x8
registers
n
CPUID
SCS_CPUID
CPUID Base Register
0xD00
-1
read-only
n
0x0
0x0
IMPLEMENTER
Implementer Code \n
24
8
read-only
PART
Architecture of the Processor \nReads as 0xC for ARMv6-M parts
16
4
read-only
PARTNO
Part Number of the Processor \nReads as 0xC20.
4
12
read-only
REVISION
Revision Number \nReads as 0x0
0
4
read-only
ICSR
SCS_ICSR
Interrupt Control State Register
0xD04
read-write
n
0x0
0x0
ISRPENDING
Interrupt Pending Flag,Excluding NMI and Faults (Read Only)\n
22
1
read-only
0
Interrupt not pending
#0
1
Interrupt pending
#1
ISRPREEMPT
Interrupt Preempt Bit(Read Only)\nIf set, a pending exception will be serviced on exit from the debug halt state
23
1
read-only
NMIPENDSET
NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception, normally the processor entersthe NMI exception handler as soon as it detects a write of 1 to this bit. Entering thehandler then clears this bit to 0. This means a read of this bit by the NMI exceptionhandler returns 1 only if the NMI signal is reasserted while the processor is executingthat handler.
31
1
read-write
0
No effect.\nNMI exception not pending
#0
1
Changes NMI exception state to pending.\nNMI exception pending
#1
PENDSTCLR
SysTick Exception Clear-pending Bit
Write Operation:
Note: This bit is write-only. When you want to clear PENDST bit, you must write 0 toPENDSTSET and write 1 to PENDSTCLR at the same time.
25
1
read-write
0
No effect
#0
1
Removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick Exception Set-pending Bit\nWrite Operation:\n
26
1
read-write
0
No effect.\nSysTick exception is not pending
#0
1
Changes SysTick exception state to pending.\nSysTick exception is pending
#1
PENDSVCLR
PendSV Clear-pending Bit
Write Operation:
This bit is write-only. To clear the PENDSV bit, you must write 0 to PENDSVSET andwrite 1 to PENDSVCLR at the same time.
27
1
read-write
0
No effect
#0
1
Removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending
28
1
read-write
0
No effect.\nPendSV exception is not pending
#0
1
Changes PendSV exception state to pending.\nPendSV exception is pending
#1
VECTACTIVE
Contains the Active Exception Number\n
0
9
read-write
0
Thread mode
0
VECTPENDING
Exception Number of the Highest Priority Pending Enabled Exception\n
12
9
read-write
0
No pending exceptions
0
NVIC_ICER
NVIC_ICER
IRQ0 ~ IRQ31 Clear-Enable Control Register
0x180
read-write
n
0x0
0x0
CLRENA
Interrupt Disable Register\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite:\nRead value indicates the current enable status.
0
32
read-write
0
No effect.\nAssociated interrupt status is Disabled
0
1
Write 1 to disable associated interrupt.\nAssociated interrupt status is Enabled
1
NVIC_ICPR
NVIC_ICPR
IRQ0 ~ IRQ31 Clear-Pending Control Register
0x280
read-write
n
0x0
0x0
CLRPEND
Clear Interrupt Pending Register\nWrite:\nRead value indicates the current pending status.
0
32
read-write
0
No effect.\nAssociated interrupt in not in pending status
0
1
Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status
1
NVIC_IPR0
NVIC_IPR0
IRQ0 ~ IRQ3 Interrupt Priority Control Register
0x400
read-write
n
0x0
0x0
PRI_0
Priority of IRQ0\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_1
Priority of IRQ1\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_2
Priority of IRQ2\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_3
Priority of IRQ3\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR1
NVIC_IPR1
IRQ4 ~ IRQ7 Interrupt Priority Control Register
0x404
read-write
n
0x0
0x0
PRI_4
Priority of IRQ4\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_5
Priority of IRQ5\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_6
Priority of IRQ6\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_7
Priority of IRQ7\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR2
NVIC_IPR2
IRQ8 ~ IRQ11 Interrupt Priority Control Register
0x408
read-write
n
0x0
0x0
PRI_10
Priority of IRQ10\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_11
Priority of IRQ11\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
PRI_8
Priority of IRQ8\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_9
Priority of IRQ9\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
NVIC_IPR3
NVIC_IPR3
IRQ12 ~ IRQ15 Interrupt Priority Control Register
0x40C
read-write
n
0x0
0x0
PRI_12
Priority of IRQ12\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_13
Priority of IRQ13\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_14
Priority of IRQ14\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_15
Priority of IRQ15\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR4
NVIC_IPR4
IRQ16 ~ IRQ19 Interrupt Priority Control Register
0x410
read-write
n
0x0
0x0
PRI_16
Priority of IRQ16\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_17
Priority of IRQ17\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_18
Priority of IRQ18\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_19
Priority of IRQ19\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR5
NVIC_IPR5
IRQ20 ~ IRQ23 Interrupt Priority Control Register
0x414
read-write
n
0x0
0x0
PRI_20
Priority of IRQ20\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_21
Priority of IRQ21\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_22
Priority of IRQ22\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_23
Priority of IRQ23\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR6
NVIC_IPR6
IRQ24 ~ IRQ27 Interrupt Priority Control Register
0x418
read-write
n
0x0
0x0
PRI_24
Priority of IRQ24\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_25
Priority of IRQ25\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_26
Priority of IRQ26\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_27
Priority of IRQ27\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR7
NVIC_IPR7
IRQ28 ~ IRQ31 Interrupt Priority Control Register
0x41C
read-write
n
0x0
0x0
PRI_28
Priority of IRQ28\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_29
Priority of IRQ29\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_30
Priority of IRQ30\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_31
Priority of IRQ31\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_ISER
NVIC_ISER
IRQ0 ~ IRQ31 Set-Enable Control Register
0x100
read-write
n
0x0
0x0
SETENA
Interrupt Enable Register \nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite:\nRead value indicates the current enable status.
0
32
read-write
0
No effect.\nAssociated interrupt status is Disabled
0
1
Write 1 to enable associated interrupt.\nAssociated interrupt status is Enabled
1
NVIC_ISPR
NVIC_ISPR
IRQ0 ~ IRQ31 Set-Pending Control Register
0x200
read-write
n
0x0
0x0
SETPEND
Set Interrupt Pending Register\nWrite:\nRead value indicates the current pending status.
0
32
read-write
0
No effect.\nAssociated interrupt in not in pending status
0
1
Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status
1
SCR
SCS_SCR
System Control Register
0xD10
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processorfrom WFE. If the processor is not waiting for an event, the event is registered and affectsthe next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Only enabled interrupts or events can wake-up the processor, disabled interrupts areexcluded
#0
1
Enabled events and all interrupts, including disabled interrupts, can wake-up theprocessor
#1
SLEEPDEEP
Processor Deep Sleep and Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode:\n
2
1
read-write
0
Sleep mode
#0
1
Deep Sleep mode
#1
SLEEPONEXIT
Sleep-on-exit Enable Control\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode.\n
1
1
read-write
0
Do not sleep when returning to Thread mode
#0
1
Enter Sleep or Deep Sleep when returning from ISR to Thread mode.Setting this bit to 1 enables an interrupt driven application to avoid returning to an emptymain application
#1
SHPR2
SCS_SHPR2
System Handler Priority Register 2
0xD1C
read-write
n
0x0
0x0
PRI_11
Priority of System Handler 11 - SVCall
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
SHPR3
SCS_SHPR3
System Handler Priority Register 3
0xD20
read-write
n
0x0
0x0
PRI_14
Priority of System Handler 14 - PendSV
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_15
Priority of System Handler 15 - SysTick
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
SYST_CTL
SYST_CTL
SysTick Control and Status
0x10
-1
read-write
n
0x0
0x0
CLKSRC
System Tick Clock Source Select Bit\n
2
1
read-write
0
Clock source is optional, refer to STCLKSEL
#0
1
Core clock used for SysTick timer
#1
COUNTFLAG
System Tick Counter Flag\nReturns 1 If Timer Counted to 0 Since Last Time this Register Was Read\n
16
1
read-write
0
COUNTFLAG is cleared on read or by a write to the Current Value register
#0
1
COUNTFLAG is set by a count transition from 1 to 0
#1
ENABLE
System Tick Counter Enable Control\n
0
1
read-write
0
System Tick counter Disabled
#0
1
System Tick counter will operate in a multi-shot manner
#1
TICKINT
System Tick Interrupt Enable Control\n
1
1
read-write
0
Counting down to 0 will not cause the SysTick exception to be pended. User can use COUNTFLAG to determine if a count to zero has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended
#1
SYST_CVR
SYST_CVR
SysTick Current Value Register
0x18
read-write
n
0x0
0x0
CURRENT
System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
0
24
read-write
SYST_RVR
SYST_RVR
SysTick Reload Value Register
0x14
read-write
n
0x0
0x0
RELOAD
System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0.
0
24
read-write
SYS
SYS Register Map
SYS
0x0
0x0
0x14
registers
n
0x100
0x4
registers
n
0x114
0x4
registers
n
0x18
0x8
registers
n
0x24
0x4
registers
n
0x30
0x10
registers
n
0x80
0xC
registers
n
BODCTL
SYS_BODCTL
Brown-Out Detector Control Register
0x18
-1
read-write
n
0x0
0x0
BODEN
Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (CONFIG0 [18]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
Brown-out Detector function Disabled
#0
1
Brown-out Detector function Enabled
#1
BODIF
Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0.
5
1
read-write
0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting
#0
1
When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled
#1
BODLPM
Brown-out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
BOD operate in normal mode (default)
#0
1
BOD Low Power mode Enabled
#1
BODOUT
Brown-out Detector Output Status
It means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled , this bit always responds 0000.
7
1
read-write
0
Brown-out Detector output status is 0
#0
1
Brown-out Detector output status is 1
#1
BODRSTEN
Brown-out Reset Enable Bit (Write Protect)
The default value is set by flash controller user configuration register CBORST(CONFIG0[19]) bit .
Note1:
While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). BOD will wake CPU up when BODOUT is high in power-down mode.
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
Brown-out INTERRUPT function Enabled
#0
1
Brown-out RESET function Enabled
#1
BODVL
Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0 [22:20]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
1
3
read-write
0
Brown-Out Detector threshold voltage is 2.0V
#000
1
Brown-Out Detector threshold voltage is 2.2V
#001
2
Brown-Out Detector threshold voltage is 2.4V
#010
3
Brown-Out Detector threshold voltage is 2.7V
#011
4
Brown-Out Detector threshold voltage is 3.0V
#100
5
Brown-Out Detector threshold voltage is 3.7V
#101
6
Brown-Out Detector threshold voltage is 4.0V
#110
7
Brown-Out Detector threshold voltage is 4.3V
#111
LVREN
Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2:
15
1
read-write
0
Low Voltage Reset function Disabled
#0
1
Low Voltage Reset function Enabled
#1
GPA_MFP
SYS_GPA_MFP
GPIOA Multiple Function Control Register
0x30
read-write
n
0x0
0x0
PA0MFP
PA.0 Multi-function Pin Selection
0
4
read-write
PA1MFP
PA.1 Multi-function Pin Selection
4
4
read-write
PA2MFP
PA.2 Multi-function Pin Selection
8
4
read-write
PA3MFP
PA.3 Multi-function Pin Selection
12
4
read-write
PA4MFP
PA.4 Multi-function Pin Selection
16
4
read-write
PA5MFP
PA.5 Multi-function Pin Selection
20
4
read-write
GPB_MFP
SYS_GPB_MFP
GPIOB Multiple Function Control Register
0x34
read-write
n
0x0
0x0
PB0MFP
PB.0 Multi-function Pin Selection
0
4
read-write
PB1MFP
PB.1 Multi-function Pin Selection
4
4
read-write
PB2MFP
PB.2 Multi-function Pin Selection
8
4
read-write
PB3MFP
PB.3 Multi-function Pin Selection
12
4
read-write
PB4MFP
PB.4 Multi-function Pin Selection
16
4
read-write
GPC_MFP
SYS_GPC_MFP
GPIOC Multiple Function Control Register
0x38
read-write
n
0x0
0x0
PC0MFP
PC.0 Multi-function Pin Selection
0
4
read-write
PC1MFP
PC.1 Multi-function Pin Selection
4
4
read-write
PC2MFP
PC.2 Multi-function Pin Selection
8
4
read-write
PC3MFP
PC.3 Multi-function Pin Selection
12
4
read-write
GPD_MFP
SYS_GPD_MFP
GPIOD Multiple Function Control Register
0x3C
-1
read-write
n
0x0
0x0
PD0MFP
PD.0 Multi-function Pin Selection
0
4
read-write
PD1MFP
PD.1 Multi-function Pin Selection
4
4
read-write
PD2MFP
PD.2 Multi-function Pin Selection
8
4
read-write
IPRST0
SYS_IPRST0
Peripheral Reset Control Register 0
0x8
read-write
n
0x0
0x0
CHIPRST
Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\nAbout the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
Chip normal operation
#0
1
Chip one-shot reset
#1
CPURST
Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
Processor core normal operation
#0
1
Processor core one-shot reset
#1
IPRST1
SYS_IPRST1
Peripheral Reset Control Register 1
0xC
read-write
n
0x0
0x0
ACMPRST
ACMP Controller Reset \n
30
1
read-write
0
ACMP controller normal operation
#0
1
ACMP controller reset
#1
ADCRST
ADC Controller Reset\n
28
1
read-write
0
ADC controller normal operation
#0
1
ADC controller reset
#1
BPWMRST
Basic PWM Controller Reset\n
16
1
read-write
0
BPWM controller normal operation
#0
1
BPWM controller reset
#1
CAPRST
CAP Controller Reset\n
8
1
read-write
0
CAP controller normal operation
#0
1
CAP controller reset
#1
EPWMRST
Enhanced PWM Controller Reset\n
20
1
read-write
0
EPWM controller normal operation
#0
1
EPWM controller reset
#1
GPIORST
GPIO Controller Reset\n
1
1
read-write
0
GPIO controller normal operation
#0
1
GPIO controller reset
#1
PGARST
PGA Controller Reset\n
12
1
read-write
0
PGA controller normal operation
#0
1
PGA controller reset
#1
TMR0RST
Timer0 Controller Reset\n
2
1
read-write
0
Timer0 controller normal operation
#0
1
Timer0 controller reset
#1
TMR1RST
Timer1 Controller Reset\n
3
1
read-write
0
Timer1 controller normal operation
#0
1
Timer1 controller reset
#1
USCI0RST
USCI0 Controller Reset\n
24
1
read-write
0
USCI0 controller normal operation
#0
1
USCI0 controller reset
#1
USCI1RST
USCI1 Controller Reset\n
25
1
read-write
0
USCI1 controller normal operation
#0
1
USCI1 controller reset
#1
IRCTCTL
SYS_IRCTCTL
HIRC Trim Control Register
0x80
-1
read-write
n
0x0
0x0
FREQSEL
Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim..\n
0
1
read-write
0
Disable HIRC auto trim function
#0
1
Enable HIRC auto trim function and trim HIRC to 48 MHz
#1
LOOPSEL
Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
4
2
read-write
0
Trim value calculation is based on average difference in 4 32.768 kHz clock
#00
1
Trim value calculation is based on average difference in 8 32.768 kHz clock
#01
2
Trim value calculation is based on average difference in 16 32.768 kHz clock
#10
3
Trim value calculation is based on average difference in 32 32.768 kHz clock
#11
RETRYCNT
Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.\n
6
2
read-write
0
Trim retry count limitation is 64 loops
#00
1
Trim retry count limitation is 128 loops
#01
2
Trim retry count limitation is 256 loops
#10
3
Trim retry count limitation is 512 loops
#11
IRCTIEN
SYS_IRCTIEN
HIRC Trim Interrupt Enable Register
0x84
read-write
n
0x0
0x0
CLKEIEN
Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.\n
2
1
read-write
0
Disable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU
#0
1
Enable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU
#1
TFAILIEN
Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.\n
1
1
read-write
0
Disable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU
#0
1
Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU
#1
IRCTISTS
SYS_IRCTISTS
HIRC Trim Interrupt Status Register
0x88
read-write
n
0x0
0x0
CLKERRIF
Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\n\nIf this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.\n
2
1
read-write
0
Clock frequency is accuracy
#0
1
Clock frequency is inaccuracy
#1
FREQLOCK
HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.\n
0
1
read-write
0
The internal high-speed oscillator frequency doesn't lock at 48 MHz yet
#0
1
The internal high-speed oscillator frequency locked at 48 MHz
#1
TFAILIF
Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.\n
1
1
read-write
0
Trim value update limitation count does not reach
#0
1
Trim value update limitation count reached and HIRC frequency still not locked
#1
IVSCTL
SYS_IVSCTL
Internal Voltage Source Control Register
0x1C
read-write
n
0x0
0x0
VTEMPEN
Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function chapter for details.
0
1
read-write
0
Temperature sensor function Disabled (default)
#0
1
Temperature sensor function Enabled
#1
PDID
SYS_PDID
Part Device Identification Number Register
0x0
read-only
n
0x0
0x0
PDID
Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used.
0
32
read-only
PORCTL
SYS_PORCTL
Power-On-Reset Controller Register
0x24
read-write
n
0x0
0x0
POROFF
Power-on Reset Enable Bit (Write Protect)
When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
16
read-write
REGLCTL
SYS_REGLCTL
Register Write-Protection Control Register
0x100
read-write
n
0x0
0x0
REGLCTL
Register Lock Control Disable Index (Read Only)
The Protected registers are:
SYS_IPRST0
SYS_IPRST0
SYS_BODCTL
LDOCR
SYS_PORCTL
CLK_PWRCTL
CLK_APBCLK bit[0]
CLK_CLKSEL0
CLK_CLKSEL1 bit[1:0]
NMI_SEL bit[8]
FMC_ISPCTL
FMC_ISPTRG
WDT_CTL
Note: The bits which are write-protected will be noted as (Write Protect) beside the description.
0
1
read-only
0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
#0
1
Write-protection Disabled for writing protected registers
#1
REGPROTDIS
Register Write-protection Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field. After this sequence is completed, the SYS_REGLCTL bit will be set to 1 and write-protection registers can be normal write.
1
7
write-only
RSTSTS
SYS_RSTSTS
System Reset Status Register
0x4
read-write
n
0x0
0x0
BODRF
BOD Reset Flag
The BOD reset flag is set by the Reset Signal from the Brown-Out Detector to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
4
1
read-write
0
No reset from BOD
#0
1
The BOD had issued the reset signal to reset the system
#1
CPURF
CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0.
7
1
read-write
0
No reset from CPU
#0
1
The Cortex-M0 Core and FMC are reset by software setting CPURST to 1
#1
LVRF
LVR Reset Flag
The LVR reset flag is set by the Reset Signal from the Low Voltage Reset Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
3
1
read-write
0
No reset from LVR
#0
1
LVR controller had issued the reset signal to reset the system
#1
PINRF
NRESET Pin Reset Flag
The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
1
1
read-write
0
No reset from nRESET pin
#0
1
Pin nRESET had issued the reset signal to reset the system
#1
PORF
POR Reset Flag
The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
0
1
read-write
0
No reset from POR or CHIPRST
#0
1
Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system
#1
SYSRF
System Reset Flag
The system reset flag is set by the Reset Signal from the Cortex-M0 Core to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
5
1
read-write
0
No reset from Cortex-M0
#0
1
The Cortex-M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core
#1
WDTRF
WDT Reset Flag
The WDT reset flag is set by the Reset Signal from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
Note1: Write 1 to clear this bit to 0.
Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
2
1
read-write
0
No reset from watchdog timer or window watchdog timer
#0
1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
#1
TSOFFSET
SYS_TSOFFSET
Temperature sensor offset Register
0x114
read-only
n
0x0
0x0
VTEMP0
Temperature Sensor Offset Value\nThis field reflects temperature sensor output voltage offset at 25oC.
0
12
read-only
VTEMP1
Temperature Sensor Offset Value\nThis field reflects temperature sensor output voltage offset at 125oC.
16
12
read-only
WAIT
SYS_WAIT
HCLK Wait State Cycle Control Register
0x10
-1
read-write
n
0x0
0x0
HCLKWS
HCLK Wait State Cycle Control Bit\nThis bit is used to enable/disable HCLK wait state when access Flash.\nNote: When HCLK frequency is faster than 48MHz, insert one wait state is necessary.
0
1
read-write
0
No wait state
#0
1
One wait state inserted when CPU access Flash
#1
TMR
TMR Register Map
TMR
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
0x40
0x14
registers
n
TIMER0_CAP
TIMER0_CAP
Timer0 Capture Data Register
0x10
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on ACMPOx matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
0
24
read-only
TIMER0_CMP
TIMER0_CMP
Timer0 Compare Register
0x4
read-write
n
0x0
0x0
CMPDAT
Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When Timer is operating at Continuous Counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into CMPDAT field. But if Timer is operating at other modes except Periodic mode on M05xxDN/DE, the 24-bit up counter will restart counting and using newest CMPDAT value to be the timer compared value if software writes a new value into CMPDAT field.
0
24
read-write
TIMER0_CNT
TIMER0_CNT
Timer0 Data Register
0xC
read-only
n
0x0
0x0
CNT
Timer Data Register\nIf CNTDATEN is set to 1, CNT register value will be updated continuously to monitor 24-bit up counter value.
0
24
read-only
TIMER0_CTL
TIMER0_CTL
Timer0 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CMPCTL
TIMERx_CMP Mode Control\n
17
1
read-write
0
In One-shot or Periodic mode, when write new CMPDAT, timer counter will reset
#0
1
In One-shot or Periodic mode, when write new CMPDAT if new CMPDAT CNT (TIMERx_CNT[23:0])(current counter) , timer counter keep counting and will not reset. If new CMPDAT = CNT(current counter) , timer counter will reset
#1
CNTDATEN
Data Load Enable Control\nWhen CNTDATEN is set, CNT (TIMERx_CNT[23:0]) (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n
16
1
read-write
0
Timer Data Register update Disabled
#0
1
Timer Data Register update Enabled while Timer counter is active
#1
CNTEN
Timer Enable Control \n
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Counter Mode Enable Control
This bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to section Event Counting Mode for detail description.
24
1
read-write
0
External event counter mode Disabled
#0
1
External event counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Interrupt Enable Control\nIf this bit is enabled, when the timer interrupt flag (TIF) is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer Interrupt function Disabled
#0
1
Timer Interrupt function Enabled
#1
OPMODE
Timer Operating Mode\n
27
2
read-write
0
The timer is operating in the One-shot mode. The associated interrupt signal is generated once (if INTEN is enabled) and CNTEN is automatically cleared by hardware
#00
1
The timer is operating in Periodic mode. The associated interrupt signal is generated periodically (if INTEN is enabled)
#01
2
The timer is operating in Toggle mode. The interrupt signal is generated periodically (if INTEN is enabled). The associated signal (tout) is changing back and forth with 50% duty cycle
#10
3
The timer is operating in Continuous Counting mode. The associated interrupt signal is generated when TIMERx_CNT = TIMERx_CMP (if INTEN is enabled). However, the 24-bit up-timer counts continuously. Please refer to 6.12.5.2 for detailed description about Continuous Counting mode operation
#11
PSC
Prescale Counter\n
0
8
read-write
RSTCNT
Timer Reset\n
26
1
read-write
0
No effect
#0
1
Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit if ACTSTS is 1
#1
WKEN
Wake-up Enable Bit\nWhen WKEN is set and the TIF or CAPIF is set, the timer controller will generator a wake-up trigger event to CPU.\n
23
1
read-write
0
Wake-up trigger event Disabled
#0
1
Wake-up trigger event Enabled
#1
TIMER0_EINTSTS
TIMER0_EINTSTS
Timer0 Extended Event Interrupt Status Register
0x18
read-write
n
0x0
0x0
CAPIF
Timer Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote1: This bit is cleared by writing 1 to it.\nNote2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on ACMPOx matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. \nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
0
1
read-write
0
Timer Cpautre interrupt did not occur
#0
1
Timer Capture interrupt occurred
#1
TIMER0_EXTCTL
TIMER0_EXTCTL
Timer0 Extended Event Control Register
0x14
read-write
n
0x0
0x0
CAPEDGE
Timer Capture Pin Edge Detection\n
1
2
read-write
0
A falling edge on ACMPOx will be detected
#00
1
A rising edge on ACMPO1 will be detected
#01
2
Either rising or falling edge on ACMPOx will be detected
#10
3
Reserved
#11
CAPEN
Timer Capture Function Enable Bit\nThis bit enables the Timer Capture Function\n
3
1
read-write
0
Timer Capture Function Disabled
#0
1
Timer Capture Function Enabled
#1
CAPFUNCS
Capture Function Select Bit\nNote1: When CAPFUNCS is 0, transition on ACMPOx is using to save the 24-bit timer counter value to CAPDAT register.\nNote2: When CAPFUNCS is 1, transition on ACMPOx is using to reset the 24-bit timer counter value.
4
1
read-write
0
Capture Mode Enabled
#0
1
Reset Mode Enabled
#1
CAPIEN
Timer Capture Interrupt Enable Bit\n
5
1
read-write
0
Timer Capture Interrupt Disabled
#0
1
Timer Capture Interrupt Enabled
#1
CAPMODE
Capture Mode Select Bit\n
8
1
read-write
0
Timer counter reset function or free-counting mode of timer capture function
#0
1
Trigger-counting mode of timer capture function
#1
CNTPHASE
Timer External Count Pin Phase Detect Selection\n
0
1
read-write
0
A falling edge of TMx (x = 0~1) pin will be counted
#0
1
A rising edge of TMx (x = 0~1) pin will be counted
#1
ECNTDBEN
Timer Counter Input Pin De-bounce Enable Control\n
7
1
read-write
0
TMx (x = 0~1) pin de-bounce Disabled
#0
1
TMx (x = 0~1) pin de-bounce Enabled
#1
TIMER0_INTSTS
TIMER0_INTSTS
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated
#1
TIMER1_CAP
TIMER1_CAP
0x30
read-write
n
0x0
0x0
TIMER1_CMP
TIMER1_CMP
0x24
read-write
n
0x0
0x0
TIMER1_CNT
TIMER1_CNT
0x2C
read-write
n
0x0
0x0
TIMER1_CTL
TIMER1_CTL
0x20
read-write
n
0x0
0x0
TIMER1_EINTSTS
TIMER1_EINTSTS
0x38
read-write
n
0x0
0x0
TIMER1_EXTCTL
TIMER1_EXTCTL
0x34
read-write
n
0x0
0x0
TIMER1_INTSTS
TIMER1_INTSTS
0x28
read-write
n
0x0
0x0
TIMER_CCAP0
TIMER_CCAP0
Timer Continuous Capture Data Register 0
0x44
read-only
n
0x0
0x0
CAPDAT
Timer Continuous Capture Data Register\nTIMER_CCAP0 store the timer count value of first rising edge\nTIMER_CCAP1 store the timer count value of first falling edge\nTIMER_CCAP2 store the timer count value of second rising edge\nTIMER_CCAP3 store the timer count value of second rising edge
0
24
read-only
TIMER_CCAP1
TIMER_CCAP1
0x48
read-write
n
0x0
0x0
TIMER_CCAP2
TIMER_CCAP2
0x4C
read-write
n
0x0
0x0
TIMER_CCAP3
TIMER_CCAP3
0x50
read-write
n
0x0
0x0
TIMER_CCAPCTL
TIMER_CCAPCTL
Timer Continuous Capture Control Register
0x40
read-write
n
0x0
0x0
CAPCHSEL
Capture Timer Channel Selection\nSelect the channel to be the continuous capture event.\n
4
1
read-write
0
PD.2
#0
1
PC.2
#1
CAPF1F
Capture Falling Edge 1 Flag\nFirst falling edge already captured, this bit will be set to 1.\nNote: This bit is cleared by hardware automatically when writing 1 to this bit.
9
1
read-write
0
None
#0
1
CAPDAT(TIMER_CCAP1[23:0]) data is ready for read
#1
CAPF2F
Capture Falling Edge 2 Flag\nSecond falling edge already captured, this bit will be set to 1\nNote: This bit is cleared by hardware automatically when writing 1 to this bit.
11
1
read-write
0
None
#0
1
CAPDAT(TIMER_CCAP3[23:0]) data is ready for read
#1
CAPR1F
Capture Rising Edge 1 Flag\nFirst rising edge already captured, this bit will be set to 1.\nNote: This bit is cleared by hardware automatically when writing 1 to this bit.
8
1
read-write
0
None
#0
1
CAPDAT(TIMER_CCAP0[23:0]) data is ready for read
#1
CAPR2F
Capture Rising Edge 2 Flag\nSecond rising edge already captured, this bit will be set to 1.\nNote: This bit is cleared by hardware automatically when writing 1 to this bit.
10
1
read-write
0
None
#0
1
CAPDAT(TIMER_CCAP2[23:0]) data is ready for read
#1
CCAPEN
Continuous Capture Enable Bit\nThis bit is to be enabled the continuous capture function.\nNote: This bit is cleared by hardware automatically when capture operation finish or writing 0 to it
0
1
read-write
0
Continuous capture function Disabled
#0
1
Continuous capture function Enabled
#1
CCAPIEN
Capture Interrupt Enable Bit\n
16
2
read-write
0
Interrupt disable
#00
1
Capture Rising Edge 1 and Falling Edge 1 interrupt enable
#01
2
Capture Rising Edge 1, Falling dege1 and Rising Edge 2 interrupt enable
#10
3
Capture Rising Edge 1, Falling dege1, Rising Edge 2 and Falling Edge 2 interrupt enable
#11
CNTSEL
Capture Timer Selection\nSelect the timer to continuous capture the input signal.\n
2
2
read-write
0
TIMER0
#00
1
TIMER1
#01
2
SysTick
#10
3
Reserved
#11
INV
Input Signal Inverse\nInvert the input signal which be captured.\n
1
1
read-write
0
None
#0
1
Inverse
#1
USCI0
USCI Register Map
USCI
0x0
0x0
0x4
registers
n
0x2C
0xC
registers
n
0x44
0x4
registers
n
0x4C
0x4
registers
n
0x54
0x14
registers
n
0x8
0x4
registers
n
0x8C
0x4
registers
n
USCI_ADDRMSK0
USCI_ADDRMSK0
USCI Device Address Mask Register 0
0x4C
read-write
n
0x0
0x0
ADDRMSK
USCI Device Address Mask\nUSCI support multiple address recognition with one address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
0
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
USCI_BRGEN
USCI_BRGEN
USCI Baud Rate Generator Register
0x8
-1
read-write
n
0x0
0x0
CLKDIV
Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate.
16
10
read-write
DSCNT
Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter\n
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). \n
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). \n
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
External input clock
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.\n
2
2
read-write
0
fSAMP_CLK = fDIV_CLK
#00
1
fSAMP_CLK = fPROT_CLK
#01
2
fSAMP_CLK = fSCLK
#10
3
fSAMP_CLK = fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.\n
4
1
read-write
0
Time measurement counter is Disabled
#0
1
Time measurement counter is Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection\n
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
USCI_CTL
USCI_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
USCI_DEVADDR0
USCI_DEVADDR0
USCI Device Address Register 0
0x44
read-write
n
0x0
0x0
DEVADDR
Device Address\nIn I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].\nNote: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
0
10
read-write
USCI_LINECTL
USCI_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In UART protocol, the length can be configured as 6~13 bits.
8
4
read-write
LSB
LSB First Transmission Selection\n
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
USCI_PROTCTL
USCI_PROTCTL
USCI Protocol Control Register
0x5C
read-write
n
0x0
0x0
AA
Assert Acknowledge Control\n
1
1
read-write
ADDR10EN
Address 10-bit Function Enable\n
4
1
read-write
0
Address match 10 bit function is disabled
#0
1
Address match 10 bit function is enabled
#1
GCFUNC
General Call Function\n
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
PROTEN
I2C Protocol Enable\n
31
1
read-write
0
I2C Protocol disable
#0
1
I2C Protocol enable
#1
PTRG
I2C Protocol Trigger\nWhen a new state is present in the USCI_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.\n
5
1
read-write
0
I2C's stretch disabled and the I2C protocol function will go ahead
#0
1
I2C's stretch active
#1
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
3
1
read-write
STO
I2C STOP Control\n
2
1
read-write
TOCNT
Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (USCI_BRGEN [5]) must be set zero on I2C mode.
16
10
read-write
USCI_PROTIEN
USCI_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
ACKIEN
Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.\n
6
1
read-write
0
The acknowledge interrupt is disabled
#0
1
The acknowledge interrupt is enabled
#1
ARBLOIEN
Arbitration Lost Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected.\n
4
1
read-write
0
The arbitration lost interrupt is disabled
#0
1
The arbitration lost interrupt is enabled
#1
ERRIEN
Error Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (USCI_PROTSTS [16])).\n
5
1
read-write
0
The error interrupt is disabled
#0
1
The error interrupt is enabled
#1
NACKIEN
Non - Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.\n
3
1
read-write
0
The non - acknowledge interrupt is disabled
#0
1
The non - acknowledge interrupt is enabled
#1
STARIEN
Start Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a start condition is detected.\n
1
1
read-write
0
The start condition interrupt is disabled
#0
1
The start condition interrupt is enabled
#1
STORIEN
Stop Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a stop condition is detected.\n
2
1
read-write
0
The stop condition interrupt is disabled
#0
1
The stop condition interrupt is enabled
#1
TOIEN
Time-out Interrupt Enable Control\nIn I2C protocol, this bit enables the interrupt generation in case of a time-out event.\n
0
1
read-write
0
The time-out interrupt is disabled
#0
1
The time-out interrupt is enabled
#1
USCI_PROTSTS
USCI_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
ACKIF
Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit
13
1
read-write
0
An acknowledge has not been received
#0
1
An acknowledge has been received
#1
ARBLOIF
Arbitration Lost Interrupt Flag\nIt is cleared by software writing one into this bit
11
1
read-write
0
An arbitration has not been lost
#0
1
An arbitration has been lost
#1
BUSHANG
Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
18
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is hang-up status for transmission
#1
ERRARBLO
Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
19
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is error arbitration lost status for transmission
#1
ERRIF
Error Interrupt Flag
It is cleared by software writing one into this bit
Note: This bit is set when slave mode, user must write one into STO register to the defined not addressed slave mode.
12
1
read-write
0
An I2C error has not been detected
#0
1
An I2C error has been detected
#1
NACKIF
Non - Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit
10
1
read-write
0
A non - acknowledge has not been received
#0
1
A non - acknowledge has been received
#1
ONBUSY
On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected\n
6
1
read-write
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
SLAREAD
Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
15
1
read-write
0
A slave read request has not been detected
#0
1
A slave read request has been detected
#1
SLASEL
Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
14
1
read-write
0
The device is not selected as slave
#0
1
The device is selected as slave
#1
STARIF
Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.\nIt is cleared by software writing one into this bit
8
1
read-write
0
A start condition has not yet been detected
#0
1
A start condition has been detected
#1
STORIF
Stop Condition Received Interrupt Flag\nIt is cleared by software writing one into this bit
9
1
read-write
0
A stop condition has not yet been detected
#0
1
A stop condition has been detected
#1
TOIF
Time-out Interrupt Flag\nNote: It is cleared by software writing one into this bit
5
1
read-write
0
A time-out interrupt status has not occurred
#0
1
A time-out interrupt status has occurred
#1
WKAKDONE
Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKF is set.
16
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WRSTSWK
Read/Write Status Bit in Address Wakeup Frame\n
17
1
read-write
0
Write command be record on the address match wakeup frame
#0
1
Read command be record on the address match wakeup frame
#1
USCI_RXDAT
USCI_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.\nNote 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]).
0
16
read-only
USCI_TMCTL
USCI_TMCTL
I2C Timing Configure Control Register
0x8C
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control Register\nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode.\n
6
6
read-write
STCTL
Setup Time Configure Control Register\nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode..\n
0
6
read-write
USCI_TXDAT
USCI_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
USCI_WKCTL
USCI_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
WKADDREN
Wake-up Address Match Enable Bit\n
1
1
read-write
0
The chip is woken up according data toggle
#0
1
The chip is woken up according address match
#1
WKEN
Wake-up Enable Bit\n
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
USCI_WKSTS
USCI_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
USCI1
USCI Register Map
USCI
0x0
0x0
0x4
registers
n
0x2C
0xC
registers
n
0x44
0x4
registers
n
0x4C
0x4
registers
n
0x54
0x14
registers
n
0x8
0x4
registers
n
0x8C
0x4
registers
n
USCI_ADDRMSK0
USCI_ADDRMSK0
USCI Device Address Mask Register 0
0x4C
read-write
n
0x0
0x0
ADDRMSK
USCI Device Address Mask\nUSCI support multiple address recognition with one address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
0
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
USCI_BRGEN
USCI_BRGEN
USCI Baud Rate Generator Register
0x8
-1
read-write
n
0x0
0x0
CLKDIV
Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate.
16
10
read-write
DSCNT
Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter\n
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). \n
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). \n
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
External input clock
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.\n
2
2
read-write
0
fSAMP_CLK = fDIV_CLK
#00
1
fSAMP_CLK = fPROT_CLK
#01
2
fSAMP_CLK = fSCLK
#10
3
fSAMP_CLK = fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.\n
4
1
read-write
0
Time measurement counter is Disabled
#0
1
Time measurement counter is Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection\n
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
USCI_CTL
USCI_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
USCI_DEVADDR0
USCI_DEVADDR0
USCI Device Address Register 0
0x44
read-write
n
0x0
0x0
DEVADDR
Device Address\nIn I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].\nNote: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
0
10
read-write
USCI_LINECTL
USCI_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In UART protocol, the length can be configured as 6~13 bits.
8
4
read-write
LSB
LSB First Transmission Selection\n
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
USCI_PROTCTL
USCI_PROTCTL
USCI Protocol Control Register
0x5C
read-write
n
0x0
0x0
AA
Assert Acknowledge Control\n
1
1
read-write
ADDR10EN
Address 10-bit Function Enable\n
4
1
read-write
0
Address match 10 bit function is disabled
#0
1
Address match 10 bit function is enabled
#1
GCFUNC
General Call Function\n
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
PROTEN
I2C Protocol Enable\n
31
1
read-write
0
I2C Protocol disable
#0
1
I2C Protocol enable
#1
PTRG
I2C Protocol Trigger\nWhen a new state is present in the USCI_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.\n
5
1
read-write
0
I2C's stretch disabled and the I2C protocol function will go ahead
#0
1
I2C's stretch active
#1
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
3
1
read-write
STO
I2C STOP Control\n
2
1
read-write
TOCNT
Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (USCI_BRGEN [5]) must be set zero on I2C mode.
16
10
read-write
USCI_PROTIEN
USCI_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
ACKIEN
Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.\n
6
1
read-write
0
The acknowledge interrupt is disabled
#0
1
The acknowledge interrupt is enabled
#1
ARBLOIEN
Arbitration Lost Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected.\n
4
1
read-write
0
The arbitration lost interrupt is disabled
#0
1
The arbitration lost interrupt is enabled
#1
ERRIEN
Error Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (USCI_PROTSTS [16])).\n
5
1
read-write
0
The error interrupt is disabled
#0
1
The error interrupt is enabled
#1
NACKIEN
Non - Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.\n
3
1
read-write
0
The non - acknowledge interrupt is disabled
#0
1
The non - acknowledge interrupt is enabled
#1
STARIEN
Start Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a start condition is detected.\n
1
1
read-write
0
The start condition interrupt is disabled
#0
1
The start condition interrupt is enabled
#1
STORIEN
Stop Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a stop condition is detected.\n
2
1
read-write
0
The stop condition interrupt is disabled
#0
1
The stop condition interrupt is enabled
#1
TOIEN
Time-out Interrupt Enable Control\nIn I2C protocol, this bit enables the interrupt generation in case of a time-out event.\n
0
1
read-write
0
The time-out interrupt is disabled
#0
1
The time-out interrupt is enabled
#1
USCI_PROTSTS
USCI_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
ACKIF
Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit
13
1
read-write
0
An acknowledge has not been received
#0
1
An acknowledge has been received
#1
ARBLOIF
Arbitration Lost Interrupt Flag\nIt is cleared by software writing one into this bit
11
1
read-write
0
An arbitration has not been lost
#0
1
An arbitration has been lost
#1
BUSHANG
Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
18
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is hang-up status for transmission
#1
ERRARBLO
Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
19
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is error arbitration lost status for transmission
#1
ERRIF
Error Interrupt Flag
It is cleared by software writing one into this bit
Note: This bit is set when slave mode, user must write one into STO register to the defined not addressed slave mode.
12
1
read-write
0
An I2C error has not been detected
#0
1
An I2C error has been detected
#1
NACKIF
Non - Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit
10
1
read-write
0
A non - acknowledge has not been received
#0
1
A non - acknowledge has been received
#1
ONBUSY
On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected\n
6
1
read-write
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
SLAREAD
Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
15
1
read-write
0
A slave read request has not been detected
#0
1
A slave read request has been detected
#1
SLASEL
Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
14
1
read-write
0
The device is not selected as slave
#0
1
The device is selected as slave
#1
STARIF
Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.\nIt is cleared by software writing one into this bit
8
1
read-write
0
A start condition has not yet been detected
#0
1
A start condition has been detected
#1
STORIF
Stop Condition Received Interrupt Flag\nIt is cleared by software writing one into this bit
9
1
read-write
0
A stop condition has not yet been detected
#0
1
A stop condition has been detected
#1
TOIF
Time-out Interrupt Flag\nNote: It is cleared by software writing one into this bit
5
1
read-write
0
A time-out interrupt status has not occurred
#0
1
A time-out interrupt status has occurred
#1
WKAKDONE
Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKF is set.
16
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WRSTSWK
Read/Write Status Bit in Address Wakeup Frame\n
17
1
read-write
0
Write command be record on the address match wakeup frame
#0
1
Read command be record on the address match wakeup frame
#1
USCI_RXDAT
USCI_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.\nNote 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]).
0
16
read-only
USCI_TMCTL
USCI_TMCTL
I2C Timing Configure Control Register
0x8C
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control Register\nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode.\n
6
6
read-write
STCTL
Setup Time Configure Control Register\nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode..\n
0
6
read-write
USCI_TXDAT
USCI_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
USCI_WKCTL
USCI_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
WKADDREN
Wake-up Address Match Enable Bit\n
1
1
read-write
0
The chip is woken up according data toggle
#0
1
The chip is woken up according address match
#1
WKEN
Wake-up Enable Bit\n
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
USCI_WKSTS
USCI_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WDT
WDT Register Map
WDT
0x0
0x0
0x4
registers
n
CTL
WDT_CTL
Watchdog Timer Control Register
0x0
-1
read-write
n
0x0
0x0
ICEDEBUG
ICE Debug Mode Acknowledge Disable Control (Write Protect)\nWDT up counter will keep going no matter CPU is hanging by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects WDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
IF
Watchdog Timer Time-out Interrupt Flag\nThis bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it.
3
1
read-write
0
WDT time-out interrupt did not occur
#0
1
WDT time-out interrupt occurred
#1
INTEN
Watchdog Timer Time-out Interrupt Enable Control (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.\n
6
1
read-write
0
WDT time-out interrupt Disabled
#0
1
WDT time-out interrupt Enabled
#1
RSTCNT
Reset Watchdog Timer Up Counter (Write Protect)\nNote: This bit will be automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Reset the internal 18-bit WDT up counter value
#1
RSTEN
Watchdog Timer Time-out Reset Enable Control (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period (1024 * TWDT) expires.\n
1
1
read-write
0
WDT time-out reset function Disabled
#0
1
WDT time-out reset function Enabled
#1
RSTF
Watchdog Timer Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
2
1
read-write
0
WDT time-out reset did not occur
#0
1
WDT time-out reset occurred
#1
TOUTSEL
Watchdog Timer Interval Selection\nThese three bits select the time-out interval for the Watchdog Timer.\n
8
3
read-write
0
24 * TWDT
#000
1
26 * TWDT
#001
2
28 * TWDT
#010
3
210 * TWDT
#011
4
212 * TWDT
#100
5
214 * TWDT
#101
6
216 * TWDT
#110
7
218 * TWDT
#111
WDTEN
Watchdog Timer Enable Control (Write Protect)\n
7
1
read-write
0
WDT Disabled. (This action will reset the internal up counter value.)
#0
1
WDT Enabled
#1
WKEN
Watchdog Timer Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1, while IF is generated to 1 and INTEN enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
4
1
read-write
0
Wake-up trigger event Disabled if WDT time-out interrupt signal generated
#0
1
Wake-up trigger event Enabled if WDT time-out interrupt signal generated
#1
WKF
Watchdog Timer Time-out Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of WDT.\nNote: This bit is cleared by writing 1 to it.
5
1
read-write
0
WDT does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated
#1