nuvoTon
NUC029AN_v1
2024.04.28
NUC029AN_v1 SVD file
8
32
ACMPA
ACMP Register Map
ACMP
0x0
0x0
0xC
registers
n
CMPCR0
CMPCR0
Comparator Control Register 0
0x0
read-write
n
0x0
0x0
CMPCN
Comparator negative input selection
4
1
read-write
0
The ACMPx_N, x=0, 1, 2 or 3, is selected as the source of negative comparator input
#0
1
The internal band-gap reference voltage is selected as the source of negative comparator input
#1
CMPEN
Comparator Enable\nComparator output needs to wait 2 us stable time after CMPEN is set.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CMPIE
Comparator Interrupt Enable
1
1
read-write
0
Interrupt function Disabled
#0
1
Interrupt function Enabled
#1
CMP_HYSEN
Comparator Hysteresis Enable
2
1
read-write
0
Hysteresis function Disabled (Default)
#0
1
Hysteresis function Enabled. The typical range is 20mV
#1
CMPCR1
CMPCR1
Comparator Control Register 1
0x4
read-write
n
0x0
0x0
CMPSR
CMPSR
Comparator Status Register
0x8
read-write
n
0x0
0x0
ACMPB
ACMP Register Map
ACMP
0x0
0x0
0xC
registers
n
CMPCR0
CMPCR0
Comparator Control Register 0
0x0
read-write
n
0x0
0x0
CMPCN
Comparator negative input selection
4
1
read-write
0
The ACMPx_N, x=0, 1, 2 or 3, is selected as the source of negative comparator input
#0
1
The internal band-gap reference voltage is selected as the source of negative comparator input
#1
CMPEN
Comparator Enable\nComparator output needs to wait 2 us stable time after CMPEN is set.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CMPIE
Comparator Interrupt Enable
1
1
read-write
0
Interrupt function Disabled
#0
1
Interrupt function Enabled
#1
CMP_HYSEN
Comparator Hysteresis Enable
2
1
read-write
0
Hysteresis function Disabled (Default)
#0
1
Hysteresis function Enabled. The typical range is 20mV
#1
CMPCR1
CMPCR1
Comparator Control Register 1
0x4
read-write
n
0x0
0x0
CMPSR
CMPSR
Comparator Status Register
0x8
read-write
n
0x0
0x0
ADC
ADC Register Map
ADC
0x0
0x0
0x30
registers
n
0x44
0x4
registers
n
ADCHER
ADCHER
ADC Channel Enable Register
0x24
read-write
n
0x0
0x0
CHEN0
Analog Input Channel 0 Enable
0
1
read-write
0
Disable
#0
1
Enable
#1
CHEN1
Analog Input Channel 1 Enable
1
1
read-write
0
Disable
#0
1
Enable
#1
CHEN2
Analog Input Channel 2 Enable
2
1
read-write
0
Disable
#0
1
Enable
#1
CHEN3
Analog Input Channel 3 Enable
3
1
read-write
0
Disable
#0
1
Enable
#1
CHEN4
Analog Input Channel 4 Enable
4
1
read-write
0
Disable
#0
1
Enable
#1
CHEN5
Analog Input Channel 5 Enable
5
1
read-write
0
Disable
#0
1
Enable
#1
CHEN6
Analog Input Channel 6 Enable
6
1
read-write
0
Disable
#0
1
Enable
#1
CHEN7
Analog Input Channel 7 Enable
7
1
read-write
0
Disable
#0
1
Enable
#1
PRESEL
Analog Input Channel 7 select\nNote:\nWhen software select the band-gap voltage as the analog input source of ADC channel 7, ADC clock rate needs to be limited to lower than 300 KHz.
8
2
read-write
0
External Analog Input
#00
1
Internal Bandgap voltage
#01
2
Internal temperature sensor
#10
3
Reserved
#11
ADCMPR0
ADCMPR0
ADC Compare Register 0
0x28
read-write
n
0x0
0x0
CMPCH
Compare Channel Selection
3
3
read-write
0
Channel 0 conversion result is selected to be compared
#000
1
Channel 1 conversion result is selected to be compared
#001
2
Channel 2 conversion result is selected to be compared
#010
3
Channel 3 conversion result is selected to be compared
#011
4
Channel 4 conversion result is selected to be compared
#100
5
Channel 5 conversion result is selected to be compared
#101
6
Channel 6 conversion result is selected to be compared
#110
7
Channel 7 conversion result is selected to be compared
#111
CMPCOND
Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
2
1
read-write
0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one
#0
1
Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one
#1
CMPD
Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel. \nWhen DMOF bit is set to 0, ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format.\nWhen DMOF bit is set to 1, ADC comparator compares CMPD with conversion result with 2'complement format. CMPD should be filled in 2'complement format.
16
12
read-write
CMPEN
Compare Enable\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register.
0
1
read-write
0
Disable compare function
#0
1
Enable compare function
#1
CMPIE
Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Disable compare function interrupt
#0
1
Enable compare function interrupt
#1
CMPMATCNT
Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
8
4
read-write
ADCMPR1
ADCMPR1
ADC Compare Register 1
0x2C
read-write
n
0x0
0x0
ADCR
ADCR
ADC Control Register
0x20
read-write
n
0x0
0x0
ADEN
A/D Converter Enable\nBefore starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
0
1
read-write
0
Disable
#0
1
Enable
#1
ADIE
A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.
1
1
read-write
0
Disable A/D interrupt function
#0
1
Enable A/D interrupt function
#1
ADMD
A/D Converter Operation Mode
When changing the operation mode, software should disable ADST bit firstly.
Note: In Burst Mode, the A/D result data always at Data Register 0.
2
2
read-write
0
Single conversion
#00
1
Burst conversion
#01
2
Single-cycle scan
#10
3
Continuous scan
#11
ADST
A/D Conversion Start\nADST bit can be set to 1 from two sources: software and external pin STADC. ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan and burst modes, A/D conversion is continuously performed until software write 0 to this bit or chip reset.
11
1
read-write
0
Conversion stopped and A/D converter enter idle state
#0
1
Conversion start
#1
DIFFEN
Differential Input Mode Enable
10
1
read-write
0
single-end analog input mode
#0
1
differential analog input mode
#1
DMOF
A/D differential input Mode Output Format
31
1
read-write
0
A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format
#0
1
A/D Conversion result will be filled in RSLT at ADDRx registers with 2'complement format
#1
TRGCOND
External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.
6
2
read-write
0
Low level
#00
1
High level
#01
2
Falling edge
#10
3
Rising edge
#11
TRGEN
External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin or PWM trigger.\nADC external trigger function is only supported in single-cycle scan mode.
8
1
read-write
0
Disable
#0
1
Enable
#1
TRGS
Hardware Trigger Source\nSoftware should disable TRGEN and ADST before change TRGS. \nIn hardware trigger mode, the ADST bit is set by the external trigger from STADC.
4
2
read-write
0
A/D conversion is started by external STADC pin
#00
3
A/D conversion is started by PWM trigger
#11
ADDR0
ADDR0
ADC Data Register 0
0x0
read-only
n
0x0
0x0
OVERRUN
Over Run Flag (Read Only)\nIf converted data in RSLT has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after ADDR register is read.
16
1
read-only
0
Data in RSLT is recent conversion result
#0
1
Data in RSLT is overwrite
#1
RSLT
A/D Conversion Result\nThis field contains conversion result of ADC.
0
16
read-only
VALID
Valid Flag \nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit
17
1
read-only
0
Data in RSLT bits is not valid
#0
1
Data in RSLT bits is valid
#1
ADDR1
ADDR1
ADC Data Register 1
0x4
read-write
n
0x0
0x0
ADDR2
ADDR2
ADC Data Register 2
0x8
read-write
n
0x0
0x0
ADDR3
ADDR3
ADC Data Register 3
0xC
read-write
n
0x0
0x0
ADDR4
ADDR4
ADC Data Register 4
0x10
read-write
n
0x0
0x0
ADDR5
ADDR5
ADC Data Register 5
0x14
read-write
n
0x0
0x0
ADDR6
ADDR6
ADC Data Register 6
0x18
read-write
n
0x0
0x0
ADDR7
ADDR7
ADC Data Register 7
0x1C
read-write
n
0x0
0x0
ADSR
ADSR
ADC Status Register
0x30
read-write
n
0x0
0x0
ADF
A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these three conditions:\nWhen A/D conversion ends in single mode\nWhen A/D conversion ends on all specified channels in scan mode.\nWhen more than 4 samples in FIFO in Burst mode.\nThis flag can be cleared by writing 1 to self.
0
1
read-write
BUSY
BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.\nIt is read only.
3
1
read-write
0
A/D converter is in idle state
#0
1
A/D converter is busy at conversion
#1
CHANNEL
Current Conversion Channel\nIt is read only.
4
3
read-write
CMPF0
Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.
1
1
read-write
0
Conversion result in ADDR does not meet ADCMPR0 setting
#0
1
Conversion result in ADDR meets ADCMPR0setting
#1
CMPF1
Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.
2
1
read-write
0
Conversion result in ADDR does not meet ADCMPR1 setting
#0
1
Conversion result in ADDR meets ADCMPR1 setting
#1
OVERRUN
Over Run flag (Read Only)\nIt is a mirror to OVERRUN bit in ADDRx\nWhen ADC in Burst Mode, and the FIFO is overrun, OVERRUN[7:0] will all set to 1.
16
8
read-only
VALID
Data Valid flag (Read Only)\nIt is a mirror of VALID bit in ADDRx\nWhen ADC in Burst Mode, and the FIFO is valid, VALID[7:0] will all set to 1.
8
8
read-only
ADTDCR
ADTDCR
ADC Trigger Delay Control Register
0x44
read-write
n
0x0
0x0
PTDT
PWM Trigger Delay Time\nSet this field will delay ADC start conversion time after PWM trigger is coming.\nPWM trigger delay time is (4 * PTDT) * system clock
0
8
read-write
CLK
CLK Register Map
CLK
0x0
0x0
0x28
registers
n
AHBCLK
AHBCLK
AHB Devices Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
DIV_EN
Hardware Divider Controller Clock Enable Control
4
1
read-write
0
Hardware Divider engine clock Disabled
#0
1
Hardware Divider engine clock Enabled
#1
EBI_EN
EBI Controller Clock Enable Control.
3
1
read-write
0
Disable the EBI controller clock
#0
1
Enable the EBI controller clock
#1
ISP_EN
Flash ISP Controller Clock Enable Control.
2
1
read-write
0
To disable the Flash ISP controller clock
#0
1
To enable the Flash ISP controller clock
#1
APBCLK
APBCLK
APB Devices Clock Enable Control Register
0x8
read-write
n
0x0
0x0
ACMPA_EN
Analog Comparator A Clock Enable
30
1
read-write
0
Disable the Analog Comparator A Clock
#0
1
Enable the Analog Comparator A Clock
#1
ACMPB_EN
Analog Comparator B Clock Enable
31
1
read-write
0
Disable the Analog Comparator B Clock
#0
1
Enable the Analog Comparator B Clock
#1
ADC_EN
Analog-Digital-Converter (ADC) Clock Enable
28
1
read-write
0
Disable ADC clock
#0
1
Enable ADC clock
#1
FDIV_EN
Clock Divider Clock Enable
6
1
read-write
0
Disable FDIV Clock
#0
1
Enable FDIV Clock
#1
I2C1_EN
I2C1 Clock Enable
9
1
read-write
0
Disable I2C1 Clock
#0
1
Enable I2C1 Clock
#1
I2C_EN
I2C0 Clock Enable
8
1
read-write
0
Disable I2C0 Clock
#0
1
Enable I2C0 Clock
#1
PWM01_EN
PWM_01 Clock Enable
20
1
read-write
0
Disable PWM01 clock
#0
1
Enable PWM01 clock
#1
PWM23_EN
PWM_23 Clock Enable
21
1
read-write
0
Disable PWM23 clock
#0
1
Enable PWM23 clock
#1
PWM45_EN
PWM_45 Clock Enable
22
1
read-write
0
Disable PWM45 clock
#0
1
Enable PWM45 clock
#1
PWM67_EN
PWM_67 Clock Enable
23
1
read-write
0
Disable PWM67 clock
#0
1
Enable PWM67 clock
#1
SPI0_EN
SPI0 Clock Enable
12
1
read-write
0
Disable SPI0 Clock
#0
1
Enable SPI0 Clock
#1
SPI1_EN
SPI1 Clock Enable
13
1
read-write
0
Disable SPI1 Clock
#0
1
Enable SPI1 Clock
#1
TMR0_EN
Timer0 Clock Enable
2
1
read-write
0
Disable Timer0 Clock
#0
1
Enable Timer0 Clock
#1
TMR1_EN
Timer1 Clock Enable
3
1
read-write
0
Disable Timer1 Clock
#0
1
Enable Timer1 Clock
#1
TMR2_EN
Timer2 Clock Enable
4
1
read-write
0
Disable Timer2 Clock
#0
1
Enable Timer2 Clock
#1
TMR3_EN
Timer3 Clock Enable
5
1
read-write
0
Disable Timer3 Clock
#0
1
Enable Timer3 Clock
#1
UART0_EN
UART0 Clock Enable
16
1
read-write
0
Disable UART0 clock
#0
1
Enable UART0 clock
#1
UART1_EN
UART1 Clock Enable
17
1
read-write
0
Disable UART1 clock
#0
1
Enable UART1 clock
#1
WDT_EN
Watchdog Timer Clock Enable (write-protected)
0
1
read-write
0
Disable Watchdog Timer Clock
#0
1
Enable Watchdog Timer Clock
#1
CLKDIV
CLKDIV
Clock Divider Number Register
0x18
read-write
n
0x0
0x0
ADC_N
ADC clock divide number from ADC clock source
16
8
read-write
HCLK_N
HCLK clock divide number from HCLK clock source
0
4
read-write
UART_N
UART clock divide number from UART clock source
8
4
read-write
CLKSEL0
CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLK_S
HCLK Clock Source Select (Write-protection Bits)
Before clock switching, the related clock sources (both pre-select and new-select) must be turn on
The 3-bit default value is reloaded from the value of CFOSC (CONFIG [26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.
These bits are protected bit. It means programming them needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
3
read-write
0
Clock source from external 4~24 MHz high speed crystal oscillator clock
#000
1
reserved
#001
2
Clock source from PLL clock
#010
3
Clock source from internal 10 kHz low speed oscillator clock
#011
7
Clock source from internal 22.1184 MHz high speed oscillator clock
#111
STCLK_S
Cortex-M0 SysTick Clock Source Select (write-protected)
3
3
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#000
1
reserved
#001
2
Clock source from external 4~24 MHz high speed crystal clock/2
#010
3
Clock source from HCLK/2
#011
7
Clock source from internal 22.1184 MHz high speed oscillator clock/2
#111
CLKSEL1
CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
ADC_S
ADC clock source select
2
2
read-write
0
Clock source from external crystal clock (4 ~ 24MHz)
#00
1
Clock source from PLL clock
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz oscillator clock
#11
PWM01_S
PWM0 and PWM1 clock source select.\nPWM0 and PWM1 uses the same Engine clock source, both of them use the same pre-scalar
28
2
read-write
0
Clock source from external crystal clock ( 4 ~ 24MHz)
#00
1
Clock source from internal 10 kHz low speed oscillator clock
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz oscillator clock
#11
PWM23_S
PWM2 and PWM3 clock source select.\nPWM2 and PWM3 uses the same Engine clock source, both of them use the same pre-scalar
30
2
read-write
0
Clock source from external crystal clock (4 ~ 24MHz)
#00
1
Clock source from internal 10 kHz low speed oscillator clock
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz oscillator clock
#11
SPI0_S
SPI0 clock source select
4
1
read-write
0
Clock source from PLL clock
#0
1
Clock source from HCLK
#1
SPI1_S
SPI1 clock source select
5
1
read-write
0
Clock source from PLL clock
#0
1
Clock source from HCLK
#1
TMR0_S
TIMER0 clock source select.
8
3
read-write
0
Clock source from external crystal clock (4 ~ 24 MHz)
#000
2
Clock source from HCLK
#010
3
Clock source from external trigger T0
#011
5
Clock source from internal 10 kHz low speed oscillator clock
#101
7
Clock source from internal 22.1184 MHz oscillator clock
#111
TMR1_S
TIMER1 clock source select.
12
3
read-write
0
Clock source from external crystal clock (4 ~ 24MHz)
#000
2
Clock source from HCLK
#010
3
Clock source from external trigger T1
#011
5
Clock source from internal 10 kHz low speed oscillator clock
#101
7
Clock source from internal 22.1184 MHz oscillator clock
#111
TMR2_S
TIMER2 clock source select.
16
3
read-write
0
Clock source from external crystal clock (4 ~ 24MHz)
#000
2
Clock source from HCLK
#010
3
Clock source from external trigger T2
#011
5
Clock source from internal 10 kHz low speed oscillator clock
#101
7
Clock source from internal 22.1184 MHz oscillator clock
#111
TMR3_S
TIMER3 clock source select.
20
3
read-write
0
Clock source from external crystal clock (4 ~ 24MHz)
#000
2
Clock source from HCLK
#010
3
Clock source from external trigger T3
#011
5
Clock source from internal 10 kHz low speed oscillator clock
#101
7
Clock source from internal 22.1184 MHz oscillator clock
#111
UART_S
UART clock source select.
24
2
read-write
0
Clock source from external crystal clock (4 ~ 24MHz)
#00
1
Clock source from PLL clock
#01
2
Reserved
#10
3
Clock source from internal 22.1184 MHz oscillator clock
#11
WDT_S
WDT clock source select (write-protected)
0
2
read-write
0
Reserved
#00
1
Reserved
#01
2
Clock source from HCLK/2048 clock
#10
3
Clock source from internal 10 kHz oscillator clock
#11
CLKSEL2
CLKSEL2
Clock Source Select Control Register 2
0x1C
-1
read-write
n
0x0
0x0
FRQDIV_S
Clock Divider Clock Source Select
2
2
read-write
0
Clock source from external crystal clock (4 ~ 24 MHz)
#00
1
Reserved
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz oscillator clock
#11
PWM45_S
PWM4 and PWM5 clock source select\nPWM4 and PWM5 used the same Engine clock source, both of them use the same pre-scalar
4
2
read-write
0
Clock source from external crystal clock (4 ~ 24 MHz)
#00
1
Clock source from internal 10 kHz low speed oscillator clock
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz oscillator clock
#11
PWM67_S
PWM6 and PWM7 clock source select\nPWM6 and PWM7 used the same Engine clock source, both of them use the same pre-scalar
6
2
read-write
0
Clock source from external crystal clock (4 ~ 24MHz)
#00
1
Clock source from internal 10 kHz low speed oscillator clock
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz oscillator clock
#11
WWDT_S
Window Watchdog Timer clock source select
16
2
read-write
2
Clock source from HCLK/2048 clock
#10
3
Clock source from internal 10 kHz low speed oscillator clock
#11
CLKSTATUS
CLKSTATUS
Clock status monitor Register
0xC
read-write
n
0x0
0x0
CLK_SW_FAIL
Clock Switching Fail Flag\nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nWrite 1 to clear the bit to 0.
7
1
read-write
0
Clock switching success
#0
1
Clock switching failed
#1
OSC10K_STB
OSC10K clock source stable flag (Read Only)
3
1
read-only
0
OSC10K clock is not stable or disable
#0
1
OSC10K clock is stable
#1
OSC22M_STB
OSC22M (Internal 22.1184 MHz) clock source stable flag (Read Only)
4
1
read-only
0
OSC22M clock is not stable or disable
#0
1
OSC22M clock is stable
#1
PLL_STB
PLL clock source stable flag (Read Only)
2
1
read-only
0
PLL clock is not stable or disable
#0
1
PLL clock is stable
#1
XTL12M_STB
External Crystal clock source stable flag (Read Only)
0
1
read-only
0
External Crystal clock is not stable or disable
#0
1
External Crystal clock is stable
#1
FRQDIV
FRQDIV
Frequency Divider Control Register
0x24
read-write
n
0x0
0x0
DIVIDER_EN
Frequency Divider Enable Bit
4
1
read-write
0
Disable Frequency Divider
#0
1
Enable Frequency Divider
#1
FSEL
Divider Output Frequency Selection Bits\nThe formula of output frequency is\nFin is the input clock frequency\nFout is the frequency of divider output clock\nN is the 4-bit value of FSEL[3:0].
0
4
read-write
PLLCON
PLLCON
PLL Control Register
0x20
-1
read-write
n
0x0
0x0
BP
PLL Bypass Control
17
1
read-write
0
PLL is in Normal mode (default)
#0
1
PLL clock output is same as PLL source clock input
#1
FB_DV
PLL Feedback Divider Control
0
9
read-write
IN_DV
PLL Input Divider Control
9
5
read-write
OE
PLL OE (FOUT enable) pin Control
18
1
read-write
0
PLL FOUT enable
#0
1
PLL FOUT is fixed low
#1
OUT_DV
PLL Output Divider Control
14
2
read-write
PD
Power down Mode\nIf the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too.
16
1
read-write
0
PLL is in Normal mode
#0
1
PLL is in Power-down mode (default)
#1
PLL_SRC
PLL Source Clock Select
19
1
read-write
0
PLL source clock from external crystal (4 ~ 24 MHz)
#0
1
PLL source clock from 22.1184 MHz oscillator
#1
PWRCON
PWRCON
System Power Down Control Register
0x0
-1
read-write
n
0x0
0x0
OSC10K_EN
Internal 10 kHz Oscillator enable (write-protected)
3
1
read-write
0
10 kHz Oscillation disable
#0
1
10 kHz Oscillation enable
#1
OSC22M_EN
Internal 22.1184 MHz Oscillator enable (write-protected)
2
1
read-write
0
22.1184 MHz Oscillation disable
#0
1
22.1184 MHz Oscillation enable
#1
PD_WAIT_CPU
This bit control the power down entry condition (write-protected)
8
1
read-write
0
Chip entry power down mode when the PWR_DOWN_EN bit is set to 1
#0
1
Chip enter power down mode when the both PWR_DOWN_EN bit is set to 1 and CPU run WFI instruction
#1
PD_WU_DLY
Enable the wake up delay counter. (write-protected)
When the chip wakes up from power down mode, the clock control will delay certain clock cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip work at external crystal (4 ~ 24MHz), and 256 clock cycles when chip work at 22.1184 MHz oscillator.
4
1
read-write
0
Disable clock cycles delay
#0
1
Enable clock cycles delay
#1
PD_WU_INT_EN
Power down mode wake Up Interrupt Enable (write-protected)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
5
1
read-write
0
Disable
#0
1
Enable
#1
PD_WU_STS
Power down mode wake up interrupt status
Set by power down wake up event , it indicates that resume from power down mode
The flag is set if the GPIO, UART, WDT, ACMPA, ACMPB , I2C, TIMER, or BOD wakeup occurred
Write 1 to clear the bit to zero.
Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
6
1
read-write
PWR_DOWN_EN
System power down enable bit (write-protected)
When CPU sets this bit 1 the chip power down mode is enabled, and chip power-down behavior will depends on the PD_WAIT_CPU bit
(a) If the PD_WAIT_CPU is 0 , then the chip enters power down mode immediately after the PWR_DOWN_EN bit set.
(b) if the PD_WAIT_CPU is 1 , then the chip keeps active till the CPU sleep mode is also active and then the chip enters power down mode
When chip wakes up from power down mode, this bit is auto cleared. Users need to set this bit again for next power down.
When in power down mode, external crystal (4~ 24MHz) and the 22.1184 MHz OSC will be disabled in this mode, but the 10 kHz OSC is not controlled by power down mode.
When in power down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by power down mode, if the peripheral clock source is from 10 kHz oscillator.
7
1
read-write
0
Chip operate in normal mode or CPU in idle mode (sleep mode) because of WFI command
#0
1
Chip enter the power down mode instant or wait CPU sleep command WFI
#1
XTL12M_EN
External Crystal Oscillator enable (write-protected)
The bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external crystal, the bit is automatically set to 1
0
1
read-write
0
Crystal oscillation disable
#0
1
Crystal oscillation enable
#1
DIV
DIV Register Map
DIV
0x0
0x0
0x14
registers
n
DIVIDEND
DIVIDEND
Dividend Source Register
0x0
read-write
n
0x0
0x0
Dividend
Dividend Source.\nThis register is given the dividend of divider before calculation starts.
0
32
read-write
DIVISOR
DIVISOR
Divisor Source Resister
0x4
-1
read-write
n
0x0
0x0
Divisor
Divisor Source.\nThis register is given the divisor of divider before calculation starts.\nNote: when this register is written, hardware divider will start calculate
0
16
read-write
DIVQUO
DIVQUO
Quotient Result Resister
0x8
read-write
n
0x0
0x0
Quotient
Quotient Result\nThis register holds the quotient result of divider after calculation complete.
0
32
read-write
DIVREM
DIVREM
Reminder Result Register
0xC
read-write
n
0x0
0x0
Reminder
Reminder Result\nThis register holds the reminder result of divider after calculation complete.
0
16
read-write
DIVSTS
DIVSTS
Divider Status Register
0x10
-1
read-write
n
0x0
0x0
DIV0
Divisor zero warning.\n1: The divisor is 0.\n0: The divisor is not 0.\nThis register is read only.
1
1
read-write
DIV_FINISH
Divider operation finished.\nThis register is read only.
0
1
read-write
0
The divider calculation is not yet
#0
1
The divider calculation is finished
#1
EBI_CTL
EBI Register Map
EBI
0x0
0x0
0x8
registers
n
EBICON
EBICON
External Bus Interface General Control Register
0x0
read-write
n
0x0
0x0
ExtBW16
EBI data width 16 bit\nThis bit defines if the data bus is 8-bit or 16-bit.
1
1
read-write
0
EBI data width is 8 bit
#0
1
EBI data width is 16 bit
#1
ExtEN
EBI Enable\nThis bit is the functional enable bit for EBI.
0
1
read-write
0
EBI function is disabled
#0
1
EBI function is enabled
#1
ExttALE
Expand Time of ALE\nThe ALE width (tALE) to latch the address can be controlled by ExttALE.
16
3
read-write
MCLKDIV
External Output Clock Divider
8
3
read-write
EXTIME
EXTIME
External Bus Interface Timing Control Register
0x4
read-write
n
0x0
0x0
ExtIR2R
Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read, idle state is inserted and nCS return to high if ExtIR2R is not zero.
24
4
read-write
ExtIW2X
Idle State Cycle After Write\nWhen write action is finish, idle state is inserted and nCS return to high if ExtIW2X is not zero.
12
4
read-write
ExttACC
EBI Data Access Time\nExttACC define data access time (tACC).
3
5
read-write
ExttAHD
EBI Data Access Hold Time\nExttAHD define data access hold time (tAHD).
8
3
read-write
FMC
FMC Register Map
FMC
0x0
0x0
0x1C
registers
n
DFBADR
DFBADR
Data Flash Base Address
0x14
-1
read-only
n
0x0
0x0
DFBADR
Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nFor 8/16/32/64KB flash memory device, the data flash size is 4KB and it start address is fixed at 0x0001_F000 by hardware internally.
0
32
read-only
FATCON
FATCON
Flash Access Time Control Register
0x18
read-write
n
0x0
0x0
LFOM
Low Frequency Optimization Mode (write-protected)\nWhen chip operation frequency is lower than 25 MHz, chip can work more efficiently by setting this bit to 1
4
1
read-write
0
Disable low frequency optimization mode
#0
1
Enable low frequency optimization mode
#1
ISPADR
ISPADR
ISP Address Register
0x4
read-write
n
0x0
0x0
ISPADR
ISP Address \nNuMicro NUC029 series equips with a 16k x 32 embedded flash, it supports word program only. ISPADR[1:0] must be kept 2'b00 for ISP operation.
0
32
read-write
ISPCMD
ISPCMD
ISP Command Register
0xC
read-write
n
0x0
0x0
ISPCMD
ISP Command
0
6
read-write
ISPCON
ISPCON
ISP Control Register
0x0
read-write
n
0x0
0x0
APUEN
APROM Update Enable (write-protected)
3
1
read-write
0
APROM can not be updated when the chip runs in APROM
#0
1
APROM can be updated when the chip runs in APROM
#1
BS
Boot Select (write-protected)
Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as MCU booting status flag, which can be used to check where MCU booted from. This bit is initiated with the inversed value of CBS in Config0 after power-on reset It keeps the same value at other reset.
1
1
read-write
0
boot from APROM
#0
1
boot from LDROM
#1
CFGUEN
Config Update Enable (write-protected)
Writing this bit to 1 enables s/w to update Config value by ISP procedure regardless of program code is running in APROM or LDROM.
4
1
read-write
0
Config update disable
#0
1
Config update enable
#1
ISPEN
ISP Enable (write-protected)\nISP function enable bit. Set this bit to enable ISP function.
0
1
read-write
0
Disable ISP function
#0
1
Enable ISP function
#1
ISPFF
ISP Fail Flag (write-protection bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0\n(2) LDROM writes to itself if LDUEN is set to 0\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear.
6
1
read-write
LDUEN
LDROM Update Enable (write-protection bit)\nLDROM update enable bit.
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated
#1
ISPDAT
ISPDAT
ISP Data Register
0x8
read-write
n
0x0
0x0
ISPDAT
ISP Data
Write data to this register before ISP program operation
Read data from this register after ISP read operation
0
32
read-write
ISPTRG
ISPTRG
ISP Trigger Control Register
0x10
read-write
n
0x0
0x0
ISPGO
ISP start trigger(write-protected)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finish.
0
1
read-write
0
ISP done
#0
1
ISP is on going
#1
GCR
GCR Register Map
GCR
0x0
0x0
0x10
registers
n
0x100
0x4
registers
n
0x18
0x8
registers
n
0x24
0x8
registers
n
0x30
0x14
registers
n
BODCR
BODCR
Brown-Out Detector Control Register
0x18
-1
read-write
n
0x0
0x0
BOD_EN
Brown-Out Detector Enable (write-protected)\nThe default value is set by flash controller user configuration register config0 bit[23]
0
1
read-write
0
Brown-Out Detector function is disabled
#0
1
Brown-Out Detector function is enabled
#1
BOD_INTF
Brown-Out Detector Interrupt Flag\nSoftware can write 1 to clear this bit to zero.
4
1
read-write
0
Brown-Out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting
#0
1
When Brown-Out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-Out interrupt is requested if Brown-Out interrupt is enabled
#1
BOD_LPM
Brown-Out Detector Low power Mode (write-protected)\nThe BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
5
1
read-write
0
BOD operate in normal mode (default)
#0
1
Enable the BOD low power mode
#1
BOD_OUT
Brown-Out Detector output status
6
1
read-write
0
Brown-Out Detector output status is 0. It means the detected voltage is higher than BOD_VL setting or BOD_EN is 0
#0
1
Brown-Out Detector output status is 1. It means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled , this bit always responds 0
#1
BOD_RSTEN
Brown-Out Reset Enable (write-protected)\nThe default value is set by flash controller user configuration register config0 bit[20].
3
1
read-write
0
Enable the Brown-Out INTERRUPT function.While the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low)
#0
1
Enable the Brown-Out RESET function. While the Brown-Out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BOD_OUT high)
#1
BOD_VL
Brown-Out Detector Threshold Voltage Selection (write-protected)
1
2
read-write
LVR_EN
Low Voltage Reset Enable (write-protected)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default.
7
1
read-write
0
Disabled Low Voltage Reset function
#0
1
Enabled Low Voltage Reset function - After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable. (Default)
#1
GPIO_2CKn
GPIO_2CKn
GPIO 2CK Strong Pull High Controller Register
0x28
read-write
n
0x0
0x0
GPIO_2CKn
GPIO two clock strong pull high disable
0
1
read-write
0
GPIO two clock strong pull high is enabled if Pxx_DOUT is 0 before reset
#0
1
GPIO two clock strong pull high is disabled if Pxx_DOUT is 0 before reset
#1
IPRSTC1
IPRSTC1
Peripheral Reset Control Register 1
0x8
read-write
n
0x0
0x0
CHIP_RST
CHIP one shot reset (write-protected)
Set this bit will reset the CHIP, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
The CHIP_RST is same as the POR reset , all the chip module is reset and the chip setting from flash are also reload
0
1
read-write
0
Normal
#0
1
Reset CHIP
#1
CPU_RST
CPU kernel one shot reset (write-protected)
Set this bit will reset the Cortex-M0 CPU kernel and Flash memory controller (FMC). This bit will automatically return to 0 after the 2 clock cycles
1
1
read-write
0
Normal
#0
1
Reset CPU
#1
DIV_RST
DIV Controller Reset (write-protection bit)
Set this bit to 1 will generate a reset signal to the DIVIDER. User need to set this bit to 0 to release from the reset state.
This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100
4
1
read-write
0
DIVIDER controller normal operation
#0
1
DIVIDER controller reset
#1
EBI_RST
EBI Controller Reset (write-protected)
Set these bit 1 will generate a reset signal to the EBI. User need to set this bit to 0 to release from the reset state
3
1
read-write
0
EBI controller normal operation
#0
1
EBI controller reset
#1
IPRSTC2
IPRSTC2
Peripheral Reset Control Register 2
0xC
read-write
n
0x0
0x0
ACMPB_RST
Analog Comparator 1 Controller Reset
23
1
read-write
0
Analog Comparator controller 1 normal operation
#0
1
Analog Comparator controller 1 reset
#1
ACMP_RST
Analog Comparator Controller Reset
22
1
read-write
0
Analog Comparator controller normal operation
#0
1
Analog Comparator controller reset
#1
ADC_RST
ADC Controller Reset
28
1
read-write
0
ADC controller normal operation
#0
1
ADC controller reset
#1
GPIO_RST
GPIO (P0~P4) controller Reset
1
1
read-write
0
GPIO controller normal operation
#0
1
GPIO controller reset
#1
I2C1_RST
I2C1 controller Reset
9
1
read-write
0
I2C1 controller normal operation
#0
1
I2C1 controller reset
#1
I2C_RST
I2C0 controller Reset
8
1
read-write
0
I2C0 controller normal operation
#0
1
I2C0 controller reset
#1
PWM03_RST
PWM0~3 controller Reset
20
1
read-write
0
PWM0~3 controller normal operation
#0
1
PWM0~3 controller reset
#1
PWM47_RST
PWM4~7 controller Reset
21
1
read-write
0
PWM4~7 controller normal operation
#0
1
PWM4~7 controller reset
#1
SPI0_RST
SPI0 controller Reset
12
1
read-write
0
SPI0 controller normal operation
#0
1
SPI0 controller reset
#1
SPI1_RST
SPI1 controller Reset
13
1
read-write
0
SPI1 controller normal operation
#0
1
SPI1 controller reset
#1
TMR0_RST
Timer0 controller Reset
2
1
read-write
0
Timer0 controller normal operation
#0
1
Timer0 controller reset
#1
TMR1_RST
Timer1 controller Reset
3
1
read-write
0
Timer1 controller normal operation
#0
1
Timer1 controller reset
#1
TMR2_RST
Timer2 controller Reset
4
1
read-write
0
Timer2 controller normal operation
#0
1
Timer2 controller reset
#1
TMR3_RST
Timer3 controller Reset
5
1
read-write
0
Timer3 controller normal operation
#0
1
Timer3 controller reset
#1
UART0_RST
UART0 controller Reset
16
1
read-write
0
UART0 controller normal operation
#0
1
UART0 controller reset
#1
UART1_RST
UART1 controller Reset
17
1
read-write
0
UART1 controller normal operation
#0
1
UART1 controller reset
#1
P0_MFP
P0_MFP
P0 multiple function and input type control register
0x30
read-write
n
0x0
0x0
P0_ALT0
P0.0 alternate function Selection
8
1
read-write
P0_ALT1
P0.1 alternate function Selection
9
1
read-write
P0_ALT10
P0.0 alternate function Selection1\nThe pin function of P0.0 depends on P0_MFP[0], P0_ALT[0], and P0_ALT1[0].\nRefer to P0_ALT[0] for details descriptions.
24
1
read-write
P0_ALT11
P0.1 alternate function Selection1\nThe pin function of P0.1 depends on P0_MFP[1], P0_ALT[1], and P0_ALT1[1].\nRefer to P0_ALT[1] for details descriptions.
25
1
read-write
P0_ALT2
P0.2 alternate function Selection
10
1
read-write
P0_ALT3
P0.3 alternate function Selection
11
1
read-write
P0_ALT4
P0.4 alternate function Selection
12
1
read-write
P0_ALT5
P0.5 alternate function Selection
13
1
read-write
P0_ALT6
P0.6 alternate function Selection
14
1
read-write
P0_ALT7
P0.7 alternate function Selection
15
1
read-write
P0_MFP
P0 multiple function Selection\nThe pin function of P0 depends on P0_MFP and P0_ALT.\nRefer to P0_ALT for details descriptions.
0
8
read-write
P0_TYPEn
P0[7:0] input Schmitt Trigger function Enable
16
8
read-write
0
Disable P0[7:0] I/O input Schmitt Trigger function
0
1
Enable P0[7:0] I/O input Schmitt Trigger function
1
P1_MFP
P1_MFP
P1 multiple function and input type control register
0x34
read-write
n
0x0
0x0
P1_ALT0
P1.0 alternate function Selection
8
1
read-write
P1_ALT1
P1.1 alternate function Selection
9
1
read-write
P1_ALT2
P1.2 alternate function Selection
10
1
read-write
P1_ALT3
P1.3 alternate function Selection
11
1
read-write
P1_ALT4
P1.4 alternate function Selection
12
1
read-write
P1_ALT5
P1.5 alternate function Selection
13
1
read-write
P1_ALT6
P1.6 alternate function Selection
14
1
read-write
P1_ALT7
P1.7 alternate function Selection
15
1
read-write
P1_MFP
P1 multiple function Selection\nThe pin function of P1 is depending on P1_MFP and P1_ALT.\nRefer to P1_ALT for details descriptions.
0
8
read-write
P1_TYPEn
P1[7:0] input Schmitt Trigger function Enable
16
8
read-write
0
Disable P1[7:0] I/O input Schmitt Trigger function
0
1
Enable P1[7:0] I/O input Schmitt Trigger function
1
P2_MFP
P2_MFP
P2 multiple function and input type control register
0x38
read-write
n
0x0
0x0
P2_ALT0
P2.0 alternate function Selection
8
1
read-write
P2_ALT1
P2.1 alternate function Selection
9
1
read-write
P2_ALT2
P2.2 alternate function Selection
10
1
read-write
P2_ALT3
P2.3 alternate function Selection
11
1
read-write
P2_ALT4
P2.4 alternate function Selection
12
1
read-write
P2_ALT5
P2.5 alternate function Selection
13
1
read-write
P2_ALT6
P2.6 alternate function Selection
14
1
read-write
P2_ALT7
P2.7 alternate function Selection
15
1
read-write
P2_MFP
P2 multiple function Selection\nThe pin function of P2 depends on P2_MFP and P2_ALT.\nRefer to P2_ALT for details descriptions.
0
8
read-write
P2_TYPEn
P2[7:0] input Schmitt Trigger function Enable
16
8
read-write
0
Disable P2[7:0] I/O input Schmitt Trigger function
0
1
Enable P2[7:0] I/O input Schmitt Trigger function
1
P3_MFP
P3_MFP
P3 multiple function and input type control register
0x3C
read-write
n
0x0
0x0
P3_ALT0
P3.0 alternate function Selection
8
1
read-write
P3_ALT1
P3.1 alternate function Selection
9
1
read-write
P3_ALT2
P3.2 alternate function Selection
10
1
read-write
P3_ALT3
P3.3 alternate function Selection
11
1
read-write
P3_ALT4
P3.4 alternate function Selection
12
1
read-write
P3_ALT5
P3.5 alternate function Selection
13
1
read-write
P3_ALT6
P3.6 alternate function Selection
14
1
read-write
P3_ALT7
P3.7 alternate function Selection
15
1
read-write
P3_MFP
P3 multiple function Selection\nThe pin function of P3 is depending on P3_MFP and P3_ALT.\nRefer to P3_ALT for details descriptions.
0
8
read-write
P3_TYPEn
P3[7:0] input Schmitt Trigger function Enable
16
8
read-write
0
Disable P3[7:0] I/O input Schmitt Trigger function
0
1
Enable P3[7:0] I/O input Schmitt Trigger function
1
P4_MFP
P4_MFP
P4 multiple function and input type control register
0x40
-1
read-write
n
0x0
0x0
P4_ALT0
P4.0 alternate function Selection
8
1
read-write
P4_ALT1
P4.1 alternate function Selection
9
1
read-write
P4_ALT2
P4.2 alternate function Selection
10
1
read-write
P4_ALT3
P4.3 alternate function Selection
11
1
read-write
P4_ALT4
P4.4 alternate function Selection
12
1
read-write
P4_ALT5
P4.5 alternate function Selection
13
1
read-write
P4_ALT6
P4.6 alternate function Selection
14
1
read-write
P4_ALT7
P4.7 alternate function Selection
15
1
read-write
P4_MFP
P4 multiple function Selection\nThe pin function of P4 is depending on P4_MFP and P4_ALT.\nRefer to P4_ALT for details descriptions.
0
8
read-write
P4_TYPEn
P4[7:0] input Schmitt Trigger function Enable
16
8
read-write
0
Disable P4[7:0] I/O input Schmitt Trigger function disable
0
1
Enable P4[7:0] I/O input Schmitt Trigger function enable
1
PDID
PDID
Part Device Identification number Register
0x0
-1
read-only
n
0x0
0x0
PDID
Part Device Identification Number\nThis register reflects device part number code. S/W can read this register to identify which device is used. For example, M052LCN PDID code is 0x2000_5200.
0
32
read-only
PORCR
PORCR
Power-On-Reset Controller Register
0x24
read-write
n
0x0
0x0
POR_DIS_CODE
Power-On-Reset enable control (write-protected)\nWhen power on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. If set the POR_DIS_CODE equal to 0x5AA5, the POR reset function will be disabled and the POR function will re-active till the power voltage is lower to set the POR_DIS_CODE to another value or reset by chip other reset function. Include:\n/RESET, Watch dog, LVR reset BOD reset, ICE reset command and the software-chip reset function.
0
16
read-write
REGWRPROT
REGWRPROT
Register Write-Protection Control Register
0x100
read-write
n
0x0
0x0
REGPROTDIS
Register Write-Protected Disable index (Read only)
0
1
read-only
0
Protection is enabled for writing protected registers. Any write to the protected register is ignored
#0
1
Protection is disabled for writing protected registers
#1
REGWRPROT
Register Write-Protected Code (Write Only)
Programming a write-protected register, must remove write-protected function by programming a sequence of value 59h , 16h , 88h to this field.
After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protected registers can be normal written.
0
8
write-only
RSTSRC
RSTSRC
System Reset Source Register
0x4
read-write
n
0x0
0x0
RSTS_BOD
The RSTS_BOD flag is set by the reset signal from the Brown-Out Detector to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
4
1
read-write
0
No reset from BOD
#0
1
The Brown-Out Detector module had issued the reset signal to reset the system
#1
RSTS_CPU
The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).\nSoftware can write 1 to clear this bit to zero.
7
1
read-write
0
No reset from CPU
#0
1
The Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1
#1
RSTS_LVR
The RSTS_LVR flag is set by the reset signal from the Low-Voltage-Reset controller to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
3
1
read-write
0
No reset from LVR
#0
1
The LVR module had issued the reset signal to reset the system
#1
RSTS_MCU
The RSTS_MCU flag is set by the reset signal from the MCU Cortex_M0 kernel to indicate the previous reset source.
This bit is cleared by writing 1 to itself.
5
1
read-write
0
No reset from MCU
#0
1
The MCU Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel
#1
RSTS_POR
The RSTS_POR flag is set by the reset signal , which is from the Power-On Reset (POR) module or bit CHIP_RST (IPRSTC1[0]) is set, to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
0
1
read-write
0
No reset from POR or CHIP_RST
#0
1
The Power-On-Reset (POR) or CHIP_RST had issued the reset signal to reset the system
#1
RSTS_RESET
The RSTS_RESET flag is set by the reset signal from the /RESET pin to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
1
1
read-write
0
No reset from Pin /RESET
#0
1
The Pin /RESET had issued the reset signal to reset the system
#1
RSTS_WDT
The RSTS_WDT flag is set by the reset signal from the Watchdog timer to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
2
1
read-write
0
No reset from Watchdog timer
#0
1
The Watchdog timer had issued the reset signal to reset the system
#1
TEMPCR
TEMPCR
Temperature Sensor Control Register
0x1C
read-write
n
0x0
0x0
VTEMP_EN
Temperature sensor Enable\nThis bit is used to enable/disable temperature sensor function.\nAfter this bit is set to 1, the value of temperature can get from ADC conversion result by ADC channel selecting channel 7 and alternative multiplexer channel selecting temperature sensor. Detail ADC conversion function please reference ADC function chapter.
0
1
read-write
0
Disabled temperature sensor function (default)
#0
1
Enabled temperature sensor function
#1
GP
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
0x100
0x24
registers
n
0x180
0x4
registers
n
0x200
0xA0
registers
n
0x40
0x24
registers
n
0x80
0x24
registers
n
0xC0
0x24
registers
n
DBNCECON
DBNCECON
External Interrupt De-bounce Control
0x180
-1
read-write
n
0x0
0x0
DBCLKSEL
De-bounce sampling cycle selection
0
4
read-write
DBCLKSRC
De-bounce counter clock source select
4
1
read-write
0
De-bounce counter clock source is the HCLK
#0
1
De-bounce counter clock source is the internal 10kHz clock
#1
ICLK_ON
Interru\nIt is recommended to turn off this bit to save system power, if on special application concern.
5
1
read-write
0
Edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1
#0
1
All IO pins edge detection circuit is always active after reset
#1
P00_PDIO
P00_PDIO
GPIO P0.0 Pin Data Input/Output
0x200
read-write
n
0x0
0x0
Pxn_PDIO
GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value
0
1
read-write
0
Set corresponding GPIO pin to low
#0
1
Set corresponding GPIO pin to high
#1
P01_PDIO
P01_PDIO
GPIO P0.1 Pin Data Input/Output
0x204
read-write
n
0x0
0x0
P02_PDIO
P02_PDIO
GPIO P0.2 Pin Data Input/Output
0x208
read-write
n
0x0
0x0
P03_PDIO
P03_PDIO
GPIO P0.3 Pin Data Input/Output
0x20C
read-write
n
0x0
0x0
P04_PDIO
P04_PDIO
GPIO P0.4 Pin Data Input/Output
0x210
read-write
n
0x0
0x0
P05_PDIO
P05_PDIO
GPIO P0.5 Pin Data Input/Output
0x214
read-write
n
0x0
0x0
P06_PDIO
P06_PDIO
GPIO P0.6 Pin Data Input/Output
0x218
read-write
n
0x0
0x0
P07_PDIO
P07_PDIO
GPIO P0.7 Pin Data Input/Output
0x21C
read-write
n
0x0
0x0
P0_DBEN
P0_DBEN
P0 De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
0
1
read-write
0
The bit[n] de-bounce function is disabled
#0
1
The bit[n] de-bounce function is enabled
#1
DBEN1
Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
1
1
read-write
0
The bit[n] de-bounce function is disabled
#0
1
The bit[n] de-bounce function is enabled
#1
DBEN2
Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
2
1
read-write
0
The bit[n] de-bounce function is disabled
#0
1
The bit[n] de-bounce function is enabled
#1
DBEN3
Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
3
1
read-write
0
The bit[n] de-bounce function is disabled
#0
1
The bit[n] de-bounce function is enabled
#1
DBEN4
Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
4
1
read-write
0
The bit[n] de-bounce function is disabled
#0
1
The bit[n] de-bounce function is enabled
#1
DBEN5
Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
5
1
read-write
0
The bit[n] de-bounce function is disabled
#0
1
The bit[n] de-bounce function is enabled
#1
DBEN6
Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
6
1
read-write
0
The bit[n] de-bounce function is disabled
#0
1
The bit[n] de-bounce function is enabled
#1
DBEN7
Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
7
1
read-write
0
The bit[n] de-bounce function is disabled
#0
1
The bit[n] de-bounce function is enabled
#1
P0_DMASK
P0_DMASK
P0 Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT).
0
1
read-write
0
The corresponding Px_DOUT[n] bit can be updated
#0
1
The corresponding Px_DOUT[n] bit is protected
#1
DMASK1
Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT).
1
1
read-write
0
The corresponding Px_DOUT[n] bit can be updated
#0
1
The corresponding Px_DOUT[n] bit is protected
#1
DMASK2
Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT).
2
1
read-write
0
The corresponding Px_DOUT[n] bit can be updated
#0
1
The corresponding Px_DOUT[n] bit is protected
#1
DMASK3
Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT).
3
1
read-write
0
The corresponding Px_DOUT[n] bit can be updated
#0
1
The corresponding Px_DOUT[n] bit is protected
#1
DMASK4
Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT).
4
1
read-write
0
The corresponding Px_DOUT[n] bit can be updated
#0
1
The corresponding Px_DOUT[n] bit is protected
#1
DMASK5
Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT).
5
1
read-write
0
The corresponding Px_DOUT[n] bit can be updated
#0
1
The corresponding Px_DOUT[n] bit is protected
#1
DMASK6
Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT).
6
1
read-write
0
The corresponding Px_DOUT[n] bit can be updated
#0
1
The corresponding Px_DOUT[n] bit is protected
#1
DMASK7
Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT).
7
1
read-write
0
The corresponding Px_DOUT[n] bit can be updated
#0
1
The corresponding Px_DOUT[n] bit is protected
#1
P0_DOUT
P0_DOUT
P0 Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT0
Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.
0
1
read-write
0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#0
1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
#1
DOUT1
Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.
1
1
read-write
0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#0
1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
#1
DOUT2
Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.
2
1
read-write
0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#0
1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
#1
DOUT3
Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.
3
1
read-write
0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#0
1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
#1
DOUT4
Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.
4
1
read-write
0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#0
1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
#1
DOUT5
Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.
5
1
read-write
0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#0
1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
#1
DOUT6
Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.
6
1
read-write
0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#0
1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
#1
DOUT7
Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.
7
1
read-write
0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#0
1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
#1
P0_IEN
P0_IEN
P0 Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EB[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
0
1
read-write
0
Disable the Px[n] state low-level or high-to-low change interrupt
#0
1
Enable the Px[n] state low-level or high-to-low change interrupt
#1
IF_EN1
Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EB[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
1
1
read-write
0
Disable the Px[n] state low-level or high-to-low change interrupt
#0
1
Enable the Px[n] state low-level or high-to-low change interrupt
#1
IF_EN2
Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EB[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
2
1
read-write
0
Disable the Px[n] state low-level or high-to-low change interrupt
#0
1
Enable the Px[n] state low-level or high-to-low change interrupt
#1
IF_EN3
Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EB[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
3
1
read-write
0
Disable the Px[n] state low-level or high-to-low change interrupt
#0
1
Enable the Px[n] state low-level or high-to-low change interrupt
#1
IF_EN4
Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EB[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
4
1
read-write
0
Disable the Px[n] state low-level or high-to-low change interrupt
#0
1
Enable the Px[n] state low-level or high-to-low change interrupt
#1
IF_EN5
Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EB[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
5
1
read-write
0
Disable the Px[n] state low-level or high-to-low change interrupt
#0
1
Enable the Px[n] state low-level or high-to-low change interrupt
#1
IF_EN6
Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EB[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
6
1
read-write
0
Disable the Px[n] state low-level or high-to-low change interrupt
#0
1
Enable the Px[n] state low-level or high-to-low change interrupt
#1
IF_EN7
Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EB[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
7
1
read-write
0
Disable the Px[n] state low-level or high-to-low change interrupt
#0
1
Enable the Px[n] state low-level or high-to-low change interrupt
#1
IR_EN0
Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
16
1
read-write
0
Disable the Px[n] level-high or low-to-high interrupt
#0
1
Enable the Px[n] level-high or low-to-high interrupt
#1
IR_EN1
Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
17
1
read-write
0
Disable the Px[n] level-high or low-to-high interrupt
#0
1
Enable the Px[n] level-high or low-to-high interrupt
#1
IR_EN2
Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
18
1
read-write
0
Disable the Px[n] level-high or low-to-high interrupt
#0
1
Enable the Px[n] level-high or low-to-high interrupt
#1
IR_EN3
Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
19
1
read-write
0
Disable the Px[n] level-high or low-to-high interrupt
#0
1
Enable the Px[n] level-high or low-to-high interrupt
#1
IR_EN4
Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
20
1
read-write
0
Disable the Px[n] level-high or low-to-high interrupt
#0
1
Enable the Px[n] level-high or low-to-high interrupt
#1
IR_EN5
Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
21
1
read-write
0
Disable the Px[n] level-high or low-to-high interrupt
#0
1
Enable the Px[n] level-high or low-to-high interrupt
#1
IR_EN6
Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
22
1
read-write
0
Disable the Px[n] level-high or low-to-high interrupt
#0
1
Enable the Px[n] level-high or low-to-high interrupt
#1
IR_EN7
Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
23
1
read-write
0
Disable the Px[n] level-high or low-to-high interrupt
#0
1
Enable the Px[n] level-high or low-to-high interrupt
#1
P0_IMD
P0_IMD
P0 Interrupt Mode Control
0x18
read-write
n
0x0
0x0
IMD0
Port 0-4 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD1
Port 0-4 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
1
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD2
Port 0-4 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
2
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD3
Port 0-4 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
3
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD4
Port 0-4 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
4
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD5
Port 0-4 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
5
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD6
Port 0-4 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
6
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD7
Port 0-4 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
7
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
P0_ISRC
P0_ISRC
P0 Interrupt Source Flag
0x20
read-write
n
0x0
0x0
ISRC0
Port 0-4 Interrupt Source Flag
Read :
0
1
read-write
0
No interrupt at Px[n]\nNo action
#0
1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
#1
ISRC1
Port 0-4 Interrupt Source Flag
Read :
1
1
read-write
0
No interrupt at Px[n]\nNo action
#0
1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
#1
ISRC2
Port 0-4 Interrupt Source Flag
Read :
2
1
read-write
0
No interrupt at Px[n]\nNo action
#0
1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
#1
ISRC3
Port 0-4 Interrupt Source Flag
Read :
3
1
read-write
0
No interrupt at Px[n]\nNo action
#0
1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
#1
ISRC4
Port 0-4 Interrupt Source Flag
Read :
4
1
read-write
0
No interrupt at Px[n]\nNo action
#0
1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
#1
ISRC5
Port 0-4 Interrupt Source Flag
Read :
5
1
read-write
0
No interrupt at Px[n]\nNo action
#0
1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
#1
ISRC6
Port 0-4 Interrupt Source Flag
Read :
6
1
read-write
0
No interrupt at Px[n]\nNo action
#0
1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
#1
ISRC7
Port 0-4 Interrupt Source Flag
Read :
7
1
read-write
0
No interrupt at Px[n]\nNo action
#0
1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
#1
P0_OFFD
P0_OFFD
P0 Digital Input Path Disable Control
0x4
read-write
n
0x0
0x0
OFFD
OFFD: Px Pin[n] Digital Input Path Disable Control
16
8
read-write
0
Enable IO digital input path
0
1
Disable IO digital input path (digital input tied to low)
1
P0_PIN
P0_PIN
P0 Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin
0
1
read-only
PIN1
Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin
1
1
read-only
PIN2
Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin
2
1
read-only
PIN3
Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin
3
1
read-only
PIN4
Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin
4
1
read-only
PIN5
Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin
5
1
read-only
PIN6
Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin
6
1
read-only
PIN7
Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin
7
1
read-only
P0_PMD
P0_PMD
P0 Pin I/O Mode Control
0x0
-1
read-write
n
0x0
0x0
PMD0
Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
0
2
read-write
0
Px [n] pin is in INPUT mode
#00
1
Px [n] pin is in OUTPUT mode
#01
2
Px [n] pin is in Open-Drain mode
#10
3
Px [n] pin is in Quasi-bidirectional mode
#11
PMD1
Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
2
2
read-write
0
Px [n] pin is in INPUT mode
#00
1
Px [n] pin is in OUTPUT mode
#01
2
Px [n] pin is in Open-Drain mode
#10
3
Px [n] pin is in Quasi-bidirectional mode
#11
PMD2
Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
4
2
read-write
0
Px [n] pin is in INPUT mode
#00
1
Px [n] pin is in OUTPUT mode
#01
2
Px [n] pin is in Open-Drain mode
#10
3
Px [n] pin is in Quasi-bidirectional mode
#11
PMD3
Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
6
2
read-write
0
Px [n] pin is in INPUT mode
#00
1
Px [n] pin is in OUTPUT mode
#01
2
Px [n] pin is in Open-Drain mode
#10
3
Px [n] pin is in Quasi-bidirectional mode
#11
PMD4
Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
8
2
read-write
0
Px [n] pin is in INPUT mode
#00
1
Px [n] pin is in OUTPUT mode
#01
2
Px [n] pin is in Open-Drain mode
#10
3
Px [n] pin is in Quasi-bidirectional mode
#11
PMD5
Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
10
2
read-write
0
Px [n] pin is in INPUT mode
#00
1
Px [n] pin is in OUTPUT mode
#01
2
Px [n] pin is in Open-Drain mode
#10
3
Px [n] pin is in Quasi-bidirectional mode
#11
PMD6
Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
12
2
read-write
0
Px [n] pin is in INPUT mode
#00
1
Px [n] pin is in OUTPUT mode
#01
2
Px [n] pin is in Open-Drain mode
#10
3
Px [n] pin is in Quasi-bidirectional mode
#11
PMD7
Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
14
2
read-write
0
Px [n] pin is in INPUT mode
#00
1
Px [n] pin is in OUTPUT mode
#01
2
Px [n] pin is in Open-Drain mode
#10
3
Px [n] pin is in Quasi-bidirectional mode
#11
P10_PDIO
P10_PDIO
GPIO P1.0 Pin Data Input/Output
0x220
read-write
n
0x0
0x0
P11_PDIO
P11_PDIO
GPIO P1.1 Pin Data Input/Output
0x224
read-write
n
0x0
0x0
P12_PDIO
P12_PDIO
GPIO P1.2 Pin Data Input/Output
0x228
read-write
n
0x0
0x0
P13_PDIO
P13_PDIO
GPIO P1.3 Pin Data Input/Output
0x22C
read-write
n
0x0
0x0
P14_PDIO
P14_PDIO
GPIO P1.4 Pin Data Input/Output
0x230
read-write
n
0x0
0x0
P15_PDIO
P15_PDIO
GPIO P1.5 Pin Data Input/Output
0x234
read-write
n
0x0
0x0
P16_PDIO
P16_PDIO
GPIO P1.6 Pin Data Input/Output
0x238
read-write
n
0x0
0x0
P17_PDIO
P17_PDIO
GPIO P1.7 Pin Data Input/Output
0x23C
read-write
n
0x0
0x0
P1_DBEN
P1_DBEN
P1 De-bounce Enable
0x54
read-write
n
0x0
0x0
P1_DMASK
P1_DMASK
P1 Data Output Write Mask
0x4C
read-write
n
0x0
0x0
P1_DOUT
P1_DOUT
P1 Data Output Value
0x48
read-write
n
0x0
0x0
P1_IEN
P1_IEN
P1 Interrupt Enable
0x5C
read-write
n
0x0
0x0
P1_IMD
P1_IMD
P1 Interrupt Mode Control
0x58
read-write
n
0x0
0x0
P1_ISRC
P1_ISRC
P1 Interrupt Source Flag
0x60
read-write
n
0x0
0x0
P1_OFFD
P1_OFFD
P1 Digital Input Path Disable Control
0x44
read-write
n
0x0
0x0
P1_PIN
P1_PIN
P1 Pin Value
0x50
read-write
n
0x0
0x0
P1_PMD
P1_PMD
P1 Pin I/O Mode Control
0x40
read-write
n
0x0
0x0
P20_PDIO
P20_PDIO
GPIO P2.0 Pin Data Input/Output
0x240
read-write
n
0x0
0x0
P21_PDIO
P21_PDIO
GPIO P2.1 Pin Data Input/Output
0x244
read-write
n
0x0
0x0
P22_PDIO
P22_PDIO
GPIO P2.2 Pin Data Input/Output
0x248
read-write
n
0x0
0x0
P23_PDIO
P23_PDIO
GPIO P2.3 Pin Data Input/Output
0x24C
read-write
n
0x0
0x0
P24_PDIO
P24_PDIO
GPIO P2.4 Pin Data Input/Output
0x250
read-write
n
0x0
0x0
P25_PDIO
P25_PDIO
GPIO P2.5 Pin Data Input/Output
0x254
read-write
n
0x0
0x0
P26_PDIO
P26_PDIO
GPIO P2.6 Pin Data Input/Output
0x258
read-write
n
0x0
0x0
P27_PDIO
P27_PDIO
GPIO P2.7 Pin Data Input/Output
0x25C
read-write
n
0x0
0x0
P2_DBEN
P2_DBEN
P2 De-bounce Enable
0x94
read-write
n
0x0
0x0
P2_DMASK
P2_DMASK
P2 Data Output Write Mask
0x8C
read-write
n
0x0
0x0
P2_DOUT
P2_DOUT
P2 Data Output Value
0x88
read-write
n
0x0
0x0
P2_IEN
P2_IEN
P2 Interrupt Enable
0x9C
read-write
n
0x0
0x0
P2_IMD
P2_IMD
P2 Interrupt Mode Control
0x98
read-write
n
0x0
0x0
P2_ISRC
P2_ISRC
P2 Interrupt Source Flag
0xA0
read-write
n
0x0
0x0
P2_OFFD
P2_OFFD
P2 Digital Input Path Disable Control
0x84
read-write
n
0x0
0x0
P2_PIN
P2_PIN
P2 Pin Value
0x90
read-write
n
0x0
0x0
P2_PMD
P2_PMD
P2 Pin I/O Mode Control
0x80
read-write
n
0x0
0x0
P30_PDIO
P30_PDIO
GPIO P3.0 Pin Data Input/Output
0x260
read-write
n
0x0
0x0
P31_PDIO
P31_PDIO
GPIO P3.1 Pin Data Input/Output
0x264
read-write
n
0x0
0x0
P32_PDIO
P32_PDIO
GPIO P3.2 Pin Data Input/Output
0x268
read-write
n
0x0
0x0
P33_PDIO
P33_PDIO
GPIO P3.3 Pin Data Input/Output
0x26C
read-write
n
0x0
0x0
P34_PDIO
P34_PDIO
GPIO P3.4 Pin Data Input/Output
0x270
read-write
n
0x0
0x0
P35_PDIO
P35_PDIO
GPIO P3.5 Pin Data Input/Output
0x274
read-write
n
0x0
0x0
P36_PDIO
P36_PDIO
GPIO P3.6 Pin Data Input/Output
0x278
read-write
n
0x0
0x0
P37_PDIO
P37_PDIO
GPIO P3.7 Pin Data Input/Output
0x27C
read-write
n
0x0
0x0
P3_DBEN
P3_DBEN
P3 De-bounce Enable
0xD4
read-write
n
0x0
0x0
P3_DMASK
P3_DMASK
P3 Data Output Write Mask
0xCC
read-write
n
0x0
0x0
P3_DOUT
P3_DOUT
P3 Data Output Value
0xC8
read-write
n
0x0
0x0
P3_IEN
P3_IEN
P3 Interrupt Enable
0xDC
read-write
n
0x0
0x0
P3_IMD
P3_IMD
P3 Interrupt Mode Control
0xD8
read-write
n
0x0
0x0
P3_ISRC
P3_ISRC
P3 Interrupt Source Flag
0xE0
read-write
n
0x0
0x0
P3_OFFD
P3_OFFD
P3 Digital Input Path Disable Control
0xC4
read-write
n
0x0
0x0
P3_PIN
P3_PIN
P3 Pin Value
0xD0
read-write
n
0x0
0x0
P3_PMD
P3_PMD
P3 Pin I/O Mode Control
0xC0
read-write
n
0x0
0x0
P40_PDIO
P40_PDIO
GPIO P4.0 Pin Data Input/Output
0x280
read-write
n
0x0
0x0
P41_PDIO
P41_PDIO
GPIO P4.1 Pin Data Input/Output
0x284
read-write
n
0x0
0x0
P42_PDIO
P42_PDIO
GPIO P4.2 Pin Data Input/Output
0x288
read-write
n
0x0
0x0
P43_PDIO
P43_PDIO
GPIO P4.3 Pin Data Input/Output
0x28C
read-write
n
0x0
0x0
P44_PDIO
P44_PDIO
GPIO P4.4 Pin Data Input/Output
0x290
read-write
n
0x0
0x0
P45_PDIO
P45_PDIO
GPIO P4.5 Pin Data Input/Output
0x294
read-write
n
0x0
0x0
P46_PDIO
P46_PDIO
GPIO P4.6 Pin Data Input/Output
0x298
read-write
n
0x0
0x0
P47_PDIO
P47_PDIO
GPIO P4.7 Pin Data Input/Output
0x29C
read-write
n
0x0
0x0
P4_DBEN
P4_DBEN
P4 De-bounce Enable
0x114
read-write
n
0x0
0x0
P4_DMASK
P4_DMASK
P4 Data Output Write Mask
0x10C
read-write
n
0x0
0x0
P4_DOUT
P4_DOUT
P4 Data Output Value
0x108
read-write
n
0x0
0x0
P4_IEN
P4_IEN
P4 Interrupt Enable
0x11C
read-write
n
0x0
0x0
P4_IMD
P4_IMD
P4 Interrupt Mode Control
0x118
read-write
n
0x0
0x0
P4_ISRC
P4_ISRC
P4 Interrupt Source Flag
0x120
read-write
n
0x0
0x0
P4_OFFD
P4_OFFD
P4 Digital Input Path Disable Control
0x104
read-write
n
0x0
0x0
P4_PIN
P4_PIN
P4 Pin Value
0x110
read-write
n
0x0
0x0
P4_PMD
P4_PMD
P4 Pin I/O Mode Control
0x100
read-write
n
0x0
0x0
I2C0
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2CADDR0
I2CADDR0
I2C Slave Address Register 0
0x4
read-write
n
0x0
0x0
GC
General Call Function
0
1
read-write
0
Disable General Call Function
#0
1
Enable General Call Function
#1
I2CADDR
I2C Address Register\nThe content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
I2CADDR1
I2CADDR1
I2C Slave Address Register 1
0x18
read-write
n
0x0
0x0
I2CADDR2
I2CADDR2
I2C Slave Address Register 2
0x1C
read-write
n
0x0
0x0
I2CADDR3
I2CADDR3
I2C Slave Address Register 3
0x20
read-write
n
0x0
0x0
I2CADM0
I2CADM0
I2C Slave Address Mask Register 0
0x24
read-write
n
0x0
0x0
I2CADMx
I2C Address Mask register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask disable (the received corresponding register bit should be exact the same as address register.)
0
1
Mask enable (the received corresponding address bit is don't care.)
1
I2CADM1
I2CADM1
I2C Slave Address Mask Register 1
0x28
read-write
n
0x0
0x0
I2CADM2
I2CADM2
I2C Slave Address Mask Register 2
0x2C
read-write
n
0x0
0x0
I2CADM3
I2CADM3
I2C Slave Address Mask Register 3
0x30
read-write
n
0x0
0x0
I2CDAT
I2CDAT
I2C DATA Register
0x8
read-write
n
0x0
0x0
I2CDAT
I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2CLK
I2CLK
I2C clock divided Register
0x10
read-write
n
0x0
0x0
I2CLK
I2C clock divided Register
Note: The minimum value of I2CLK is 4.
0
8
read-write
I2CON
I2CON
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control Bit
2
1
read-write
EI
Enable Interrupt
7
1
read-write
0
Disable I2C interrupt
#0
1
Enable I2C interrupt
#1
ENS1
I2C Controller Enable Bit
6
1
read-write
0
Disable
#0
1
Enable
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one to this bit.
3
1
read-write
STA
I2C START Control Bit\nSetting STA to logic 1 to enter master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control Bit
In master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2CSTATUS
I2CSTATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
I2CSTATUS
I2C Status Register\nThe status register of I2C:
0
8
read-only
I2CTOC
I2CTOC
I2C Timeout Control Register
0x14
read-write
n
0x0
0x0
DIV4
Time-Out counter input clock is divided by 4 \nWhen Enable, The time-Out period is extend 4 times.
1
1
read-write
0
Disable
#0
1
Enable
#1
ENTI
Time-out counter is enabled/disable\nWhen Enable, the 14 bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Disable
#0
1
Enable
#1
TIF
Time-Out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nS/W can write 1 to clear this bit.
0
1
read-write
I2CWKUPCON
I2CWKUPCON
I2C Wake Up Control Register
0x3C
read-write
n
0x0
0x0
WKUPEN
I2C Wakeup Function Enable
0
1
read-write
0
Disable I2C wake up function
#0
1
Enable I2C wake up function
#1
I2CWKUPSTS
I2CWKUPSTS
I2C Wake Up Status Register
0x40
read-write
n
0x0
0x0
WKUPIF
I2C Wake Up Interrupt Flag\nWhen chip is waked up from power down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit
0
1
read-write
I2C1
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2CADDR0
I2CADDR0
I2C Slave Address Register 0
0x4
read-write
n
0x0
0x0
GC
General Call Function
0
1
read-write
0
Disable General Call Function
#0
1
Enable General Call Function
#1
I2CADDR
I2C Address Register\nThe content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
I2CADDR1
I2CADDR1
I2C Slave Address Register 1
0x18
read-write
n
0x0
0x0
I2CADDR2
I2CADDR2
I2C Slave Address Register 2
0x1C
read-write
n
0x0
0x0
I2CADDR3
I2CADDR3
I2C Slave Address Register 3
0x20
read-write
n
0x0
0x0
I2CADM0
I2CADM0
I2C Slave Address Mask Register 0
0x24
read-write
n
0x0
0x0
I2CADMx
I2C Address Mask register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask disable (the received corresponding register bit should be exact the same as address register.)
0
1
Mask enable (the received corresponding address bit is don't care.)
1
I2CADM1
I2CADM1
I2C Slave Address Mask Register 1
0x28
read-write
n
0x0
0x0
I2CADM2
I2CADM2
I2C Slave Address Mask Register 2
0x2C
read-write
n
0x0
0x0
I2CADM3
I2CADM3
I2C Slave Address Mask Register 3
0x30
read-write
n
0x0
0x0
I2CDAT
I2CDAT
I2C DATA Register
0x8
read-write
n
0x0
0x0
I2CDAT
I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2CLK
I2CLK
I2C clock divided Register
0x10
read-write
n
0x0
0x0
I2CLK
I2C clock divided Register
Note: The minimum value of I2CLK is 4.
0
8
read-write
I2CON
I2CON
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control Bit
2
1
read-write
EI
Enable Interrupt
7
1
read-write
0
Disable I2C interrupt
#0
1
Enable I2C interrupt
#1
ENS1
I2C Controller Enable Bit
6
1
read-write
0
Disable
#0
1
Enable
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one to this bit.
3
1
read-write
STA
I2C START Control Bit\nSetting STA to logic 1 to enter master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control Bit
In master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2CSTATUS
I2CSTATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
I2CSTATUS
I2C Status Register\nThe status register of I2C:
0
8
read-only
I2CTOC
I2CTOC
I2C Timeout Control Register
0x14
read-write
n
0x0
0x0
DIV4
Time-Out counter input clock is divided by 4 \nWhen Enable, The time-Out period is extend 4 times.
1
1
read-write
0
Disable
#0
1
Enable
#1
ENTI
Time-out counter is enabled/disable\nWhen Enable, the 14 bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Disable
#0
1
Enable
#1
TIF
Time-Out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nS/W can write 1 to clear this bit.
0
1
read-write
I2CWKUPCON
I2CWKUPCON
I2C Wake Up Control Register
0x3C
read-write
n
0x0
0x0
WKUPEN
I2C Wakeup Function Enable
0
1
read-write
0
Disable I2C wake up function
#0
1
Enable I2C wake up function
#1
I2CWKUPSTS
I2CWKUPSTS
I2C Wake Up Status Register
0x40
read-write
n
0x0
0x0
WKUPIF
I2C Wake Up Interrupt Flag\nWhen chip is waked up from power down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit
0
1
read-write
INT
INT Register Map
INT
0x0
0x0
0x88
registers
n
IRQ0_SRC
IRQ0_SRC
IRQ0 (BOD) interrupt source identity
0x0
read-only
n
0x0
0x0
INT_SRC
Bit0 : BOD_INT
0
3
read-only
IRQ10_SRC
IRQ10_SRC
IRQ10 (TMR2) interrupt source identity
0x28
read-only
n
0x0
0x0
INT_SRC
Bit0: TMR2_INT
0
3
read-only
IRQ11_SRC
IRQ11_SRC
IRQ11 (TMR3) interrupt source identity
0x2C
read-only
n
0x0
0x0
INT_SRC
Bit0: TMR3_INT
0
3
read-only
IRQ12_SRC
IRQ12_SRC
IRQ12 (UART0) interrupt source identity
0x30
read-only
n
0x0
0x0
INT_SRC
Bit0: UART0_INT
0
3
read-only
IRQ13_SRC
IRQ13_SRC
IRQ13 (UART1) interrupt source identity
0x34
read-only
n
0x0
0x0
INT_SRC
Bit0: UART1_INT
0
3
read-only
IRQ14_SRC
IRQ14_SRC
IRQ14 (SPI0) interrupt source identity
0x38
read-only
n
0x0
0x0
INT_SRC
Bit0: SPI0_INT
0
3
read-only
IRQ15_SRC
IRQ15_SRC
IRQ15 (SPI1) interrupt source identity
0x3C
read-only
n
0x0
0x0
INT_SRC
Bit0: SPI1_INT
0
3
read-only
IRQ16_SRC
IRQ16_SRC
Reserved
0x40
read-only
n
0x0
0x0
IRQ17_SRC
IRQ17_SRC
Reserved
0x44
read-only
n
0x0
0x0
IRQ18_SRC
IRQ18_SRC
IRQ18 (I2C0) interrupt source identity
0x48
read-only
n
0x0
0x0
INT_SRC
Bit0: I2C0_INT
0
3
read-only
IRQ19_SRC
IRQ19_SRC
IRQ19 (I2C1) interrupt source identity
0x4C
read-only
n
0x0
0x0
INT_SRC
Bit0: I2C1_INT
0
3
read-only
IRQ1_SRC
IRQ1_SRC
IRQ1 (WDT) interrupt source identity
0x4
read-only
n
0x0
0x0
INT_SRC
Bit0 : WDT_INT
0
3
read-only
IRQ20_SRC
IRQ20_SRC
Reserved
0x50
read-only
n
0x0
0x0
IRQ21_SRC
IRQ21_SRC
Reserved
0x54
read-only
n
0x0
0x0
IRQ22_SRC
IRQ22_SRC
Reserved
0x58
read-only
n
0x0
0x0
IRQ23_SRC
IRQ23_SRC
Reserved
0x5C
read-only
n
0x0
0x0
IRQ24_SRC
IRQ24_SRC
Reserved
0x60
read-only
n
0x0
0x0
IRQ25_SRC
IRQ25_SRC
IRQ25 (ACMPA) interrupt source identity
0x64
read-only
n
0x0
0x0
INT_SRC
Bit0: ACMPA_INT
0
3
read-only
IRQ26_SRC
IRQ26_SRC
IRQ26 (ACMPB) interrupt source identity
0x68
read-only
n
0x0
0x0
INT_SRC
Bit0: ACMPB_INT
0
3
read-only
IRQ27_SRC
IRQ27_SRC
Reserved
0x6C
read-only
n
0x0
0x0
IRQ28_SRC
IRQ28_SRC
IRQ28 (PWRWU) interrupt source identity
0x70
read-only
n
0x0
0x0
INT_SRC
Bit0: PWRWU_INT
0
3
read-only
IRQ29_SRC
IRQ29_SRC
IRQ29 (ADC) interrupt source identity
0x74
read-only
n
0x0
0x0
INT_SRC
Bit0: ADC_INT
0
3
read-only
IRQ2_SRC
IRQ2_SRC
IRQ2 (EINT0) interrupt source identity
0x8
read-only
n
0x0
0x0
INT_SRC
Bit0: EINT0 - external interrupt 0 from P3.2
0
3
read-only
IRQ30_SRC
IRQ30_SRC
Reserved
0x78
read-only
n
0x0
0x0
IRQ31_SRC
IRQ31_SRC
Reserved
0x7C
read-only
n
0x0
0x0
IRQ3_SRC
IRQ3_SRC
IRQ3 (EINT1) interrupt source identity
0xC
read-only
n
0x0
0x0
INT_SRC
Bit0: EINT1 - external interrupt 1 from P3.3
0
3
read-only
IRQ4_SRC
IRQ4_SRC
IRQ4 (P0/1) interrupt source identity
0x10
read-only
n
0x0
0x0
INT_SRC
Bit1: P1_INT\nBit0: P0_INT
0
3
read-only
IRQ5_SRC
IRQ5_SRC
IRQ5 (P2/3/4) interrupt source identity
0x14
read-only
n
0x0
0x0
INT_SRC
Bit2: P4_INT\nBit1: P3_INT\nBit0: P2_INT
0
3
read-only
IRQ6_SRC
IRQ6_SRC
IRQ6 (PWMA) interrupt source identity
0x18
read-only
n
0x0
0x0
INT_SRC
Bit3: PWM3_INT\nBit2: PWM2_INT\nBit1: PWM1_INT\nBit0: PWM0_INT
0
4
read-only
IRQ7_SRC
IRQ7_SRC
IRQ7 (PWMB) interrupt source identity
0x1C
read-only
n
0x0
0x0
INT_SRC
Bit3: PWM7_INT\nBit2: PWM6_INT\nBit1: PWM5_INT\nBit0: PWM4_INT
0
4
read-only
IRQ8_SRC
IRQ8_SRC
IRQ8 (TMR0) interrupt source identity
0x20
read-only
n
0x0
0x0
INT_SRC
Bit0: TMR0_INT
0
3
read-only
IRQ9_SRC
IRQ9_SRC
IRQ9 (TMR1) interrupt source identity
0x24
read-only
n
0x0
0x0
INT_SRC
Bit0: TMR1_INT
0
3
read-only
MCU_IRQ
MCU_IRQ
MCU Interrupt Request Source Register
0x84
-1
read-write
n
0x0
0x0
MCU_IRQ
MCU IRQ Source Register
The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. There are two modes to generate interrupt to Cortex-M0, the normal mode and test mode.
The MCU_IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0.
When the MCU_IRQ[n] is 0 , set MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 NVIC[n].
When the MCU_IRQ[n] is 1 (mean an interrupt is assert), set 1 to the MCU_IRQ[n] will clear the interrupt and set MCU_IRQ[n] 0 : no any effect
0
32
read-write
NMI_SEL
NMI_SEL
NMI source interrupt select control register
0x80
read-write
n
0x0
0x0
NMI_EN
NMI interrupt enable (write-protection bit)
This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100
8
1
read-write
0
Disable NMI interrupt
#0
1
Enable NMI interrupt
#1
NMI_SEL
NMI interrupt source selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0]\nThe NMI_SEL bit[4:0] used to select the NMI interrupt source
0
5
read-write
PWMA
PWM Register Map
PWM
0x0
0x0
0x3C
registers
n
0x40
0x8
registers
n
0x50
0x38
registers
n
0x98
0x4
registers
n
CAPENR
CAPENR
PWM Capture Input 0~3 Enable Register
0x78
read-write
n
0x0
0x0
CAPENR
Capture Input Enable Register
There are four capture inputs from pad. Bit0~Bit3 are used to control each inputs ON or OFF.
CAPENR
Bit 3210 for PWM group A
Bit xxx1 ( Capture channel 0 is from P2.0 or P4.0 (only one port can be selected)
Bit xx1x ( Capture channel 1 is from P2.1 or P4.1(only one port can be selected)
Bit x1xx ( Capture channel 2 is from P2.2 or P4.2(only one port can be selected)
Bit 1xxx ( Capture channel 3 is from P2.3 or P4.3(only one port can be selected)
Bit 3210 for PWM group B
Bit xxx1 ( Capture channel 0 is from P2.4
Bit xx1x ( Capture channel 1 is from P2.5
Bit x1xx ( Capture channel 2 is from P2.6
Bit 1xxx ( Capture channel 3 is from P2.7
0
4
read-write
0
OFF (PWMn multi-function pin input does not affect input capture function.)
0
1
ON (PWMn multi-function pin input will affect its input capture function.)
1
CCR0
CCR0
PWM Capture Control Register 0
0x50
read-write
n
0x0
0x0
CAPCH0EN
Channel 0 Capture Function Enable\nWhen Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.
3
1
read-write
0
Capture function on PWM group channel 0 Disabled
#0
1
Capture function on PWM group channel 0 Enabled
#1
CAPCH1EN
Channel 1 Capture Function Enable\nWhen Enable, Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 1 Disabled
#0
1
Capture function on PWM group channel 1 Enabled
#1
CAPIF0
Capture0 Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
4
1
read-write
CAPIF1
Capture1 Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
20
1
read-write
CFLRI0
CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to 0.
7
1
read-write
CFLRI1
CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to 0.
23
1
read-write
CFL_IE0
PWM Group Channel 0 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 0 has falling transition, Capture will issues an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE1
PWM Group Channel 1 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has falling transition, Capture will issues an Interrupt.
18
1
read-write
0
Disable falling latch interrupt
#0
1
Enable falling latch interrupt
#1
CRLRI0
CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware. \nWrite 1 to clear this bit to 0.
6
1
read-write
CRLRI1
CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to 0.
22
1
read-write
CRL_IE0
PWM Group Channel 0 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 0 has rising transition, Capture will issues an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE1
PWM Group Channel 1 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has rising transition, Capture will issues an Interrupt.
17
1
read-write
0
Disable rising latch interrupt
#0
1
Enable rising latch interrupt
#1
INV0
PWM Group Channel 0 Inverter Enable
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV1
PWM Group Channel 1 Inverter Enable
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CCR2
CCR2
PWM Capture Control Register 2
0x54
read-write
n
0x0
0x0
CAPCH2EN
Channel 2 Capture Function Enable\nWhen Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.
3
1
read-write
0
Disable capture function on PWM group channel 2
#0
1
Enable capture function on PWM group channel 2
#1
CAPCH3EN
Channel 3 Capture Function Enable\nWhen Enable, Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 3 Disabled
#0
1
Capture function on PWM group channel 3 Enabled
#1
CAPIF2
Capture2 Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0
4
1
read-write
CAPIF3
Capture3 Interrupt Indication Flag\nWrite 1 to clear this bit to zero.
20
1
read-write
CFLRI2
CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0
7
1
read-write
CFLRI3
CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to 0
23
1
read-write
CFL_IE2
PWM Group Channel 2 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 2 has falling transition, Capture issues an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE3
PWM Group Channel 3 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 3 has falling transition, Capture will issues an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI2
CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0
6
1
read-write
CRLRI3
CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to 0
22
1
read-write
CRL_IE2
PWM Group Channel 2 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 2 has rising transition, Capture issues an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE3
PWM Group Channel 3 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 3 has rising transition, Capture will issues an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV2
PWM Group Channel 2 Inverter EnableEnable
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV3
PWM Group Channel 3 Inverter EnableEnable
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CFLR0
CFLR0
PWM Capture Falling Latch Register (Channel 0)
0x5C
read-only
n
0x0
0x0
CFLRn
Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition.
0
16
read-only
CFLR1
CFLR1
PWM Capture Falling Latch Register (Channel 1)
0x64
read-write
n
0x0
0x0
CFLR2
CFLR2
PWM Capture Falling Latch Register (Channel 2)
0x6C
read-write
n
0x0
0x0
CFLR3
CFLR3
PWM Capture Falling Latch Register (Channel 3)
0x74
read-write
n
0x0
0x0
CMR0
CMR0
PWM Comparator Register 0
0x10
read-write
n
0x0
0x0
CMRn
PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CMR1
CMR1
PWM Comparator Register 1
0x1C
read-write
n
0x0
0x0
CMR2
CMR2
PWM Comparator Register 2
0x28
read-write
n
0x0
0x0
CMR3
CMR3
PWM Comparator Register 3
0x34
read-write
n
0x0
0x0
CNR0
CNR0
PWM Counter Register 0
0xC
read-write
n
0x0
0x0
CNRn
PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at center-aligned type, CNR value should be set between 0x0001 to 0xFFFE. If CNR equal to 0x0000 or 0xFFFF, the PWM will work unpredictable.\nNote: When CNR value is set to 0, PWM output is always high.
0
16
read-write
CNR1
CNR1
PWM Counter Register 1
0x18
read-write
n
0x0
0x0
CNR2
CNR2
PWM Counter Register 2
0x24
read-write
n
0x0
0x0
CNR3
CNR3
PWM Counter Register 3
0x30
read-write
n
0x0
0x0
CRLR0
CRLR0
PWM Capture Rising Latch Register (Channel 0)
0x58
read-only
n
0x0
0x0
CRLRn
Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CRLR1
CRLR1
PWM Capture Rising Latch Register (Channel 1)
0x60
read-write
n
0x0
0x0
CRLR2
CRLR2
PWM Capture Rising Latch Register (Channel 2)
0x68
read-write
n
0x0
0x0
CRLR3
CRLR3
PWM Capture Rising Latch Register (Channel 3)
0x70
read-write
n
0x0
0x0
CSR
CSR
PWM Clock Select Register
0x4
read-write
n
0x0
0x0
CSR0
Timer 0 Clock Source Selection (PWM timer 0 for group A and PWM timer 4 for group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3)
0
3
read-write
CSR1
Timer 1 Clock Source Selection (PWM timer 1 for group A and PWM timer 5 for group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3)
4
3
read-write
CSR2
Timer 2 Clock Source Selection (PWM timer 2 for group A and PWM timer 6 for group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3)
8
3
read-write
CSR3
Timer 3 Clock Source Selection (PWM timer 3 for group A and PWM timer 7 for group B)
12
3
read-write
PCR
PCR
PWM Control Register
0x8
read-write
n
0x0
0x0
CH0EN
PWM-Timer 0 Enable (PWM timer 0 for group A and PWM timer 4 for group B)
0
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH0INV
PWM-Timer 0 Output Inverter Enable(PWM timer 0 for group A and PWM timer 4 for group B)
2
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH0MOD
PWM-Timer 0 Auto-reload/One-Shot Mode (PWM timer 0 for group A and PWM timer 4 for group B)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared.
3
1
read-write
0
One-shot Mode
#0
1
Auto-reload Mode
#1
CH0PINV
PWM-Timer 0 Output Polar Inverse Enable (PWM timer 0 for group A and PWM timer 4 for group B)
1
1
read-write
0
PWM0 output polar inverse Disabled
#0
1
PWM0 output polar inverse Enabled
#1
CH1EN
PWM-Timer 1 Enable (PWM timer 1 for group A and PWM timer 5 for group B)
8
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH1INV
PWM-Timer 1 Output Inverter Enable(PWM timer 1 for group A and PWM timer 5 for group B)
10
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH1MOD
PWM-Timer 1 Auto-reload/One-Shot Mode (PWM timer 1 for group A and PWM timer 5 for group B)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared.
11
1
read-write
0
One-shot Mode
#0
1
Auto-reload Mode
#1
CH1PINV
PWM-Timer 1 Output Polar Inverse Enable (PWM timer 1 for group A and PWM timer 5 for group B)
9
1
read-write
0
PWM1 output polar inverse Disabled
#0
1
PWM1 output polar inverse Enabled
#1
CH2EN
PWM-Timer 2 Enable (PWM timer 2 for group A and PWM timer 6 for group B)
16
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH2INV
PWM-Timer 2 Output Inverter Enable(PWM timer 2 for group A and PWM timer 6 for group B)
18
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH2MOD
PWM-Timer 2 Auto-reload/One-Shot Mode (PWM timer 2 for group A and PWM timer 6 for group B)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be cleared.
19
1
read-write
0
One-shot Mode
#0
1
Auto-reload Mode
#1
CH2PINV
PWM-Timer 2 Output Polar Inverse Enable (PWM timer 2 for group A and PWM timer 6 for group B)
17
1
read-write
0
PWM2 output polar inverse Disabled
#0
1
PWM2 output polar inverse Enabled
#1
CH3EN
PWM-Timer 3 Enable (PWM timer 3 for group A and PWM timer 7 for group B)
24
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH3INV
PWM-Timer 3 Output Inverter Enable (PWM timer 3 for group A and PWM timer 7 for group B)
26
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH3MOD
PWM-Timer 3 Auto-reload/One-Shot Mode (PWM timer 3 for group A and PWM timer 7 for group B)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be cleared.
27
1
read-write
0
One-shot Mode
#0
1
Auto-reload Mode
#1
CH3PINV
PWM-Timer 3 Output Polar Inverse Enable (PWM timer 3 for group A and PWM timer 7 for group B)
25
1
read-write
0
PWM3 output polar inverse Disabled
#0
1
PWM3 output polar inverse Enabled
#1
DZEN01
Dead-Zone 0 Generator Enable/Disable (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nNote: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B.
4
1
read-write
0
Disabled
#0
1
Enabled
#1
DZEN23
Dead-Zone 2 Generator Enable/Disable (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nNote: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B.
5
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM01TYPE
PWM01 Aligned Type Selection Bit (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)
30
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
PWM23TYPE
PWM23 Aligned Type Selection Bit (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)
31
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
PDR0
PDR0
PWM Data Register 0
0x14
read-only
n
0x0
0x0
PDRn
PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter.
0
16
read-only
PDR1
PDR1
PWM Data Register 1
0x20
read-write
n
0x0
0x0
PDR2
PDR2
PWM Data Register 2
0x2C
read-write
n
0x0
0x0
PDR3
PDR3
PWM Data Register 3
0x38
read-write
n
0x0
0x0
PIER
PIER
PWM Interrupt Enable Register
0x40
read-write
n
0x0
0x0
INT01DTYPE
PWM01 Duty Interrupt Type Selection Bit (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nNote: Set INT01DTYPE to 1 only work when PWM operating in center aligned type.
24
1
read-write
0
PWMDIFn will be set if PWM counter down count and matches CMRn register. PWM will trigger ADC to conversion when PWM counter down count and matches CMRn register if correlate PWM trigger enable bit (PWMnDTEN) is set to 1
#0
1
PWMDIFn will be set when PWM counter up count and matches CMRn register. PWM will trigger ADC to conversion when PWM counter up count and matches CMRn register if correlate PWM trigger enable bit (PWMnDTEN) is set to 1
#1
INT01TYPE
PWM01 Interrupt Period Type Selection Bit (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nNote: Set INT01TYPE to 1 only work when PWM operating in center aligned type.
16
1
read-write
0
PWMIFn will be set if PWM counter underflow. PWM will trigger ADC to conversion when PWM counter underflow if correlate PWM trigger enable bit (PWMnTEN) is set to 1
#0
1
PWMIFn will be set if PWM counter matches CNRn register. PWM will trigger ADC to conversion when PWM counter matches CNRn register if correlate PWM trigger enable bit (PWMnTEN) is set to 1
#1
INT23DTYPE
PWM23 Duty Interrupt Type Selection Bit (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nNote: Set INT23DTYPE to 1 only work when PWM operating in center aligned type.
25
1
read-write
0
PWMDIFn will be set if PWM counter down count and matches CMRn register. PWM will trigger ADC to conversion when PWM counter down count and matches CMRn register if correlate PWM trigger enable bit (PWMnDTEN) is set to 1
#0
1
PWMDIFn will be set when PWM counter up count and matches CMRn register. PWM will trigger ADC to conversion when PWM counter up count and matches CMRn register if correlate PWM trigger enable bit (PWMnDTEN) is set to 1
#1
INT23TYPE
PWM23 Interrupt Period Type Selection Bit (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nNote: Set INT23TYPE to 1 only work when PWM operating in center aligned type.
17
1
read-write
0
PWMIFn will be set if PWM counter underflow. PWM will trigger ADC to conversion when PWM counter underflow if correlate PWM trigger enable bit (PWMnTEN) is set to 1
#0
1
PWMIFn will be set if PWM counter matches CNRn register. PWM will trigger ADC to conversion when PWM counter matches CNRn register if correlate PWM trigger enable bit (PWMnTEN) is set to 1
#1
PWMDIE0
PWM channel 0 Duty Interrupt Enable
8
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE1
PWM channel 1 Duty Interrupt Enable
9
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE2
PWM channel 2 Duty Interrupt Enable
10
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE3
PWM channel 3 Duty Interrupt Enable
11
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE0
PWM channel 0 Period Interrupt Enable
0
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE1
PWM channel 1 Period Interrupt Enable
1
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE2
PWM channel 2 Period Interrupt Enable
2
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE3
PWM channel 3 Period Interrupt Enable
3
1
read-write
0
Disabled
#0
1
Enabled
#1
PIIR
PIIR
PWM Interrupt Indication Register
0x44
read-write
n
0x0
0x0
PWMDIF0
PWM channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMR0, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in edge-aligned type selection
8
1
read-write
PWMDIF1
PWM channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 PWM counter down count and reaches CMR1, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in edge-aligned type selection
9
1
read-write
PWMDIF2
PWM channel 2 Duty Interrupt Flag\nFlag is set by hardware when channel 2 PWM counter down count and reaches CMR2, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in edge-aligned type selection
10
1
read-write
PWMDIF3
PWM channel 3 Duty Interrupt Flag\nFlag is set by hardware when channel 3 PWM counter down count and reaches CMR3, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in edge-aligned type selection
11
1
read-write
PWMIF0
PWM channel 0 Period Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to zero
0
1
read-write
PWMIF1
PWM channel 1 Period Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to zero
1
1
read-write
PWMIF2
PWM channel 2 Period Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register), software can write 1 to clear this bit to zero
2
1
read-write
PWMIF3
PWM channel 3 Period Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register), software can write 1 to clear this bit to zero
3
1
read-write
POE
POE
PWM Output Enable Register for Channel 0~3
0x7C
read-write
n
0x0
0x0
PWM0
PWM Channel 0 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
0
1
read-write
0
Disable PWM channel 0 output to pin
#0
1
Enable PWM channel 0 output to pin
#1
PWM1
PWM Channel 1 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
1
1
read-write
0
Disable PWM channel 1 output to pin
#0
1
Enable PWM channel 1 output to pin
#1
PWM2
PWM Channel 2 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
2
1
read-write
0
Disable PWM channel 2 output to pin
#0
1
Enable PWM channel 2 output to pin
#1
PWM3
PWM Channel 3 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
3
1
read-write
0
Disable PWM channel 3 output to pin
#0
1
Enable PWM channel 3 output to pin
#1
PPR
PPR
PWM Pre-scale Register
0x0
read-write
n
0x0
0x0
CP01
Clock prescaler 0 (PWM counter 0 1 for group A and PWM counter 4 5 for group B)
Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter
0
8
read-write
CP23
Clock prescaler 2 (PWM counter 2 3 for group A and PWM counter 6 7 for group B)
Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter
8
8
read-write
DZI01
Dead zone interval register for pair of channel 0 and channel 1 (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nThese 8 bits determine dead zone length.
16
8
read-write
DZI23
Dead zone interval register for pair of channel2 and channel3 (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nThese 8 bits determine dead zone length.
24
8
read-write
PSCR
PSCR
PWM Synchronous Control Register
0x98
read-write
n
0x0
0x0
PSSEN0
PWM0 Synchronous Start Enable\nIf this bit is set to 1, PWM-Timer0 will synchronous start with group A PWM-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A.
0
1
read-write
0
PWM0 synchronous start disable
#0
1
PWM0 synchronous start enable
#1
PSSEN1
PWM1 Synchronous Start Enable\nIf this bit is set to 1, PWM-Timer1 will synchronous start with group A PWM-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A.
8
1
read-write
0
PWM1 synchronous start disable
#0
1
PWM1 synchronous start enable
#1
PSSEN2
PWM2 Synchronous Start Enable\nIf this bit is set to 1, PWM-Timer2 will synchronous start with group A PWM-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A.
16
1
read-write
0
PWM2 synchronous start disable
#0
1
PWM2 synchronous start enable
#1
PSSEN3
PWM3 Synchronous Start Enable\nIf this bit is set to 1, PWM group-Timer3 will synchronous start with PWM group A-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A.
24
1
read-write
0
PWM3 synchronous start disable
#0
1
PWM3 synchronous start enable
#1
TCON
TCON
PWM Trigger Control Register for Channel 0~3
0x80
read-write
n
0x0
0x0
PWM0DTEN
Channel 0 PWM Duty Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count or down count to match CMR based on INT01DTYPE setting.
8
1
read-write
0
Disable PWM channel 0 trigger ADC function
#0
1
Enable PWM channel 0 trigger ADC function
#1
PWM0TEN
Channel 0 PWM Period Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count to (CNR+1) or down count to underflow based on INT01PTYPE setting.
0
1
read-write
0
Disable PWM channel 0 trigger ADC function
#0
1
Enable PWM channel 0 trigger ADC function
#1
PWM1DTEN
Channel 1 PWM Duty Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count or down count to match CMR based on INT01DTYPE setting.
9
1
read-write
0
Disable PWM channel 1 trigger ADC function
#0
1
Enable PWM channel 1 trigger ADC function
#1
PWM1TEN
Channel 1 PWM Period Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count to (CNR+1) or down count to underflow based on INT01PTYPE setting.
1
1
read-write
0
Disable PWM channel 1 trigger ADC function
#0
1
Enable PWM channel 1 trigger ADC function
#1
PWM2DTEN
Channel 2 PWM Duty Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count or down count to match CMR based on INT23DTYPE setting.
10
1
read-write
0
Disable PWM channel 2 trigger ADC function
#0
1
Enable PWM channel 2 trigger ADC function
#1
PWM2TEN
Channel 2 PWM Period Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count to (CNR+1) or down count to underflow based on INT23PTYPE setting.
2
1
read-write
0
Disable PWM channel 2 trigger ADC function
#0
1
Enable PWM channel 2 trigger ADC function
#1
PWM3DTEN
Channel 3 PWM Duty Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count or down count to match CMR based on INT23DTYPE setting.
11
1
read-write
0
Disable PWM channel 3 trigger ADC function
#0
1
Enable PWM channel 3 trigger ADC function
#1
PWM3TEN
Channel 3 PWM Period Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count to (CNR+1) or down count to underflow based on INT23PTYPE setting.
3
1
read-write
0
Disable PWM channel 3 trigger ADC function
#0
1
Enable PWM channel 3 trigger ADC function
#1
TSTATUS
TSTATUS
PWM Trigger Status Register
0x84
read-write
n
0x0
0x0
PWM0TF
PWM Channel 0 Trigger ADC Flag\nThis bit is set to 1 by hardware when PWM0 trigger ADC condition matched. As this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
0
1
read-write
PWM1TF
PWM Channel 1 Trigger ADC Flag\nThis bit is set to 1 by hardware when PWM1 trigger ADC condition matched. As this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
1
1
read-write
PWM2TF
PWM Channel 2 Trigger ADC Flag\nThis bit is set to 1 by hardware when PWM2 trigger ADC condition matched. As this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
2
1
read-write
PWM3TF
PWM Channel 3 Trigger ADC Flag\nThis bit is set to 1 by hardware when PWM3 trigger ADC condition matched. As this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
3
1
read-write
PWMB
PWM Register Map
PWM
0x0
0x0
0x3C
registers
n
0x40
0x8
registers
n
0x50
0x38
registers
n
0x98
0x4
registers
n
CAPENR
CAPENR
PWM Capture Input 0~3 Enable Register
0x78
read-write
n
0x0
0x0
CAPENR
Capture Input Enable Register
There are four capture inputs from pad. Bit0~Bit3 are used to control each inputs ON or OFF.
CAPENR
Bit 3210 for PWM group A
Bit xxx1 ( Capture channel 0 is from P2.0 or P4.0 (only one port can be selected)
Bit xx1x ( Capture channel 1 is from P2.1 or P4.1(only one port can be selected)
Bit x1xx ( Capture channel 2 is from P2.2 or P4.2(only one port can be selected)
Bit 1xxx ( Capture channel 3 is from P2.3 or P4.3(only one port can be selected)
Bit 3210 for PWM group B
Bit xxx1 ( Capture channel 0 is from P2.4
Bit xx1x ( Capture channel 1 is from P2.5
Bit x1xx ( Capture channel 2 is from P2.6
Bit 1xxx ( Capture channel 3 is from P2.7
0
4
read-write
0
OFF (PWMn multi-function pin input does not affect input capture function.)
0
1
ON (PWMn multi-function pin input will affect its input capture function.)
1
CCR0
CCR0
PWM Capture Control Register 0
0x50
read-write
n
0x0
0x0
CAPCH0EN
Channel 0 Capture Function Enable\nWhen Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.
3
1
read-write
0
Capture function on PWM group channel 0 Disabled
#0
1
Capture function on PWM group channel 0 Enabled
#1
CAPCH1EN
Channel 1 Capture Function Enable\nWhen Enable, Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 1 Disabled
#0
1
Capture function on PWM group channel 1 Enabled
#1
CAPIF0
Capture0 Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
4
1
read-write
CAPIF1
Capture1 Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
20
1
read-write
CFLRI0
CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to 0.
7
1
read-write
CFLRI1
CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to 0.
23
1
read-write
CFL_IE0
PWM Group Channel 0 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 0 has falling transition, Capture will issues an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE1
PWM Group Channel 1 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has falling transition, Capture will issues an Interrupt.
18
1
read-write
0
Disable falling latch interrupt
#0
1
Enable falling latch interrupt
#1
CRLRI0
CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware. \nWrite 1 to clear this bit to 0.
6
1
read-write
CRLRI1
CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to 0.
22
1
read-write
CRL_IE0
PWM Group Channel 0 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 0 has rising transition, Capture will issues an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE1
PWM Group Channel 1 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has rising transition, Capture will issues an Interrupt.
17
1
read-write
0
Disable rising latch interrupt
#0
1
Enable rising latch interrupt
#1
INV0
PWM Group Channel 0 Inverter Enable
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV1
PWM Group Channel 1 Inverter Enable
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CCR2
CCR2
PWM Capture Control Register 2
0x54
read-write
n
0x0
0x0
CAPCH2EN
Channel 2 Capture Function Enable\nWhen Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.
3
1
read-write
0
Disable capture function on PWM group channel 2
#0
1
Enable capture function on PWM group channel 2
#1
CAPCH3EN
Channel 3 Capture Function Enable\nWhen Enable, Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 3 Disabled
#0
1
Capture function on PWM group channel 3 Enabled
#1
CAPIF2
Capture2 Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0
4
1
read-write
CAPIF3
Capture3 Interrupt Indication Flag\nWrite 1 to clear this bit to zero.
20
1
read-write
CFLRI2
CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0
7
1
read-write
CFLRI3
CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to 0
23
1
read-write
CFL_IE2
PWM Group Channel 2 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 2 has falling transition, Capture issues an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE3
PWM Group Channel 3 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 3 has falling transition, Capture will issues an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI2
CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0
6
1
read-write
CRLRI3
CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to 0
22
1
read-write
CRL_IE2
PWM Group Channel 2 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 2 has rising transition, Capture issues an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE3
PWM Group Channel 3 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 3 has rising transition, Capture will issues an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV2
PWM Group Channel 2 Inverter EnableEnable
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV3
PWM Group Channel 3 Inverter EnableEnable
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CFLR0
CFLR0
PWM Capture Falling Latch Register (Channel 0)
0x5C
read-only
n
0x0
0x0
CFLRn
Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition.
0
16
read-only
CFLR1
CFLR1
PWM Capture Falling Latch Register (Channel 1)
0x64
read-write
n
0x0
0x0
CFLR2
CFLR2
PWM Capture Falling Latch Register (Channel 2)
0x6C
read-write
n
0x0
0x0
CFLR3
CFLR3
PWM Capture Falling Latch Register (Channel 3)
0x74
read-write
n
0x0
0x0
CMR0
CMR0
PWM Comparator Register 0
0x10
read-write
n
0x0
0x0
CMRn
PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CMR1
CMR1
PWM Comparator Register 1
0x1C
read-write
n
0x0
0x0
CMR2
CMR2
PWM Comparator Register 2
0x28
read-write
n
0x0
0x0
CMR3
CMR3
PWM Comparator Register 3
0x34
read-write
n
0x0
0x0
CNR0
CNR0
PWM Counter Register 0
0xC
read-write
n
0x0
0x0
CNRn
PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at center-aligned type, CNR value should be set between 0x0001 to 0xFFFE. If CNR equal to 0x0000 or 0xFFFF, the PWM will work unpredictable.\nNote: When CNR value is set to 0, PWM output is always high.
0
16
read-write
CNR1
CNR1
PWM Counter Register 1
0x18
read-write
n
0x0
0x0
CNR2
CNR2
PWM Counter Register 2
0x24
read-write
n
0x0
0x0
CNR3
CNR3
PWM Counter Register 3
0x30
read-write
n
0x0
0x0
CRLR0
CRLR0
PWM Capture Rising Latch Register (Channel 0)
0x58
read-only
n
0x0
0x0
CRLRn
Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CRLR1
CRLR1
PWM Capture Rising Latch Register (Channel 1)
0x60
read-write
n
0x0
0x0
CRLR2
CRLR2
PWM Capture Rising Latch Register (Channel 2)
0x68
read-write
n
0x0
0x0
CRLR3
CRLR3
PWM Capture Rising Latch Register (Channel 3)
0x70
read-write
n
0x0
0x0
CSR
CSR
PWM Clock Select Register
0x4
read-write
n
0x0
0x0
CSR0
Timer 0 Clock Source Selection (PWM timer 0 for group A and PWM timer 4 for group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3)
0
3
read-write
CSR1
Timer 1 Clock Source Selection (PWM timer 1 for group A and PWM timer 5 for group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3)
4
3
read-write
CSR2
Timer 2 Clock Source Selection (PWM timer 2 for group A and PWM timer 6 for group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3)
8
3
read-write
CSR3
Timer 3 Clock Source Selection (PWM timer 3 for group A and PWM timer 7 for group B)
12
3
read-write
PCR
PCR
PWM Control Register
0x8
read-write
n
0x0
0x0
CH0EN
PWM-Timer 0 Enable (PWM timer 0 for group A and PWM timer 4 for group B)
0
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH0INV
PWM-Timer 0 Output Inverter Enable(PWM timer 0 for group A and PWM timer 4 for group B)
2
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH0MOD
PWM-Timer 0 Auto-reload/One-Shot Mode (PWM timer 0 for group A and PWM timer 4 for group B)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared.
3
1
read-write
0
One-shot Mode
#0
1
Auto-reload Mode
#1
CH0PINV
PWM-Timer 0 Output Polar Inverse Enable (PWM timer 0 for group A and PWM timer 4 for group B)
1
1
read-write
0
PWM0 output polar inverse Disabled
#0
1
PWM0 output polar inverse Enabled
#1
CH1EN
PWM-Timer 1 Enable (PWM timer 1 for group A and PWM timer 5 for group B)
8
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH1INV
PWM-Timer 1 Output Inverter Enable(PWM timer 1 for group A and PWM timer 5 for group B)
10
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH1MOD
PWM-Timer 1 Auto-reload/One-Shot Mode (PWM timer 1 for group A and PWM timer 5 for group B)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared.
11
1
read-write
0
One-shot Mode
#0
1
Auto-reload Mode
#1
CH1PINV
PWM-Timer 1 Output Polar Inverse Enable (PWM timer 1 for group A and PWM timer 5 for group B)
9
1
read-write
0
PWM1 output polar inverse Disabled
#0
1
PWM1 output polar inverse Enabled
#1
CH2EN
PWM-Timer 2 Enable (PWM timer 2 for group A and PWM timer 6 for group B)
16
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH2INV
PWM-Timer 2 Output Inverter Enable(PWM timer 2 for group A and PWM timer 6 for group B)
18
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH2MOD
PWM-Timer 2 Auto-reload/One-Shot Mode (PWM timer 2 for group A and PWM timer 6 for group B)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be cleared.
19
1
read-write
0
One-shot Mode
#0
1
Auto-reload Mode
#1
CH2PINV
PWM-Timer 2 Output Polar Inverse Enable (PWM timer 2 for group A and PWM timer 6 for group B)
17
1
read-write
0
PWM2 output polar inverse Disabled
#0
1
PWM2 output polar inverse Enabled
#1
CH3EN
PWM-Timer 3 Enable (PWM timer 3 for group A and PWM timer 7 for group B)
24
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH3INV
PWM-Timer 3 Output Inverter Enable (PWM timer 3 for group A and PWM timer 7 for group B)
26
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH3MOD
PWM-Timer 3 Auto-reload/One-Shot Mode (PWM timer 3 for group A and PWM timer 7 for group B)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be cleared.
27
1
read-write
0
One-shot Mode
#0
1
Auto-reload Mode
#1
CH3PINV
PWM-Timer 3 Output Polar Inverse Enable (PWM timer 3 for group A and PWM timer 7 for group B)
25
1
read-write
0
PWM3 output polar inverse Disabled
#0
1
PWM3 output polar inverse Enabled
#1
DZEN01
Dead-Zone 0 Generator Enable/Disable (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nNote: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B.
4
1
read-write
0
Disabled
#0
1
Enabled
#1
DZEN23
Dead-Zone 2 Generator Enable/Disable (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nNote: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B.
5
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM01TYPE
PWM01 Aligned Type Selection Bit (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)
30
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
PWM23TYPE
PWM23 Aligned Type Selection Bit (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)
31
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
PDR0
PDR0
PWM Data Register 0
0x14
read-only
n
0x0
0x0
PDRn
PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter.
0
16
read-only
PDR1
PDR1
PWM Data Register 1
0x20
read-write
n
0x0
0x0
PDR2
PDR2
PWM Data Register 2
0x2C
read-write
n
0x0
0x0
PDR3
PDR3
PWM Data Register 3
0x38
read-write
n
0x0
0x0
PIER
PIER
PWM Interrupt Enable Register
0x40
read-write
n
0x0
0x0
INT01DTYPE
PWM01 Duty Interrupt Type Selection Bit (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nNote: Set INT01DTYPE to 1 only work when PWM operating in center aligned type.
24
1
read-write
0
PWMDIFn will be set if PWM counter down count and matches CMRn register. PWM will trigger ADC to conversion when PWM counter down count and matches CMRn register if correlate PWM trigger enable bit (PWMnDTEN) is set to 1
#0
1
PWMDIFn will be set when PWM counter up count and matches CMRn register. PWM will trigger ADC to conversion when PWM counter up count and matches CMRn register if correlate PWM trigger enable bit (PWMnDTEN) is set to 1
#1
INT01TYPE
PWM01 Interrupt Period Type Selection Bit (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nNote: Set INT01TYPE to 1 only work when PWM operating in center aligned type.
16
1
read-write
0
PWMIFn will be set if PWM counter underflow. PWM will trigger ADC to conversion when PWM counter underflow if correlate PWM trigger enable bit (PWMnTEN) is set to 1
#0
1
PWMIFn will be set if PWM counter matches CNRn register. PWM will trigger ADC to conversion when PWM counter matches CNRn register if correlate PWM trigger enable bit (PWMnTEN) is set to 1
#1
INT23DTYPE
PWM23 Duty Interrupt Type Selection Bit (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nNote: Set INT23DTYPE to 1 only work when PWM operating in center aligned type.
25
1
read-write
0
PWMDIFn will be set if PWM counter down count and matches CMRn register. PWM will trigger ADC to conversion when PWM counter down count and matches CMRn register if correlate PWM trigger enable bit (PWMnDTEN) is set to 1
#0
1
PWMDIFn will be set when PWM counter up count and matches CMRn register. PWM will trigger ADC to conversion when PWM counter up count and matches CMRn register if correlate PWM trigger enable bit (PWMnDTEN) is set to 1
#1
INT23TYPE
PWM23 Interrupt Period Type Selection Bit (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nNote: Set INT23TYPE to 1 only work when PWM operating in center aligned type.
17
1
read-write
0
PWMIFn will be set if PWM counter underflow. PWM will trigger ADC to conversion when PWM counter underflow if correlate PWM trigger enable bit (PWMnTEN) is set to 1
#0
1
PWMIFn will be set if PWM counter matches CNRn register. PWM will trigger ADC to conversion when PWM counter matches CNRn register if correlate PWM trigger enable bit (PWMnTEN) is set to 1
#1
PWMDIE0
PWM channel 0 Duty Interrupt Enable
8
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE1
PWM channel 1 Duty Interrupt Enable
9
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE2
PWM channel 2 Duty Interrupt Enable
10
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE3
PWM channel 3 Duty Interrupt Enable
11
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE0
PWM channel 0 Period Interrupt Enable
0
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE1
PWM channel 1 Period Interrupt Enable
1
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE2
PWM channel 2 Period Interrupt Enable
2
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE3
PWM channel 3 Period Interrupt Enable
3
1
read-write
0
Disabled
#0
1
Enabled
#1
PIIR
PIIR
PWM Interrupt Indication Register
0x44
read-write
n
0x0
0x0
PWMDIF0
PWM channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMR0, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in edge-aligned type selection
8
1
read-write
PWMDIF1
PWM channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 PWM counter down count and reaches CMR1, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in edge-aligned type selection
9
1
read-write
PWMDIF2
PWM channel 2 Duty Interrupt Flag\nFlag is set by hardware when channel 2 PWM counter down count and reaches CMR2, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in edge-aligned type selection
10
1
read-write
PWMDIF3
PWM channel 3 Duty Interrupt Flag\nFlag is set by hardware when channel 3 PWM counter down count and reaches CMR3, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in edge-aligned type selection
11
1
read-write
PWMIF0
PWM channel 0 Period Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to zero
0
1
read-write
PWMIF1
PWM channel 1 Period Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to zero
1
1
read-write
PWMIF2
PWM channel 2 Period Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register), software can write 1 to clear this bit to zero
2
1
read-write
PWMIF3
PWM channel 3 Period Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register), software can write 1 to clear this bit to zero
3
1
read-write
POE
POE
PWM Output Enable Register for Channel 0~3
0x7C
read-write
n
0x0
0x0
PWM0
PWM Channel 0 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
0
1
read-write
0
Disable PWM channel 0 output to pin
#0
1
Enable PWM channel 0 output to pin
#1
PWM1
PWM Channel 1 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
1
1
read-write
0
Disable PWM channel 1 output to pin
#0
1
Enable PWM channel 1 output to pin
#1
PWM2
PWM Channel 2 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
2
1
read-write
0
Disable PWM channel 2 output to pin
#0
1
Enable PWM channel 2 output to pin
#1
PWM3
PWM Channel 3 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
3
1
read-write
0
Disable PWM channel 3 output to pin
#0
1
Enable PWM channel 3 output to pin
#1
PPR
PPR
PWM Pre-scale Register
0x0
read-write
n
0x0
0x0
CP01
Clock prescaler 0 (PWM counter 0 1 for group A and PWM counter 4 5 for group B)
Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter
0
8
read-write
CP23
Clock prescaler 2 (PWM counter 2 3 for group A and PWM counter 6 7 for group B)
Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter
8
8
read-write
DZI01
Dead zone interval register for pair of channel 0 and channel 1 (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nThese 8 bits determine dead zone length.
16
8
read-write
DZI23
Dead zone interval register for pair of channel2 and channel3 (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nThese 8 bits determine dead zone length.
24
8
read-write
PSCR
PSCR
PWM Synchronous Control Register
0x98
read-write
n
0x0
0x0
PSSEN0
PWM0 Synchronous Start Enable\nIf this bit is set to 1, PWM-Timer0 will synchronous start with group A PWM-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A.
0
1
read-write
0
PWM0 synchronous start disable
#0
1
PWM0 synchronous start enable
#1
PSSEN1
PWM1 Synchronous Start Enable\nIf this bit is set to 1, PWM-Timer1 will synchronous start with group A PWM-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A.
8
1
read-write
0
PWM1 synchronous start disable
#0
1
PWM1 synchronous start enable
#1
PSSEN2
PWM2 Synchronous Start Enable\nIf this bit is set to 1, PWM-Timer2 will synchronous start with group A PWM-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A.
16
1
read-write
0
PWM2 synchronous start disable
#0
1
PWM2 synchronous start enable
#1
PSSEN3
PWM3 Synchronous Start Enable\nIf this bit is set to 1, PWM group-Timer3 will synchronous start with PWM group A-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A.
24
1
read-write
0
PWM3 synchronous start disable
#0
1
PWM3 synchronous start enable
#1
TCON
TCON
PWM Trigger Control Register for Channel 0~3
0x80
read-write
n
0x0
0x0
PWM0DTEN
Channel 0 PWM Duty Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count or down count to match CMR based on INT01DTYPE setting.
8
1
read-write
0
Disable PWM channel 0 trigger ADC function
#0
1
Enable PWM channel 0 trigger ADC function
#1
PWM0TEN
Channel 0 PWM Period Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count to (CNR+1) or down count to underflow based on INT01PTYPE setting.
0
1
read-write
0
Disable PWM channel 0 trigger ADC function
#0
1
Enable PWM channel 0 trigger ADC function
#1
PWM1DTEN
Channel 1 PWM Duty Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count or down count to match CMR based on INT01DTYPE setting.
9
1
read-write
0
Disable PWM channel 1 trigger ADC function
#0
1
Enable PWM channel 1 trigger ADC function
#1
PWM1TEN
Channel 1 PWM Period Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count to (CNR+1) or down count to underflow based on INT01PTYPE setting.
1
1
read-write
0
Disable PWM channel 1 trigger ADC function
#0
1
Enable PWM channel 1 trigger ADC function
#1
PWM2DTEN
Channel 2 PWM Duty Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count or down count to match CMR based on INT23DTYPE setting.
10
1
read-write
0
Disable PWM channel 2 trigger ADC function
#0
1
Enable PWM channel 2 trigger ADC function
#1
PWM2TEN
Channel 2 PWM Period Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count to (CNR+1) or down count to underflow based on INT23PTYPE setting.
2
1
read-write
0
Disable PWM channel 2 trigger ADC function
#0
1
Enable PWM channel 2 trigger ADC function
#1
PWM3DTEN
Channel 3 PWM Duty Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count or down count to match CMR based on INT23DTYPE setting.
11
1
read-write
0
Disable PWM channel 3 trigger ADC function
#0
1
Enable PWM channel 3 trigger ADC function
#1
PWM3TEN
Channel 3 PWM Period Trigger ADC Enable Register\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM counter up count to (CNR+1) or down count to underflow based on INT23PTYPE setting.
3
1
read-write
0
Disable PWM channel 3 trigger ADC function
#0
1
Enable PWM channel 3 trigger ADC function
#1
TSTATUS
TSTATUS
PWM Trigger Status Register
0x84
read-write
n
0x0
0x0
PWM0TF
PWM Channel 0 Trigger ADC Flag\nThis bit is set to 1 by hardware when PWM0 trigger ADC condition matched. As this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
0
1
read-write
PWM1TF
PWM Channel 1 Trigger ADC Flag\nThis bit is set to 1 by hardware when PWM1 trigger ADC condition matched. As this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
1
1
read-write
PWM2TF
PWM Channel 2 Trigger ADC Flag\nThis bit is set to 1 by hardware when PWM2 trigger ADC condition matched. As this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
2
1
read-write
PWM3TF
PWM Channel 3 Trigger ADC Flag\nThis bit is set to 1 by hardware when PWM3 trigger ADC condition matched. As this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
3
1
read-write
SCS
SCS Register Map
SCS
0x0
0x10
0xC
registers
n
0x100
0x4
registers
n
0x180
0x4
registers
n
0x200
0x4
registers
n
0x280
0x4
registers
n
0x400
0x20
registers
n
0xD00
0x8
registers
n
0xD0C
0x8
registers
n
0xD1C
0x8
registers
n
AIRCR
AIRCR
Application Interrupt and Reset Control Register
0xD0C
-1
read-write
n
0x0
0x0
SYSRESETREQ
Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence.
2
1
read-write
VECTCLRACTIVE
Set this bit to 1 will clears all active state information for fixed and configurable exceptions.\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack.
1
1
read-write
VECTORKEY
When write this register, this field should be 0x05FA, otherwise the write action will be unpredictable.
16
16
read-write
CPUID
CPUID
CPUID Register
0xD00
-1
read-only
n
0x0
0x0
IMPLEMENTER
None
24
8
read-only
PART
Reads as 0xC for ARMv6-M parts
16
4
read-only
PARTNO
Reads as 0xC20.
4
12
read-only
REVISION
Reads as 0x0
0
4
read-only
ICSR
ICSR
Interrupt Control State Register
0xD04
read-write
n
0x0
0x0
ISRPENDING
Interrupt pending flag, excluding NMI and Faults:\nThis is a read only bit.
22
1
read-write
0
interrupt not pending
#0
1
interrupt pending
#1
ISRPREEMPT
If set, a pending exception will be serviced on exit from the debug halt state.\nThis is a read only bit.
23
1
read-write
NMIPENDSET
NMI set-pending bit\nWrite:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
31
1
read-write
0
no effect\nNMI exception is not pending
#0
1
changes NMI exception state to pending.\nNMI exception is pending
#1
PENDSTCLR
SysTick exception clear-pending bit.
Write:
This is a write only bit. When you want to clear PENDST bit, you must write 0 to PENDSTSET and write 1 to PENDSTCLR at the same time.
25
1
read-write
0
no effect
#0
1
removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick exception set-pending bit.\nWrite:
26
1
read-write
0
no effect\nSysTick exception is not pending
#0
1
changes SysTick exception state to pending.\nSysTick exception is pending
#1
PENDSVCLR
PendSV clear-pending bit.
Write:
This is a write only bit. When you want to clear PENDSV bit, you must write 0 to PENDSVSET and write 1 to PENDSVCLR at the same time.
27
1
read-write
0
no effect
#0
1
removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV set-pending bit.\nWrite:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
no effect\nPendSV exception is not pending
#0
1
changes PendSV exception state to pending.\nPendSV exception is pending
#1
VECTACTIVE
Contains the active exception number
0
6
read-write
0
Thread mode
0
VECTPENDING
Indicates the exception number of the highest priority pending enabled exception:
12
6
read-write
0
no pending exceptions
0
NVIC_ICER
NVIC_ICER
IRQ0 ~ IRQ31 Clear-Enable Control Register
0x180
read-write
n
0x0
0x0
CLRENA
Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). \nWriting 1 will disable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with the current enable state.
0
32
read-write
NVIC_ICPR
NVIC_ICPR
IRQ0 ~ IRQ31 Clear-Pending Control Register
0x280
read-write
n
0x0
0x0
CLRPEND
Writing 1 to a bit un-pends the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the current pending state.
0
32
read-write
NVIC_IPR0
NVIC_IPR0
IRQ0 ~ IRQ3 Interrupt Priority Control Register
0x400
read-write
n
0x0
0x0
PRI_0
Priority of IRQ0
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_1
Priority of IRQ1
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_2
Priority of IRQ2
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_3
Priority of IRQ3
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR1
NVIC_IPR1
IRQ4 ~ IRQ7 Interrupt Priority Control Register
0x404
read-write
n
0x0
0x0
PRI_4
Priority of IRQ4
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_5
Priority of IRQ5
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_6
Priority of IRQ6
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_7
Priority of IRQ7
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR2
NVIC_IPR2
IRQ8 ~ IRQ11 Interrupt Priority Control Register
0x408
read-write
n
0x0
0x0
PRI_10
Priority of IRQ10
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_11
Priority of IRQ11
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
PRI_8
Priority of IRQ8
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_9
Priority of IRQ9
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
NVIC_IPR3
NVIC_IPR3
IRQ12 ~ IRQ15 Interrupt Priority Control Register
0x40C
read-write
n
0x0
0x0
PRI_12
Priority of IRQ12
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_13
Priority of IRQ13
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_14
Priority of IRQ14
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_15
Priority of IRQ15
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR4
NVIC_IPR4
IRQ16 ~ IRQ19 Interrupt Priority Control Register
0x410
read-write
n
0x0
0x0
PRI_16
Priority of IRQ16
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_17
Priority of IRQ17
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_18
Priority of IRQ18
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_19
Priority of IRQ19
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR5
NVIC_IPR5
IRQ20 ~ IRQ23 Interrupt Priority Control Register
0x414
read-write
n
0x0
0x0
PRI_20
Priority of IRQ20
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_21
Priority of IRQ21
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_22
Priority of IRQ22
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_23
Priority of IRQ23
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR6
NVIC_IPR6
IRQ24 ~ IRQ27 Interrupt Priority Control Register
0x418
read-write
n
0x0
0x0
PRI_24
Priority of IRQ24
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_25
Priority of IRQ25
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_26
Priority of IRQ26
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_27
Priority of IRQ27
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR7
NVIC_IPR7
IRQ28 ~ IRQ31 Interrupt Priority Control Register
0x41C
read-write
n
0x0
0x0
PRI_28
Priority of IRQ28
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_29
Priority of IRQ29
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_30
Priority of IRQ30
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_31
Priority of IRQ31
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_ISER
NVIC_ISER
IRQ0 ~ IRQ31 Set-Enable Control Register
0x100
read-write
n
0x0
0x0
SETENA
Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). \nWriting 1 will enable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with the current enable state.
0
32
read-write
NVIC_ISPR
NVIC_ISPR
IRQ0 ~ IRQ31 Set-Pending Control Register
0x200
read-write
n
0x0
0x0
SETPEND
Writing 1 to a bit pends the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the current pending state.
0
32
read-write
SCR
SCR
System Control Register
0xD10
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending bit:\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded
#0
1
enabled events and all interrupts, including disabled interrupts, can wake-up the processor
#1
SLEEPDEEP
Controls whether the processor uses sleep or deep sleep as its low power mode:
2
1
read-write
0
sleep
#0
1
deep sleep
#1
SLEEPONEXIT
Indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
0
do not sleep when returning to Thread mode
#0
1
enter sleep, or deep sleep, on return from an ISR to Thread mode
#1
SHPR2
SHPR2
System Handler Priority Register 2
0xD1C
read-write
n
0x0
0x0
PRI_11
Priority of system handler 11 - SVCall
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
SHPR3
SHPR3
System Handler Priority Register 3
0xD20
read-write
n
0x0
0x0
PRI_14
Priority of system handler 14 - PendSV
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_15
Priority of system handler 15 - SysTick
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
SYST_CSR
SYST_CSR
SysTick Control and Status Register
0x10
read-write
n
0x0
0x0
CLKSRC
None
2
1
read-write
0
Clock source is optional, refer to STCLK_S
#0
1
Core clock used for SysTick
#1
COUNTFLAG
Returns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-write
ENABLE
None
0
1
read-write
0
The counter is disabled
#0
1
The counter will operate in a multi-shot manner
#1
TICKINT
None
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended
#1
SYST_CVR
SYST_CVR
SysTick Current Value Register
0x18
read-write
n
0x0
0x0
CURRENT
Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
0
24
read-write
SYST_RVR
SYST_RVR
SysTick Reload Value Register
0x14
read-write
n
0x0
0x0
RELOAD
Value to load into the Current Value register when the counter reaches 0.
0
24
read-write
SPI0
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x3C
0xC
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity
11
1
read-write
0
SPICLK idle low
#0
1
SPICLK idle high
#1
FIFO
FIFO Mode
Note:
Before enabling FIFO mode, the other related settings should be set in advance.
In master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data into the 8-depth FIFO. It means all data stored at transmit FIFO buffer are transferred when the transmit FIFO buffer is empty and the GO_BUSY bit back to 0.
21
1
read-write
0
Disable FIFO Mode
#0
1
Enable FIFO Mode
#1
GO_BUSY
SPI Transfer Control Bit and Busy Status\nIf the FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit.\nNote:\nAll registers should be set before writing 1 to this GO_BUSY bit.
0
1
read-write
0
Writing 0 to this bit to stop data transfer if SPI is transferring
#0
1
In master mode, writing 1 to this bit to start the SPI data transfer in slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
SPI Unit Transfer Interrupt Enable Bit
17
1
read-write
0
Disable SPI unit transfer interrupt
#0
1
Enable SPI unit transfer interrupt
#1
IF
SPI Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
It indicates that the transfer does not finish yet
#0
1
It indicates that the SPI controller has finished one unit transfer
#1
LSB
LSB First
10
1
read-write
0
The MSB, which bit of SPI_TX0/SPI_RX0 register depends on the setting of TX_BIT_LEN, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI_TX0 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0)
#1
REORDER
Byte Reorder Function\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.
19
1
read-write
0
Disable the byte reorder function
#0
1
Enable byte reorder function
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[24].
24
1
read-only
0
Indicates that the receive FIFO buffer is not empty
#0
1
Indicates that the receive FIFO buffer is empty
#1
RX_FULL
Receive FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[25].
25
1
read-only
0
Indicates that the receive FIOF buffer is not full
#0
1
Indicates that the receive FIFO buffer is full
#1
RX_NEG
Receive on Negative Edge
1
1
read-write
0
The received data input signal is latched on the rising edge of SPICLK
#0
1
The received data input signal is latched on the falling edge of SPICLK
#1
SLAVE
Slave Mode Enable Bit
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\nThese four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation:\n(SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:
12
4
read-write
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.
3
5
read-write
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_STAUTS[26].
26
1
read-only
0
Indicates that the transmit FIFO buffer is not empty
#0
1
Indicates that the transmit FIFO buffer is empty
#1
TX_FULL
Transmit FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[27].
27
1
read-only
0
Indicates that the transmit FIFO buffer is not full
#0
1
Indicates that the transmit FIFO buffer is full
#1
TX_NEG
Transmit on Negative Edge
2
1
read-write
0
The transmitted data output signal is changed on the rising edge of SPICLK
#0
1
The transmitted data output signal is changed on the falling edge of SPICLK
#1
SPI_CNTRL2
SPI_CNTRL2
Control and Status Register 2
0x3C
read-write
n
0x0
0x0
BCn
SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
31
1
read-write
0
Backward compatible clock configuration
#0
1
The clock configuration is not backward compatible
#1
NOSLVSEL
Slave 3-Wire Mode Enable Bit\nThis is used to ignore the slave select signal in slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI.\nNote: In 3-wire mode, the SS_LTRIG, SPI_SSR[4], shall be set as 1.
8
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLV_ABORT
Slave 3-Wire Mode Abort Control Bit\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: It will be cleared to 0 automatically by hardware after the software sets this bit to 1.
9
1
read-write
SLV_START_INTSTS
Slave 3-Wire Mode Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode.
11
1
read-write
0
It indicates that the SPI transfer is not active
#0
1
It indicates that the transfer has started in slave 3-wire mode. It will be cleared to 0 as transfer done or by writing one to this bit
#1
SSTA_INTEN
Slave 3-Wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.
10
1
read-write
0
Disable the transfer start interrupt
#0
1
Enable the transaction start interrupt. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
#1
SS_INT_OPT
Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register (master only)\nThe value in this field is the frequency divider for generating the SPI engine clock and its SPI clock. The frequency is obtained according to the following equation:\nIf the bit of BCn, SPI_CNTRL2[31], is set to'0'.\n\nelse if BCn is set to '1',\n\nwhere \n is the SPI engine clock source. It is defined in the CLKSEL1 register.
0
8
read-write
SPI_FIFO_CTL
SPI_FIFO_CTL
SPI FIFO Control Register
0x40
-1
read-write
n
0x0
0x0
RXOV_INTEN
Receive FIFO Overrun Interrupt Enable
6
1
read-write
0
Disable Receive FIFO overrun interrupt
#0
1
Enable Receive FIFO overrun interrupt
#1
RX_CLR
Clear Receive FIFO Buffer
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1
#1
RX_INTEN
Receive Threshold Interrupt Enable
2
1
read-write
0
Disable receive threshold interrupt
#0
1
Enable receive threshold interrupt
#1
RX_THRESHOLD
Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
24
2
read-write
TIMEOUT_INTEN
Receive FIFO Time-out Interrupt Enable
21
1
read-write
0
Disable time-out interrupt
#0
1
Enable time-out interrupt
#1
TX_CLR
Clear Transmit FIFO Buffer
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1
#1
TX_INTEN
Transmit Threshold Interrupt Enable
3
1
read-write
0
Disable transmit threshold interrupt
#0
1
Enable transmit threshold interrupt
#1
TX_THRESHOLD
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
28
2
read-write
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If the FIFO mode is disabled, the software can access the last received data by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the software can access the receive FIFO buffer by reading this register. This is a read-only register.
0
32
read-only
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable Bit (Master only)
3
1
read-write
0
If this bit is cleared, slave select signal will be asserted/de-asserted by setting /clearing SSR[0]
#0
1
If this bit is set, SPISSx signal will be generated automatically. It means that device/slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nIn slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only
5
1
read-write
0
The transferred bit length of one transaction does not meet the specified requirement
#0
1
The transferred bit length meets the specified requirement which defined in TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master only)
If AUTOSS bit is cleared, writing 1 to this field sets the SPISSx line to active state and writing 0 sets the line back to inactive state.
If AUTOSS bit is set, writing 0 to this field will keep the SPISSx line at inactive state writing 1 to this field will select the SPISSx line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx is specified in SS_LVL.
0
1
read-write
SS_LTRIG
Slave Select Level Trigger Enable Bit (Slave only)
4
1
read-write
0
The slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge
#0
1
The slave select signal will be level-trigger. The SS_LVL bit decides the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nIt defines the active status of slave select signal (SPISSx).
2
1
read-write
0
The slave select signal SPISSx is active on low-level/falling-edge
#0
1
The slave select signal SPISSx is active on high-level/rising-edge
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x44
-1
read-write
n
0x0
0x0
IF
SPI Unit Transfer Interrupt Flag\nIt's a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
It indicates that the transfer does not finish yet
#0
1
It indicates that the SPI controller has finished one unit transfer
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[24].
24
1
read-only
0
Indicates that the receive FIFO buffer is not empty
#0
1
Indicates that the receive FIFO buffer is empty
#1
RX_FIFO_COUNT
Receive FIFO Data Count (read only)\nIndicates the valid data count of receive FIFO buffer.
12
4
read-only
RX_FULL
Receive FIFO Buffer Full Indicator (read only) \nIt's a mutual mirror bit of SPI_CNTRL[25].
25
1
read-only
0
Indicates that the receive FIFO buffer is not full
#0
1
Indicates that the receive FIFO buffer is full
#1
RX_INTSTS
Receive FIFO Threshold Interrupt Status (read only)
0
1
read-only
0
It indicates that the valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#0
1
It indicates that the valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
#1
RX_OVERRUN
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
SLV_START_INTSTS
Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11].
11
1
read-write
0
It indicates that the transfer is not started
#0
1
It indicates that the transfer has started in slave 3-wire mode. It will be cleared as transfer done or by writing one to this bit
#1
TIMEOUT
Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
20
1
read-write
0
No receive FIFO time-out event
#0
1
It indicates that the receive FIFO buffer is not empty and there is not be read over 64 SPI clock period in master mode and over 576 SPI engine clock period in slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (read only) \nIt's a mutual mirror bit of SPI_CNTRL[26].
26
1
read-only
0
Indicates that the transmit FIFO buffer is not empty
#0
1
Indicates that the transmit FIFO buffer is empty
#1
TX_FIFO_COUNT
Transmit FIFO Data Count (read only)\nIndicates the valid data count of transmit FIFO buffer.
28
4
read-only
TX_FULL
Transmit FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[27].
27
1
read-only
0
Indicates that the transmit FIFO buffer is not full
#0
1
Indicates that the transmit FIFO buffer is full
#1
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (read only)
4
1
read-only
0
It indicates that the valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#0
1
It indicates that the valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bit TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: when the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1.
0
32
write-only
SPI1
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x3C
0xC
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity
11
1
read-write
0
SPICLK idle low
#0
1
SPICLK idle high
#1
FIFO
FIFO Mode
Note:
Before enabling FIFO mode, the other related settings should be set in advance.
In master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data into the 8-depth FIFO. It means all data stored at transmit FIFO buffer are transferred when the transmit FIFO buffer is empty and the GO_BUSY bit back to 0.
21
1
read-write
0
Disable FIFO Mode
#0
1
Enable FIFO Mode
#1
GO_BUSY
SPI Transfer Control Bit and Busy Status\nIf the FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit.\nNote:\nAll registers should be set before writing 1 to this GO_BUSY bit.
0
1
read-write
0
Writing 0 to this bit to stop data transfer if SPI is transferring
#0
1
In master mode, writing 1 to this bit to start the SPI data transfer in slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
SPI Unit Transfer Interrupt Enable Bit
17
1
read-write
0
Disable SPI unit transfer interrupt
#0
1
Enable SPI unit transfer interrupt
#1
IF
SPI Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
It indicates that the transfer does not finish yet
#0
1
It indicates that the SPI controller has finished one unit transfer
#1
LSB
LSB First
10
1
read-write
0
The MSB, which bit of SPI_TX0/SPI_RX0 register depends on the setting of TX_BIT_LEN, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI_TX0 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0)
#1
REORDER
Byte Reorder Function\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.
19
1
read-write
0
Disable the byte reorder function
#0
1
Enable byte reorder function
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[24].
24
1
read-only
0
Indicates that the receive FIFO buffer is not empty
#0
1
Indicates that the receive FIFO buffer is empty
#1
RX_FULL
Receive FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[25].
25
1
read-only
0
Indicates that the receive FIOF buffer is not full
#0
1
Indicates that the receive FIFO buffer is full
#1
RX_NEG
Receive on Negative Edge
1
1
read-write
0
The received data input signal is latched on the rising edge of SPICLK
#0
1
The received data input signal is latched on the falling edge of SPICLK
#1
SLAVE
Slave Mode Enable Bit
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\nThese four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation:\n(SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:
12
4
read-write
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.
3
5
read-write
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_STAUTS[26].
26
1
read-only
0
Indicates that the transmit FIFO buffer is not empty
#0
1
Indicates that the transmit FIFO buffer is empty
#1
TX_FULL
Transmit FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[27].
27
1
read-only
0
Indicates that the transmit FIFO buffer is not full
#0
1
Indicates that the transmit FIFO buffer is full
#1
TX_NEG
Transmit on Negative Edge
2
1
read-write
0
The transmitted data output signal is changed on the rising edge of SPICLK
#0
1
The transmitted data output signal is changed on the falling edge of SPICLK
#1
SPI_CNTRL2
SPI_CNTRL2
Control and Status Register 2
0x3C
read-write
n
0x0
0x0
BCn
SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
31
1
read-write
0
Backward compatible clock configuration
#0
1
The clock configuration is not backward compatible
#1
NOSLVSEL
Slave 3-Wire Mode Enable Bit\nThis is used to ignore the slave select signal in slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI.\nNote: In 3-wire mode, the SS_LTRIG, SPI_SSR[4], shall be set as 1.
8
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLV_ABORT
Slave 3-Wire Mode Abort Control Bit\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: It will be cleared to 0 automatically by hardware after the software sets this bit to 1.
9
1
read-write
SLV_START_INTSTS
Slave 3-Wire Mode Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode.
11
1
read-write
0
It indicates that the SPI transfer is not active
#0
1
It indicates that the transfer has started in slave 3-wire mode. It will be cleared to 0 as transfer done or by writing one to this bit
#1
SSTA_INTEN
Slave 3-Wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.
10
1
read-write
0
Disable the transfer start interrupt
#0
1
Enable the transaction start interrupt. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
#1
SS_INT_OPT
Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register (master only)\nThe value in this field is the frequency divider for generating the SPI engine clock and its SPI clock. The frequency is obtained according to the following equation:\nIf the bit of BCn, SPI_CNTRL2[31], is set to'0'.\n\nelse if BCn is set to '1',\n\nwhere \n is the SPI engine clock source. It is defined in the CLKSEL1 register.
0
8
read-write
SPI_FIFO_CTL
SPI_FIFO_CTL
SPI FIFO Control Register
0x40
-1
read-write
n
0x0
0x0
RXOV_INTEN
Receive FIFO Overrun Interrupt Enable
6
1
read-write
0
Disable Receive FIFO overrun interrupt
#0
1
Enable Receive FIFO overrun interrupt
#1
RX_CLR
Clear Receive FIFO Buffer
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1
#1
RX_INTEN
Receive Threshold Interrupt Enable
2
1
read-write
0
Disable receive threshold interrupt
#0
1
Enable receive threshold interrupt
#1
RX_THRESHOLD
Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
24
2
read-write
TIMEOUT_INTEN
Receive FIFO Time-out Interrupt Enable
21
1
read-write
0
Disable time-out interrupt
#0
1
Enable time-out interrupt
#1
TX_CLR
Clear Transmit FIFO Buffer
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1
#1
TX_INTEN
Transmit Threshold Interrupt Enable
3
1
read-write
0
Disable transmit threshold interrupt
#0
1
Enable transmit threshold interrupt
#1
TX_THRESHOLD
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
28
2
read-write
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If the FIFO mode is disabled, the software can access the last received data by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the software can access the receive FIFO buffer by reading this register. This is a read-only register.
0
32
read-only
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable Bit (Master only)
3
1
read-write
0
If this bit is cleared, slave select signal will be asserted/de-asserted by setting /clearing SSR[0]
#0
1
If this bit is set, SPISSx signal will be generated automatically. It means that device/slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nIn slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only
5
1
read-write
0
The transferred bit length of one transaction does not meet the specified requirement
#0
1
The transferred bit length meets the specified requirement which defined in TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master only)
If AUTOSS bit is cleared, writing 1 to this field sets the SPISSx line to active state and writing 0 sets the line back to inactive state.
If AUTOSS bit is set, writing 0 to this field will keep the SPISSx line at inactive state writing 1 to this field will select the SPISSx line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx is specified in SS_LVL.
0
1
read-write
SS_LTRIG
Slave Select Level Trigger Enable Bit (Slave only)
4
1
read-write
0
The slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge
#0
1
The slave select signal will be level-trigger. The SS_LVL bit decides the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nIt defines the active status of slave select signal (SPISSx).
2
1
read-write
0
The slave select signal SPISSx is active on low-level/falling-edge
#0
1
The slave select signal SPISSx is active on high-level/rising-edge
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x44
-1
read-write
n
0x0
0x0
IF
SPI Unit Transfer Interrupt Flag\nIt's a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
It indicates that the transfer does not finish yet
#0
1
It indicates that the SPI controller has finished one unit transfer
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[24].
24
1
read-only
0
Indicates that the receive FIFO buffer is not empty
#0
1
Indicates that the receive FIFO buffer is empty
#1
RX_FIFO_COUNT
Receive FIFO Data Count (read only)\nIndicates the valid data count of receive FIFO buffer.
12
4
read-only
RX_FULL
Receive FIFO Buffer Full Indicator (read only) \nIt's a mutual mirror bit of SPI_CNTRL[25].
25
1
read-only
0
Indicates that the receive FIFO buffer is not full
#0
1
Indicates that the receive FIFO buffer is full
#1
RX_INTSTS
Receive FIFO Threshold Interrupt Status (read only)
0
1
read-only
0
It indicates that the valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#0
1
It indicates that the valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
#1
RX_OVERRUN
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
SLV_START_INTSTS
Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11].
11
1
read-write
0
It indicates that the transfer is not started
#0
1
It indicates that the transfer has started in slave 3-wire mode. It will be cleared as transfer done or by writing one to this bit
#1
TIMEOUT
Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
20
1
read-write
0
No receive FIFO time-out event
#0
1
It indicates that the receive FIFO buffer is not empty and there is not be read over 64 SPI clock period in master mode and over 576 SPI engine clock period in slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (read only) \nIt's a mutual mirror bit of SPI_CNTRL[26].
26
1
read-only
0
Indicates that the transmit FIFO buffer is not empty
#0
1
Indicates that the transmit FIFO buffer is empty
#1
TX_FIFO_COUNT
Transmit FIFO Data Count (read only)\nIndicates the valid data count of transmit FIFO buffer.
28
4
read-only
TX_FULL
Transmit FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[27].
27
1
read-only
0
Indicates that the transmit FIFO buffer is not full
#0
1
Indicates that the transmit FIFO buffer is full
#1
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (read only)
4
1
read-only
0
It indicates that the valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#0
1
It indicates that the valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bit TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: when the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1.
0
32
write-only
TMR01
TMR Register Map
TMR
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TCAP0
TCAP0
Timer0 Capture Data Register
0x10
read-only
n
0x0
0x0
TCAP
Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set, RSTCAPSEL (TTXCON[4]) is 0, and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred, the internal 24-bit up-timer value will be loaded into TCAP. User can read this register for the counter value.
0
24
read-only
TCAP1
TCAP1
Timer1 Capture Data Register
0x30
read-write
n
0x0
0x0
TCMPR0
TCMPR0
Timer0 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP.
0
24
read-write
TCMPR1
TCMPR1
Timer1 Compare Register
0x24
read-write
n
0x0
0x0
TCSR0
TCSR0
Timer0 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CACT
Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.
25
1
read-only
0
Timer is not active
#0
1
Timer is in active
#1
CAP_SRC
Capture Function Source
22
1
read-write
0
Capture Function source is from TxEX (Timer External Pin)
#0
1
Capture Function source is from ACMP(Analog Comparator Output)
#1
CEN
Timer Enable Bit
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
CRST
Timer Reset Bit\nSet this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0.
26
1
read-write
0
No effect
#0
1
Reset Timer's pre-scaled counter, internal 24-bit up-timer and CEN bit
#1
CTB
Counter Mode Enable Bit \nThis bit is the counter mode enable bit. When Timer is used as an event counter, this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of external pin by TX_PHASE field.
24
1
read-write
0
Disable counter mode
#0
1
Enable counter mode
#1
DBGACK_TMR
ICE debug mode acknowledge Disable (write-protected)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement disabled
#1
IE
Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated timer is equal to TCMPR.
29
1
read-write
0
Disable timer Interrupt
#0
1
Enable timer Interrupt
#1
INTR_TRG_EN
Inter-Timer Trigger Mode Enable\nThis bit controls if the inter-timer trigger mode is enabled.\nIf inter-timer trigger mode is enabled, the TIMER0/TIMER2 will be in counter mode and counting with external clock source or event. And, TIMER1/TIMER3 will be in trigger-counting mode of capture function.\nNote: For TIMER1 and TIMER3, this bit is ignored and the read back value is always 1'b0.
19
1
read-write
0
The inter-timer trigger mode is disabled
#0
1
The inter-timer trigger mode is enabled
#1
MODE
Timer Operating Mode
27
2
read-write
PERIODIC_SEL
Periodic Mode Behavior Selection Enable\nWhen users update TCMP, TDR will be reset to default value.
20
1
read-write
0
The behavior selection in periodic mode is disabled
#0
1
The behavior selection in periodic mode is enabled
#1
PRESCALE
Pre-scale Counter
0
8
read-write
TDR_EN
Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.
16
1
read-write
0
Timer Data Register update disable
#0
1
Timer Data Register update enable
#1
TOGGLE_PIN
Toggle Mode Output PIN
21
1
read-write
0
Toggle mode output to Tx (Timer Event Count Pin)
#0
1
Toggle mode output to TxEX (Timer External Pin)
#1
WAKE_EN
Wake up Enable\nWhen WAKE_EN is set and the TIF is set, the timer controller will generator a wake-up trigger event to CPU.
23
1
read-write
0
Wake-up trigger event disable
#0
1
Wake-up trigger event enable
#1
TCSR1
TCSR1
Timer1 Control and Status Register
0x20
read-write
n
0x0
0x0
TDR0
TDR0
Timer0 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register
User can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1
0
24
read-only
TDR1
TDR1
Timer1 Data Register
0x2C
read-write
n
0x0
0x0
TEXCON0
TEXCON0
Timer0 External Control Register
0x14
read-write
n
0x0
0x0
RSTCAPSEL
Timer External Reset Counter / Capture mode select
4
1
read-write
0
TEX transition is using as the timer capture function
#0
1
TEX transition is using as the timer counter reset function
#1
TCDB
Timer Counter pin De-bounce enable bit\nIf this bit is enabled, the edge of T0~T3 pin is detected with de-bounce circuit.
7
1
read-write
0
Disable De-bounce
#0
1
Enable De-bounce
#1
TEXDB
Timer External Capture pin De-bounce enable bit\nIf this bit is enabled, the edge of T0EX~T3EX pin is detected with de-bounce circuit.
6
1
read-write
0
Disable De-bounce
#0
1
Enable De-bounce
#1
TEXEN
Timer External Pin Enable. \nThis bit enables the reset/capture function on the TEX pin.
3
1
read-write
0
The TEX pin will be ignored
#0
1
The transition detected on the TEX pin will result in capture or reset of timer counter
#1
TEXIEN
Timer External interrupt Enable Bit
5
1
read-write
0
Disable timer External Interrupt
#0
1
Enable timer External Interrupt
#1
TEX_EDGE
Timer External Pin Edge Detect
1
2
read-write
0
a 1 to 0 transition on TEX will be detected
#00
1
a 0 to 1 transition on TEX will be detected
#01
2
either 1 to 0 or 0 to 1 transition on TEX will be detected
#10
3
Reserved
#11
TX_PHASE
Timer External Count Phase \nThis bit indicates the external count pin phase.
0
1
read-write
0
A falling edge of external count pin will be counted
#0
1
A rising edge of external count pin will be counted
#1
TEXCON1
TEXCON1
Timer1 External Control Register
0x34
read-write
n
0x0
0x0
TEXISR0
TEXISR0
Timer0 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
TEXIF
Timer External Interrupt Flag\nThis bit indicates the external interrupt status of Timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1,and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred. It is cleared by writing 1 to this bit.
0
1
read-write
TEXISR1
TEXISR1
Timer1 External Interrupt Status Register
0x38
read-write
n
0x0
0x0
TISR0
TISR0
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt status of Timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit.
0
1
read-write
TISR1
TISR1
Timer1 Interrupt Status Register
0x28
read-write
n
0x0
0x0
TMR23
TMR Register Map
TMR
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TCAP2
TCAP2
Timer2 Capture Data Register
0x10
read-only
n
0x0
0x0
TCAP
Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set, RSTCAPSEL (TTXCON[4]) is 0, and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred, the internal 24-bit up-timer value will be loaded into TCAP. User can read this register for the counter value.
0
24
read-only
TCAP3
TCAP3
Timer3 Capture Data Register
0x30
read-write
n
0x0
0x0
TCMPR2
TCMPR2
Timer2 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP.
0
24
read-write
TCMPR3
TCMPR3
Timer3 Compare Register
0x24
read-write
n
0x0
0x0
TCSR2
TCSR2
Timer2 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CACT
Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.
25
1
read-only
0
Timer is not active
#0
1
Timer is in active
#1
CAP_SRC
Capture Function Source
22
1
read-write
0
Capture Function source is from TxEX (Timer External Pin)
#0
1
Capture Function source is from ACMP(Analog Comparator Output)
#1
CEN
Timer Enable Bit
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
CRST
Timer Reset Bit\nSet this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0.
26
1
read-write
0
No effect
#0
1
Reset Timer's pre-scaled counter, internal 24-bit up-timer and CEN bit
#1
CTB
Counter Mode Enable Bit \nThis bit is the counter mode enable bit. When Timer is used as an event counter, this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of external pin by TX_PHASE field.
24
1
read-write
0
Disable counter mode
#0
1
Enable counter mode
#1
DBGACK_TMR
ICE debug mode acknowledge Disable (write-protected)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement disabled
#1
IE
Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated timer is equal to TCMPR.
29
1
read-write
0
Disable timer Interrupt
#0
1
Enable timer Interrupt
#1
INTR_TRG_EN
Inter-Timer Trigger Mode Enable\nThis bit controls if the inter-timer trigger mode is enabled.\nIf inter-timer trigger mode is enabled, the TIMER0/TIMER2 will be in counter mode and counting with external clock source or event. And, TIMER1/TIMER3 will be in trigger-counting mode of capture function.\nNote: For TIMER1 and TIMER3, this bit is ignored and the read back value is always 1'b0.
19
1
read-write
0
The inter-timer trigger mode is disabled
#0
1
The inter-timer trigger mode is enabled
#1
MODE
Timer Operating Mode
27
2
read-write
PERIODIC_SEL
Periodic Mode Behavior Selection Enable\nWhen users update TCMP, TDR will be reset to default value.
20
1
read-write
0
The behavior selection in periodic mode is disabled
#0
1
The behavior selection in periodic mode is enabled
#1
PRESCALE
Pre-scale Counter
0
8
read-write
TDR_EN
Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.
16
1
read-write
0
Timer Data Register update disable
#0
1
Timer Data Register update enable
#1
TOGGLE_PIN
Toggle Mode Output PIN
21
1
read-write
0
Toggle mode output to Tx (Timer Event Count Pin)
#0
1
Toggle mode output to TxEX (Timer External Pin)
#1
WAKE_EN
Wake up Enable\nWhen WAKE_EN is set and the TIF is set, the timer controller will generator a wake-up trigger event to CPU.
23
1
read-write
0
Wake-up trigger event disable
#0
1
Wake-up trigger event enable
#1
TCSR3
TCSR3
Timer3 Control and Status Register
0x20
read-write
n
0x0
0x0
TDR2
TDR2
Timer2 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register
User can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1
0
24
read-only
TDR3
TDR3
Timer3 Data Register
0x2C
read-write
n
0x0
0x0
TEXCON2
TEXCON2
Timer2 External Control Register
0x14
read-write
n
0x0
0x0
RSTCAPSEL
Timer External Reset Counter / Capture mode select
4
1
read-write
0
TEX transition is using as the timer capture function
#0
1
TEX transition is using as the timer counter reset function
#1
TCDB
Timer Counter pin De-bounce enable bit\nIf this bit is enabled, the edge of T0~T3 pin is detected with de-bounce circuit.
7
1
read-write
0
Disable De-bounce
#0
1
Enable De-bounce
#1
TEXDB
Timer External Capture pin De-bounce enable bit\nIf this bit is enabled, the edge of T0EX~T3EX pin is detected with de-bounce circuit.
6
1
read-write
0
Disable De-bounce
#0
1
Enable De-bounce
#1
TEXEN
Timer External Pin Enable. \nThis bit enables the reset/capture function on the TEX pin.
3
1
read-write
0
The TEX pin will be ignored
#0
1
The transition detected on the TEX pin will result in capture or reset of timer counter
#1
TEXIEN
Timer External interrupt Enable Bit
5
1
read-write
0
Disable timer External Interrupt
#0
1
Enable timer External Interrupt
#1
TEX_EDGE
Timer External Pin Edge Detect
1
2
read-write
0
a 1 to 0 transition on TEX will be detected
#00
1
a 0 to 1 transition on TEX will be detected
#01
2
either 1 to 0 or 0 to 1 transition on TEX will be detected
#10
3
Reserved
#11
TX_PHASE
Timer External Count Phase \nThis bit indicates the external count pin phase.
0
1
read-write
0
A falling edge of external count pin will be counted
#0
1
A rising edge of external count pin will be counted
#1
TEXCON3
TEXCON3
Timer3 External Control Register
0x34
read-write
n
0x0
0x0
TEXISR2
TEXISR2
Timer2 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
TEXIF
Timer External Interrupt Flag\nThis bit indicates the external interrupt status of Timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1,and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred. It is cleared by writing 1 to this bit.
0
1
read-write
TEXISR3
TEXISR3
Timer3 External Interrupt Status Register
0x38
read-write
n
0x0
0x0
TISR2
TISR2
Timer2 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt status of Timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit.
0
1
read-write
TISR3
TISR3
Timer3 Interrupt Status Register
0x28
read-write
n
0x0
0x0
UART0
UART Register Map
UART
0x0
0x0
0x30
registers
n
UA_ALT_CSR
UA_ALT_CSR
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address match value register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LIN_RX_EN
LIN RX Enable
6
1
read-write
0
Disable LIN RX mode
#0
1
Enable LIN RX mode
#1
LIN_TX_EN
LIN TX Break Mode Enable\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
Disable LIN TX Break Mode
#0
1
Enable LIN TX Break Mode
#1
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode.
9
1
read-write
0
Disable RS-485 Auto Address Detection Operation Mode (AAD)
#0
1
Enable RS-485 Auto Address Detection Operation Mode (AAD)
#1
RS485_ADD_EN
RS-485 Address Detection Enable\nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
Disable address detection mode
#0
1
Enable address detection mode
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
Disable RS-485 Auto Direction Operation Mode (AUO)
#0
1
Enable RS-485 Auto Direction Operation Mode (AUO)
#1
RS485_NMM
RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It can't be active with RS-485_AAD operation mode.
8
1
read-write
0
Disable RS-485 Normal Multi-drop Operation Mode (NMM)
#0
1
Enable RS-485 Normal Multi-drop Operation Mode (NMM)
#1
UA_LIN_BKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote: This break field length is UA_LIN_BKFL + 2
0
4
read-write
UA_BAUD
UA_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BRD
Baud Rate Divider\nThe field indicated the baud rate divider
0
16
read-write
DIVIDER_X
Divider X
24
4
read-write
DIV_X_EN
Divider X Enable\nRefer to the table below for more information.\nNote: When in IrDA mode, this bit must disable.
29
1
read-write
0
Disable divider X (the equation of M = 16)
#0
1
Enable divider X (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
#1
DIV_X_ONE
Divider X equal 1\nRefer to the Table 6.114 below for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3)
#1
UA_FCR
UA_FCR
UART FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level
4
4
read-write
RFR
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
1
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the RX internal state machine and pointers
#1
RTS_TRI_LEV
RTS Trigger Level for Auto-flow Control Use
16
4
read-write
RX_DIS
Receiver Disable register.\nThe receiver is disabled or not (set 1 is disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.
8
1
read-write
0
Enable Receiver
#0
1
Disable Receiver
#1
TFR
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
2
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the TX internal state machine and pointers
#1
UA_FSR
UA_FSR
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
BIF
Break Interrupt Flag (Read Only)
This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to UA_FCR [RFR]
6
1
read-only
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to UA_FCR [RFR]
5
1
read-only
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to UA_FCR[RFR]
4
1
read-only
RS485_ADD_DETF
RS-485 Address Byte Detection Flag (Read Only)\nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-only
RX_EMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RX_FULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RX_POINTER is equal to 16, otherwise is cleared by hardware.
15
1
read-only
RX_OVER_IF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-only
RX_POINTER
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.\nWhen RX_POINTER is equal to 16, RX_FULL is set. At this moment, RX_POINTER is cleared immediately by hardware.
8
6
read-only
TE_FLAG
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TX_EMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
TX_FULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to 16, otherwise is cleared by hardware.
23
1
read-only
TX_OVER_IF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it.
24
1
read-only
TX_POINTER
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.\nWhen TX_POINTER is equal to 16, TX_FULL is set. At this moment, TX_POINTER is cleared immediately by hardware.
16
6
read-only
UA_FUN_SEL
UA_FUN_SEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable
0
2
read-write
0
UART Function
#00
1
Enable LIN Function
#01
2
Enable IrDA Function
#10
3
Enable RS-485 Function
#11
UA_IER
UA_IER
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
AUTO_CTS_EN
CTS Auto Flow Control Enable\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
Disable CTS auto flow control
#0
1
Enable CTS auto flow control
#1
AUTO_RTS_EN
RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal.
12
1
read-write
0
Disable RTS auto flow control
#0
1
Enable RTS auto flow control
#1
BUF_ERR_IEN
Buffer Error Interrupt Enable
5
1
read-write
0
Mask off INT_BUF_ERR
#0
1
Enable INT_BUF_ERR
#1
LIN_RX_BRK_IEN
LIN RX Break Field Detected Interrupt Enable\nNote: This field is used for LIN function mode.
8
1
read-write
0
Mask off Lin bus RX break filed interrupt
#0
1
Enable Lin bus RX break filed interrupt
#1
MODEM_IEN
Modem Status Interrupt Enable
3
1
read-write
0
Mask off INT_MODEM
#0
1
Enable INT_MODEM
#1
RDA_IEN
Receive Data Available Interrupt Enable.
0
1
read-write
0
Mask off INT_RDA
#0
1
Enable INT_RDA
#1
RLS_IEN
Receive Line Status Interrupt Enable
2
1
read-write
0
Mask off INT_RLS
#0
1
Enable INT_RLS
#1
RTO_IEN
RX Time Out Interrupt Enable
4
1
read-write
0
Mask off INT_TOUT
#0
1
Enable INT_TOUT
#1
THRE_IEN
Transmit Holding Register Empty Interrupt Enable
1
1
read-write
0
Mask off INT_THRE
#0
1
Enable INT_THRE
#1
TIME_OUT_EN
Time Out Counter Enable
11
1
read-write
0
Disable Time-out counter
#0
1
Enable Time-out counter
#1
WAKE_EN
Wake Up CPU Function Enable
6
1
read-write
0
Disable UART wake up CPU function
#0
1
Enable wake up function, when the system is in deep sleep mode, an external CTS change will wake up CPU from deep sleep mode
#1
UA_IRCR
UA_IRCR
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
INV_RX
INV_RX
6
1
read-write
0
No inversion
#0
1
Inverse RX input signal
#1
INV_TX
INV_TX
5
1
read-write
0
No inversion
#0
1
Inverse TX output signal
#1
TX_SELECT
TX_SELECT
1
1
read-write
0
Enable IrDA receiver
#0
1
Enable IrDA transmitter
#1
UA_ISR
UA_ISR
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUF_ERR_IF
Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows or Break Interrupt Flag or Parity Error Flag or Frame Error Flag (TX_OVER_IF or RX_OVER_IF ) is set. When BUF_ERR_IF is set, the transfer is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.
5
1
read-only
BUF_ERR_INT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
The buffer error interrupt is generated
#1
LIN_RX_BREAK_IF
LIN Bus RX Break Field Detected Flag (Read Only)\nThis bit is set when RX received LIN Break Field. If UA_IER [LIN_RX_BRK_IEN] is enabled the LIN RX Break interrupt will be generated.\nNote: This bit is read only, but can be cleared by writing '1' to it.
7
1
read-only
LIN_RX_BREAK_INT
LIN Bus RX Break Field Detected Interrupt Indicator (Read Only)\nThis bit is set if LIN_RX_BRK_IEN and LIN_RX_BREAK_IF are both set to 1.
15
1
read-only
0
No LIN RX Break interrupt is generated
#0
1
The LIN RX Break interrupt is generated
#1
MODEM_IF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
3
1
read-only
MODEM_INT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.
11
1
read-only
0
No Modem interrupt is generated
#0
1
The Modem interrupt is generated
#1
RDA_IF
Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDA_INT
Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
The RDA interrupt is generated
#1
RLS_IF
Receive Line Interrupt Flag (Read Only).\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLS_INT
Receive Line Status Interrupt Indicator (Read Only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
The RLS interrupt is generated
#1
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
1
1
read-only
THRE_INT
Transmit Holding Register Empty Interrupt Indicator (Read Only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
The THRE interrupt is generated
#1
TOUT_IF
Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
4
1
read-only
TOUT_INT
Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.
12
1
read-only
0
No Tout interrupt is generated
#0
1
The Tout interrupt is generated
#1
UA_LCR
UA_LCR
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set.
4
1
read-write
0
Odd number of logic 1's are transmitted or checked in the data word and parity bits
#0
1
Even number of logic 1's are transmitted or checked in the data word and parity bits
#1
NSB
Number of STOP bit
2
1
read-write
0
1 STOP bit
#0
1
2 STOP bits (1.5 STOP bits if WLS[1:0]=00)
#1
PBE
Parity Bit Enable
3
1
read-write
0
Parity bit is not generated (transmit data) or checked (receive data) during transfer
#0
1
Parity bit is generated or checked between the last data word bit and stop bit of the serial data
#1
SPE
Stick Parity Enable
5
1
read-write
0
Disable stick parity
#0
1
When bits PBE , EPE and SPE are set, the parity bit is transmitted and checked as cleared. When PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as set
#1
WLS
Word Length Select
0
2
read-write
UA_MCR
UA_MCR
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
LEV_RTS
RTS Trigger Level\nThis bit can change the RTS trigger level.
9
1
read-write
0
low level triggered
#0
1
high level triggered
#1
RTS
RTS (Request-To-Send) Signal
1
1
read-write
0
Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered)
#0
1
Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered)
#1
RTS_ST
RTS Pin State (Read Only)\nThis bit is the output pin status of RTS.
13
1
read-only
UA_MSR
UA_MSR
UART Modem Status Register
0x14
read-write
n
0x0
0x0
CTS_ST
CTS Pin Status (Read Only)\nThis bit is the pin status of CTS when UART clock is enabled, and CTS multi-function port is selected.
4
1
read-only
DCTSF
Detect CTS State Change Flag (Read Only)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nSoftware can write 1 to clear this bit to zero
0
1
read-only
LEV_CTS
CTS Trigger Level\nThis bit can change the CTS trigger level.
8
1
read-write
0
low level triggered
#0
1
high level triggered
#1
UA_RBR
UA_RBR
UART Receive Buffer Register
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first).
0
8
read-only
UA_THR
UA_THR
UART Transmit Holding Register
UA_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first).
0
8
write-only
UA_TOR
UA_TOR
UART Time Out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay time value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit.
8
8
read-write
TOIC
Time Out Interrupt Comparator
0
8
read-write
UART1
UART Register Map
UART
0x0
0x0
0x30
registers
n
UA_ALT_CSR
UA_ALT_CSR
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address match value register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LIN_RX_EN
LIN RX Enable
6
1
read-write
0
Disable LIN RX mode
#0
1
Enable LIN RX mode
#1
LIN_TX_EN
LIN TX Break Mode Enable\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
Disable LIN TX Break Mode
#0
1
Enable LIN TX Break Mode
#1
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode.
9
1
read-write
0
Disable RS-485 Auto Address Detection Operation Mode (AAD)
#0
1
Enable RS-485 Auto Address Detection Operation Mode (AAD)
#1
RS485_ADD_EN
RS-485 Address Detection Enable\nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
Disable address detection mode
#0
1
Enable address detection mode
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
Disable RS-485 Auto Direction Operation Mode (AUO)
#0
1
Enable RS-485 Auto Direction Operation Mode (AUO)
#1
RS485_NMM
RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It can't be active with RS-485_AAD operation mode.
8
1
read-write
0
Disable RS-485 Normal Multi-drop Operation Mode (NMM)
#0
1
Enable RS-485 Normal Multi-drop Operation Mode (NMM)
#1
UA_LIN_BKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote: This break field length is UA_LIN_BKFL + 2
0
4
read-write
UA_BAUD
UA_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BRD
Baud Rate Divider\nThe field indicated the baud rate divider
0
16
read-write
DIVIDER_X
Divider X
24
4
read-write
DIV_X_EN
Divider X Enable\nRefer to the table below for more information.\nNote: When in IrDA mode, this bit must disable.
29
1
read-write
0
Disable divider X (the equation of M = 16)
#0
1
Enable divider X (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
#1
DIV_X_ONE
Divider X equal 1\nRefer to the Table 6.114 below for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3)
#1
UA_FCR
UA_FCR
UART FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level
4
4
read-write
RFR
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
1
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the RX internal state machine and pointers
#1
RTS_TRI_LEV
RTS Trigger Level for Auto-flow Control Use
16
4
read-write
RX_DIS
Receiver Disable register.\nThe receiver is disabled or not (set 1 is disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.
8
1
read-write
0
Enable Receiver
#0
1
Disable Receiver
#1
TFR
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
2
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the TX internal state machine and pointers
#1
UA_FSR
UA_FSR
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
BIF
Break Interrupt Flag (Read Only)
This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to UA_FCR [RFR]
6
1
read-only
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to UA_FCR [RFR]
5
1
read-only
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to UA_FCR[RFR]
4
1
read-only
RS485_ADD_DETF
RS-485 Address Byte Detection Flag (Read Only)\nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-only
RX_EMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RX_FULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RX_POINTER is equal to 16, otherwise is cleared by hardware.
15
1
read-only
RX_OVER_IF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-only
RX_POINTER
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.\nWhen RX_POINTER is equal to 16, RX_FULL is set. At this moment, RX_POINTER is cleared immediately by hardware.
8
6
read-only
TE_FLAG
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TX_EMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
TX_FULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to 16, otherwise is cleared by hardware.
23
1
read-only
TX_OVER_IF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it.
24
1
read-only
TX_POINTER
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.\nWhen TX_POINTER is equal to 16, TX_FULL is set. At this moment, TX_POINTER is cleared immediately by hardware.
16
6
read-only
UA_FUN_SEL
UA_FUN_SEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable
0
2
read-write
0
UART Function
#00
1
Enable LIN Function
#01
2
Enable IrDA Function
#10
3
Enable RS-485 Function
#11
UA_IER
UA_IER
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
AUTO_CTS_EN
CTS Auto Flow Control Enable\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
Disable CTS auto flow control
#0
1
Enable CTS auto flow control
#1
AUTO_RTS_EN
RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal.
12
1
read-write
0
Disable RTS auto flow control
#0
1
Enable RTS auto flow control
#1
BUF_ERR_IEN
Buffer Error Interrupt Enable
5
1
read-write
0
Mask off INT_BUF_ERR
#0
1
Enable INT_BUF_ERR
#1
LIN_RX_BRK_IEN
LIN RX Break Field Detected Interrupt Enable\nNote: This field is used for LIN function mode.
8
1
read-write
0
Mask off Lin bus RX break filed interrupt
#0
1
Enable Lin bus RX break filed interrupt
#1
MODEM_IEN
Modem Status Interrupt Enable
3
1
read-write
0
Mask off INT_MODEM
#0
1
Enable INT_MODEM
#1
RDA_IEN
Receive Data Available Interrupt Enable.
0
1
read-write
0
Mask off INT_RDA
#0
1
Enable INT_RDA
#1
RLS_IEN
Receive Line Status Interrupt Enable
2
1
read-write
0
Mask off INT_RLS
#0
1
Enable INT_RLS
#1
RTO_IEN
RX Time Out Interrupt Enable
4
1
read-write
0
Mask off INT_TOUT
#0
1
Enable INT_TOUT
#1
THRE_IEN
Transmit Holding Register Empty Interrupt Enable
1
1
read-write
0
Mask off INT_THRE
#0
1
Enable INT_THRE
#1
TIME_OUT_EN
Time Out Counter Enable
11
1
read-write
0
Disable Time-out counter
#0
1
Enable Time-out counter
#1
WAKE_EN
Wake Up CPU Function Enable
6
1
read-write
0
Disable UART wake up CPU function
#0
1
Enable wake up function, when the system is in deep sleep mode, an external CTS change will wake up CPU from deep sleep mode
#1
UA_IRCR
UA_IRCR
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
INV_RX
INV_RX
6
1
read-write
0
No inversion
#0
1
Inverse RX input signal
#1
INV_TX
INV_TX
5
1
read-write
0
No inversion
#0
1
Inverse TX output signal
#1
TX_SELECT
TX_SELECT
1
1
read-write
0
Enable IrDA receiver
#0
1
Enable IrDA transmitter
#1
UA_ISR
UA_ISR
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUF_ERR_IF
Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows or Break Interrupt Flag or Parity Error Flag or Frame Error Flag (TX_OVER_IF or RX_OVER_IF ) is set. When BUF_ERR_IF is set, the transfer is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.
5
1
read-only
BUF_ERR_INT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
The buffer error interrupt is generated
#1
LIN_RX_BREAK_IF
LIN Bus RX Break Field Detected Flag (Read Only)\nThis bit is set when RX received LIN Break Field. If UA_IER [LIN_RX_BRK_IEN] is enabled the LIN RX Break interrupt will be generated.\nNote: This bit is read only, but can be cleared by writing '1' to it.
7
1
read-only
LIN_RX_BREAK_INT
LIN Bus RX Break Field Detected Interrupt Indicator (Read Only)\nThis bit is set if LIN_RX_BRK_IEN and LIN_RX_BREAK_IF are both set to 1.
15
1
read-only
0
No LIN RX Break interrupt is generated
#0
1
The LIN RX Break interrupt is generated
#1
MODEM_IF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
3
1
read-only
MODEM_INT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.
11
1
read-only
0
No Modem interrupt is generated
#0
1
The Modem interrupt is generated
#1
RDA_IF
Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDA_INT
Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
The RDA interrupt is generated
#1
RLS_IF
Receive Line Interrupt Flag (Read Only).\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLS_INT
Receive Line Status Interrupt Indicator (Read Only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
The RLS interrupt is generated
#1
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
1
1
read-only
THRE_INT
Transmit Holding Register Empty Interrupt Indicator (Read Only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
The THRE interrupt is generated
#1
TOUT_IF
Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
4
1
read-only
TOUT_INT
Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.
12
1
read-only
0
No Tout interrupt is generated
#0
1
The Tout interrupt is generated
#1
UA_LCR
UA_LCR
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set.
4
1
read-write
0
Odd number of logic 1's are transmitted or checked in the data word and parity bits
#0
1
Even number of logic 1's are transmitted or checked in the data word and parity bits
#1
NSB
Number of STOP bit
2
1
read-write
0
1 STOP bit
#0
1
2 STOP bits (1.5 STOP bits if WLS[1:0]=00)
#1
PBE
Parity Bit Enable
3
1
read-write
0
Parity bit is not generated (transmit data) or checked (receive data) during transfer
#0
1
Parity bit is generated or checked between the last data word bit and stop bit of the serial data
#1
SPE
Stick Parity Enable
5
1
read-write
0
Disable stick parity
#0
1
When bits PBE , EPE and SPE are set, the parity bit is transmitted and checked as cleared. When PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as set
#1
WLS
Word Length Select
0
2
read-write
UA_MCR
UA_MCR
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
LEV_RTS
RTS Trigger Level\nThis bit can change the RTS trigger level.
9
1
read-write
0
low level triggered
#0
1
high level triggered
#1
RTS
RTS (Request-To-Send) Signal
1
1
read-write
0
Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered)
#0
1
Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered)
#1
RTS_ST
RTS Pin State (Read Only)\nThis bit is the output pin status of RTS.
13
1
read-only
UA_MSR
UA_MSR
UART Modem Status Register
0x14
read-write
n
0x0
0x0
CTS_ST
CTS Pin Status (Read Only)\nThis bit is the pin status of CTS when UART clock is enabled, and CTS multi-function port is selected.
4
1
read-only
DCTSF
Detect CTS State Change Flag (Read Only)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nSoftware can write 1 to clear this bit to zero
0
1
read-only
LEV_CTS
CTS Trigger Level\nThis bit can change the CTS trigger level.
8
1
read-write
0
low level triggered
#0
1
high level triggered
#1
UA_RBR
UA_RBR
UART Receive Buffer Register
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first).
0
8
read-only
UA_THR
UA_THR
UART Transmit Holding Register
UA_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first).
0
8
write-only
UA_TOR
UA_TOR
UART Time Out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay time value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit.
8
8
read-write
TOIC
Time Out Interrupt Comparator
0
8
read-write
WDT
WDT Register Map
WDT
0x0
0x0
0x8
registers
n
WTCR
WTCR
Watchdog Timer Control Register
0x0
-1
read-write
n
0x0
0x0
DBGACK_WDT
ICE debug mode acknowledge Disable (write-protected)\nWatchdog Timer counter will keep going no matter ICE debug mode acknowledged or not.
31
1
read-write
0
ICE debug mode acknowledgement effects Watchdog Timer counting
#0
1
ICE debug mode acknowledgement disabled
#1
WTE
Watchdog Timer Enable (write protection bits)
7
1
read-write
0
Disable the Watchdog timer (This action will reset the internal counter)
#0
1
Enable the Watchdog timer
#1
WTIE
Watchdog Timer Interrupt Enable (write protection bits)
6
1
read-write
0
Disable the Watchdog timer interrupt
#0
1
Enable the Watchdog timer interrupt
#1
WTIF
Watchdog Timer Interrupt Flag\nWhen watchdog timeout, the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. \nNote: This bit is cleared by writing 1 to this bit.
3
1
read-write
0
Watchdog timer interrupt did not occur
#0
1
Watchdog timer interrupt occurs
#1
WTIS
Watchdog Timer Interval Select (write protection bits)
8
3
read-write
WTR
Clear Watchdog Timer (write-protection bit)\nSet this bit will clear the Watchdog timer.\nNote: This bit will be auto cleared by hardware
0
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Reset the contents of the Watchdog timer
#1
WTRE
Watchdog Timer Reset Enable\nSetting this bit will enable the Watchdog timer reset function.
1
1
read-write
0
Disable Watchdog timer reset function
#0
1
Enable Watchdog timer reset function
#1
WTRF
Watchdog Timer Reset Flag\nWhen the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If WTRE is disabled, then the Watchdog timer has no effect on this bit.\nNote: Write 1 to clear this bit to zero.
2
1
read-write
0
Watchdog timer reset did not occur
#0
1
Watchdog timer reset occurs
#1
WTWKE
Watchdog Timer Wake-up Function Enable bit (write-protection bit)\nNote: Chip can wake-up by WDT only if WDT clock source select RC10K
4
1
read-write
0
Disable Watchdog timer wake-up chip function
#0
1
Enable the Wake-up function that Watchdog timer timeout can wake-up chip from power down mode
#1
WTWKF
Watchdog Timer Wake-up Flag\nIf Watchdog timer causes chip wakes up from power down mode, this bit will be set to high. It must be cleared by software with a write 1 to this bit.
5
1
read-write
0
Watchdog timer does not cause chip wake-up
#0
1
Chip wake-up from idle or power down mode by Watchdog timeout
#1
WTCRALT
WTCRALT
Watchdog Timer Alternative Control Register
0x4
read-write
n
0x0
0x0
WTRDSEL
Watchdog Timer Reset Delay Select (Write-protection Bits)
When WDT time-out happened, software has a time named WDT reset delay period to clear WDT counter to prevent WDT time-out reset happened. Software can select a suitable value of WDT reset delay period for different WDT time-out period.
These bits are protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
This register will be reset to 0 if WDT time-out reset happened
0
2
read-write
0
Watchdog Timer reset delay period is (1024+2) * WDT_CLK
#00
1
Watchdog Timer reset delay period is (128+2) * WDT_CLK
#01
2
Watchdog Timer reset delay period is (16+2) * WDT_CLK
#10
3
Watchdog Timer reset delay period is (1+2) * WDT_CLK
#11
WWDT
WWDT Register Map
WWDT
0x0
0x0
0x10
registers
n
WWDTCR
WWDTCR
Window Watchdog Timer Control Register
0x4
-1
read-write
n
0x0
0x0
DBGACK_WWDT
ICE debug mode acknowledge Disable
31
1
read-write
0
WWDT counter stopped if system is in Debug mode
#0
1
WWDT still counted even system is in Debug mode
#1
PERIODSEL
WWDT Pre-scale Period Select
8
4
read-write
WINCMP
WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: Software can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If Software writes WWDTRLD when current WWDT counter value larger than WINCMP, WWDT reset signal will generate immediately.
16
6
read-write
WWDTEN
WWDT Enable\nSet this bit to enable Window Watchdog Timer counter counting.
0
1
read-write
0
Window Watchdog Timer counter is stopped
#0
1
Window Watchdog Timer counter is starting counting
#1
WWDTIE
WWDT Interrupt Enable\nSetting this bit to enable the Window Watchdog Timer time-out interrupt function.
1
1
read-write
0
WWDT time-out interrupt function Disabled if WWDTIF (WWDTSR[0] WWDT compare match interrupt flag) is 1
#0
1
WWDT time-out interrupt function Enabled if WWDTIF (WWDTSR[0] WWDT compare match interrupt flag) is 1
#1
WWDTCVR
WWDTCVR
Window Watchdog Timer Counter Value Register
0xC
-1
read-only
n
0x0
0x0
WWDTCVAL
WWDT Counter Value\nThis register reflects the current WWDT counter value and this register is read only
0
6
read-only
WWDTRLD
WWDTRLD
Window Watchdog Timer Reload Counter Register
0x0
write-only
n
0x0
0x0
WWDTRLD
WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. \nNote: Software can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If software writes WWDTRLD when current WWDT counter value larger than WINCMP, WWDT reset signal will generate immediately.
0
32
write-only
WWDTSR
WWDTSR
Window Watchdog Timer Status Register
0x8
read-write
n
0x0
0x0
WWDTIF
WWDT Compare Match Interrupt Flag\nWhen current WWDT counter value matches to WWCMP, this bit is set to 1. This bit will be cleared by writing 1 to itself.
0
1
read-write
WWDTRF
WWDT Reset Flag\nWhen WWDT counter counts down to 0 or writes WWDTRLD during current WWDT counter value larger than WINCMP, chip will be reset and this bit is set to 1. This bit will be cleared to 0 by writing 1 to itself.
1
1
read-write