nuvoTon
NUC100BN_v1
2024.04.27
NUC100BN_v1 SVD file
8
32
ADC
ADC Register Map
ADC
0x0
0x0
0x38
registers
n
0x40
0x4
registers
n
ADCALR
ADCALR
A/D Calibration Register
0x34
read-write
n
0x0
0x0
CALDONE
Calibration Complete\nWhen writing 0 to CALEN bit, CALDONE bit is cleared by hardware immediately. It is a read only bit.
1
1
read-write
0
A/D converter has not been calibrated or calibration is in progress if CALEN bit is set
#0
1
A/D converter self-calibration is done
#1
CALEN
Self-calibration Enable\nSoftware can set this bit to 1 to enable A/D converter to do self-calibration function. It needs 127 ADC clocks to complete calibration. This bit must be kept at 1 after CALDONE asserted. Clearing this bit will disable self-calibration function.
0
1
read-write
0
Self-calibration Disabled
#0
1
Self-calibration Enabled
#1
ADCHER
ADCHER
A/D Channel Enable Register
0x24
read-write
n
0x0
0x0
CHEN0
Analog Input Channel 0 Enable\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CHEN1
Analog Input Channel 1 Enable\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
CHEN2
Analog Input Channel 2 Enable\n
2
1
read-write
0
Disabled
#0
1
Enabled
#1
CHEN3
Analog Input Channel 3 Enable\n
3
1
read-write
0
Disabled
#0
1
Enabled
#1
CHEN4
Analog Input Channel 4 Enable\n
4
1
read-write
0
Disabled
#0
1
Enabled
#1
CHEN5
Analog Input Channel 5 Enable\n
5
1
read-write
0
Disabled
#0
1
Enabled
#1
CHEN6
Analog Input Channel 6 Enable\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
CHEN7
Analog Input Channel 7 Enable\n
7
1
read-write
0
Disabled
#0
1
Enabled
#1
PRESEL
Analog Input Channel 7 select\nNote:\nWhen software selects the band-gap voltage as the analog input source of ADC channel 7, ADC clock rate needs to be limited to lower than 300 kHz.
8
2
read-write
0
External analog input
#00
1
Internal band-gap voltage
#01
2
Internal temperature sensor
#10
3
Reserved
#11
ADCMPR0
ADCMPR0
A/D Compare Register 0
0x28
read-write
n
0x0
0x0
CMPCH
Compare Channel Selection\n
3
3
read-write
0
Channel 0 conversion result is selected to be compared
#000
1
Channel 1 conversion result is selected to be compared
#001
2
Channel 2 conversion result is selected to be compared
#010
3
Channel 3 conversion result is selected to be compared
#011
4
Channel 4 conversion result is selected to be compared
#100
5
Channel 5 conversion result is selected to be compared
#101
6
Channel 6 conversion result is selected to be compared
#110
7
Channel 7 conversion result is selected to be compared
#111
CMPCOND
Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
2
1
read-write
0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one
#0
1
Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one
#1
CMPD
Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nThe following description is only support in NuMicro( NUC100/NUC120 Low Density:\nWhen DMOF bit is set to 0, ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format.\nWhen DMOF bit is set to 1, ADC comparator compares CMPD with conversion result with 2'complement format. CMPD should be filled in 2'complement format.
16
12
read-write
CMPEN
Compare Enable\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register.
0
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
CMPIE
Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Compare function interrupt Disabled
#0
1
Compare function interrupt Enabled
#1
CMPMATCNT
Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
8
4
read-write
ADCMPR1
ADCMPR1
A/D Compare Register 1
0x2C
read-write
n
0x0
0x0
ADCR
ADCR
A/D Control Register
0x20
read-write
n
0x0
0x0
ADEN
A/D Converter Enable\nBefore starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
ADIE
A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.
1
1
read-write
0
A/D interrupt function Disabled
#0
1
A/D interrupt function Enabled
#1
ADMD
A/D Converter Operation Mode\nWhen changing the operation mode, software should disable ADST bit firstly.
2
2
read-write
0
Single conversion
#00
1
Reserved
#01
2
Single-cycle scan
#10
3
Continuous scan
#11
ADST
A/D Conversion Start\nADST bit can be set to 1 from two sources: software and external pin STADC. ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode, A/D conversion is continuously performed until software write 0 to this bit or chip reset.
11
1
read-write
0
Conversion stopped and A/D converter enter idle state
#0
1
Conversion start
#1
DIFFEN
Differential Input Mode Enable\n
10
1
read-write
0
Single-end analog input mode
#0
1
Differential analog input mode
#1
DMOF
A/D Differential Input Mode Output Format (Only Supported in NuMicro( NUC100/NUC120 Low Density)\n
31
1
read-write
0
A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format
#0
1
A/D Conversion result will be filled in RSLT at ADDRx registers with 2'complement format
#1
PTEN
PDMA Transfer Enable\n
9
1
read-write
0
PDMA data transfer Disabled
#0
1
PDMA data transfer in ADDR 0~7 Enabled
#1
TRGCOND
External Trigger Conditions\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.\n
6
2
read-write
0
Low level
#00
1
High level
#01
2
Falling edge
#10
3
Rising edge
#11
TRGEN
External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin.\nADC external trigger function is only supported in single-cycle scan mode.
8
1
read-write
0
Disabled
#0
1
Enabled
#1
TRGS
Hardware Trigger Source\nSoftware should disable TRGEN and ADST before change TRGS.\nIn hardware trigger mode, the ADST bit is set by the external trigger from STADC.
4
2
read-write
0
A/D conversion is started by external STADC pin
#00
ADDR0
ADDR0
A/D Data Register 0
0x0
read-only
n
0x0
0x0
OVERRUN
Over Run Flag\nIf converted data in RSLT[15:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a read only bit
16
1
read-only
0
Data in RSLT[15:0] is recent conversion result
#0
1
Data in RSLT[15:0] is overwrite
#1
RSLT
A/D Conversion Result\nThis field contains conversion result of ADC.\nFor NuMicro( NUC100/NUC120 Medium density, RSLT[15:12] always read as 0.\nThe following description is only support in NuMicro( NUC100/NUC120 Low Density:\nWhen DMOF bit (ADCR[31]) set to 0, 12-bit ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12].\nWhen DMOF bit (ADCR[31]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RSLT[11:0] and signed bits to will be filled in RSLT[15:12].
0
16
read-only
VALID
Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit
17
1
read-only
0
Data in RSLT[15:0] bits is not valid
#0
1
Data in RSLT[15:0] bits is valid
#1
ADDR1
ADDR1
A/D Data Register 1
0x4
read-write
n
0x0
0x0
ADDR2
ADDR2
A/D Data Register 2
0x8
read-write
n
0x0
0x0
ADDR3
ADDR3
A/D Data Register 3
0xC
read-write
n
0x0
0x0
ADDR4
ADDR4
A/D Data Register 4
0x10
read-write
n
0x0
0x0
ADDR5
ADDR5
A/D Data Register 5
0x14
read-write
n
0x0
0x0
ADDR6
ADDR6
A/D Data Register 6
0x18
read-write
n
0x0
0x0
ADDR7
ADDR7
A/D Data Register 7
0x1C
read-write
n
0x0
0x0
ADPDMA
ADPDMA
ADC PDMA Current Transfer Data
0x40
read-only
n
0x0
0x0
AD_PDMA
ADC PDMA Current Transfer Data Register\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.\nThis is a read only register.
0
12
read-only
ADSR
ADSR
A/D Status Register
0x30
read-write
n
0x0
0x0
ADF
A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\n1. When A/D conversion ends in Single mode\n2. When A/D conversion ends on all specified channels in Scan mode\nThis flag can be cleared by writing 1 to itself.
0
1
read-write
BUSY
BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.\nIt is read only.
3
1
read-write
0
A/D converter is in idle state
#0
1
A/D converter is busy at conversion
#1
CHANNEL
Current Conversion Channel\nIt is read only.
4
3
read-write
CMPF0
Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.\n
1
1
read-write
0
Conversion result in ADDR does not meet ADCMPR0 setting
#0
1
Conversion result in ADDR meets ADCMPR0 setting
#1
CMPF1
Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.\n
2
1
read-write
0
Conversion result in ADDR does not meet ADCMPR1 setting
#0
1
Conversion result in ADDR meets ADCMPR1 setting
#1
OVERRUN
Over Run flag\nIt is a mirror to OVERRUN bit in ADDRx\nIt is read only.
16
8
read-write
VALID
Data Valid flag\nIt is a mirror of VALID bit in ADDRx\nIt is read only.
8
8
read-write
CLK
CLK Register Map
CLK
0x0
0x0
0x28
registers
n
AHBCLK
AHBCLK
AHB Devices Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
EBI_EN
EBI Controller Clock Enable Control (NuMicro( NUC100/NUC120 Low Density Only)\n
3
1
read-write
0
EBI engine clock Disabled
#0
1
EBI engine clock Enabled
#1
ISP_EN
Flash ISP Controller Clock Enable Control\n
2
1
read-write
0
Flash ISP engine clock Disabled
#0
1
Flash ISP engine clock Enabled
#1
PDMA_EN
PDMA Controller Clock Enable Control\n
1
1
read-write
0
PDMA engine clock Disabled
#0
1
PDMA engine clock Enabled
#1
APBCLK
APBCLK
APB Devices Clock Enable Control Register
0x8
read-write
n
0x0
0x0
ACMP_EN
Analog Comparator Clock Enable\n
30
1
read-write
0
Analog Comparator Clock Disabled
#0
1
Analog Comparator Clock Enabled
#1
ADC_EN
Analog-Digital-Converter (ADC) Clock Enable\n
28
1
read-write
0
ADC clock Disabled
#0
1
ADC clock Enabled
#1
FDIV_EN
Frequency Divider Output Clock Enable\n
6
1
read-write
0
FDIV clock Disabled
#0
1
FDIV clock Enabled
#1
I2C0_EN
I2C0 Clock Enable\n
8
1
read-write
0
I2C0 clock Disabled
#0
1
I2C0 clock Enabled
#1
I2C1_EN
I2C1 Clock Enable\n
9
1
read-write
0
I2C1 clock Disabled
#0
1
I2C1 clock Enabled
#1
I2S_EN
I2S Clock Enable\n
29
1
read-write
0
I2S clock Disabled
#0
1
I2S clock Enabled
#1
PS2_EN
PS/2 Clock Enable\n
31
1
read-write
0
PS/2 clock Disabled
#0
1
PS/2 clock Enabled
#1
PWM01_EN
PWM_01 Clock Enable\n
20
1
read-write
0
PWM01 clock Disabled
#0
1
PWM01 clock Enabled
#1
PWM23_EN
PWM_23 Clock Enable\n
21
1
read-write
0
PWM23 clock Disabled
#0
1
PWM23 clock Enabled
#1
PWM45_EN
PWM_45 Clock Enable (NuMicro( NUC100/NUC120 Medium Density Only)\n
22
1
read-write
0
PWM45 clock Disabled
#0
1
PWM45 clock Enabled
#1
PWM67_EN
PWM_67 Clock Enable (NuMicro( NUC100/NUC120 Medium Density Only)\n
23
1
read-write
0
PWM67 clock Disabled
#0
1
PWM67 clock Enabled
#1
RTC_EN
Real-Time-Clock APB interface Clock Enable\nThis bit is used to control the RTC APB clock only, The RTC engine clock source is from the external 32.768 kHz low speed crystal.\n
1
1
read-write
0
RTC clock Disabled
#0
1
RTC clock Enabled
#1
SPI0_EN
SPI0 Clock Enable\n
12
1
read-write
0
SPI0 clock Disabled
#0
1
SPI0 clock Enabled
#1
SPI1_EN
SPI1 Clock Enable\n
13
1
read-write
0
SPI1 clock Disabled
#0
1
SPI1 clock Enabled
#1
SPI2_EN
SPI2 Clock Enable (NuMicro( NUC100/NUC120 Medium Density Only)\n
14
1
read-write
0
SPI2 clock Disabled
#0
1
SPI2 clock Enabled
#1
SPI3_EN
SPI3 Clock Enable (NuMicro( NUC100/NUC120 Medium Density Only)\n
15
1
read-write
0
SPI3 clock Disabled
#0
1
SPI3 clock Enabled
#1
TMR0_EN
Timer0 Clock Enable\n
2
1
read-write
0
Timer0 clock Disabled
#0
1
Timer0 clock Enabled
#1
TMR1_EN
Timer1 Clock Enable\n
3
1
read-write
0
Timer1 clock Disabled
#0
1
Timer1 clock Enabled
#1
TMR2_EN
Timer2 Clock Enable\n
4
1
read-write
0
Timer2 clock Disabled
#0
1
Timer2 clock Enabled
#1
TMR3_EN
Timer3 Clock Enable\n
5
1
read-write
0
Timer3 clock Disabled
#0
1
Timer3 clock Enabled
#1
UART0_EN
UART0 Clock Enable\n
16
1
read-write
0
UART0 clock Disabled
#0
1
UART0 clock Enabled
#1
UART1_EN
UART1 Clock Enable\n
17
1
read-write
0
UART1 clock Disabled
#0
1
UART1 clock Enabled
#1
UART2_EN
UART2 Clock Enable (NuMicro( NUC100/NUC120 Medium Density Only)\n
18
1
read-write
0
UART2 clock Disabled
#0
1
UART2 clock Enabled
#1
USBD_EN
USB 2.0 FS Device Controller Clock Enable\n
27
1
read-write
0
USB clock Disabled
#0
1
USB clock Enabled
#1
WDT_EN
Watchdog Timer Clock Enable (write-protection bit)
This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
1
read-write
0
Watchdog Timer Clock Disabled
#0
1
Watchdog Timer Clock Enabled
#1
CLKDIV
CLKDIV
Clock Divider Number Register
0x18
read-write
n
0x0
0x0
ADC_N
ADC clock divide number from ADC Clock Source\n
16
8
read-write
HCLK_N
HCLK Clock Divide Number from HCLK Clock Source\n
0
4
read-write
UART_N
UART Clock Divide Number from UART Clock Source\n
8
4
read-write
USB_N
USB clock divide number from PLL Clock\n
4
4
read-write
CLKSEL0
CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLK_S
HCLK Clock Source Selection (Write-Protection Bits)
Before clock switching, the related clock sources (both pre-select and new-select) must be turn on
The 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.
These bits are protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
3
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#000
1
Clock source from external 32.768 kHz low speed crystal clock
#001
2
Clock source from PLL clock
#010
3
Clock source from internal 10 kHz low speed oscillator clock
#011
7
Clock source from internal 22.1184 MHz high speed oscillator clock
#111
STCLK_S
Cortex_M0 SysTick Clock Source Selection (Write-Protection Bits)\n
3
3
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#000
1
Clock source from external 32.768 kHz low speed crystal clock
#001
2
Clock source from external 4~24 MHz high speed crystal clock/2
#010
3
Clock source from HCLK/2
#011
7
Clock source from internal 22.1184 MHz high speed oscillator clock/2
#111
CLKSEL1
CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
ADC_S
ADC Clock Source Selection\n
2
2
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#00
1
Clock source from PLL clock
#01
3
Clock source from internal 22.1184 MHz high speed oscillator clock
#11
PWM01_S
PWM0 and PWM1 Clock Source Selection
PWM0 and PWM1 use the same Engine clock source both of them use the same prescaler.
28
2
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#00
1
Clock source from external 32.768 kHz low speed crystal clock
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz high speed oscillator clock
#11
PWM23_S
PWM2 and PWM3 Clock Source Selection
PWM2 and PWM3 use the same Engine clock source both of them use the same prescaler.
30
2
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#00
1
Clock source from external 32.768 kHz low speed crystal clock
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz high speed oscillator clock
#11
TMR0_S
TIMER0 Clock Source Selection\n
8
3
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#000
1
Clock source from external 32.768 kHz low speed crystal clock
#001
2
Clock source from HCLK
#010
7
Clock source from internal 22.1184 MHz high speed oscillator clock
#111
TMR1_S
TIMER1 Clock Source Selection\n
12
3
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#000
1
Clock source from external 32.768 kHz low speed crystal clock
#001
2
Clock source from HCLK
#010
7
Clock source from internal 22.1184 MHz high speed oscillator clock
#111
TMR2_S
TIMER2 Clock Source Selection\n
16
3
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#000
1
Clock source from external 32.768 kHz low speed crystal clock
#001
2
Clock source from HCLK
#010
7
Clock source from internal 22.1184 MHz high speed oscillator clock
#111
TMR3_S
TIMER3 Clock Source Selection\n
20
3
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#000
1
Clock source from external 32.768 kHz low speed crystal clock
#001
2
Clock source from HCLK
#010
7
Clock source from internal 22.1184 MHz high speed oscillator clock
#111
UART_S
UART Clock Source Selection\n
24
2
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#00
1
Clock source from PLL clock
#01
3
Clock source from internal 22.1184 MHz high speed oscillator clock
#11
WDT_S
Watchdog Timer Clock Source Selection (Write-Protection Bits)
These bits are protected bit, program this need to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
2
read-write
2
Clock source from HCLK/2048 clock
#10
3
Clock source from internal 10 kHz low speed oscillator clock
#11
CLKSEL2
CLKSEL2
Clock Source Select Control Register 2
0x1C
-1
read-write
n
0x0
0x0
FRQDIV_S
Clock Divider Clock Source Selection\n
2
2
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#00
1
Clock source from external 32.768 kHz low speed crystal clock
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz high speed oscillator clock
#11
I2S_S
I2S Clock Source Selection\n
0
2
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#00
1
Clock source from PLL clock
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz high speed oscillator clock
#11
PWM45_S
PWM4 and PWM5 Clock Source Selection (NuMicro( NUC100/NUC120 Medium Density Only)
PWM4 and PWM5 use the same Engine clock source both of them use the same prescaler
4
2
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#00
1
Clock source from external 32.768 kHz low speed crystal clock
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz high speed oscillator clock
#11
PWM67_S
PWM6 and PWM7 Clock Source Selection (NuMicro( NUC100/NUC120 Medium Density Only)
PWM6 and PWM7 use the same Engine clock source both of them use the same prescaler
6
2
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#00
1
Clock source from external 32.768 kHz low speed crystal clock
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz high speed oscillator clock
#11
CLKSTATUS
CLKSTATUS
Clock Status Monitor Register\n(NuMicro( NUC100/NUC120 Low Density Only)
0xC
read-write
n
0x0
0x0
CLK_SW_FAIL
Clock Switching Fail Flag\nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nWrite 1 to clear the bit to zero.\nNote: This bit only support in NuMicro( NUC100/NUC120 Low Density.
7
1
read-write
0
Clock switching success
#0
1
Clock switching failure
#1
OSC10K_STB
Internal 10 kHz Low Speed oscillator clock source stable flag\nThis is read only bit.
3
1
read-write
0
Internal 10 kHz low speed oscillator clock is not stable or disabled
#0
1
Internal 10 kHz low speed oscillator clock is stable
#1
OSC22M_STB
Internal 22.1184 MHz High Speed oscillator clock source stable flag\nThis is read only bit.
4
1
read-write
0
Internal 22.1184 MHz high speed oscillator clock is not stable or disabled
#0
1
Internal 22.1184 MHz high speed oscillator clock is stable
#1
PLL_STB
Internal PLL clock source stable flag\nThis is read only bit.
2
1
read-write
0
Internal PLL clock is not stable or disabled
#0
1
Internal PLL clock is stable
#1
XTL12M_STB
External 4~24 MHz High Speed crystal clock source stable flag\nThis is read only bit.
0
1
read-write
0
External 4~24 MHz high speed crystal clock is not stable or disabled
#0
1
External 4~24 MHz high speed crystal clock is stable
#1
XTL32K_STB
External 32.768 kHz Low Speed Crystal Clock Source Stable Flag\nThis is read only bit.
1
1
read-write
0
External 32.768 kHz low speed crystal clock is not stable or disabled
#0
1
External 32.768 kHz low speed crystal clock is stable
#1
FRQDIV
FRQDIV
Frequency Divider Control Register
0x24
read-write
n
0x0
0x0
DIVIDER_EN
Frequency Divider Enable Bit\n
4
1
read-write
0
Frequency Divider Disabled
#0
1
Frequency Divider Enabled
#1
FSEL
Divider Output Frequency Selection Bits\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0].
0
4
read-write
PLLCON
PLLCON
PLL Control Register
0x20
-1
read-write
n
0x0
0x0
BP
PLL Bypass Control\n
17
1
read-write
0
PLL is in normal mode (default)
#0
1
PLL clock output is same as clock input (XTALin)
#1
FB_DV
PLL Feedback Divider Control Pins\nRefer to the formulas below the table.
0
9
read-write
IN_DV
PLL Input Divider Control Pins\nRefer to the formulas below the table.
9
5
read-write
OE
PLL OE (FOUT Enable) Pin Control\n
18
1
read-write
0
PLL FOUT Enabled
#0
1
PLL FOUT Fixed Low
#1
OUT_DV
PLL Output Divider Control Pins\nRefer to the formulas below the table.
14
2
read-write
PD
Power-down Mode\nIf set the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too.\n
16
1
read-write
0
PLL is in Normal mode
#0
1
PLL is in Power-down mode (default)
#1
PLL_SRC
PLL Source Clock Selection\n
19
1
read-write
0
PLL source clock from external 4~24 MHz high speed crystal
#0
1
PLL source clock from internal 22.1184 MHz high speed oscillator
#1
PWRCON
PWRCON
System Power-down Control Register
0x0
-1
read-write
n
0x0
0x0
OSC10K_EN
Internal 10 kHz Low Speed Oscillator Enable (Write-protection Bit)\n
3
1
read-write
0
Internal 10 kHz low speed oscillator Disabled
#0
1
Internal 10 kHz low speed oscillator Enabled
#1
OSC22M_EN
Internal 22.1184 MHz High Speed Oscillator Enable (Write-protection Bit)\n
2
1
read-write
0
Internal 22.1184 MHz high speed oscillator Disabled
#0
1
Internal 22.1184 MHz high speed oscillator Enabled
#1
PD_WAIT_CPU
This Bit Control the Power-down Entry Condition (Write-protection Bit)\n
8
1
read-write
0
Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1
#0
1
Chip enters Power-down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU runs WFI instruction
#1
PD_WU_DLY
Enable the Wake-up Delay Counter (Write-protection Bit)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator.\n
4
1
read-write
0
Clock cycles delay Disabled
#0
1
Clock cycles delay Enabled
#1
PD_WU_INT_EN
Power-down Mode Wake-up Interrupt Enable (Write-protection Bit)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
5
1
read-write
0
Disabled
#0
1
Enabled
#1
PD_WU_STS
Power-down Mode Wake-up Interrupt Status
Set by power-down wake-up event , it indicates that resume from Power-down mode
The flag is set if the GPIO, USB, UART, WDT, ACMP, BOD or RTC wake-up occurred
Write 1 to clear the bit to 0.
Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
6
1
read-write
PWR_DOWN_EN
System Power-down Enable Bit (Write-protection Bit)\nWhen this bit is set to 1, the Power-down mode is enabled and chip power-down behavior will depends on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0, then the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set.\n(b) if the PD_WAIT_CPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode\nWhen chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next power-down.\nIn Power-down mode, external 4~24 MHz high speed crystal and the internal 22.1184 MHz high speed oscillator will be disabled in this mode, but the external 32.768 kHz low speed crystal and internal 10 kHz low speed oscillator are not controlled by Power-down mode.\nIn Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from external 32.768 kHz low speed crystal or the internal 10 kHz low speed oscillator.\n
7
1
read-write
0
Chip operating normally or chip in idle mode because of WFI command
#0
1
Chip enters Power-down mode instant or wait CPU sleep command WFI
#1
XTL12M_EN
External 4~24 MHz High Speed Crystal Enable (Write-protection Bit)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically\n
0
1
read-write
0
External 4~24 MHz high speed crystal Disabled
#0
1
External 4~24 MHz high speed crystal Enabled
#1
XTL32K_EN
External 32.768 kHz Low Speed Crystal Enable (Write-protection Bit)\n
1
1
read-write
0
External 32.768 kHz low speed crystal Disabled
#0
1
External 32.768 kHz low speed crystal Enabled (Normal operation)
#1
CMP
CMP Register Map
CMP
0x0
0x0
0xC
registers
n
CMP0CR
CMP0CR
Comparator0 Control Register
0x0
read-write
n
0x0
0x0
CMP0CN
Comparator0 Negative Input Selection\n
4
1
read-write
0
The source of the negative comparator input is from CPN0 pin
#0
1
Internal band-gap reference voltage is selected as the source of negative comparator input
#1
CMP0EN
Comparator0 Enable\nComparator output needs wait 2 us stable time after CMP0EN is set.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CMP0IE
Comparator0 Interrupt Enable\n
1
1
read-write
0
Interrupt function Disabled
#0
1
Interrupt function Enabled
#1
CMP0_HYSEN
Comparator0 Hysteresis Enable\n
2
1
read-write
0
Hysteresis function Disabled (Default)
#0
1
Hysteresis function Enabled. The typical range is 20mV
#1
CMP1CR
CMP1CR
Comparator1 Control Register
0x4
read-write
n
0x0
0x0
CMP1CN
Comparator1 Negative Input Selection\n
4
1
read-write
0
The source of the negative comparator input is from CPN1 pin
#0
1
Internal band-gap reference voltage is selected as the source of negative comparator input
#1
CMP1EN
Comparator1 Enable\nComparator output needs to wait 2 us stable time after CMP1EN is set.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CMP1IE
Comparator1 Interrupt Enable\n
1
1
read-write
0
Interrupt function Disabled
#0
1
Interrupt function Enabled
#1
CMP1_HYSEN
Comparator1 Hysteresis Enable\n
2
1
read-write
0
Hysteresis function Disabled (default)
#0
1
Hysteresis function Enabled. The typical range is 20mV
#1
CMPSR
CMPSR
Comparator Status Register
0x8
read-write
n
0x0
0x0
CMPF0
Comparator0 Flag\nThis bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if CMP0IE set.\nWrite 1 to clear this bit to 0.
0
1
read-write
CMPF1
Comparator1 Flag\nThis bit is set by hardware whenever the comparator1 output changes state. This will cause an interrupt if CMP1IE set.\nWrite 1 to clear this bit to 0.
1
1
read-write
CO0
Comparator0 Output\n
2
1
read-write
CO1
Comparator1 Output\n
3
1
read-write
EBI
EBI Register Map
EBI
0x0
0x0
0x8
registers
n
EBICON
EBICON
External Bus Interface General Control Register
0x0
read-write
n
0x0
0x0
ExtBW16
EBI Data Width 16-bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n
1
1
read-write
0
EBI data width is 8-bit
#0
1
EBI data width is 16-bit
#1
ExtEN
EBI Enable\nThis bit is the functional enable bit for EBI.\n
0
1
read-write
0
EBI function Disabled
#0
1
EBI function Enabled
#1
ExttALE
Expand Time of ALE\nThe ALE width (tALE) to latch the address can be controlled by ExttALE.\n
16
3
read-write
MCLKDIV
External Output Clock Divider\n
8
3
read-write
EXTIME
EXTIME
External Bus Interface Timing Control Register
0x4
read-write
n
0x0
0x0
ExtIR2R
Idle State Cycle Between Read-Read\nWhen read action is finished and the next action is going to read, idle state is inserted and nCS return to high if ExtIR2R is not zero.\n
24
4
read-write
ExtIW2X
Idle State Cycle After Write\nWhen write action is finished, idle state is inserted and nCS return to high if ExtIW2X is not zero.\n
12
4
read-write
ExttACC
EBI Data Access Time\nExttACC defines data access time (tACC).\n
3
5
read-write
ExttAHD
EBI Data Access Hold Time\nExttAHD defines data access hold time (tAHD).\n
8
3
read-write
FMC
FMC Register Map
FMC
0x0
0x0
0x1C
registers
n
DFBADR
DFBADR
Data Flash Start Address (AP ROM Size Is Less Than 128KB)
0x14
-1
read-only
n
0x0
0x0
DFBADR
Data Flash Base Address\nThis register indicates data flash start address. It is read only.\nFor 128KB flash memory device, the data flash size is defined by user configuration, register content is loaded from Config1 when chip power on but for 64/32KB device, it is fixed at 0x0001_F000.
0
32
read-only
FATCON
FATCON
Flash Access Window Control Register
0x18
read-write
n
0x0
0x0
FATS
Flash Access Time Window Selection (Write-protection Bits)\n
1
3
read-write
FPSEN
Flash Power Save Enable (Write-protection Bit)\nIf CPU clock is slower than 24 MHz, software can enable flash power saving function.\n
0
1
read-write
0
Flash power saving Disabled
#0
1
Flash power saving Enabled
#1
LFOM
Low Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 25 MHz, chip can work more efficiently by setting this bit to 1\n(This bit is only for NuMicro( NUC100/NUC120 Low Density.)
4
1
read-write
0
Low frequency optimization mode Disabled
#0
1
Low frequency optimization mode Enabled
#1
ISPADR
ISPADR
ISP Address Register
0x4
read-write
n
0x0
0x0
ISPADR
ISP Address
The NuMicro( NUC100 Series has a maximum of 32Kx32 embedded flash it supports word program only. ISPADR[1:0] must be kept 00b for ISP operation.
0
32
read-write
ISPCMD
ISPCMD
ISP Command Register
0xC
read-write
n
0x0
0x0
FCEN
ISP Command
4
1
read-write
FCTRL
ISP Command
0
4
read-write
FOEN
ISP Command\n
5
1
read-write
ISPCON
ISPCON
ISP Control Register
0x0
read-write
n
0x0
0x0
BS
Boot Selection (Write-protection Bit)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened\n
1
1
read-write
0
Boot from APROM
#0
1
Boot from LDROM
#1
CFGUEN
Enable Config-bits Update by ISP (Write-protection Bit)\n
4
1
read-write
0
ISP Disabled for config-bits update
#0
1
ISP Enabled for config-bits update
#1
ISPEN
ISP Enable (Write-protection Bit)\nISP function enable bit. Set this bit to enable ISP function.\n
0
1
read-write
0
ISP function Disabled
#0
1
ISP function Enabled
#1
ISPFF
ISP Fail Flag (Write-protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself\n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear.
6
1
read-write
LDUEN
LDROM Update Enable (Write-protection Bit)\n
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated when the chip runs in APROM
#1
ISPDAT
ISPDAT
ISP Data Register
0x8
read-write
n
0x0
0x0
ISPDAT
ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
0
32
read-write
ISPTRG
ISPTRG
ISP Trigger Register
0x10
read-write
n
0x0
0x0
ISPGO
ISP start trigger (Write-protection Bit)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
1
read-write
0
ISP operation finished
#0
1
ISP progressed
#1
GCR
GCR Register Map
GCR
0x0
0x0
0x14
registers
n
0x100
0x4
registers
n
0x18
0x8
registers
n
0x24
0x4
registers
n
0x30
0x14
registers
n
0x50
0x4
registers
n
ALT_MFP
ALT_MFP
Alternative Multiple Function Pin Control Register
0x50
read-write
n
0x0
0x0
EBI_EN
EBI_EN is used to switch GPIO function to EBI function (AD[15:0], ALE, RE, WE, CS, MCLK), which needs additional registers EBI_EN[7:0] and EBI_MCLK_EN for some GPIO to switch to EBI function(AD[15:8], MCLK).\n
11
1
read-write
EBI_HB_EN0
Bits EBI_HB_EN[0], EBI_EN and GPA_MFP[5] determine the PA.5 function.\n
16
1
read-write
EBI_HB_EN1
Bits EBI_HB_EN[1], EBI_EN and GPA_MFP[4] determine the PA.4 function.\n
17
1
read-write
EBI_HB_EN2
Bits EBI_HB_EN[2], EBI_EN and GPA_MFP[3] determine the PA.3 function.\n
18
1
read-write
EBI_HB_EN3
Bits EBI_HB_EN[3], EBI_EN and GPA_MFP[2] determine the PA.2 function.\n
19
1
read-write
EBI_HB_EN4
Bits EBI_HB_EN[4], EBI_EN and GPA_MFP[1] determine the PA.1 function.\n
20
1
read-write
EBI_HB_EN5
Bits EBI_HB_EN[5], EBI_EN and GPA_MFP[12] determine the PA.12 function.\n
21
1
read-write
EBI_HB_EN6
Bits EBI_HB_EN[6], EBI_EN and GPA_MFP[13] determine the PA.13 function.\n
22
1
read-write
EBI_HB_EN7
EBI_HB_EN is used to switch GPIO function to EBI address/data bus high byte (AD[15:8]), EBI_HB_EN, EBI_EN and the corresponding GPx_MFP[y] determine the Px.y function.
23
1
read-write
EBI_MCLK_EN
Bits EBI_MCLK_EN, EBI_EN and GPC_MFP[8] determine the PC.8 function.\n
12
1
read-write
EBI_nWRH_EN
Bits EBI_nWRH_EN, EBI_EN and GPB_MFP[3] determine the PB.3 function.\n
14
1
read-write
EBI_nWRL_EN
Bits EBI_nWRL_EN, EBI_EN and GPB_MFP[2] determine the PB.2 function.\n
13
1
read-write
PA15_I2SMCLK
Bits PA15_I2SMCLK and GPA_MFP[15] determine the PA.15 function.\n
9
1
read-write
PA7_S21
Bits PA7_S21, GPA_MFP[7] and EBI_EN (ALT_MFP[11]).determine the PA.7 function.\n
2
1
read-write
PB10_S01
Bits PB10_S01 and GPB_MFP[10] determine the PB.10 function.\n
0
1
read-write
PB11_PWM4
Bits PB11_PWM4 and GPB_MFP[11] determine the PB.11 function.\n
4
1
read-write
PB12_CLKO
Bits PB12_CLKO, GPB_MFP[12] and EBI_EN (ALT_MFP[11]) determine the PB.12 function.\n
10
1
read-write
PB14_S31
Bits PB14_S31 and GPB_MFP[14] determine the PB.14 function.\n
3
1
read-write
PB9_S11
Bits PB9_S11 and GPB_MFP[9] determine the PB.9 function.\n
1
1
read-write
PC0_I2SLRCLK
Bits PC0_I2SLRCLK and GPC_MFP[0] determine the PC.0 function.\n
5
1
read-write
PC1_I2SBCLK
Bits PC1_I2SBCLK and GPC_MFP[1] determine the PC.1 function.\n
6
1
read-write
PC2_I2SDI
Bits PC2_I2SDI and GPC_MFP[2] determine the PC.2 function.\n
7
1
read-write
PC3_I2SDO
Bits PC3_I2SDO and GPC_MFP[3] determine the PC.3 function.\n
8
1
read-write
BODCR
BODCR
Brown-out Detector Control Register
0x18
-1
read-write
n
0x0
0x0
BOD_EN
Brown-out Detector Enable (write-protection bit)
The default value is set by flash controller user configuration register config0 bit[23]
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
1
read-write
0
Brown-out Detector function Disabled
#0
1
Brown-out Detector function Enabled
#1
BOD_INTF
Brown-out Detector Interrupt Flag\nWrite 1 to clear this bit to 0.
4
1
read-write
0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting
#0
1
When Brown-out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled
#1
BOD_LPM
Brown-out Detector Low power Mode (Write-Protection Bit)
The BOD consumes about 100 uA in Normal mode, and the low power mode can reduce the current to about 1/10 but slow the BOD response.
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
5
1
read-write
0
BOD operated in Normal mode (default)
#0
1
BOD low power mode Enabled
#1
BOD_OUT
Brown-out Detector output status\n
6
1
read-write
0
Brown-out Detector output status is 0. It means the detected voltage is higher than BOD_VL setting or BOD_EN is 0
#0
1
Brown-out Detector output status is 1. It means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled , this bit always responds 0
#1
BOD_RSTEN
Brown-out Reset Enable (Write-Protection Bit)
While the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low).
The default value is set by flash controller user configuration register config0 bit[20].
This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
3
1
read-write
0
Brown-out INTERRUPT function Enabled
#0
1
Brown-out RESET function Enabled
#1
BOD_VL
Brown-out Detector Threshold Voltage Selection (Write-Protection Bit)\n
1
2
read-write
LVR_EN
Low Voltage Reset Enable (Write-Protection Bit)
The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default.
This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
7
1
read-write
0
Low Voltage Reset function Disabled
#0
1
Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable. (Default)
#1
CPR
CPR
Chip Performance Register
0x10
read-write
n
0x0
0x0
HPE
High Performance Enable (Write-Protection Bit)\nThis bit is used to control chip operation performance.\nWhen this bit set, internal RAM and GPIO access is working with zero wait state, and Flash controller will predict next address more efficiently. The high performance is enabled without limiting by chip operation frequency.\n
0
1
read-write
0
Chip operation at normal mode
#0
1
Chip operation at high performance mode
#1
GPA_MFP
GPA_MFP
GPIOA Multiple Function and Input Type Control Register
0x30
read-write
n
0x0
0x0
GPA_MFP0
PA.0 Pin Function Selection\n
0
1
read-write
0
GPIOA[0] selected to the pin PA.0
#0
1
ADC0 (Analog-to-Digital converter channel 0) function selected to the pin PA.0
#1
GPA_MFP1
PA.1 Pin Function Selection\n
1
1
read-write
GPA_MFP10
PA.10 Pin Function Selection\n
10
1
read-write
GPA_MFP11
PA.11 Pin Function Selection\n
11
1
read-write
GPA_MFP12
PA.12 Pin Function Selection\n
12
1
read-write
GPA_MFP13
PA.13 Pin Function Selection\n
13
1
read-write
GPA_MFP14
PA.14 Pin Function Selection\n
14
1
read-write
GPA_MFP15
PA.15 Pin Function Selection\n
15
1
read-write
GPA_MFP2
PA.2 Pin Function Selection\n
2
1
read-write
GPA_MFP3
PA.3 Pin Function Selection\n
3
1
read-write
GPA_MFP4
PA.4 Pin Function Selection\n
4
1
read-write
GPA_MFP5
PA.5 Pin Function Selection\n
5
1
read-write
GPA_MFP6
PA.6 Pin Function Selection\n
6
1
read-write
GPA_MFP7
PA.7 Pin Function Selection\n
7
1
read-write
GPA_MFP8
PA.8 Pin Function Selection\n
8
1
read-write
0
GPIOA[8] selected to the pin PA.8
#0
1
I2C0 SDA function selected to the pin PA.8
#1
GPA_MFP9
PA.9 Pin Function Selection\n
9
1
read-write
0
GPIOA[9] selected to the pin PA.9
#0
1
I2C0 SCL function selected to the pin PA.9
#1
GPA_TYPEn
None
16
16
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOA[15:0] I/O input Schmitt Trigger function Enabled
1
GPB_MFP
GPB_MFP
GPIOB Multiple Function and Input Type Control Register
0x34
read-write
n
0x0
0x0
GPB_MFP0
PB.0 Pin Function Selection\n
0
1
read-write
0
GPIOB[0] selected to the pin PB.0
#0
1
UART0 RXD function selected to the pin PB.0
#1
GPB_MFP1
PB.1 Pin Function Selection\n
1
1
read-write
0
GPIOB[1] selected to the pin PB.1
#0
1
UART0 TXD function selected to the pin PB.1
#1
GPB_MFP10
PB.10 Pin Function Selection\n
10
1
read-write
GPB_MFP11
PB.11 Pin Function Selection\n
11
1
read-write
GPB_MFP12
PB.12 Pin Function Selection\n
12
1
read-write
GPB_MFP13
PB.13 Pin Function Selection\n
13
1
read-write
GPB_MFP14
PB.14 Pin Function Selection\n
14
1
read-write
GPB_MFP15
PB.15 Pin Function Selection\n
15
1
read-write
0
GPIOB[15] selected to the pin PB.15
#0
1
External Interrupt INT1 function selected to the pin PB.15
#1
GPB_MFP2
PB.2 Pin Function Selection\n
2
1
read-write
GPB_MFP3
PB.3 Pin Function Selection\n
3
1
read-write
GPB_MFP4
PB.4 Pin Function Selection\n
4
1
read-write
0
GPIOB[4] selected to the pin PB.4
#0
1
UART1 RXD function selected to the pin PB.4
#1
GPB_MFP5
PB. 5 Pin Function Selection\n
5
1
read-write
0
GPIOB[5] is selected to the pin PB.5
#0
1
UART1 TXD function is selected to the pin PB.5
#1
GPB_MFP6
PB.6 Pin Function Selection\n
6
1
read-write
GPB_MFP7
PB.7 Pin Function Selection\n
7
1
read-write
GPB_MFP8
PB.8 Pin Function Selection\n
8
1
read-write
0
GPIOB[8] selected to the pin PB.8
#0
1
TM0 (Timer/Counter external trigger clock input) function selected to the pin PB.8
#1
GPB_MFP9
PB.9 Pin Function Selection\n
9
1
read-write
GPB_TYPEn
None
16
16
read-write
0
GPIOB[15:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOB[15:0] I/O input Schmitt Trigger function Enabled
1
GPC_MFP
GPC_MFP
GPIOC Multiple Function and Input Type Control Register
0x38
read-write
n
0x0
0x0
GPC_MFP0
PC.0 Pin Function Selection\n
0
1
read-write
GPC_MFP1
PC.1 Pin Function Selection\n
1
1
read-write
GPC_MFP10
PC.10 Pin Function Selection\n
10
1
read-write
0
GPIOC[10] is selected to the pin PC.10
#0
1
SPI1 MISO0 (master input, slave output pin-0) function selected to the pin PC.10
#1
GPC_MFP11
PC.11 Pin Function Selection\n
11
1
read-write
0
GPIOC[11] selected to the pin PC.11
#0
1
SPI1 MOSI0 (master output, slave input pin-0) function selected to the pin PC.11
#1
GPC_MFP12
PC.12 Pin Function Selection\n
12
1
read-write
0
GPIOC[12] selected to the pin PC.12
#0
1
SPI1 MISO1 (master input, slave output pin-1) function selected to the pin PC.12
#1
GPC_MFP13
PC.13 Pin Function Selection\n
13
1
read-write
0
GPIOC[13] selected to the pin PC.13
#0
1
SPI1 MOSI1 (master output, slave input pin-1) function selected to the pin PC.13
#1
GPC_MFP14
PC.14 Pin Function Selection\n
14
1
read-write
GPC_MFP15
PC.15 Pin Function Selection\n
15
1
read-write
GPC_MFP2
PC.2 Pin Function Selection\n
2
1
read-write
GPC_MFP3
PC.3 Pin Function Selection\n
3
1
read-write
GPC_MFP4
PC.4 Pin Function Selection\n
4
1
read-write
0
GPIOC[4] is selected to the pin PC.4
#0
1
SPI0 MISO1 (master input, slave output pin-1) function is selected to the pin PC.4
#1
GPC_MFP5
PC.5 Pin Function Selection\n
5
1
read-write
0
GPIOC[5] is selected to the pin PC.5
#0
1
SPI0 MOSI1 (master output, slave input pin-1) function is selected to the pin PC.5
#1
GPC_MFP6
PC.6 Pin Function Selection\n
6
1
read-write
GPC_MFP7
PC.7 Pin Function Selection\n
7
1
read-write
GPC_MFP8
PC.8 Pin Function Selection\n
8
1
read-write
GPC_MFP9
PC.9 Pin Function Selection\n
9
1
read-write
0
GPIOC[9] selected to the pin PC.9
#0
1
SPI1 SPICLK function selected to the pin PC.9
#1
GPC_TYPEn
None
16
16
read-write
0
GPIOC[15:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOC[15:0] I/O input Schmitt Trigger function Enabled
1
GPD_MFP
GPD_MFP
GPIOD Multiple Function and Input Type Control Register
0x3C
read-write
n
0x0
0x0
GPD_MFP0
PD.0 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
0
1
read-write
0
GPIOD[0] selected to the pin PD.0
#0
1
SPI2 SS20 function selected to the pin PD.0
#1
GPD_MFP1
PD.1 Pin Function Selection\nFor NuMicro( NUC100/NUC120 Medium Density:\nFor NuMicro( NUC100/NUC120 Low Density:\nReserved
1
1
read-write
0
GPIOD[1] selected to the pin PD.1
#0
1
SPI2 SPICLK function selected to the pin PD.1
#1
GPD_MFP10
PD.10 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
10
1
read-write
0
GPIOD[10] selected to the pin PD.10
#0
1
SPI3 MISO0 (master input, slave output pin-0) function selected to the pin PD.10
#1
GPD_MFP11
PD.11 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
11
1
read-write
0
GPIOD[11] selected to the pin PD.11
#0
1
SPI3 MOSI0 (master output, slave input pin-0) function selected to the pin PD.11
#1
GPD_MFP12
PD.12 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
12
1
read-write
0
GPIOD[12] selected to the pin PD.12
#0
1
SPI3 MISO1 (master input, slave output pin-1) function selected to the pin PD.12
#1
GPD_MFP13
PD.13 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
13
1
read-write
0
GPIOD[13] selected to the pin PD.13
#0
1
SPI3 MOSI1 (master output, slave input pin-1) function selected to the pin PD.13
#1
GPD_MFP14
PD.14 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
14
1
read-write
0
GPIOD[14] selected to the pin PD.14
#0
1
UART2 RXD function is selected to the pin PD.14
#1
GPD_MFP15
PD.15 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
15
1
read-write
0
GPIOD[15] selected to the pin PD.15
#0
1
UART2 TXD function selected to the pin PD.15
#1
GPD_MFP2
PD.2 Pin Function Selection\nFor NuMicro( NUC100/NUC120 Medium Density:\nFor NuMicro( NUC100/NUC120 Low Density:\nReserved
2
1
read-write
0
GPIOD[2] selected to the pin PD.2
#0
1
SPI2 MISO0 (master input, slave output pin-0) function selected to the pin PD.2
#1
GPD_MFP3
PD.3 Pin Function Selection\nFor NuMicro( NUC100/NUC120 Medium Density:\nFor NuMicro( NUC100/NUC120 Low Density:\nReserved
3
1
read-write
0
GPIOD[3] selected to the pin PD.3
#0
1
SPI2 MOSI0 (master output, slave input pin-0) function selected to the pin PD.3
#1
GPD_MFP4
PD.4 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
4
1
read-write
0
GPIOD[4]is selected to the pin PD.4
#0
1
SPI2 MISO1 (master input, slave output pin-1) function selected to the pin PD.4
#1
GPD_MFP5
PD.5 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
5
1
read-write
0
GPIOD[5] is selected to the pin PD.5
#0
1
SPI2 MOSI1 (master output, slave input pin-1) function selected to the pin PD.5
#1
GPD_MFP6
Reserved
6
1
read-write
GPD_MFP7
Reserved
7
1
read-write
GPD_MFP8
PD.8 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
8
1
read-write
0
GPIOD[8] selected to the pin PD8
#0
1
SPI3 SS30 function selected to the pin PD8
#1
GPD_MFP9
PD.9 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
9
1
read-write
0
GPIOD[9] selected to the pin PD.9
#0
1
SPI3 SPICLK function selected to the pin PD.9
#1
GPD_TYPEn
None
16
16
read-write
0
GPIOD[15:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOD[15:0] I/O input Schmitt Trigger function Enabled
1
GPE_MFP
GPE_MFP
GPIOE Multiple Function and Input Type Control Register
0x40
read-write
n
0x0
0x0
GPE_MFP0
PE.0 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
0
1
read-write
0
GPIOE[0] selected to the pin PE.0
#0
1
PWM6 function selected to the pin PE.0
#1
GPE_MFP1
PE.1 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
1
1
read-write
0
GPIOE[1] selected to the pin PE.1
#0
1
PWM7 function selected to the pin PE.1
#1
GPE_MFP5
PE.5 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
5
1
read-write
0
GPIOE[5] selected to the pin PE.5
#0
1
PWM5 function selected to the pin PE.5
#1
GPE_TYPEn
Note: In this field, NuMicro( NUC100/NUC120 Low Density only has GPE_TYPE5 bit.
16
16
read-write
0
GPIOE[15:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOE[15:0] I/O input Schmitt Trigger function Enabled
1
IPRSTC1
IPRSTC1
IP Reset Control Register 1
0x8
read-write
n
0x0
0x0
CHIP_RST
CHIP One-shot Reset (Write-Protection Bit)
Setting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
The CHIP_RST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
About the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2
This bit is the protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
0
1
read-write
0
CHIP normal operation
#0
1
CHIP one-shot reset
#1
CPU_RST
CPU Kernel one-shot reset (Write-protection Bit)
Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return 0 after two clock cycles
This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
1
1
read-write
0
CPU normal operation
#0
1
CPU one-shot reset
#1
EBI_RST
EBI Controller Reset (NuMicro( NUC100/NUC120 Low Density 64 pin Package Only) (Write-protection Bit in NuMicro( NUC100/NUC120 Low Density 64-pin Package)
Set this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state.
This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
3
1
read-write
0
EBI controller normal operation
#0
1
EBI controller reset
#1
PDMA_RST
PDMA Controller Reset (Write-protection Bit in NuMicro( NUC100/NUC120 Low Density)
Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.
This bit is the protected bit, which means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
2
1
read-write
0
PDMA controller normal operation
#0
1
PDMA controller reset
#1
IPRSTC2
IPRSTC2
IP Reset Control Register 2
0xC
read-write
n
0x0
0x0
ACMP_RST
Analog Comparator Controller Reset\n
22
1
read-write
0
Analog Comparator controller normal operation
#0
1
Analog Comparator controller reset
#1
ADC_RST
ADC Controller Reset\n
28
1
read-write
0
ADC controller normal operation
#0
1
ADC controller reset
#1
GPIO_RST
GPIO controller Reset\n
1
1
read-write
0
GPIO controller normal operation
#0
1
GPIO controller reset
#1
I2C0_RST
I2C0 controller Reset\n
8
1
read-write
0
I2C0 controller normal operation
#0
1
I2C0 controller reset
#1
I2C1_RST
I2C1 controller Reset\n
9
1
read-write
0
I2C1 controller normal operation
#0
1
I2C1 controller reset
#1
I2S_RST
I2S Controller Reset\n
29
1
read-write
0
I2S controller normal operation
#0
1
I2S controller reset
#1
PS2_RST
PS/2 Controller Reset\n
23
1
read-write
0
PS/2 controller normal operation
#0
1
PS/2 controller reset
#1
PWM03_RST
PWM03 controller Reset\n
20
1
read-write
0
PWM03 controller normal operation
#0
1
PWM03 controller reset
#1
PWM47_RST
PWM47 controller Reset (NuMicro( NUC100/NUC120 Medium Density Only)\n
21
1
read-write
0
PWM47 controller normal operation
#0
1
PWM47 controller reset
#1
SPI0_RST
SPI0 controller Reset\n
12
1
read-write
0
SPI0 controller normal operation
#0
1
SPI0 controller reset
#1
SPI1_RST
SPI1 controller Reset\n
13
1
read-write
0
SPI1 controller normal operation
#0
1
SPI1 controller reset
#1
SPI2_RST
SPI2 controller Reset (NuMicro( NUC100/NUC120 Medium Density Only)\n
14
1
read-write
0
SPI2 controller normal operation
#0
1
SPI2 controller reset
#1
SPI3_RST
SPI3 controller Reset (NuMicro( NUC100/NUC120 Medium Density Only)\n
15
1
read-write
0
SPI3 controller normal operation
#0
1
SPI3 controller reset
#1
TMR0_RST
Timer0 controller Reset\n
2
1
read-write
0
Timer0 controller normal operation
#0
1
Timer0 controller reset
#1
TMR1_RST
Timer1 controller Reset\n
3
1
read-write
0
Timer1 controller normal operation
#0
1
Timer1 controller reset
#1
TMR2_RST
Timer2 controller Reset\n
4
1
read-write
0
Timer2 controller normal operation
#0
1
Timer2 controller reset
#1
TMR3_RST
Timer3 controller Reset\n
5
1
read-write
0
Timer3 controller normal operation
#0
1
Timer3 controller reset
#1
UART0_RST
UART0 controller Reset\n
16
1
read-write
0
UART0 controller normal operation
#0
1
UART0 controller reset
#1
UART1_RST
UART1 controller Reset\n
17
1
read-write
0
UART1 controller normal operation
#0
1
UART1 controller reset
#1
UART2_RST
UART2 controller Reset (NuMicro( NUC100/NUC120 Medium Density Only)\n
18
1
read-write
0
UART2 controller normal operation
#0
1
UART2 controller reset
#1
USBD_RST
USB Device Controller Reset\n
27
1
read-write
0
USB device controller normal operation
#0
1
USB device controller reset
#1
PDID
PDID
Part Device Identification Number Register
0x0
-1
read-only
n
0x0
0x0
PDID
Part Device Identification Number\nThis register reflects device part number code. S/W can read this register to identify which device is used.
0
32
read-only
PORCR
PORCR
Power-On-reset Controller Register
0x24
read-write
n
0x0
0x0
POR_DIS_CODE
Power-On-Reset Enable Control (Write-protection Bits)
When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
/RESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
16
read-write
REGWRPROT
REGWRPROT
Register Write Protect Register
0x100
read-write
n
0x0
0x0
REGWRPROT
Register Write-Protection Code (Write Only)
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write.
Register Write-Protection Disable index (Read only)
The Protected registers are:
IPRSTC1: address 0x5000_0008
CPR: address 0x5000_0010 (Low Density only)
BODCR: address 0x5000_0018
PORCR: address 0x5000_0024
PWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear)
APBCLK bit[0]: address 0x5000_0208 (bit[0] is watchdog clock enable)
CLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select)
CLKSEL1 bit[1:0]: address 0x5000_0214 (for watchdog clock source select)
ISPCON: address 0x5000_C000 (Flash ISP Control register)
ISPTRG: address 0x5000_C010 (ISP Trigger Control register)
WTCR: address 0x4000_4000
FATCON: address 0x5000_C018
0
8
read-write
0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
0
1
Write-protection Disabled for writing protected registers
1
RSTSRC
RSTSRC
System Reset Source Register
0x4
read-write
n
0x0
0x0
RSTS_BOD
The RSTS_BOD flag is set by the reset signal from the Brown-out-Detector to indicate the previous reset source.
Write 1 to clear this bit to 0.
4
1
read-write
0
No reset from BOD
#0
1
BOD had issued the reset signal to reset the system
#1
RSTS_CPU
The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).\nWrite 1 to clear this bit to 0.
7
1
read-write
0
No reset from CPU
#0
1
Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1
#1
RSTS_LVR
The RSTS_LVR flag is set by the reset signal from the Low-Voltage-Reset controller to indicate the previous reset source.
Write 1 to clear this bit to 0.
3
1
read-write
0
No reset from LVR
#0
1
LVR controller had issued the reset signal to reset the system
#1
RSTS_POR
The RSTS_POR flag is set by the reset signal from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source.
Write 1 to clear this bit to 0.
0
1
read-write
0
No reset from POR or CHIP_RST
#0
1
Power-On Reset (POR) or CHIP_RST had issued the reset signal to reset the system
#1
RSTS_RESET
The RSTS_RESET flag is set by the reset signal from the /RESET pin to indicate the previous reset source.
Write 1 to clear this bit to 0.
1
1
read-write
0
No reset from /RESET pin
#0
1
Pin /RESET had issued the reset signal to reset the system
#1
RSTS_SYS
The RSTS_SYS flag is set by the reset signal from the Cortex_M0 kernel to indicate the previous reset source.
Write 1 to clear this bit to 0.
5
1
read-write
0
No reset from Cortex_M0
#0
1
Cortex_M0 had issued the reset signal to reset the system by writing 1 to bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex_M0 kernel
#1
RSTS_WDT
The RSTS_WDT flag is set by the reset signal from the watchdog timer to indicate the previous reset source.
Write 1 to clear this bit to 0.
2
1
read-write
0
No reset from watchdog timer
#0
1
Watchdog timer had issued the reset signal to reset the system
#1
TEMPCR
TEMPCR
Temperature Sensor Control Register
0x1C
read-write
n
0x0
0x0
VTEMP_EN
Temperature Sensor Enable\nThis bit is used to enable/disable temperature sensor function.\nAfter this bit is set to 1, the value of temperature can be obtained from ADC conversion result by ADC channel selecting channel 7 and alternative multiplexer channel selecting temperature sensor. Please refer to the ADC function chapter for detailed ADC conversion function description.
0
1
read-write
0
Temperature sensor function Disabled (default)
#0
1
Temperature sensor function Enabled
#1
GP
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
0x100
0x24
registers
n
0x180
0x4
registers
n
0x200
0x100
registers
n
0x314
0x4
registers
n
0x40
0x24
registers
n
0x80
0x24
registers
n
0xC0
0x24
registers
n
DBNCECON
DBNCECON
De-bounce Cycle Control
0x180
-1
read-write
n
0x0
0x0
DBCLKSEL
De-bounce Sampling Cycle Selection\n
0
4
read-write
DBCLKSRC
De-bounce counter clock source select\n
4
1
read-write
0
De-bounce counter clock source is the HCLK
#0
1
De-bounce counter clock source is the internal 10 kHz low speed oscillator
#1
ICLK_ON
Interrupt clock On mode\nIt is recommended to turn off this bit to save system power, if on special application concern.
5
1
read-write
0
Edge detection circuit is active only if I/O pin corresponding GPIOx_IEN bit is set to 1
#0
1
All I/O pins edge detection circuit is always active after reset
#1
GPIOA_DBEN
GPIOA_DBEN
GPIO Port A De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
0
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN1
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
1
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN10
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
10
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN11
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
11
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN12
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
12
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN13
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
13
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN14
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
14
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN15
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
15
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN2
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
2
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN3
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
3
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN4
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
4
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN5
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
5
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN6
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
6
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN7
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
7
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN8
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
8
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN9
Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended to set this bit to '0' if GPIO is chosen as power-down wakeup source. If setting this bit to '1', it will cause GPIO to produce interrupt twice. One is caused by wake up event, and the other is caused by delayed de-bounce results.
9
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
GPIOA_DMASK
GPIOA_DMASK
GPIO Port A Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
0
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK1
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
1
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK10
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
10
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK11
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
11
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK12
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
12
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK13
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
13
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK14
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
14
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK15
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
15
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK2
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
2
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK3
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
3
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK4
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
4
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK5
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
5
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK6
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
6
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK7
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
7
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK8
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
8
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK9
Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\nNote: This function only protects the corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
9
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
GPIOA_DOUT
GPIOA_DOUT
GPIO Port A Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT0
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
0
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
DOUT1
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
1
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
DOUT10
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
10
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
DOUT11
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
11
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
DOUT12
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
12
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
DOUT13
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
13
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
DOUT14
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
14
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
DOUT15
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
15
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
DOUT2
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
2
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
DOUT3
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
3
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
DOUT4
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
4
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
DOUT5
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
5
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
DOUT6
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
6
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
DOUT7
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
7
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
DOUT8
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
8
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
DOUT9
GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configured as output, open-drain and quasi-mode.\n
9
1
read-write
0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configured as output, open-drain and quasi-mode
#0
1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configured as output, open-drain and quasi-mode
#1
GPIOA_IEN
GPIOA_IEN
GPIO Port A Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
0
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN1
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
1
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN10
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
10
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN11
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
11
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN12
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
12
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN13
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
13
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN14
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
14
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN15
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
15
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN2
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
2
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN3
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
3
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN4
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
4
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN5
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
5
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN6
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
6
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN7
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
7
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN8
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
8
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN9
Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
9
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IR_EN0
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
16
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN1
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
17
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN10
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
26
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN11
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
27
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN12
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
28
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN13
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
29
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN14
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
30
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN15
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
31
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN2
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
18
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN3
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
19
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN4
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
20
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN5
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
21
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN6
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
22
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN7
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
23
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN8
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
24
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN9
Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
25
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
GPIOA_IMD
GPIOA_IMD
GPIO Port A Interrupt Mode Control
0x18
read-write
n
0x0
0x0
IMD0
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
0
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD1
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
1
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD10
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
10
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD11
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
11
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD12
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
12
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD13
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
13
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD14
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
14
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD15
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
15
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD2
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
2
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD3
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
3
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD4
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
4
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD5
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
5
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD6
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
6
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD7
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
7
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD8
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
8
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD9
Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
9
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
GPIOA_ISRC
GPIOA_ISRC
GPIO Port A Interrupt Source Flag
0x20
read-write
n
0x0
0x0
ISRC0
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
0
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC1
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
1
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC10
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
10
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC11
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
11
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC12
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
12
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC13
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
13
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC14
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
14
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC15
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
15
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC2
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
2
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC3
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
3
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC4
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
4
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC5
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
5
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC6
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
6
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC7
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
7
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC8
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
8
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC9
Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
9
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
GPIOA_OFFD
GPIOA_OFFD
GPIO Port A Pin Digital Input Path Disable Control
0x4
read-write
n
0x0
0x0
OFFD
GPIOx Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, user can disable GPIO digital input path to avoid creepage\n
16
16
read-write
0
Digital I/O input path Enabled
0
1
Digital I/O input path Disabled (digital input tied to low)
1
GPIOA_PIN
GPIOA_PIN
GPIO Port A Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
0
1
read-only
PIN1
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
1
1
read-only
PIN10
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
10
1
read-only
PIN11
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
11
1
read-only
PIN12
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
12
1
read-only
PIN13
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
13
1
read-only
PIN14
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
14
1
read-only
PIN15
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
15
1
read-only
PIN2
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
2
1
read-only
PIN3
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
3
1
read-only
PIN4
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
4
1
read-only
PIN5
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
5
1
read-only
PIN6
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
6
1
read-only
PIN7
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
7
1
read-only
PIN8
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
8
1
read-only
PIN9
Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If the bit is 1. The corresponding pin status is high otherwise, the pin status is low.
9
1
read-only
GPIOA_PMD
GPIOA_PMD
GPIO Port A Pin I/O Mode Control
0x0
-1
read-write
n
0x0
0x0
PMD0
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
0
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD1
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
2
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD10
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
20
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD11
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
22
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD12
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
24
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD13
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
26
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD14
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
28
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD15
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
30
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD2
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
4
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD3
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
6
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD4
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
8
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD5
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
10
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD6
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
12
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD7
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
14
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD8
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
16
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD9
GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type GPIOx pin.\n
18
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
GPIOB_DBEN
GPIOB_DBEN
GPIO Port B De-bounce Enable
0x54
read-write
n
0x0
0x0
GPIOB_DMASK
GPIOB_DMASK
GPIO Port B Data Output Write Mask
0x4C
read-write
n
0x0
0x0
GPIOB_DOUT
GPIOB_DOUT
GPIO Port B Data Output Value
0x48
read-write
n
0x0
0x0
GPIOB_IEN
GPIOB_IEN
GPIO Port B Interrupt Enable
0x5C
read-write
n
0x0
0x0
GPIOB_IMD
GPIOB_IMD
GPIO Port B Interrupt Mode Control
0x58
read-write
n
0x0
0x0
GPIOB_ISRC
GPIOB_ISRC
GPIO Port B Interrupt Source Flag
0x60
read-write
n
0x0
0x0
GPIOB_OFFD
GPIOB_OFFD
GPIO Port B Pin Digital Input Path Disable Control
0x44
read-write
n
0x0
0x0
GPIOB_PIN
GPIOB_PIN
GPIO Port B Pin Value
0x50
read-write
n
0x0
0x0
GPIOB_PMD
GPIOB_PMD
GPIO Port B Pin I/O Mode Control
0x40
read-write
n
0x0
0x0
GPIOC_DBEN
GPIOC_DBEN
GPIO Port C De-bounce Enable
0x94
read-write
n
0x0
0x0
GPIOC_DMASK
GPIOC_DMASK
GPIO Port C Data Output Write Mask
0x8C
read-write
n
0x0
0x0
GPIOC_DOUT
GPIOC_DOUT
GPIO Port C Data Output Value
0x88
read-write
n
0x0
0x0
GPIOC_IEN
GPIOC_IEN
GPIO Port C Interrupt Enable
0x9C
read-write
n
0x0
0x0
GPIOC_IMD
GPIOC_IMD
GPIO Port C Interrupt Mode Control
0x98
read-write
n
0x0
0x0
GPIOC_ISRC
GPIOC_ISRC
GPIO Port C Interrupt Source Flag
0xA0
read-write
n
0x0
0x0
GPIOC_OFFD
GPIOC_OFFD
GPIO Port C Pin Digital Input Path Disable Control
0x84
read-write
n
0x0
0x0
GPIOC_PIN
GPIOC_PIN
GPIO Port C Pin Value
0x90
read-write
n
0x0
0x0
GPIOC_PMD
GPIOC_PMD
GPIO Port C Pin I/O Mode Control
0x80
read-write
n
0x0
0x0
GPIOD_DBEN
GPIOD_DBEN
GPIO Port D De-bounce Enable
0xD4
read-write
n
0x0
0x0
GPIOD_DMASK
GPIOD_DMASK
GPIO Port D Data Output Write Mask
0xCC
read-write
n
0x0
0x0
GPIOD_DOUT
GPIOD_DOUT
GPIO Port D Data Output Value
0xC8
read-write
n
0x0
0x0
GPIOD_IEN
GPIOD_IEN
GPIO Port D Interrupt Enable
0xDC
read-write
n
0x0
0x0
GPIOD_IMD
GPIOD_IMD
GPIO Port D Interrupt Mode Control
0xD8
read-write
n
0x0
0x0
GPIOD_ISRC
GPIOD_ISRC
GPIO Port D Interrupt Source Flag
0xE0
read-write
n
0x0
0x0
GPIOD_OFFD
GPIOD_OFFD
GPIO Port D Pin Digital Input Path Disable Control
0xC4
read-write
n
0x0
0x0
GPIOD_PIN
GPIOD_PIN
GPIO Port D Pin Value
0xD0
read-write
n
0x0
0x0
GPIOD_PMD
GPIOD_PMD
GPIO Port D Pin I/O Mode Control
0xC0
read-write
n
0x0
0x0
GPIOE_DBEN
GPIOE_DBEN
GPIO Port E De-bounce Enable
0x114
read-write
n
0x0
0x0
GPIOE_DMASK
GPIOE_DMASK
GPIO Port E Data Output Write Mask
0x10C
read-write
n
0x0
0x0
GPIOE_DOUT
GPIOE_DOUT
GPIO Port E Data Output Value
0x108
read-write
n
0x0
0x0
GPIOE_IEN
GPIOE_IEN
GPIO Port E Interrupt Enable
0x11C
read-write
n
0x0
0x0
GPIOE_IMD
GPIOE_IMD
GPIO Port E Interrupt Mode Control
0x118
read-write
n
0x0
0x0
GPIOE_ISRC
GPIOE_ISRC
GPIO Port E Interrupt Source Flag
0x120
read-write
n
0x0
0x0
GPIOE_OFFD
GPIOE_OFFD
GPIO Port E Pin Digital Input Path Disable Control
0x104
read-write
n
0x0
0x0
GPIOE_PIN
GPIOE_PIN
GPIO Port E Pin Value
0x110
read-write
n
0x0
0x0
GPIOE_PMD
GPIOE_PMD
GPIO Port E Pin I/O Mode Control
0x100
read-write
n
0x0
0x0
PA0_PDIO
PA0_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x200
-1
read-write
n
0x0
0x0
Pxn_PDIO
GPIO Px.n Pin Data I/O\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example, writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0], read PA0_PDIO will return the value of GPIOA_PIN[0]\nNote: The write operation will not be affected by register GPIOx_DMASK.
0
1
read-write
0
Corresponding GPIO pin set to low
#0
1
Corresponding GPIO pin set to high
#1
PA10_PDIO
PA10_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x228
read-write
n
0x0
0x0
PA11_PDIO
PA11_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x22C
read-write
n
0x0
0x0
PA12_PDIO
PA12_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x230
read-write
n
0x0
0x0
PA13_PDIO
PA13_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x234
read-write
n
0x0
0x0
PA14_PDIO
PA14_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x238
read-write
n
0x0
0x0
PA15_PDIO
PA15_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x23C
read-write
n
0x0
0x0
PA1_PDIO
PA1_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x204
read-write
n
0x0
0x0
PA2_PDIO
PA2_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x208
read-write
n
0x0
0x0
PA3_PDIO
PA3_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x20C
read-write
n
0x0
0x0
PA4_PDIO
PA4_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x210
read-write
n
0x0
0x0
PA5_PDIO
PA5_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x214
read-write
n
0x0
0x0
PA6_PDIO
PA6_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x218
read-write
n
0x0
0x0
PA7_PDIO
PA7_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x21C
read-write
n
0x0
0x0
PA8_PDIO
PA8_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x220
read-write
n
0x0
0x0
PA9_PDIO
PA9_PDIO
GPIO PA.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x224
read-write
n
0x0
0x0
PB0_PDIO
PB0_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x240
read-write
n
0x0
0x0
PB10_PDIO
PB10_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x268
read-write
n
0x0
0x0
PB11_PDIO
PB11_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x26C
read-write
n
0x0
0x0
PB12_PDIO
PB12_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x270
read-write
n
0x0
0x0
PB13_PDIO
PB13_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x274
read-write
n
0x0
0x0
PB14_PDIO
PB14_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x278
read-write
n
0x0
0x0
PB15_PDIO
PB15_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x27C
read-write
n
0x0
0x0
PB1_PDIO
PB1_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x244
read-write
n
0x0
0x0
PB2_PDIO
PB2_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x248
read-write
n
0x0
0x0
PB3_PDIO
PB3_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x24C
read-write
n
0x0
0x0
PB4_PDIO
PB4_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x250
read-write
n
0x0
0x0
PB5_PDIO
PB5_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x254
read-write
n
0x0
0x0
PB6_PDIO
PB6_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x258
read-write
n
0x0
0x0
PB7_PDIO
PB7_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x25C
read-write
n
0x0
0x0
PB8_PDIO
PB8_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x260
read-write
n
0x0
0x0
PB9_PDIO
PB9_PDIO
GPIO PB.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x264
read-write
n
0x0
0x0
PC0_PDIO
PC0_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x280
read-write
n
0x0
0x0
PC10_PDIO
PC10_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2A8
read-write
n
0x0
0x0
PC11_PDIO
PC11_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2AC
read-write
n
0x0
0x0
PC12_PDIO
PC12_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2B0
read-write
n
0x0
0x0
PC13_PDIO
PC13_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2B4
read-write
n
0x0
0x0
PC14_PDIO
PC14_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2B8
read-write
n
0x0
0x0
PC15_PDIO
PC15_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2BC
read-write
n
0x0
0x0
PC1_PDIO
PC1_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x284
read-write
n
0x0
0x0
PC2_PDIO
PC2_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x288
read-write
n
0x0
0x0
PC3_PDIO
PC3_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x28C
read-write
n
0x0
0x0
PC4_PDIO
PC4_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x290
read-write
n
0x0
0x0
PC5_PDIO
PC5_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x294
read-write
n
0x0
0x0
PC6_PDIO
PC6_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x298
read-write
n
0x0
0x0
PC7_PDIO
PC7_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x29C
read-write
n
0x0
0x0
PC8_PDIO
PC8_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2A0
read-write
n
0x0
0x0
PC9_PDIO
PC9_PDIO
GPIO PC.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2A4
read-write
n
0x0
0x0
PD0_PDIO
PD0_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2C0
read-write
n
0x0
0x0
PD10_PDIO
PD10_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2E8
read-write
n
0x0
0x0
PD11_PDIO
PD11_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2EC
read-write
n
0x0
0x0
PD12_PDIO
PD12_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2F0
read-write
n
0x0
0x0
PD13_PDIO
PD13_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2F4
read-write
n
0x0
0x0
PD14_PDIO
PD14_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2F8
read-write
n
0x0
0x0
PD15_PDIO
PD15_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2FC
read-write
n
0x0
0x0
PD1_PDIO
PD1_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2C4
read-write
n
0x0
0x0
PD2_PDIO
PD2_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2C8
read-write
n
0x0
0x0
PD3_PDIO
PD3_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2CC
read-write
n
0x0
0x0
PD4_PDIO
PD4_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2D0
read-write
n
0x0
0x0
PD5_PDIO
PD5_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2D4
read-write
n
0x0
0x0
PD6_PDIO
PD6_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2D8
read-write
n
0x0
0x0
PD7_PDIO
PD7_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2DC
read-write
n
0x0
0x0
PD8_PDIO
PD8_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2E0
read-write
n
0x0
0x0
PD9_PDIO
PD9_PDIO
GPIO PD.n Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x2E4
read-write
n
0x0
0x0
PE5_PDIO
PE5_PDIO
GPIO PE.5 Pin Data Input/Output\n(NuMicro( NUC100/NUC120 Low Density Only)
0x314
read-write
n
0x0
0x0
I2C0
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
I2CADDR0
I2CADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
GC
General Call Function\n
0
1
read-write
0
General Call function Disabled
#0
1
General Call function Enabled
#1
I2CADDR
I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
I2CADDR1
I2CADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
I2CADDR2
I2CADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2CADDR3
I2CADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2CADM0
I2CADM0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
I2CADM
I2C Address Mask register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask disable (the received corresponding register bit should be exact the same as address register.)
0
1
Mask enable (the received corresponding address bit is don't care.)
1
I2CADM1
I2CADM1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2CADM2
I2CADM2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2CADM3
I2CADM3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2CDAT
I2CDAT
I2C Data Register
0x8
read-write
n
0x0
0x0
I2CDAT
I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2CLK
I2CLK
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
I2CLK
I2C clock divided Register\nNote: the minimum value of I2CLK is 4.
0
8
read-write
I2CON
I2CON
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control Bit\n
2
1
read-write
EI
Enable Interrupt\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
ENS1
I2C Controller Enable Bit\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit.
3
1
read-write
STA
I2C START Control Bit\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control Bit
In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2CSTATUS
I2CSTATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
I2CSTATUS
I2C Status Register\nThe status register of I2C:\n
0
8
read-only
I2CTOC
I2CTOC
I2C Time Out Control Register
0x14
read-write
n
0x0
0x0
DIV4
Time-Out counter input clock is divided by 4\nWhen Enabled, The time-Out period is extend 4 times.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
ENTI
Time-out counter is enabled/disable\nWhen Enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
TIF
Time-Out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nS/W can write 1 to clear this bit.
0
1
read-write
I2C1
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
I2CADDR0
I2CADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
GC
General Call Function\n
0
1
read-write
0
General Call function Disabled
#0
1
General Call function Enabled
#1
I2CADDR
I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
I2CADDR1
I2CADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
I2CADDR2
I2CADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2CADDR3
I2CADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2CADM0
I2CADM0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
I2CADM
I2C Address Mask register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask disable (the received corresponding register bit should be exact the same as address register.)
0
1
Mask enable (the received corresponding address bit is don't care.)
1
I2CADM1
I2CADM1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2CADM2
I2CADM2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2CADM3
I2CADM3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2CDAT
I2CDAT
I2C Data Register
0x8
read-write
n
0x0
0x0
I2CDAT
I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2CLK
I2CLK
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
I2CLK
I2C clock divided Register\nNote: the minimum value of I2CLK is 4.
0
8
read-write
I2CON
I2CON
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control Bit\n
2
1
read-write
EI
Enable Interrupt\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
ENS1
I2C Controller Enable Bit\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit.
3
1
read-write
STA
I2C START Control Bit\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control Bit
In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2CSTATUS
I2CSTATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
I2CSTATUS
I2C Status Register\nThe status register of I2C:\n
0
8
read-only
I2CTOC
I2CTOC
I2C Time Out Control Register
0x14
read-write
n
0x0
0x0
DIV4
Time-Out counter input clock is divided by 4\nWhen Enabled, The time-Out period is extend 4 times.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
ENTI
Time-out counter is enabled/disable\nWhen Enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
TIF
Time-Out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nS/W can write 1 to clear this bit.
0
1
read-write
I2S
I2S Register Map
I2S
0x0
0x0
0x18
registers
n
I2SCLKDIV
I2SCLKDIV
I2S Clock Divider Register
0x4
read-write
n
0x0
0x0
BCLK_DIV
Bit Clock Divider\nIf I2S operates in Master mode, bit clock is provided by the NuMicro( NUC100 series. Software can program these bits to generate sampling rate clock frequency.\n
8
8
read-write
MCLK_DIV
Master Clock Divider\nIf chip external crystal frequency is (2xMCLK_DIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLK_DIV is set to 0, MCLK is the same as external clock input.\n
0
3
read-write
I2SCON
I2SCON
I2S Control Register
0x0
read-write
n
0x0
0x0
CLR_RXFIFO
Clear Receive FIFO\nWrite 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXFIFO_LEVEL[3:0] returns 0 and receive FIFO becomes empty.\nThis bit is cleared by hardware automatically, read it return zero.
19
1
read-write
CLR_TXFIFO
Clear Transmit FIFO\nWrite 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXFIFO_LEVEL[3:0] returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nThis bit is clear by hardware automatically, read it return zero.
18
1
read-write
FORMAT
Data Format\n
7
1
read-write
0
I2S data format
#0
1
MSB justified data format
#1
I2SEN
I2S Controller Enable\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
LCHZCEN
Left channel zero-cross Detect Enable\nIf this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF flag in I2SSTATUS register is set to 1.\n
17
1
read-write
0
Left channel zero-cross detect Disabled
#0
1
Left channel zero-cross detect Enabled
#1
MCLKEN
Master Clock Enable\nIf the external crystal clock in NuMicro( NUC100 series is frequency 2*N*256fs, software can program MCLK_DIV[2:0] in I2SCLKDIV register to get 256fs clock to audio codec chip.\n
15
1
read-write
0
Master clock Disabled
#0
1
Master clock Enabled
#1
MONO
Monaural Data\nNote: when chip records data, only right channel data will be saved if monaural format is select.
6
1
read-write
0
Data is stereo format
#0
1
Data is monaural format
#1
MUTE
Transmit Mute Enable\n
3
1
read-write
0
Transmit data is shifted from buffer
#0
1
Transmit channel zero
#1
RCHZCEN
Right Channel Zero-cross Detection Enable\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all zero then RZCF flag in I2SSTATUS register is set to 1.\n
16
1
read-write
0
Right channel zero-cross detect Disabled
#0
1
Right channel zero-cross detect Enabled
#1
RXDMA
Enable Receive DMA\nWhen RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.\n
21
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
RXEN
Receive Enable\n
2
1
read-write
0
Data receiving Disabled
#0
1
Data receiving Enabled
#1
RXTH
Receive FIFO Threshold Level\nWhen received data word(s) in buffer is equal to or higher than threshold level then RXTHF flag is set.\n
12
3
read-write
0
1 word data in receive FIFO
#000
1
2 word data in receive FIFO
#001
2
3 word data in receive FIFO
#010
3
4 word data in receive FIFO
#011
4
5 word data in receive FIFO
#100
5
6 word data in receive FIFO
#101
6
7 word data in receive FIFO
#110
7
8 word data in receive FIFO
#111
SLAVE
Slave Mode\nI2S can operate as master or slave. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro( NUC100 series to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.\n
8
1
read-write
0
Master mode
#0
1
Slave mode
#1
TXDMA
Enable Transmit DMA\nWhen TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.\n
20
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
TXEN
Transmit Enable\n
1
1
read-write
0
Data transmission Disabled
#0
1
Data transmission Enabled
#1
TXTH
Transmit FIFO Threshold Level\nIf remain data word (32 bits) in transmit FIFO is the same or less than threshold level then TXTHF flag is set.\n
9
3
read-write
0
0 word data in transmit FIFO
#000
1
1 word data in transmit FIFO
#001
2
2 words data in transmit FIFO
#010
3
3 words data in transmit FIFO
#011
4
4 words data in transmit FIFO
#100
5
5 words data in transmit FIFO
#101
6
6 words data in transmit FIFO
#110
7
7 words data in transmit FIFO
#111
WORDWIDTH
Word Width\n
4
2
read-write
0
data is 8-bit
#00
1
data is 16-bit
#01
2
data is 24-bit
#10
3
data is 32-bit
#11
I2SIE
I2SIE
I2S Interrupt Enable Register
0x8
read-write
n
0x0
0x0
LZCIE
Left Channel Zero-cross interrupt Enable\nInterrupt occur if this bit is set to 1 and left channel zero-cross \n
12
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXOVFIE
Receive FIFO Overflow Interrupt Enable\n
1
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXTHIE
Receive FIFO Threshold Level Interrupt Enable\nWhen data word in receive FIFO is equal or higher then RXTH[2:0] and the RXTHF bit is set to 1. If RXTHIE bit is enabled, interrupt occur.\n
2
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXUDFIE
Receive FIFO Underflow Interrupt Enable\nIf software read receive FIFO when it is empty then RXUDF flag in I2SSTATUS register is set to 1.\n
0
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RZCIE
Right Channel zero-cross interrupt Enable\n
11
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXOVFIE
Transmit FIFO Overflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1\n
9
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXTHIE
Transmit FIFO Threshold Level Interrupt Enable\nInterrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[2:0].\n
10
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXUDFIE
Transmit FIFO Underflow Interrupt Enable\nInterrupt occur if this bit is set to 1 and transmit FIFO underflow flag is set to 1.\n
8
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
I2SRXFIFO
I2SRXFIFO
I2S Receive FIFO Register
0x14
read-only
n
0x0
0x0
RXFIFO
Receive FIFO register\nI2S contains 8 words (8x32 bit) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RX_LEVEL[3:0] in I2SSTATUS register.
0
32
read-only
I2SSTATUS
I2SSTATUS
I2S Status Register
0xC
-1
read-write
n
0x0
0x0
I2SINT
I2S Interrupt Flag\nIt is wire-OR of I2STXINT and I2SRXINT bits.\nThis bit is read only.
0
1
read-write
0
No I2S interrupt
#0
1
I2S interrupt
#1
I2SRXINT
I2S Receive Interrupt\nThis bit is read only.
1
1
read-write
0
No receive interrupt
#0
1
Receive interrupt
#1
I2STXINT
I2S Transmit Interrupt\nThis bit is read only
2
1
read-write
0
No transmit interrupt
#0
1
Transmit interrupt
#1
LZCF
Left Channel Zero-cross Flag\nIt indicates left channel next sample data sign bit is changed or all data bits are zero.\nWrite 1 to clear this bit to 0.
23
1
read-write
0
No zero-cross
#0
1
Left channel zero-cross is detected
#1
RIGHT
Right Channel\nThis bit indicate current transmit data is belong to right channel\nThis bit is read only
3
1
read-write
0
Left channel
#0
1
Right channel
#1
RXEMPTY
Receive FIFO Empty\nThis bit reflects data words number in receive FIFO is zero\nThis bit is read only.
12
1
read-write
0
Not empty
#0
1
Empty
#1
RXFULL
Receive FIFO Full\nThis bit reflect data words number in receive FIFO is 8\nThis bit is read only.
11
1
read-write
0
Not full
#0
1
Full
#1
RXOVF
Receive FIFO Overflow Flag\nWhen receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.\nWrite 1 to clear this bit to 0.
9
1
read-write
0
No overflow occur
#0
1
Overflow occur
#1
RXTHF
Receive FIFO Threshold Flag\nWhen data word(s) in receive FIFO is equal or higher than threshold value set in RXTH[2:0] the RXTHF bit becomes to 1. It keeps at 1 till RXFIFO_LEVEL[3:0] less than RXTH[1:0] after software read RXFIFO register.\nThis bit is read only.
10
1
read-write
0
Data word(s) in FIFO is lower than threshold level
#0
1
Data word(s) in FIFO is equal or higher than threshold level
#1
RXUDF
Receive FIFO Underflow Flag\nRead receive FIFO when it is empty, this bit set to 1 indicate underflow occur.\nWrite 1 to clear this bit to zero
8
1
read-write
0
No underflow occur
#0
1
Underflow occur
#1
RX_LEVEL
Receive FIFO Level\nThese bits indicate word number in receive FIFO\n
24
4
read-write
0
No data
#0000
1
1 word in receive FIFO
#0001
8
8 words in receive FIFO
#1000
RZCF
Right Channel Zero-cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are zero.\nWrite 1 to clear this bit to 0.
22
1
read-write
0
No zero-cross
#0
1
Right channel zero-cross is detected
#1
TXBUSY
Transmit Busy\nThis bit is clear to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer. \nThis bit is read only.
21
1
read-write
0
Transmit shift buffer is empty
#0
1
Transmit shift buffer is busy
#1
TXEMPTY
Transmit FIFO Empty\nThis bit reflect data word number in transmit FIFO is zero\nThis bit is read only.
20
1
read-write
0
Not empty
#0
1
Empty
#1
TXFULL
Transmit FIFO Full\nThis bit reflect data word number in transmit FIFO is 8\nThis bit is read only
19
1
read-write
0
Not full
#0
1
Full
#1
TXOVF
Transmit FIFO Overflow Flag\nWrite data to transmit FIFO when it is full and this bit set to 1\nWrite 1 to clear this bit to 0.
17
1
read-write
0
No overflow
#0
1
Overflow
#1
TXTHF
Transmit FIFO Threshold Flag\nWhen data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH[2:0] the TXTHF bit becomes to 1. It keeps at 1 till TXFIFO_LEVEL[3:0] is higher than TXTH[1:0] after software write TXFIFO register.\nThis bit is read only
18
1
read-write
0
Data word(s) in FIFO is higher than threshold level
#0
1
Data word(s) in FIFO is equal or lower than threshold level
#1
TXUDF
Transmit FIFO Underflow Flag\nWhen transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.\nWrite 1 to clear this bit to 0.
16
1
read-write
0
No underflow
#0
1
Underflow
#1
TX_LEVEL
Transmit FIFO Level\nThese bits indicate word number in transmit FIFO\n
28
4
read-write
0
No data
#0000
1
1 word in transmit FIFO
#0001
8
8 words in transmit FIFO
#1000
I2STXFIFO
I2STXFIFO
I2S Transmit FIFO Register
0x10
write-only
n
0x0
0x0
TXFIFO
Transmit FIFO Register\nI2S contains 8 words (8x32 bit) data buffer for data transmit. Write data to this register to prepare data for transmit. The remaining word number is indicated by TX_LEVEL[3:0] in I2SSTATUS.
0
32
write-only
INT
INT Register Map
INT
0x0
0x0
0x88
registers
n
IRQ0_SRC
IRQ0_SRC
IRQ0 (BOD) Interrupt Source Identity
0x0
read-only
n
0x0
0x0
INT_SRC
Interrupt Source\nDefine the interrupt sources for interrupt event.
0
4
read-only
IRQ10_SRC
IRQ10_SRC
IRQ10 (TMR2) Interrupt Source Identity
0x28
read-write
n
0x0
0x0
IRQ11_SRC
IRQ11_SRC
IRQ11 (TMR3) Interrupt Source Identity
0x2C
read-write
n
0x0
0x0
IRQ12_SRC
IRQ12_SRC
IRQ12 (UART0) Interrupt Source Identity
0x30
read-write
n
0x0
0x0
IRQ13_SRC
IRQ13_SRC
IRQ13 (UART1) Interrupt Source Identity
0x34
read-write
n
0x0
0x0
IRQ14_SRC
IRQ14_SRC
IRQ14 (SPI0) Interrupt Source Identity
0x38
read-write
n
0x0
0x0
IRQ15_SRC
IRQ15_SRC
IRQ15 (SPI1) Interrupt Source Identity
0x3C
read-write
n
0x0
0x0
IRQ16_SRC
IRQ16_SRC
IRQ16 (SPI2) Interrupt Source Identity
0x40
read-write
n
0x0
0x0
IRQ17_SRC
IRQ17_SRC
IRQ17 (SPI3)) Interrupt Source Identity
0x44
read-write
n
0x0
0x0
IRQ18_SRC
IRQ18_SRC
IRQ18 (I2C0) Interrupt Source Identity
0x48
read-write
n
0x0
0x0
IRQ19_SRC
IRQ19_SRC
IRQ19 (I2C1) Interrupt Source Identity
0x4C
read-write
n
0x0
0x0
IRQ1_SRC
IRQ1_SRC
IRQ1 (WDT) Interrupt Source Identity
0x4
read-write
n
0x0
0x0
IRQ20_SRC
IRQ20_SRC
IRQ20 (Reserved) Interrupt Source Identity
0x50
read-write
n
0x0
0x0
IRQ21_SRC
IRQ21_SRC
IRQ21 (Reserved) Interrupt Source Identity
0x54
read-write
n
0x0
0x0
IRQ22_SRC
IRQ22_SRC
IRQ22 (Reserved) Interrupt Source Identity
0x58
read-write
n
0x0
0x0
IRQ23_SRC
IRQ23_SRC
IRQ23 (USBD) Interrupt Source Identity
0x5C
read-write
n
0x0
0x0
IRQ24_SRC
IRQ24_SRC
IRQ24 (PS/2) Interrupt Source Identity
0x60
read-write
n
0x0
0x0
IRQ25_SRC
IRQ25_SRC
IRQ25 (ACMP) Interrupt Source Identity
0x64
read-write
n
0x0
0x0
IRQ26_SRC
IRQ26_SRC
IRQ26 (PDMA) Interrupt Source Identity
0x68
read-write
n
0x0
0x0
IRQ27_SRC
IRQ27_SRC
IRQ27 (I2S) Interrupt Source Identity
0x6C
read-write
n
0x0
0x0
IRQ28_SRC
IRQ28_SRC
IRQ28 (PWRWU) Interrupt Source Identity
0x70
read-write
n
0x0
0x0
IRQ29_SRC
IRQ29_SRC
IRQ29 (ADC) Interrupt Source Identity
0x74
read-write
n
0x0
0x0
IRQ2_SRC
IRQ2_SRC
IRQ2 (EINT0) Interrupt Source Identity
0x8
read-write
n
0x0
0x0
IRQ30_SRC
IRQ30_SRC
IRQ30 (Reserved) Interrupt Source Identity
0x78
read-write
n
0x0
0x0
IRQ31_SRC
IRQ31_SRC
IRQ31 (RTC) Interrupt Source Identity
0x7C
read-write
n
0x0
0x0
IRQ3_SRC
IRQ3_SRC
IRQ3 (EINT1) Interrupt Source Identity
0xC
read-write
n
0x0
0x0
IRQ4_SRC
IRQ4_SRC
IRQ4 (GPA/B) Interrupt Source Identity
0x10
read-write
n
0x0
0x0
IRQ5_SRC
IRQ5_SRC
IRQ5 (GPC/D/E) Interrupt Source Identity
0x14
read-write
n
0x0
0x0
IRQ6_SRC
IRQ6_SRC
IRQ6 (PWMA) Interrupt Source Identity
0x18
read-write
n
0x0
0x0
IRQ7_SRC
IRQ7_SRC
IRQ7 (PWMB) Interrupt Source Identity
0x1C
read-write
n
0x0
0x0
IRQ8_SRC
IRQ8_SRC
IRQ8 (TMR0) Interrupt Source Identity
0x20
read-write
n
0x0
0x0
IRQ9_SRC
IRQ9_SRC
IRQ9 (TMR1) Interrupt Source Identity
0x24
read-write
n
0x0
0x0
MCU_IRQ
MCU_IRQ
MCU IRQ Number Identity Register
0x84
read-write
n
0x0
0x0
MCU_IRQ
MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0. There are two modes to generate interrupt to Cortex-M0, the normal mode and test mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0: Set MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting MCU_IRQ[n] 1 will clear the interrupt and setting MCU_IRQ[n] 0 has no effect.
0
32
read-write
NMI_SEL
NMI_SEL
NMI Source Interrupt Select Control Register
0x80
read-write
n
0x0
0x0
NMI_SEL
NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL.
0
5
read-write
PDMA_ch0
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR
PDMA_BCR
PDMA Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA, which must be word alignment.
0
16
read-write
PDMA_CBCR
PDMA_CBCR
PDMA Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value.
0
16
read-only
PDMA_CDAR
PDMA_CDAR
PDMA Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR
PDMA_CSAR
PDMA Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSR
PDMA_CSR
PDMA Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer Destination address is increasing successively
#00
1
Reserved
#01
2
Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer Source address is increasing successively
#00
1
Reserved
#01
2
Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will auto clear after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer is completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DAR
PDMA_DAR
PDMA Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IER
PDMA_IER
PDMA Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISR
PDMA_ISR
PDMA Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINT
PDMA_POINT
PDMA Internal Buffer Pointer
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
2
read-only
PDMA_SAR
PDMA_SAR
PDMA Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment
0
32
read-write
PDMA_SBUF0_c
PDMA_SBUF0_c
PDMA Shared Buffer FIFO 0
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 words internal buffer.
0
32
read-only
PDMA_ch1
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR
PDMA_BCR
PDMA Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA, which must be word alignment.
0
16
read-write
PDMA_CBCR
PDMA_CBCR
PDMA Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value.
0
16
read-only
PDMA_CDAR
PDMA_CDAR
PDMA Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR
PDMA_CSAR
PDMA Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSR
PDMA_CSR
PDMA Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer Destination address is increasing successively
#00
1
Reserved
#01
2
Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer Source address is increasing successively
#00
1
Reserved
#01
2
Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will auto clear after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer is completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DAR
PDMA_DAR
PDMA Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IER
PDMA_IER
PDMA Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISR
PDMA_ISR
PDMA Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINT
PDMA_POINT
PDMA Internal Buffer Pointer
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
2
read-only
PDMA_SAR
PDMA_SAR
PDMA Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment
0
32
read-write
PDMA_SBUF0_c
PDMA_SBUF0_c
PDMA Shared Buffer FIFO 0
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 words internal buffer.
0
32
read-only
PDMA_ch2
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR
PDMA_BCR
PDMA Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA, which must be word alignment.
0
16
read-write
PDMA_CBCR
PDMA_CBCR
PDMA Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value.
0
16
read-only
PDMA_CDAR
PDMA_CDAR
PDMA Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR
PDMA_CSAR
PDMA Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSR
PDMA_CSR
PDMA Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer Destination address is increasing successively
#00
1
Reserved
#01
2
Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer Source address is increasing successively
#00
1
Reserved
#01
2
Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will auto clear after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer is completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DAR
PDMA_DAR
PDMA Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IER
PDMA_IER
PDMA Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISR
PDMA_ISR
PDMA Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINT
PDMA_POINT
PDMA Internal Buffer Pointer
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
2
read-only
PDMA_SAR
PDMA_SAR
PDMA Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment
0
32
read-write
PDMA_SBUF0_c
PDMA_SBUF0_c
PDMA Shared Buffer FIFO 0
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 words internal buffer.
0
32
read-only
PDMA_ch3
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR
PDMA_BCR
PDMA Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA, which must be word alignment.
0
16
read-write
PDMA_CBCR
PDMA_CBCR
PDMA Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value.
0
16
read-only
PDMA_CDAR
PDMA_CDAR
PDMA Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR
PDMA_CSAR
PDMA Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSR
PDMA_CSR
PDMA Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer Destination address is increasing successively
#00
1
Reserved
#01
2
Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer Source address is increasing successively
#00
1
Reserved
#01
2
Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will auto clear after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer is completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DAR
PDMA_DAR
PDMA Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IER
PDMA_IER
PDMA Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISR
PDMA_ISR
PDMA Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINT
PDMA_POINT
PDMA Internal Buffer Pointer
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
2
read-only
PDMA_SAR
PDMA_SAR
PDMA Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment
0
32
read-write
PDMA_SBUF0_c
PDMA_SBUF0_c
PDMA Shared Buffer FIFO 0
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 words internal buffer.
0
32
read-only
PDMA_ch4
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR
PDMA_BCR
PDMA Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA, which must be word alignment.
0
16
read-write
PDMA_CBCR
PDMA_CBCR
PDMA Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value.
0
16
read-only
PDMA_CDAR
PDMA_CDAR
PDMA Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR
PDMA_CSAR
PDMA Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSR
PDMA_CSR
PDMA Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer Destination address is increasing successively
#00
1
Reserved
#01
2
Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer Source address is increasing successively
#00
1
Reserved
#01
2
Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will auto clear after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer is completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DAR
PDMA_DAR
PDMA Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IER
PDMA_IER
PDMA Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISR
PDMA_ISR
PDMA Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINT
PDMA_POINT
PDMA Internal Buffer Pointer
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
2
read-only
PDMA_SAR
PDMA_SAR
PDMA Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment
0
32
read-write
PDMA_SBUF0_c
PDMA_SBUF0_c
PDMA Shared Buffer FIFO 0
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 words internal buffer.
0
32
read-only
PDMA_ch5
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR
PDMA_BCR
PDMA Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA, which must be word alignment.
0
16
read-write
PDMA_CBCR
PDMA_CBCR
PDMA Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value.
0
16
read-only
PDMA_CDAR
PDMA_CDAR
PDMA Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR
PDMA_CSAR
PDMA Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSR
PDMA_CSR
PDMA Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer Destination address is increasing successively
#00
1
Reserved
#01
2
Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer Source address is increasing successively
#00
1
Reserved
#01
2
Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will auto clear after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer is completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DAR
PDMA_DAR
PDMA Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IER
PDMA_IER
PDMA Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISR
PDMA_ISR
PDMA Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINT
PDMA_POINT
PDMA Internal Buffer Pointer
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
2
read-only
PDMA_SAR
PDMA_SAR
PDMA Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment
0
32
read-write
PDMA_SBUF0_c
PDMA_SBUF0_c
PDMA Shared Buffer FIFO 0
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 words internal buffer.
0
32
read-only
PDMA_ch6
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR
PDMA_BCR
PDMA Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA, which must be word alignment.
0
16
read-write
PDMA_CBCR
PDMA_CBCR
PDMA Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value.
0
16
read-only
PDMA_CDAR
PDMA_CDAR
PDMA Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR
PDMA_CSAR
PDMA Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSR
PDMA_CSR
PDMA Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer Destination address is increasing successively
#00
1
Reserved
#01
2
Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer Source address is increasing successively
#00
1
Reserved
#01
2
Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will auto clear after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer is completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DAR
PDMA_DAR
PDMA Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IER
PDMA_IER
PDMA Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISR
PDMA_ISR
PDMA Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINT
PDMA_POINT
PDMA Internal Buffer Pointer
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
2
read-only
PDMA_SAR
PDMA_SAR
PDMA Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment
0
32
read-write
PDMA_SBUF0_c
PDMA_SBUF0_c
PDMA Shared Buffer FIFO 0
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 words internal buffer.
0
32
read-only
PDMA_ch7
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR
PDMA_BCR
PDMA Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA, which must be word alignment.
0
16
read-write
PDMA_CBCR
PDMA_CBCR
PDMA Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value.
0
16
read-only
PDMA_CDAR
PDMA_CDAR
PDMA Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR
PDMA_CSAR
PDMA Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSR
PDMA_CSR
PDMA Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer Destination address is increasing successively
#00
1
Reserved
#01
2
Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer Source address is increasing successively
#00
1
Reserved
#01
2
Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will auto clear after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer is completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DAR
PDMA_DAR
PDMA Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IER
PDMA_IER
PDMA Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISR
PDMA_ISR
PDMA Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINT
PDMA_POINT
PDMA Internal Buffer Pointer
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
2
read-only
PDMA_SAR
PDMA_SAR
PDMA Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment
0
32
read-write
PDMA_SBUF0_c
PDMA_SBUF0_c
PDMA Shared Buffer FIFO 0
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 words internal buffer.
0
32
read-only
PDMA_ch8
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR
PDMA_BCR
PDMA Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA, which must be word alignment.
0
16
read-write
PDMA_CBCR
PDMA_CBCR
PDMA Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value.
0
16
read-only
PDMA_CDAR
PDMA_CDAR
PDMA Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR
PDMA_CSAR
PDMA Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSR
PDMA_CSR
PDMA Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer Destination address is increasing successively
#00
1
Reserved
#01
2
Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer Source address is increasing successively
#00
1
Reserved
#01
2
Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will auto clear after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer is completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DAR
PDMA_DAR
PDMA Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IER
PDMA_IER
PDMA Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISR
PDMA_ISR
PDMA Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINT
PDMA_POINT
PDMA Internal Buffer Pointer
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
2
read-only
PDMA_SAR
PDMA_SAR
PDMA Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment
0
32
read-write
PDMA_SBUF0_c
PDMA_SBUF0_c
PDMA Shared Buffer FIFO 0
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 words internal buffer.
0
32
read-only
PDMA_GCR
PDMA Register Map
PDMA
0x0
0x0
0x14
registers
n
PDMA_GCRCSR
PDMA_GCRCSR
PDMA Global Control Register
0x0
read-write
n
0x0
0x0
CLK0_EN
PDMA Controller Channel 0 Clock Enable Control\n
8
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK1_EN
PDMA Controller Channel 1 Clock Enable Control (NuMicro( NUC100/NUC120 Medium Density Only)\n
9
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK2_EN
PDMA Controller Channel 2 Clock Enable Control (NuMicro( NUC100/NUC120 Medium Density Only)\n
10
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK3_EN
PDMA Controller Channel 3 Clock Enable Control (NuMicro( NUC100/NUC120 Medium Density Only)\n
11
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK4_EN
PDMA Controller Channel 4 Clock Enable Control (NuMicro( NUC100/NUC120 Medium Density Only)\n
12
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK5_EN
PDMA Controller Channel 5 Clock Enable Control (NuMicro( NUC100/NUC120 Medium Density Only)\n
13
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK6_EN
PDMA Controller Channel 6 Clock Enable Control (NuMicro( NUC100/NUC120 Medium Density Only)\n
14
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK7_EN
PDMA Controller Channel 7 Clock Enable Control (NuMicro( NUC100/NUC120 Medium Density Only)\n
15
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK8_EN
PDMA Controller Channel 8 Clock Enable Control (NuMicro( NUC100/NUC120 Medium Density Only)\n
16
1
read-write
0
Disabled
#0
1
Enabled
#1
PDMA_GCRISR
PDMA_GCRISR
PDMA Global Interrupt Register
0xC
read-only
n
0x0
0x0
INTR
Interrupt Pin Status\nThis bit is the Interrupt status of PDMA controller.\nNote: This bit is read only
31
1
read-only
INTR0
Interrupt Pin Status of Channel 0\nThis bit is the Interrupt status of PDMA channel0.\nNote: This bit is read only
0
1
read-only
INTR1
Interrupt Pin Status of Channel 1 (NuMicro( NUC100/NUC120 Medium Density Only)\nThis bit is the Interrupt status of PDMA channel1.\nNote: This bit is read only
1
1
read-only
INTR2
Interrupt Pin Status of Channel 2 (NuMicro( NUC100/NUC120 Medium Density Only)\nThis bit is the Interrupt status of PDMA channel2.\nNote: This bit is read only
2
1
read-only
INTR3
Interrupt Pin Status of Channel 3 (NuMicro( NUC100/NUC120 Medium Density Only)\nThis bit is the Interrupt status of PDMA channel3.\nNote: This bit is read only
3
1
read-only
INTR4
Interrupt Pin Status of Channel 4 (NuMicro( NUC100/NUC120 Medium Density Only)\nThis bit is the Interrupt status of PDMA channel4.\nNote: This bit is read only
4
1
read-only
INTR5
Interrupt Pin Status of Channel 5 (NuMicro( NUC100/NUC120 Medium Density Only)\nThis bit is the Interrupt status of PDMA channel5.\nNote: This bit is read only
5
1
read-only
INTR6
Interrupt Pin Status of Channel 6 (NuMicro( NUC100/NUC120 Medium Density Only)\nThis bit is the Interrupt status of PDMA channel6.\nNote: This bit is read only
6
1
read-only
INTR7
Interrupt Pin Status of Channel 7 (NuMicro( NUC100/NUC120 Medium Density Only)\nThis bit is the Interrupt status of PDMA channel7.\nNote: This bit is read only
7
1
read-only
INTR8
Interrupt Pin Status of Channel 8 (NuMicro( NUC100/NUC120 Medium Density Only)\nThis bit is the Interrupt status of PDMA channel8.\nNote: This bit is read only
8
1
read-only
PDMA_PDSSR0
PDMA_PDSSR0
PDMA Service Selection Control Register 0
0x4
-1
read-write
n
0x0
0x0
SPI0_RXSEL
PDMA SPI0 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI0 RX. Software can change the channel RX setting by SPI0_RXSEL\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4 \n4'b0101: CH5\n4'b0110: CH6\n4'b0111: CH7\n4'b1000: CH8\nOthers : Reserved\n(The NuMicro( NUC100/NUC120 Low Density should ne set as 4'b0000 for PDMA channel 0 only.)
0
4
read-write
SPI0_TXSEL
PDMA SPI0 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI0 TX. Software can configure the TX channel setting by SPI0_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
4
4
read-write
SPI1_RXSEL
PDMA SPI1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI1 RX. Software can configure the RX channel setting by SPI1_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
8
4
read-write
SPI1_TXSEL
PDMA SPI1 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI1 TX. Software can configure the TX channel setting by SPI1_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
12
4
read-write
SPI2_RXSEL
PDMA SPI2 RX Selection (NuMicro( NUC100/NUC120 Medium Density Only)\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI2 RX. Software can configure the RX channel setting by SPI2_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
16
4
read-write
SPI2_TXSEL
PDMA SPI2 TX Selection (NuMicro( NUC100/NUC120 Medium Density Only)\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI2 TX. Software can configure the TX channel setting by SPI2_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
20
4
read-write
SPI3_RXSEL
PDMA SPI3 RX Selection (NuMicro( NUC100/NUC120 Medium Density Only)\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI3 RX. Software can configure the RX channel setting by SPI3_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
24
4
read-write
SPI3_TXSEL
PDMA SPI3 TX Selection (NuMicro( NUC100/NUC120 Medium Density Only)\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI3 TX. Software can configure the TX channel setting by SPI3_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
28
4
read-write
PDMA_PDSSR1
PDMA_PDSSR1
PDMA Service Selection Control Register 1
0x8
-1
read-write
n
0x0
0x0
ADC_RXSEL
PDMA ADC RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral ADC RX. Software can configure the RX channel setting by ADC_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL
24
4
read-write
UART0_RXSEL
This filed defines which PDMA channel is connected to the on-chip peripheral UART0 RX. Software can change the channel RX setting by UART0_RXSEL\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4 \n4'b0101: CH5\n4'b0110: CH6\n4'b0111: CH7\n4'b1000: CH8\nOthers : Reserved\n(The NuMicro( NUC100/NUC120 Low Density should be set as 4'b0000 for PDMA channel 0 only.)
0
4
read-write
UART0_TXSEL
PDMA UART0 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART0 TX. Software can configure the TX channel setting by UART0_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL
4
4
read-write
UART1_RXSEL
PDMA UART1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART1 RX. Software can configure the RX channel setting by UART1_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL
8
4
read-write
UART1_TXSEL
PDMA UART1 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART1 TX. Software can configure the TX channel setting by UART1_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL
12
4
read-write
PDMA_PDSSR2
PDMA_PDSSR2
PDMA Service Selection Control Register 2
0x10
-1
read-write
n
0x0
0x0
I2S_RXSEL
PDMA I2S RX Selection
This filed defines which PDMA channel is connected to the on-chip peripheral I2S RX. Software can change the channel RX setting by I2S_RXSEL.
4'b0000: CH0
4'b0001: CH1
4'b0010: CH2
4'b0011: CH3
4'b0100: CH4
4'b0101: CH5
4'b0110: CH6
4'b0111: CH7
4'b1000: CH8
Others : Reserved
0
4
read-write
I2S_TXSEL
PDMA I2S TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral I2S TX. Software can configure the TX channel setting by I2S_TXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL.
4
4
read-write
PS2
PS2 Register Map
PS2
0x0
0x0
0x20
registers
n
PS2CON
PS2CON
PS/2 Control Register
0x0
read-write
n
0x0
0x0
ACK
Acknowledge Enable\n
7
1
read-write
0
Always send acknowledge to host at 12th clock for host to device communication
#0
1
If parity error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock
#1
CLRFIFO
Clear TX FIFO\nWrite 1 to this bit to terminate device to host transmission. The TXEMPTY bit in PS2STATUS bit will be set to 1 and pointer BYTEIDEX is reset to 0 regardless there is residue data in buffer or not. The buffer content is not been cleared.\n
8
1
read-write
0
Not active
#0
1
Clear FIFO
#1
FPS2CLK
Force PS2CLK Line\nIt forces PS2CLK line high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n
10
1
read-write
0
Force PS2CLK line low
#0
1
Force PS2CLK line high
#1
FPS2DAT
Force PS2DATA Line\nIt forces PS2DATA high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n
11
1
read-write
0
Force PS2DATA low
#0
1
Force PS2DATA high
#1
OVERRIDE
Software Override PS/2 CLK/DATA Pin State\n
9
1
read-write
0
PS2CLK and PS2DATA pins are controlled by internal state machine
#0
1
PS2CLK and PS2DATA pins are controlled by S/W
#1
PS2EN
Enable PS/2 Device\nEnable PS/2 device controller\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
RXINTEN
Enable Receive Interrupt\n
2
1
read-write
0
Data receive complete interrupt Disabled
#0
1
Data receive complete interrupt Enabled
#1
TXFIFODIPTH
Transmit Data FIFO Depth\nThere is 16 bytes buffer for data transmit. S/W can define the FIFO depth from 1 to 16 bytes depends on application.\n
3
4
read-write
0
1 byte
0
1
2 bytes
1
14
15 bytes
14
15
16 bytes
15
TXINTEN
Enable Transmit Interrupt\n
1
1
read-write
0
Data transmit complete interrupt Disabled
#0
1
Data transmit complete interrupt Enabled
#1
PS2INTID
PS2INTID
PS/2 Interrupt Identification Register
0x1C
read-write
n
0x0
0x0
RXINT
Receive Interrupt\nThis bit is set to 1 when acknowledge bit is sent for Host to device communication. Interrupt occurs if RXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No interrupt
#0
1
Receive interrupt occurs
#1
TXINT
Transmit Interrupt\nThis bit is set to 1 after STOP bit is transmitted. Interrupt occur if TXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
No interrupt
#0
1
Transmit interrupt occurs
#1
PS2RXDATA
PS2RXDATA
PS/2 Receive Data Register
0x14
read-only
n
0x0
0x0
PS2RXDATA
Received Data
For host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2RXDATA register. CPU must read this register before next byte reception complete otherwise, the data will be overwritten and RXOVF bit in PS2STATUS[6] will be set to 1.
0
8
read-only
PS2STATUS
PS2STATUS
PS/2 Status Register
0x18
-1
read-write
n
0x0
0x0
BYTEIDX
Byte Index\n
8
4
read-write
FRAMERR
Frame Error
For host to device communication, if STOP bit (logic 1) is not received it is a frame error. If frame error occurs, DATA line may keep at low state after 12th clock. At this moment, S/W overrides PS2CLK to send clock till PS2DATA release to high state. After that, device sends a Resend command to host.
Write 1 to clear this bit.
2
1
read-write
0
No frame error
#0
1
Frame error occur
#1
PS2CLK
CLK Pin State\nThis bit reflects the status of the PS2CLK line after synchronizing.
0
1
read-write
PS2DATA
DATA Pin State\nThis bit reflects the status of the PS2DATA line after synchronizing and sampling.
1
1
read-write
RXBUSY
Receive Busy\nThis bit indicates that the PS/2 device is currently receiving data.\nRead only bit.
4
1
read-write
0
Idle
#0
1
Currently receiving data
#1
RXOVF
RX Buffer Overwrite\nWrite 1 to clear this bit.
6
1
read-write
0
No overwrite
#0
1
Data in PS2RXDATA register is overwritten by new received data
#1
RXPARITY
Received Parity\nThis bit reflects the parity bit for the last received data byte (odd parity).\nRead only bit.
3
1
read-write
TXBUSY
Transmit Busy\nThis bit indicates that the PS/2 device is currently sending data.\nRead only bit.
5
1
read-write
0
Idle
#0
1
Currently sending data
#1
TXEMPTY
TX FIFO Empty\nWhen S/W writes any data to PS2TXDATA0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled. When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1.\nRead only bit.
7
1
read-write
0
There is data to be transmitted
#0
1
FIFO is empty
#1
PS2TXDATA0
PS2TXDATA0
PS/2 Transmit Data Register 0
0x4
read-write
n
0x0
0x0
PS2TXDATAx
Transmit Data\nWriting data to this register starts device to host communication if bus is in IDLE state. Software must enable PS2EN before writing data to TX buffer.
0
32
read-write
PS2TXDATA1
PS2TXDATA1
PS/2 Transmit Data Register 1
0x8
read-write
n
0x0
0x0
PS2TXDATA2
PS2TXDATA2
PS/2 Transmit Data Register 2
0xC
read-write
n
0x0
0x0
PS2TXDATA3
PS2TXDATA3
PS/2 Transmit Data Register 3
0x10
read-write
n
0x0
0x0
PWMA
PWM Register Map
PWM
0x0
0x0
0x48
registers
n
0x50
0x30
registers
n
CAPENR
CAPENR
PWM Group A Capture Input 0~3 Enable Register\nPWM Group B Capture Input 0~3 Enable Register\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x78
read-write
n
0x0
0x0
CINEN0
Channel 0 Capture Input Enable\n
0
1
read-write
0
PWM Channel 0 capture input path Disabled. The input of PWM channel 0 capture function is always regarded as 0
#0
1
PWM Channel 0 capture input path Enabled. The input of PWM channel 0 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM0
#1
CINEN1
Channel 1 Capture Input Enable\n
1
1
read-write
0
PWM Channel 1 capture input path Disabled. The input of PWM channel 1 capture function is always regarded as 0
#0
1
PWM Channel 1 capture input path Enabled. The input of PWM channel 1 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM1
#1
CINEN2
Channel 2 Capture Input Enable\n
2
1
read-write
0
PWM Channel 2 capture input path Disabled. The input of PWM channel 2 capture function is always regarded as 0
#0
1
PWM Channel 2 capture input path Enabled. The input of PWM channel 2 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM2
#1
CINEN3
Channel 3 Capture Input Enable\n
3
1
read-write
0
PWM Channel 3 capture input path Disabled. The input of PWM channel 3 capture function is always regarded as 0
#0
1
PWM Channel 3 capture input path Enabled. The input of PWM channel 3 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM3
#1
CCR0
CCR0
PWM Group A Capture Control Register 0\nPWM Group B Capture Control Register 0\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x50
read-write
n
0x0
0x0
CAPCH0EN
Channel 0 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.
3
1
read-write
0
Capture function on PWM group channel 0 Disabled
#0
1
Capture function on PWM group channel 0 Enabled
#1
CAPCH1EN
Channel 1 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 1 Disabled
#0
1
Capture function on PWM group channel 1 Enabled
#1
CAPIF0
Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero
4
1
read-write
CAPIF1
Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero
20
1
read-write
CFLRI0
CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
7
1
read-write
CFLRI1
CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
23
1
read-write
CFL_IE0
Channel 0 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 0 has falling transition, Capture will issue an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE1
Channel 1 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 1 has falling transition, Capture will issue an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI0
CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
6
1
read-write
CRLRI1
CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
22
1
read-write
CRL_IE0
Channel 0 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 0 has rising transition, Capture will issue an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE1
Channel 1 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 1 has rising transition, Capture will issue an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV0
Channel 0 Inverter Enable\n
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV1
Channel 1 Inverter Enable\n
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CCR2
CCR2
PWM Group A Capture Control Register 2\nPWM Group B Capture Control Register 2\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x54
read-write
n
0x0
0x0
CAPCH2EN
Channel 2 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.
3
1
read-write
0
Capture function on PWM group channel 2 Disabled
#0
1
Capture function on PWM group channel 2 Enabled
#1
CAPCH3EN
Channel 3 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 3 Disabled
#0
1
Capture function on PWM group channel 3 Enabled
#1
CAPIF2
Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero
4
1
read-write
CAPIF3
Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
20
1
read-write
CFLRI2
CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
7
1
read-write
CFLRI3
CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
23
1
read-write
CFL_IE2
Channel 2 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 2 has falling transition, Capture will issue an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE3
Channel 3 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 3 has falling transition, Capture will issue an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI2
CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
6
1
read-write
CRLRI3
CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1.
22
1
read-write
CRL_IE2
Channel 2 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 2 has rising transition, Capture will issue an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE3
Channel 3 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 3 has rising transition, Capture will issue an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV2
Channel 2 Inverter Enable\n
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV3
Channel 3 Inverter Enable\n
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CFLR0
CFLR0
PWM Group A Capture Falling Latch Register (Channel 0)\nPWM Group B Capture Falling Latch Register (Channel 0) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x5C
read-only
n
0x0
0x0
CFLRx
Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition.
0
16
read-only
CFLR1
CFLR1
PWM Group A Capture Falling Latch Register (Channel 1)\nPWM Group B Capture Falling Latch Register (Channel 1) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x64
read-write
n
0x0
0x0
CFLR2
CFLR2
PWM Group A Capture Falling Latch Register (Channel 2)\nPWM Group B Capture Falling Latch Register (Channel 2) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x6C
read-write
n
0x0
0x0
CFLR3
CFLR3
PWM Group A Capture Falling Latch Register (Channel 3)\nPWM Group B Capture Falling Latch Register (Channel 3) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x74
read-write
n
0x0
0x0
CMR0
CMR0
PWM Group A Comparator Register 0\nPWM Group B Comparator Register 0\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x10
read-write
n
0x0
0x0
CMRx
PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CMR will take effect in next PWM cycle.
0
16
read-write
CMR1
CMR1
PWM Group A Comparator Register 1\nPWM Group B Comparator Register 1\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x1C
read-write
n
0x0
0x0
CMR2
CMR2
PWM Group A Comparator Register 2\nPWM Group B Comparator Register 2\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x28
read-write
n
0x0
0x0
CMR3
CMR3
PWM Group A Comparator Register 3\nPWM Group B Comparator Register 3\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x34
read-write
n
0x0
0x0
CNR0
CNR0
PWM Group A Counter Register 0\nPWM Group B Counter Register 0\n(NuMicro( NUC100/NUC120 Medium Density Only)
0xC
read-write
n
0x0
0x0
CNRx
PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CNR1
CNR1
PWM Group A Counter Register 1\nPWM Group B Counter Register 1\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x18
read-write
n
0x0
0x0
CNR2
CNR2
PWM Group A Counter Register 2\nPWM Group B Counter Register 2\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x24
read-write
n
0x0
0x0
CNR3
CNR3
PWM Group A Counter Register 3\nPWM Group B Counter Register 3\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x30
read-write
n
0x0
0x0
CRLR0
CRLR0
PWM Group A Capture Rising Latch Register (Channel 0)\nPWM Group B Capture Rising Latch Register (Channel 0) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x58
read-only
n
0x0
0x0
CRLRx
Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CRLR1
CRLR1
PWM Group A Capture Rising Latch Register (Channel 1)\nPWM Group B Capture Rising Latch Register (Channel 1) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x60
read-write
n
0x0
0x0
CRLR2
CRLR2
PWM Group A Capture Rising Latch Register (Channel 2)\nPWM Group B Capture Rising Latch Register (Channel 2) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x68
read-write
n
0x0
0x0
CRLR3
CRLR3
PWM Group A Capture Rising Latch Register (Channel 3)\nPWM Group B Capture Rising Latch Register (Channel 3) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x70
read-write
n
0x0
0x0
CSR
CSR
PWM Group A Clock Source Divider Select Register\nPWM Group B Clock Source Divider Select Register\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x4
read-write
n
0x0
0x0
CSR0
PWM Timer 0 Clock Source Divider Selection (PWM timer 0 for group A and PWM timer 4 for group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3.)
0
3
read-write
CSR1
PWM Timer 1 Clock Source Divider Selection (PWM timer 1 for group A and PWM timer 5 for group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3.)
4
3
read-write
CSR2
PWM Timer 2 Clock Source Divider Selection (PWM timer 2 for group A and PWM timer 6 for group B)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3.)
8
3
read-write
CSR3
PWM Timer 3 Clock Source Divider Selection (PWM timer 3 for group A and PWM timer 7 for group B)\n
12
3
read-write
PBCR
PBCR
PWM Backward Compatible Register\n(NuMicro( NUC100/NUC120 Low Density Only)
0x3C
read-write
n
0x0
0x0
BCn
PWM Backward Compatible Register\nRefer to the CCR0/CCR2 register bit 6, 7, 22, 23 descriptions.
0
1
read-write
0
Configure write 0 to clear CFLRI0~3 and CRLRI0~3
#0
1
Configure write 1 to clear CFLRI0~3 and CRLRI0~3
#1
PCR
PCR
PWM Group A Control Register\nPWM Group B Control Register\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x8
read-write
n
0x0
0x0
CH0EN
PWM-Timer 0 Enable (PWM timer 0 for group A and PWM timer 4 for group B)\n
0
1
read-write
0
Corresponding PWM-Timer Running Stopped
#0
1
Corresponding PWM-Timer Start Run Enabled
#1
CH0INV
PWM-Timer 0 Output Inverter Enable (PWM timer 0 for group A and PWM timer 4 for group B)\n
2
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH0MOD
PWM-Timer 0 Auto-reload/One-Shot Mode (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared.
3
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH1EN
PWM-Timer 1 Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n
8
1
read-write
0
Corresponding PWM-Timer Running Stopped
#0
1
Corresponding PWM-Timer Start Run Enabled
#1
CH1INV
PWM-Timer 1 Output Inverter Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n
10
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH1MOD
PWM-Timer 1 Auto-reload/One-Shot Mode (PWM timer 1 for Group A and PWM timer 5 for Group B)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared.
11
1
read-write
0
One-shot mode
#0
1
Auto-load mode
#1
CH2EN
PWM-Timer 2 Enable (PWM timer 2 for group A and PWM timer 6 for Group B)\n
16
1
read-write
0
corresponding PWM-Timer Running Stopped
#0
1
corresponding PWM-Timer Start Run Enabled
#1
CH2INV
PWM-Timer 2 Output Inverter Enable (PWM timer 2 for group A and PWM timer 6 for group B)\n
18
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH2MOD
PWM-Timer 2 Auto-reload/One-Shot Mode (PWM timer 2 for group A and PWM timer 6 for group B)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be cleared.
19
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH3EN
PWM-Timer 3 Enable (PWM timer 3 for group A and PWM timer 7 for group B)\n
24
1
read-write
0
Corresponding PWM-Timer Running Stopped
#0
1
Corresponding PWM-Timer Start Run Enabled
#1
CH3INV
PWM-Timer 3 Output Inverter Enable (PWM timer 3 for group A and PWM timer 7 for group B)\n
26
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH3MOD
PWM-Timer 3 Auto-reload/One-Shot Mode (PWM timer 3 for group A and PWM timer 7 for group B)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be cleared.
27
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
DZEN01
Dead-Zone 0 Generator Enable (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B)\nNote: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B.
4
1
read-write
0
Disabled
#0
1
Enabled
#1
DZEN23
Dead-Zone 2 Generator Enable (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B)\nNote: When the Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B.
5
1
read-write
0
Disabled
#0
1
Enabled
#1
PDR0
PDR0
PWM Group A Data Register 0\nPWM Group B Data Register 0\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x14
read-only
n
0x0
0x0
PDRx
PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter.
0
16
read-only
PDR1
PDR1
PWM Group A Data Register 1\nPWM Group B Data Register 1\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x20
read-write
n
0x0
0x0
PDR2
PDR2
PWM Group A Data Register 2\nPWM Group B Data Register 2\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x2C
read-write
n
0x0
0x0
PDR3
PDR3
PWM Group A Data Register 3\nPWM Group B Data Register 3\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x38
read-write
n
0x0
0x0
PIER
PIER
PWM Group A Interrupt Enable Register\nPWM Group B Interrupt Enable Register\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x40
read-write
n
0x0
0x0
PWMIE0
PWM channel 0 Interrupt Enable\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE1
PWM channel 1 Interrupt Enable\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE2
PWM channel 2 Interrupt Enable\n
2
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE3
PWM channel 3 Interrupt Enable\n
3
1
read-write
0
Disabled
#0
1
Enabled
#1
PIIR
PIIR
PWM Group A Interrupt Indication Register\nPWM Group B Interrupt Indication Register\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x44
read-write
n
0x0
0x0
PWMIF0
PWM channel 0 Interrupt Status\nThis bit is set by hardware when PWM0 down counter reaches zero if PWM3 interrupt enable bit (PWMIE0) is 1, software can write 1 to clear this bit to zero
0
1
read-write
PWMIF1
PWM channel 1 Interrupt Status\nThis bit is set by hardware when PWM1 down counter reaches zero if PWM3 interrupt enable bit (PWMIE1) is 1, software can write 1 to clear this bit to zero
1
1
read-write
PWMIF2
PWM channel 2 Interrupt Status\nThis bit is set by hardware when PWM2 down counter reaches zero if PWM3 interrupt enable bit (PWMIE2) is 1, software can write 1 to clear this bit to zero
2
1
read-write
PWMIF3
PWM channel 3 Interrupt Status\nThis bit is set by hardware when PWM3 down counter reaches zero if PWM3 interrupt enable bit (PWMIE3) is 1, software can write 1 to clear this bit to zero
3
1
read-write
POE
POE
PWM Group A Output Enable for Channel 0~3\nPWM Group B Output Enable for Channel 0~3\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x7C
read-write
n
0x0
0x0
POE0
Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.
0
1
read-write
0
PWM channel 0 output to pin Disabled
#0
1
PWM channel 0 output to pin Enabled
#1
POE1
Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.
1
1
read-write
0
PWM channel 1 output to pin Disabled
#0
1
PWM channel 1 output to pin Enabled
#1
POE2
Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.
2
1
read-write
0
PWM channel 2 output to pin Disabled
#0
1
PWM channel 2 output to pin Enabled
#1
POE3
Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.
3
1
read-write
0
PWM channel 3 output to pin Disabled
#0
1
PWM channel 3 output to pin Enabled
#1
PPR
PPR
PWM Group A Prescaler Register\nPWM Group B Prescaler Register\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x0
read-write
n
0x0
0x0
CP01
Clock Prescaler 0 (PWM-timer 0 / 1 for group A and PWM-timer 4 / 5 for Group B)
Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer
0
8
read-write
CP23
Clock Prescaler 2 (PWM-timer2 /3 for group A and PWM-timer 6 / 7 for Group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer\n
8
8
read-write
DZI01
Dead-zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 Pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nThese 8-bit determine the dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
16
8
read-write
DZI23
Dead-zone Interval for Pair of Channel2 and Channel3 (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nThese 8-bit determine the dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
24
8
read-write
PWMB
PWM Register Map
PWM
0x0
0x0
0x3C
registers
n
0x40
0x8
registers
n
0x50
0x30
registers
n
CAPENR
CAPENR
PWM Group A Capture Input 0~3 Enable Register\nPWM Group B Capture Input 0~3 Enable Register\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x78
read-write
n
0x0
0x0
CINEN0
Channel 0 Capture Input Enable\n
0
1
read-write
0
PWM Channel 0 capture input path Disabled. The input of PWM channel 0 capture function is always regarded as 0
#0
1
PWM Channel 0 capture input path Enabled. The input of PWM channel 0 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM0
#1
CINEN1
Channel 1 Capture Input Enable\n
1
1
read-write
0
PWM Channel 1 capture input path Disabled. The input of PWM channel 1 capture function is always regarded as 0
#0
1
PWM Channel 1 capture input path Enabled. The input of PWM channel 1 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM1
#1
CINEN2
Channel 2 Capture Input Enable\n
2
1
read-write
0
PWM Channel 2 capture input path Disabled. The input of PWM channel 2 capture function is always regarded as 0
#0
1
PWM Channel 2 capture input path Enabled. The input of PWM channel 2 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM2
#1
CINEN3
Channel 3 Capture Input Enable\n
3
1
read-write
0
PWM Channel 3 capture input path Disabled. The input of PWM channel 3 capture function is always regarded as 0
#0
1
PWM Channel 3 capture input path Enabled. The input of PWM channel 3 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM3
#1
CCR0
CCR0
PWM Group A Capture Control Register 0\nPWM Group B Capture Control Register 0\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x50
read-write
n
0x0
0x0
CAPCH0EN
Channel 0 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.
3
1
read-write
0
Capture function on PWM group channel 0 Disabled
#0
1
Capture function on PWM group channel 0 Enabled
#1
CAPCH1EN
Channel 1 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 1 Disabled
#0
1
Capture function on PWM group channel 1 Enabled
#1
CAPIF0
Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero
4
1
read-write
CAPIF1
Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero
20
1
read-write
CFLRI0
CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
7
1
read-write
CFLRI1
CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
23
1
read-write
CFL_IE0
Channel 0 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 0 has falling transition, Capture will issue an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE1
Channel 1 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 1 has falling transition, Capture will issue an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI0
CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
6
1
read-write
CRLRI1
CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
22
1
read-write
CRL_IE0
Channel 0 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 0 has rising transition, Capture will issue an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE1
Channel 1 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 1 has rising transition, Capture will issue an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV0
Channel 0 Inverter Enable\n
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV1
Channel 1 Inverter Enable\n
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CCR2
CCR2
PWM Group A Capture Control Register 2\nPWM Group B Capture Control Register 2\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x54
read-write
n
0x0
0x0
CAPCH2EN
Channel 2 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.
3
1
read-write
0
Capture function on PWM group channel 2 Disabled
#0
1
Capture function on PWM group channel 2 Enabled
#1
CAPCH3EN
Channel 3 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 3 Disabled
#0
1
Capture function on PWM group channel 3 Enabled
#1
CAPIF2
Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero
4
1
read-write
CAPIF3
Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
20
1
read-write
CFLRI2
CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
7
1
read-write
CFLRI3
CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
23
1
read-write
CFL_IE2
Channel 2 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 2 has falling transition, Capture will issue an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE3
Channel 3 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 3 has falling transition, Capture will issue an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI2
CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
6
1
read-write
CRLRI3
CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nIn NuMicro( NUC100/NUC120 Medium Density, software can write 0 to clear this bit to zero.\nIn NuMicro( NUC100/NUC120 Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1.
22
1
read-write
CRL_IE2
Channel 2 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 2 has rising transition, Capture will issue an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE3
Channel 3 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 3 has rising transition, Capture will issue an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV2
Channel 2 Inverter Enable\n
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV3
Channel 3 Inverter Enable\n
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CFLR0
CFLR0
PWM Group A Capture Falling Latch Register (Channel 0)\nPWM Group B Capture Falling Latch Register (Channel 0) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x5C
read-only
n
0x0
0x0
CFLRx
Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition.
0
16
read-only
CFLR1
CFLR1
PWM Group A Capture Falling Latch Register (Channel 1)\nPWM Group B Capture Falling Latch Register (Channel 1) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x64
read-write
n
0x0
0x0
CFLR2
CFLR2
PWM Group A Capture Falling Latch Register (Channel 2)\nPWM Group B Capture Falling Latch Register (Channel 2) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x6C
read-write
n
0x0
0x0
CFLR3
CFLR3
PWM Group A Capture Falling Latch Register (Channel 3)\nPWM Group B Capture Falling Latch Register (Channel 3) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x74
read-write
n
0x0
0x0
CMR0
CMR0
PWM Group A Comparator Register 0\nPWM Group B Comparator Register 0\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x10
read-write
n
0x0
0x0
CMRx
PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CMR will take effect in next PWM cycle.
0
16
read-write
CMR1
CMR1
PWM Group A Comparator Register 1\nPWM Group B Comparator Register 1\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x1C
read-write
n
0x0
0x0
CMR2
CMR2
PWM Group A Comparator Register 2\nPWM Group B Comparator Register 2\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x28
read-write
n
0x0
0x0
CMR3
CMR3
PWM Group A Comparator Register 3\nPWM Group B Comparator Register 3\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x34
read-write
n
0x0
0x0
CNR0
CNR0
PWM Group A Counter Register 0\nPWM Group B Counter Register 0\n(NuMicro( NUC100/NUC120 Medium Density Only)
0xC
read-write
n
0x0
0x0
CNRx
PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CNR1
CNR1
PWM Group A Counter Register 1\nPWM Group B Counter Register 1\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x18
read-write
n
0x0
0x0
CNR2
CNR2
PWM Group A Counter Register 2\nPWM Group B Counter Register 2\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x24
read-write
n
0x0
0x0
CNR3
CNR3
PWM Group A Counter Register 3\nPWM Group B Counter Register 3\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x30
read-write
n
0x0
0x0
CRLR0
CRLR0
PWM Group A Capture Rising Latch Register (Channel 0)\nPWM Group B Capture Rising Latch Register (Channel 0) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x58
read-only
n
0x0
0x0
CRLRx
Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CRLR1
CRLR1
PWM Group A Capture Rising Latch Register (Channel 1)\nPWM Group B Capture Rising Latch Register (Channel 1) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x60
read-write
n
0x0
0x0
CRLR2
CRLR2
PWM Group A Capture Rising Latch Register (Channel 2)\nPWM Group B Capture Rising Latch Register (Channel 2) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x68
read-write
n
0x0
0x0
CRLR3
CRLR3
PWM Group A Capture Rising Latch Register (Channel 3)\nPWM Group B Capture Rising Latch Register (Channel 3) \n(NuMicro( NUC100/NUC120 Medium Density Only)
0x70
read-write
n
0x0
0x0
CSR
CSR
PWM Group A Clock Source Divider Select Register\nPWM Group B Clock Source Divider Select Register\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x4
read-write
n
0x0
0x0
CSR0
PWM Timer 0 Clock Source Divider Selection (PWM timer 0 for group A and PWM timer 4 for group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3.)
0
3
read-write
CSR1
PWM Timer 1 Clock Source Divider Selection (PWM timer 1 for group A and PWM timer 5 for group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3.)
4
3
read-write
CSR2
PWM Timer 2 Clock Source Divider Selection (PWM timer 2 for group A and PWM timer 6 for group B)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3.)
8
3
read-write
CSR3
PWM Timer 3 Clock Source Divider Selection (PWM timer 3 for group A and PWM timer 7 for group B)\n
12
3
read-write
PCR
PCR
PWM Group A Control Register\nPWM Group B Control Register\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x8
read-write
n
0x0
0x0
CH0EN
PWM-Timer 0 Enable (PWM timer 0 for group A and PWM timer 4 for group B)\n
0
1
read-write
0
Corresponding PWM-Timer Running Stopped
#0
1
Corresponding PWM-Timer Start Run Enabled
#1
CH0INV
PWM-Timer 0 Output Inverter Enable (PWM timer 0 for group A and PWM timer 4 for group B)\n
2
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH0MOD
PWM-Timer 0 Auto-reload/One-Shot Mode (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared.
3
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH1EN
PWM-Timer 1 Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n
8
1
read-write
0
Corresponding PWM-Timer Running Stopped
#0
1
Corresponding PWM-Timer Start Run Enabled
#1
CH1INV
PWM-Timer 1 Output Inverter Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n
10
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH1MOD
PWM-Timer 1 Auto-reload/One-Shot Mode (PWM timer 1 for Group A and PWM timer 5 for Group B)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared.
11
1
read-write
0
One-shot mode
#0
1
Auto-load mode
#1
CH2EN
PWM-Timer 2 Enable (PWM timer 2 for group A and PWM timer 6 for Group B)\n
16
1
read-write
0
corresponding PWM-Timer Running Stopped
#0
1
corresponding PWM-Timer Start Run Enabled
#1
CH2INV
PWM-Timer 2 Output Inverter Enable (PWM timer 2 for group A and PWM timer 6 for group B)\n
18
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH2MOD
PWM-Timer 2 Auto-reload/One-Shot Mode (PWM timer 2 for group A and PWM timer 6 for group B)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be cleared.
19
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH3EN
PWM-Timer 3 Enable (PWM timer 3 for group A and PWM timer 7 for group B)\n
24
1
read-write
0
Corresponding PWM-Timer Running Stopped
#0
1
Corresponding PWM-Timer Start Run Enabled
#1
CH3INV
PWM-Timer 3 Output Inverter Enable (PWM timer 3 for group A and PWM timer 7 for group B)\n
26
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH3MOD
PWM-Timer 3 Auto-reload/One-Shot Mode (PWM timer 3 for group A and PWM timer 7 for group B)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be cleared.
27
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
DZEN01
Dead-Zone 0 Generator Enable (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B)\nNote: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B.
4
1
read-write
0
Disabled
#0
1
Enabled
#1
DZEN23
Dead-Zone 2 Generator Enable (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B)\nNote: When the Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B.
5
1
read-write
0
Disabled
#0
1
Enabled
#1
PDR0
PDR0
PWM Group A Data Register 0\nPWM Group B Data Register 0\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x14
read-only
n
0x0
0x0
PDRx
PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter.
0
16
read-only
PDR1
PDR1
PWM Group A Data Register 1\nPWM Group B Data Register 1\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x20
read-write
n
0x0
0x0
PDR2
PDR2
PWM Group A Data Register 2\nPWM Group B Data Register 2\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x2C
read-write
n
0x0
0x0
PDR3
PDR3
PWM Group A Data Register 3\nPWM Group B Data Register 3\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x38
read-write
n
0x0
0x0
PIER
PIER
PWM Group A Interrupt Enable Register\nPWM Group B Interrupt Enable Register\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x40
read-write
n
0x0
0x0
PWMIE0
PWM channel 0 Interrupt Enable\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE1
PWM channel 1 Interrupt Enable\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE2
PWM channel 2 Interrupt Enable\n
2
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE3
PWM channel 3 Interrupt Enable\n
3
1
read-write
0
Disabled
#0
1
Enabled
#1
PIIR
PIIR
PWM Group A Interrupt Indication Register\nPWM Group B Interrupt Indication Register\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x44
read-write
n
0x0
0x0
PWMIF0
PWM channel 0 Interrupt Status\nThis bit is set by hardware when PWM0 down counter reaches zero if PWM3 interrupt enable bit (PWMIE0) is 1, software can write 1 to clear this bit to zero
0
1
read-write
PWMIF1
PWM channel 1 Interrupt Status\nThis bit is set by hardware when PWM1 down counter reaches zero if PWM3 interrupt enable bit (PWMIE1) is 1, software can write 1 to clear this bit to zero
1
1
read-write
PWMIF2
PWM channel 2 Interrupt Status\nThis bit is set by hardware when PWM2 down counter reaches zero if PWM3 interrupt enable bit (PWMIE2) is 1, software can write 1 to clear this bit to zero
2
1
read-write
PWMIF3
PWM channel 3 Interrupt Status\nThis bit is set by hardware when PWM3 down counter reaches zero if PWM3 interrupt enable bit (PWMIE3) is 1, software can write 1 to clear this bit to zero
3
1
read-write
POE
POE
PWM Group A Output Enable for Channel 0~3\nPWM Group B Output Enable for Channel 0~3\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x7C
read-write
n
0x0
0x0
POE0
Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.
0
1
read-write
0
PWM channel 0 output to pin Disabled
#0
1
PWM channel 0 output to pin Enabled
#1
POE1
Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.
1
1
read-write
0
PWM channel 1 output to pin Disabled
#0
1
PWM channel 1 output to pin Enabled
#1
POE2
Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.
2
1
read-write
0
PWM channel 2 output to pin Disabled
#0
1
PWM channel 2 output to pin Enabled
#1
POE3
Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.
3
1
read-write
0
PWM channel 3 output to pin Disabled
#0
1
PWM channel 3 output to pin Enabled
#1
PPR
PPR
PWM Group A Prescaler Register\nPWM Group B Prescaler Register\n(NuMicro( NUC100/NUC120 Medium Density Only)
0x0
read-write
n
0x0
0x0
CP01
Clock Prescaler 0 (PWM-timer 0 / 1 for group A and PWM-timer 4 / 5 for Group B)
Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer
0
8
read-write
CP23
Clock Prescaler 2 (PWM-timer2 /3 for group A and PWM-timer 6 / 7 for Group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer\n
8
8
read-write
DZI01
Dead-zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 Pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nThese 8-bit determine the dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
16
8
read-write
DZI23
Dead-zone Interval for Pair of Channel2 and Channel3 (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nThese 8-bit determine the dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
24
8
read-write
RTC
RTC Register Map
RTC
0x0
0x0
0x30
registers
n
AER
AER
RTC Access Enable Register
0x4
read-write
n
0x0
0x0
AER
RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this register will enable RTC access and keep 1024 RTC clock
0
16
write-only
ENF
RTC Register Access Enable Flag (Read only)\n
16
1
read-only
0
RTC register read/write Disabled
#0
1
RTC register read/write Enabled
#1
CAR
CAR
Calendar Alarm Register
0x20
read-write
n
0x0
0x0
_10DAY
10-Day Calendar Digit of Alarm Setting (0~3)
4
2
read-write
_10MON
10-Month Calendar Digit of Alarm Setting (0~1)
12
1
read-write
_10YEAR
10-Year Calendar Digit of Alarm Setting (0~9)
20
4
read-write
_1DAY
1-Day Calendar Digit of Alarm Setting (0~9)
0
4
read-write
_1MON
1-Month Calendar Digit of Alarm Setting (0~9)
8
4
read-write
_1YEAR
1-Year Calendar Digit of Alarm Setting (0~9)
16
4
read-write
CLR
CLR
Calendar Loading Register
0x10
-1
read-write
n
0x0
0x0
_10DAY
10-Day Calendar Digit (0~3)
4
2
read-write
_10MON
10-Month Calendar Digit (0~1)
12
1
read-write
_10YEAR
10-Year Calendar Digit (0~9)
20
4
read-write
_1DAY
1-Day Calendar Digit (0~9)
0
4
read-write
_1MON
1-Month Calendar Digit (0~9)
8
4
read-write
_1YEAR
1-Year Calendar Digit (0~9)
16
4
read-write
DWR
DWR
Day of the Week Register
0x18
-1
read-write
n
0x0
0x0
DWR
Day of the Week Register \n
0
3
read-write
FCR
FCR
RTC Frequency Compensation Register
0x8
-1
read-write
n
0x0
0x0
FRACTION
Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number. Refer to 5.8.4.4 for the examples.
0
6
read-write
INTEGER
Integer Part\n
8
4
read-write
INIR
INIR
RTC Initiation Register
0x0
read-write
n
0x0
0x0
INIR
RTC Initiation (Write only)
When RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIR to make RTC leaving reset state. Once the INIR is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
The INIR is a write-only field and read value will be always 0 .
RTC Active Status (Read only)
0
32
write-only
0
RTC is at reset state
0
1
RTC is at normal active state
1
LIR
LIR
Leap Year Indicator Register
0x24
read-only
n
0x0
0x0
LIR
Leap Year Indication Register (Read Only)\n
0
1
read-only
0
This year is not a leap year
#0
1
This year is leap year
#1
RIER
RIER
RTC Interrupt Enable Register
0x28
read-write
n
0x0
0x0
AIER
Alarm Interrupt Enable\n
0
1
read-write
0
RTC Alarm Interrupt Disabled
#0
1
RTC Alarm Interrupt Enabled
#1
TIER
Time Tick Interrupt Enable\n
1
1
read-write
0
RTC Time Tick Interrupt Disabled
#0
1
RTC Time Tick Interrupt Enabled
#1
RIIR
RIIR
RTC Interrupt Indicator Register
0x2C
read-write
n
0x0
0x0
AIF
RTC Alarm Interrupt Flag\n
0
1
read-write
0
RCT Alarm Interrupt condition never occurred
#0
1
RTC Alarm Interrupt is requested if RIER.AIER = 1
#1
TIF
RTC Time Tick Interrupt Flag\n
1
1
read-write
0
RCT Time Tick Interrupt condition never occurred
#0
1
RTC Time Tick Interrupt is requested if RIER.TIER = 1
#1
TAR
TAR
Time Alarm Register
0x1C
read-write
n
0x0
0x0
_10HR
10-Hour Time Digit of Alarm Setting (0~2)
20
2
read-write
_10MIN
10-Min Time Digit of Alarm Setting (0~5)
12
3
read-write
_10SEC
10-Sec Time Digit of Alarm Setting (0~5)
4
3
read-write
_1HR
1-Hour Time Digit of Alarm Setting (0~9)
16
4
read-write
_1MIN
1-Min Time Digit of Alarm Setting (0~9)
8
4
read-write
_1SEC
1-Sec Time Digit of Alarm Setting (0~9)
0
4
read-write
TLR
TLR
Time Loading Register
0xC
read-write
n
0x0
0x0
_10HR
10-Hour Time Digit (0~2)
20
2
read-write
_10MIN
10-Min Time Digit (0~5)
12
3
read-write
_10SEC
10-Sec Time Digit (0~5)
4
3
read-write
_1HR
1-Hour Time Digit (0~9)
16
4
read-write
_1MIN
1-Min Time Digit (0~9)
8
4
read-write
_1SEC
1-Sec Time Digit (0~9)
0
4
read-write
TSSR
TSSR
Time Scale Selection Register
0x14
-1
read-write
n
0x0
0x0
_24H_12H
24-Hour / 12-Hour Time Scale Selection\n
0
1
read-write
0
Selected as 12-hour time scale with AM and PM indication
#0
1
Selected as 24-hour time scale
#1
TTR
TTR
RTC Time Tick Register
0x30
read-write
n
0x0
0x0
TTR
Time Tick Register\n
0
3
read-write
TWKE
RTC Timer Wake-up Function Enable\nIf TWKE is set before chip is in Power-down mode, chip will be woken up by RTC controller when a RTC Time Tick occurs.\nNote1: Tick timer setting follows the TTR[2:0] description.\nNote2: When Alarm Match occurs, chip will be woken up from Power-down mode no matter TWKE is 1 or 0.
3
1
read-write
0
RTC Timer wake-up Disabled by Timer Tick occur function
#0
1
RTC Timer wake-up function Enabled so that chip can be woken up from Power-down mode by Time Tick
#1
SCS
SCS Register Map
SCS
0x0
0x10
0xC
registers
n
0x100
0x4
registers
n
0x180
0x4
registers
n
0x200
0x4
registers
n
0x280
0x4
registers
n
0x400
0x20
registers
n
0xD00
0x8
registers
n
0xD0C
0x8
registers
n
0xD1C
0x8
registers
n
AIRCR
AIRCR
Application Interrupt and Reset Control Register
0xD0C
-1
read-write
n
0x0
0x0
SYSRESETREQ
Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence.
2
1
read-write
VECTCLRACTIVE
Setting this bit to 1 will clear all active state information for fixed and configurable exceptions.\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack.
1
1
read-write
VECTORKEY
When writing this register, this field should be 0x05FA, otherwise the write action will be unpredictable.
16
16
read-write
CPUID
CPUID
CPUID Register
0xD00
-1
read-only
n
0x0
0x0
IMPLEMENTER
None
24
8
read-only
PART
Read as 0xC for ARMv6-M parts
16
4
read-only
PARTNO
Read as 0xC20.
4
12
read-only
REVISION
Read as 0x0
0
4
read-only
ICSR
ICSR
Interrupt Control and State Register
0xD04
read-write
n
0x0
0x0
ISRPENDING
Interrupt pending flag, excluding NMI and Faults:\nThis is a read only bit.
22
1
read-write
0
Interrupt not pending
#0
1
Interrupt pending
#1
ISRPREEMPT
If set, a pending exception will be serviced on exit from the debug halt state.\nThis is a read only bit.
23
1
read-write
NMIPENDSET
NMI set-pending bit\nWrite:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
31
1
read-write
0
No effect\nNMI exception not pending
#0
1
changes NMI exception state to pending.\nNMI exception pending
#1
PENDSTCLR
SysTick Exception Clear-pending Bit
Write:
This is a write only bit. When you want to clear PENDST bit, you must write 0 to PENDSTSET and write 1 to PENDSTCLR at the same time.
25
1
read-write
0
No effect
#0
1
Removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick Exception Set-pending Bit\nWrite:\n
26
1
read-write
0
No effect\nSysTick exception is not pending
#0
1
Changes SysTick exception state to pending.\nSysTick exception is pending
#1
PENDSVCLR
PendSV clear-pending bit.
Write:
This is a write only bit. When you want to clear PENDSV bit, you must write 0 to PENDSVSET and write 1 to PENDSVCLR at the same time.
27
1
read-write
0
No effect
#0
1
Removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV set-pending bit.\nWrite:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
No effect\nPendSV exception is not pending
#0
1
Changes PendSV exception state to pending.\nPendSV exception is pending
#1
VECTACTIVE
Contains the active exception number\n
0
6
read-write
0
Thread mode
0
VECTPENDING
Indicates the exception number of the highest priority pending enabled exception:\n
12
6
read-write
0
No pending exceptions
0
NVIC_ICER
NVIC_ICER
IRQ0 ~ IRQ31 Clear-enable Control Register
0x180
read-write
n
0x0
0x0
CLRENA
Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nThe register reads back with the current enable state.
0
32
read-write
0
No effect
0
1
Associated interrupt Disabled
1
NVIC_ICPR
NVIC_ICPR
IRQ0 ~ IRQ31 Clear-pending Control Register
0x280
read-write
n
0x0
0x0
CLRPEND
The register reads back with the current pending state.
0
32
read-write
0
No effect
0
1
Remove the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)
1
NVIC_IPR0
NVIC_IPR0
IRQ0 ~ IRQ3 Interrupt Priority Control Register
0x400
read-write
n
0x0
0x0
PRI_0
Priority of IRQ0
0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_1
Priority of IRQ1
0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_2
Priority of IRQ2
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_3
Priority of IRQ3
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR1
NVIC_IPR1
IRQ4 ~ IRQ7 Interrupt Priority Control Register
0x404
read-write
n
0x0
0x0
PRI_4
Priority of IRQ4
0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_5
Priority of IRQ5
0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_6
Priority of IRQ6
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_7
Priority of IRQ7
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR2
NVIC_IPR2
IRQ8 ~ IRQ11 Interrupt Priority Control Register
0x408
read-write
n
0x0
0x0
PRI_10
Priority of IRQ10
0 denotes the highest priority and 3 denotes the lowest priority
22
2
read-write
PRI_11
Priority of IRQ11
0 denotes the highest priority and 3 denotes the lowest priority
30
2
read-write
PRI_8
Priority of IRQ8
0 denotes the highest priority and 3 denotes the lowest priority
6
2
read-write
PRI_9
Priority of IRQ9
0 denotes the highest priority and 3 denotes the lowest priority
14
2
read-write
NVIC_IPR3
NVIC_IPR3
IRQ12 ~ IRQ15 Interrupt Priority Control Register
0x40C
read-write
n
0x0
0x0
PRI_12
Priority of IRQ12
0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_13
Priority of IRQ13
0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_14
Priority of IRQ14
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_15
Priority of IRQ15
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR4
NVIC_IPR4
IRQ16 ~ IRQ19 Interrupt Priority Control Register
0x410
read-write
n
0x0
0x0
PRI_16
Priority of IRQ16
0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_17
Priority of IRQ17
0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_18
Priority of IRQ18
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_19
Priority of IRQ19
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR5
NVIC_IPR5
IRQ20 ~ IRQ23 Interrupt Priority Control Register
0x414
read-write
n
0x0
0x0
PRI_20
Priority of IRQ20
0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_21
Priority of IRQ21
0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_22
Priority of IRQ22
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_23
Priority of IRQ23
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR6
NVIC_IPR6
IRQ24 ~ IRQ27 Interrupt Priority Control Register
0x418
read-write
n
0x0
0x0
PRI_24
Priority of IRQ24
0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_25
Priority of IRQ25
0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_26
Priority of IRQ26
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_27
Priority of IRQ27
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR7
NVIC_IPR7
IRQ28 ~ IRQ31 Interrupt Priority Control Register
0x41C
read-write
n
0x0
0x0
PRI_28
Priority of IRQ28
0 denotes the highest priority and 3 denotes the lowest priority
6
2
read-write
PRI_29
Priority of IRQ29
0 denotes the highest priority and 3 denotes the lowest priority
14
2
read-write
PRI_30
Priority of IRQ30
0 denotes the highest priority and 3 denotes the lowest priority
22
2
read-write
PRI_31
Priority of IRQ31
0 denotes the highest priority and 3 denotes the lowest priority
30
2
read-write
NVIC_ISER
NVIC_ISER
IRQ0 ~ IRQ31 Set-enable Control Register
0x100
read-write
n
0x0
0x0
SETENA
Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nThe register reads back with the current enable state.
0
32
read-write
0
No effect
0
1
Associated interrupt Enabled
1
NVIC_ISPR
NVIC_ISPR
IRQ0 ~ IRQ31 Set-pending Control Register
0x200
read-write
n
0x0
0x0
SETPEND
The register reads back with the current pending state.
0
32
read-write
0
No effect
0
1
Set pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)
1
SCR
SCR
System Control Register
0xD10
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending bit:\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Only enabled interrupts or events can wake up the processor, disabled interrupts are excluded
#0
1
Enabled events and all interrupts, including disabled interrupts, can wake up the processor
#1
SLEEPDEEP
Controls whether the processor uses sleep or deep sleep as its low power mode:\n
2
1
read-write
0
Sleep
#0
1
Deep sleep
#1
SLEEPONEXIT
Indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
0
Do not sleep when returning to Thread mode
#0
1
Enter sleep, or deep sleep, on return from an ISR to Thread mode
#1
SHPR2
SHPR2
System Handler Priority Register 2
0xD1C
read-write
n
0x0
0x0
PRI_11
Priority of system handler 11 - SVCall
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
SHPR3
SHPR3
System Handler Priority Register 3
0xD20
read-write
n
0x0
0x0
PRI_14
Priority of system handler 14 - PendSV
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_15
Priority of system handler 15 - SysTick
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
SYST_CSR
SYST_CSR
SysTick Control and Status Register
0x10
read-write
n
0x0
0x0
CLKSRC
None
2
1
read-write
0
Clock source is (optional) external reference clock
#0
1
Core clock used for SysTick
#1
COUNTFLAG
Returns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-write
ENABLE
None
0
1
read-write
0
Counter Disabled
#0
1
Counter will operate in a multi-shot manner
#1
TICKINT
None
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended
#1
SYST_CVR
SYST_CVR
SysTick Current Value Register
0x18
read-write
n
0x0
0x0
CURRENT
Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
0
24
read-write
SYST_RVR
SYST_RVR
SysTick Reload Value Register
0x14
read-write
n
0x0
0x0
RELOAD
Value to load into the Current Value register when the counter reaches 0.
0
24
read-write
SPI0
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x8
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity\n
11
1
read-write
0
SPICLK idle low
#0
1
SPICLK idle high
#1
GO_BUSY
Go and Busy Status\nDuring the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote: All registers should be set before writing 1 to this GO_BUSY bit.
0
1
read-write
0
Stop data transfer if SPI is transferring
#0
1
In Master mode, start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Interrupt Enable\n
17
1
read-write
0
SPI Interrupt Disabled
#0
1
SPI Interrupt Enabled
#1
IF
Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
Indicates the transfer dose not finish
#0
1
Indicates the transfer is done
#1
LSB
LSB First\n
10
1
read-write
0
MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the TX_BIT_LEN field)
#0
1
LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position in the RX register (bit 0 of SPI_RX0/1)
#1
REORDER
Reorder Mode Select\nNote:\nByte reorder function is only available when TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, if the byte suspend function is enabled, the slave select pin must be kept at active state during the successive four bytes transfer.
19
2
read-write
0
Both byte reorder and byte suspend functions Disabled
#00
1
Byte reorder function Enabled, and a byte suspend interval (2~17 SPICLK cycles) inserted among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word)
#01
2
Byte reorder function Enabled, but byte suspend function Disabled
#10
3
Byte reorder function Disabled, but a suspend interval (2~17 SPICLK cycles) inserted among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word)
#11
RX_NEG
Receive At Negative Edge\n
1
1
read-write
0
Received data input signal is latched at the rising edge of SPICLK
#0
1
Received data input signal is latched at the falling edge of SPICLK
#1
SLAVE
Slave Mode Enable Bit\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\n
12
4
read-write
TWOB
Two Bits Transfer Mode Active\nNote: When TWOB is enabled, the serial transmitted 2-bit data output are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.\nNote: When TWOB is enabled, the setting of TX_NUM must be programmed as 0x00.
22
1
read-write
0
Two-bit Transfer mode Disabled
#0
1
Two-bit Transfer mode Enabled
#1
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
3
5
read-write
TX_NEG
Transmit At Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed at the rising edge of SPICLK
#0
1
Transmitted data output signal is changed at the falling edge of SPICLK
#1
TX_NUM
Numbers of Transmit/Receive Word\nThis field specifies how many transmit/receive word numbers should be executed in one transfer.\nNote: In Slave mode with level-trigger configuration, if TX_NUM is set to 01, the slave select pin must be kept at active state during the successive data transfer.
8
2
read-write
0
Only one transmit/receive word will be executed in one transfer
#00
1
Two successive transmit/receive words will be executed in one transfer. (burst mode)
#01
2
Reserved
#10
3
Reserved
#11
VARCLK_EN
Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is enabled, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)
23
1
read-write
0
Serial clock output frequency is fixed and decided only by the value of DIVIDER
#0
1
Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register (Master Only)
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 (Master Only)\nThe value in this field is the frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIn Slave mode, the period of SPI clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK.
0
16
read-write
DIVIDER2
Clock Divider 2 (Master Only)\nThe value in this field is the 2nd frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIf VARCLK_EN is cleared to 0, this setting is unmeaning.
16
16
read-write
SPI_DMA
SPI_DMA
SPI DMA Control Register
0x38
read-write
n
0x0
0x0
RX_DMA_GO
Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. SPI controller will issue request to PDMA controller automatically.\nHardware will clear this bit to 0 automatically after PDMA transfer done.
1
1
read-write
TX_DMA_GO
Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically.\nIf using PDMA mode to transfer data, remember not to set GO_BUSY bit of SPI_CNTRL register. The DMA controller inside SPI controller will set it automatically whenever necessary.\nHardware will clear this bit to 0 automatically after PDMA transfer done.\nNote: In DMA mode, the burst mode is not supported.
0
1
read-write
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. The values of the other bits are unknown.\nNote: The Data Receive Registers are read only.
0
32
read-only
SPI_RX1
SPI_RX1
Data Receive Register 1
0x14
read-write
n
0x0
0x0
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Enable Bit (Master only)\n
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing related bits in SSR[1:0]
#0
1
If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SSR[1:0], will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nWhen the SS_LTRIG bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only.
5
1
read-write
0
Transaction number or the transferred bit length of one transaction does not meet the specified requirements
#0
1
Transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master only)
If AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL.
Note: SPISSx0 is also defined as slave select input in Slave mode.
0
2
read-write
SS_LTRIG
Slave Select Level Trigger Enable Bit (Slave only)\n
4
1
read-write
0
Input slave select signal is edge-trigger. This is the default value. It depends on SS_LVL to decide the signal is active at falling-edge or rising-edge
#0
1
Slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nIt defines the active status of slave select signal (SPISSx0/1).\n
2
1
read-write
0
Slave select signal SPISSx0/1 is active at low-level/falling-edge
#0
1
Slave select signal SPISSx0/1 is active at high-level/rising-edge
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The valid bits depend on the transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the SPI controller will perform two 32-bit transmit/receive successive using the same setting. The transmission sequence is TX0[31:0] first and then TX1[31:0].
0
32
write-only
SPI_TX1
SPI_TX1
Data Transmit Register 1
0x24
read-write
n
0x0
0x0
SPI_VARCLK
SPI_VARCLK
Variable Clock Pattern Register
0x34
-1
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern\nThe value in this field is the frequency patterns of the SPI clock. If the bit pattern of VARCLK is '0', the output frequency of SPICLK is in accordance with the value of DIVIDER. If the bit patterns of VARCLK are '1', the output frequency of SPICLK is in accordance with the value of DIVIDER2. Refer to register SPI_DIVIDER.\nRefer to the Variable Serial Clock Frequency paragraph for more detailed description.
0
32
read-write
SPI1
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x8
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity\n
11
1
read-write
0
SPICLK idle low
#0
1
SPICLK idle high
#1
GO_BUSY
Go and Busy Status\nDuring the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote: All registers should be set before writing 1 to this GO_BUSY bit.
0
1
read-write
0
Stop data transfer if SPI is transferring
#0
1
In Master mode, start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Interrupt Enable\n
17
1
read-write
0
SPI Interrupt Disabled
#0
1
SPI Interrupt Enabled
#1
IF
Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
Indicates the transfer dose not finish
#0
1
Indicates the transfer is done
#1
LSB
LSB First\n
10
1
read-write
0
MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the TX_BIT_LEN field)
#0
1
LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position in the RX register (bit 0 of SPI_RX0/1)
#1
REORDER
Reorder Mode Select\nNote:\nByte reorder function is only available when TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, if the byte suspend function is enabled, the slave select pin must be kept at active state during the successive four bytes transfer.
19
2
read-write
0
Both byte reorder and byte suspend functions Disabled
#00
1
Byte reorder function Enabled, and a byte suspend interval (2~17 SPICLK cycles) inserted among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word)
#01
2
Byte reorder function Enabled, but byte suspend function Disabled
#10
3
Byte reorder function Disabled, but a suspend interval (2~17 SPICLK cycles) inserted among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word)
#11
RX_NEG
Receive At Negative Edge\n
1
1
read-write
0
Received data input signal is latched at the rising edge of SPICLK
#0
1
Received data input signal is latched at the falling edge of SPICLK
#1
SLAVE
Slave Mode Enable Bit\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\n
12
4
read-write
TWOB
Two Bits Transfer Mode Active\nNote: When TWOB is enabled, the serial transmitted 2-bit data output are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.\nNote: When TWOB is enabled, the setting of TX_NUM must be programmed as 0x00.
22
1
read-write
0
Two-bit Transfer mode Disabled
#0
1
Two-bit Transfer mode Enabled
#1
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
3
5
read-write
TX_NEG
Transmit At Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed at the rising edge of SPICLK
#0
1
Transmitted data output signal is changed at the falling edge of SPICLK
#1
TX_NUM
Numbers of Transmit/Receive Word\nThis field specifies how many transmit/receive word numbers should be executed in one transfer.\nNote: In Slave mode with level-trigger configuration, if TX_NUM is set to 01, the slave select pin must be kept at active state during the successive data transfer.
8
2
read-write
0
Only one transmit/receive word will be executed in one transfer
#00
1
Two successive transmit/receive words will be executed in one transfer. (burst mode)
#01
2
Reserved
#10
3
Reserved
#11
VARCLK_EN
Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is enabled, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)
23
1
read-write
0
Serial clock output frequency is fixed and decided only by the value of DIVIDER
#0
1
Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register (Master Only)
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 (Master Only)\nThe value in this field is the frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIn Slave mode, the period of SPI clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK.
0
16
read-write
DIVIDER2
Clock Divider 2 (Master Only)\nThe value in this field is the 2nd frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIf VARCLK_EN is cleared to 0, this setting is unmeaning.
16
16
read-write
SPI_DMA
SPI_DMA
SPI DMA Control Register
0x38
read-write
n
0x0
0x0
RX_DMA_GO
Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. SPI controller will issue request to PDMA controller automatically.\nHardware will clear this bit to 0 automatically after PDMA transfer done.
1
1
read-write
TX_DMA_GO
Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically.\nIf using PDMA mode to transfer data, remember not to set GO_BUSY bit of SPI_CNTRL register. The DMA controller inside SPI controller will set it automatically whenever necessary.\nHardware will clear this bit to 0 automatically after PDMA transfer done.\nNote: In DMA mode, the burst mode is not supported.
0
1
read-write
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. The values of the other bits are unknown.\nNote: The Data Receive Registers are read only.
0
32
read-only
SPI_RX1
SPI_RX1
Data Receive Register 1
0x14
read-write
n
0x0
0x0
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Enable Bit (Master only)\n
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing related bits in SSR[1:0]
#0
1
If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SSR[1:0], will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nWhen the SS_LTRIG bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only.
5
1
read-write
0
Transaction number or the transferred bit length of one transaction does not meet the specified requirements
#0
1
Transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master only)
If AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL.
Note: SPISSx0 is also defined as slave select input in Slave mode.
0
2
read-write
SS_LTRIG
Slave Select Level Trigger Enable Bit (Slave only)\n
4
1
read-write
0
Input slave select signal is edge-trigger. This is the default value. It depends on SS_LVL to decide the signal is active at falling-edge or rising-edge
#0
1
Slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nIt defines the active status of slave select signal (SPISSx0/1).\n
2
1
read-write
0
Slave select signal SPISSx0/1 is active at low-level/falling-edge
#0
1
Slave select signal SPISSx0/1 is active at high-level/rising-edge
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The valid bits depend on the transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the SPI controller will perform two 32-bit transmit/receive successive using the same setting. The transmission sequence is TX0[31:0] first and then TX1[31:0].
0
32
write-only
SPI_TX1
SPI_TX1
Data Transmit Register 1
0x24
read-write
n
0x0
0x0
SPI_VARCLK
SPI_VARCLK
Variable Clock Pattern Register
0x34
-1
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern\nThe value in this field is the frequency patterns of the SPI clock. If the bit pattern of VARCLK is '0', the output frequency of SPICLK is in accordance with the value of DIVIDER. If the bit patterns of VARCLK are '1', the output frequency of SPICLK is in accordance with the value of DIVIDER2. Refer to register SPI_DIVIDER.\nRefer to the Variable Serial Clock Frequency paragraph for more detailed description.
0
32
read-write
SPI2
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x8
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity\n
11
1
read-write
0
SPICLK idle low
#0
1
SPICLK idle high
#1
GO_BUSY
Go and Busy Status\nDuring the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote: All registers should be set before writing 1 to this GO_BUSY bit.
0
1
read-write
0
Stop data transfer if SPI is transferring
#0
1
In Master mode, start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Interrupt Enable\n
17
1
read-write
0
SPI Interrupt Disabled
#0
1
SPI Interrupt Enabled
#1
IF
Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
Indicates the transfer dose not finish
#0
1
Indicates the transfer is done
#1
LSB
LSB First\n
10
1
read-write
0
MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the TX_BIT_LEN field)
#0
1
LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position in the RX register (bit 0 of SPI_RX0/1)
#1
REORDER
Reorder Mode Select\nNote:\nByte reorder function is only available when TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, if the byte suspend function is enabled, the slave select pin must be kept at active state during the successive four bytes transfer.
19
2
read-write
0
Both byte reorder and byte suspend functions Disabled
#00
1
Byte reorder function Enabled, and a byte suspend interval (2~17 SPICLK cycles) inserted among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word)
#01
2
Byte reorder function Enabled, but byte suspend function Disabled
#10
3
Byte reorder function Disabled, but a suspend interval (2~17 SPICLK cycles) inserted among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word)
#11
RX_NEG
Receive At Negative Edge\n
1
1
read-write
0
Received data input signal is latched at the rising edge of SPICLK
#0
1
Received data input signal is latched at the falling edge of SPICLK
#1
SLAVE
Slave Mode Enable Bit\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\n
12
4
read-write
TWOB
Two Bits Transfer Mode Active\nNote: When TWOB is enabled, the serial transmitted 2-bit data output are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.\nNote: When TWOB is enabled, the setting of TX_NUM must be programmed as 0x00.
22
1
read-write
0
Two-bit Transfer mode Disabled
#0
1
Two-bit Transfer mode Enabled
#1
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
3
5
read-write
TX_NEG
Transmit At Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed at the rising edge of SPICLK
#0
1
Transmitted data output signal is changed at the falling edge of SPICLK
#1
TX_NUM
Numbers of Transmit/Receive Word\nThis field specifies how many transmit/receive word numbers should be executed in one transfer.\nNote: In Slave mode with level-trigger configuration, if TX_NUM is set to 01, the slave select pin must be kept at active state during the successive data transfer.
8
2
read-write
0
Only one transmit/receive word will be executed in one transfer
#00
1
Two successive transmit/receive words will be executed in one transfer. (burst mode)
#01
2
Reserved
#10
3
Reserved
#11
VARCLK_EN
Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is enabled, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)
23
1
read-write
0
Serial clock output frequency is fixed and decided only by the value of DIVIDER
#0
1
Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register (Master Only)
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 (Master Only)\nThe value in this field is the frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIn Slave mode, the period of SPI clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK.
0
16
read-write
DIVIDER2
Clock Divider 2 (Master Only)\nThe value in this field is the 2nd frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIf VARCLK_EN is cleared to 0, this setting is unmeaning.
16
16
read-write
SPI_DMA
SPI_DMA
SPI DMA Control Register
0x38
read-write
n
0x0
0x0
RX_DMA_GO
Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. SPI controller will issue request to PDMA controller automatically.\nHardware will clear this bit to 0 automatically after PDMA transfer done.
1
1
read-write
TX_DMA_GO
Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically.\nIf using PDMA mode to transfer data, remember not to set GO_BUSY bit of SPI_CNTRL register. The DMA controller inside SPI controller will set it automatically whenever necessary.\nHardware will clear this bit to 0 automatically after PDMA transfer done.\nNote: In DMA mode, the burst mode is not supported.
0
1
read-write
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. The values of the other bits are unknown.\nNote: The Data Receive Registers are read only.
0
32
read-only
SPI_RX1
SPI_RX1
Data Receive Register 1
0x14
read-write
n
0x0
0x0
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Enable Bit (Master only)\n
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing related bits in SSR[1:0]
#0
1
If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SSR[1:0], will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nWhen the SS_LTRIG bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only.
5
1
read-write
0
Transaction number or the transferred bit length of one transaction does not meet the specified requirements
#0
1
Transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master only)
If AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL.
Note: SPISSx0 is also defined as slave select input in Slave mode.
0
2
read-write
SS_LTRIG
Slave Select Level Trigger Enable Bit (Slave only)\n
4
1
read-write
0
Input slave select signal is edge-trigger. This is the default value. It depends on SS_LVL to decide the signal is active at falling-edge or rising-edge
#0
1
Slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nIt defines the active status of slave select signal (SPISSx0/1).\n
2
1
read-write
0
Slave select signal SPISSx0/1 is active at low-level/falling-edge
#0
1
Slave select signal SPISSx0/1 is active at high-level/rising-edge
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The valid bits depend on the transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the SPI controller will perform two 32-bit transmit/receive successive using the same setting. The transmission sequence is TX0[31:0] first and then TX1[31:0].
0
32
write-only
SPI_TX1
SPI_TX1
Data Transmit Register 1
0x24
read-write
n
0x0
0x0
SPI_VARCLK
SPI_VARCLK
Variable Clock Pattern Register
0x34
-1
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern\nThe value in this field is the frequency patterns of the SPI clock. If the bit pattern of VARCLK is '0', the output frequency of SPICLK is in accordance with the value of DIVIDER. If the bit patterns of VARCLK are '1', the output frequency of SPICLK is in accordance with the value of DIVIDER2. Refer to register SPI_DIVIDER.\nRefer to the Variable Serial Clock Frequency paragraph for more detailed description.
0
32
read-write
SPI3
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x8
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity\n
11
1
read-write
0
SPICLK idle low
#0
1
SPICLK idle high
#1
GO_BUSY
Go and Busy Status\nDuring the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote: All registers should be set before writing 1 to this GO_BUSY bit.
0
1
read-write
0
Stop data transfer if SPI is transferring
#0
1
In Master mode, start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Interrupt Enable\n
17
1
read-write
0
SPI Interrupt Disabled
#0
1
SPI Interrupt Enabled
#1
IF
Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
Indicates the transfer dose not finish
#0
1
Indicates the transfer is done
#1
LSB
LSB First\n
10
1
read-write
0
MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the TX_BIT_LEN field)
#0
1
LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position in the RX register (bit 0 of SPI_RX0/1)
#1
REORDER
Reorder Mode Select\nNote:\nByte reorder function is only available when TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, if the byte suspend function is enabled, the slave select pin must be kept at active state during the successive four bytes transfer.
19
2
read-write
0
Both byte reorder and byte suspend functions Disabled
#00
1
Byte reorder function Enabled, and a byte suspend interval (2~17 SPICLK cycles) inserted among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word)
#01
2
Byte reorder function Enabled, but byte suspend function Disabled
#10
3
Byte reorder function Disabled, but a suspend interval (2~17 SPICLK cycles) inserted among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word)
#11
RX_NEG
Receive At Negative Edge\n
1
1
read-write
0
Received data input signal is latched at the rising edge of SPICLK
#0
1
Received data input signal is latched at the falling edge of SPICLK
#1
SLAVE
Slave Mode Enable Bit\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\n
12
4
read-write
TWOB
Two Bits Transfer Mode Active\nNote: When TWOB is enabled, the serial transmitted 2-bit data output are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.\nNote: When TWOB is enabled, the setting of TX_NUM must be programmed as 0x00.
22
1
read-write
0
Two-bit Transfer mode Disabled
#0
1
Two-bit Transfer mode Enabled
#1
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
3
5
read-write
TX_NEG
Transmit At Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed at the rising edge of SPICLK
#0
1
Transmitted data output signal is changed at the falling edge of SPICLK
#1
TX_NUM
Numbers of Transmit/Receive Word\nThis field specifies how many transmit/receive word numbers should be executed in one transfer.\nNote: In Slave mode with level-trigger configuration, if TX_NUM is set to 01, the slave select pin must be kept at active state during the successive data transfer.
8
2
read-write
0
Only one transmit/receive word will be executed in one transfer
#00
1
Two successive transmit/receive words will be executed in one transfer. (burst mode)
#01
2
Reserved
#10
3
Reserved
#11
VARCLK_EN
Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is enabled, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)
23
1
read-write
0
Serial clock output frequency is fixed and decided only by the value of DIVIDER
#0
1
Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register (Master Only)
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 (Master Only)\nThe value in this field is the frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIn Slave mode, the period of SPI clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK.
0
16
read-write
DIVIDER2
Clock Divider 2 (Master Only)\nThe value in this field is the 2nd frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIf VARCLK_EN is cleared to 0, this setting is unmeaning.
16
16
read-write
SPI_DMA
SPI_DMA
SPI DMA Control Register
0x38
read-write
n
0x0
0x0
RX_DMA_GO
Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. SPI controller will issue request to PDMA controller automatically.\nHardware will clear this bit to 0 automatically after PDMA transfer done.
1
1
read-write
TX_DMA_GO
Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically.\nIf using PDMA mode to transfer data, remember not to set GO_BUSY bit of SPI_CNTRL register. The DMA controller inside SPI controller will set it automatically whenever necessary.\nHardware will clear this bit to 0 automatically after PDMA transfer done.\nNote: In DMA mode, the burst mode is not supported.
0
1
read-write
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. The values of the other bits are unknown.\nNote: The Data Receive Registers are read only.
0
32
read-only
SPI_RX1
SPI_RX1
Data Receive Register 1
0x14
read-write
n
0x0
0x0
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Enable Bit (Master only)\n
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing related bits in SSR[1:0]
#0
1
If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SSR[1:0], will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nWhen the SS_LTRIG bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only.
5
1
read-write
0
Transaction number or the transferred bit length of one transaction does not meet the specified requirements
#0
1
Transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master only)
If AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL.
Note: SPISSx0 is also defined as slave select input in Slave mode.
0
2
read-write
SS_LTRIG
Slave Select Level Trigger Enable Bit (Slave only)\n
4
1
read-write
0
Input slave select signal is edge-trigger. This is the default value. It depends on SS_LVL to decide the signal is active at falling-edge or rising-edge
#0
1
Slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nIt defines the active status of slave select signal (SPISSx0/1).\n
2
1
read-write
0
Slave select signal SPISSx0/1 is active at low-level/falling-edge
#0
1
Slave select signal SPISSx0/1 is active at high-level/rising-edge
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The valid bits depend on the transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the SPI controller will perform two 32-bit transmit/receive successive using the same setting. The transmission sequence is TX0[31:0] first and then TX1[31:0].
0
32
write-only
SPI_TX1
SPI_TX1
Data Transmit Register 1
0x24
read-write
n
0x0
0x0
SPI_VARCLK
SPI_VARCLK
Variable Clock Pattern Register
0x34
-1
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern\nThe value in this field is the frequency patterns of the SPI clock. If the bit pattern of VARCLK is '0', the output frequency of SPICLK is in accordance with the value of DIVIDER. If the bit patterns of VARCLK are '1', the output frequency of SPICLK is in accordance with the value of DIVIDER2. Refer to register SPI_DIVIDER.\nRefer to the Variable Serial Clock Frequency paragraph for more detailed description.
0
32
read-write
TMR01
TMR Register Map
TMR
0x0
0x0
0x10
registers
n
0x20
0x10
registers
n
TCMPR0
TCMPR0
Timer0 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP.
0
24
read-write
TCMPR1
TCMPR1
Timer1 Compare Register
0x24
read-write
n
0x0
0x0
TCSR0
TCSR0
Timer0 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CACT
Timer Active Status Bit (Read Only)\nThis bit indicates the up-timer status.\n
25
1
read-only
0
Timer is not active
#0
1
Timer is active
#1
CEN
Timer Enable Bit\n
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
CRST
Timer Reset Bit\nSetting this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0.\n
26
1
read-write
0
No effect
#0
1
Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit
#1
CTB
Counter Mode Enable Bit (NuMicro( NUC100/NUC120 Low Density Only)\nThis bit is the counter mode enable bit. When Timer is used as an event counter, this bit should be set to 1 and Timer will work as an event counter. The event is triggered by rising edge from external pin\n
24
1
read-write
0
Disabled counter mode
#0
1
counter mode Enabled
#1
DBGACK_TMR
ICE Debug Mode Acknowledge Disable (Write-protection Bit)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement disabled
#1
IE
Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR.
29
1
read-write
0
Timer Interrupt Disabled
#0
1
Timer Interrupt Enabled
#1
MODE
Timer Operating Mode\n
27
2
read-write
PRESCALE
Pre-scale Counter\n
0
8
read-write
TDR_EN
Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n
16
1
read-write
0
Timer Data Register update Disabled
#0
1
Timer Data Register update Enabled
#1
TCSR1
TCSR1
Timer1 Control and Status Register
0x20
read-write
n
0x0
0x0
TDR0
TDR0
Timer0 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register\nWhen TCSR.TDR_EN is set to 1, the internal 24-bit up-timer value will be loaded into TDR. User can read this register for the up-timer value.
0
24
read-only
TDR1
TDR1
Timer1 Data Register
0x2C
read-write
n
0x0
0x0
TISR0
TISR0
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt status of Timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit up-timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit.
0
1
read-write
TISR1
TISR1
Timer1 Interrupt Status Register
0x28
read-write
n
0x0
0x0
TMR23
TMR Register Map
TMR
0x0
0x0
0x10
registers
n
0x20
0x10
registers
n
TCMPR2
TCMPR2
Timer2 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP.
0
24
read-write
TCMPR3
TCMPR3
Timer3 Compare Register
0x24
read-write
n
0x0
0x0
TCSR2
TCSR2
Timer2 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CACT
Timer Active Status Bit (Read Only)\nThis bit indicates the up-timer status.\n
25
1
read-only
0
Timer is not active
#0
1
Timer is active
#1
CEN
Timer Enable Bit\n
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
CRST
Timer Reset Bit\nSetting this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0.\n
26
1
read-write
0
No effect
#0
1
Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit
#1
CTB
Counter Mode Enable Bit (NuMicro( NUC100/NUC120 Low Density Only)\nThis bit is the counter mode enable bit. When Timer is used as an event counter, this bit should be set to 1 and Timer will work as an event counter. The event is triggered by rising edge from external pin\n
24
1
read-write
0
Disabled counter mode
#0
1
counter mode Enabled
#1
DBGACK_TMR
ICE Debug Mode Acknowledge Disable (Write-protection Bit)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement disabled
#1
IE
Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR.
29
1
read-write
0
Timer Interrupt Disabled
#0
1
Timer Interrupt Enabled
#1
MODE
Timer Operating Mode\n
27
2
read-write
PRESCALE
Pre-scale Counter\n
0
8
read-write
TDR_EN
Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n
16
1
read-write
0
Timer Data Register update Disabled
#0
1
Timer Data Register update Enabled
#1
TCSR3
TCSR3
Timer3 Control and Status Register
0x20
read-write
n
0x0
0x0
TDR2
TDR2
Timer2 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register\nWhen TCSR.TDR_EN is set to 1, the internal 24-bit up-timer value will be loaded into TDR. User can read this register for the up-timer value.
0
24
read-only
TDR3
TDR3
Timer3 Data Register
0x2C
read-write
n
0x0
0x0
TISR2
TISR2
Timer2 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt status of Timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit up-timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit.
0
1
read-write
TISR3
TISR3
Timer3 Interrupt Status Register
0x28
read-write
n
0x0
0x0
UART0
UART Register Map
UART
0x0
0x0
0x30
registers
n
UA_ALT_CSR
UA_ALT_CSR
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address Match Value Register (NuMicro( NUC100/NUC120 Low Density Only)\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD) (NuMicro( NUC100/NUC120 Low Density Only)\nNote: It can't be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation Mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation Mode (AAD) Enabled
#1
RS485_ADD_EN
RS-485 Address Detection Enable (NuMicro( NUC100/NUC120 Low Density Only)\nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD) (NuMicro( NUC100/NUC120 Low Density Only)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation Mode (AUO) Disabled
#0
1
RS-485 Auto Direction Operation mode (AUO) Enabled
#1
RS485_NMM
RS-485 Normal Multi-drop Operation Mode (NMM) (NuMicro( NUC100/NUC120 Low Density Only)\nNote: It can't be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UA_BAUD
UA_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BRD
Baud Rate Divider\nThe field indicates the baud rate divider.
0
16
read-write
DIVIDER_X
Divider X\n
24
4
read-write
DIV_X_EN
Divider X Enable\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must be disabled.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
#1
DIV_X_ONE
Divider X Equal to 1\nRefer to the Table 513 below for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3)
#1
UA_FCR
UA_FCR
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\n
4
4
read-write
RFR
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
RTS_TRI_LEV
RTS Trigger Level for Auto-flow Control Use (Not Available in UART2 Channel)\n
16
4
read-write
RX_DIS
Receiver Disable Register.
The receiver is disabled or not (set 1 to disable receiver)
Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
TFR
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UA_FSR
UA_FSR
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
BIF
Break Interrupt Flag (Read Only)
This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
Note:Note: This bit is read only, but can be cleared by writing '1' to it.
6
1
read-only
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
5
1
read-only
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
4
1
read-only
RS485_ADD_DETF
RS-485 Address Byte Detection Flag (NuMicro( NUC100/NUC120Low Density Only)\nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-write
RX_EMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiates RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RX_OVER_IF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-only
RX_POINTER
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.
8
6
read-only
TE_FLAG
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TX_EMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
TX_OVER_IF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it.
24
1
read-only
TX_POINTER
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.
16
6
read-only
UA_FUN_SEL
UA_FUN_SEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable\n
0
2
read-write
0
UART function
#00
1
Reserved
#01
2
IrDA function Enabled
#10
3
RS-485 Function Enabled (NuMicro( NUC100/NUC120 Low Density Only)
#11
UA_IER
UA_IER
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
AUTO_CTS_EN
CTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
CTS auto flow control Disabled
#0
1
CTS auto flow control Enabled
#1
AUTO_RTS_EN
RTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal.
12
1
read-write
0
RTS auto flow control Disabled
#0
1
RTS auto flow control Enabled
#1
BUF_ERR_IEN
Buffer Error Interrupt Enable\n
5
1
read-write
0
INT_BUF_ERR Maskdd off
#0
1
INT_BUF_ERR Enabled
#1
DMA_RX_EN
RX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable RX DMA service.\n
15
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
DMA_TX_EN
TX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable TX DMA service.\n
14
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
MODEM_IEN
Modem Status Interrupt Enable (Not Available in UART2 Channel)\n
3
1
read-write
0
INT_MODEM Masked off
#0
1
INT_MODEM Enabled
#1
RDA_IEN
Receive Data Available Interrupt Enable.\n
0
1
read-write
0
INT_RDA Masked off
#0
1
INT_RDA Enabled
#1
RLS_IEN
Receive Line Status Interrupt Enable \n
2
1
read-write
0
INT_RLS Masked off
#0
1
INT_RLS Enabled
#1
RTO_IEN
RX Time Out Interrupt Enable\n
4
1
read-write
0
INT_TOUT Masked off
#0
1
INT_TOUT Enabled
#1
THRE_IEN
Transmit Holding Register Empty Interrupt Enable\n
1
1
read-write
0
INT_THRE Masked off
#0
1
INT_THRE Enabled
#1
TIME_OUT_EN
Time Out Counter Enable\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
WAKE_EN
UART Wake-up Function Enable (Not Available in UART2 Channel)\n
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled when the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode
#1
UA_IRCR
UA_IRCR
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
INV_RX
INV_RX\n
6
1
read-write
0
No inversion
#0
1
Inverse RX input signal
#1
INV_TX
INV_TX\n
5
1
read-write
0
No inversion
#0
1
Inverse TX output signal
#1
TX_SELECT
TX_SELECT\n
1
1
read-write
0
IrDA receiver Enabled
#0
1
IrDA transmitter Enabled
#1
UA_ISR
UA_ISR
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUF_ERR_IF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows or Break Interrupt Flag or Parity Error Flag or Frame Error Flag (TX_OVER_IF or RX_OVER_IF or BIF or PEF or FEF) is set. When BUF_ERR_IF is set, the transfer is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.
5
1
read-only
BUF_ERR_INT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HW_BUF_ERR_IF
In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared.
21
1
read-only
HW_BUF_ERR_INT
In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1.\n
29
1
read-only
0
No buffer error interrupt is generated in DMA mode
#0
1
Buffer error interrupt is generated in DMA mode
#1
HW_MODEM_IF
In DMA Mode, MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
19
1
read-only
HW_MODEM_INT
In DMA Mode, MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)
This bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in DMA mode
#0
1
Modem interrupt is generated in DMA mode
#1
HW_RLS_IF
In DMA Mode, Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
18
1
read-only
HW_RLS_INT
In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1.\n
26
1
read-only
0
No RLS interrupt is generated in DMA mode
#0
1
RLS interrupt is generated in DMA mode
#1
HW_TOUT_IF
In DMA Mode, Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
20
1
read-only
HW_TOUT_INT
In DMA Mode, Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1.\n
28
1
read-only
0
No Tout interrupt is generated in DMA mode
#0
1
Tout interrupt is generated in DMA mode
#1
MODEM_IF
MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
3
1
read-only
MODEM_INT
MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDA_IF
Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDA_INT
Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLS_IF
Receive Line Interrupt Flag (Read Only).\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLS_INT
Receive Line Status Interrupt Indicator (Read Only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
1
1
read-only
THRE_INT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TOUT_IF
Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
4
1
read-only
TOUT_INT
Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
UA_LCR
UA_LCR
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of STOP bit
2
1
read-write
0
1 STOP bit
#0
1
2 STOP bits (1.5 STOP bits if WLS[1:0]=00)
#1
PBE
Parity Bit Enable\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable\n
5
1
read-write
0
Stick parity Disabled
#0
1
If bit 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0. If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
UA_MCR
UA_MCR
UART Modem Control Register\nReserved
0x10
-1
read-write
n
0x0
0x0
LEV_RTS
RTS Trigger Level (Not Available in UART2 Channel)\nThis bit can change the RTS trigger level.\n
9
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
RTS
RTS (Request-To-Send) Signal (Not Available in UART2 Channel)\n
1
1
read-write
0
Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered)
#0
1
Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered)
#1
RTS_ST
RTS Pin State (Read Only) (Not Available in UART2 Channel)\nThis bit is the output pin status of RTS.
13
1
read-only
UA_MSR
UA_MSR
UART Modem Status Register\nReserved
0x14
-1
read-write
n
0x0
0x0
CTS_ST
CTS Pin Status (Read Only) (Not Available in UART2 Channel)\nThis bit is the pin status of CTS.
4
1
read-only
DCTSF
Detect CTS State Change Flag (Read Only) (Not Available in UART2 Channel)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nWrite 1 to clear this bit to 0.
0
1
read-only
LEV_CTS
CTS Trigger Level (Not Available in UART2 Channel)\nThis bit can change the CTS trigger level.\n
8
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
UA_RBR
UA_RBR
UART Receive Buffer Register
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first).
0
8
read-only
UA_THR
UA_THR
UART Transmit Holding Register
UA_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first).
0
8
write-only
UA_TOR
UA_TOR
UART Time Out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value (NuMicro( NUC100/NUC120 Low Density Only)\nThis field is use to programming the transfer delay time between the last stop bit and next start bit.
8
8
read-write
TOIC
Time Out Interrupt Comparator\n
0
8
read-write
UART1
UART Register Map
UART
0x0
0x0
0x30
registers
n
UA_ALT_CSR
UA_ALT_CSR
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address Match Value Register (NuMicro( NUC100/NUC120 Low Density Only)\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD) (NuMicro( NUC100/NUC120 Low Density Only)\nNote: It can't be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation Mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation Mode (AAD) Enabled
#1
RS485_ADD_EN
RS-485 Address Detection Enable (NuMicro( NUC100/NUC120 Low Density Only)\nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD) (NuMicro( NUC100/NUC120 Low Density Only)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation Mode (AUO) Disabled
#0
1
RS-485 Auto Direction Operation mode (AUO) Enabled
#1
RS485_NMM
RS-485 Normal Multi-drop Operation Mode (NMM) (NuMicro( NUC100/NUC120 Low Density Only)\nNote: It can't be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UA_BAUD
UA_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BRD
Baud Rate Divider\nThe field indicates the baud rate divider.
0
16
read-write
DIVIDER_X
Divider X\n
24
4
read-write
DIV_X_EN
Divider X Enable\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must be disabled.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
#1
DIV_X_ONE
Divider X Equal to 1\nRefer to the Table 513 below for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3)
#1
UA_FCR
UA_FCR
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\n
4
4
read-write
RFR
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
RTS_TRI_LEV
RTS Trigger Level for Auto-flow Control Use (Not Available in UART2 Channel)\n
16
4
read-write
RX_DIS
Receiver Disable Register.
The receiver is disabled or not (set 1 to disable receiver)
Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
TFR
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UA_FSR
UA_FSR
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
BIF
Break Interrupt Flag (Read Only)
This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
Note:Note: This bit is read only, but can be cleared by writing '1' to it.
6
1
read-only
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
5
1
read-only
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
4
1
read-only
RS485_ADD_DETF
RS-485 Address Byte Detection Flag (NuMicro( NUC100/NUC120Low Density Only)\nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-write
RX_EMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiates RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RX_OVER_IF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-only
RX_POINTER
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.
8
6
read-only
TE_FLAG
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TX_EMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
TX_OVER_IF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it.
24
1
read-only
TX_POINTER
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.
16
6
read-only
UA_FUN_SEL
UA_FUN_SEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable\n
0
2
read-write
0
UART function
#00
1
Reserved
#01
2
IrDA function Enabled
#10
3
RS-485 Function Enabled (NuMicro( NUC100/NUC120 Low Density Only)
#11
UA_IER
UA_IER
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
AUTO_CTS_EN
CTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
CTS auto flow control Disabled
#0
1
CTS auto flow control Enabled
#1
AUTO_RTS_EN
RTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal.
12
1
read-write
0
RTS auto flow control Disabled
#0
1
RTS auto flow control Enabled
#1
BUF_ERR_IEN
Buffer Error Interrupt Enable\n
5
1
read-write
0
INT_BUF_ERR Maskdd off
#0
1
INT_BUF_ERR Enabled
#1
DMA_RX_EN
RX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable RX DMA service.\n
15
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
DMA_TX_EN
TX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable TX DMA service.\n
14
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
MODEM_IEN
Modem Status Interrupt Enable (Not Available in UART2 Channel)\n
3
1
read-write
0
INT_MODEM Masked off
#0
1
INT_MODEM Enabled
#1
RDA_IEN
Receive Data Available Interrupt Enable.\n
0
1
read-write
0
INT_RDA Masked off
#0
1
INT_RDA Enabled
#1
RLS_IEN
Receive Line Status Interrupt Enable \n
2
1
read-write
0
INT_RLS Masked off
#0
1
INT_RLS Enabled
#1
RTO_IEN
RX Time Out Interrupt Enable\n
4
1
read-write
0
INT_TOUT Masked off
#0
1
INT_TOUT Enabled
#1
THRE_IEN
Transmit Holding Register Empty Interrupt Enable\n
1
1
read-write
0
INT_THRE Masked off
#0
1
INT_THRE Enabled
#1
TIME_OUT_EN
Time Out Counter Enable\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
WAKE_EN
UART Wake-up Function Enable (Not Available in UART2 Channel)\n
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled when the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode
#1
UA_IRCR
UA_IRCR
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
INV_RX
INV_RX\n
6
1
read-write
0
No inversion
#0
1
Inverse RX input signal
#1
INV_TX
INV_TX\n
5
1
read-write
0
No inversion
#0
1
Inverse TX output signal
#1
TX_SELECT
TX_SELECT\n
1
1
read-write
0
IrDA receiver Enabled
#0
1
IrDA transmitter Enabled
#1
UA_ISR
UA_ISR
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUF_ERR_IF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows or Break Interrupt Flag or Parity Error Flag or Frame Error Flag (TX_OVER_IF or RX_OVER_IF or BIF or PEF or FEF) is set. When BUF_ERR_IF is set, the transfer is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.
5
1
read-only
BUF_ERR_INT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HW_BUF_ERR_IF
In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared.
21
1
read-only
HW_BUF_ERR_INT
In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1.\n
29
1
read-only
0
No buffer error interrupt is generated in DMA mode
#0
1
Buffer error interrupt is generated in DMA mode
#1
HW_MODEM_IF
In DMA Mode, MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
19
1
read-only
HW_MODEM_INT
In DMA Mode, MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)
This bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in DMA mode
#0
1
Modem interrupt is generated in DMA mode
#1
HW_RLS_IF
In DMA Mode, Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
18
1
read-only
HW_RLS_INT
In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1.\n
26
1
read-only
0
No RLS interrupt is generated in DMA mode
#0
1
RLS interrupt is generated in DMA mode
#1
HW_TOUT_IF
In DMA Mode, Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
20
1
read-only
HW_TOUT_INT
In DMA Mode, Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1.\n
28
1
read-only
0
No Tout interrupt is generated in DMA mode
#0
1
Tout interrupt is generated in DMA mode
#1
MODEM_IF
MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
3
1
read-only
MODEM_INT
MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDA_IF
Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDA_INT
Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLS_IF
Receive Line Interrupt Flag (Read Only).\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLS_INT
Receive Line Status Interrupt Indicator (Read Only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
1
1
read-only
THRE_INT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TOUT_IF
Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
4
1
read-only
TOUT_INT
Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
UA_LCR
UA_LCR
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of STOP bit
2
1
read-write
0
1 STOP bit
#0
1
2 STOP bits (1.5 STOP bits if WLS[1:0]=00)
#1
PBE
Parity Bit Enable\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable\n
5
1
read-write
0
Stick parity Disabled
#0
1
If bit 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0. If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
UA_MCR
UA_MCR
UART Modem Control Register\nReserved
0x10
-1
read-write
n
0x0
0x0
LEV_RTS
RTS Trigger Level (Not Available in UART2 Channel)\nThis bit can change the RTS trigger level.\n
9
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
RTS
RTS (Request-To-Send) Signal (Not Available in UART2 Channel)\n
1
1
read-write
0
Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered)
#0
1
Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered)
#1
RTS_ST
RTS Pin State (Read Only) (Not Available in UART2 Channel)\nThis bit is the output pin status of RTS.
13
1
read-only
UA_MSR
UA_MSR
UART Modem Status Register\nReserved
0x14
-1
read-write
n
0x0
0x0
CTS_ST
CTS Pin Status (Read Only) (Not Available in UART2 Channel)\nThis bit is the pin status of CTS.
4
1
read-only
DCTSF
Detect CTS State Change Flag (Read Only) (Not Available in UART2 Channel)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nWrite 1 to clear this bit to 0.
0
1
read-only
LEV_CTS
CTS Trigger Level (Not Available in UART2 Channel)\nThis bit can change the CTS trigger level.\n
8
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
UA_RBR
UA_RBR
UART Receive Buffer Register
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first).
0
8
read-only
UA_THR
UA_THR
UART Transmit Holding Register
UA_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first).
0
8
write-only
UA_TOR
UA_TOR
UART Time Out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value (NuMicro( NUC100/NUC120 Low Density Only)\nThis field is use to programming the transfer delay time between the last stop bit and next start bit.
8
8
read-write
TOIC
Time Out Interrupt Comparator\n
0
8
read-write
UART2
UART Register Map
UART
0x0
0x0
0x30
registers
n
UA_ALT_CSR
UA_ALT_CSR
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address Match Value Register (NuMicro( NUC100/NUC120 Low Density Only)\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD) (NuMicro( NUC100/NUC120 Low Density Only)\nNote: It can't be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation Mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation Mode (AAD) Enabled
#1
RS485_ADD_EN
RS-485 Address Detection Enable (NuMicro( NUC100/NUC120 Low Density Only)\nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD) (NuMicro( NUC100/NUC120 Low Density Only)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation Mode (AUO) Disabled
#0
1
RS-485 Auto Direction Operation mode (AUO) Enabled
#1
RS485_NMM
RS-485 Normal Multi-drop Operation Mode (NMM) (NuMicro( NUC100/NUC120 Low Density Only)\nNote: It can't be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UA_BAUD
UA_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BRD
Baud Rate Divider\nThe field indicates the baud rate divider.
0
16
read-write
DIVIDER_X
Divider X\n
24
4
read-write
DIV_X_EN
Divider X Enable\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must be disabled.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
#1
DIV_X_ONE
Divider X Equal to 1\nRefer to the Table 513 below for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3)
#1
UA_FCR
UA_FCR
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\n
4
4
read-write
RFR
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
RTS_TRI_LEV
RTS Trigger Level for Auto-flow Control Use (Not Available in UART2 Channel)\n
16
4
read-write
RX_DIS
Receiver Disable Register.
The receiver is disabled or not (set 1 to disable receiver)
Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
TFR
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UA_FSR
UA_FSR
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
BIF
Break Interrupt Flag (Read Only)
This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
Note:Note: This bit is read only, but can be cleared by writing '1' to it.
6
1
read-only
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
5
1
read-only
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
4
1
read-only
RS485_ADD_DETF
RS-485 Address Byte Detection Flag (NuMicro( NUC100/NUC120Low Density Only)\nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-write
RX_EMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiates RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RX_OVER_IF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-only
RX_POINTER
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.
8
6
read-only
TE_FLAG
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TX_EMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
TX_OVER_IF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it.
24
1
read-only
TX_POINTER
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.
16
6
read-only
UA_FUN_SEL
UA_FUN_SEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable\n
0
2
read-write
0
UART function
#00
1
Reserved
#01
2
IrDA function Enabled
#10
3
RS-485 Function Enabled (NuMicro( NUC100/NUC120 Low Density Only)
#11
UA_IER
UA_IER
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
AUTO_CTS_EN
CTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
CTS auto flow control Disabled
#0
1
CTS auto flow control Enabled
#1
AUTO_RTS_EN
RTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal.
12
1
read-write
0
RTS auto flow control Disabled
#0
1
RTS auto flow control Enabled
#1
BUF_ERR_IEN
Buffer Error Interrupt Enable\n
5
1
read-write
0
INT_BUF_ERR Maskdd off
#0
1
INT_BUF_ERR Enabled
#1
DMA_RX_EN
RX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable RX DMA service.\n
15
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
DMA_TX_EN
TX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable TX DMA service.\n
14
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
MODEM_IEN
Modem Status Interrupt Enable (Not Available in UART2 Channel)\n
3
1
read-write
0
INT_MODEM Masked off
#0
1
INT_MODEM Enabled
#1
RDA_IEN
Receive Data Available Interrupt Enable.\n
0
1
read-write
0
INT_RDA Masked off
#0
1
INT_RDA Enabled
#1
RLS_IEN
Receive Line Status Interrupt Enable \n
2
1
read-write
0
INT_RLS Masked off
#0
1
INT_RLS Enabled
#1
RTO_IEN
RX Time Out Interrupt Enable\n
4
1
read-write
0
INT_TOUT Masked off
#0
1
INT_TOUT Enabled
#1
THRE_IEN
Transmit Holding Register Empty Interrupt Enable\n
1
1
read-write
0
INT_THRE Masked off
#0
1
INT_THRE Enabled
#1
TIME_OUT_EN
Time Out Counter Enable\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
WAKE_EN
UART Wake-up Function Enable (Not Available in UART2 Channel)\n
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled when the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode
#1
UA_IRCR
UA_IRCR
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
INV_RX
INV_RX\n
6
1
read-write
0
No inversion
#0
1
Inverse RX input signal
#1
INV_TX
INV_TX\n
5
1
read-write
0
No inversion
#0
1
Inverse TX output signal
#1
TX_SELECT
TX_SELECT\n
1
1
read-write
0
IrDA receiver Enabled
#0
1
IrDA transmitter Enabled
#1
UA_ISR
UA_ISR
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUF_ERR_IF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows or Break Interrupt Flag or Parity Error Flag or Frame Error Flag (TX_OVER_IF or RX_OVER_IF or BIF or PEF or FEF) is set. When BUF_ERR_IF is set, the transfer is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.
5
1
read-only
BUF_ERR_INT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HW_BUF_ERR_IF
In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared.
21
1
read-only
HW_BUF_ERR_INT
In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1.\n
29
1
read-only
0
No buffer error interrupt is generated in DMA mode
#0
1
Buffer error interrupt is generated in DMA mode
#1
HW_MODEM_IF
In DMA Mode, MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
19
1
read-only
HW_MODEM_INT
In DMA Mode, MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)
This bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in DMA mode
#0
1
Modem interrupt is generated in DMA mode
#1
HW_RLS_IF
In DMA Mode, Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
18
1
read-only
HW_RLS_INT
In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1.\n
26
1
read-only
0
No RLS interrupt is generated in DMA mode
#0
1
RLS interrupt is generated in DMA mode
#1
HW_TOUT_IF
In DMA Mode, Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
20
1
read-only
HW_TOUT_INT
In DMA Mode, Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1.\n
28
1
read-only
0
No Tout interrupt is generated in DMA mode
#0
1
Tout interrupt is generated in DMA mode
#1
MODEM_IF
MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
3
1
read-only
MODEM_INT
MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDA_IF
Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDA_INT
Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLS_IF
Receive Line Interrupt Flag (Read Only).\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLS_INT
Receive Line Status Interrupt Indicator (Read Only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
1
1
read-only
THRE_INT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TOUT_IF
Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
4
1
read-only
TOUT_INT
Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
UA_LCR
UA_LCR
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of STOP bit
2
1
read-write
0
1 STOP bit
#0
1
2 STOP bits (1.5 STOP bits if WLS[1:0]=00)
#1
PBE
Parity Bit Enable\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable\n
5
1
read-write
0
Stick parity Disabled
#0
1
If bit 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0. If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
UA_MCR
UA_MCR
UART Modem Control Register\nReserved
0x10
-1
read-write
n
0x0
0x0
LEV_RTS
RTS Trigger Level (Not Available in UART2 Channel)\nThis bit can change the RTS trigger level.\n
9
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
RTS
RTS (Request-To-Send) Signal (Not Available in UART2 Channel)\n
1
1
read-write
0
Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered)
#0
1
Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered)
#1
RTS_ST
RTS Pin State (Read Only) (Not Available in UART2 Channel)\nThis bit is the output pin status of RTS.
13
1
read-only
UA_MSR
UA_MSR
UART Modem Status Register\nReserved
0x14
-1
read-write
n
0x0
0x0
CTS_ST
CTS Pin Status (Read Only) (Not Available in UART2 Channel)\nThis bit is the pin status of CTS.
4
1
read-only
DCTSF
Detect CTS State Change Flag (Read Only) (Not Available in UART2 Channel)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nWrite 1 to clear this bit to 0.
0
1
read-only
LEV_CTS
CTS Trigger Level (Not Available in UART2 Channel)\nThis bit can change the CTS trigger level.\n
8
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
UA_RBR
UA_RBR
UART Receive Buffer Register
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first).
0
8
read-only
UA_THR
UA_THR
UART Transmit Holding Register
UA_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first).
0
8
write-only
UA_TOR
UA_TOR
UART Time Out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value (NuMicro( NUC100/NUC120 Low Density Only)\nThis field is use to programming the transfer delay time between the last stop bit and next start bit.
8
8
read-write
TOIC
Time Out Interrupt Comparator\n
0
8
read-write
USB
USB Register Map
USB
0x0
0x0
0x1C
registers
n
0x20
0x60
registers
n
0x90
0x4
registers
n
ATTR
USB_ATTR
USB Bus Status and Attribution Register
0x10
-1
read-write
n
0x0
0x0
BYTEM
CPU access USB SRAM Size Mode Select\n
10
1
read-write
0
Word mode: The size of the transfer from CPU to USB SRAM can be Word only
#0
1
Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only
#1
DPPU_EN
Pull-up resistor on USB_DP enable\n
8
1
read-write
0
Pull-up resistor in USB_DP bus Disabled
#0
1
Pull-up resistor in USB_DP bus Active
#1
PHY_EN
PHY Transceiver Function Enable\n
4
1
read-write
0
PHY transceiver function Disabled
#0
1
PHY transceiver function Enabled
#1
PWRDN
Power-down PHY Transceiver, low active\n
9
1
read-write
0
Power-down related circuit of PHY transceiver
#0
1
Turn on related circuit of PHY transceiver
#1
RESUME
Resume Status\nIt is a read only bit.
2
1
read-write
0
No bus resume
#0
1
Resume from suspend
#1
RWAKEUP
Remote Wake-up\n
5
1
read-write
0
Release the USB bus from K state
#0
1
Force USB bus to K (USB_DP low, USB_DM: high) state, used for remote wake-up
#1
SUSPEND
Suspend Status\nIt is a read only bit.
1
1
read-write
0
Bus no suspend
#0
1
Bus idle more than 3ms, either cable is plugged off or host is sleeping
#1
TIMEOUT
Time Out Status\nIt is a read only bit.
3
1
read-write
0
No time-out
#0
1
No Bus response more than 18 bits time
#1
USBRST
USB Reset Status\nIt is a read only bit.
0
1
read-write
0
Bus no reset
#0
1
Bus reset when SE0 (single-ended 0) more than 2.5us
#1
USB_EN
USB Controller Enable\n
7
1
read-write
0
USB Controller Disabled
#0
1
USB Controller Enabled
#1
BUFSEG0
USB_BUFSEG0
Endpoint 0 Buffer Segmentation Register
0x20
read-write
n
0x0
0x0
BUFSEG
It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:\nUSB_SRAM address + { BUFSEG[8:3], 3'b000}\nRefer to the section 5.4.4.7 for the endpoint SRAM structure and its description.
3
6
read-write
BUFSEG1
USB_BUFSEG1
Endpoint 1 Buffer Segmentation Register
0x30
read-write
n
0x0
0x0
BUFSEG2
USB_BUFSEG2
Endpoint 2 Buffer Segmentation Register
0x40
read-write
n
0x0
0x0
BUFSEG3
USB_BUFSEG3
Endpoint 3 Buffer Segmentation Register
0x50
read-write
n
0x0
0x0
BUFSEG4
USB_BUFSEG4
Endpoint 4 Buffer Segmentation Register
0x60
read-write
n
0x0
0x0
BUFSEG5
USB_BUFSEG5
Endpoint 5 Buffer Segmentation Register
0x70
read-write
n
0x0
0x0
CFG0
USB_CFG0
Endpoint 0 Configuration Register
0x28
read-write
n
0x0
0x0
CSTALL
Clear STALL Response\n
9
1
read-write
0
Disable the device to clear the STALL handshake in setup stage
#0
1
Clear the device to response STALL handshake in setup stage
#1
DSQ_SYNC
Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the following IN token transaction. H/W will toggle automatically in IN token base on the bit.
7
1
read-write
0
DATA0 PID
#0
1
DATA1 PID
#1
EP_NUM
Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint
0
4
read-write
ISOCH
Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake.\n
4
1
read-write
0
No Isochronous endpoint
#0
1
Isochronous endpoint
#1
STATE
Endpoint STATE\n
5
2
read-write
0
Endpoint Disabled
#00
1
Out endpoint
#01
2
IN endpoint
#10
3
Undefined
#11
CFG1
USB_CFG1
Endpoint 1 Configuration Register
0x38
read-write
n
0x0
0x0
CFG2
USB_CFG2
Endpoint 2 Configuration Register
0x48
read-write
n
0x0
0x0
CFG3
USB_CFG3
Endpoint 3 Configuration Register
0x58
read-write
n
0x0
0x0
CFG4
USB_CFG4
Endpoint 4 Configuration Register
0x68
read-write
n
0x0
0x0
CFG5
USB_CFG5
Endpoint 5 Configuration Register
0x78
read-write
n
0x0
0x0
CFGP0
USB_CFGP0
Endpoint 0 Set Stall and Clear In/Out Ready Control Register
0x2C
read-write
n
0x0
0x0
CLRRDY
Clear Ready\nWhen the MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start, user can set this bit to 1 to turn it off and it is auto clear to 0.\nFor IN token, write '1' to clear the IN token had ready to transmit the data to USB.\nFor OUT token, write '1' to clear the OUT token had ready to receive the data from USB.\nThis bit writes 1 only and is always 0 when it was read back.
0
1
read-write
SSTALL
Set STALL\n
1
1
read-write
0
Disable the device to response STALL
#0
1
Set the device to respond STALL automatically
#1
CFGP1
USB_CFGP1
Endpoint 1 Set Stall and Clear In/Out Ready Control Register
0x3C
read-write
n
0x0
0x0
CFGP2
USB_CFGP2
Endpoint 2 Set Stall and Clear In/Out Ready Control Register
0x4C
read-write
n
0x0
0x0
CFGP3
USB_CFGP3
Endpoint 3 Set Stall and Clear In/Out Ready Control Register
0x5C
read-write
n
0x0
0x0
CFGP4
USB_CFGP4
Endpoint 4 Set Stall and Clear In/Out Ready Control Register
0x6C
read-write
n
0x0
0x0
CFGP5
USB_CFGP5
Endpoint 5 Set Stall and Clear In/Out Ready Control Register
0x7C
read-write
n
0x0
0x0
DRVSE0
USB_DRVSE0
USB Drive SE0 Control Register
0x90
-1
read-write
n
0x0
0x0
DRVSE0
Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_DP and USB_DM) are being pulled low.\n
0
1
read-write
0
None
#0
1
Force USB PHY transceiver to drive SE0
#1
EPSTS
USB_EPSTS
USB Endpoint Status Register
0xC
read-only
n
0x0
0x0
EPSTS0
Endpoint 0 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n
8
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS1
Endpoint 1 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n
11
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS2
Endpoint 2 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n
14
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS3
Endpoint 3 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n
17
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS4
Endpoint 4 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n
20
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS5
Endpoint 5 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n
23
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
OVERRUN
Overrun\nIt indicates that the received data is over the maximum payload number or not.\n
7
1
read-only
0
No overrun
#0
1
Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes
#1
FADDR
USB_FADDR
USB Device Function Address Register
0x8
read-write
n
0x0
0x0
FADDR
USB Device Function Address
0
7
read-write
FLDET
USB_FLDET
USB Floating Detected Register
0x14
read-only
n
0x0
0x0
FLDET
Device Floating Detected\n
0
1
read-only
0
Controller is not attached into the USB host
#0
1
Controller is attached into the BUS
#1
INTEN
USB_INTEN
USB Interrupt Enable Register
0x0
read-write
n
0x0
0x0
BUS_IE
Bus Event Interrupt Enable\n
0
1
read-write
0
BUS event interrupt Disabled
#0
1
BUS event interrupt Enabled
#1
FLDET_IE
Floating Detected Interrupt Enable\n
2
1
read-write
0
Floating detect Interrupt Disabled
#0
1
Floating detect Interrupt Enabled
#1
INNAK_EN
Active NAK Function and its Status in IN Token\n
15
1
read-write
0
NAK status is not updated into the endpoint status register when it was set to 0. It also disables the interrupt event when device responds to NAK after receiving IN token
#0
1
NAK status is updated into the endpoint status register, USB_EPSTS, when it is set to 1 and there is NAK response in IN token. It also enable the interrupt event when the device responds NAK after receiving IN token
#1
USB_IE
USB Event Interrupt Enable\n
1
1
read-write
0
USB event interrupt Disabled
#0
1
USB event interrupt Enabled
#1
WAKEUP_EN
Wake-up Function Enable\n
8
1
read-write
0
USB wake-up function Disabled
#0
1
USB wake-up function Enabled
#1
WAKEUP_IE
USB Wake-up Interrupt Enable\n
3
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
INTSTS
USB_INTSTS
USB Interrupt Event Status Register
0x4
read-write
n
0x0
0x0
BUS_STS
BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus.\n
0
1
read-write
0
No BUS event occurred
#0
1
Bus event occurred check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS[0]
#1
EPEVT0
Endpoint 0's USB Event Status\n
16
1
read-write
0
No event occurred in endpoint 0
#0
1
USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[16] or USB_INTSTS[1]
#1
EPEVT1
Endpoint 1's USB Event Status\n
17
1
read-write
0
No event occurred in endpoint 1
#0
1
USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[17] or USB_INTSTS[1]
#1
EPEVT2
Endpoint 2's USB Event Status\n
18
1
read-write
0
No event occurred in endpoint 2
#0
1
USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1]
#1
EPEVT3
Endpoint 3's USB Event Status\n
19
1
read-write
0
No event occurred in endpoint 3
#0
1
USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[19] or USB_INTSTS[1]
#1
EPEVT4
Endpoint 4's USB Event Status\n
20
1
read-write
0
No event occurred in endpoint 4
#0
1
USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[20] or USB_INTSTS[1]
#1
EPEVT5
Endpoint 5's USB Event Status\n
21
1
read-write
0
No event occurred in endpoint 5
#0
1
USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[21] or USB_INTSTS[1]
#1
FLDET_STS
Floating Detected Interrupt Status\n
2
1
read-write
0
There is not attached/detached event in the USB
#0
1
There is attached/detached event in the USB bus and it is cleared by write 1 to USB_INTSTS[2]
#1
SETUP
Setup Event Status\n
31
1
read-write
0
No Setup event
#0
1
Setup event occurred, cleared by write 1 to USB_INTSTS[31]
#1
USB_STS
USB event Interrupt Status\nThe USB event includes the Setup Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.\n
1
1
read-write
0
No USB event occurred
#0
1
USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[1] or EPSTS0~5 and SETUP (USB_INTSTS[31])
#1
WAKEUP_STS
Wake-up Interrupt Status\n
3
1
read-write
0
No Wake-up event occurred
#0
1
Wake-up event occurred, cleared by write 1 to USB_INTSTS[3]
#1
MXPLD0
USB_MXPLD0
Endpoint 0 Maximal Payload Register
0x24
read-write
n
0x0
0x0
MXPLD
Maximal Payload
Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
(1) When the register is written by CPU,
For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
(2) When the register is read by CPU,
For IN token, the value of MXPLD is indicated by the data length be transmitted to host.
For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
0
9
read-write
MXPLD1
USB_MXPLD1
Endpoint 1 Maximal Payload Register
0x34
read-write
n
0x0
0x0
MXPLD2
USB_MXPLD2
Endpoint 2 Maximal Payload Register
0x44
read-write
n
0x0
0x0
MXPLD3
USB_MXPLD3
Endpoint 3 Maximal Payload Register
0x54
read-write
n
0x0
0x0
MXPLD4
USB_MXPLD4
Endpoint 4 Maximal Payload Register
0x64
read-write
n
0x0
0x0
MXPLD5
USB_MXPLD5
Endpoint 5 Maximal Payload Register
0x74
read-write
n
0x0
0x0
STBUFSEG
USB_STBUFSEG
Setup Token Buffer Segmentation Register
0x18
read-write
n
0x0
0x0
STBUFSEG
It is used to indicate the offset address for the Setup token with the USB SRAM starting address. The effective starting address is\nUSB_SRAM address + { STBUFSEG[8:3], 3'b000} \nNote: It is used for Setup token only.
3
6
read-write
WDT
WDT Register Map
WDT
0x0
0x0
0x4
registers
n
WTCR
WTCR
Watchdog Timer Control Register
0x0
-1
read-write
n
0x0
0x0
DBGACK_WDT
ICE Debug Mode Acknowledge Disable (Write-protection Bit)\nWatchdog Timer counter will keep going no matter ICE debug mode acknowledged or not.
31
1
read-write
0
ICE debug mode acknowledgement affects Watchdog Timer counting
#0
1
ICE debug mode acknowledgement disabled
#1
WTE
Watchdog Timer Enable (Write-protection Bit)\n
7
1
read-write
0
Watchdog timer Disabled (This action will reset the internal counter)
#0
1
Watchdog timer Enabled
#1
WTIE
Watchdog Timer Interrupt Enable (Write-protection Bit)\n
6
1
read-write
0
Watchdog timer interrupt Disabled
#0
1
Watchdog timer interrupt Enabled
#1
WTIF
Watchdog Timer Interrupt Flag\nIf the Watchdog timer interrupt is enabled, this bit will be set to indicate that Watchdog timer interrupt has occurred.\nNote: This bit is cleared by writing 1 to this bit.
3
1
read-write
0
Watchdog timer interrupt did not occur
#0
1
Watchdog timer interrupt occurred
#1
WTIS
Watchdog Timer Interval Selection (Write-protection Bits)\n
8
3
read-write
WTR
Clear Watchdog Timer (Write-protection Bit)\nSet this bit will clear the Watchdog timer.\nNote: This bit will be automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Reset the contents of the Watchdog timer
#1
WTRE
Watchdog Timer Reset Enable (Write-protection Bit)\nSetting this bit will enable the Watchdog timer reset function.\n
1
1
read-write
0
Watchdog timer reset function Disabled
#0
1
Watchdog timer reset function Enabled
#1
WTRF
Watchdog Timer Reset Flag\nWhen the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If WTRE is disabled, then the Watchdog timer has no effect on this bit.\nNote: This bit is cleared by writing 1 to this bit.
2
1
read-write
0
Watchdog timer reset did not occur
#0
1
Watchdog timer reset occurred
#1
WTWKE
Watchdog Timer Wake-up Function Enable bit (Write-protection Bit)\nNote: Chip can be woken up by WDT only if WDT clock source selects RC10K.
4
1
read-write
0
Watchdog timer Wake-up chip function Disabled
#0
1
Wake-up function Enabled so that Watchdog timer timeout can wake-up chip from Power-down mode
#1
WTWKF
Watchdog Timer Wake-up Flag\nIf Watchdog timer causes chip wakes up from Power-down mode, this bit will be set to high. It must be cleared by software with a write 1 to this bit.\n
5
1
read-write
0
Watchdog timer does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode by Watchdog timeout
#1