nuvoTon NUC122_v1 2024.05.01 NUC122_v1 SVD file 8 32 CLK CLK Register Map CLK 0x0 0x0 0x1C registers n 0x20 0x4 registers n AHBCLK AHBCLK AHB Devices Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 ISP_EN Flash ISP Controller Clock Enable Control 2 1 read-write 0 Disable the Flash ISP engine clock #0 1 Enable the Flash ISP engine clock #1 APBCLK APBCLK APB Devices Clock Enable Control Register 0x8 read-write n 0x0 0x0 I2C1_EN I2C1 Clock Enable 9 1 read-write 0 Disable I2C1 clock #0 1 Enable I2C1 clock #1 PS2_EN PS2 Clock Enable 31 1 read-write 0 Disable PS/2 clock #0 1 Enable PS/2 clock #1 PWM01_EN PWM_01 Clock Enable 20 1 read-write 0 Disable PWM01 clock #0 1 Enable PWM01 clock #1 PWM23_EN PWM_23 Clock Enable 21 1 read-write 0 Disable PWM23 clock #0 1 Enable PWM23 clock #1 RTC_EN Real-Time-Clock APB interface Clock Enable\nThis bit is used to control the RTC APB clock only, The RTC engine clock source is from the 32768 Hz crystal. 1 1 read-write 0 Disable RTC clock #0 1 Enable RTC clock #1 SPI0_EN SPI0 Clock Enable 12 1 read-write 0 Disable SPI0 clock #0 1 Enable SPI0 clock #1 SPI1_EN SPI1 Clock Enable 13 1 read-write 0 Disable SPI1 clock #0 1 Enable SPI1 clock #1 TMR0_EN Timer0 Clock Enable 2 1 read-write 0 Disable Timer0 clock #0 1 Enable Timer0 clock #1 TMR1_EN Timer1 Clock Enable 3 1 read-write 0 Disable Timer1 clock #0 1 Enable Timer1 clock #1 TMR2_EN Timer2 Clock Enable 4 1 read-write 0 Disable Timer2 clock #0 1 Enable Timer2 clock #1 TMR3_EN Timer3 Clock Enable 5 1 read-write 0 Disable Timer3 clock #0 1 Enable Timer3 clock #1 UART0_EN UART0 Clock Enable 16 1 read-write 0 Disable UART0 clock #0 1 Enable UART0 clock #1 UART1_EN UART1 Clock Enable 17 1 read-write 0 Disable UART1 clock #0 1 Enable UART1 clock #1 USBD_EN USB 2.0 FS Device Controller Clock Enable 27 1 read-write 0 Disable USB clock #0 1 Enable USB clock #1 WDT_EN Watchdog Timer Clock Enable (write-protection bit) This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 0 1 read-write 0 Disable Watchdog Timer clock #0 1 Enable Watchdog Timer clock #1 CLKDIV CLKDIV Clock Divider Register 0x18 read-write n 0x0 0x0 HCLK_N HCLK Clock Divider from HCLK Clock Source 0 4 read-write UART_N UART Clock Divider from UART Clock Source 8 4 read-write USB_N USB Clock Divider from PLL Clock Source 4 4 read-write CLKSEL0 CLKSEL0 Clock Source Selection Control Register 0 0x10 -1 read-write n 0x0 0x0 HCLK_S HCLK Clock Source Selection (write-protection bits) Note: Before clock switching, the related clock sources (both pre-select and new-select) must be turn on The 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b. These bits are protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 0 3 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #000 1 Clock source from external 32.768 KHz low speed crystal clock #001 2 Clock source from PLL clock #010 3 Clock source from internal 10 KHz low speed oscillator clock #011 7 Clock source from internal 22.1184 MHz high speed oscillator clock #111 STCLK_S Cortex-M0 SysTick Clock Source Selection (write-protection bits) 3 3 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #000 1 Clock source from external 32.768 KHz low speed crystal clock #001 2 Clock source from external 4~24 MHz high speed crystal clock/2 #010 3 Clock source from HCLK/2 #011 7 Clock source from internal 22.1184 MHz high speed oscillator clock/2 #111 CLKSEL1 CLKSEL1 Clock Source Selection Control Register 1 0x14 -1 read-write n 0x0 0x0 PWM01_S PWM0 and PWM1 Clock Source Selection\nPWM0 and PWM1 uses the same Engine clock source, both of them use the same prescaler 28 2 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #00 1 Clock source from external 32.768 KHz low speed crystal clock #01 2 Clock source from HCLK #10 3 Clock source from internal 22.1184 MHz high speed oscillator clock #11 PWM23_S PWM2 and PWM3 Clock Source Selection\nPWM2 and PWM3 uses the same Engine clock source, both of them use the same prescaler 30 2 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #00 1 Clock source from external 32.768 KHz low speed crystal clock #01 2 Clock source from HCLK #10 3 Clock source from internal 22.1184 MHz high speed oscillator clock #11 TMR0_S TIMER0 Clock Source Selection 8 3 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #000 1 Clock source from external 32.768 KHz low speed crystal clock #001 2 Clock source from HCLK #010 3 Reserved #011 7 Clock source from internal 22.1184 MHz high speed oscillator clock #111 TMR1_S TIMER1 Clock Source Selection 12 3 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #000 1 Clock source from external 32.768 KHz low speed crystal clock #001 2 Clock source from HCLK #010 3 Reserved #011 7 Clock source from internal 22.1184 MHz high speed oscillator clock #111 TMR2_S TIMER2 Clock Source Selection 16 3 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #000 1 Clock source from external 32.768 KHz low speed crystal clock #001 2 Clock source from HCLK #010 3 Reserved #011 7 Clock source from internal 22.1184 MHz high speed oscillator clock #111 TMR3_S TIMER3 Clock Source Selection 20 3 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #000 1 Clock source from external 32.768 KHz low speed crystal clock #001 2 Clock source from HCLK #010 3 Reserved #011 7 Clock source from internal 22.1184 MHz high speed oscillator clock #111 UART_S UART Clock Source Selection 24 2 read-write 0 Clock source from external 4~24 MHz high speed crystal clock #00 1 Clock source from PLL clock #01 3 Clock source from internal 22.1184 MHz high speed oscillator clock #11 WDT_S Watchdog Timer Clock Source Selection (write-protection bits) These bits are protected-bit, program this need to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 0 2 read-write 0 Reserved #00 1 Reserved #01 2 Clock source from HCLK/2048 clock #10 3 Clock source from internal 10 KHz low speed oscillator clock #11 CLKSTATUS CLKSTATUS Clock Status Monitor Register 0xC read-write n 0x0 0x0 CLK_SW_FAIL Clock Switching Fail Flag (write-protection bit)\nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nWrite 1 to clear the bit to zero. 7 1 read-write 0 Clock switching success #0 1 Clock switching failure #1 OSC10K_STB Internal 10 KHz Low Speed Oscillator Clock Source Stable Flag\nThis is read only bit 3 1 read-write 0 Internal 10 KHz low speed oscillator clock is not stable or disabled #0 1 Internal 10 KHz low speed oscillator clock is stable #1 OSC22M_STB Internal 22.1184 MHz High Speed Oscillator Clock Source Stable Flag\nThis is read only bit 4 1 read-write 0 Internal 22.1184 MHz high speed oscillator clock is not stable or disabled #0 1 Internal 22.1184 MHz high speed oscillator clock is stable #1 PLL_STB Internal PLL Clock Source Stable Flag\nThis is read only bit 2 1 read-write 0 Internal PLL clock is not stable or disabled #0 1 Internal PLL clock is stable #1 XTL12M_STB External 4~24 MHz High Speed Crystal Clock Source Stable Flag\nThis is read only bit 0 1 read-write 0 External 4~24 MHz high speed crystal clock is not stable or disabled #0 1 External 4~24 MHz high speed crystal clock is stable #1 XTL32K_STB External 32.768 KHz Low Speed Crystal Clock Source Stable Flag\nThis is read only bit 1 1 read-write 0 External 32.768 KHz low speed crystal clock is not stable or disabled #0 1 External 32.768 KHz low speed crystal clock is stable #1 PLLCON PLLCON PLL Control Register 0x20 -1 read-write n 0x0 0x0 BP PLL Bypass Control 17 1 read-write 0 PLL is in normal mode (default) #0 1 PLL clock output is same as clock input (XTALin) #1 FB_DV PLL Feedback Divider\nRefer to the formulas below the table. 0 9 read-write IN_DV PLL Input Divider \nRefer to the formulas below the table. 9 5 read-write OE PLL OE (FOUT enable) 18 1 read-write 0 PLL FOUT enable #0 1 PLL FOUT is fixed low #1 OUT_DV PLL Output Divider \nRefer to the formulas below the table. 14 2 read-write PD Power Down Mode\nIf set the PWR_DOWN_EN bit to 1 in PWRCON register, the PLL will enter power down mode too. 16 1 read-write 0 PLL is in normal mode #0 1 PLL is in power down mode (default) #1 PLL_SRC PLL Source Clock Selection 19 1 read-write 0 PLL source clock from external 4~24 MHz high speed crystal #0 1 PLL source clock from internal 22.1184 MHz high speed oscillator #1 PWRCON PWRCON System Power Down Control Register 0x0 -1 read-write n 0x0 0x0 OSC10K_EN Internal 10 KHz Low Speed Oscillator Enable (write-protection bit) 3 1 read-write 0 Disable 10 KHz low speed oscillator #0 1 Enable 10 KHz low speed oscillator #1 OSC22M_EN Internal 22.1184 MHz High Speed Oscillator Enable (write-protection bit) 2 1 read-write 0 Disable 22.1184 MHz high speed oscillator #0 1 Enable 22.1184 MHz high speed oscillator #1 PD_WAIT_CPU This Bit Control the Power Down Entry Condition (write-protection bit) 8 1 read-write 0 Chip entry power down mode when the PWR_DOWN_EN bit is set to 1 #0 1 Chip enter power down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction #1 PD_WU_DLY Wake-Up Delay Counter Enable (write-protection bit)\nWhen the chip be woken-up from power down mode, the clock control will delay certain clock cycles to wait system clock is stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at 22.1184 MHz high speed oscillator. 4 1 read-write 0 Disable clock cycles delay #0 1 Enable clock cycles delay #1 PD_WU_INT_EN Power Down Mode Wake-Up Interrupt Enable (write-protection bit)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high. 5 1 read-write 0 Disable #0 1 Enable #1 PD_WU_STS Power Down Mode Wake-Up Interrupt Status Set by power down wake-up event , it indicates that resume from power down mode The flag is set if the GPIO, USB, UART, WDT, BOD or RTC wake-up occurred Write 1 to clear the bit to zero. Note: This bit is effective only if PD_WU_INT_EN (PWRCON[5]) be set to 1. 6 1 read-write PWR_DOWN_EN System Power Down Enable (write-protection bit)\nWhen this bit is set to 1, the chip power down mode is enabled and chip power down behavior will depends on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0, then the chip enters power down mode immediately after the PWR_DOWN_EN bit set.\n(b) if the PD_WAIT_CPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters power down mode\nWhen chip be woken-up from power down mode, this bit is auto cleared. Users need to set this bit again for next power down.\nWhen in power down mode, external 4~24 MHz high speed crystal and the 22.1184 MHz high speed OSC will be disabled in this mode, but the 32.768 KHz low speed crystal and 10 KHz low speed OSC is not controlled by power down mode.\nWhen in power down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by power down mode, if the peripheral clock source is from 32.768 KHz low speed crystal or the 10 KHz low speed oscillator. 7 1 read-write 0 Chip is operating normally or chip is in idle mode because of WFI command #0 1 Chip enters the power down mode instant or wait CPU sleep command WFI #1 XTL12M_EN External 4~24 MHz High Speed Crystal Enable (write-protection bit)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically 0 1 read-write 0 Disable external 4~24 MHz high speed crystal #0 1 Enable external 4~24 MHz high speed crystal #1 XTL32K_EN External 32.768 KHz Low Speed Crystal Enable (write-protection bit) 1 1 read-write 0 Disable 32.768 KHz low speed crystal #0 1 Enable 32.768 KHz low speed crystal (Normal operation) #1 FMC FMC Register Map FMC 0x0 0x0 0x14 registers n 0x18 0x4 registers n FATCON FATCON Flash Access Window Control Register 0x18 read-write n 0x0 0x0 LFOM Low Frequency Optimization Mode (write-protection bit) If chip operation frequency lower than 20 MHz, chip can work more efficiently when this bit is set to 1. If chip operation frequency is 40 MHz, both of LFOM and MFOM have to set to zero. 4 1 read-write MFOM Middle Frequency Optimization Mode (write-protection bit) If chip operation frequency is between 20 MHz ~ 40 MHz, chip can work more efficiently when this bit is set to 1. If chip operation frequency is 40 MHz, both of LFOM and MFOM have to set to zero. 6 1 read-write ISPADR ISPADR ISP Address Register 0x4 read-write n 0x0 0x0 ISPADR ISP Address\nNuMicro( NUC122 Series equips with a maximum 16Kx32 embedded flash, it supports word program only. ISPADR[1:0] must be kept 00b for ISP operation. 0 32 read-write ISPCMD ISPCMD ISP Command Register 0xC read-write n 0x0 0x0 FCEN ISP Command 4 1 read-write FCTRL ISP Command 0 4 read-write FOEN ISP Command 5 1 read-write ISPCON ISPCON ISP Control Register 0x0 read-write n 0x0 0x0 BS Boot Select (write-protection bit)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened. 1 1 read-write 0 boot from APROM #0 1 boot from LDROM #1 CFGUEN Enable Config-bits Update by ISP (write-protection bit) 4 1 read-write 0 Disable ISP can update config-bits #0 1 Enable ISP can update config-bits #1 ET Flash Erase Time (write-protection bits) 12 3 read-write ISPEN ISP Enable (write-protection bit)\nISP function enable bit. Set this bit to enable ISP function. 0 1 read-write 0 Disable ISP function #0 1 Enable ISP function #1 ISPFF ISP Fail Flag (write-protection bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself \n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear. 6 1 read-write LDUEN LDROM Update Enable (write-protection bit)\nLDROM update enable bit. 5 1 read-write 0 LDROM can not be updated #0 1 LDROM can be updated when the chip runs in APROM #1 PT Flash Program Time (write-protection bits) 8 3 read-write ISPDAT ISPDAT ISP Data Register 0x8 read-write n 0x0 0x0 ISPDAT ISP Data\nWrite data to this register before ISP program operation\nRead data from this register after ISP read operation 0 32 read-write ISPTRG ISPTRG ISP Trigger Control Register 0x10 read-write n 0x0 0x0 ISPGO ISP Start Trigger\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 0 1 read-write 0 ISP operation is finished #0 1 ISP is on going #1 GCR GCR Register Map GCR 0x0 0x0 0x10 registers n 0x100 0x4 registers n 0x18 0x4 registers n 0x24 0x4 registers n 0x30 0x10 registers n 0x50 0x4 registers n ALT_MFP ALT_MFP Alternative Multiple Function Pin Control Register 0x50 read-write n 0x0 0x0 ALT_MFP14_2 They are necessary to set 0 2 13 read-write ALT_MFP15 The PB.4 pin function depends on GPB_MFP4 and ALT_MFP[15]. 15 1 read-write ALT_MFP21_16 They are necessary to set 0 16 6 read-write PB10_S01 Bits PB10_S01 and GPB_MFP[10] determine the PB.10 function. 0 1 read-write PB9_S11 Bits PB9_S11 and GPB_MFP[9] determine the PB.9 function. 1 1 read-write BODCR BODCR Brownout Detector Control Register 0x18 -1 read-write n 0x0 0x0 BOD_EN Brownout Detector Enable (write-protection bit) The default value is set by flash controller user configuration register config0 bit[23] This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 0 1 read-write 0 Brownout Detector function is disabled #0 1 Brownout Detector function is enabled #1 BOD_INTF Brownout Detector Interrupt Flag\nSoftware can write 1 to clear this bit to zero. 4 1 read-write 0 Brownout Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting #0 1 When Brownout Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the brownout interrupt is requested if brownout interrupt is enabled #1 BOD_LPM Brownout Detector Low Power Mode (write-protection bit) The BOD consumes about 100 uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 5 1 read-write 0 BOD operate in normal mode (default) #0 1 Enable the BOD low power mode #1 BOD_OUT Brownout Detector Output Status 6 1 read-write 0 Brownout Detector output status is 0. It means the detected voltage is higher than BOD_VL setting or BOD_EN is 0 #0 1 Brownout Detector output status is 1. It means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled , this bit always responds 0 #1 BOD_RSTEN Brownout Reset Enable (write-protection bit) While the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low). The default value is set by flash controller user configuration register config0 bit[20]. This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 3 1 read-write 0 Enable the brownout INTERRUPT function #0 1 Enable the brownout RESET function #1 BOD_VL Brownout Detector Threshold Voltage Selection (write-protection bits) 1 2 read-write LVR_EN Low Voltage Reset Enable (write-protection bit) The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default. This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100 7 1 read-write 0 Disabled Low Voltage Reset function #0 1 Enabled Low Voltage Reset function - After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable. (default) #1 GPA_MFP GPA_MFP GPIOA Multiple Function and Input Type Control Register 0x30 read-write n 0x0 0x0 GPA_MFP10 PA.10 Pin Function Selection 10 1 read-write GPA_MFP11 PA.11 Pin Function Selection 11 1 read-write GPA_MFP12 PA.12 Pin Function Selection 12 1 read-write GPA_MFP13 PA.13 Pin Function Selection 13 1 read-write GPA_MFP14 PA.14 Pin Function Selection 14 1 read-write GPA_MFP15 PA.15 Pin Function Selection 15 1 read-write GPA_TYPEn GPA[9:0] are reserved 16 16 read-write 0 Disable GPIOA[15:0] I/O input Schmitt Trigger function 0 1 Enable GPIOA[15:0] I/O input Schmitt Trigger function 1 GPB_MFP GPB_MFP GPIOB Multiple Function and Input Type Control Register 0x34 read-write n 0x0 0x0 GPB_MFP0 PB.0 Pin Function Selection 0 1 read-write 0 The GPIOB[0] is selected to the pin PB.0 #0 1 The UART0 RXD function is selected to the pin PB.0 #1 GPB_MFP1 PB.1 Pin Function Selection 1 1 read-write 0 The GPIOB[1] is selected to the pin PB.1 #0 1 The UART0 TXD function is selected to the pin PB.1 #1 GPB_MFP10 PB.10 Pin Function Selection 10 1 read-write GPB_MFP14 PB.14 Pin Function Selection 14 1 read-write GPB_MFP15 PB.15 Pin Function Selection 15 1 read-write GPB_MFP2 PB.2 Pin Function Selection 2 1 read-write GPB_MFP3 PB.3 Pin Function Selection 3 1 read-write GPB_MFP4 PB.4 Pin Function Selection 4 1 read-write 0 The GPIOB[4] is selected to the pin PB.4 #0 1 The UART1 RXD function is selected to the pin PB.4 #1 GPB_MFP5 PB. 5 Pin Function Selection 5 1 read-write 0 The GPIOB[5] is selected to the pin PB.5 #0 1 The UART1 TXD function is selected to the pin PB.5 #1 GPB_MFP6 PB.6 Pin Function Selection 6 1 read-write GPB_MFP7 PB.7 Pin Function Selection 7 1 read-write GPB_MFP8 PB.8 Pin Function Selection 8 1 read-write GPB_MFP9 PB.9 Pin Function Selection 9 1 read-write GPB_TYPEn GPB[13:11],are reserved 16 16 read-write 0 Disable GPIOB[15:0] I/O input Schmitt Trigger function 0 1 Enable GPIOB[15:0] I/O input Schmitt Trigger function 1 GPC_MFP GPC_MFP GPIOC Multiple Function and Input Type Control Register 0x38 read-write n 0x0 0x0 GPC_MFP0 PC.0 Pin Function Selection 0 1 read-write GPC_MFP1 PC.1 Pin Function Selection 1 1 read-write GPC_MFP10 PC.10 Pin Function Selection 10 1 read-write GPC_MFP11 PC.11 Pin Function Selection 11 1 read-write GPC_MFP12 PC.12 Pin Function Selection\nBoth GPC_MFP[12] and ALT_MFP[13] are needed to set 0 for GPIOC[12] function on PC.12. 12 1 read-write GPC_MFP13 PC.13 Pin Function Selection\nBoth GPC_MFP[13] and ALT_MFP[21] are needed to set 0 for GPIOC[13] function on PC.13. 13 1 read-write GPC_MFP2 PC.2 Pin Function Selection 2 1 read-write GPC_MFP3 PC.3 Pin Function Selection 3 1 read-write GPC_MFP4 PC.4 Pin Function Selection\nGPC_MFP[4] is needed to set 0 for GPIOC[4] function on PC.4. 4 1 read-write GPC_MFP5 PC.5 Pin Function Selection\nGPC_MFP[5] is needed to set 0 for GPIOC[5] function on PC.5. 5 1 read-write GPC_MFP8 PC.8 Pin Function Selection 8 1 read-write GPC_MFP9 PC.9 Pin Function Selection 9 1 read-write GPC_TYPEn GPC[15:14], GPC[7:6] are reserved 16 16 read-write 0 Disable GPIOC[15:0] I/O input Schmitt Trigger function 0 1 Enable GPIOC[15:0] I/O input Schmitt Trigger function 1 GPD_MFP GPD_MFP GPIOD Multiple Function and Input Type Control Register 0x3C read-write n 0x0 0x0 GPD_MFP0 PD.0 Pin Function Selection\nGPD_MFP[0] is needed to set 0 for GPIOD[0] function on PD.0 0 1 read-write GPD_MFP1 PD.1 Pin Function Selection 1 1 read-write 0 The GPIOD[1] is selected to the pin PD.1 #0 1 The SPI0 SS01 function is selected to the pin PD.1(the validity of this function is depended on part no) #1 GPD_MFP10 PD.10 Pin Function Selection \nBoth GPD_MFP[10] and ALT_MFP[20] are needed to set 0 for GPIOD[10] function on PD.10 10 1 read-write GPD_MFP11 PD.11 Pin Function Selection\nBoth GPD_MFP[11] and ALT_MFP[21] are needed to set 0 for GPIOD[11] function on PD.11 11 1 read-write GPD_MFP2 PD.2 Pin Function Selection\nGPD_MFP[2] is needed to set 0 for GPIOD[2] function on PD.2 2 1 read-write GPD_MFP3 PD.3 Pin Function Selection\nGPD_MFP[3] is needed to set 0 for GPIOD[3] function on PD.3 3 1 read-write GPD_MFP4 PD.4 Pin Function Selection\nGPD_MFP[4] is needed to set 0 for GPIOD[4] function on PD.4 4 1 read-write GPD_MFP5 PD.5 Pin Function Selection\nGPD_MFP[5] is needed to set 0 for GPIOD[5] function on PD.5 5 1 read-write GPD_MFP8 PD.8 Pin Function Selection \nBoth GPD_MFP[8] and ALT_MFP[18] are needed to set 0 for GPIOD[8] function on PD.8 8 1 read-write GPD_MFP9 PD.9 Pin Function Selection\nBoth GPD_MFP[9] and ALT_MFP[19] are needed to set 0 for GPIOD[9] function on PD.9 9 1 read-write GPD_TYPEn GPIOD[15:12], GPIOD[7:6] are reserved 16 16 read-write 0 Disable GPIOD[15:0] I/O input Schmitt Trigger function 0 1 Enable GPIOD[15:0] I/O input Schmitt Trigger function 1 IPRSTC1 IPRSTC1 Peripheral Reset Control Register 1 0x8 read-write n 0x0 0x0 CHIP_RST CHIP One Shot Reset (write-protection bit) Setting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIP_RST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. About the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2 This bit is the protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100 0 1 read-write 0 CHIP normal operation #0 1 CHIP one shot reset #1 CPU_RST CPU Kernel One Shot Reset (write-protection bit) Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100 1 1 read-write 0 CPU normal operation #0 1 CPU one shot reset #1 IPRSTC2 IPRSTC2 Peripheral Reset Control Register 2 0xC read-write n 0x0 0x0 GPIO_RST GPIO Controller Reset 1 1 read-write 0 GPIO controller normal operation #0 1 GPIO controller reset #1 I2C1_RST I2C1 Controller Reset 9 1 read-write 0 I2C1 controller normal operation #0 1 I2C1 controller reset #1 PS2_RST PS/2 Controller Reset 23 1 read-write 0 PS/2 controller normal operation #0 1 PS/2 controller reset #1 PWM03_RST PWM03 Controller Reset 20 1 read-write 0 PWM03 controller normal operation #0 1 PWM03 controller reset #1 SPI0_RST SPI0 Controller Reset 12 1 read-write 0 SPI0 controller normal operation #0 1 SPI0 controller reset #1 SPI1_RST SPI1 Controller Reset 13 1 read-write 0 SPI1 controller normal operation #0 1 SPI1 controller reset #1 TMR0_RST Timer0 Controller Reset 2 1 read-write 0 Timer0 controller normal operation #0 1 Timer0 controller reset #1 TMR1_RST Timer1 Controller Reset 3 1 read-write 0 Timer1 controller normal operation #0 1 Timer1 controller reset #1 TMR2_RST Timer2 Controller Reset 4 1 read-write 0 Timer2 controller normal operation #0 1 Timer2 controller reset #1 TMR3_RST Timer3 Controller Reset 5 1 read-write 0 Timer3 controller normal operation #0 1 Timer3 controller reset #1 UART0_RST UART0 Controller Reset 16 1 read-write 0 UART0 controller normal operation #0 1 UART0 controller reset #1 UART1_RST UART1 Controller Reset 17 1 read-write 0 UART1 controller normal operation #0 1 UART1 controller reset #1 USBD_RST USB Device Controller Reset 27 1 read-write 0 USB device controller normal operation #0 1 USB device controller reset #1 PDID PDID Part Device Identification Number Register 0x0 -1 read-only n 0x0 0x0 PDID Part Device Identification Number\nThis register reflects device part number code. S/W can read this register to identify which device is used. 0 32 read-only PORCR PORCR Power-On Reset Control Register 0x24 read-write n 0x0 0x0 POR_DIS_CODE The register is used for the Power-On Reset enable control (write-protection bits) When power on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: /RESET pin, Watchdog Timer Time-Out reset, LVR reset, BOD reset, ICE reset command and the software-chip reset function This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 0 16 read-write REGWRPROT REGWRPROT Register Write-Protection Control Register 0x100 read-write n 0x0 0x0 REGPROTDIS Register Write-Protection Disable Index (Read only)\nThe Protected registers are:\nIPRSTC1: address 0x5000_0008\nBODCR: address 0x5000_0018\nPORCR: address 0x5000_0024\nPWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) \nAPBCLK bit[0]: address 0x5000_0208 (bit[0] is Watchdog Timer clock enable)\nCLK_SEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select)\nCLK_SEL1 bit[1:0]: address 0x5000_0214 (for Watchdog Timer clock source select)\nNMI_SEL bit[7]: address 0x5000_0380 (for interrupt test mode)\nISPCON: address 0x5000_C000 (Flash ISP Control register)\nWTCR: address 0x4000_4000\nFATCON: address 0x5000_C018 0 1 read-only 0 Write-protection is enabled for writing protected registers. Any write to the protected register is ignored #0 1 Write-protection is disabled for writing protected registers #1 REGWRPROT Register Write-Protection Code (Write only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write. 0 8 write-only RSTSRC RSTSRC System Reset Source Register 0x4 read-write n 0x0 0x0 RSTS_BOD The RSTS_BOD flag is set by the reset signal from the Brownout Detector to indicate the previous reset source. Software can write 1 to clear this bit to zero. 4 1 read-write 0 No reset from BOD #0 1 The BOD had issued the reset signal to reset the system #1 RSTS_CPU The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).\nSoftware can write 1 to clear this bit to zero. 7 1 read-write 0 No reset from CPU #0 1 The Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1 #1 RSTS_LVR The RSTS_LVR flag is set by the reset signal from the Low-Voltage-Reset controller to indicate the previous reset source. Software can write 1 to clear this bit to zero. 3 1 read-write 0 No reset from LVR #0 1 The LVR controller had issued the reset signal to reset the system #1 RSTS_POR The RSTS_POR flag is set by the reset signal from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source. Software can write 1 to clear this bit to zero. 0 1 read-write 0 No reset from POR or CHIP_RST #0 1 The Power-On Reset (POR) or CHIP_RST had issued the reset signal to reset the system #1 RSTS_RESET The RSTS_RESET flag is set by the reset signal from the /RESET pin to indicate the previous reset source. Software can write 1 to clear this bit to zero. 1 1 read-write 0 No reset from /RESET pin #0 1 The Pin /RESET had issued the reset signal to reset the system #1 RSTS_SYS The RSTS_SYS flag is set by the reset signal from the Cortex-M0 kernel to indicate the previous reset source. Software can write 1 to clear this bit to zero. 5 1 read-write 0 No reset from Cortex-M0 #0 1 The Cortex-M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 kernel #1 RSTS_WDT The RSTS_WDT flag is set by the reset signal from the Watchdog Timer to indicate the previous reset source. Software can write 1 to clear this bit to zero. 2 1 read-write 0 No reset from Watchdog Timer #0 1 The Watchdog Timer had issued the reset signal to reset the system #1 GP GPIO Register Map GPIO 0x0 0x0 0x24 registers n 0x180 0x4 registers n 0x200 0x100 registers n 0x40 0x24 registers n 0x80 0x24 registers n 0xC0 0x24 registers n DBNCECON DBNCECON De-bounce Cycle Control 0x180 -1 read-write n 0x0 0x0 DBCLKSEL De-bounce Sampling Cycle Selection 0 4 read-write DBCLKSRC De-bounce Counter Clock Source Selection 4 1 read-write 0 De-bounce counter clock source is the HCLK #0 1 De-bounce counter clock source is the internal 10 KHz low speed clock #1 ICLK_ON Interrupt Clock On Mode\nSet this bit to 0 will disable the interrupt generate circuit clock, if the pin[n] interrupt is disabled 5 1 read-write 0 Disable the clock if the GPIOA/B/C/D[n] interrupt is disabled #0 1 Interrupt generated circuit clock always enable #1 GPIOA0_DOUT GPIOA0_DOUT GPIO PA.0 Bit Output/Input Value 0x200 read-write n 0x0 0x0 GPIOxx_DOUT GPIOxx I/O Pin Bit Output/Input Control\nWrite this bit can control one GPIO pin output value\nRead this register to get IO pin status.\nFor example: write GPIOA0_DOUT will reflect the written value to bit GPIOA_DOUT[0], read GPIOA0_DOUT will return the value of GPIOA_PIN[0]. 0 1 read-write 0 Set corresponding GPIO pin to low #0 1 Set corresponding GPIO pin to high #1 GPIOA10_DOUT GPIOA10_DOUT GPIO PA.10 Bit Output/Input Value 0x228 read-write n 0x0 0x0 GPIOA11_DOUT GPIOA11_DOUT GPIO PA.11 Bit Output/Input Value 0x22C read-write n 0x0 0x0 GPIOA12_DOUT GPIOA12_DOUT GPIO PA.12 Bit Output/Input Value 0x230 read-write n 0x0 0x0 GPIOA13_DOUT GPIOA13_DOUT GPIO PA.13 Bit Output/Input Value 0x234 read-write n 0x0 0x0 GPIOA14_DOUT GPIOA14_DOUT GPIO PA.14 Bit Output/Input Value 0x238 read-write n 0x0 0x0 GPIOA15_DOUT GPIOA15_DOUT GPIO PA.15 Bit Output/Input Value 0x23C read-write n 0x0 0x0 GPIOA1_DOUT GPIOA1_DOUT GPIO PA.1 Bit Output/Input Value 0x204 read-write n 0x0 0x0 GPIOA2_DOUT GPIOA2_DOUT GPIO PA.2 Bit Output/Input Value 0x208 read-write n 0x0 0x0 GPIOA3_DOUT GPIOA3_DOUT GPIO PA.3 Bit Output/Input Value 0x20C read-write n 0x0 0x0 GPIOA4_DOUT GPIOA4_DOUT GPIO PA.4 Bit Output/Input Value 0x210 read-write n 0x0 0x0 GPIOA5_DOUT GPIOA5_DOUT GPIO PA.5 Bit Output/Input Value 0x214 read-write n 0x0 0x0 GPIOA6_DOUT GPIOA6_DOUT GPIO PA.6 Bit Output/Input Value 0x218 read-write n 0x0 0x0 GPIOA7_DOUT GPIOA7_DOUT GPIO PA.7 Bit Output/Input Value 0x21C read-write n 0x0 0x0 GPIOA8_DOUT GPIOA8_DOUT GPIO PA.8 Bit Output/Input Value 0x220 read-write n 0x0 0x0 GPIOA9_DOUT GPIOA9_DOUT GPIO PA.9 Bit Output/Input Value 0x224 read-write n 0x0 0x0 GPIOA_DBEN GPIOA_DBEN GPIO Port A De-bounce Enable 0x14 read-write n 0x0 0x0 DBEN0 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 0 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN1 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 1 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN10 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 10 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN11 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 11 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN12 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 12 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN13 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 13 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN14 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 14 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN15 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 15 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN2 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 2 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN3 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 3 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN4 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 4 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN5 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 5 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN6 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 6 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN7 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 7 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN8 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 8 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 DBEN9 Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 9 1 read-write 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 GPIOA_DMASK GPIOA_DMASK GPIO Port A Data Output Write Mask 0xC read-write n 0x0 0x0 DMASK0 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 0 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 DMASK1 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 1 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 DMASK10 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 10 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 DMASK11 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 11 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 DMASK12 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 12 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 DMASK13 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 13 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 DMASK14 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 14 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 DMASK15 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 15 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 DMASK2 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 2 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 DMASK3 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 3 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 DMASK4 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 4 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 DMASK5 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 5 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 DMASK6 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 6 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 DMASK7 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 7 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 DMASK8 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 8 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 DMASK9 Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT). 9 1 read-write 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 GPIOA_DOUT GPIOA_DOUT GPIO Port A Data Output Value 0x8 -1 read-write n 0x0 0x0 DOUT0 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 0 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 DOUT1 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 1 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 DOUT10 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 10 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 DOUT11 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 11 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 DOUT12 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 12 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 DOUT13 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 13 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 DOUT14 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 14 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 DOUT15 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 15 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 DOUT2 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 2 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 DOUT3 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 3 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 DOUT4 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 4 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 DOUT5 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 5 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 DOUT6 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 6 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 DOUT7 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 7 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 DOUT8 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 8 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 DOUT9 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode. 9 1 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode #1 GPIOA_IEN GPIOA_IEN GPIO Port A Interrupt Enable 0x1C read-write n 0x0 0x0 IF_EN0 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 0 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IF_EN1 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 1 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IF_EN10 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 10 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IF_EN11 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 11 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IF_EN12 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 12 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IF_EN13 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 13 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IF_EN14 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 14 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IF_EN15 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 15 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IF_EN2 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 2 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IF_EN3 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 3 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IF_EN4 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 4 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IF_EN5 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 5 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IF_EN6 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 6 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IF_EN7 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 7 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IF_EN8 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 8 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IF_EN9 Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt. 9 1 read-write 0 Disable the PIN[n] state low-level or high-to-low change interrupt #0 1 Enable the PIN[n] state low-level or high-to-low change interrupt #1 IR_EN0 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 16 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 IR_EN1 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 17 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 IR_EN10 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 26 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 IR_EN11 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 27 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 IR_EN12 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 28 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 IR_EN13 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 29 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 IR_EN14 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 30 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 IR_EN15 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 31 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 IR_EN2 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 18 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 IR_EN3 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 19 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 IR_EN4 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 20 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 IR_EN5 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 21 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 IR_EN6 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 22 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 IR_EN7 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 23 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 IR_EN8 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 24 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 IR_EN9 Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt. 25 1 read-write 0 Disable the PIN[n] level-high or low-to-high interrupt #0 1 Enable the PIN[n] level-high or low-to-high interrupt #1 GPIOA_IMD GPIOA_IMD GPIO Port A Interrupt Mode Control 0x18 read-write n 0x0 0x0 IMD0 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 0 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD1 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 1 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD10 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 10 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD11 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 11 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD12 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 12 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD13 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 13 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD14 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 14 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD15 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 15 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD2 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 2 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD3 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 3 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD4 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 4 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD5 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 5 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD6 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 6 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD7 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 7 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD8 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 8 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD9 Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 9 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 GPIOA_ISRC GPIOA_ISRC GPIO Port A Interrupt Trigger Source Indicator 0x20 read-write n 0x0 0x0 ISRC0 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 0 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC1 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 1 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC10 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 10 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC11 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 11 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC12 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 12 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC13 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 13 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC14 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 14 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC15 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 15 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC2 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 2 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC3 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 3 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC4 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 4 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC5 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 5 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC6 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 6 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC7 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 7 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC8 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 8 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 ISRC9 Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead : 9 1 read-write 0 No interrupt at GPIOx[n]\nNo action #0 1 Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt #1 GPIOA_OFFD GPIOA_OFFD GPIO Port A Pin OFF Digital Enable 0x4 read-write n 0x0 0x0 OFFD GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, users can OFF digital input path to avoid creepage, 16 16 read-write 0 Enable IO digital input path 0 1 Disable IO digital input path (digital input tied to low) 1 GPIOA_PIN GPIOA_PIN GPIO Port A Pin Value 0x10 read-only n 0x0 0x0 PIN0 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 0 1 read-only PIN1 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 1 1 read-only PIN10 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 10 1 read-only PIN11 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 11 1 read-only PIN12 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 12 1 read-only PIN13 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 13 1 read-only PIN14 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 14 1 read-only PIN15 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 15 1 read-only PIN2 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 2 1 read-only PIN3 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 3 1 read-only PIN4 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 4 1 read-only PIN5 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 5 1 read-only PIN6 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 6 1 read-only PIN7 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 7 1 read-only PIN8 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 8 1 read-only PIN9 Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low 9 1 read-only GPIOA_PMD GPIOA_PMD GPIO Port A Pin I/O Mode Control 0x0 -1 read-write n 0x0 0x0 PMD0 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 0 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD1 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 2 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD10 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 20 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD11 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 22 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD12 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 24 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD13 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 26 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD14 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 28 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD15 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 30 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD2 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 4 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD3 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 6 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD4 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 8 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD5 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 10 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD6 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 12 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD7 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 14 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD8 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 16 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD9 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins. 18 2 read-write 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 GPIOB0_DOUT GPIOB0_DOUT GPIO PB.0 Bit Output/Input Value 0x240 read-write n 0x0 0x0 GPIOB10_DOUT GPIOB10_DOUT GPIO PB.10 Bit Output/Input Value 0x268 read-write n 0x0 0x0 GPIOB11_DOUT GPIOB11_DOUT GPIO PB.11 Bit Output/Input Value 0x26C read-write n 0x0 0x0 GPIOB12_DOUT GPIOB12_DOUT GPIO PB.12 Bit Output/Input Value 0x270 read-write n 0x0 0x0 GPIOB13_DOUT GPIOB13_DOUT GPIO PB.13 Bit Output/Input Value 0x274 read-write n 0x0 0x0 GPIOB14_DOUT GPIOB14_DOUT GPIO PB.14 Bit Output/Input Value 0x278 read-write n 0x0 0x0 GPIOB15_DOUT GPIOB15_DOUT GPIO PB.15 Bit Output/Input Value 0x27C read-write n 0x0 0x0 GPIOB1_DOUT GPIOB1_DOUT GPIO PB.1 Bit Output/Input Value 0x244 read-write n 0x0 0x0 GPIOB2_DOUT GPIOB2_DOUT GPIO PB.2 Bit Output/Input Value 0x248 read-write n 0x0 0x0 GPIOB3_DOUT GPIOB3_DOUT GPIO PB.3 Bit Output/Input Value 0x24C read-write n 0x0 0x0 GPIOB4_DOUT GPIOB4_DOUT GPIO PB.4 Bit Output/Input Value 0x250 read-write n 0x0 0x0 GPIOB5_DOUT GPIOB5_DOUT GPIO PB.5 Bit Output/Input Value 0x254 read-write n 0x0 0x0 GPIOB6_DOUT GPIOB6_DOUT GPIO PB.6 Bit Output/Input Value 0x258 read-write n 0x0 0x0 GPIOB7_DOUT GPIOB7_DOUT GPIO PB.7 Bit Output/Input Value 0x25C read-write n 0x0 0x0 GPIOB8_DOUT GPIOB8_DOUT GPIO PB.8 Bit Output/Input Value 0x260 read-write n 0x0 0x0 GPIOB9_DOUT GPIOB9_DOUT GPIO PB.9 Bit Output/Input Value 0x264 read-write n 0x0 0x0 GPIOB_DBEN GPIOB_DBEN GPIO Port B De-bounce Enable 0x54 read-write n 0x0 0x0 GPIOB_DMASK GPIOB_DMASK GPIO Port B Data Output Write Mask 0x4C read-write n 0x0 0x0 GPIOB_DOUT GPIOB_DOUT GPIO Port B Data Output Value 0x48 read-write n 0x0 0x0 GPIOB_IEN GPIOB_IEN GPIO Port B Interrupt Enable 0x5C read-write n 0x0 0x0 GPIOB_IMD GPIOB_IMD GPIO Port B Interrupt Mode Control 0x58 read-write n 0x0 0x0 GPIOB_ISRC GPIOB_ISRC GPIO Port B Interrupt Trigger Source Indicator 0x60 read-write n 0x0 0x0 GPIOB_OFFD GPIOB_OFFD GPIO Port B Pin OFF Digital Enable 0x44 read-write n 0x0 0x0 GPIOB_PIN GPIOB_PIN GPIO Port B Pin Value 0x50 read-write n 0x0 0x0 GPIOB_PMD GPIOB_PMD GPIO Port B Pin I/O Mode Control 0x40 read-write n 0x0 0x0 GPIOC0_DOUT GPIOC0_DOUT GPIO PC.0 Bit Output/Input Value 0x280 read-write n 0x0 0x0 GPIOC10_DOUT GPIOC10_DOUT GPIO PC.10 Bit Output/Input Value 0x2A8 read-write n 0x0 0x0 GPIOC11_DOUT GPIOC11_DOUT GPIO PC.11 Bit Output/Input Value 0x2AC read-write n 0x0 0x0 GPIOC12_DOUT GPIOC12_DOUT GPIO PC.12 Bit Output/Input Value 0x2B0 read-write n 0x0 0x0 GPIOC13_DOUT GPIOC13_DOUT GPIO PC.13 Bit Output/Input Value 0x2B4 read-write n 0x0 0x0 GPIOC14_DOUT GPIOC14_DOUT GPIO PC.14 Bit Output/Input Value 0x2B8 read-write n 0x0 0x0 GPIOC15_DOUT GPIOC15_DOUT GPIO PC.15 Bit Output/Input Value 0x2BC read-write n 0x0 0x0 GPIOC1_DOUT GPIOC1_DOUT GPIO PC.1 Bit Output/Input Value 0x284 read-write n 0x0 0x0 GPIOC2_DOUT GPIOC2_DOUT GPIO PC.2 Bit Output/Input Value 0x288 read-write n 0x0 0x0 GPIOC3_DOUT GPIOC3_DOUT GPIO PC.3 Bit Output/Input Value 0x28C read-write n 0x0 0x0 GPIOC4_DOUT GPIOC4_DOUT GPIO PC.4 Bit Output/Input Value 0x290 read-write n 0x0 0x0 GPIOC5_DOUT GPIOC5_DOUT GPIO PC.5 Bit Output/Input Value 0x294 read-write n 0x0 0x0 GPIOC6_DOUT GPIOC6_DOUT GPIO PC.6 Bit Output/Input Value 0x298 read-write n 0x0 0x0 GPIOC7_DOUT GPIOC7_DOUT GPIO PC.7 Bit Output/Input Value 0x29C read-write n 0x0 0x0 GPIOC8_DOUT GPIOC8_DOUT GPIO PC.8 Bit Output/Input Value 0x2A0 read-write n 0x0 0x0 GPIOC9_DOUT GPIOC9_DOUT GPIO PC.9 Bit Output/Input Value 0x2A4 read-write n 0x0 0x0 GPIOC_DBEN GPIOC_DBEN GPIO Port C De-bounce Enable 0x94 read-write n 0x0 0x0 GPIOC_DMASK GPIOC_DMASK GPIO Port C Data Output Write Mask 0x8C read-write n 0x0 0x0 GPIOC_DOUT GPIOC_DOUT GPIO Port C Data Output Value 0x88 read-write n 0x0 0x0 GPIOC_IEN GPIOC_IEN GPIO Port C Interrupt Enable 0x9C read-write n 0x0 0x0 GPIOC_IMD GPIOC_IMD GPIO Port C Interrupt Mode Control 0x98 read-write n 0x0 0x0 GPIOC_ISRC GPIOC_ISRC GPIO Port C Interrupt Trigger Source Indicator 0xA0 read-write n 0x0 0x0 GPIOC_OFFD GPIOC_OFFD GPIO Port C Pin OFF Digital Enable 0x84 read-write n 0x0 0x0 GPIOC_PIN GPIOC_PIN GPIO Port C Pin Value 0x90 read-write n 0x0 0x0 GPIOC_PMD GPIOC_PMD GPIO Port C Pin I/O Mode Control 0x80 read-write n 0x0 0x0 GPIOD0_DOUT GPIOD0_DOUT GPIO PD.0 Bit Output/Input Value 0x2C0 read-write n 0x0 0x0 GPIOD10_DOUT GPIOD10_DOUT GPIO PD.10 Bit Output/Input Value 0x2E8 read-write n 0x0 0x0 GPIOD11_DOUT GPIOD11_DOUT GPIO PD.11 Bit Output/Input Value 0x2EC read-write n 0x0 0x0 GPIOD12_DOUT GPIOD12_DOUT GPIO PD.12 Bit Output/Input Value 0x2F0 read-write n 0x0 0x0 GPIOD13_DOUT GPIOD13_DOUT GPIO PD.13 Bit Output/Input Value 0x2F4 read-write n 0x0 0x0 GPIOD14_DOUT GPIOD14_DOUT GPIO PD.14 Bit Output/Input Value 0x2F8 read-write n 0x0 0x0 GPIOD15_DOUT GPIOD15_DOUT GPIO PD.15 Bit Output/Input Value 0x2FC read-write n 0x0 0x0 GPIOD1_DOUT GPIOD1_DOUT GPIO PD.1 Bit Output/Input Value 0x2C4 read-write n 0x0 0x0 GPIOD2_DOUT GPIOD2_DOUT GPIO PD.2 Bit Output/Input Value 0x2C8 read-write n 0x0 0x0 GPIOD3_DOUT GPIOD3_DOUT GPIO PD.3 Bit Output/Input Value 0x2CC read-write n 0x0 0x0 GPIOD4_DOUT GPIOD4_DOUT GPIO PD.4 Bit Output/Input Value 0x2D0 read-write n 0x0 0x0 GPIOD5_DOUT GPIOD5_DOUT GPIO PD.5 Bit Output/Input Value 0x2D4 read-write n 0x0 0x0 GPIOD6_DOUT GPIOD6_DOUT GPIO PD.6 Bit Output/Input Value 0x2D8 read-write n 0x0 0x0 GPIOD7_DOUT GPIOD7_DOUT GPIO PD.7 Bit Output/Input Value 0x2DC read-write n 0x0 0x0 GPIOD8_DOUT GPIOD8_DOUT GPIO PD.8 Bit Output/Input Value 0x2E0 read-write n 0x0 0x0 GPIOD9_DOUT GPIOD9_DOUT GPIO PD.9 Bit Output/Input Value 0x2E4 read-write n 0x0 0x0 GPIOD_DBEN GPIOD_DBEN GPIO Port D De-bounce Enable 0xD4 read-write n 0x0 0x0 GPIOD_DMASK GPIOD_DMASK GPIO Port D Data Output Write Mask 0xCC read-write n 0x0 0x0 GPIOD_DOUT GPIOD_DOUT GPIO Port D Data Output Value 0xC8 read-write n 0x0 0x0 GPIOD_IEN GPIOD_IEN GPIO Port D Interrupt Enable 0xDC read-write n 0x0 0x0 GPIOD_IMD GPIOD_IMD GPIO Port D Interrupt Mode Control 0xD8 read-write n 0x0 0x0 GPIOD_ISRC GPIOD_ISRC GPIO Port D Interrupt Trigger Source Indicator 0xE0 read-write n 0x0 0x0 GPIOD_OFFD GPIOD_OFFD GPIO Port D Pin OFF Digital Enable 0xC4 read-write n 0x0 0x0 GPIOD_PIN GPIOD_PIN GPIO Port D Pin Value 0xD0 read-write n 0x0 0x0 GPIOD_PMD GPIOD_PMD GPIO Port D Pin I/O Mode Control 0xC0 read-write n 0x0 0x0 I2C I2C Register Map I2C 0x0 0x0 0x30 registers n I2CADDR0 I2CADDR0 I2C Slave Address Register 0 0x4 read-write n 0x0 0x0 GC General Call Function 0 1 read-write 0 Disable General Call Function #0 1 Enable General Call Function #1 I2CADDR I2C Address Register The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched. 1 7 read-write I2CADDR1 I2CADDR1 I2C Slave Address Register 1 0x18 read-write n 0x0 0x0 I2CADDR2 I2CADDR2 I2C Slave Address Register 2 0x1C read-write n 0x0 0x0 I2CADDR3 I2CADDR3 I2C Slave Address Register 3 0x20 read-write n 0x0 0x0 I2CADM0 I2CADM0 I2C Slave Address Mask Register 0 0x24 read-write n 0x0 0x0 I2CADMx I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exactly the same as address register. 1 7 read-write 0 Mask disable (the received corresponding register bit should be exactly the same as address register.) 0 1 Mask enable (the received corresponding address bit is don't care.) 1 I2CADM1 I2CADM1 I2C Slave Address Mask Register 1 0x28 read-write n 0x0 0x0 I2CADM2 I2CADM2 I2C Slave Address Mask Register 2 0x2C read-write n 0x0 0x0 I2CADM3 I2CADM3 I2C Slave Address Mask Register 3 0x30 read-write n 0x0 0x0 I2CDAT I2CDAT I2C Data Register 0x8 read-write n 0x0 0x0 I2CDAT I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port. 0 8 read-write I2CLK I2CLK I2C Clock Divider Register 0x10 read-write n 0x0 0x0 I2CLK I2C Clock Divider Register 0 8 read-write I2CON I2CON I2C Control Register 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control Bit 2 1 read-write EI Enable Interrupt 7 1 read-write 0 Disable I2C interrupt #0 1 Enable I2C interrupt #1 ENS1 I2C Controller Enable Bit 6 1 read-write 0 Disable #0 1 Enable #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit. 3 1 read-write STA I2C START Control Bit\nSet STA to logic 1 to enter master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control Bit In master mode, set STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode, set STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. 4 1 read-write I2CSTATUS I2CSTATUS I2C Status Register 0xC -1 read-only n 0x0 0x0 I2CSTATUS I2C Status Register\nThe status register of I2C: 0 8 read-only I2CTOC I2CTOC I2C Time-Out Counter Register 0x14 read-write n 0x0 0x0 DIV4 Time-Out Counter Input Clock is Divided by 4\nWhen Enable, The time-Out period is extended 4 times. 1 1 read-write 0 The Time-out counter input clock divided by 4 Disable #0 1 The Time-out counter input clock divided by 4 Enable #1 ENTI Time-out Counter Enable\nWhen Enable, the 14 bit time-out counter will start counting when SI is clear. Writing 1 to the SI flag will reset counter and re-start up counting after SI is cleared. 2 1 read-write 0 Time-out counter Disable #0 1 Time-out counter Enable #1 TIF Time-Out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nS/W can write 1 to clear this bit. 0 1 read-write INT INT Register Map INT 0x0 0x0 0x88 registers n IRQ0_SRC IRQ0_SRC IRQ0 (BOD) Interrupt Source Identity 0x0 read-only n 0x0 0x0 INT_SRC Interrupt Source\nDefine the interrupt sources for interrupt event. 0 4 read-only IRQ10_SRC IRQ10_SRC IRQ10 (BOD) Interrupt Source Identity 0x28 read-write n 0x0 0x0 IRQ11_SRC IRQ11_SRC IRQ11 (BOD) Interrupt Source Identity 0x2C read-write n 0x0 0x0 IRQ12_SRC IRQ12_SRC IRQ12 (BOD) Interrupt Source Identity 0x30 read-write n 0x0 0x0 IRQ13_SRC IRQ13_SRC IRQ13 (BOD) Interrupt Source Identity 0x34 read-write n 0x0 0x0 IRQ14_SRC IRQ14_SRC IRQ14 (BOD) Interrupt Source Identity 0x38 read-write n 0x0 0x0 IRQ15_SRC IRQ15_SRC IRQ15 (BOD) Interrupt Source Identity 0x3C read-write n 0x0 0x0 IRQ16_SRC IRQ16_SRC IRQ16 (BOD) Interrupt Source Identity 0x40 read-write n 0x0 0x0 IRQ17_SRC IRQ17_SRC IRQ17 (BOD) Interrupt Source Identity 0x44 read-write n 0x0 0x0 IRQ18_SRC IRQ18_SRC IRQ18 (BOD) Interrupt Source Identity 0x48 read-write n 0x0 0x0 IRQ19_SRC IRQ19_SRC IRQ19 (BOD) Interrupt Source Identity 0x4C read-write n 0x0 0x0 IRQ1_SRC IRQ1_SRC IRQ1 (BOD) Interrupt Source Identity 0x4 read-write n 0x0 0x0 IRQ20_SRC IRQ20_SRC IRQ20 (BOD) Interrupt Source Identity 0x50 read-write n 0x0 0x0 IRQ21_SRC IRQ21_SRC IRQ21 (BOD) Interrupt Source Identity 0x54 read-write n 0x0 0x0 IRQ22_SRC IRQ22_SRC IRQ22 (BOD) Interrupt Source Identity 0x58 read-write n 0x0 0x0 IRQ23_SRC IRQ23_SRC IRQ23 (BOD) Interrupt Source Identity 0x5C read-write n 0x0 0x0 IRQ24_SRC IRQ24_SRC IRQ24 (BOD) Interrupt Source Identity 0x60 read-write n 0x0 0x0 IRQ25_SRC IRQ25_SRC IRQ25 (BOD) Interrupt Source Identity 0x64 read-write n 0x0 0x0 IRQ26_SRC IRQ26_SRC IRQ26 (BOD) Interrupt Source Identity 0x68 read-write n 0x0 0x0 IRQ27_SRC IRQ27_SRC IRQ27 (BOD) Interrupt Source Identity 0x6C read-write n 0x0 0x0 IRQ28_SRC IRQ28_SRC IRQ28 (BOD) Interrupt Source Identity 0x70 read-write n 0x0 0x0 IRQ29_SRC IRQ29_SRC IRQ29 (BOD) Interrupt Source Identity 0x74 read-write n 0x0 0x0 IRQ2_SRC IRQ2_SRC IRQ2 (BOD) Interrupt Source Identity 0x8 read-write n 0x0 0x0 IRQ30_SRC IRQ30_SRC IRQ30 (BOD) Interrupt Source Identity 0x78 read-write n 0x0 0x0 IRQ31_SRC IRQ31_SRC IRQ31 (BOD) Interrupt Source Identity 0x7C read-write n 0x0 0x0 IRQ3_SRC IRQ3_SRC IRQ3 (BOD) Interrupt Source Identity 0xC read-write n 0x0 0x0 IRQ4_SRC IRQ4_SRC IRQ4(BOD) Interrupt Source Identity 0x10 read-write n 0x0 0x0 IRQ5_SRC IRQ5_SRC IRQ5 (BOD) Interrupt Source Identity 0x14 read-write n 0x0 0x0 IRQ6_SRC IRQ6_SRC IRQ6 (BOD) Interrupt Source Identity 0x18 read-write n 0x0 0x0 IRQ7_SRC IRQ7_SRC IRQ7 (BOD) Interrupt Source Identity 0x1C read-write n 0x0 0x0 IRQ8_SRC IRQ8_SRC IRQ8 (BOD) Interrupt Source Identity 0x20 read-write n 0x0 0x0 IRQ9_SRC IRQ9_SRC IRQ9 (BOD) Interrupt Source Identity 0x24 read-write n 0x0 0x0 MCU_IRQ MCU_IRQ MCU IRQ Number Identity Register 0x84 read-write n 0x0 0x0 MCU_IRQ MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0. There are two modes to generate interrupt to Cortex-M0, the normal mode and test mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0: Set MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), set 1 to the MCU_IRQ[n] will clear the interrupt and set MCU_IRQ[n] 0 : no any effect. 0 32 read-write NMI_SEL NMI_SEL NMI Interrupt Source Selection Control Register 0x80 read-write n 0x0 0x0 INT_TEST Interrupt Test Mode (write-protection bit) 7 1 read-write NMI_SEL NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupts by setting NMI_SEL. 0 5 read-write PS2 PS2 Register Map PS2 0x0 0x0 0x20 registers n PS2CON PS2CON PS/2 Control Register 0x0 read-write n 0x0 0x0 ACK Acknowledge Enable 7 1 read-write 0 Always send acknowledge to host at 12th clock for host to device communication #0 1 If parity error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock #1 CLRFIFO Clear TX FIFO\nWrite 1 to this bit to terminate device to host transmission. The TXEMPTY bit in PS2STATUS bit will be set to 1 and pointer BYTEIDEX is reset to 0 regardless there is residue data in buffer or not. The buffer content is not been cleared. 8 1 read-write 0 Not active #0 1 Clear FIFO #1 FPS2CLK Force PS2CLK Line\nIt forces PS2CLK line high or low regardless of the internal state of the device controller if OVERRIDE is set to high. 10 1 read-write 0 Force PS2CLK line low #0 1 Force PS2CLK line high #1 FPS2DAT Force PS2DATA Line\nIt forces PS2DATA high or low regardless of the internal state of the device controller if OVERRIDE is set to high. 11 1 read-write 0 Force PS2DATA low #0 1 Force PS2DATA high #1 OVERRIDE Software Override PS/2 CLK/DATA Pin State 9 1 read-write 0 PS2CLK and PS2DATA pins are controlled by internal state machine #0 1 PS2CLK and PS2DATA pins are controlled by S/W #1 PS2EN Enable PS/2 Device\nEnable PS/2 device controller 0 1 read-write 0 Disable #0 1 Enable #1 RXINTEN Enable Receive Interrupt 2 1 read-write 0 Disable data receive complete interrupt #0 1 Enable data receive complete interrupt #1 TXFIFODIPTH Transmit Data FIFO Depth\nThere is 16 bytes buffer for data transmit. S/W can define the FIFO depth from 1 to 16 bytes depends on application. 3 4 read-write 0 1 byte 0 1 2 bytes 1 14 15 bytes 14 15 16 bytes 15 TXINTEN Enable Transmit Interrupt 1 1 read-write 0 Disable data transmit complete interrupt #0 1 Enable data transmit complete interrupt #1 PS2INTID PS2INTID PS/2 Interrupt Identification Register 0x1C read-write n 0x0 0x0 RXINT Receive Interrupt\nThis bit is set to 1 when acknowledge bit is sent for Host to device communication. Interrupt occurs if RXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0. 0 1 read-write 0 No interrupt #0 1 Receive interrupt occurs #1 TXINT Transmit Interrupt\nThis bit is set to 1 after STOP bit is transmitted. Interrupt occur if TXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0. 1 1 read-write 0 No interrupt #0 1 Transmit interrupt occurs #1 PS2RXDATA PS2RXDATA PS/2 Receive Data Register 0x14 read-only n 0x0 0x0 PS2RXDATA Received Data\nFor host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2RXDATA register. CPU must read this register before next byte reception complete, otherwise the data will be overwritten and RXOVF bit in PS2STATUS[6] will be set to 1. 0 8 read-only PS2STATUS PS2STATUS PS/2 Status Register 0x18 -1 read-write n 0x0 0x0 BYTEIDX Byte Index 8 4 read-write FRAMERR Frame Error For host to device communication, if STOP bit (logic 1) is not received it is a frame error. If frame error occurs, DATA line may keep at low state after 12th clock. At this moment, S/W overrides PS2CLK to send clock till PS2DATA release to high state. After that, device sends a Resend command to host. Write 1 to clear this bit. 2 1 read-write 0 No frame error #0 1 Frame error occur #1 PS2CLK CLK Pin State\nThis bit reflects the status of the PS2CLK line after synchronizing. 0 1 read-write PS2DATA DATA Pin State\nThis bit reflects the status of the PS2DATA line after synchronizing and sampling. 1 1 read-write RXBUSY Receive Busy\nThis bit indicates that the PS/2 device is currently receiving data.\nRead only bit. 4 1 read-write 0 Idle #0 1 Currently receiving data #1 RXOVF RX Buffer Overwrite\nWrite 1 to clear this bit. 6 1 read-write 0 No overwrite #0 1 Data in PS2RXDATA register is overwritten by new received data #1 RXPARITY Received Parity\nThis bit reflects the parity bit for the last received data byte (odd parity).\nRead only bit. 3 1 read-write TXBUSY Transmit Busy\nThis bit indicates that the PS/2 device is currently sending data.\nRead only bit. 5 1 read-write 0 Idle #0 1 Currently sending data #1 TXEMPTY TX FIFO Empty\nWhen S/W writes any data to PS2TXDATA0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled. When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1.\nRead only bit. 7 1 read-write 0 There is data to be transmitted #0 1 FIFO is empty #1 PS2TXDATA0 PS2TXDATA0 PS/2 Transmit Data Register 0 0x4 read-write n 0x0 0x0 PS2TXDATAx Transmit Data\nWrite data to this register starts device to host communication if bus is in IDLE state. S/W must enable PS2EN before writing data to TX buffer. 0 32 read-write PS2TXDATA1 PS2TXDATA1 PS/2 Transmit Data Register 1 0x8 read-write n 0x0 0x0 PS2TXDATA2 PS2TXDATA2 PS/2 Transmit Data Register 2 0xC read-write n 0x0 0x0 PS2TXDATA3 PS2TXDATA3 PS/2 Transmit Data Register 3 0x10 read-write n 0x0 0x0 PWMA PWM Register Map PWM 0x0 0x0 0x3C registers n 0x40 0x8 registers n 0x50 0x30 registers n CAPENR CAPENR PWM Group A Capture Input 0~3 Enable Register 0x78 read-write n 0x0 0x0 CAPENR Capture Input Enable Register There are four capture inputs from pad. Bit0~Bit3 are used to control each input enable or disable. CAPENR Bit 3210 for PWM group A Bit xxx1 ( Capture channel 0 is from pin PA.12 Bit xx1x ( Capture channel 1 is from pin PA.13 Bit x1xx ( Capture channel 2 is from pin PA.14 Bit 1xxx ( Capture channel 3 is from pin PA.15 0 4 read-write 0 Disable (PWMx multi-function pin input does not affect input capture function.) 0 1 Enable (PWMx multi-function pin input will affect its input capture function.) 1 CCR0 CCR0 PWM Group A Capture Control Register 0 0x50 read-write n 0x0 0x0 CAPCH0EN Channel 0 Capture Function Enable\nWhen Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt. 3 1 read-write 0 Disable capture function on PWM group channel 0 #0 1 Enable capture function on PWM group channel 0 #1 CAPCH1EN Channel 1 Capture Function Enable\nWhen Enable, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt. 19 1 read-write 0 Disable capture function on PWM group channel 1 #0 1 Enable capture function on PWM group channel 1 #1 CAPIF0 Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero 4 1 read-write CAPIF1 Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero 20 1 read-write CFLRI0 CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero. 7 1 read-write CFLRI1 CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero 23 1 read-write CFL_IE0 Channel 0 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 0 has falling transition, Capture issues an Interrupt. 2 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CFL_IE1 Channel 1 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has falling transition, Capture issues an Interrupt. 18 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CRLRI0 CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero. 6 1 read-write CRLRI1 CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero 22 1 read-write CRL_IE0 Channel 0 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 0 has rising transition, Capture issues an Interrupt. 1 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 CRL_IE1 Channel 1 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has rising transition, Capture issues an Interrupt. 17 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 INV0 Channel 0 Inverter Enable 0 1 read-write 0 Inverter disable #0 1 Inverter enable. Reverse the input signal from GPIO before fed to Capture timer #1 INV1 Channel 1 Inverter Enable 16 1 read-write 0 Inverter disable #0 1 Inverter enable. Reverse the input signal from GPIO before fed to Capture timer #1 CCR2 CCR2 PWM Group A Capture Control Register 2 0x54 read-write n 0x0 0x0 CAPCH2EN Channel 2 Capture Function Enable\nWhen Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt. 3 1 read-write 0 Disable capture function on PWM group channel 2 #0 1 Enable capture function on PWM group channel 2 #1 CAPCH3EN Channel 3 Capture Function Enable\nWhen Enable, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt. 19 1 read-write 0 Disable capture function on PWM group channel 3 #0 1 Enable capture function on PWM group channel 3 #1 CAPIF2 Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero 4 1 read-write CAPIF3 Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero 20 1 read-write CFLRI2 CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero. 7 1 read-write CFLRI3 CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero. 23 1 read-write CFL_IE2 Channel 2 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 2 has falling transition, Capture issues an Interrupt. 2 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CFL_IE3 Channel 3 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 3 has falling transition, Capture issues an Interrupt. 18 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CRLRI2 CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero. 6 1 read-write CRLRI3 CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero. 22 1 read-write CRL_IE2 Channel 2 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 2 has rising transition, Capture issues an Interrupt. 1 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 CRL_IE3 Channel 3 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 3 has rising transition, Capture issues an Interrupt. 17 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 INV2 Channel 2 Inverter Enable 0 1 read-write 0 Inverter disable #0 1 Inverter enable. Reverse the input signal from GPIO before fed to Capture timer #1 INV3 Channel 3 Inverter Enable 16 1 read-write 0 Inverter disable #0 1 Inverter enable. Reverse the input signal from GPIO before fed to Capture timer #1 CFLR0 CFLR0 PWM Group A Capture Falling Latch Register (Channel 0) 0x5C read-only n 0x0 0x0 CFLRx Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has falling transition. 0 16 read-only CFLR1 CFLR1 PWM Group A Capture Falling Latch Register (Channel 1) 0x64 read-write n 0x0 0x0 CFLR2 CFLR2 PWM Group A Capture Falling Latch Register (Channel 2) 0x6C read-write n 0x0 0x0 CFLR3 CFLR3 PWM Group A Capture Falling Latch Register (Channel 3) 0x74 read-write n 0x0 0x0 CMR0 CMR0 PWM Group A Comparator Register 0 0x10 read-write n 0x0 0x0 CMRx PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CMR will take effect in next PWM cycle. 0 16 read-write CMR1 CMR1 PWM Group A Comparator Register 1 0x1C read-write n 0x0 0x0 CMR2 CMR2 PWM Group A Comparator Register 2 0x28 read-write n 0x0 0x0 CMR3 CMR3 PWM Group A Comparator Register 3 0x34 read-write n 0x0 0x0 CNR0 CNR0 PWM Group A Counter Register 0 0xC read-write n 0x0 0x0 CNRx PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle. 0 16 read-write CNR1 CNR1 PWM Group A Counter Register 1 0x18 read-write n 0x0 0x0 CNR2 CNR2 PWM Group A Counter Register 2 0x24 read-write n 0x0 0x0 CNR3 CNR3 PWM Group A Counter Register 3 0x30 read-write n 0x0 0x0 CRLR0 CRLR0 PWM Group A Capture Rising Latch Register (Channel 0) 0x58 read-only n 0x0 0x0 CRLRx Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition. 0 16 read-only CRLR1 CRLR1 PWM Group A Capture Rising Latch Register (Channel 1) 0x60 read-write n 0x0 0x0 CRLR2 CRLR2 PWM Group A Capture Rising Latch Register (Channel 2) 0x68 read-write n 0x0 0x0 CRLR3 CRLR3 PWM Group A Capture Rising Latch Register (Channel 3) 0x70 read-write n 0x0 0x0 CSR CSR PWM Group A Clock Selection Register 0x4 read-write n 0x0 0x0 CSR0 PWM Timer 0 Clock Source Selection (PWM timer 0 for group A)\nSelect clock input for PWM timer.\n(Table is the same as CSR3) 0 3 read-write CSR1 PWM Timer 1 Clock Source Selection (PWM timer 1 for group A)\nSelect clock input for PWM timer.\n(Table is the same as CSR3) 4 3 read-write CSR2 PWM Timer 2 Clock Source Selection (PWM timer 2 for group A)\nSelect clock input for PWM timer.\n(Table is the same as CSR3) 8 3 read-write CSR3 PWM Timer 3 Clock Source Selection (PWM timer 3 for group A) 12 3 read-write PCR PCR PWM Group A Control Register 0x8 read-write n 0x0 0x0 CH0EN PWM-Timer 0 Enable (PWM timer 0 for group A) 0 1 read-write 0 Stop corresponding PWM-Timer Running #0 1 Enable corresponding PWM-Timer Start Run #1 CH0INV PWM-Timer 0 Output Inverter Enable (PWM timer 0 for group A 2 1 read-write 0 Inverter disable #0 1 Inverter enable #1 CH0MOD PWM-Timer 0 Auto-reload/One-Shot Mode (PWM timer 0 for group A)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be clear. 3 1 read-write 0 One-Shot Mode #0 1 Auto-reload Mode #1 CH1EN PWM-Timer 1 Enable (PWM timer 1 for group A) 8 1 read-write 0 Stop corresponding PWM-Timer Running #0 1 Enable corresponding PWM-Timer Start Run #1 CH1INV PWM-Timer 1 Output Inverter Enable (PWM timer 1 for group A) 10 1 read-write 0 Inverter disable #0 1 Inverter enable #1 CH1MOD PWM-Timer 1 Auto-reload/One-Shot Mode (PWM timer 1 for group A)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be clear. 11 1 read-write 0 One-Shot Mode #0 1 Auto-load Mode #1 CH2EN PWM-Timer 2 Enable (PWM timer 2 for group A) 16 1 read-write 0 Stop corresponding PWM-Timer Running #0 1 Enable corresponding PWM-Timer Start Run #1 CH2INV PWM-Timer 2 Output Inverter Enable (PWM timer 2 for group A) 18 1 read-write 0 Inverter disable #0 1 Inverter enable #1 CH2MOD PWM-Timer 2 Auto-reload/One-Shot Mode (PWM timer 2 for group A)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be clear. 19 1 read-write 0 One-Shot Mode #0 1 Auto-reload Mode #1 CH3EN PWM-Timer 3 Enable (PWM timer 3 for group A) 24 1 read-write 0 Stop corresponding PWM-Timer Running #0 1 Enable corresponding PWM-Timer Start Run #1 CH3INV PWM-Timer 3 Output Inverter Enable (PWM timer 3 for group A) 26 1 read-write 0 Inverter disable #0 1 Inverter enable #1 CH3MOD PWM-Timer 3 Auto-reload/One-Shot Mode (PWM timer 3 for group A)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be clear. 27 1 read-write 0 One-Shot Mode #0 1 Auto-reload Mode #1 DZEN01 Dead-Zone 0 Generator Enable (PWM0 and PWM1 pair for PWM group A)\nNote: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A 4 1 read-write 0 Disable #0 1 Enable #1 DZEN23 Dead-Zone 2 Generator Enable (PWM2 and PWM3 pair for PWM group A)\nNote: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A. 5 1 read-write 0 Disable #0 1 Enable #1 PDR0 PDR0 PWM Group A Data Register 0 0x14 read-only n 0x0 0x0 PDRx PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter. 0 16 read-only PDR1 PDR1 PWM Group A Data Register 1 0x20 read-write n 0x0 0x0 PDR2 PDR2 PWM Group A Data Register 2 0x2C read-write n 0x0 0x0 PDR3 PDR3 PWM Group A Data Register 3 0x38 read-write n 0x0 0x0 PIER PIER PWM Group A Interrupt Enable Register 0x40 read-write n 0x0 0x0 PWMIE0 PWM Channel 0 Interrupt Enable 0 1 read-write 0 Disable #0 1 Enable #1 PWMIE1 PWM Channel 1 Interrupt Enable 1 1 read-write 0 Disable #0 1 Enable #1 PWMIE2 PWM Channel 2 Interrupt Enable 2 1 read-write 0 Disable #0 1 Enable #1 PWMIE3 PWM Channel 3 Interrupt Enable 3 1 read-write 0 Disable #0 1 Enable #1 PIIR PIIR PWM Group A Interrupt Indication Register 0x44 read-write n 0x0 0x0 PWMIF0 PWM Channel 0 Interrupt Status\nThis bit is set by hardware when PWM0 down counter reaches zero and PWM0 interrupt enable bit (PWMIE0) is 1, software can write 1 to clear this bit to zero. 0 1 read-write PWMIF1 PWM Channel 1 Interrupt Status\nThis bit is set by hardware when PWM1 down counter reaches zero and PWM1 interrupt enable bit (PWMIE1) is 1, software can write 1 to clear this bit to zero. 1 1 read-write PWMIF2 PWM Channel 2 Interrupt Status\nThis bit is set by hardware when PWM2 down counter reaches zero and PWM2 interrupt enable bit (PWMIE2) is 1, software can write 1 to clear this bit to zero. 2 1 read-write PWMIF3 PWM Channel 3 Interrupt Status\nThis bit is set by hardware when PWM3 down counter reaches zero and PWM3 interrupt enable bit (PWMIE3) is 1, software can write 1 to clear this bit to zero. 3 1 read-write POE POE PWM Group A Output Enable Register for Channel 0~3 0x7C read-write n 0x0 0x0 PWM0 Channel 0 Output Enable \nNote: The corresponding GPIO pin also must be switched to PWM function 0 1 read-write 0 Disable PWM channel 0 output to pin #0 1 Enable PWM channel 0 output to pin #1 PWM1 Channel 1 Output Enable\nNote: The corresponding GPIO pin also must be switched to PWM function 1 1 read-write 0 Disable PWM channel 1 output to pin #0 1 Enable PWM channel 1 output to pin #1 PWM2 Channel 2 Output Enable \nNote: The corresponding GPIO pin also must be switched to PWM function 2 1 read-write 0 Disable PWM channel 2 output to pin #0 1 Enable PWM channel 2 output to pin #1 PWM3 Channel 3 Output Enable \nNote: The corresponding GPIO pin also must be switched to PWM function 3 1 read-write 0 Disable PWM channel 3 output to pin #0 1 Enable PWM channel 3 output to pin #1 PPR PPR PWM Group A Pre-scale Register 0x0 read-write n 0x0 0x0 CP01 Clock Prescaler 0 (PWM-timer 0 1 for group A) Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer 0 8 read-write CP23 Clock Prescaler 2 (PWM-timer2 3 for group A) Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer 8 8 read-write DZI01 Dead Zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 pair for PWM group A)\nThese 8 bits determine dead zone length. 16 8 read-write DZI23 Dead Zone Interval for Pair of Channel2 and Channel3 (PWM2 and PWM3 pair for PWM group A)\nThese 8 bits determine dead zone length. 24 8 read-write RTC RTC Register Map RTC 0x0 0x0 0x30 registers n AER AER RTC Access Enable Register 0x4 read-write n 0x0 0x0 AER RTC Register Access Enable Password (Write only)\nWriting 0xA965 to this register will enable RTC registers read/write access and keep 512 RTC clocks. 0 16 write-only ENF RTC Register Access Enable Flag (Read only) 16 1 read-only 0 RTC register read/write disable #0 1 RTC register read/write enable #1 CAR CAR Calendar Alarm Register 0x20 read-write n 0x0 0x0 _10DAY 10-Day Calendar Digit of Alarm Setting (0~3) 4 2 read-write _10MON 10-Month Calendar Digit of Alarm Setting (0~1) 12 1 read-write _10YEAR 10-Year Calendar Digit of Alarm Setting (0~9) 20 4 read-write _1DAY 1-Day Calendar Digit of Alarm Setting (0~9) 0 4 read-write _1MON 1-Month Calendar Digit of Alarm Setting (0~9) 8 4 read-write _1YEAR 1-Year Calendar Digit of Alarm Setting (0~9) 16 4 read-write CLR CLR Calendar Loading Register 0x10 -1 read-write n 0x0 0x0 _10DAY 10-Day Calendar Digit (0~3) 4 2 read-write _10MON 10-Month Calendar Digit (0~1) 12 1 read-write _10YEAR 10-Year Calendar Digit (0~9) 20 4 read-write _1DAY 1-Day Calendar Digit (0~9) 0 4 read-write _1MON 1-Month Calendar Digit (0~9) 8 4 read-write _1YEAR 1-Year Calendar Digit (0~9) 16 4 read-write DWR DWR Day of the Week Register 0x18 -1 read-write n 0x0 0x0 DWR Day of the Week Register 0 3 read-write FCR FCR Frequency Compensation Register 0x8 -1 read-write n 0x0 0x0 FRACTION Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number. Refer to 5.8.4.4 for the examples. 0 6 read-write INTEGER Integer Part 8 4 read-write INIR INIR RTC Initiation Register 0x0 read-write n 0x0 0x0 INIR RTC Initiation\nRead return current RTC active status\nA write of 0xa5eb1357 to make RTC leaving reset state.\nWhen RTC block is powered on, RTC is in reset state. User has to write a number 0x a5eb1357 to INIR register to make RTC leave reset state. Once the INIR is written as 0xa5eb1357, the RTC will be in normal active state permanently. 0 32 read-write 0 RTC is in reset state 0 1 RTC is in normal active state 1 LIR LIR RTC Leap Year Indication Register 0x24 read-only n 0x0 0x0 LIR Leap Year Indication REGISTER (Real only). 0 1 read-only 0 It indicate that this year is not a leap year #0 1 It indicate that this year is leap year #1 RIER RIER RTC Interrupt Enable Register 0x28 read-write n 0x0 0x0 AIER Alarm Interrupt Enable 0 1 read-write 0 RTC Alarm Interrupt is disabled #0 1 RTC Alarm Interrupt is enabled #1 TIER Time Tick Interrupt Enable 1 1 read-write 0 RTC Time Tick Interrupt is disabled #0 1 RTC Time Tick Interrupt is enabled #1 RIIR RIIR RTC Interrupt Indication Register 0x2C read-write n 0x0 0x0 AIF RTC Alarm Interrupt Flag 0 1 read-write 0 Indicates RTC Alarm Interrupt condition never occurred #0 1 Indicates RTC Alarm Interrupt is requested if RIER.AIER=1 #1 TIF RTC Time Tick Interrupt Flag 1 1 read-write 0 Indicates RTC Time Tick Interrupt condition never occurred #0 1 Indicates RTC Time Tick Interrupt is requested if RIER.TIER=1 #1 TAR TAR Time Alarm Register 0x1C read-write n 0x0 0x0 _10HR 10-Hour Time Digit of Alarm Setting (0~2) 20 2 read-write _10MIN 10-Min Time Digit of Alarm Setting (0~5) 12 3 read-write _10SEC 10-Sec Time Digit of Alarm Setting (0~5) 4 3 read-write _1HR 1-Hour Time Digit of Alarm Setting (0~9) 16 4 read-write _1MIN 1-Min Time Digit of Alarm Setting (0~9) 8 4 read-write _1SEC 1-Sec Time Digit of Alarm Setting (0~9) 0 4 read-write TLR TLR Time Loading Register 0xC read-write n 0x0 0x0 _10HR 10-Hour Time Digit (0~2) 20 2 read-write _10MIN 10-Min Time Digit (0~5) 12 3 read-write _10SEC 10-Sec Time Digit (0~5) 4 3 read-write _1HR 1-Hour Time Digit (0~9) 16 4 read-write _1MIN 1-Min Time Digit (0~9) 8 4 read-write _1SEC 1-Sec Time Digit (0~9) 0 4 read-write TSSR TSSR Time Scale Selection Register 0x14 -1 read-write n 0x0 0x0 _24hr_12hr 24-Hour / 12-Hour Mode Selection 0 1 read-write 0 select 12-hour time scale with AM and PM indication #0 1 select 24-hour time scale #1 TTR TTR RTC Time Tick Register 0x30 read-write n 0x0 0x0 TTR Time Tick Register 0 3 read-write TWKE RTC Timer Wake-Up Function Enable Bit\nIf TWKE is set before chip is in power down mode, chip will be woken-up by RTC controller when a RTC Time Tick occurs, The chip can also be woken-up by alarm match occur.\nNote: Tick timer setting follows TTR[2:0] description. 3 1 read-write 0 Disable RTC Timer wake-up function #0 1 Enable RTC Timer wake-up function that chip can be woken-up from power down mode by Time Tick or Alarm Match #1 SCS SCS Register Map SCS 0x0 0x10 0xC registers n 0x100 0x4 registers n 0x180 0x4 registers n 0x200 0x4 registers n 0x280 0x4 registers n 0x400 0x20 registers n 0xD00 0x8 registers n 0xD0C 0x8 registers n 0xD1C 0x8 registers n AIRCR AIRCR Application Interrupt and Reset Control Register 0xD0C -1 read-write n 0x0 0x0 SYSRESETREQ Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence. 2 1 read-write VECTCLRACTIVE Set this bit to 1 will clears all active state information for fixed and configurable exceptions.\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack. 1 1 read-write VECTORKEY When write this register, this field should be 0x05FA, otherwise the write action will be unpredictable. 16 16 read-write CPUID CPUID CPUID Register 0xD00 -1 read-only n 0x0 0x0 IMPLEMENTER None 24 8 read-only PART Reads as 0xC for ARM v6-M parts 16 4 read-only PARTNO Reads as 0xC20. 4 12 read-only REVISION Reads as 0x0 0 4 read-only ICSR ICSR Interrupt Control and State Register 0xD04 read-write n 0x0 0x0 ISRPENDING Interrupt pending flag, excluding NMI and Faults:\nThis is a read only bit. 22 1 read-write 0 interrupt not pending #0 1 interrupt pending #1 ISRPREEMPT If set, a pending exception will be serviced on exit from the debug halt state.\nThis is a read only bit. 23 1 read-write NMIPENDSET NMI set-pending bit\nWrite:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 31 1 read-write 0 no effect\nNMI exception is not pending #0 1 changes NMI exception state to pending.\nNMI exception is pending #1 PENDSTCLR SysTick exception clear-pending bit. Write: This is a write only bit. When you want to clear PENDST bit, you must write 0 to PENDSTSET and write 1 to PENDSTCLR at the same time. 25 1 read-write 0 no effect #0 1 removes the pending state from the SysTick exception #1 PENDSTSET SysTick exception set-pending bit.\nWrite: 26 1 read-write 0 no effect\nSysTick exception is not pending #0 1 changes SysTick exception state to pending.\nSysTick exception is pending #1 PENDSVCLR PendSV clear-pending bit. Write: This is a write only bit. When you want to clear PENDSV bit, you must write 0 to PENDSVSET and write 1 to PENDSVCLR at the same time. 27 1 read-write 0 no effect #0 1 removes the pending state from the PendSV exception #1 PENDSVSET PendSV set-pending bit.\nWrite:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending. 28 1 read-write 0 no effect\nPendSV exception is not pending #0 1 changes PendSV exception state to pending.\nPendSV exception is pending #1 VECTACTIVE Contains the active exception number 0 6 read-write 0 Thread mode 0 VECTPENDING Indicates the exception number of the highest priority pending enabled exception: 12 6 read-write 0 no pending exceptions 0 NVIC_ICER NVIC_ICER IRQ0 ~ IRQ31 Clear-Enable Control Register 0x180 read-write n 0x0 0x0 CLRENA Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 1 will disable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with the current enable state. 0 32 read-write NVIC_ICPR NVIC_ICPR IRQ0 ~ IRQ31 Clear-Pending Control Register 0x280 read-write n 0x0 0x0 CLRPEND Writing 1 to a bit to remove the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the current pending state. 0 32 read-write NVIC_IPR0 NVIC_IPR0 IRQ0 ~ IRQ3 Priority Control Register 0x400 read-write n 0x0 0x0 PRI_0 Priority of IRQ0 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_1 Priority of IRQ1 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_2 Priority of IRQ2 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_3 Priority of IRQ3 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR1 NVIC_IPR1 IRQ4 ~ IRQ7 Priority Control Register 0x404 read-write n 0x0 0x0 PRI_4 Priority of IRQ4 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_5 Priority of IRQ5 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_6 Priority of IRQ6 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_7 Priority of IRQ7 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR2 NVIC_IPR2 IRQ8 ~ IRQ11 Priority Control Register 0x408 read-write n 0x0 0x0 PRI_10 Priority of IRQ10 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_11 Priority of IRQ11 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write PRI_8 Priority of IRQ8 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_9 Priority of IRQ9 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write NVIC_IPR3 NVIC_IPR3 IRQ12 ~ IRQ15 Priority Control Register 0x40C read-write n 0x0 0x0 PRI_12 Priority of IRQ12 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_13 Priority of IRQ13 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_14 Priority of IRQ14 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_15 Priority of IRQ15 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR4 NVIC_IPR4 IRQ16 ~ IRQ19 Priority Control Register 0x410 read-write n 0x0 0x0 PRI_16 Priority of IRQ16 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_17 Priority of IRQ17 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_18 Priority of IRQ18 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_19 Priority of IRQ19 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR5 NVIC_IPR5 IRQ20 ~ IRQ23 Priority Control Register 0x414 read-write n 0x0 0x0 PRI_20 Priority of IRQ20 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_21 Priority of IRQ21 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_22 Priority of IRQ22 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_23 Priority of IRQ23 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR6 NVIC_IPR6 IRQ24 ~ IRQ27 Priority Control Register 0x418 read-write n 0x0 0x0 PRI_24 Priority of IRQ24 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_25 Priority of IRQ25 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_26 Priority of IRQ26 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_27 Priority of IRQ27 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_IPR7 NVIC_IPR7 IRQ28 ~ IRQ31 Priority Control Register 0x41C read-write n 0x0 0x0 PRI_28 Priority of IRQ28 0 denotes the highest priority and 3 denotes lowest priority 6 2 read-write PRI_29 Priority of IRQ29 0 denotes the highest priority and 3 denotes lowest priority 14 2 read-write PRI_30 Priority of IRQ30 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_31 Priority of IRQ31 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write NVIC_ISER NVIC_ISER IRQ0 ~ IRQ31 Set-Enable Control Register 0x100 read-write n 0x0 0x0 SETENA Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 1 will enable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with the current enable state. 0 32 read-write NVIC_ISPR NVIC_ISPR IRQ0 ~ IRQ31 Set-Pending Control Register 0x200 read-write n 0x0 0x0 SETPEND Writing 1 to a bit to set pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the current pending state. 0 32 read-write SCR SCR System Control Register 0xD10 read-write n 0x0 0x0 SEVONPEND Send Event on Pending bit:\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event. 4 1 read-write 0 only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded #0 1 enabled events and all interrupts, including disabled interrupts, can wakeup the processor #1 SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low power mode: 2 1 read-write 0 sleep #0 1 deep sleep #1 SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 1 1 read-write 0 do not sleep when returning to Thread mode #0 1 enter sleep, or deep sleep, on return from an ISR to Thread mode #1 SHPR2 SHPR2 System Handler Priority Register 2 0xD1C read-write n 0x0 0x0 PRI_11 Priority of system handler 11 - SVCall 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write SHPR3 SHPR3 System Handler Priority Register 3 0xD20 read-write n 0x0 0x0 PRI_14 Priority of system handler 14 - PendSV 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI_15 Priority of system handler 15 - SysTick 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write SYST_CSR SYST_CSR SysTick Control and Status Register 0x10 read-write n 0x0 0x0 CLKSRC None 2 1 read-write 0 Clock source is (optional) external reference clock #0 1 Core clock used for SysTick #1 COUNTFLAG Returns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register. 16 1 read-write ENABLE None 0 1 read-write 0 The counter is disabled #0 1 The counter will operate in a multi-shot manner #1 TICKINT None 1 1 read-write 0 Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended #1 SYST_CVR SYST_CVR SysTick Current Value Register 0x18 read-write n 0x0 0x0 CURRENT Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. 0 24 read-write SYST_RVR SYST_RVR SysTick Reload Value Register 0x14 read-write n 0x0 0x0 RELOAD Value to load into the Current Value register when the counter reaches 0. 0 24 read-write SPI0 SPI Register Map SPI 0x0 0x0 0xC registers n 0x10 0x8 registers n 0x20 0x8 registers n 0x34 0x4 registers n SPI_CNTRL SPI_CNTRL Control and Status Register 0x0 -1 read-write n 0x0 0x0 CLKP Clock Polarity 11 1 read-write 0 SPICLK idle low #0 1 SPICLK idle high #1 GO_BUSY Go and Busy Status\nDuring the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote:\nAll registers should be set before writing 1 to this GO_BUSY bit. 0 1 read-write 0 Writing 0 to this bit to stop data transfer if SPI is transferring #0 1 In master mode, writing 1 to this bit to start the SPI data transfer in slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master #1 IE Interrupt Enable 17 1 read-write 0 Disable SPI Interrupt #0 1 Enable SPI Interrupt #1 IF Interrupt Flag\nNote: This bit is cleared by writing 1 to itself. 16 1 read-write 0 It indicates that the transfer dose not finish yet #0 1 It indicates that the transfer is done #1 LSB LSB First 10 1 read-write 0 The MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the TX_BIT_LEN field) #0 1 The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position in the RX register (bit 0 of SPI_RX0/1) #1 REORDER Reorder Mode Select\nNote:\n1. Byte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\n2. In slave mode with level-trigger configuration, if the byte suspend function is enabled, the slave select pin must be kept at active state during the successive four bytes transfer. 19 2 read-write 0 Disable both byte reorder and byte suspend functions #00 1 Enable byte reorder function and insert a byte suspend interval (2~17 SPICLK cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word) #01 2 Enable byte reorder function, but disable byte suspend function #10 3 Disable byte reorder function, but insert a suspend interval (2~17 SPICLK cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word) #11 RX_NEG Receive At Negative Edge 1 1 read-write 0 The received data input signal is latched at the rising edge of SPICLK #0 1 The received data input signal is latched at the falling edge of SPICLK #1 SLAVE Slave Mode Indication 18 1 read-write 0 Master mode #0 1 Slave mode #1 SP_CYCLE Suspend Interval (Master only) 12 4 read-write TX_BIT_LEN Transmit Bit Length\nThis field specifies how many bits are transmitted in one transaction. Up to 32 bits can be transmitted. 3 5 read-write TX_NEG Transmit At Negative Edge 2 1 read-write 0 The transmitted data output signal is changed at the rising edge of SPICLK #0 1 The transmitted data output signal is changed at the falling edge of SPICLK #1 TX_NUM Numbers of Transmit/Receive Word\nThis field specifies how many transmit/receive word numbers should be executed in one transfer.\nNote: In slave mode with level-trigger configuration, if TX_NUM is set to 01, the slave select pin must be kept at active state during the successive data transfer. 8 2 read-write 0 Only one transmit/receive word will be executed in one transfer #00 1 Two successive transmit/receive words will be executed in one transfer. (burst mode) #01 2 Reserved #10 3 Reserved #11 VARCLK_EN Variable Clock Enable (Master only)\nNote that when enable this VARCLK_EN bit, the setting of TX_BIT_LEN must be programmed as 0x10 (16 bits mode) 23 1 read-write 0 The serial clock output frequency is fixed and decided only by the value of DIVIDER #0 1 The serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2 #1 SPI_DIVIDER SPI_DIVIDER Clock Divider Register (Master only) 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider Register (Master only)\nThe value in this field is the frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIn slave mode, the period of SPI clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK. 0 16 read-write DIVIDER2 Clock Divider 2 Register (Master only)\nThe value in this field is the 2nd frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIf VARCLK_EN is cleared to 0, this setting is unmeaning. 16 16 read-write SPI_RX0 SPI_RX0 Data Receive Register 0 0x10 read-only n 0x0 0x0 RX Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. The values of the other bits are unknown.\nNote: The Data Receive Registers are read only registers. 0 32 read-only SPI_RX1 SPI_RX1 Data Receive Register 1 0x14 read-write n 0x0 0x0 SPI_SSR SPI_SSR Slave Select Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Select (Master only) 3 1 read-write 0 If this bit is cleared, slave select signals will be asserted and de-asserted by setting and clearing related bits in SSR[1:0] #0 1 If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SSR[1:0], will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished #1 LTRIG_FLAG Level Trigger Flag\nWhen the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only 5 1 read-write 0 The transaction number or the transferred bit length of one transaction doesn't meet the specified requirements #0 1 The transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN #1 SSR Slave Select Register (Master only) If AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state. If AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state writing 1 to any bit location of this field will select the corresponding SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL. Note: SPISSx0 is also defined as slave select input in slave mode. 0 2 read-write SS_LTRIG Slave Select Level Trigger (Slave only) 4 1 read-write 0 The input slave select signal is edge-trigger. This is the default value. It depends on SS_LVL to decide the signal is active at falling-edge or rising-edge #0 1 The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high #1 SS_LVL Slave Select Active Level\nIt defines the active state of slave select signal (SPISSx0/1). 2 1 read-write 0 The slave select signal SPISSx0/1 is active at low-level/falling-edge #0 1 The slave select signal SPISSx0/1 is active at high-level/rising-edge #1 SPI_TX0 SPI_TX0 Data Transmit Register 0 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the SPI controller will perform two 32-bit transmit/receive successive using the same setting. The transmission sequence is TX0[31:0] first and then TX1[31:0]. 0 32 write-only SPI_TX1 SPI_TX1 Data Transmit Register 1 0x24 read-write n 0x0 0x0 SPI_VARCLK SPI_VARCLK Variable Clock Pattern Register (Master only) 0x34 -1 read-write n 0x0 0x0 VARCLK Variable Clock Pattern (Master only)\nThe value in this field is the frequency patterns of the SPI clock. If the bit pattern of VARCLK is '0', the output frequency of SPICLK is according the value of DIVIDER. If the bit patterns of VARCLK are '1', the output frequency of SPICLK is according the value of DIVIDER2. Refer to register SPI_DIVIDER.\nRefer to Variable Clock paragraph for more detailed Description. 0 32 read-write SPI1 SPI Register Map SPI 0x0 0x0 0xC registers n 0x10 0x8 registers n 0x20 0x8 registers n 0x34 0x4 registers n SPI_CNTRL SPI_CNTRL Control and Status Register 0x0 -1 read-write n 0x0 0x0 CLKP Clock Polarity 11 1 read-write 0 SPICLK idle low #0 1 SPICLK idle high #1 GO_BUSY Go and Busy Status\nDuring the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote:\nAll registers should be set before writing 1 to this GO_BUSY bit. 0 1 read-write 0 Writing 0 to this bit to stop data transfer if SPI is transferring #0 1 In master mode, writing 1 to this bit to start the SPI data transfer in slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master #1 IE Interrupt Enable 17 1 read-write 0 Disable SPI Interrupt #0 1 Enable SPI Interrupt #1 IF Interrupt Flag\nNote: This bit is cleared by writing 1 to itself. 16 1 read-write 0 It indicates that the transfer dose not finish yet #0 1 It indicates that the transfer is done #1 LSB LSB First 10 1 read-write 0 The MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the TX_BIT_LEN field) #0 1 The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position in the RX register (bit 0 of SPI_RX0/1) #1 REORDER Reorder Mode Select\nNote:\n1. Byte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\n2. In slave mode with level-trigger configuration, if the byte suspend function is enabled, the slave select pin must be kept at active state during the successive four bytes transfer. 19 2 read-write 0 Disable both byte reorder and byte suspend functions #00 1 Enable byte reorder function and insert a byte suspend interval (2~17 SPICLK cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word) #01 2 Enable byte reorder function, but disable byte suspend function #10 3 Disable byte reorder function, but insert a suspend interval (2~17 SPICLK cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word) #11 RX_NEG Receive At Negative Edge 1 1 read-write 0 The received data input signal is latched at the rising edge of SPICLK #0 1 The received data input signal is latched at the falling edge of SPICLK #1 SLAVE Slave Mode Indication 18 1 read-write 0 Master mode #0 1 Slave mode #1 SP_CYCLE Suspend Interval (Master only) 12 4 read-write TX_BIT_LEN Transmit Bit Length\nThis field specifies how many bits are transmitted in one transaction. Up to 32 bits can be transmitted. 3 5 read-write TX_NEG Transmit At Negative Edge 2 1 read-write 0 The transmitted data output signal is changed at the rising edge of SPICLK #0 1 The transmitted data output signal is changed at the falling edge of SPICLK #1 TX_NUM Numbers of Transmit/Receive Word\nThis field specifies how many transmit/receive word numbers should be executed in one transfer.\nNote: In slave mode with level-trigger configuration, if TX_NUM is set to 01, the slave select pin must be kept at active state during the successive data transfer. 8 2 read-write 0 Only one transmit/receive word will be executed in one transfer #00 1 Two successive transmit/receive words will be executed in one transfer. (burst mode) #01 2 Reserved #10 3 Reserved #11 VARCLK_EN Variable Clock Enable (Master only)\nNote that when enable this VARCLK_EN bit, the setting of TX_BIT_LEN must be programmed as 0x10 (16 bits mode) 23 1 read-write 0 The serial clock output frequency is fixed and decided only by the value of DIVIDER #0 1 The serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2 #1 SPI_DIVIDER SPI_DIVIDER Clock Divider Register (Master only) 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider Register (Master only)\nThe value in this field is the frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIn slave mode, the period of SPI clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK. 0 16 read-write DIVIDER2 Clock Divider 2 Register (Master only)\nThe value in this field is the 2nd frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIf VARCLK_EN is cleared to 0, this setting is unmeaning. 16 16 read-write SPI_RX0 SPI_RX0 Data Receive Register 0 0x10 read-only n 0x0 0x0 RX Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. The values of the other bits are unknown.\nNote: The Data Receive Registers are read only registers. 0 32 read-only SPI_RX1 SPI_RX1 Data Receive Register 1 0x14 read-write n 0x0 0x0 SPI_SSR SPI_SSR Slave Select Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Select (Master only) 3 1 read-write 0 If this bit is cleared, slave select signals will be asserted and de-asserted by setting and clearing related bits in SSR[1:0] #0 1 If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SSR[1:0], will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished #1 LTRIG_FLAG Level Trigger Flag\nWhen the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only 5 1 read-write 0 The transaction number or the transferred bit length of one transaction doesn't meet the specified requirements #0 1 The transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN #1 SSR Slave Select Register (Master only) If AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state. If AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state writing 1 to any bit location of this field will select the corresponding SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL. Note: SPISSx0 is also defined as slave select input in slave mode. 0 2 read-write SS_LTRIG Slave Select Level Trigger (Slave only) 4 1 read-write 0 The input slave select signal is edge-trigger. This is the default value. It depends on SS_LVL to decide the signal is active at falling-edge or rising-edge #0 1 The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high #1 SS_LVL Slave Select Active Level\nIt defines the active state of slave select signal (SPISSx0/1). 2 1 read-write 0 The slave select signal SPISSx0/1 is active at low-level/falling-edge #0 1 The slave select signal SPISSx0/1 is active at high-level/rising-edge #1 SPI_TX0 SPI_TX0 Data Transmit Register 0 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the SPI controller will perform two 32-bit transmit/receive successive using the same setting. The transmission sequence is TX0[31:0] first and then TX1[31:0]. 0 32 write-only SPI_TX1 SPI_TX1 Data Transmit Register 1 0x24 read-write n 0x0 0x0 SPI_VARCLK SPI_VARCLK Variable Clock Pattern Register (Master only) 0x34 -1 read-write n 0x0 0x0 VARCLK Variable Clock Pattern (Master only)\nThe value in this field is the frequency patterns of the SPI clock. If the bit pattern of VARCLK is '0', the output frequency of SPICLK is according the value of DIVIDER. If the bit patterns of VARCLK are '1', the output frequency of SPICLK is according the value of DIVIDER2. Refer to register SPI_DIVIDER.\nRefer to Variable Clock paragraph for more detailed Description. 0 32 read-write TMR01 TMR Register Map TMR 0x0 0x0 0x10 registers n 0x20 0x10 registers n TCMPR0 TCMPR0 Timer0 Compare Register 0x4 read-write n 0x0 0x0 TCMP Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF (TISR[0] timet interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if software writes a new value into TCMP field. 0 24 read-write TCMPR1 TCMPR1 Timer1 Compare Register 0x24 read-write n 0x0 0x0 TCSR0 TCSR0 Timer0 Control and Status Register 0x0 -1 read-write n 0x0 0x0 CACT Timer Active Status Bit (Read only)\nThis bit indicates the 24-bit up counter status. 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CEN Timer Enable Bit 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 CRST Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TDR) and also force CEN (TCSR[30] timer enable bit) to 0 if CACT (TCSR[25] timer active status bit) is 1. 26 1 read-write 0 No effect #0 1 Reset 8-bit pre-scale counter, 24-bit up counter value and CEN bit #1 CTB Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to 5.10.4.5 for detail description. 24 1 read-write 0 External counter mode Disabled #0 1 External counter mode Enabled #1 DBGACK_TMR ICE Debug Mode Acknowledge Disable (write-protection bit)\nTIMER counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement disabled #1 IE Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal (TIF) when the associated up-timer value is equal to TCMPR. 29 1 read-write 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 MODE Timer Operating Mode 27 2 read-write PRESCALE Pre-scale Counter 0 8 read-write TDR_EN Data Load Enable\nWhen this bit is set, timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting. 16 1 read-write 0 Timer Data Register update Disabled #0 1 Timer Data Register update Enabled while timer counter is active #1 TCSR1 TCSR1 Timer1 Control and Status Register 0x20 read-write n 0x0 0x0 TDR0 TDR0 Timer0 Data Register 0xC read-only n 0x0 0x0 TDR Timer Data Register\nWhen TCSR.TDR_EN is set to 1, the internal 24-bit up-timer value will be loaded into TDR. User can read this register for the up-timer value. 0 24 read-only TDR1 TDR1 Timer1 Data Register 0x2C read-write n 0x0 0x0 TISR0 TISR0 Timer0 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer.\nAnd this bit is set by hardware when the timer counter value) matches the timer compared value (TCMP value). It is cleared by writing 1 to it through software. 0 1 read-write TISR1 TISR1 Timer1 Interrupt Status Register 0x28 read-write n 0x0 0x0 TMR23 TMR Register Map TMR 0x0 0x0 0x10 registers n 0x20 0x10 registers n TCMPR2 TCMPR2 Timer2 Compare Register 0x4 read-write n 0x0 0x0 TCMP Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF (TISR[0] timet interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if software writes a new value into TCMP field. 0 24 read-write TCMPR3 TCMPR3 Timer3 Compare Register 0x24 read-write n 0x0 0x0 TCSR2 TCSR2 Timer2 Control and Status Register 0x0 -1 read-write n 0x0 0x0 CACT Timer Active Status Bit (Read only)\nThis bit indicates the 24-bit up counter status. 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CEN Timer Enable Bit 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 CRST Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TDR) and also force CEN (TCSR[30] timer enable bit) to 0 if CACT (TCSR[25] timer active status bit) is 1. 26 1 read-write 0 No effect #0 1 Reset 8-bit pre-scale counter, 24-bit up counter value and CEN bit #1 CTB Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to 5.10.4.5 for detail description. 24 1 read-write 0 External counter mode Disabled #0 1 External counter mode Enabled #1 DBGACK_TMR ICE Debug Mode Acknowledge Disable (write-protection bit)\nTIMER counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement disabled #1 IE Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal (TIF) when the associated up-timer value is equal to TCMPR. 29 1 read-write 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 MODE Timer Operating Mode 27 2 read-write PRESCALE Pre-scale Counter 0 8 read-write TDR_EN Data Load Enable\nWhen this bit is set, timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting. 16 1 read-write 0 Timer Data Register update Disabled #0 1 Timer Data Register update Enabled while timer counter is active #1 TCSR3 TCSR3 Timer3 Control and Status Register 0x20 read-write n 0x0 0x0 TDR2 TDR2 Timer2 Data Register 0xC read-only n 0x0 0x0 TDR Timer Data Register\nWhen TCSR.TDR_EN is set to 1, the internal 24-bit up-timer value will be loaded into TDR. User can read this register for the up-timer value. 0 24 read-only TDR3 TDR3 Timer3 Data Register 0x2C read-write n 0x0 0x0 TISR2 TISR2 Timer2 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer.\nAnd this bit is set by hardware when the timer counter value) matches the timer compared value (TCMP value). It is cleared by writing 1 to it through software. 0 1 read-write TISR3 TISR3 Timer3 Interrupt Status Register 0x28 read-write n 0x0 0x0 UART0 UART Register Map UART 0x0 0x0 0x30 registers n UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ADDR_MATCH Address Match Value Register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write RS_485_AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode. 9 1 read-write 0 Disable RS-485 Auto Address Detection Operation Mode (AAD) #0 1 Enable RS-485 Auto Address Detection Operation Mode (AAD) #1 RS_485_ADD_EN RS-485 Address Detection Enable\nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode. 15 1 read-write 0 Disable address detection mode #0 1 Enable address detection mode #1 RS_485_AUD RS-485 Auto Direction Mode (AUD)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 Disable RS-485 Auto Direction Operation Mode (AUO) #0 1 Enable RS-485 Auto Direction Operation Mode (AUO) #1 RS_485_NMM RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It can't be active with RS-485_AAD operation mode. 8 1 read-write 0 Disable RS-485 Normal Multi-drop Operation Mode (NMM) #0 1 Enable RS-485 Normal Multi-drop Operation Mode (NMM) #1 UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 -1 read-write n 0x0 0x0 BRD Baud Rate Divider\nThe field indicated the baud rate divider 0 16 read-write DIVIDER_X Divider X 24 4 read-write DIV_X_EN Divider X Enable\nRefer to the table below for more information.\nNote: When in IrDA mode, this bit must disable. 29 1 read-write 0 Disable divider X (the equation of M = 16) #0 1 Enable divider X (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 DIV_X_ONE Divider X Equal 1\nRefer to the table below for more information. 28 1 read-write 0 Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3) #1 UA_FCR UA_FCR UART FIFO Control Register 0x8 read-write n 0x0 0x0 RFITL RX FIFO Interrupt (INT_RDA) Trigger Level 4 4 read-write RFR RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles. 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the RX internal state machine and pointers #1 RTS_TRI_LEV RTS Trigger Level for Auto-flow Control 16 4 read-write RX_DIS Receiver Disable \nThe receiver is disabled or not (set 1 is disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed. 8 1 read-write 0 Enable Receiver #0 1 Disable Receiver #1 TFR TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles. 2 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the TX internal state machine and pointers #1 UA_FSR UA_FSR UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 BIF Break Interrupt Flag (Read only) This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit. Note: This bit is read only, but can be cleared by writing '1' to it. 6 1 read-only FEF Framing Error Flag (Read only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit. Note: This bit is read only, but can be cleared by writing '1' to it. 5 1 read-only PEF Parity Error Flag (Read only) This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit. Note: This bit is read only, but can be cleared by writing '1' to it. 4 1 read-only RS_485_ADD_DETF RS-485 Address Byte Detection Flag (Read only)\nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only RX_EMPTY Receiver FIFO Empty (Read only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only RX_FULL Receiver FIFO Full (Read only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RX_POINTER is more than 15, otherwise is cleared by hardware. 15 1 read-only RX_OVER_IF RX Overflow Error IF (Read only)\nThis bit is set when RX FIFO overflow.\nNote: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only RX_POINTER RX FIFO Pointer (Read only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one. 8 6 read-only TE_FLAG Transmitter Empty Flag (Read only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only TX_EMPTY Transmitter FIFO Empty (Read only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). 22 1 read-only TX_FULL Transmitter FIFO Full (Read only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is more than 15, otherwise is cleared by hardware. 23 1 read-only TX_OVER_IF TX Overflow Error Interrupt Flag (Read only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it. 24 1 read-only TX_POINTER TX FIFO Pointer (Read only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one. 16 6 read-only UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUN_SEL Function Select Enable 0 2 read-write 0 UART Function #00 1 Reserved #01 2 Enable IrDA Function #10 3 Enable RS-485 Function #11 UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 AUTO_CTS_EN CTS Auto Flow Control Enable\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 read-write 0 Disable CTS auto flow control #0 1 Enable CTS auto flow control #1 AUTO_RTS_EN RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal. 12 1 read-write 0 Disable RTS auto flow control #0 1 Enable RTS auto flow control #1 BUF_ERR_IEN Buffer Error Interrupt Enable 5 1 read-write 0 Mask off INT_BUF_ERR #0 1 Enable INT_BUF_ERR #1 MODEM_IEN Modem Status Interrupt Enable 3 1 read-write 0 Mask off INT_MODEM #0 1 Enable INT_MODEM #1 RDA_IEN Receive Data Available Interrupt Enable. 0 1 read-write 0 Mask off INT_RDA #0 1 Enable INT_RDA #1 RLS_IEN Receive Line Status Interrupt Enable 2 1 read-write 0 Mask off INT_RLS #0 1 Enable INT_RLS #1 RTO_IEN RX Time-Out Interrupt Enable 4 1 read-write 0 Mask off INT_TOUT #0 1 Enable INT_TOUT #1 THRE_IEN Transmit Holding Register Empty Interrupt Enable 1 1 read-write 0 Mask off INT_THRE #0 1 Enable INT_THRE #1 TIME_OUT_EN Time-Out Counter Enable 11 1 read-write 0 Disable Time-out counter #0 1 Enable Time-out counter #1 WAKE_EN UART Wake-Up Function Enable 6 1 read-write 0 Disable UART wake-up function #0 1 Enable UART wake-up function, when the chip is in power down mode, an external /CTS change will wake-up chip from power down mode #1 UA_IRCR UA_IRCR UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 INV_RX INV_RX 6 1 read-write 0 No inversion #0 1 Inverse RX input signal #1 INV_TX INV_TX 5 1 read-write 0 No inversion #0 1 Inverse TX output signal #1 TX_SELECT TX_SELECT 1 1 read-write 0 Enable IrDA receiver #0 1 Enable IrDA transmitter #1 UA_ISR UA_ISR UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 BUF_ERR_IF Buffer Error Interrupt Flag (Read only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. 5 1 read-only BUF_ERR_INT Buffer Error Interrupt Indicator (Read only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 The buffer error interrupt is generated #1 MODEM_IF MODEM Interrupt Flag (Read only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. 3 1 read-only MODEM_INT MODEM Status Interrupt Indicator (Read only).\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1. 11 1 read-only 0 No Modem interrupt is generated #0 1 The Modem interrupt is generated #1 RDA_IF Receive Data Available Interrupt Flag (Read only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL). 0 1 read-only RDA_INT Receive Data Available Interrupt Indicator (Read only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 The RDA interrupt is generated #1 RLS_IF Receive Line Interrupt Flag (Read only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. 2 1 read-only RLS_INT Receive Line Status Interrupt Indicator (Read only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 The RLS interrupt is generated #1 THRE_IF Transmit Holding Register Empty Interrupt Flag (Read only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only THRE_INT Transmit Holding Register Empty Interrupt Indicator (Read only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 The THRE interrupt is generated #1 TOUT_IF Time-Out Interrupt Flag (Read only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 4 1 read-only TOUT_INT Time-Out Interrupt Indicator (Read only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1. 12 1 read-only 0 No Tout interrupt is generated #0 1 The Tout interrupt is generated #1 UA_LCR UA_LCR UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write EPE Even Parity Enable\nThis bit has effect only when PEB(UA_LCR[3]) (parity bit enable) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of STOP bit 2 1 read-write 0 1 STOP bit is generated in the transmitted data #0 1 2 STOP bit is generated in the transmitted data 1.5 STOP bit is generated when UA_LCR[1:0]=00 #1 PBE Parity Bit Enable 3 1 read-write 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 SPE Stick Parity Enable 5 1 read-write 0 Stick parity disabled #0 1 If PEB(UA_LCR[3]) and EBE(UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PEB(UA_LCR[3]) is 1 and EBE(UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1 #1 WLS Word Length Select 0 2 read-write UA_MCR UA_MCR UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 LEV_RTS RTS Trigger Level\nThis bit can change the RTS trigger level. 9 1 read-write 0 low level triggered #0 1 high level triggered #1 RTS RTS (Request-To-Send) Signal 1 1 read-write 0 Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered) #0 1 Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered) #1 RTS_ST RTS Pin State (Read only)\nThis bit is the output pin status of RTS. 13 1 read-only UA_MSR UA_MSR UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTS_ST CTS Pin Status (Read only)\nThis bit is the pin status of CTS. 4 1 read-only DCTSF Detect CTS State Change Flag (Read only)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nSoftware can write 1 to clear this bit to 0 0 1 read-only LEV_CTS CTS polarity setting\nThis bit can select the polarity of CTS active level to send TX_FIFO data.\nAccording to CTS pin and LEV_CTS setting, the four cases are described as following:\nWhen the CTS pin input is high, the CTS function is not active if the LEV_CTS is set to 1. 8 1 read-write UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register (Read only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first). 0 8 read-only UA_THR UA_THR UART Transmit Holding Register UA_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first). 0 8 write-only UA_TOR UA_TOR UART Time-Out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value\nThis field is use to programming the transfer delay time between the last stop bit and the next start bit. 8 8 read-write TOIC Time-Out Interrupt Comparator 0 8 read-write UART1 UART Register Map UART 0x0 0x0 0x30 registers n UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ADDR_MATCH Address Match Value Register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write RS_485_AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode. 9 1 read-write 0 Disable RS-485 Auto Address Detection Operation Mode (AAD) #0 1 Enable RS-485 Auto Address Detection Operation Mode (AAD) #1 RS_485_ADD_EN RS-485 Address Detection Enable\nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode. 15 1 read-write 0 Disable address detection mode #0 1 Enable address detection mode #1 RS_485_AUD RS-485 Auto Direction Mode (AUD)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 Disable RS-485 Auto Direction Operation Mode (AUO) #0 1 Enable RS-485 Auto Direction Operation Mode (AUO) #1 RS_485_NMM RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It can't be active with RS-485_AAD operation mode. 8 1 read-write 0 Disable RS-485 Normal Multi-drop Operation Mode (NMM) #0 1 Enable RS-485 Normal Multi-drop Operation Mode (NMM) #1 UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 -1 read-write n 0x0 0x0 BRD Baud Rate Divider\nThe field indicated the baud rate divider 0 16 read-write DIVIDER_X Divider X 24 4 read-write DIV_X_EN Divider X Enable\nRefer to the table below for more information.\nNote: When in IrDA mode, this bit must disable. 29 1 read-write 0 Disable divider X (the equation of M = 16) #0 1 Enable divider X (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 DIV_X_ONE Divider X Equal 1\nRefer to the table below for more information. 28 1 read-write 0 Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3) #1 UA_FCR UA_FCR UART FIFO Control Register 0x8 read-write n 0x0 0x0 RFITL RX FIFO Interrupt (INT_RDA) Trigger Level 4 4 read-write RFR RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles. 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the RX internal state machine and pointers #1 RTS_TRI_LEV RTS Trigger Level for Auto-flow Control 16 4 read-write RX_DIS Receiver Disable \nThe receiver is disabled or not (set 1 is disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed. 8 1 read-write 0 Enable Receiver #0 1 Disable Receiver #1 TFR TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles. 2 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the TX internal state machine and pointers #1 UA_FSR UA_FSR UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 BIF Break Interrupt Flag (Read only) This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit. Note: This bit is read only, but can be cleared by writing '1' to it. 6 1 read-only FEF Framing Error Flag (Read only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit. Note: This bit is read only, but can be cleared by writing '1' to it. 5 1 read-only PEF Parity Error Flag (Read only) This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit. Note: This bit is read only, but can be cleared by writing '1' to it. 4 1 read-only RS_485_ADD_DETF RS-485 Address Byte Detection Flag (Read only)\nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only RX_EMPTY Receiver FIFO Empty (Read only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only RX_FULL Receiver FIFO Full (Read only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RX_POINTER is more than 15, otherwise is cleared by hardware. 15 1 read-only RX_OVER_IF RX Overflow Error IF (Read only)\nThis bit is set when RX FIFO overflow.\nNote: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only RX_POINTER RX FIFO Pointer (Read only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one. 8 6 read-only TE_FLAG Transmitter Empty Flag (Read only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only TX_EMPTY Transmitter FIFO Empty (Read only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). 22 1 read-only TX_FULL Transmitter FIFO Full (Read only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is more than 15, otherwise is cleared by hardware. 23 1 read-only TX_OVER_IF TX Overflow Error Interrupt Flag (Read only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it. 24 1 read-only TX_POINTER TX FIFO Pointer (Read only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one. 16 6 read-only UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUN_SEL Function Select Enable 0 2 read-write 0 UART Function #00 1 Reserved #01 2 Enable IrDA Function #10 3 Enable RS-485 Function #11 UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 AUTO_CTS_EN CTS Auto Flow Control Enable\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 read-write 0 Disable CTS auto flow control #0 1 Enable CTS auto flow control #1 AUTO_RTS_EN RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal. 12 1 read-write 0 Disable RTS auto flow control #0 1 Enable RTS auto flow control #1 BUF_ERR_IEN Buffer Error Interrupt Enable 5 1 read-write 0 Mask off INT_BUF_ERR #0 1 Enable INT_BUF_ERR #1 MODEM_IEN Modem Status Interrupt Enable 3 1 read-write 0 Mask off INT_MODEM #0 1 Enable INT_MODEM #1 RDA_IEN Receive Data Available Interrupt Enable. 0 1 read-write 0 Mask off INT_RDA #0 1 Enable INT_RDA #1 RLS_IEN Receive Line Status Interrupt Enable 2 1 read-write 0 Mask off INT_RLS #0 1 Enable INT_RLS #1 RTO_IEN RX Time-Out Interrupt Enable 4 1 read-write 0 Mask off INT_TOUT #0 1 Enable INT_TOUT #1 THRE_IEN Transmit Holding Register Empty Interrupt Enable 1 1 read-write 0 Mask off INT_THRE #0 1 Enable INT_THRE #1 TIME_OUT_EN Time-Out Counter Enable 11 1 read-write 0 Disable Time-out counter #0 1 Enable Time-out counter #1 WAKE_EN UART Wake-Up Function Enable 6 1 read-write 0 Disable UART wake-up function #0 1 Enable UART wake-up function, when the chip is in power down mode, an external /CTS change will wake-up chip from power down mode #1 UA_IRCR UA_IRCR UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 INV_RX INV_RX 6 1 read-write 0 No inversion #0 1 Inverse RX input signal #1 INV_TX INV_TX 5 1 read-write 0 No inversion #0 1 Inverse TX output signal #1 TX_SELECT TX_SELECT 1 1 read-write 0 Enable IrDA receiver #0 1 Enable IrDA transmitter #1 UA_ISR UA_ISR UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 BUF_ERR_IF Buffer Error Interrupt Flag (Read only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. 5 1 read-only BUF_ERR_INT Buffer Error Interrupt Indicator (Read only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 The buffer error interrupt is generated #1 MODEM_IF MODEM Interrupt Flag (Read only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. 3 1 read-only MODEM_INT MODEM Status Interrupt Indicator (Read only).\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1. 11 1 read-only 0 No Modem interrupt is generated #0 1 The Modem interrupt is generated #1 RDA_IF Receive Data Available Interrupt Flag (Read only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL). 0 1 read-only RDA_INT Receive Data Available Interrupt Indicator (Read only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 The RDA interrupt is generated #1 RLS_IF Receive Line Interrupt Flag (Read only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. 2 1 read-only RLS_INT Receive Line Status Interrupt Indicator (Read only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 The RLS interrupt is generated #1 THRE_IF Transmit Holding Register Empty Interrupt Flag (Read only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only THRE_INT Transmit Holding Register Empty Interrupt Indicator (Read only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 The THRE interrupt is generated #1 TOUT_IF Time-Out Interrupt Flag (Read only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 4 1 read-only TOUT_INT Time-Out Interrupt Indicator (Read only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1. 12 1 read-only 0 No Tout interrupt is generated #0 1 The Tout interrupt is generated #1 UA_LCR UA_LCR UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write EPE Even Parity Enable\nThis bit has effect only when PEB(UA_LCR[3]) (parity bit enable) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of STOP bit 2 1 read-write 0 1 STOP bit is generated in the transmitted data #0 1 2 STOP bit is generated in the transmitted data 1.5 STOP bit is generated when UA_LCR[1:0]=00 #1 PBE Parity Bit Enable 3 1 read-write 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 SPE Stick Parity Enable 5 1 read-write 0 Stick parity disabled #0 1 If PEB(UA_LCR[3]) and EBE(UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PEB(UA_LCR[3]) is 1 and EBE(UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1 #1 WLS Word Length Select 0 2 read-write UA_MCR UA_MCR UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 LEV_RTS RTS Trigger Level\nThis bit can change the RTS trigger level. 9 1 read-write 0 low level triggered #0 1 high level triggered #1 RTS RTS (Request-To-Send) Signal 1 1 read-write 0 Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered) #0 1 Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered) #1 RTS_ST RTS Pin State (Read only)\nThis bit is the output pin status of RTS. 13 1 read-only UA_MSR UA_MSR UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTS_ST CTS Pin Status (Read only)\nThis bit is the pin status of CTS. 4 1 read-only DCTSF Detect CTS State Change Flag (Read only)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nSoftware can write 1 to clear this bit to 0 0 1 read-only LEV_CTS CTS polarity setting\nThis bit can select the polarity of CTS active level to send TX_FIFO data.\nAccording to CTS pin and LEV_CTS setting, the four cases are described as following:\nWhen the CTS pin input is high, the CTS function is not active if the LEV_CTS is set to 1. 8 1 read-write UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register (Read only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first). 0 8 read-only UA_THR UA_THR UART Transmit Holding Register UA_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first). 0 8 write-only UA_TOR UA_TOR UART Time-Out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value\nThis field is use to programming the transfer delay time between the last stop bit and the next start bit. 8 8 read-write TOIC Time-Out Interrupt Comparator 0 8 read-write USB USB Register Map USB 0x0 0x0 0x1C registers n 0x20 0x60 registers n 0x90 0x4 registers n ATTR USB_ATTR USB Bus Status and Attribution Register 0x10 -1 read-write n 0x0 0x0 BYTEM CPU access USB SRAM Size Mode Selection 10 1 read-write 0 Word Mode: The size of the transfer from CPU to USB SRAM can be Word only #0 1 Byte Mode: The size of the transfer from CPU to USB SRAM can be Byte only #1 DPPU_EN Pull-up Resistor on USB_DP Enable 8 1 read-write 0 Disable the pull-up resistor in USB_DP bus #0 1 The pull-up resistor in USB_DP bus active #1 PHY_EN PHY Transceiver Function Enable 4 1 read-write 0 Disable PHY transceiver function #0 1 Enable PHY transceiver function #1 PWRDN Power Down PHY Transceiver (low active) 9 1 read-write 0 power down related circuit of PHY transceiver #0 1 Turn-on related circuit of PHY transceiver #1 RESUME Resume Status\nIt is a read only bit. 2 1 read-write 0 No bus resume #0 1 Resume from suspend #1 RWAKEUP Remote Wake-Up 5 1 read-write 0 Release the USB bus from K state #0 1 Force USB bus to K (USB_DP low, USB_DM: high) state, used for remote wake-up #1 SUSPEND Suspend Status\nIt is a read only bit. 1 1 read-write 0 Bus no suspend #0 1 Bus idle more than 3 ms, either cable is plugged off or host is sleeping #1 TIMEOUT Time-Out Status\nIt is a read only bit. 3 1 read-write 0 No time-out #0 1 Bus no any response more than 18 bits time #1 USBRST USB Reset Status\nIt is a read only bit. 0 1 read-write 0 Bus no reset #0 1 Bus reset when SE0 (single-ended 0) more than 2.5us #1 USB_EN USB Controller Enable 7 1 read-write 0 Disable USB Controller #0 1 Enable USB Controller #1 BUFSEG USB_BUFSEG Setup Token Buffer Segmentation Register 0x18 read-write n 0x0 0x0 BUFSEG It is used to indicate the offset address for the Setup token with the USB SRAM starting address. The effective starting address is\nUSB_SRAM address + { BUFSEG[8:3], 3'b000} \nNote: It is used for Setup token only. 3 6 read-write BUFSEG0 USB_BUFSEG0 Endpoint 0 Buffer Segmentation Register 0x20 read-write n 0x0 0x0 BUFSEGx It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is\nUSB_SRAM address + {BUFSEG[8:3], 3'b000}\nRefer to section 5.4.4.7 for the endpoint SRAM structure and its description. 3 6 read-write BUFSEG1 USB_BUFSEG1 Endpoint 1 Buffer Segmentation Register 0x30 read-write n 0x0 0x0 BUFSEG2 USB_BUFSEG2 Endpoint 2 Buffer Segmentation Register 0x40 read-write n 0x0 0x0 BUFSEG3 USB_BUFSEG3 Endpoint 3 Buffer Segmentation Register 0x50 read-write n 0x0 0x0 BUFSEG4 USB_BUFSEG4 Endpoint 4 Buffer Segmentation Register 0x60 read-write n 0x0 0x0 BUFSEG5 USB_BUFSEG5 Endpoint 5 Buffer Segmentation Register 0x70 read-write n 0x0 0x0 CFG0 USB_CFG0 Endpoint 0 Configuration Register 0x28 read-write n 0x0 0x0 CSTALL Clear STALL Response 9 1 read-write 0 Disable the device to clear the STALL handshake in setup stage #0 1 Clear the device to response STALL handshake in setup stage #1 DSQ_SYNC Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the following IN token transaction. H/W will toggle automatically in IN token base on the bit. 7 1 read-write 0 DATA0 PID #0 1 DATA1 PID #1 EP_NUM Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint 0 4 read-write ISOCH Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake. 4 1 read-write 0 No Isochronous endpoint #0 1 Isochronous endpoint #1 STATE Endpoint STATE 5 2 read-write 0 Endpoint is disabled #00 1 Out endpoint #01 2 IN endpoint #10 3 Undefined #11 CFG1 USB_CFG1 Endpoint 1 Configuration Register 0x38 read-write n 0x0 0x0 CFG2 USB_CFG2 Endpoint 2 Configuration Register 0x48 read-write n 0x0 0x0 CFG3 USB_CFG3 Endpoint 3 Configuration Register 0x58 read-write n 0x0 0x0 CFG4 USB_CFG4 Endpoint 4 Configuration Register 0x68 read-write n 0x0 0x0 CFG5 USB_CFG5 Endpoint 5 Configuration Register 0x78 read-write n 0x0 0x0 CFGP0 USB_CFGP0 Endpoint 0 Set Stall and Clear In/Out Ready Control Register 0x2C read-write n 0x0 0x0 CLRRDY Clear Ready\nWhen the MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it is auto clear to 0.\nFor IN token, write '1' is used to clear the IN token had ready to transmit the data to USB.\nFor OUT token, write '1' is used to clear the OUT token had ready to receive the data from USB.\nThis bit is write 1 only and it is always 0 when it was read back. 0 1 read-write SSTALL Set STALL 1 1 read-write 0 Disable the device to response STALL #0 1 Set the device to respond STALL automatically #1 CFGP1 USB_CFGP1 Endpoint 1 Set Stall and Clear In/Out Ready Control Register 0x3C read-write n 0x0 0x0 CFGP2 USB_CFGP2 Endpoint 2 Set Stall and Clear In/Out Ready Control Register 0x4C read-write n 0x0 0x0 CFGP3 USB_CFGP3 Endpoint 3 Set Stall and Clear In/Out Ready Control Register 0x5C read-write n 0x0 0x0 CFGP4 USB_CFGP4 Endpoint 4 Set Stall and Clear In/Out Ready Control Register 0x6C read-write n 0x0 0x0 CFGP5 USB_CFGP5 Endpoint 5 Set Stall and Clear In/Out Ready Control Register 0x7C read-write n 0x0 0x0 DRVSE0 USB_DRVSE0 USB Drive SE0 Control Register 0x90 -1 read-write n 0x0 0x0 DRVSE0 Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_DP and USB_DM) are being pulled low. 0 1 read-write 0 None #0 1 Force USB PHY transceiver to drive SE0 #1 EPSTS USB_EPSTS USB Endpoint Status Register 0xC read-only n 0x0 0x0 EPSTS0 Endpoint 0 Bus Status\nThese bits are used to indicate the current status of this endpoint 8 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS1 Endpoint 1 Bus Status\nThese bits are used to indicate the current status of this endpoint 11 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS2 Endpoint 2 Bus Status\nThese bits are used to indicate the current status of this endpoint 14 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS3 Endpoint 3 Bus Status\nThese bits are used to indicate the current status of this endpoint 17 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS4 Endpoint 4 Bus Status\nThese bits are used to indicate the current status of this endpoint 20 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS5 Endpoint 5 Bus Status\nThese bits are used to indicate the current status of this endpoint 23 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 OVERRUN Overrun\nIt indicates that the received data is over the maximum payload number or not. 7 1 read-only 0 No overrun #0 1 It indicates that the Out Data more than the Max Payload in MXPLD register or the Setup Data more than 8 Bytes #1 FADDR USB_FADDR USB Device Function Address Register 0x8 read-write n 0x0 0x0 FADDR USB device's Function Address 0 7 read-write FLDET USB_FLDET USB Floating Detected Register 0x14 read-only n 0x0 0x0 FLDET Device Floating Detected 0 1 read-only 0 The controller didn't attached into the USB host #0 1 When the controller is attached into the BUS, this bit will be set as 1 #1 INTEN USB_INTEN USB Interrupt Enable Register 0x0 read-write n 0x0 0x0 BUS_IE Bus Event Interrupt Enable 0 1 read-write 0 Disable BUS event interrupt #0 1 Enable BUS event interrupt #1 FLDET_IE Floating Detected Interrupt Enable 2 1 read-write 0 Disable Floating detect Interrupt #0 1 Enable Floating detect Interrupt #1 INNAK_EN Active NAK Function and its Status in IN Token 15 1 read-write 0 The NAK status doesn't be updated into the endpoint status register when it was set to 0. It also disable the interrupt event when device responds NAK after receiving IN token #0 1 The NAK status is updated into the endpoint status register, USB_EPSTS, when it is set to 1 and there is NAK response in IN token. It also enable the interrupt event when the device responds NAK after receiving IN token #1 USB_IE USB Event Interrupt Enable 1 1 read-write 0 Disable USB event interrupt #0 1 Enable USB event interrupt #1 WAKEUP_EN Wake-Up Function Enable 8 1 read-write 0 Disable USB wake-up function #0 1 Enable USB wake-up function #1 WAKEUP_IE USB Wake-Up Interrupt Enable 3 1 read-write 0 Disable USB wake-up Interrupt #0 1 Enable USB wake-up Interrupt #1 INTSTS USB_INTSTS USB Interrupt Event Status Register 0x4 read-write n 0x0 0x0 BUS_STS BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus. 0 1 read-write 0 No any BUS event is occurred #0 1 Bus event occurred check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS[0] #1 EPEVT0 Endpoint 0's USB Event Status 16 1 read-write 0 No event occurred in endpoint 0 #0 1 USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[16] or USB_INTSTS[1] #1 EPEVT1 Endpoint 1's USB Event Status 17 1 read-write 0 No event occurred in endpoint 1 #0 1 USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[17] or USB_INTSTS[1] #1 EPEVT2 Endpoint 2's USB Event Status 18 1 read-write 0 No event occurred in endpoint 2 #0 1 USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1] #1 EPEVT3 Endpoint 3's USB Event Status 19 1 read-write 0 No event occurred in endpoint 3 #0 1 USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[19] or USB_INTSTS[1] #1 EPEVT4 Endpoint 4's USB Event Status 20 1 read-write 0 No event occurred in endpoint 4 #0 1 USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[20] or USB_INTSTS[1] #1 EPEVT5 Endpoint 5's USB Event Status 21 1 read-write 0 No event occurred in endpoint 5 #0 1 USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[21] or USB_INTSTS[1] #1 FLDET_STS Floating Detected Interrupt Status 2 1 read-write 0 There is not attached/detached event in the USB #0 1 There is attached/detached event in the USB bus and it is cleared by write 1 to USB_INTSTS[2] #1 SETUP Setup Event Status 31 1 read-write 0 No Setup event #0 1 Setup event occurred, cleared by write 1 to USB_INTSTS[31] #1 USB_STS USB Event Interrupt Status\nThe USB event includes the Setup Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. 1 1 read-write 0 No any USB event is occurred #0 1 USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[1] or EPSTS0~5 and SETUP (USB_INTSTS[31]) #1 WAKEUP_STS Wake-Up Interrupt Status 3 1 read-write 0 No wake-up event is occurred #0 1 Wake-up event occurred, cleared by write 1 to USB_INTSTS[3] #1 MXPLD0 USB_MXPLD0 Endpoint 0 Maximal Payload Register 0x24 read-write n 0x0 0x0 MXPLD Maximal Payload It is used to define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. (1). When the register is written by CPU, For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. (2). When the register is read by CPU, For IN token, the value of MXPLD is indicated the data length be transmitted to host For OUT token, the value of MXPLD is indicated the actual data length receiving from host. Note that once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 0 9 read-write MXPLD1 USB_MXPLD1 Endpoint 1 Maximal Payload Register 0x34 read-write n 0x0 0x0 MXPLD2 USB_MXPLD2 Endpoint 2 Maximal Payload Register 0x44 read-write n 0x0 0x0 MXPLD3 USB_MXPLD3 Endpoint 3 Maximal Payload Register 0x54 read-write n 0x0 0x0 MXPLD4 USB_MXPLD4 Endpoint 4 Maximal Payload Register 0x64 read-write n 0x0 0x0 MXPLD5 USB_MXPLD5 Endpoint 5 Maximal Payload Register 0x74 read-write n 0x0 0x0 WDT WDT Register Map WDT 0x0 0x0 0x4 registers n WTCR WTCR Watchdog Timer Control Register 0x0 -1 read-write n 0x0 0x0 DBGACK_WDT ICE Debug Mode Acknowledge Disable (write-protection bit)\nWatchdog Timer counter will keep going no matter CPU is held by ICE or no. 31 1 read-write 0 ICE debug mode acknowledgement effects Watchdog Timer counting #0 1 ICE debug mode acknowledgement disabled #1 WTE Watchdog Timer Enable (write-protection bit) 7 1 read-write 0 Watchdog Timer Disabled (This action will reset the internal counter) #0 1 Watchdog Timer Enabled #1 WTIE Watchdog Timer Interrupt Enable (write-protection bit)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. 6 1 read-write 0 Watchdog Timer interrupt Disabled #0 1 Watchdog Timer interrupt Enabled #1 WTIF Watchdog Timer Interrupt Flag\nThis bit will set to 1 while WDT counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to this bit.. 3 1 read-write 0 Watchdog Timer time-out interrupt did not occur #0 1 Watchdog Timer time-out interrupt occurred #1 WTIS Watchdog Timer Interval Select (write-protection bits) 8 3 read-write WTR Reset Watchdog Timer Counter (write-protection bit) Set this bit will reset the Watchdog Timer. Note: This bit will be automatically cleared by hardware 0 1 read-write 0 No effect #0 1 Reset the internal 18-bit WDT counter #1 WTRE Watchdog Timer Reset Enable (write-protection bit)\nSetting this bit will enable the Watchdog Timer time-out reset function If the WDT counter value has not been cleared after the specific WDT reset delay period expires. 1 1 read-write 0 Watchdog Timer time-out reset function Disabled #0 1 Watchdog Timer time-out reset function Enabled #1 WTRF Watchdog Timer Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to this bit. 2 1 read-write 0 Watchdog Timer time-out reset did not occur #0 1 Watchdog Timer time-out reset occurred #1 WTWKE Watchdog Timer Wake-Up Function Enable bit (write-protection bit)\nIf this bit is set to 1, while WDT interrupt flag (WTCR[3] WTIF) is generated to 1 and WTIE (WTCR[6] WDT interrupt enable) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator. 4 1 read-write 0 Wake-up trigger event Disabled if WDT time-out interrupt signal generated #0 1 Wake-up trigger event Enabled if WDT time-out interrupt signal generated #1 WTWKF Watchdog Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of WDT\nNote: This bit is cleared by writing 1 to this bit. 5 1 read-write 0 Watchdog Timer does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated #1